diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 778989e5b7..5c57be6c71 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -168,6 +168,9 @@ jobs: - {RTT_BSP: "raspberry-pi/raspi3-64", RTT_TOOL_CHAIN: "sourcery-aarch64"} - {RTT_BSP: "raspberry-pi/raspi4-64", RTT_TOOL_CHAIN: "sourcery-aarch64"} - {RTT_BSP: "rockchip/rk3568", RTT_TOOL_CHAIN: "sourcery-aarch64"} + - {RTT_BSP: "microchip/samc21", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "microchip/same54", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "microchip/same70", RTT_TOOL_CHAIN: "sourcery-arm"} steps: - uses: actions/checkout@v3 - name: Set up Python diff --git a/bsp/microchip/README.md b/bsp/microchip/README.md new file mode 100644 index 0000000000..b88d64ad75 --- /dev/null +++ b/bsp/microchip/README.md @@ -0,0 +1,218 @@ +# 1. Microchip BSP Introduction + +Supported Microchip SAM (ARM Cortex-Mx Core) MCU is as following： + +## ARM Cortex-M0+ Series +- samc21 | 5V Cortex-M0+ with 2 CAN-FD support +- saml21 | 3.3V low power Cortex-M0+ +- samd21 | 3.3V industrial level Cortex-M0+ + +## ARM Cortex-M4 Series +- same54 | 3.3V 120MHz Cortex-M4F core with CAN-FD/USB/Ethernet support + +## ARM Cortex-M7 Series +- same70 | 3.3V 300MHz Cortex-M7 core with CAN-FD/High speed USB/Ethernet support + +## Directory description： + * applications: + * user main function entrance, + * driver example - like i2c, can, adc ... + * application example + * board: + * user board initialization + * user driver adpater code, like console device, ethernet device + * bsp: + * MCU BSP files - startup file, peripheral drivers, configuation headers and linker script + * generated from start.atmel.com - DO NOT modify it + +# 2. RT-Thread porting guide of Microchip SAM MCU + +## 2.1 Configure project BSP on Atmel Start + + * Visit and click CREATE NEW PROJECT. + +![](doc/2-1-1-atmel-start-online.png) + + * Input MCU part number and then select device, click CREATE NEW PROJECT. + +![](doc/2-1-2-atmel-start-newproject.png) + + * Add STDIO and other driver/middleware to project. + +![](doc/2-1-3-atmel-start-add-STDIO.png) + + * Configure STDIO driver. + +![](doc/2-1-4-atmel-start-driver-stdio.png) + + * Configure CAN module clock. + +![](doc/2-1-5-atmel-start-can-clock.png) + + * Configure CAN module driver. + +![](doc/2-1-6-atmel-start-driver-can0.png) + +![](doc/2-1-6-atmel-start-driver-can1.png) + + * Add LED pin description. + +![](doc/2-1-8-atmel-start-add-LED0.png) + + * Rename project. + +![](doc/2-1-7-atmel-start-rename-project.png) + + * Save project configuration. + +![](doc/2-1-9-atmel-start-save-configuration.png) + + * Export project source code. + +![](doc/2-1-10-atmel-start-export-project.png) + +## 2.2 Add project to RT-Thread source code + + * Link: and download RT souce code. + +![](doc/2-2-1-atmel-start-download-RT-Thread.png) + + * Unzip downloaded RT-Thread and SAME70 CAN Example + +![](doc/2-2-2-atmel-start-unzip-file.png) + + * Enter rt-thread-xxx/bsp/microchip directory and copy same70 folder and rename it to same70q20. + +![](doc/2-2-3-atmel-start-copy-file.png) + + * Enter same70q20 directory and remove all files except SConscript file. + +![](doc/2-2-4-atmel-start-remove-old-files.png) + + * Copy all files from SAME70 CAN Example to rt-thread-xxx/bsp/microchip/same70q20/bsp. + +![](doc/2-2-5-atmel-start-copy-files.png) + + * Modify rt-thread-xxx\bsp\microchip\same70q20\rtconfig.py. + +![](doc/2-2-6-atmel-start-modify-file0.png) + + * Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\SConscript. + +![](doc/2-2-6-atmel-start-modify-file1.png) + + * Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\same70b\gcc\gcc\same70q20b_flash.ld. + +![](doc/2-2-6-atmel-start-modify-file2.png) + + * Modify rt-thread-xxx\bsp\microchip\same70q20\bsp\same70b\gcc\gcc\startup_same70q20b.c. + +![](doc/2-2-6-atmel-start-modify-file3.png) + + * Alright, now you can use RT-Thread env tools to compile the project. + +## 2.3 Compile project with RT-Thread env tools + +About RT-Thread env tools, click [Here](https://github.com/RT-Thread/rt-thread/blob/master/documentation/env/env.md). + + * Download RT-Thread env tools + +![](doc/2-3-1-atmel-start-download-env-tools.png) + + * Unzip downloaded file and run env.exe. + +![](doc/2-3-2-atmel-start-run-env-tools.png) + + * Enter your project directory and run scons command to compile it. + +![](doc/2-3-3-atmel-start-env-tools-compile.png) + + * Compile error you may have and proposed solution. + +![](doc/2-3-4-atmel-start-env-tools-errors.png) + + * Fix compiling error + +![](doc/2-3-5-atmel-start-env-tools-fixerrors.png) + + * Compiling success + +![](doc/2-3-6-atmel-start-env-tools-compiling-OK.png) + + * In the following chapter I will show you how to debug RT-Thread with Studio 7. + +# 3. RT-Thread debugging with Microchip IDE + + * Link: , download & install Microchip Studio 7. + +![](doc/3-1-1-atmel-start-Studio7-download.png) + + * Open installed Microchip Studio 7 and open object file for debugging. + +![](doc/3-1-2-atmel-start-Studio7-open-objects.png) + + * Choose object file, fill project name and select where to save this project. + +![](doc/3-1-3-atmel-start-Studio7-import-debug.png) + + * Select the right part number and complete object set up. + +![](doc/3-1-4-atmel-start-Studio7-select-device.png) + + * Object file import complete and you can see related files are linked to project. + +![](doc/3-1-5-atmel-start-Studio7-project-complete.png) + + * Right click the project and choose the debug tools in project propertities setting. + +![](doc/3-1-6-atmel-start-Studio7-project-properties.png) + + * Choose debugger/programmer and debugger interface - SWD or JTGA. + +![](doc/3-1-7-atmel-start-Studio7-select-tools.png) + + * Press debugging button and enjoy your debugging journey. + +![](doc/3-1-8-atmel-start-Studio7-start-debugging1.png) + + * Debugging start and you can add breakpoint. + +![](doc/3-1-8-atmel-start-Studio7-start-debugging2.png) + + * Debugging paused at breakpoint and you can monitor local variables at Watch window. + +![](doc/3-1-8-atmel-start-Studio7-start-debugging3.png) + + +# 4. Reconfigure MCU BSP + + * Visit and upload project configuration. + +![](doc/4-1-1-atmel-start-Studio7-reimport-project.png) + + * Now you can reconfigure your project. + +![](doc/4-1-2-atmel-start-Studio7-project-configurtion.png) + + +# 5. Microchip SAM MCU BSP configuration and user guide + + * Please refer to for more details +[ASF4 API Reference Manual](https://ww1.microchip.com/downloads/en/DeviceDoc/50002633B.pdf) + +## 5.1 SAMC2x/E5x/E70 CAN Driver + + * CAN driver configuration. + +![](doc/5-1-1-atmel-start-driver-can0.png) +![](doc/5-1-1-atmel-start-driver-can1.png) + + * CAN driver user guide - see P121 for more details. + + * To be continued. + +# 6. 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diff --git a/bsp/microchip/doc/5-1-1-atmel-start-driver-can0.png b/bsp/microchip/doc/5-1-1-atmel-start-driver-can0.png new file mode 100644 index 0000000000..c071f596d0 Binary files /dev/null and b/bsp/microchip/doc/5-1-1-atmel-start-driver-can0.png differ diff --git a/bsp/microchip/doc/5-1-1-atmel-start-driver-can1.png b/bsp/microchip/doc/5-1-1-atmel-start-driver-can1.png new file mode 100644 index 0000000000..34b29d13f5 Binary files /dev/null and b/bsp/microchip/doc/5-1-1-atmel-start-driver-can1.png differ diff --git a/bsp/microchip/samc21/.config b/bsp/microchip/samc21/.config new file mode 100644 index 0000000000..9d2bd72f81 --- /dev/null +++ b/bsp/microchip/samc21/.config @@ -0,0 +1,648 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=200 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40100 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +# CONFIG_RT_USING_MSH is not set +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SAMC21J18=y +# CONFIG_SOC_SAMC21G18 is not set +# CONFIG_SOC_SAMC21E18 is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_SAMC21_CAN0=y +CONFIG_SAMC21_ADC0=y + +# +# Application Demo Config +# +CONFIG_SAM_CAN_EXAMPLE=y +CONFIG_SAM_ADC_EXAMPLE=y +CONFIG_SOC_SAMC21=y diff --git a/bsp/microchip/samc21/.ignore_format.yml b/bsp/microchip/samc21/.ignore_format.yml new file mode 100644 index 0000000000..988269df37 --- /dev/null +++ b/bsp/microchip/samc21/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- bsp diff --git a/bsp/microchip/samc21/Kconfig b/bsp/microchip/samc21/Kconfig new file mode 100644 index 0000000000..bf9cab1d29 --- /dev/null +++ b/bsp/microchip/samc21/Kconfig @@ -0,0 +1,31 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default: "rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config SOC_SAMC21 + bool + select ARCH_ARM + select ARCH_ARM_CORTEX_M + select ARCH_ARM_CORTEX_M0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/microchip/samc21/README.md b/bsp/microchip/samc21/README.md new file mode 100644 index 0000000000..fe2287ca79 --- /dev/null +++ b/bsp/microchip/samc21/README.md @@ -0,0 +1,70 @@ +# SAMC21J18A BSP Introduction + +[中文](README_zh.md) + +- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V +- C21: Cortex-M0+ + Advanced Feature Set + 2x CAN-FD + Delta-Sigma ADC +- Pin: N=100 pins, J=64 pins, G=48 pins, E=32 pins +- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n) +- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB) +## Datasheet: + +#### KEY FEATURES + +#### Core + - 32-bit Arm® Cortex®-M0+ CPU running at up to 48 MHz or 64 MHz with Single-cycle hardware multiplier + +#### Memories + - 32/64/128/256 KB in-system self-programmable Flash + - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation + - 4/8/16/32 KB SRAM main memory + +#### System + - Power-on Reset (POR) and Brown-out Detection (BOD) + - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M) + - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N) + - 16 external interrupts + - One non-maskable interrupt + - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface + +#### High-Performance Peripherals + - Hardware Divide and Square Root Accelerator (DIVAS) + - 12-channel Direct Memory Access Controller (DMAC) + - 12-channel Event System + - Up to eight 16-bit Timer/Counters (TC), configurable as either + - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions + - Frequency Meter (The division reference clock is only available in the SAM C21N) + - 32-bit Real Time Counter (RTC) with clock/calendar function + - Watchdog Timer (WDT) + - CRC-32 generator + - Up to two Controller Area Network (CAN) interfaces in the SAM C21 + - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI + - One Configurable Custom Logic (CCL) + - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels) + - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21 + - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21 + - Up to four Analog Comparators (AC) with Window Compare function + - Integrated Temperature Sensor in the SAM C21 + - Peripheral Touch Controller (PTC) + - 256-Channel capacitive touch + +#### I/O + - Up to 84 programmable I/O pins + +#### Qualification + - AEC - Q100 Grade 1 (-40°C to 125°C) + +#### Voltage + - 2.7V – 5.5V + - -40°C to +125°C, DC to 48 MHz + - -40°C to +85°C, DC to 64 MHz + +#### Packages + - 100-pin TQFP + - 64-pin TQFP, VQFN + - 56-pin WLCSP + - 48-pin TQFP, VQFN + - 32-pin TQFP, VQFN + +#### Board info +- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO） diff --git a/bsp/microchip/samc21/README_zh.md b/bsp/microchip/samc21/README_zh.md new file mode 100644 index 0000000000..f7388b0af9 --- /dev/null +++ b/bsp/microchip/samc21/README_zh.md @@ -0,0 +1,70 @@ +# SAMC21J18A BSP 介绍 + +[English](README.md) + +- MCU: ATSAMC21J18A @64MHz, 256KB FLASH, 32KB RAM, 2.7V – 5.5V +- C21: Cortex-M0+内核 + 丰富外设 + 2路CAN-FD + Delta-Sigma ADC +- 管脚: N系列-100 pins, J系列-64 pins, G系列-48 pins, E系列-32 pins +- Flash: 18=256KB, 17=128KB, 16=64KB , 15=32KB(size=2^n) +- SRAM : 32KB(Flash 256KB), 16KB(Flash 128KB), 8KB(Flash 64KB), 4KB(Flash 32KB) +## 手册: + +#### KEY FEATURES + +#### 内核 + - 32-bit Arm® Cortex®-M0+ 内核， 主频最高48MHz和64 MHz+单指令周期的硬件乘法器 + +#### 内存 + - 32/64/128/256 KB in-system self-programmable Flash + - 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation + - 4/8/16/32 KB SRAM main memory + +#### 系统特性 + - Power-on Reset (POR) and Brown-out Detection (BOD) + - Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M) + - External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C20/C21 N) + - 16 external interrupts + - One non-maskable interrupt + - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface + +#### 高性能外设 + - Hardware Divide and Square Root Accelerator (DIVAS) + - 12-channel Direct Memory Access Controller (DMAC) + - 12-channel Event System + - Up to eight 16-bit Timer/Counters (TC), configurable as either + - Two 24-bit and one 16-bit Timer/Counter for Control (TCC), with extended functions + - Frequency Meter (The division reference clock is only available in the SAM C21N) + - 32-bit Real Time Counter (RTC) with clock/calendar function + - Watchdog Timer (WDT) + - CRC-32 generator + - Up to two Controller Area Network (CAN) interfaces in the SAM C21 + - Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as USART/I2C/SPI + - One Configurable Custom Logic (CCL) + - Up to Two 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to 12 channels each (20 unique channels) + - One 16-bit Sigma-Delta Analog-to-Digital Converter (SDADC) with up to 3 differential channels in the SAM C21 + - 10-bit, 350 ksps Digital-to-Analog Converter (DAC) in the SAM C21 + - Up to four Analog Comparators (AC) with Window Compare function + - Integrated Temperature Sensor in the SAM C21 + - Peripheral Touch Controller (PTC) + - 256-Channel capacitive touch + +#### I/O管脚 + - 最多提供84个用户可编程I/O管脚 + +#### 汽车应用 + - AEC - Q100 Grade 1 (-40°C to 125°C) + +#### 工作电压 + - 2.7V – 5.5V + - -40°C to +125°C, DC to 48 MHz + - -40°C to +85°C, DC to 64 MHz + +#### 封装 + - 100-pin TQFP + - 64-pin TQFP, VQFN + - 56-pin WLCSP + - 48-pin TQFP, VQFN + - 32-pin TQFP, VQFN + +#### 官方开发板信息 +- [SAM C21 XPLAINED PRO]（https://www.microchip.com/en-us/development-tool/ATSAMC21-XPRO） \ No newline at end of file diff --git a/bsp/microchip/samc21/SConscript b/bsp/microchip/samc21/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/microchip/samc21/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/microchip/samc21/SConstruct b/bsp/microchip/samc21/SConstruct new file mode 100644 index 0000000000..4d91cd5ba5 --- /dev/null +++ b/bsp/microchip/samc21/SConstruct @@ -0,0 +1,41 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/microchip/samc21/applications/SConscript b/bsp/microchip/samc21/applications/SConscript new file mode 100644 index 0000000000..e806dae56e --- /dev/null +++ b/bsp/microchip/samc21/applications/SConscript @@ -0,0 +1,10 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/microchip/samc21/applications/can_demo.c b/bsp/microchip/samc21/applications/can_demo.c new file mode 100644 index 0000000000..a21f755725 --- /dev/null +++ b/bsp/microchip/samc21/applications/can_demo.c @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include "driver_init.h" +#include "utils.h" + +#include "can_demo.h" + +#ifdef SAM_CAN_EXAMPLE + +static volatile enum can_async_interrupt_type can_errors; +static rt_sem_t can_txdone; +static rt_sem_t can_rxdone; +static rt_uint8_t can_stack[ 512 ]; +static struct rt_thread can_thread; + +/** + * @brief Callback function and should be invoked after call can_async_write. + * + * @note + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_tx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_txdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after remote device send. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_rx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after CAN device IRQ handler detects errors happened. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_err_callback(struct can_async_descriptor *const descr, + enum can_async_interrupt_type type) +{ + rt_err_t result; + + if (type == CAN_IRQ_EW) + { + /* Error warning, Error counter has reached the error warning limit of 96, + * An error count value greater than about 96 indicates a heavily disturbed + * bus. It may be of advantage to provide means to test for this condition. + */ + } + else if (type == CAN_IRQ_EA) + { + /* Error Active State, The CAN node normally take part in bus communication + * and sends an ACTIVE ERROR FLAG when an error has been detected. + */ + } + else if (type == CAN_IRQ_EP) + { + /* Error Passive State, The Can node goes into error passive state if at least + * one of its error counters is greater than 127. It still takes part in bus + * activities, but it sends a passive error frame only, on errors. + */ + } + else if (type == CAN_IRQ_BO) + { + /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is + * greater than or equal to 256. + */ + + /* Suspend CAN task and re-initialize CAN module. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } + else if (type == CAN_IRQ_DO) + { + /* Data Overrun in receive queue. A message was lost because the messages in + * the queue was not reading and releasing fast enough. There is not enough + * space for a new message in receive queue. + */ + + /* Suggest to delete CAN task and re-initialize it. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } +}; + +/** + * @brief Initialize CAN module before task run. + * + * @note This function will set CAN Tx/Rx callback function and filters. + * + * @param None. + * + * @return None. + */ + +static inline void can_demo_init(void) +{ + struct can_filter filter; + + /** + * CAN_Node0_tx_callback callback should be invoked after call + * can_async_write, and remote device should receive message with ID=0x45A + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback); + + + /* Should set at least one CAN standard & message filter before enable it. */ + + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + /* If set second standard message filter, should increase filter index + * and filter algorithm + * For example: index should set to 1, otherwise it will replace filter 0. + * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */ + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter); + + can_async_enable(&CAN_0); +} + +/** + * @brief CAN task. + * + * @note This task will waiting for CAN RX semaphore and then process input. + * + * @param parameter - task input parameter. + * + * @return None. + */ + +static void can_thread_entry(void* parameter) +{ + int32_t ret; + rt_err_t result; + uint8_t data[64]; + uint32_t count=0; + struct can_message msg; + + while (1) + { +#ifndef RT_USING_FINSH + rt_kprintf("can task run count : %d\r\n",count); +#endif + count++; + + result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER); + if (RT_EOK != result) + continue; + + do + { + /* Process the incoming packet. */ + ret = can_async_read(&CAN_0, &msg); + if (ret == ERR_NONE) + { +#ifndef RT_USING_FINSH + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_TYPE_DATA ? "data" : "remote"); + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_FMT_STDID ? "Standard" : "Extended"); + rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len); + rt_kprintf("CAN RX Message content: "); + for (uint8_t i = 0; i < msg.len; i++) + rt_kprintf("0x%02X ", data[i]); + rt_kprintf("\r\n"); +#endif + } + } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */ + + /* CAN task got CAN error message, handler CAN Error Status */ + if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO)) + { + can_async_init(&CAN_0, CAN1); + } + } +} + +/** + * @brief Call this function will to send a CAN message. + * + * @note + * + * @param msg - message to be sent, timeouts - wait timeouts for Tx completion. + * + * @return RT_OK or RT_ERROR. + */ + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts) +{ + rt_err_t result; + + if (RT_NULL == msg) + { + rt_kprintf("can_send_message input message error\r\n"); + return RT_ERROR; + } + + can_async_write(&CAN_0, msg); + result = rt_sem_take(can_rxdone, timeouts); + + return result; +} + +/** + * @brief Call this function will create a CAN task. + * + * @note Should create Tx/Rx semaphore before run task. + * + * @param None. + * + * @return RT_OK or -RT_ERROR. + */ + +rt_err_t can_demo_run(void) +{ + rt_err_t result; + + can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_rxdone) + { + rt_kprintf("can_rx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_txdone) + { + rt_kprintf("can_tx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_demo_init(); + + /* initialize CAN thread */ + result = rt_thread_init(&can_thread, + "can", + can_thread_entry, + RT_NULL, + (rt_uint8_t*)&can_stack[0], + sizeof(can_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&can_thread); + } + + return result; +} +#endif + +/*@}*/ diff --git a/bsp/microchip/samc21/applications/can_demo.h b/bsp/microchip/samc21/applications/can_demo.h new file mode 100644 index 0000000000..499d0390f8 --- /dev/null +++ b/bsp/microchip/samc21/applications/can_demo.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __APPLICATION_CAN_H_ +#define __APPLICATION_CAN_H_ + +#include + +/** + * @brief External function definitions + * + */ +rt_err_t can_demo_run(void); + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts); + +#endif // __APPLICATION_CAN_H_ diff --git a/bsp/microchip/samc21/applications/main.c b/bsp/microchip/samc21/applications/main.c new file mode 100644 index 0000000000..8985159058 --- /dev/null +++ b/bsp/microchip/samc21/applications/main.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include + +#ifdef SAM_CAN_EXAMPLE +#include "can_demo.h" +#endif + +static rt_uint8_t led_stack[ 512 ]; +static struct rt_thread led_thread; + +static void led_thread_entry(void* parameter) +{ + unsigned int count=0; + + while (1) + { + /* toggle led */ +#ifndef RT_USING_FINSH + rt_kprintf("led toggle, count : %d\r\n",count); +#endif + count++; + gpio_toggle_pin_level(LED0); + rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */ + } +} + +int main(void) +{ + rt_err_t result; + + /* initialize led thread */ + result = rt_thread_init(&led_thread, + "led", + led_thread_entry, + RT_NULL, + (rt_uint8_t*)&led_stack[0], + sizeof(led_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&led_thread); + } + +#ifdef SAM_CAN_EXAMPLE + can_demo_run(); +#endif + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/samc21/board/Kconfig b/bsp/microchip/samc21/board/Kconfig new file mode 100644 index 0000000000..6004fe8fc7 --- /dev/null +++ b/bsp/microchip/samc21/board/Kconfig @@ -0,0 +1,52 @@ +menu "Hardware Drivers Config" + +choice + prompt "select chip type" + default SOC_SAMC21J18 + + config SOC_SAMC21J18 + bool "SOC_SAMC21J18" + help + Refer to SAMC21 DataSheet + + config SOC_SAMC21G18 + bool "SOC_SAMC21G18" + help + Refer to SAMC21 DataSheet + + config SOC_SAMC21E18 + bool "SOC_SAMC21E18" + help + Refer to SAMC21 DataSheet + +endchoice +endmenu + +menu "Onboard Peripheral Drivers" + depends on SOC_SAMC21J18 + + config SAMC21_CAN0 + bool "Enable CAN0" + default false + + config SAMC21_ADC0 + bool "Enable ADC0" + default false +endmenu + +menu "Application Demo Config" + config SAM_CAN_EXAMPLE + bool "Enable SAM CAN Example" + depends on SAMC21_CAN0 + default true + help + Add CAN example task to project + + config SAM_ADC_EXAMPLE + bool "Enable SAM ADC Example" + depends on SAMC21_ADC0 + default true + help + Add ADC example task to project + +endmenu diff --git a/bsp/microchip/samc21/board/SConscript b/bsp/microchip/samc21/board/SConscript new file mode 100644 index 0000000000..1b4455424f --- /dev/null +++ b/bsp/microchip/samc21/board/SConscript @@ -0,0 +1,17 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +#remove other no use files +#SrcRemove(src, '*.c') + +# You can select chips from the list above +CPPDEFINES = ['SAMC21xxx'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/microchip/samc21/board/board.c b/bsp/microchip/samc21/board/board.c new file mode 100644 index 0000000000..457492ad51 --- /dev/null +++ b/bsp/microchip/samc21/board/board.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#include +#include "peripheral_clk_config.h" + +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +extern int rt_hw_uart_init(void); +#endif + +static struct io_descriptor* g_stdio; + +void rt_hw_console_output(const char *str) +{ + io_write(g_stdio, (uint8_t *)str, strlen(str)); +} +RTM_EXPORT(rt_hw_console_output); + +static inline void hw_board_init_usart(void) +{ + usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio); + usart_sync_enable(&TARGET_IO); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial SAMC21 board. + */ +void rt_hw_board_init(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* enable USART stdout module */ + hw_board_init_usart(); + + /* UART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + + /* init systick */ + SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND); + + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + +#ifdef RT_USING_HEAP + #if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END); + #elif __ICCARM__ + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END); + #endif +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/*@}*/ diff --git a/bsp/microchip/samc21/board/board.h b/bsp/microchip/samc21/board/board.h new file mode 100644 index 0000000000..6de1e3f6e1 --- /dev/null +++ b/bsp/microchip/samc21/board/board.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <4-32> +// Default: 32 +#if defined(__SAMC21E15A__) || defined(__ATSAMC21E15A__) + #define SAMC21_SRAM_SIZE 4 +#elif defined(__SAMC21E16A__) || defined(__ATSAMC21E16A__) + #define SAMC21_SRAM_SIZE 8 +#elif defined(__SAMC21E17A__) || defined(__ATSAMC21E17A__) + #define SAMC21_SRAM_SIZE 16 +#elif defined(__SAMC21E18A__) || defined(__ATSAMC21E18A__) + #define SAMC21_SRAM_SIZE 32 +#elif defined(__SAMC21G15A__) || defined(__ATSAMC21G15A__) + #define SAMC21_SRAM_SIZE 4 +#elif defined(__SAMC21G16A__) || defined(__ATSAMC21G16A__) + #define SAMC21_SRAM_SIZE 8 +#elif defined(__SAMC21G17A__) || defined(__ATSAMC21G17A__) + #define SAMC21_SRAM_SIZE 16 +#elif defined(__SAMC21G18A__) || defined(__ATSAMC21G18A__) + #define SAMC21_SRAM_SIZE 32 +#elif defined(__SAMC21J15A__) || defined(__ATSAMC21J15A__) + #define SAMC21_SRAM_SIZE 4 +#elif defined(__SAMC21J16A__) || defined(__ATSAMC21J16A__) + #define SAMC21_SRAM_SIZE 8 +#elif defined(__SAMC21J17A__) || defined(__ATSAMC21J17A__) + #define SAMC21_SRAM_SIZE 16 +#elif defined(__SAMC21J17AU__) || defined(__ATSAMC21J17AU__) + #define SAMC21_SRAM_SIZE 16 +#elif defined(__SAMC21J18A__) || defined(__ATSAMC21J18A__) + #define SAMC21_SRAM_SIZE 32 +#elif defined(__SAMC21J18AU__) || defined(__ATSAMC21J18AU__) + #define SAMC21_SRAM_SIZE 32 +#else + #error Board does not support the specified device. +#endif + +#define SAMC21_SRAM_END (0x20000000 + SAMC21_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_begin("HEAP")) +#define HEAP_END (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#define HEAP_END SAMC21_SRAM_END +#endif + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/microchip/samc21/board/serial.c b/bsp/microchip/samc21/board/serial.c new file mode 100644 index 0000000000..28ba104dbe --- /dev/null +++ b/bsp/microchip/samc21/board/serial.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include +#include + +#include + +/* SAM MCU serial device */ +static struct rt_serial_device sam_serial; + +/** + * @brief Configure serial port + * + * This function will configure UART baudrate, parity and so on. + * + * @return RT_EOK. + */ +static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + usart_sync_disable(desc); + + /* Set baudrate */ + usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate); + + /* Set stop bit */ + if (cfg->stop_bits == STOP_BITS_1) + usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE); + else if (cfg->stop_bits == STOP_BITS_2) + usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO); + + if (cfg->bit_order == BIT_ORDER_LSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB); + else if (cfg->bit_order == BIT_ORDER_MSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB); + + /* Set character size */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS); + break; + case DATA_BITS_6: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS); + break; + case DATA_BITS_7: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS); + break; + case DATA_BITS_8: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS); + break; + case DATA_BITS_9: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS); + break; + default: + break; + } + + if (cfg->parity == PARITY_NONE) + usart_sync_set_parity(desc, USART_PARITY_NONE); + else if (cfg->parity == PARITY_ODD) + usart_sync_set_parity(desc, USART_PARITY_ODD); + else if (cfg->parity == PARITY_EVEN) + usart_sync_set_parity(desc, USART_PARITY_EVEN); + + usart_sync_enable(desc); + + return RT_EOK; +} + +/** + * @brief Control serial port + * + * This function provide UART enable/disable control. + * + * @return RT_EOK. + */ +static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + usart_sync_disable(desc); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + usart_sync_enable(desc); + break; + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + break; + } + + return RT_EOK; +} + +/** + * @brief Serial sends a char + * + * This function will send a char to the UART + * + * @return 1. + */ +static int serial_putc(struct rt_serial_device *serial, char c) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + io_write(&desc->io, (const uint8_t *)&c, 1); + + return 1; +} + +/** + * @brief Serial gets a char + * + * This function will get a char from the UART + * + * @return received char character or -1 if no char received. + */ +static int serial_getc(struct rt_serial_device *serial) +{ + char c; + int ch; + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + ch = -1; + if (usart_sync_is_rx_not_empty(desc)) + { + io_read(&desc->io, (uint8_t *)&c, 1);; + ch = c & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops sam_serial_ops = +{ + serial_configure, + serial_control, + serial_putc, + serial_getc, +}; + +/** + * @brief Initialize the UART + * + * This function initialize the UART + * + * @return None. + */ +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + sam_serial.ops = &sam_serial_ops; + sam_serial.config = config; + sam_serial.serial_rx = RT_NULL; + sam_serial.serial_rx = RT_NULL; + rt_hw_serial_register(&sam_serial, "uart0", + RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO); + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/samc21/board/serial.h b/bsp/microchip/samc21/board/serial.h new file mode 100644 index 0000000000..12e6811231 --- /dev/null +++ b/bsp/microchip/samc21/board/serial.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __BOARD_SERIAL_H_ +#define __BOARD_SERIAL_H_ + +#include + +/** + * @brief External function definitions + * + */ +int rt_hw_uart_init(void); + +#endif // __BOARD_SERIAL_H_ diff --git a/bsp/microchip/samc21/bsp/AtmelStart.env_conf b/bsp/microchip/samc21/bsp/AtmelStart.env_conf new file mode 100644 index 0000000000..ea16f17e5f --- /dev/null +++ b/bsp/microchip/samc21/bsp/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/bsp/microchip/samc21/bsp/AtmelStart.gpdsc b/bsp/microchip/samc21/bsp/AtmelStart.gpdsc new file mode 100644 index 0000000000..53c65dde79 --- /dev/null +++ b/bsp/microchip/samc21/bsp/AtmelStart.gpdsc @@ -0,0 +1,203 @@ + + Atmel + SAMC21 LED switcher + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + + + + + + + + +
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-M):

+ +
+

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
+
+

+Processor Support

+

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

+

+Cortex-M Reference Manuals

+

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

+ +

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

+ +

+Armv8-M Architecture

+

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

+

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

+
+

+Tested and Verified Toolchains

+

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

+
    +
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • Arm: Arm Compiler 6.9
    • +
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • +
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • +
+
+
+
+ + + + diff --git a/bsp/microchip/samc21/bsp/SConscript b/bsp/microchip/samc21/bsp/SConscript new file mode 100644 index 0000000000..08c10b1d21 --- /dev/null +++ b/bsp/microchip/samc21/bsp/SConscript @@ -0,0 +1,58 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +#var defined +CPPDEFINES = [] + +#common lib define +CPPDEFINES += [rtconfig.DEVICE_TYPE] + +# The set of source files associated with this SConscript file. +src = Glob('hal/src/*.c') +src += Glob('hal/utils/src/*.c') +src += Glob('hpl/can/*.c') +src += Glob('hpl/core/*.c') +src += Glob('hpl/divas/*.c') +src += Glob('hpl/dmac/*.c') +src += Glob('hpl/gclk/*.c') +src += Glob('hpl/mclk/*.c') +src += Glob('hpl/nvmctrl/*.c') +src += Glob('hpl/osc32kctrl/*.c') +src += Glob('hpl/oscctrl/*.c') +src += Glob('hpl/pm/*.c') +src += Glob('hpl/port/*.c') +src += Glob('hpl/sercom/*.c') +src += [cwd + '/atmel_start.c'] +src += [cwd + '/driver_init.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/samc21/gcc/system_samc21.c'] + src += [cwd + '/samc21/gcc/gcc/startup_samc21.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/samc21/armcc/arm_addon/armcc/' + 'system_samc21.c'] + src += [cwd + '/samc21/armcc/arm_addon/armcc/arm/' + 'startup_samc21.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/samc21/iar/' + 'system_samc21.c'] + src += [cwd + '/samc21/iar/iar/' + 'startup_samc21.c'] + +path = [ + cwd, + cwd + '/CMSIS/Core/Include', + cwd + '/config', + cwd + '/hal/include', + cwd + '/hal/utils/include', + cwd + '/hpl/can', + cwd + '/hpl/core', + cwd + '/hpl/gclk', + cwd + '/hpl/pm', + cwd + '/hpl/port', + cwd + '/hri', + cwd + '/samc21/include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/microchip/samc21/bsp/armcc/Makefile b/bsp/microchip/samc21/bsp/armcc/Makefile new file mode 100644 index 0000000000..c756181f09 --- /dev/null +++ b/bsp/microchip/samc21/bsp/armcc/Makefile @@ -0,0 +1,218 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/pm \ +hpl/osc32kctrl \ +hpl/can \ +hpl/dmac \ +samc21/armcc/Device/SAMC21/Source/ARM \ +hal/src \ +hpl/mclk \ +hal/utils/src \ +hpl/sercom \ +examples \ +hpl/gclk \ +hpl/oscctrl \ +samc21/armcc/Device/SAMC21/Source \ +hpl/nvmctrl \ +hpl/core \ +hpl/divas + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hal/src/hal_can_async.o \ +hpl/can/hpl_can.o \ +hpl/nvmctrl/hpl_nvmctrl.o \ +samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.o \ +hal/src/hal_delay.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hpl/core/hpl_init.o \ +hal/utils/src/utils_list.o \ +hpl/core/hpl_core_m0plus_base.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/pm/hpl_pm.o \ +hal/src/hal_usart_sync.o \ +hpl/mclk/hpl_mclk.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_flash.o \ +hal/src/hal_init.o \ +main.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +examples/driver_examples.o \ +driver_init.o \ +samc21/armcc/Device/SAMC21/Source/system_samc21.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +hpl/divas/hpl_divas.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +atmel_start.o \ +hal/src/hal_atomic.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hal/src/hal_can_async.o" \ +"hpl/can/hpl_can.o" \ +"hpl/nvmctrl/hpl_nvmctrl.o" \ +"samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.o" \ +"hal/src/hal_delay.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hpl/core/hpl_init.o" \ +"hal/utils/src/utils_list.o" \ +"hpl/core/hpl_core_m0plus_base.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/pm/hpl_pm.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_flash.o" \ +"hal/src/hal_init.o" \ +"main.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"samc21/armcc/Device/SAMC21/Source/system_samc21.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"hpl/divas/hpl_divas.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"atmel_start.o" \ +"hal/src/hal_atomic.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hal/src/hal_can_async.d" \ +"hpl/can/hpl_can.d" \ +"samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.d" \ +"hpl/nvmctrl/hpl_nvmctrl.d" \ +"hpl/core/hpl_core_m0plus_base.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"hal/src/hal_flash.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"hpl/mclk/hpl_mclk.d" \ +"driver_init.d" \ +"samc21/armcc/Device/SAMC21/Source/system_samc21.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hpl/divas/hpl_divas.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARMCC Linker + $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ +--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ +--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ +-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \ +$(OBJS_AS_ARGS) + + @echo Finished building target: $@ + +# Compiler target(s) + + + + +%.o: %.c + @echo Building file: $< + @echo ARMCC Compiler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMC21J18A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARMCC Assembler + $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMC21J18A__ SETA 1" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include" \ +--depend "$(@:%.o=%.d)" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARMCC Preprocessing Assembler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMC21J18A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/bsp/microchip/samc21/bsp/atmel_start.c b/bsp/microchip/samc21/bsp/atmel_start.c new file mode 100644 index 0000000000..79f252aed9 --- /dev/null +++ b/bsp/microchip/samc21/bsp/atmel_start.c @@ -0,0 +1,9 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/bsp/microchip/samc21/bsp/atmel_start.h b/bsp/microchip/samc21/bsp/atmel_start.h new file mode 100644 index 0000000000..0de62f528d --- /dev/null +++ b/bsp/microchip/samc21/bsp/atmel_start.h @@ -0,0 +1,18 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/microchip/samc21/bsp/atmel_start_config.atstart b/bsp/microchip/samc21/bsp/atmel_start_config.atstart new file mode 100644 index 0000000000..726b284ec9 --- /dev/null +++ b/bsp/microchip/samc21/bsp/atmel_start_config.atstart @@ -0,0 +1,737 @@ +format_version: '2' +name: SAMC21 LED switcher +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: SAMC21XplainedPro + device: SAMC21J18A-AN +details: null +application: + definition: 'Atmel:Application_Examples:0.0.1::Application:RWW_FLASH:' + configuration: null +middlewares: {} +drivers: + DMAC: + user_label: DMAC + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_1_settings: false + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dqos: Background (no sensitive operation) + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_2: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_enable_0: false + dmac_enable_1: false + dmac_enable_10: false + dmac_enable_11: false + dmac_enable_12: false + dmac_enable_13: false + dmac_enable_14: false + dmac_enable_15: false + dmac_enable_2: false + dmac_enable_3: false + dmac_enable_4: false + dmac_enable_5: false + dmac_enable_6: false + dmac_enable_7: false + dmac_enable_8: false + dmac_enable_9: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_2: No action + dmac_evact_3: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_2: false + dmac_evie_3: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_2: false + dmac_evoe_3: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_fqos: Background (no sensitive operation) + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: false + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_2: false + dmac_runstdby_3: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_2: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + dmac_wrbqos: Background (no sensitive operation) + optional_signals: [] + variant: null + clocks: + domain_group: null + GCLK: + user_label: GCLK + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 400000 + $input_id: External Crystal Oscillator 0.4-32MHz (XOSC) + RESERVED_InputFreq: 400000 + RESERVED_InputFreq_id: External Crystal Oscillator 0.4-32MHz (XOSC) + _$freq_output_Generic clock generator 0: 40001536 + _$freq_output_Generic clock generator 1: 4000000 + _$freq_output_Generic clock generator 2: 400000 + _$freq_output_Generic clock generator 3: 400000 + _$freq_output_Generic clock generator 4: 400000 + _$freq_output_Generic clock generator 5: 400000 + _$freq_output_Generic clock generator 6: 400000 + _$freq_output_Generic clock generator 7: 400000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: true + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: true + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_1_enable: true + gclk_arch_gen_1_idc: true + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Fractional Digital Phase Locked Loop (FDPLL96M) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: 48MHz Internal Oscillator (OSC48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 40001536 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 40001536 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 40001536 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + nvm_wait_states: '4' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + FLASH_0: + user_label: FLASH_0 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH + functionality: Flash + api: HAL:Driver:FLASH + configuration: + nvm_arch_cache: false + nvm_arch_read_mode: No Miss Penalty + nvm_arch_sleepprm: Wake On Access + optional_signals: [] + variant: null + clocks: + domain_group: null + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osc32k: false + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: true + osc32k_arch_calib: 0 + osc32k_arch_calib_enable: false + osc32k_arch_en1k: false + osc32k_arch_en32k: false + osc32k_arch_enable: false + osc32k_arch_ondemand: false + osc32k_arch_runstdby: false + osc32k_arch_startup: 92us + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_en1k: false + xosc32k_arch_en32k: true + xosc32k_arch_enable: true + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: true + xosc32k_arch_startup: 62592us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 32768 + $input_id: 32kHz External Crystal Oscillator (XOSC32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) + _$freq_output_48MHz Internal Oscillator (OSC48M): 4000000 + _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000 + _$freq_output_Fractional Digital Phase Locked Loop (FDPLL96M): 40001536 + enable_fdpll96m: true + enable_osc48m: true + enable_xosc: false + fdpll96m_arch_enable: true + fdpll96m_arch_filter: Default filter mode + fdpll96m_arch_lbypass: false + fdpll96m_arch_lpen: false + fdpll96m_arch_ltime: No time-out, automatic lock + fdpll96m_arch_ondemand: true + fdpll96m_arch_runstdby: false + fdpll96m_arch_wuf: false + fdpll96m_clock_div: 0 + fdpll96m_ldr: 1219 + fdpll96m_ldrfrac: 12 + fdpll96m_presc: '1' + fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + osc48m_arch_enable: true + osc48m_arch_ondemand: true + osc48m_arch_runstdby: false + osc48m_arch_startup: 21.333us + osc48m_div: 11 + xosc_arch_ampgc: false + xosc_arch_cfden: false + xosc_arch_cfdeo: false + xosc_arch_enable: false + xosc_arch_gain: 2MHz + xosc_arch_ondemand: true + xosc_arch_runstdby: false + xosc_arch_startup: 31us + xosc_arch_swben: false + xosc_arch_xtalen: false + xosc_frequency: 400000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 115200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=1, RXPO=3, CMODE=0 + required_signals: + - name: SERCOM4/PAD/2 + pad: PB10 + label: TX + - name: SERCOM4/PAD/3 + pad: PB11 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 1 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 1 + CAN_0: + user_label: CAN_0 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::CAN0::driver_config_definition::CAN::HAL:Driver:CAN.Async + functionality: CAN + api: HAL:Driver:CAN_Async + configuration: + can_btp_brp: 4 + can_btp_sjw: 10 + can_btp_tseg1: 31 + can_btp_tseg2: 8 + can_cccr_brse: false + can_cccr_fdoe: false + can_dbtp_dbrp: 4 + can_dbtp_dsjw: 4 + can_dbtp_dtseg1: 31 + can_dbtp_dtseg2: 8 + can_dbtp_tdc: false + can_gfc_anfe: Reject + can_gfc_anfs: Reject + can_gfc_rrfe: Filter remote frames with 29-bit standard IDs + can_gfc_rrfs: Filter remote frames with 11-bit standard IDs + can_ie_bo: true + can_ie_do: true + can_ie_ea: true + can_ie_ep: true + can_ie_ew: true + can_mrcfg_dqos: Sensitive latency + can_mrcfg_runstandby: false + can_rxesc_f0ds: 8 byte data field. + can_rxf0c_f0om: blocking mode + can_rxf0c_f0s: 32 + can_rxf0c_f0wm: 0 + can_sidfc_lss: 128 + can_txbc_tfqs: 32 + can_txefc_efs: 32 + can_txefc_efwm: 0 + can_txesc_tbds: 8 byte data field. + can_xidam_eidm: 0 + can_xidfc_lss: 64 + optional_signals: + - identifier: CAN_0:RX + pad: PA25 + mode: Enabled + configuration: null + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::CAN0.RX + name: CAN0/RX + label: RX + - identifier: CAN_0:TX + pad: PA24 + mode: Enabled + configuration: null + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::CAN0.TX + name: CAN0/TX + label: TX + variant: null + clocks: + domain_group: + nodes: + - name: CAN + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + can_gclk_selection: Generic clock generator 0 +pads: + PB10: + name: PB10 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10 + mode: Peripheral IO + user_label: PB10 + configuration: null + PB11: + name: PB11 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB11 + mode: Peripheral IO + user_label: PB11 + configuration: null + LED0: + name: PA15 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA15 + mode: Digital output + user_label: LED0 + configuration: null + PA24: + name: PA24 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA24 + mode: Peripheral IO + user_label: PA24 + configuration: null + PA25: + name: PA25 + definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA25 + mode: Peripheral IO + user_label: PA25 + configuration: null +toolchain_options: [] +static_files: [] diff --git a/bsp/microchip/samc21/bsp/atmel_start_pins.h b/bsp/microchip/samc21/bsp/atmel_start_pins.h new file mode 100644 index 0000000000..93a0d0d7c5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/atmel_start_pins.h @@ -0,0 +1,31 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAMC21 has 9 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 + +#define LED0 GPIO(GPIO_PORTA, 15) +#define PA24 GPIO(GPIO_PORTA, 24) +#define PA25 GPIO(GPIO_PORTA, 25) +#define PB10 GPIO(GPIO_PORTB, 10) +#define PB11 GPIO(GPIO_PORTB, 11) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/bsp/microchip/samc21/bsp/config/hpl_can_config.h b/bsp/microchip/samc21/bsp/config/hpl_can_config.h new file mode 100644 index 0000000000..3a5f9d217d --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_can_config.h @@ -0,0 +1,391 @@ +/* Auto-generated config file hpl_can_config.h */ +#ifndef HPL_CAN_CONFIG_H +#define HPL_CAN_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_CAN0_ENABLED +#define CONF_CAN0_ENABLED 1 +#endif +// Basic Configuration + +// FD Operation Enable +// Enable CAN FD operation +// can_cccr_fdoe +#ifndef CONF_CAN0_CCCR_FDOE +#define CONF_CAN0_CCCR_FDOE 0 +#endif + +// Bit Rate Switch Enable +// Bit Rate Switch Enable +// can_cccr_brse +#ifndef CONF_CAN0_CCCR_BRSE +#define CONF_CAN0_CCCR_BRSE 0 +#endif + +// Run In Standby is invalid for C21/E5x/D5x devices +// Run In Standby +// Indicates whether to not disable CAN during standby sleep mode +// can_mrcfg_runstandby +#ifndef CONF_CAN0_MRCFG_RUNSTANDBY +#define CONF_CAN0_MRCFG_RUNSTANDBY 0 +#endif +// + +// Data Quality of Service +// Select he memory priority access during the Message RAM read/write data operation. +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// can_mrcfg_dqos +#ifndef CONF_CAN0_MRCFG_DQOS +#define CONF_CAN0_MRCFG_DQOS 2 +#endif + +// + +// Normal Bit Timing and Prescaler Configuration + +// Baud Rate Prescaler <1-512> +// Baud Rate Prescale +// can_btp_brp +#ifndef CONF_CAN0_BTP_BRP +#define CONF_CAN0_BTP_BRP 4 +#endif + +// time segment before sample point <2-256> +// time segment before sample point +// can_btp_tseg1 +#ifndef CONF_CAN0_BTP_TSEG1 +#define CONF_CAN0_BTP_TSEG1 31 +#endif + +// time segment after sample point <1-128> +// time segment after sample point +// can_btp_tseg2 +#ifndef CONF_CAN0_BTP_TSEG2 +#define CONF_CAN0_BTP_TSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-128> +// (Re)Syncronization Jump Width +// can_btp_sjw +#ifndef CONF_CAN0_BTP_SJW +#define CONF_CAN0_BTP_SJW 10 +#endif + +// + +// Data Bit Timing and Prescaler Configuration + +// Transceiver Delay Compensation Enable +// Transceiver Delay Compensation Enable +// can_dbtp_tdc +#ifndef CONF_CAN0_DBTP_TDC +#define CONF_CAN0_DBTP_TDC 0 +#endif + +// Data Baud Rate Prescaler <1-32> +// Data Baud Rate Prescaler +// can_dbtp_dbrp +#ifndef CONF_CAN0_DBTP_DBRP +#define CONF_CAN0_DBTP_DBRP 4 +#endif + +// Fast time segment before sample point <1-32> +// Fast time segment before sample point +// can_dbtp_dtseg1 +#ifndef CONF_CAN0_DBTP_DTSEG1 +#define CONF_CAN0_DBTP_DTSEG1 31 +#endif + +// Data time segment after sample point <1-16> +// Fast time segment after sample point +// can_dbtp_dtseg2 +#ifndef CONF_CAN0_DBTP_DTSEG2 +#define CONF_CAN0_DBTP_DTSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-16> +// Fast Syncronization Jump Width +// can_dbtp_dsjw +#ifndef CONF_CAN0_DBTP_DSJW +#define CONF_CAN0_DBTP_DSJW 4 +#endif + +// + +// RX FIFO Configuration + +// Operation Mode +// Select Operation Mode +// <0=> blocking mode +// <1=> overwrite mode +// can_rxf0c_f0om +#ifndef CONF_CAN0_RXF0C_F0OM +#define CONF_CAN0_RXF0C_F0OM 0 +#endif + +// Watermark <0-64> +// Watermark, 0 for disable watermark interrupt +// can_rxf0c_f0wm +#ifndef CONF_CAN0_RXF0C_F0WM +#define CONF_CAN0_RXF0C_F0WM 0 +#endif + +// Size <0-64> +// Number of Rx FIFO 0 element +// can_rxf0c_f0s +#ifndef CONF_CAN0_RXF0C_F0S +#define CONF_CAN0_RXF0C_F0S 32 +#endif + +// Data Field Size +// Rx FIFO 0 Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_rxesc_f0ds +#ifndef CONF_CAN0_RXESC_F0DS +#define CONF_CAN0_RXESC_F0DS 0 +#endif + +/* Bytes size for CAN FIFO 0 element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN0_F0DS +#define CONF_CAN0_F0DS \ + ((CONF_CAN0_RXESC_F0DS < 5) ? ((CONF_CAN0_RXESC_F0DS << 2) + 16) : (40 + ((CONF_CAN0_RXESC_F0DS % 5) << 4))) + +// + +// TX FIFO Configuration + +// Transmit FIFO Size <0-32> +// Number of Tx Buffers used for Tx FIFO +// can_txbc_tfqs +#ifndef CONF_CAN0_TXBC_TFQS +#define CONF_CAN0_TXBC_TFQS 32 +#endif + +// Tx Buffer Data Field Size +// Tx Buffer Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_txesc_tbds +#ifndef CONF_CAN0_TXESC_TBDS +#define CONF_CAN0_TXESC_TBDS 0 +#endif + +/* Bytes size for CAN Transmit Buffer element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN0_TBDS +#define CONF_CAN0_TBDS \ + ((CONF_CAN0_TXESC_TBDS < 5) ? ((CONF_CAN0_TXESC_TBDS << 2) + 16) : (40 + ((CONF_CAN0_TXESC_TBDS % 5) << 4))) + +// + +// TX Event Configuration + +// Watermark <0-32> +// Watermark, 0 for disable watermark interrupt +// can_txefc_efwm +#ifndef CONF_CAN0_TXEFC_EFWM +#define CONF_CAN0_TXEFC_EFWM 0 +#endif + +// Size <0-32> +// Number of Event FIFO element +// can_txefc_efs +#ifndef CONF_CAN0_TXEFC_EFS +#define CONF_CAN0_TXEFC_EFS 32 +#endif + +// + +// Filter Configuration + +// Accept Non-matching Frames Standard +// Defines how received messages with 11-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfs +#ifndef CONF_CAN0_GFC_ANFS +#define CONF_CAN0_GFC_ANFS 2 +#endif + +// Accept Non-matching Frames Extended +// Defines how received messages with 29-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfe +#ifndef CONF_CAN0_GFC_ANFE +#define CONF_CAN0_GFC_ANFE 2 +#endif + +// Reject Remote Frames Standard +// Defines how received remote frames with 11-bit standard IDs. +// <0=> Filter remote frames with 11-bit standard IDs +// <1=> Reject all remote frames with 11-bit standard IDs +// can_gfc_rrfs +#ifndef CONF_CAN0_GFC_RRFS +#define CONF_CAN0_GFC_RRFS 0 +#endif + +// Reject Remote Frames Extended +// Defines how received remote frames with 29-bit standard IDs. +// <0=> Filter remote frames with 29-bit standard IDs +// <1=> Reject all remote frames with 29-bit standard IDs +// can_gfc_rrfe +#ifndef CONF_CAN0_GFC_RRFE +#define CONF_CAN0_GFC_RRFE 0 +#endif + +// Number of standard Message ID filter elements <0-128> +// Number of standard Message ID filter elements +// can_sidfc_lss +#ifndef CONF_CAN0_SIDFC_LSS +#define CONF_CAN0_SIDFC_LSS 128 +#endif + +// Number of Extended Message ID filter elements <0-128> +// Number of Extended Message ID filter elements +// can_xidfc_lss +#ifndef CONF_CAN0_XIDFC_LSS +#define CONF_CAN0_XIDFC_LSS 64 +#endif + +// Extended ID Mask <0x0000-0x1FFFFFFF> +// For acceptance filtering of extended frames the Extended ID AND Mask is +// ANDed with the Message ID of a received frame. Intended for masking of +// 29-bit IDs in SAE J1939. With the reset value of all bits set to one the +// mask is not active. +// can_xidam_eidm +#ifndef CONF_CAN0_XIDAM_EIDM +#define CONF_CAN0_XIDAM_EIDM 0x0 +#endif + +// + +// Interrupt Configuration + +// Error Warning +// Indicates whether to not disable CAN error warning interrupt +// can_ie_ew +#ifndef CONF_CAN0_IE_EW +#define CONF_CAN0_IE_EW 1 +#endif + +// Error Active +// Indicates whether to not disable CAN error active interrupt +// can_ie_ea +#ifndef CONF_CAN0_IE_EA +#define CONF_CAN0_IE_EA 1 +#endif + +// Error Passive +// Indicates whether to not disable CAN error passive interrupt +// can_ie_ep +#ifndef CONF_CAN0_IE_EP +#define CONF_CAN0_IE_EP 1 +#endif + +// Bus Off +// Indicates whether to not disable CAN bus off interrupt +// can_ie_bo +#ifndef CONF_CAN0_IE_BO +#define CONF_CAN0_IE_BO 1 +#endif + +// Data Overrun +// Indicates whether to not disable CAN data overrun interrupt +// can_ie_do +#ifndef CONF_CAN0_IE_DO +#define CONF_CAN0_IE_DO 1 +#endif + +// + +#ifndef CONF_CAN0_CCCR_REG +#define CONF_CAN0_CCCR_REG (CONF_CAN0_CCCR_FDOE << CAN_CCCR_FDOE_Pos) | (CONF_CAN0_CCCR_BRSE << CAN_CCCR_BRSE_Pos) +#endif + +#ifndef CONF_CAN0_MRCFG_REG +#define CONF_CAN0_MRCFG_REG CAN_MRCFG_QOS(CONF_CAN0_MRCFG_DQOS) +#endif + +#ifndef CONF_CAN0_BTP_REG +#define CONF_CAN0_BTP_REG \ + CAN_NBTP_NBRP(CONF_CAN0_BTP_BRP - 1) | CAN_NBTP_NTSEG1(CONF_CAN0_BTP_TSEG1 - 1) \ + | CAN_NBTP_NTSEG2(CONF_CAN0_BTP_TSEG2 - 1) | CAN_NBTP_NSJW(CONF_CAN0_BTP_SJW - 1) +#endif + +#ifndef CONF_CAN0_DBTP_REG +#define CONF_CAN0_DBTP_REG \ + (CONF_CAN0_DBTP_TDC << CAN_DBTP_TDC_Pos) | CAN_DBTP_DBRP(CONF_CAN0_DBTP_DBRP - 1) \ + | CAN_DBTP_DTSEG1(CONF_CAN0_DBTP_DTSEG1 - 1) | CAN_DBTP_DTSEG2(CONF_CAN0_DBTP_DTSEG2 - 1) \ + | CAN_DBTP_DSJW(CONF_CAN0_DBTP_DSJW - 1) +#endif + +#ifndef CONF_CAN0_RXF0C_REG +#define CONF_CAN0_RXF0C_REG \ + (CONF_CAN0_RXF0C_F0OM << CAN_RXF0C_F0OM_Pos) | CAN_RXF0C_F0WM(CONF_CAN0_RXF0C_F0WM) \ + | CAN_RXF0C_F0S(CONF_CAN0_RXF0C_F0S) +#endif + +#ifndef CONF_CAN0_RXESC_REG +#define CONF_CAN0_RXESC_REG CAN_RXESC_F0DS(CONF_CAN0_RXESC_F0DS) +#endif + +#ifndef CONF_CAN0_TXESC_REG +#define CONF_CAN0_TXESC_REG CAN_TXESC_TBDS(CONF_CAN0_TXESC_TBDS) +#endif + +#ifndef CONF_CAN0_TXBC_REG +#define CONF_CAN0_TXBC_REG CAN_TXBC_TFQS(CONF_CAN0_TXBC_TFQS) +#endif + +#ifndef CONF_CAN0_TXEFC_REG +#define CONF_CAN0_TXEFC_REG CAN_TXEFC_EFWM(CONF_CAN0_TXEFC_EFWM) | CAN_TXEFC_EFS(CONF_CAN0_TXEFC_EFS) +#endif + +#ifndef CONF_CAN0_GFC_REG +#define CONF_CAN0_GFC_REG \ + CAN_GFC_ANFS(CONF_CAN0_GFC_ANFS) | CAN_GFC_ANFE(CONF_CAN0_GFC_ANFE) | (CONF_CAN0_GFC_RRFS << CAN_GFC_RRFS_Pos) \ + | (CONF_CAN0_GFC_RRFE << CAN_GFC_RRFE_Pos) +#endif + +#ifndef CONF_CAN0_SIDFC_REG +#define CONF_CAN0_SIDFC_REG CAN_SIDFC_LSS(CONF_CAN0_SIDFC_LSS) +#endif + +#ifndef CONF_CAN0_XIDFC_REG +#define CONF_CAN0_XIDFC_REG CAN_XIDFC_LSE(CONF_CAN0_XIDFC_LSS) +#endif + +#ifndef CONF_CAN0_XIDAM_REG +#define CONF_CAN0_XIDAM_REG CAN_XIDAM_EIDM(CONF_CAN0_XIDAM_EIDM) +#endif + +#ifndef CONF_CAN0_IE_REG +#define CONF_CAN0_IE_REG \ + (CONF_CAN0_IE_EW << CAN_IR_EW_Pos) | (CONF_CAN0_IE_EA << CAN_IR_EP_Pos) | (CONF_CAN0_IE_EP << CAN_IR_EP_Pos) \ + | (CONF_CAN0_IE_BO << CAN_IR_BO_Pos) | (CONF_CAN0_IE_DO << CAN_IR_RF0L_Pos) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_CAN_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_divas_config.h b/bsp/microchip/samc21/bsp/config/hpl_divas_config.h new file mode 100644 index 0000000000..ff6392e0d9 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_divas_config.h @@ -0,0 +1,13 @@ + +// Advanced settings + +// Disable Leading Zero Optimization +// Leading zero optimization makes division faster but cycles to take varias according to input values +// With leading zero optimization the clock cycles are 2-8 for 16-bit and 2-16 for 32-bit +// Disable leading zero optimization will force the division to take a fixed time of maximum number of cycles +// divas_arch_dlz +#ifndef CONF_DIVAS_DLZ +#define CONF_DIVAS_DLZ 0 +#endif + +// diff --git a/bsp/microchip/samc21/bsp/config/hpl_dmac_config.h b/bsp/microchip/samc21/bsp/config/hpl_dmac_config.h new file mode 100644 index 0000000000..1626b5c4d6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_dmac_config.h @@ -0,0 +1,3474 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> TSENS Result Ready Trigger +// <0x02=> SERCOM0 RX Trigger +// <0x03=> SERCOM0 TX Trigger +// <0x04=> SERCOM1 RX Trigger +// <0x05=> SERCOM1 TX Trigger +// <0x06=> SERCOM2 RX Trigger +// <0x07=> SERCOM2 TX Trigger +// <0x08=> SERCOM3 RX Trigger +// <0x09=> SERCOM3 TX Trigger +// <0x0A=> SERCOM4 RX Trigger +// <0x0B=> SERCOM4 TX Trigger +// <0x0C=> SERCOM5 RX Trigger +// <0x0D=> SERCOM5 TX Trigger +// <0x0E=> CAN0 Debug Trigger +// <0x0F=> CAN1 Debug Trigger +// <0x10=> TCC0 Overflow Trigger +// <0x11=> TCC0 Match/Compare 0 Trigger +// <0x12=> TCC0 Match/Compare 1 Trigger +// <0x13=> TCC0 Match/Compare 2 Trigger +// <0x14=> TCC0 Match/Compare 3 Trigger +// <0x15=> TCC1 Overflow Trigger +// <0x16=> TCC1 Match/Compare 0 Trigger +// <0x17=> TCC1 Match/Compare 1 Trigger +// <0x18=> TCC2 Overflow Trigger +// <0x19=> TCC2 Match/Compare 0 Trigger +// <0x1A=> TCC2 Match/Compare 1 Trigger +// <0x1B=> TC0 Overflow Trigger +// <0x1C=> TC0 Match/Compare 0 Trigger +// <0x1D=> TC0 Match/Compare 1 Trigger +// <0x1E=> TC1 Overflow Trigger +// <0x1F=> TC1 Match/Compare 0 Trigger +// <0x20=> TC1 Match/Compare 1 Trigger +// <0x21=> TC2 Overflow Trigger +// <0x22=> TC2 Match/Compare 0 Trigger +// <0x23=> TC2 Match/Compare 1 Trigger +// <0x24=> TC3 Overflow Trigger +// <0x25=> TC3 Match/Compare 0 Trigger +// <0x26=> TC3 Match/Compare 1 Trigger +// <0x27=> TC4 Overflow Trigger +// <0x28=> TC4 Match/Compare 0 Trigger +// <0x29=> TC4 Match/Compare 1 Trigger +// <0x2A=> ADC0 Result Ready Trigger +// <0x2B=> ADC1 Result Ready Trigger +// <0x2C=> SDADC Result Ready Trigger +// <0x2D=> DAC Empty Trigger +// <0x2E=> PTC End of Conversion Trigger +// <0x2F=> PTC Window Compare Trigger +// <0x30=> PTC Sequence Trigger +// <0x31=> SERCOM6 RX Trigger +// <0x32=> SERCOM6 TX Trigger +// <0x33=> SERCOM7 RX Trigger +// <0x34=> SERCOM7 TX Trigger +// <0x35=> TC5 Overflow Trigger +// <0x36=> TC5 Match/Compare 0 Trigger +// <0x37=> TC5 Match/Compare 1 Trigger +// <0x38=> TC6 Overflow Trigger +// <0x39=> TC6 Match/Compare 0 Trigger +// <0x3A=> TC6 Match/Compare 1 Trigger +// <0x3B=> TC7 Overflow Trigger +// <0x3C=> TC7 Match/Compare 0 Trigger +// <0x3D=> TC7 Match/Compare 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_gclk_config.h b/bsp/microchip/samc21/bsp/config/hpl_gclk_config.h new file mode 100644 index 0000000000..8bb8c3f434 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_gclk_config.h @@ -0,0 +1,608 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL96M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 1 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_OSC48M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 1 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 48MHz Internal Oscillator (OSC48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_mclk_config.h b/bsp/microchip/samc21/bsp/config/hpl_mclk_config.h new file mode 100644 index 0000000000..71977d4bb0 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_mclk_config.h @@ -0,0 +1,72 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif + +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 4 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_nvmctrl_config.h b/bsp/microchip/samc21/bsp/config/hpl_nvmctrl_config.h new file mode 100644 index 0000000000..88d6bb93ff --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_nvmctrl_config.h @@ -0,0 +1,38 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Read Mode Selection +// <0x00=> No Miss Penalty +// <0x01=> Low Power +// <0x02=> Deterministic +// nvm_arch_read_mode +#ifndef CONF_NVM_READ_MODE +#define CONF_NVM_READ_MODE 0 +#endif + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// Cache Disable +// Indicate whether cache is disable or not +// nvm_arch_cache +#ifndef CONF_NVM_CACHE +#define CONF_NVM_CACHE 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_osc32kctrl_config.h b/bsp/microchip/samc21/bsp/config/hpl_osc32kctrl_config.h new file mode 100644 index 0000000000..bc933ba434 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_osc32kctrl_config.h @@ -0,0 +1,229 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>122us +// <0x1=>1068us +// <0x2=>62592us +// <0x3=>125092us +// <0x4=>500092us +// <0x5=>1000092us +// <0x6=>2000092us +// <0x7=>4000092us// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x2 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 1 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 1 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator Control +// Enable +// Indicates whether 32kHz Internal Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc32k_arch_calib_enable +#ifndef CONF_OSC32K_CALIB_ENABLE +#define CONF_OSC32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x7F> +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0x0 +#endif + +// Start-Up Time +// <0x0=>92us +// <0x1=>122us +// <0x2=>183us +// <0x3=>305us +// <0x4=>549us +// <0x5=>1038us +// <0x6=>2014us +// <0x7=>3967us +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_oscctrl_config.h b/bsp/microchip/samc21/bsp/config/hpl_oscctrl_config.h new file mode 100644 index 0000000000..652408aa63 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_oscctrl_config.h @@ -0,0 +1,308 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc_arch_swben +#ifndef CONF_XOSC_SWBEN +#define CONF_XOSC_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc_arch_cfden +#ifndef CONF_XOSC_CFDEN +#define CONF_XOSC_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc_arch_cfdeo +#ifndef CONF_XOSC_CFDEO +#define CONF_XOSC_CFDEO 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 48MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC48M is enabled or not +// enable_osc48m +#ifndef CONF_OSC48M_CONFIG +#define CONF_OSC48M_CONFIG 1 +#endif + +// 48MHz Internal Oscillator Control +// Enable +// Indicates whether 48MHz Internal Oscillator is enabled or not +// osc48m_arch_enable +#ifndef CONF_OSC48M_ENABLE +#define CONF_OSC48M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc48m_arch_ondemand +#ifndef CONF_OSC48M_ONDEMAND +#define CONF_OSC48M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc48m_arch_runstdby +#ifndef CONF_OSC48M_RUNSTDBY +#define CONF_OSC48M_RUNSTDBY 0 +#endif + +// Oscillator Division Selection <0x0-0xF> +// Indicates OSC48M division value +// osc48m_div +#ifndef CONF_OSC48M_DIV +#define CONF_OSC48M_DIV 11 +#endif + +// Start-Up Time +// <0x0=> 166ns +// <0x1=> 333ns +// <0x2=> 667ns +// <0x3=> 1.333us +// <0x4=> 2.667us +// <0x5=> 5.333us +// <0x6=> 10.667us +// <0x7=> 21.333us +// osc48m_arch_startup +#ifndef CONF_OSC48M_STARTUP +#define CONF_OSC48M_STARTUP 0x7 +#endif + +// +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 1 +#endif + +#define CONF_OSCCTRL_DPLL_REFCLK_XOSC32K 0 +#define CONF_OSCCTRL_DPLL_REFCLK_XOSC 1 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK 2 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK0 CONF_OSCCTRL_DPLL_REFCLK_GCLK +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK1 3 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK2 4 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK3 5 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK4 6 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK5 7 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK6 8 +#define CONF_OSCCTRL_DPLL_REFCLK_GCLK7 9 + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_REFCLK_VAL +#define CONF_DPLL_REFCLK_VAL CONF_OSCCTRL_DPLL_REFCLK_XOSC32K +#endif + +#if (CONF_DPLL_REFCLK_VAL <= CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#define CONF_DPLL_REFCLK CONF_DPLL_REFCLK_VAL +#endif +#if (CONF_DPLL_REFCLK_VAL > CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#define CONF_DPLL_REFCLK CONF_OSCCTRL_DPLL_REFCLK_GCLK +#define CONF_DPLL_GCLK (CONF_DPLL_REFCLK_VAL - CONF_OSCCTRL_DPLL_REFCLK_GCLK0) +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/16)/(2^presc) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xc +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/16)/(2^presc) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x4c3 +#endif + +// Clock Divider <0x0-0x3FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0x0=>Default filter mode +// <0x1=>Low bandwidth filter +// <0x2=>High bandwidth filter +// <0x3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_port_config.h b/bsp/microchip/samc21/bsp/config/hpl_port_config.h new file mode 100644 index 0000000000..1efce33e33 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/hpl_sercom_config.h b/bsp/microchip/samc21/bsp/config/hpl_sercom_config.h new file mode 100644 index 0000000000..a310177cd5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/hpl_sercom_config.h @@ -0,0 +1,259 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_4_USART_RXEN +#define CONF_SERCOM_4_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_4_USART_TXEN +#define CONF_SERCOM_4_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_4_USART_PARITY +#define CONF_SERCOM_4_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_4_USART_CHSIZE +#define CONF_SERCOM_4_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_4_USART_SBMODE +#define CONF_SERCOM_4_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_4_USART_BAUD +#define CONF_SERCOM_4_USART_BAUD 115200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG +#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_4_USART_RUNSTDBY +#define CONF_SERCOM_4_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_4_USART_IBON +#define CONF_SERCOM_4_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_4_USART_SFDE +#define CONF_SERCOM_4_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_4_USART_CLODEN +#define CONF_SERCOM_4_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_4_USART_MODE +#define CONF_SERCOM_4_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_4_USART_SAMPR +#define CONF_SERCOM_4_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_4_USART_SAMPA +#define CONF_SERCOM_4_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_4_USART_FRACTIONAL +#define CONF_SERCOM_4_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_4_USART_DORD +#define CONF_SERCOM_4_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_4_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_4_USART_ENC +#define CONF_SERCOM_4_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_4_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_4_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_4_USART_CMODE +#define CONF_SERCOM_4_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_4_USART_RXPO +#define CONF_SERCOM_4_USART_RXPO 3 /* RX is on PIN_PB11 */ +#endif + +#ifndef CONF_SERCOM_4_USART_TXPO +#define CONF_SERCOM_4_USART_TXPO 1 /* TX is on PIN_PB10 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_4_USART_PARITY == 0 +#define CONF_SERCOM_4_USART_PMODE 0 +#define CONF_SERCOM_4_USART_FORM 4 +#else +#define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 +#define CONF_SERCOM_4_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_4_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_4_USART_PARITY == 0 +#define CONF_SERCOM_4_USART_PMODE 0 +#define CONF_SERCOM_4_USART_FORM 0 +#else +#define CONF_SERCOM_4_USART_PMODE CONF_SERCOM_4_USART_PARITY - 1 +#define CONF_SERCOM_4_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_4_USART_SAMPR == 0 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 1 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 16)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 2 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 3 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 8)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_4_USART_SAMPR == 4 +#ifndef CONF_SERCOM_4_USART_BAUD_RATE +#define CONF_SERCOM_4_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/config/peripheral_clk_config.h b/bsp/microchip/samc21/bsp/config/peripheral_clk_config.h new file mode 100644 index 0000000000..94f49f8193 --- /dev/null +++ b/bsp/microchip/samc21/bsp/config/peripheral_clk_config.h @@ -0,0 +1,113 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 40001536 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM4_CORE_SRC +#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM4_SLOW_SRC +#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY + * \brief SERCOM4's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY +#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 40001536 +#endif + +/** + * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY + * \brief SERCOM4's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 4000000 +#endif + +// CAN0 Clock Source +// can_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CAN0. +#ifndef CONF_GCLK_CAN0_SRC +#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_CAN0_FREQUENCY + * \brief CAN0's Clock frequency + */ +#ifndef CONF_GCLK_CAN0_FREQUENCY +#define CONF_GCLK_CAN0_FREQUENCY 40001536 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/bsp/microchip/samc21/bsp/driver_init.c b/bsp/microchip/samc21/bsp/driver_init.c new file mode 100644 index 0000000000..aba61963fe --- /dev/null +++ b/bsp/microchip/samc21/bsp/driver_init.c @@ -0,0 +1,96 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct can_async_descriptor CAN_0; + +struct flash_descriptor FLASH_0; + +struct usart_sync_descriptor TARGET_IO; + +void FLASH_0_CLOCK_init(void) +{ + + hri_mclk_set_AHBMASK_NVMCTRL_bit(MCLK); +} + +void FLASH_0_init(void) +{ + FLASH_0_CLOCK_init(); + flash_init(&FLASH_0, NVMCTRL); +} + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PB10, PINMUX_PB10D_SERCOM4_PAD2); + + gpio_set_pin_function(PB11, PINMUX_PB11D_SERCOM4_PAD3); +} + +void TARGET_IO_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBCMASK_SERCOM4_bit(MCLK); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + usart_sync_init(&TARGET_IO, SERCOM4, (void *)NULL); + TARGET_IO_PORT_init(); +} + +void CAN_0_PORT_init(void) +{ + + gpio_set_pin_function(PA25, PINMUX_PA25G_CAN0_RX); + + gpio_set_pin_function(PA24, PINMUX_PA24G_CAN0_TX); +} +/** + * \brief CAN initialization function + * + * Enables CAN peripheral, clocks and initializes CAN driver + */ +void CAN_0_init(void) +{ + hri_mclk_set_AHBMASK_CAN0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, CAN0_GCLK_ID, CONF_GCLK_CAN0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + can_async_init(&CAN_0, CAN0); + CAN_0_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + // GPIO on PA15 + + gpio_set_pin_level(LED0, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(LED0, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF); + + FLASH_0_init(); + + TARGET_IO_init(); + CAN_0_init(); +} diff --git a/bsp/microchip/samc21/bsp/driver_init.h b/bsp/microchip/samc21/bsp/driver_init.h new file mode 100644 index 0000000000..e5e5ba5d1c --- /dev/null +++ b/bsp/microchip/samc21/bsp/driver_init.h @@ -0,0 +1,50 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +extern struct flash_descriptor FLASH_0; + +extern struct usart_sync_descriptor TARGET_IO; +extern struct can_async_descriptor CAN_0; + +void FLASH_0_init(void); +void FLASH_0_CLOCK_init(void); + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/bsp/microchip/samc21/bsp/examples/driver_examples.c b/bsp/microchip/samc21/bsp/examples/driver_examples.c new file mode 100644 index 0000000000..bbce78ed06 --- /dev/null +++ b/bsp/microchip/samc21/bsp/examples/driver_examples.c @@ -0,0 +1,145 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +static uint8_t src_data[128]; +static uint8_t chk_data[128]; +/** + * Example of using FLASH_0 to read and write Flash main array. + */ +void FLASH_0_example(void) +{ + uint32_t page_size; + uint16_t i; + + /* Init source data */ + page_size = flash_get_page_size(&FLASH_0); + + for (i = 0; i < page_size; i++) { + src_data[i] = i; + } + + /* Write data to flash */ + flash_write(&FLASH_0, 0x3200, src_data, page_size); + + /* Read data from flash */ + flash_read(&FLASH_0, 0x3200, chk_data, page_size); +} + +/** + * Example of using FLASH_0 to read and write Flash RWWEE array. + */ +void RWW_FLASH_0_example(void) +{ + uint32_t page_size; + uint16_t i; + + /* Init source data */ + page_size = _rww_flash_get_page_size(&FLASH_0.dev); + + for (i = 0; i < page_size; i++) { + src_data[i] = i; + } + + /* Write data to RWWEE flash */ + if (_rww_flash_write(&FLASH_0.dev, NVMCTRL_RWW_EEPROM_ADDR, src_data, page_size) != ERR_NONE) { + while (1) + ; /* Trap here when flash write error happen */ + } + + /* Read data from RWWEE flash */ + if (_rww_flash_read(&FLASH_0.dev, NVMCTRL_RWW_EEPROM_ADDR, chk_data, page_size) != ERR_NONE) { + while (1) + ; /* Trap here when flash read error happen */ + } + + /* Check data */ + for (i = 0; i < page_size; i++) { + if (src_data[i] != chk_data[i]) { + while (1) + ; /* Trap here when check error happen */ + } + } +} + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void CAN_0_tx_callback(struct can_async_descriptor *const descr) +{ + (void)descr; +} +void CAN_0_rx_callback(struct can_async_descriptor *const descr) +{ + struct can_message msg; + uint8_t data[64]; + msg.data = data; + can_async_read(descr, &msg); + return; +} + +/** + * Example of using CAN_0 to Encrypt/Decrypt datas. + */ +void CAN_0_example(void) +{ + struct can_message msg; + struct can_filter filter; + uint8_t send_data[4]; + send_data[0] = 0x00; + send_data[1] = 0x01; + send_data[2] = 0x02; + send_data[3] = 0x03; + + msg.id = 0x45A; + msg.type = CAN_TYPE_DATA; + msg.data = send_data; + msg.len = 4; + msg.fmt = CAN_FMT_STDID; + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)CAN_0_tx_callback); + can_async_enable(&CAN_0); + + /** + * CAN_0_tx_callback callback should be invoked after call + * can_async_write, and remote device should recieve message with ID=0x45A + */ + can_async_write(&CAN_0, &msg); + + msg.id = 0x100000A5; + msg.fmt = CAN_FMT_EXTID; + /** + * remote device should recieve message with ID=0x100000A5 + */ + can_async_write(&CAN_0, &msg); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)CAN_0_rx_callback); + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 1, CAN_FMT_EXTID, &filter); +} diff --git a/bsp/microchip/samc21/bsp/examples/driver_examples.h b/bsp/microchip/samc21/bsp/examples/driver_examples.h new file mode 100644 index 0000000000..fab317f6f0 --- /dev/null +++ b/bsp/microchip/samc21/bsp/examples/driver_examples.h @@ -0,0 +1,25 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void FLASH_0_example(void); +void RWW_FLASH_0_example(void); + +void TARGET_IO_example(void); + +void CAN_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/bsp/microchip/samc21/bsp/hal/documentation/can_async.rst b/bsp/microchip/samc21/bsp/hal/documentation/can_async.rst new file mode 100644 index 0000000000..7574b19ddb --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/documentation/can_async.rst @@ -0,0 +1,42 @@ +================================================= +CAN (Controller Area Network) Asynchronous Driver +================================================= + +The Controller Area Network (CAN) performs communication according to +ISO11898-1 (Bosch CAN specification 2.0 part A,B) + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* CAN message transfer: transmission, reception +* Callback on message transmited, recepted, error +* Callback on error warning, error active, error passive, bus off, data overrun +* Set CAN mode: normal, monitoring + +Applications +------------ + +Transmission and reception CAN meesage in a CAN Network. + +Dependencies +------------ + +CAN capable hardware compatible with the ISO11898-1 (Bosch CAN specification +2.0 part A,B) + +Concurrency +----------- + +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/samc21/bsp/hal/documentation/flash.rst b/bsp/microchip/samc21/bsp/hal/documentation/flash.rst new file mode 100644 index 0000000000..fcc86e63f8 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/documentation/flash.rst @@ -0,0 +1,52 @@ +The Flash Driver +================ + +Flash is a re-programmable memory that retains program and data +storage even with power off. + +User can write or read several bytes from any valid address in a flash. + +As to the erase/lock/unlock command, the input parameter of address should +be a bytes address aligned with the page start, otherwise, the command will fail +to be executed. At the meantime, the number of pages that can be locked or unlocked +at once depends on region size of the flash. User can get the real number +from the function return value which could be different for the different devices. + +Features +-------- + +* Initialization/de-initialization +* Writing/Reading bytes +* Locking/Unlocking/Erasing pages +* Notifications about errors or being ready for a new command + +Applications +------------ + +* Mini disk which can retain program and data storage +* Boot loader +* Non volatile storage + +Dependencies +------------ + +The peripheral which controls a re-programmable flash memory. + +Concurrency +----------- + +N/A + +Limitations +----------- + +User should pay attention to set a proper stack size in their application, +since the driver manages a temporary buffer in stack to cache unchanged data +when calling flash write and erase function. +Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, +write operation erazes row content before each write. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/samc21/bsp/hal/documentation/usart_sync.rst b/bsp/microchip/samc21/bsp/hal/documentation/usart_sync.rst new file mode 100644 index 0000000000..15e4b13885 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_atomic.h b/bsp/microchip/samc21/bsp/hal/include/hal_atomic.h new file mode 100644 index 0000000000..82151fc5d5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_can_async.h b/bsp/microchip/samc21/bsp/hal/include/hal_can_async.h new file mode 100644 index 0000000000..4ed993eb8f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_can_async.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_CAN_ASYNC_H_INCLUDED +#define HAL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \addtogroup doc_driver_hal_can_async + * + *@{ + */ + +/** + * \brief CAN Asynchronous descriptor + * + * The CAN descriptor forward declaration. + */ +struct can_async_descriptor; + +/** + * Callback for CAN interrupt + */ +typedef void (*can_cb_t)(struct can_async_descriptor *const descr); + +/** + * \brief CAN callbacks + */ +struct can_callbacks { + can_cb_t tx_done; + can_cb_t rx_done; + void (*irq_handler)(struct can_async_descriptor *const descr, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN descriptor + */ +struct can_async_descriptor { + struct _can_async_device dev; /*!< CAN HPL device descriptor */ + struct can_callbacks cb; /*!< CAN Interrupt Callbacks handler */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN descriptor. + * + * \param[in, out] descr A CAN descriptor to initialize. + * \param[in] hw The pointer to hardware instance. + * + * \return Initialization status. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given CAN descriptor. + * + * \param[in, out] descr The CAN descriptor to deinitialize. + * + * \return De-initialization status. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr); + +/** + * \brief Enable CAN + * + * This function enables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to enable. + * + * \return Enabling status. + */ +int32_t can_async_enable(struct can_async_descriptor *const descr); + +/** + * \brief Disable CAN + * + * This function disables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to disable. + * + * \return Disabling status. + */ +int32_t can_async_disable(struct can_async_descriptor *const descr); + +/** + * \brief Read a CAN message + * + * \param[in] descr The CAN descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] descr The CAN descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Register CAN callback function to interrupt + * + * \param[in] descr The CAN descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL will de-register any + * registered callback + * + * \return The status of callback assignment. + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb); + +/** + * \brief Return number of read errors + * + * This function returns the number of read errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of read errors. + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr); + +/** + * \brief Return number of write errors + * + * This function returns the number of write errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of write errors. + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr); + +/** + * \brief Set CAN to the specified mode + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] mode The CAN operation mode + * + * \return Status of the operation. + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode); + +/** + * \brief Set CAN Filter + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] index Index of Filter list + * \param[in] fmt CAN Indentify Type + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation. + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/** + * \brief Retrieve the current driver version + * + * \return The current driver version. + */ +uint32_t can_async_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_delay.h b/bsp/microchip/samc21/bsp/hal/include/hal_delay.h new file mode 100644 index 0000000000..9d4aa5c1bc --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_flash.h b/bsp/microchip/samc21/bsp/hal/include/hal_flash.h new file mode 100644 index 0000000000..8216afdec1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_flash.h @@ -0,0 +1,209 @@ +/** + * \file + * + * \brief Flash related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_FLASH_H_INCLUDED +#define _HAL_FLASH_H_INCLUDED + +#include + +/** + * \addtogroup doc_driver_hal_flash + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of flash_descriptor. */ +struct flash_descriptor; + +/** The callback types */ +enum flash_cb_type { + /** Callback type for ready to accept a new command */ + FLASH_CB_READY, + /** Callback type for error */ + FLASH_CB_ERROR, + FLASH_CB_N +}; + +/** \brief Prototype of callback on FLASH + * + */ +typedef void (*flash_cb_t)(struct flash_descriptor *const descr); + +/** \brief FLASH HAL callbacks + * + */ +struct flash_callbacks { + /** Callback invoked when ready to accept a new command */ + flash_cb_t cb_ready; + /** Callback invoked when error occurs */ + flash_cb_t cb_error; +}; + +/** \brief FLASH HAL driver struct for asynchronous access + */ +struct flash_descriptor { + /** Pointer to FLASH device instance */ + struct _flash_device dev; + /** Callbacks for asynchronous transfer */ + struct flash_callbacks callbacks; +}; + +/** \brief Initialize the FLASH HAL instance and hardware for callback mode + * + * Initialize FLASH HAL with interrupt mode (uses callbacks). + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] hw Pointer to the hardware base. + * \return Initialize status. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw); + +/** \brief Deinitialize the FLASH HAL instance + * + * Abort transfer, disable and reset FLASH, and deinitialize software. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \return Deinitialze status. + */ +int32_t flash_deinit(struct flash_descriptor *flash); + +/** \brief Writes a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to a buffer where the content + * will be written to the flash + * \param[in] length Number of bytes to write + * \return Write status. + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Appends a number of bytes to a page in the internal Flash + * + * This functions never erases the flash before writing. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write to flash + * \param[in] buffer Pointer to a buffer with data to write to flash + * \param[in] length Number of bytes to append + * \return Append status. + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Reads a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read pages will be stored + * \param[in] length Number of bytes to read + * \return Read status. + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** \brief Register a function as FLASH transfer completion callback + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] type Callback type (\ref flash_cb_type). + * \param[in] func Pointer to callback function. + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); + +/** \brief Execute lock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute erase in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** + * \brief Get the flash page size + * + * \param[in, out] flash Pointer to the HAL FLASH instance + * + * \return The flash page size + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash); + +/** + * \brief Get the number of flash page + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * + * \return The flash total page numbers + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t flash_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_gpio.h b/bsp/microchip/samc21/bsp/hal/include/hal_gpio.h new file mode 100644 index 0000000000..fbfa2d4aec --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_init.h b/bsp/microchip/samc21/bsp/hal/include/hal_init.h new file mode 100644 index 0000000000..d7bc6fe209 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_io.h b/bsp/microchip/samc21/bsp/hal/include/hal_io.h new file mode 100644 index 0000000000..f50401d7a6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_sleep.h b/bsp/microchip/samc21/bsp/hal/include/hal_sleep.h new file mode 100644 index 0000000000..b90ef6a5b6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hal_usart_sync.h b/bsp/microchip/samc21/bsp/hal/include/hal_usart_sync.h new file mode 100644 index 0000000000..1ef22fc63f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_can.h b/bsp/microchip/samc21/bsp/hal/include/hpl_can.h new file mode 100644 index 0000000000..80b53138d3 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_can.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_H_INCLUDED +#define HPL_CAN_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can CAN Common declaration + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN Message Format + */ +enum can_format { + CAN_FMT_STDID, /*!< Standard Format, 11 bits identifier */ + CAN_FMT_EXTID /*!< Extended Format, 29 bits identifier */ +}; + +/** + * \brief CAN Message Type + */ +enum can_type { + CAN_TYPE_DATA, /*!< A DATA FRAME carries data from a transmitter to the + receivers.*/ + CAN_TYPE_REMOTE /*!< A REMOTE FRAME is transmitted by a bus unit to request + the transmission of the DATA FRAME with the same + IDENTIFIER */ +}; + +/** + * \brief CAN Bus Mode + */ +enum can_mode { + /** Normal operation Mode */ + CAN_MODE_NORMAL, + /** In Bus Monitoring mode (see ISO11898-1, 10.12 Bus monitoring), the CAN + * is able to receive valid data frames and valid remote frames, but + * cannot start a transmission. In this mode, it sends only recessive bits + * on the CAN bus. If the CAN is required to send a dominant bit (ACK bit, + * overload flag, active error flag), the bit is rerouted internally so + * that the CAN monitors this dominant bit, although the CAN bus may + * remain in recessive state. + * The Bus Monitoring mode can be used to analyze the traffic on a CAN bus + * without affecting it by the transmission of dominant bits. + */ + CAN_MODE_MONITORING +}; + +/** + * \brief CAN Message + */ +struct can_message { + uint32_t id; /* Message identifier */ + enum can_type type; /* Message Type */ + uint8_t * data; /* Pointer to Message Data */ + uint8_t len; /* Message Length */ + enum can_format fmt; /* Identifier format, CAN_STD, CAN_EXT */ +}; + +/** + * \brief CAN Filter + */ +struct can_filter { + uint32_t id; /* Message identifier */ + uint32_t mask; /* The mask applied to the id */ +}; + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_can_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_can_async.h new file mode 100644 index 0000000000..ba82672549 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_can_async.h @@ -0,0 +1,245 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_ASYNC_H_INCLUDED +#define HPL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can_async CAN HPL Driver + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN device descriptor forware declaration + */ +struct _can_async_device; + +/** + * \brief CAN callback types + */ +enum can_async_callback_type { + CAN_ASYNC_RX_CB, /*!< A new message arrived */ + CAN_ASYNC_TX_CB, /*!< A message transmitted */ + CAN_ASYNC_IRQ_CB /*!< Message error of some kind on the CAN bus IRQ */ +}; + +enum can_async_interrupt_type { + CAN_IRQ_EW, /*!< Error warning, Error counter has reached the + error warning limit of 96, An error count value + greater than about 96 indicates a heavily disturbed + bus. It may be of advantage to provide means to test + for this condition. Refer to ISO 11898-1 (Bosch CAN + specification 2.0 part A,B) + */ + CAN_IRQ_EA, /*!< Error Active State, The CAN node normally take + part in bus communication and sends an ACTIVE ERROR + FLAG when an error has been detected. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_EP, /*!< Error Passive State, The Can node goes into error + passive state if at least one of its error counters is + greater than 127. It still takes part in bus + activities, but it sends a passive error frame only, + on errors. Refer to ISO 11898-1 (7) + */ + CAN_IRQ_BO, /*!< Bus Off State, The CAN node is 'bus off' when the + TRANSMIT ERROR COUNT is greater than or equal to 256. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_DO /*!< Data Overrun in receive queue. A message was lost + because the messages in the queue was not reading and + releasing fast enough. There is not enough space for + a new message in receive queue. + */ +}; +/** + * \brief CAN interrupt handlers structure + */ +struct _can_async_callback { + void (*tx_done)(struct _can_async_device *dev); + void (*rx_done)(struct _can_async_device *dev); + void (*irq_handler)(struct _can_async_device *dev, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN device descriptor + */ +struct _can_async_device { + void * hw; /*!< CAN hardware pointer */ + struct _can_async_callback cb; /*!< CAN interrupt handler */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * context; /*!< CAN hardware context */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN device descriptor. + * + * \param[in, out] dev A CAN device descriptor to initialize + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev); + +/** + * \brief Enable CAN + * + * This function enable CAN by the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to enable + * + * \return Enabling status. + */ +int32_t _can_async_enable(struct _can_async_device *const dev); + +/** + * \brief Disable CAN + * + * This function disable CAN by the given can device descriptor. + * + * \param[in] dev The CAN descriptor to disable + * + * \return Disabling status. + */ +int32_t _can_async_disable(struct _can_async_device *const dev); + +/** + * \brief Read a CAN message + * + * \param[in] dev The CAN device descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] dev The CAN device descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Set CAN Interrupt State + * + * \param[in] dev The CAN device descriptor + * \param[in] type Callback type + * \param[in] state ture for enable or false for disable + * + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state); + +/** + * \brief Return number of read errors + * + * This function return number of read errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of read errors. + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev); + +/** + * \brief Return number of write errors + * + * This function return number of write errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of write errors. + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] mode CAN operation mode + * + * \return Status of the operation + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] index Index of Filter list + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_core.h b/bsp/microchip/samc21/bsp/hal/include/hpl_core.h new file mode 100644 index 0000000000..9324c43e7c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_delay.h b/bsp/microchip/samc21/bsp/hal/include/hpl_delay.h new file mode 100644 index 0000000000..a0f1ac8125 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_div.h b/bsp/microchip/samc21/bsp/hal/include/hpl_div.h new file mode 100644 index 0000000000..f45f794b7b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_div.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Division operation related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DIV_H_INCLUDED +#define _HPL_DIV_H_INCLUDED + +/** + * \addtogroup HPL Div + * + * \section hpl_div_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize hardware for division operation + */ +void _div_init(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DIV_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_dma.h b/bsp/microchip/samc21/bsp/hal/include/hpl_dma.h new file mode 100644 index 0000000000..1e08434a16 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_flash.h b/bsp/microchip/samc21/bsp/hal/include/hpl_flash.h new file mode 100644 index 0000000000..3a42c4485b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_flash.h @@ -0,0 +1,265 @@ +/** + * \file + * + * \brief FLASH related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_FLASH_H_INCLUDED +#define _HPL_FLASH_H_INCLUDED + +/** + * \addtogroup hpl__flash__group FLASH HPL APIs + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief FLASH device structure + * + * The FLASH device structure forward declaration. + */ +struct _flash_device; + +/** The callback types */ +enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; + +/** + * \brief FLASH interrupt handlers structure + */ +struct _flash_callback { + /** Ready to accept new command handler */ + void (*ready_cb)(struct _flash_device *device); + /** Error handler */ + void (*error_cb)(struct _flash_device *device); +}; + +/** + * \brief FLASH descriptor device structure. + */ +struct _flash_device { + struct _flash_callback flash_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize FLASH. + * + * This function does low level FLASH configuration. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialize status. + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw); + +/** + * \brief Deinitialize FLASH. + * + * \param[in] device The pointer to FLASH device instance + */ +void _flash_deinit(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Appends a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer with data to write to flash + * \param[in] length Number of bytes to write + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Execute lock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief check whether the region which is pointed by address + * is locked + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to check + * + * \return The lock status of assigned address. + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); + +/** \brief Execute erase in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + */ +void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** + * \brief Get the flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the numbers of flash page. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Get the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The number of wait states for read and write operations + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device); + +/** + * \brief Set the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] state The number of wait states + * + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); + +/** + * \brief Enable/disable Flash interrupt + * + * param[in] device The pointer to Flash device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); + +/* + * Below RWW flash APIs are only available for device which has RWWEE + * flash array, such as SAM C20/C21/D21/L21/L22/R30/DA1/HA1 etc. + */ +/** + * \brief Get the RWWEE flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _rww_flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the total page numbers of RWWEE flash. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _rww_flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal RWWEE Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + * + * \return Read status, ERR_NONE for successful read. + */ +int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal RWWEE Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + * + * \return Write status, ERR_NONE for successful write. + */ +int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_gpio.h b/bsp/microchip/samc21/bsp/hal/include/hpl_gpio.h new file mode 100644 index 0000000000..5cdd387b89 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000000..8a9491debb --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000000..ce173ae29a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000000..92a5765d16 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000000..93b593456c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_init.h b/bsp/microchip/samc21/bsp/hal/include/hpl_init.h new file mode 100644 index 0000000000..71bf49c98e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_irq.h b/bsp/microchip/samc21/bsp/hal/include/hpl_irq.h new file mode 100644 index 0000000000..2894944a0d --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_missing_features.h b/bsp/microchip/samc21/bsp/hal/include/hpl_missing_features.h new file mode 100644 index 0000000000..7071db297c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_reset.h b/bsp/microchip/samc21/bsp/hal/include/hpl_reset.h new file mode 100644 index 0000000000..28e4c96246 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_reset.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + + RESET_REASON_POR = 1, + RESET_REASON_BODCORE = 2, + RESET_REASON_BODVDD = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_sleep.h b/bsp/microchip/samc21/bsp/hal/include/hpl_sleep.h new file mode 100644 index 0000000000..6731ec30e4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi.h new file mode 100644 index 0000000000..a5652e5061 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_async.h new file mode 100644 index 0000000000..8e5a84856c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000000..8d3555ed67 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_dma.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000000..2b48300ed5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000000..38df15b463 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000000..564724390c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000000..ff4c811af7 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_spi_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000000..dc88648f8e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_usart.h b/bsp/microchip/samc21/bsp/hal/include/hpl_usart.h new file mode 100644 index 0000000000..0e09501d7a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_usart_async.h b/bsp/microchip/samc21/bsp/hal/include/hpl_usart_async.h new file mode 100644 index 0000000000..3f833d1ae1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_usart_sync.h b/bsp/microchip/samc21/bsp/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000000..abc7264f2d --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/include/hpl_user_area.h b/bsp/microchip/samc21/bsp/hal/include/hpl_user_area.h new file mode 100644 index 0000000000..1f14098d80 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/include/hpl_user_area.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief Special user data area access + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USER_DATA_H_INCLUDED +#define _HPL_USER_DATA_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Read data from user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * \param[in] base The base address of the user area + * \param[in] offset The byte offset of the data to be read inside the area + * \param[out] buf Pointer to buffer to place the read data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes read. + * \retval ERR_NONE Data read successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); + +/** + * \brief Read no more than 32 bits data from user data area + * + * When reading bits, the bitfield can cross 32-bis boundaries. + * + * \param[in] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] n_bits Number of bits to read + * \return data read, assert if anything wrong (address not in user area + * offset, size error, etc.). + */ +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); + +/** + * \brief Write data to user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * When assigned offset and size exceeds the data area, error is reported. + * + * \param[out] base The base address of the user area + * \param[in] offset The offset of the data to be written inside the area + * \param[in] buf Pointer to buffer to place the written data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes writting. + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); + +/** + * \brief Write no more than 32 bits data to user data area + * + * When writting bits, the bitfield can cross 32-bis boundaries. + * + * \param[out] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] bits The data content + * \param[in] n_bits Number of bits to write + * \return Operation result + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_atomic.c b/bsp/microchip/samc21/bsp/hal/src/hal_atomic.c new file mode 100644 index 0000000000..f56418ee6f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_can_async.c b/bsp/microchip/samc21/bsp/hal/src/hal_can_async.c new file mode 100644 index 0000000000..84c75c45cd --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_can_async.c @@ -0,0 +1,230 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +#define DRIVER_VERSION 0x00000001u + +/** + * \internal Callback of CAN Message Write finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_tx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Message Read finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_rx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Interrupt + * + * \param[in] dev The pointer to CAN device structure + * \param[in] type Interrupt source type + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type); + +/** + * \brief Initialize CAN. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw) +{ + int32_t rc; + + ASSERT(descr && hw); + + rc = _can_async_init(&descr->dev, hw); + if (rc) { + return rc; + } + descr->dev.cb.tx_done = can_tx_done; + descr->dev.cb.rx_done = can_rx_done; + descr->dev.cb.irq_handler = can_irq_handler; + + return ERR_NONE; +} + +/** + * \brief Deinitialize CAN. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_deinit(&descr->dev); +} + +/** + * \brief Enable CAN + */ +int32_t can_async_enable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_enable(&descr->dev); +} + +/** + * \brief Disable CAN + */ +int32_t can_async_disable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_disable(&descr->dev); +} + +/** + * \brief Read a CAN message + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_read(&descr->dev, msg); +} + +/** + * \brief Write a CAN message + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_write(&descr->dev, msg); +} + +/** + * \brief Register CAN callback function to interrupt + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb) +{ + ASSERT(descr); + + switch (type) { + case CAN_ASYNC_RX_CB: + descr->cb.rx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_TX_CB: + descr->cb.tx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_IRQ_CB: + descr->cb.irq_handler + = (cb != NULL) ? (void (*)(struct can_async_descriptor *const, enum can_async_interrupt_type))cb : NULL; + break; + default: + return ERR_INVALID_ARG; + } + + _can_async_set_irq_state(&descr->dev, type, NULL != cb); + + return ERR_NONE; +} + +/** + * \brief Return number of read errors + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_rxerr(&descr->dev); +} + +/** + * \brief Return number of write errors + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_txerr(&descr->dev); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode) +{ + ASSERT(descr); + return _can_async_set_mode(&descr->dev, mode); +} + +/** + * \brief Set CAN filter + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + ASSERT(descr); + return _can_async_set_filter(&descr->dev, index, fmt, filter); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t can_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Callback of CAN Message Write finished + */ +static void can_tx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.tx_done) { + descr->cb.tx_done(descr); + } +} + +/** + * \internal Callback of CAN Message Read finished + */ +static void can_rx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.rx_done) { + descr->cb.rx_done(descr); + } +} + +/** + * \internal Callback of CAN Interrupt + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.irq_handler) { + descr->cb.irq_handler(descr, type); + } +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_delay.c b/bsp/microchip/samc21/bsp/hal/src/hal_delay.c new file mode 100644 index 0000000000..6f77cc7064 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_flash.c b/bsp/microchip/samc21/bsp/hal/src/hal_flash.c new file mode 100644 index 0000000000..b1a58b710e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_flash.c @@ -0,0 +1,314 @@ +/** + * \file + * + * \brief Flash functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_flash.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void flash_ready(struct _flash_device *device); +static void flash_error(struct _flash_device *device); + +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); + +/** + * \brief Initialize the FLASH HAL instance and hardware for callback mode. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw) +{ + int32_t rc; + + ASSERT(flash && hw); + + rc = _flash_init(&flash->dev, hw); + if (rc) { + return rc; + } + + flash->dev.flash_cb.ready_cb = flash_ready; + flash->dev.flash_cb.error_cb = flash_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize the FLASH HAL instance. + */ +int32_t flash_deinit(struct flash_descriptor *flash) +{ + ASSERT(flash); + + _flash_deinit(&flash->dev); + + return ERR_NONE; +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(&flash->dev, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Updates several bytes to the internal Flash + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_write(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Appends a number of bytes to a page in the internal Flash + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_append(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Execute erase in the internal flash + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + _flash_erase(&flash->dev, dst_addr, page_nums); + + return ERR_NONE; +} + +/** + * \brief Register a function as FLASH transfer completion callback + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) +{ + ASSERT(flash); + + switch (type) { + case FLASH_CB_READY: + flash->callbacks.cb_ready = func; + break; + + case FLASH_CB_ERROR: + flash->callbacks.cb_error = func; + break; + + default: + return ERR_INVALID_ARG; + } + + _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); + + return ERR_NONE; +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_lock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_unlock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Get the flash page size. + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_page_size(&flash->dev); +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_total_pages(&flash->dev); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t flash_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal check the address whether it is aligned + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] flash_addr address to be check in flash + * + * \return whether it is valid + * \retval 0 Valid. + * \retval -1 Error, invalid. + */ +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) +{ + ASSERT(flash); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + + /* Check if the read address not aligned to the start of a page */ + if (flash_addr & (page_size - 1)) { + return ERR_BAD_ADDRESS; + } + return ERR_NONE; +} + +/** + * \internal Ready for a new flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_ready(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_ready) { + descr->callbacks.cb_ready(descr); + } +} + +/** + * \internal Error occurs in flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_error(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_error) { + descr->callbacks.cb_error(descr); + } +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_gpio.c b/bsp/microchip/samc21/bsp/hal/src/hal_gpio.c new file mode 100644 index 0000000000..00dfea6f70 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_init.c b/bsp/microchip/samc21/bsp/hal/src/hal_init.c new file mode 100644 index 0000000000..fb65341fb6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_io.c b/bsp/microchip/samc21/bsp/hal/src/hal_io.c new file mode 100644 index 0000000000..7e8feb0453 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_sleep.c b/bsp/microchip/samc21/bsp/hal/src/hal_sleep.c new file mode 100644 index 0000000000..89472f156a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/samc21/bsp/hal/src/hal_usart_sync.c b/bsp/microchip/samc21/bsp/hal/src/hal_usart_sync.c new file mode 100644 index 0000000000..ab99c1d166 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/compiler.h b/bsp/microchip/samc21/bsp/hal/utils/include/compiler.h new file mode 100644 index 0000000000..f35db3df8e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/err_codes.h b/bsp/microchip/samc21/bsp/hal/utils/include/err_codes.h new file mode 100644 index 0000000000..a7aff01893 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/events.h b/bsp/microchip/samc21/bsp/hal/utils/include/events.h new file mode 100644 index 0000000000..3ee891a73e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/parts.h b/bsp/microchip/samc21/bsp/hal/utils/include/parts.h new file mode 100644 index 0000000000..a95358660a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "samc21.h" + +#include "hri_c21.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils.h new file mode 100644 index 0000000000..1cf2699690 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils_assert.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils_assert.h new file mode 100644 index 0000000000..c2328d6c31 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils_event.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils_event.h new file mode 100644 index 0000000000..13067c4fec --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils_increment_macro.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000000..464c6cbb72 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils_list.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils_list.h new file mode 100644 index 0000000000..977e8ccad4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/include/utils_repeat_macro.h b/bsp/microchip/samc21/bsp/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000000..89e6f52d5b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/bsp/microchip/samc21/bsp/hal/utils/src/utils_assert.c b/bsp/microchip/samc21/bsp/hal/utils/src/utils_assert.c new file mode 100644 index 0000000000..b376c9700f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/bsp/microchip/samc21/bsp/hal/utils/src/utils_event.c b/bsp/microchip/samc21/bsp/hal/utils/src/utils_event.c new file mode 100644 index 0000000000..d1af9d0cf1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/bsp/microchip/samc21/bsp/hal/utils/src/utils_list.c b/bsp/microchip/samc21/bsp/hal/utils/src/utils_list.c new file mode 100644 index 0000000000..4006a01933 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/bsp/microchip/samc21/bsp/hal/utils/src/utils_syscalls.c b/bsp/microchip/samc21/bsp/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000000..d8c6357e15 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} +#if 0 +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} +#endif +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/bsp/microchip/samc21/bsp/hpl/can/hpl_can.c b/bsp/microchip/samc21/bsp/hpl/can/hpl_can.c new file mode 100644 index 0000000000..cb2615d46d --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/can/hpl_can.c @@ -0,0 +1,423 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +#ifdef CONF_CAN0_ENABLED +COMPILER_ALIGNED(4) +uint8_t can0_rx_fifo[CONF_CAN0_F0DS * CONF_CAN0_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can0_tx_fifo[CONF_CAN0_TBDS * CONF_CAN0_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can0_tx_event_fifo[CONF_CAN0_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can0_rx_std_filter[CONF_CAN0_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can0_rx_ext_filter[CONF_CAN0_XIDFC_LSS]; + +struct _can_context _can0_context = {.rx_fifo = can0_rx_fifo, + .tx_fifo = can0_tx_fifo, + .tx_event = can0_tx_event_fifo, + .rx_std_filter = can0_rx_std_filter, + .rx_ext_filter = can0_rx_ext_filter}; +static struct _can_async_device *_can0_dev = NULL; /*!< Pointer to hpl device */ + +#endif /* CONF_CAN0_ENABLED */ + +#ifdef CONF_CAN1_ENABLED +COMPILER_ALIGNED(4) +uint8_t can1_rx_fifo[CONF_CAN1_F0DS * CONF_CAN1_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can1_tx_fifo[CONF_CAN1_TBDS * CONF_CAN1_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can1_tx_event_fifo[CONF_CAN1_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can1_rx_std_filter[CONF_CAN1_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can1_rx_ext_filter[CONF_CAN1_XIDFC_LSS]; + +struct _can_context _can1_context = {.rx_fifo = can1_rx_fifo, + .tx_fifo = can1_tx_fifo, + .tx_event = can1_tx_event_fifo, + .rx_std_filter = can1_rx_std_filter, + .rx_ext_filter = can1_rx_ext_filter}; +static struct _can_async_device *_can1_dev = NULL; /*!< Pointer to hpl device */ + +#endif /* CONF_CAN1_ENABLED */ + +/** + * \brief Initialize CAN. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw) +{ + dev->hw = hw; + hri_can_set_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_can_set_CCCR_CCE_bit(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (hw == CAN0) { + _can0_dev = dev; + dev->context = (void *)&_can0_context; + hri_can_set_CCCR_reg(dev->hw, CONF_CAN0_CCCR_REG); + hri_can_write_MRCFG_reg(dev->hw, CONF_CAN0_MRCFG_REG); + hri_can_write_NBTP_reg(dev->hw, CONF_CAN0_BTP_REG); + hri_can_write_DBTP_reg(dev->hw, CONF_CAN0_DBTP_REG); + hri_can_write_RXF0C_reg(dev->hw, CONF_CAN0_RXF0C_REG | CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo)); + hri_can_write_RXESC_reg(dev->hw, CONF_CAN0_RXESC_REG); + hri_can_write_TXESC_reg(dev->hw, CONF_CAN0_TXESC_REG); + hri_can_write_TXBC_reg(dev->hw, CONF_CAN0_TXBC_REG | CAN_TXBC_TBSA((uint32_t)can0_tx_fifo)); + hri_can_write_TXEFC_reg(dev->hw, CONF_CAN0_TXEFC_REG | CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo)); + hri_can_write_GFC_reg(dev->hw, CONF_CAN0_GFC_REG); + hri_can_write_SIDFC_reg(dev->hw, CONF_CAN0_SIDFC_REG | CAN_SIDFC_FLSSA((uint32_t)can0_rx_std_filter)); + hri_can_write_XIDFC_reg(dev->hw, CONF_CAN0_XIDFC_REG | CAN_XIDFC_FLESA((uint32_t)can0_rx_ext_filter)); + hri_can_write_XIDAM_reg(dev->hw, CONF_CAN0_XIDAM_REG); + + NVIC_DisableIRQ(CAN0_IRQn); + NVIC_ClearPendingIRQ(CAN0_IRQn); + NVIC_EnableIRQ(CAN0_IRQn); + hri_can_write_ILE_reg(dev->hw, CAN_ILE_EINT0); + } +#endif + +#ifdef CONF_CAN1_ENABLED + if (hw == CAN1) { + _can1_dev = dev; + dev->context = (void *)&_can1_context; + hri_can_set_CCCR_reg(dev->hw, CONF_CAN1_CCCR_REG); + hri_can_write_MRCFG_reg(dev->hw, CONF_CAN1_MRCFG_REG); + hri_can_write_NBTP_reg(dev->hw, CONF_CAN1_BTP_REG); + hri_can_write_DBTP_reg(dev->hw, CONF_CAN1_DBTP_REG); + hri_can_write_RXF0C_reg(dev->hw, CONF_CAN1_RXF0C_REG | CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo)); + hri_can_write_RXESC_reg(dev->hw, CONF_CAN1_RXESC_REG); + hri_can_write_TXESC_reg(dev->hw, CONF_CAN1_TXESC_REG); + hri_can_write_TXBC_reg(dev->hw, CONF_CAN1_TXBC_REG | CAN_TXBC_TBSA((uint32_t)can1_tx_fifo)); + hri_can_write_TXEFC_reg(dev->hw, CONF_CAN1_TXEFC_REG | CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo)); + hri_can_write_GFC_reg(dev->hw, CONF_CAN1_GFC_REG); + hri_can_write_SIDFC_reg(dev->hw, CONF_CAN1_SIDFC_REG | CAN_SIDFC_FLSSA((uint32_t)can1_rx_std_filter)); + hri_can_write_XIDFC_reg(dev->hw, CONF_CAN1_XIDFC_REG | CAN_XIDFC_FLESA((uint32_t)can1_rx_ext_filter)); + hri_can_write_XIDAM_reg(dev->hw, CONF_CAN1_XIDAM_REG); + + NVIC_DisableIRQ(CAN1_IRQn); + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_EnableIRQ(CAN1_IRQn); + hri_can_write_ILE_reg(dev->hw, CAN_ILE_EINT0); + } +#endif + + /* Disable CCE to prevent Configuration Change */ + hri_can_clear_CCCR_CCE_bit(dev->hw); + hri_can_clear_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw)) { + }; + + return ERR_NONE; +} + +/** + * \brief De-initialize CAN. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + dev->hw = NULL; + return ERR_NONE; +} + +/** + * \brief Enable CAN + */ +int32_t _can_async_enable(struct _can_async_device *const dev) +{ + hri_can_clear_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Disable CAN + */ +int32_t _can_async_disable(struct _can_async_device *const dev) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Read a CAN message + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_rx_fifo_entry *f = NULL; + hri_can_rxf0s_reg_t get_index; + + if (!hri_can_read_RXF0S_F0FL_bf(dev->hw)) { + return ERR_NOT_FOUND; + } + + get_index = hri_can_read_RXF0S_F0GI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == CAN0) { + f = (struct _can_rx_fifo_entry *)(can0_rx_fifo + get_index * CONF_CAN0_F0DS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == CAN1) { + f = (struct _can_rx_fifo_entry *)(can1_rx_fifo + get_index * CONF_CAN1_F0DS); + } +#endif + + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (f->R0.bit.XTD == 1) { + msg->fmt = CAN_FMT_EXTID; + msg->id = f->R0.bit.ID; + } else { + msg->fmt = CAN_FMT_STDID; + /* A standard identifier is stored into ID[28:18] */ + msg->id = f->R0.bit.ID >> 18; + } + + if (f->R0.bit.RTR == 1) { + msg->type = CAN_TYPE_REMOTE; + } + + const uint8_t dlc2len[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + msg->len = dlc2len[f->R1.bit.DLC]; + + memcpy(msg->data, f->data, msg->len); + + hri_can_write_RXF0A_F0AI_bf(dev->hw, get_index); + + return ERR_NONE; +} + +/** + * \brief Write a CAN message + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_tx_fifo_entry *f = NULL; + hri_can_txfqs_reg_t put_index; + + if (hri_can_get_TXFQS_TFQF_bit(dev->hw)) { + return ERR_NO_RESOURCE; + } + + put_index = hri_can_read_TXFQS_TFQPI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == CAN0) { + f = (struct _can_tx_fifo_entry *)(can0_tx_fifo + put_index * CONF_CAN0_TBDS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == CAN1) { + f = (struct _can_tx_fifo_entry *)(can1_tx_fifo + put_index * CONF_CAN1_TBDS); + } +#endif + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (msg->fmt == CAN_FMT_EXTID) { + f->T0.val = msg->id; + f->T0.bit.XTD = 1; + } else { + /* A standard identifier is stored into ID[28:18] */ + f->T0.val = msg->id << 18; + } + + if (msg->len <= 8) { + f->T1.bit.DLC = msg->len; + } else if (msg->len <= 12) { + f->T1.bit.DLC = 0x9; + } else if (msg->len <= 16) { + f->T1.bit.DLC = 0xA; + } else if (msg->len <= 20) { + f->T1.bit.DLC = 0xB; + } else if (msg->len <= 24) { + f->T1.bit.DLC = 0xC; + } else if (msg->len <= 32) { + f->T1.bit.DLC = 0xD; + } else if (msg->len <= 48) { + f->T1.bit.DLC = 0xE; + } else if (msg->len <= 64) { + f->T1.bit.DLC = 0xF; + } + + f->T1.bit.FDF = hri_can_get_CCCR_FDOE_bit(dev->hw); + f->T1.bit.BRS = hri_can_get_CCCR_BRSE_bit(dev->hw); + + memcpy(f->data, msg->data, msg->len); + + hri_can_write_TXBAR_reg(dev->hw, 1 << hri_can_read_TXFQS_TFQPI_bf(dev->hw)); + return ERR_NONE; +} + +/** + * \brief Set CAN Interrupt State + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state) +{ + uint32_t ie; + + if (type == CAN_ASYNC_RX_CB) { + hri_can_write_IE_RF0NE_bit(dev->hw, state); + } else if (type == CAN_ASYNC_TX_CB) { + hri_can_write_IE_TCE_bit(dev->hw, state); + hri_can_write_TXBTIE_reg(dev->hw, CAN_TXBTIE_MASK); + } else if (type == CAN_ASYNC_IRQ_CB) { + ie = hri_can_get_IE_reg(dev->hw, CAN_IE_RF0NE | CAN_IE_TCE); + hri_can_write_IE_reg(dev->hw, ie | CONF_CAN0_IE_REG); + } + + return; +} + +/** + * \brief Return number of read errors + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev) +{ + return hri_can_read_ECR_REC_bf(dev->hw); +} + +/** + * \brief Return number of write errors + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev) +{ + return hri_can_read_ECR_TEC_bf(dev->hw); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_can_set_CCCR_CCE_bit(dev->hw); + + if (mode == CAN_MODE_MONITORING) { + hri_can_set_CCCR_MON_bit(dev->hw); + } else { + hri_can_clear_CCCR_MON_bit(dev->hw); + } + + /* Disable CCE to prevent Configuration Change */ + hri_can_clear_CCCR_CCE_bit(dev->hw); + hri_can_clear_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw)) + ; + + return ERR_NONE; +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + struct _can_standard_message_filter_element *sf; + struct _can_extended_message_filter_element *ef; + + sf = &((struct _can_context *)dev->context)->rx_std_filter[index]; + ef = &((struct _can_context *)dev->context)->rx_ext_filter[index]; + + if (fmt == CAN_FMT_STDID) { + if (filter == NULL) { + sf->S0.val = 0; + return ERR_NONE; + } + sf->S0.val = filter->mask; + sf->S0.bit.SFID1 = filter->id; + sf->S0.bit.SFT = _CAN_SFT_CLASSIC; + sf->S0.bit.SFEC = _CAN_SFEC_STF0M; + } else if (fmt == CAN_FMT_EXTID) { + if (filter == NULL) { + ef->F0.val = 0; + return ERR_NONE; + } + ef->F0.val = filter->id; + ef->F0.bit.EFEC = _CAN_EFEC_STF0M; + ef->F1.val = filter->mask; + ef->F1.bit.EFT = _CAN_EFT_CLASSIC; + } + + return ERR_NONE; +} + +/* + * \brief CAN interrupt handler + */ +void CAN0_Handler(void) +{ + struct _can_async_device *dev = _can0_dev; + uint32_t ir; + ir = hri_can_read_IR_reg(dev->hw); + + if (ir & CAN_IR_RF0N) { + dev->cb.rx_done(dev); + } + + if (ir & CAN_IR_TC) { + dev->cb.tx_done(dev); + } + + if (ir & CAN_IR_BO) { + dev->cb.irq_handler(dev, CAN_IRQ_BO); + } + + if (ir & CAN_IR_EW) { + dev->cb.irq_handler(dev, CAN_IRQ_EW); + } + + if (ir & CAN_IR_EP) { + dev->cb.irq_handler(dev, hri_can_get_PSR_EP_bit(dev->hw) ? CAN_IRQ_EP : CAN_IRQ_EA); + } + + if (ir & CAN_IR_RF0L) { + dev->cb.irq_handler(dev, CAN_IRQ_DO); + } + + hri_can_write_IR_reg(dev->hw, ir); +} diff --git a/bsp/microchip/samc21/bsp/hpl/can/hpl_can_base.h b/bsp/microchip/samc21/bsp/hpl/can/hpl_can_base.h new file mode 100644 index 0000000000..8e820d6a6a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/can/hpl_can_base.h @@ -0,0 +1,204 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_BASE_H_INCLUDED +#define HPL_CAN_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief CAN receive FIFO element. + */ +struct _can_rx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R0; + __IO union { + struct { + uint32_t RXTS : 16; /*!< Rx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t : 2; /*!< Reserved */ + uint32_t FIDX : 7; /*!< Filter Index */ + uint32_t ANMF : 1; /*!< Accepted Non-matching Frame */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit FIFO element. + */ +struct _can_tx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T0; + __IO union { + struct { + uint32_t : 16; /*!< Reserved */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t : 1; /*!< Reserved */ + uint32_t EFC : 1; /*!< Event FIFO Control */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit Event element. + */ +struct _can_tx_event_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R0; + __IO union { + struct { + uint32_t TXTS : 16; /*!< Tx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t ET : 2; /*!< Event Type */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R1; +}; + +/** + * \brief CAN standard message ID filter element structure. + * + * Common element structure for standard message ID filter element. + */ +struct _can_standard_message_filter_element { + __IO union { + struct { + uint32_t SFID2 : 11; /*!< Standard Filter ID 2 */ + uint32_t : 5; /*!< Reserved */ + uint32_t SFID1 : 11; /*!< Standard Filter ID 1 */ + uint32_t SFEC : 3; /*!< Standard Filter Configuration */ + uint32_t SFT : 2; /*!< Standard Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } S0; +}; + +#define _CAN_SFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_SFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_SFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_SFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_SFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_SFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_SFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_SFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_SFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_SFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_SFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ + +#define _CAN_EFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_EFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_EFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_EFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_EFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_EFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_EFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_EFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_EFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_EFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_EFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ +/** + * \brief CAN extended message ID filter element structure. + * + * Common element structure for extended message ID filter element. + */ +struct _can_extended_message_filter_element { + __IO union { + struct { + uint32_t EFID1 : 29; /*!< bit: Extended Filter ID 1 */ + uint32_t EFEC : 3; /*!< bit: Extended Filter Configuration */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F0; + __IO union { + struct { + uint32_t EFID2 : 29; /*!< bit: Extended Filter ID 2 */ + uint32_t : 1; /*!< bit: Reserved */ + uint32_t EFT : 2; /*!< bit: Extended Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F1; +}; + +struct _can_context { + uint8_t * rx_fifo; /*!< receive message fifo */ + uint8_t * tx_fifo; /*!< transfer message fifo */ + struct _can_tx_event_entry *tx_event; /*!< transfer event fifo */ + /* Standard filter List */ + struct _can_standard_message_filter_element *rx_std_filter; + /* Extended filter List */ + struct _can_extended_message_filter_element *rx_ext_filter; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_BASE_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hpl/core/hpl_core_m0plus_base.c b/bsp/microchip/samc21/bsp/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 0000000000..28d799ec36 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined __GNUC__ + __asm(".syntax unified\n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#endif +#endif +} diff --git a/bsp/microchip/samc21/bsp/hpl/core/hpl_core_port.h b/bsp/microchip/samc21/bsp/hpl/core/hpl_core_port.h new file mode 100644 index 0000000000..3f3e8f282e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hpl/core/hpl_init.c b/bsp/microchip/samc21/bsp/hpl/core/hpl_init.c new file mode 100644 index 0000000000..367e1429a2 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/core/hpl_init.c @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +/* Referenced GCLKs (out of 0~7), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x000000FF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + + _div_init(); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif +} diff --git a/bsp/microchip/samc21/bsp/hpl/divas/hpl_divas.c b/bsp/microchip/samc21/bsp/hpl/divas/hpl_divas.c new file mode 100644 index 0000000000..2a39ac3134 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/divas/hpl_divas.c @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Division operation related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#include +#define _DIVAS_CRITICAL_ENTER() \ + do { \ + volatile hal_atomic_t _divas_atomic; \ + _divas_atomic = __get_PRIMASK(); \ + __disable_irq(); +#define _DIVAS_CRITICAL_LEAVE() \ + __set_PRIMASK(_divas_atomic); \ + } \ + while (0) + +/** Return 32 bit result, the result only. */ +#define _divas_result32() (DIVAS->RESULT.reg) + +/** Return 64 bit result, the result and remainder. */ +#define _divas_result64() (*((uint64_t *)(&DIVAS->RESULT.reg))) + +/** \brief Execute hardware for division + * \param[in] s Indicate operation mode: signed/unsigned + * \param[in] n The dividend + * \param[in] d The divisor + */ +static inline void _divas_div(const uint8_t s, const uint32_t n, const uint32_t d) +{ + DIVAS->CTRLA.bit.SIGNED = s; + DIVAS->DIVIDEND.reg = n; + DIVAS->DIVISOR.reg = d; + while (DIVAS->STATUS.bit.BUSY) { + /* Wait the division is complete. */ + } +} + +/** + * \brief Initialize hardware for division operation + */ +void _div_init(void) +{ + hri_divas_write_CTRLA_DLZ_bit(DIVAS, CONF_DIVAS_DLZ); +} + +/** + * \brief Do signed division + */ +int32_t __aeabi_idiv(int32_t numerator, int32_t denominator) +{ + int32_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(1, numerator, denominator); + res = _divas_result32(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do unsigned division + */ +uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator) +{ + uint32_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(0, numerator, denominator); + res = _divas_result32(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do signed division, return result and remainder + */ +uint64_t __aeabi_idivmod(int numerator, int denominator) +{ + uint64_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(1, numerator, denominator); + res = _divas_result64(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} + +/** + * \brief Do unsigned division, return result and remainder + */ +uint64_t __aeabi_uidivmod(unsigned numerator, unsigned denominator) +{ + uint64_t res; + _DIVAS_CRITICAL_ENTER(); + _divas_div(0, numerator, denominator); + res = _divas_result64(); + _DIVAS_CRITICAL_LEAVE(); + return res; +} diff --git a/bsp/microchip/samc21/bsp/hpl/dmac/hpl_dmac.c b/bsp/microchip/samc21/bsp/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000000..153c0f3098 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/dmac/hpl_dmac.c @@ -0,0 +1,244 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_QOSCTRL_reg(DMAC, + DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) + | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static inline void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); + uint8_t flag_status; + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); + + if (flag_status & DMAC_CHINTFLAG_TERR) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } + hri_dmac_write_CHID_reg(DMAC, current_channel); +} + +/** + * \brief DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk.c b/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000000..f93ec0c9e0 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk.c @@ -0,0 +1,246 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif +} diff --git a/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk_base.h b/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000000..3e7d282576 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hpl/mclk/hpl_mclk.c b/bsp/microchip/samc21/bsp/hpl/mclk/hpl_mclk.c new file mode 100644 index 0000000000..bb079d857a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/mclk/hpl_mclk.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); +} diff --git a/bsp/microchip/samc21/bsp/hpl/nvmctrl/hpl_nvmctrl.c b/bsp/microchip/samc21/bsp/hpl/nvmctrl/hpl_nvmctrl.c new file mode 100644 index 0000000000..c1d42c5e8f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/nvmctrl/hpl_nvmctrl.c @@ -0,0 +1,782 @@ + +/** + * \file + * + * \brief Non-Volatile Memory Controller + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) + +/** + * \brief NVM configuration type + */ +struct nvm_configuration { + hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */ +}; + +/** + * \brief Array of NVM configurations + */ +static struct nvm_configuration _nvm + = {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos) + | (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)}; + +/*!< Pointer to hpl device */ +static struct _flash_device *_nvm_dev = NULL; + +static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd); +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, + uint32_t nvmctrl_cmd); + +/** + * \brief Initialize NVM + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw) +{ + ASSERT(device && (hw == NVMCTRL)); + uint32_t ctrlb; + + device->hw = hw; + ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb); + + _nvm_dev = device; + NVIC_DisableIRQ(NVMCTRL_IRQn); + NVIC_ClearPendingIRQ(NVMCTRL_IRQn); + NVIC_EnableIRQ(NVMCTRL_IRQn); + return ERR_NONE; +} + +/** + * \brief De-initialize NVM + */ +void _flash_deinit(struct _flash_device *const device) +{ + device->hw = NULL; + NVIC_DisableIRQ(NVMCTRL_IRQn); +} + +/** + * \brief Get the flash page size. + */ +uint32_t _flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)FLASH_NB_OF_PAGES; +} + +/** + * \brief Get the number of wait states for read and write operations. + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device) +{ + return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk); +} + +/** + * \brief Set the number of wait states for read and write operations. + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) +{ + hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state); +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash. + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t nvm_address = src_addr / 2; + uint32_t i; + uint16_t data; + + /* Check if the module is busy */ + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + /* Check whether byte address is word-aligned*/ + if (src_addr % 2) { + data = NVM_MEMORY[nvm_address++]; + buffer[0] = data >> 8; + i = 1; + } else { + i = 0; + } + + /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy + * to ensure alignment */ + while (i < length) { + data = NVM_MEMORY[nvm_address++]; + buffer[i] = (data & 0xFF); + if (i < (length - 1)) { + buffer[i + 1] = (data >> 8); + } + i += 2; + } +} + +/** + * \brief Writes a number of bytes to a page in the internal Flash. + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr, row_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + do { + row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= row_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + if (0 == k) { + j++; + } + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_program(device->hw, + row_start_addr + i * NVMCTRL_PAGE_SIZE, + tmp_buffer[i], + NVMCTRL_PAGE_SIZE, + NVMCTRL_CTRLA_CMD_WP); + } + + } while (row_end_addr < (wr_start_addr + length - 1)); +} + +/** + * \brief Appends a number of bytes in the internal Flash. + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); + uint32_t size; + uint32_t offset = 0; + + if (dst_addr != page_start_addr) { + /* Need to write some data to the end of a page */ + size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); + _flash_program(device->hw, dst_addr, buffer, size, NVMCTRL_CTRLA_CMD_WP); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } + + while (offset < length) { + size = min(length - offset, NVMCTRL_PAGE_SIZE); + _flash_program(device->hw, page_start_addr, buffer + offset, size, NVMCTRL_CTRLA_CMD_WP); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } +} + +/** + * \brief Execute erase in the internal flash + */ +void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) +{ + uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr; + uint32_t i; + + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); + + /* when address is not aligned with row start address */ + if (dst_addr != row_start_addr) { + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) { + _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + if (--page_nums == 0) { + return; + } + dst_addr += NVMCTRL_PAGE_SIZE; + if (dst_addr == row_start_addr) { + break; + } + } + } + + while (page_nums >= NVMCTRL_ROW_PAGES) { + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_ER); + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + page_nums -= NVMCTRL_ROW_PAGES; + } + + if (page_nums != 0) { + for (i = 0; i < page_nums; i++) { + _flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + row_start_addr += NVMCTRL_PAGE_SIZE; + } + } +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief check whether the region which is pointed by address + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) +{ + uint16_t region_id; + + /* Get region for given page */ + region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16); + + return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id)); +} + +/** + * \brief Enable/disable Flash interrupt + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) +{ + ASSERT(device); + + if (FLASH_DEVICE_CB_READY == type) { + hri_nvmctrl_write_INTEN_READY_bit(device->hw, state); + } else if (FLASH_DEVICE_CB_ERROR == type) { + hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal erase a row in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to erase + */ +static void _flash_erase_row(void *const hw, const uint32_t dst_addr, uint32_t nvmctrl_cmd) +{ + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + /* Set address and command */ + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal write a page in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to write + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] size The size of data to write to a page + */ +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size, + uint32_t nvmctrl_cmd) +{ + ASSERT(!(dst_addr % 2)); + + uint32_t nvm_address = dst_addr / 2; + uint16_t i, data; + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + for (i = 0; i < size; i += 2) { + data = buffer[i]; + if (i < NVMCTRL_PAGE_SIZE - 1) { + data |= (buffer[i + 1] << 8); + } + NVM_MEMORY[nvm_address++] = data; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, nvmctrl_cmd | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal NVM interrupt handler + */ +void NVMCTRL_Handler(void) +{ + void *const hw = _nvm_dev->hw; + + if (hri_nvmctrl_get_interrupt_READY_bit(hw)) { + if (NULL != _nvm_dev->flash_cb.ready_cb) { + _nvm_dev->flash_cb.ready_cb(_nvm_dev); + } + } else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) { + hri_nvmctrl_clear_interrupt_ERROR_bit(hw); + if (NULL != _nvm_dev->flash_cb.error_cb) { + _nvm_dev->flash_cb.error_cb(_nvm_dev); + } + } +} + +/* +The NVM User Row contains calibration data that are automatically read at device +power on. +The NVM User Row can be read at address 0x804000. +*/ +#ifndef _NVM_USER_ROW_BASE +#define _NVM_USER_ROW_BASE 0x804000 +#endif +#define _NVM_USER_ROW_N_BITS 64 +#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) +#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) +#define _IS_NVM_USER_ROW(b) \ + (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) +#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) + +/* +The NVM Software Calibration Area can be read at address 0x806020. +The NVM Software Calibration Area can not be written. +*/ +#ifndef _NVM_SW_CALIB_AREA_BASE +#define _NVM_SW_CALIB_AREA_BASE 0x806020 +#endif +#define _NVM_SW_CALIB_AREA_N_BITS 128 +#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) +#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) +#define _IS_NVM_SW_CALIB_AREA(b) \ + (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) +#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) + +/** + * \internal Read left aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return base[bit_offset >> 5] & ((1 << n_bits) - 1); +} + +/** + * \internal Read right aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); +} + +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) +{ + ASSERT(buf); + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Copy data */ + memcpy(buf, ((uint8_t *)base) + offset, size); + return ERR_NONE; +} + +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) +{ + volatile uint32_t *mem_base = (volatile uint32_t *)base; + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) + && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); + } else { + ASSERT(false); + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are read from 32-bit aligned address + * and then combined together. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) + + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); +} + +/** \internal Write 64-bit user row + * \param[in] _row Pointer to 64-bit user row data. + */ +static int32_t _user_row_write_exec(const uint32_t *_row) +{ + Nvmctrl *hw = NVMCTRL; + uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL); + + /* Denie if Security Bit is set */ + if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) { + return ERR_DENIED; + } + + /* Do Save */ + + /* - Prepare. */ + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + hri_nvmctrl_set_CTRLB_MANW_bit(hw); + + /* - Erase AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* - Page buffer clear & write. */ + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0]; + *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1]; + + /* - Write AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)(_NVM_USER_ROW_BASE / 2)); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* Restore CTRLB */ + hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb); + + return ERR_NONE; +} + +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) +{ + uint32_t _row[2]; /* Copy of user row. */ + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + memcpy(_row, base, 8); /* Store previous data. */ + memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ + + return _user_row_write_exec(_row); +} + +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) +{ + uint32_t _row[2]; /* Copy of user row. */ + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are splitted for 32-bit aligned address + * and then saved. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + + memcpy(_row, base, 8); /* Store previous data. */ + if (l_bits) { + uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); + _row[bit_offset >> 5] &= ~l_mask; + _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; + } + if (r_bits) { + uint32_t r_mask = (1 << r_bits) - 1; + _row[r_off >> 5] &= ~r_mask; + _row[r_off >> 5] |= bits >> l_bits; + } + return _user_row_write_exec(_row); +} + +/** + * \brief Return if given address is in Flash RWWEE array range. + */ +static bool _is_valid_rww_flash_address(uint32_t addr) +{ +#define RWWEE_ADDR_START NVMCTRL_RWW_EEPROM_ADDR +#define RWWEE_ADDR_END (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES) + + if ((addr < NVMCTRL_RWW_EEPROM_ADDR) + || (addr > (NVMCTRL_RWW_EEPROM_ADDR + NVMCTRL_PAGE_SIZE * NVMCTRL_RWWEE_PAGES))) { + return false; + } + return true; +} + +/** + * \brief Get the RWWEE flash page size. + */ +uint32_t _rww_flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the total page numbers of RWWEE flash. + */ +uint32_t _rww_flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_RWWEE_PAGES; +} + +/** + * \brief Reads a number of bytes in the internal RWWEE Flash. + */ +int32_t _rww_flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + /* Check if the address is valid */ + if (!_is_valid_rww_flash_address(src_addr) || !_is_valid_rww_flash_address(src_addr + length)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(device, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Writes a number of bytes in the internal RWWEE Flash. + */ +int32_t _rww_flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr, row_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + /* Check if the address is valid */ + if (!_is_valid_rww_flash_address(dst_addr) || !_is_valid_rww_flash_address(dst_addr + length)) { + return ERR_BAD_ADDRESS; + } + + do { + row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _rww_flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= row_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + if (0 == k) { + j++; + } + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_row(device->hw, row_start_addr, NVMCTRL_CTRLA_CMD_RWWEEER); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_program(device->hw, + row_start_addr + i * NVMCTRL_PAGE_SIZE, + tmp_buffer[i], + NVMCTRL_PAGE_SIZE, + NVMCTRL_CTRLA_CMD_RWWEEWP); + } + + } while (row_end_addr < (wr_start_addr + length - 1)); + + return ERR_NONE; +} diff --git a/bsp/microchip/samc21/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c b/bsp/microchip/samc21/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 0000000000..09fcc4bdf2 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,107 @@ +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, + (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos) + | (CONF_XOSC32K_SWBEN << OSC32KCTRL_CFDCTRL_SWBACK_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSC32K_CONFIG == 1 + /* OSC32K calibration value at bit 18:12 of memory 0x00806020 */ + calib = (*((uint32_t *)0x00806020) & 0x007F000) >> 12; + hri_osc32kctrl_write_OSC32K_reg( + hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | +#else + OSC32KCTRL_OSC32K_CALIB(calib) | +#endif + OSC32KCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) | (CONF_OSC32K_ONDEMAND << OSC32KCTRL_OSC32K_ONDEMAND_Pos) + | (CONF_OSC32K_RUNSTDBY << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) + | (CONF_OSC32K_EN1K << OSC32KCTRL_OSC32K_EN1K_Pos) | (CONF_OSC32K_EN32K << OSC32KCTRL_OSC32K_EN32K_Pos) + | (CONF_OSC32K_ENABLE << OSC32KCTRL_OSC32K_ENABLE_Pos)); +#endif +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSCULP32K_ULP32KSW == 1 + hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); + while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) + ; +#endif +#endif + +#if CONF_OSC32K_CONFIG == 1 +#if CONF_OSC32K_ENABLE == 1 && CONF_OSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(hw)) + ; +#endif +#endif + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/bsp/microchip/samc21/bsp/hpl/oscctrl/hpl_oscctrl.c b/bsp/microchip/samc21/bsp/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 0000000000..e4e09862db --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,121 @@ +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) + | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); + + hri_oscctrl_write_EVCTRL_reg(hw, (CONF_XOSC_CFDEO << OSCCTRL_EVCTRL_CFDEO_Pos)); +#endif +#if CONF_OSC48M_CONFIG == 1 + hri_oscctrl_write_OSC48MCTRL_reg(hw, + (CONF_OSC48M_RUNSTDBY << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos) + | (CONF_OSC48M_ENABLE << OSCCTRL_OSC48MCTRL_ENABLE_Pos)); + hri_oscctrl_write_OSC48MDIV_reg(hw, OSCCTRL_OSC48MDIV_DIV(CONF_OSC48M_DIV)); + while (hri_oscctrl_get_OSC48MSYNCBUSY_OSC48MDIV_bit(hw)) + ; + hri_oscctrl_write_OSC48MSTUP_reg(hw, OSCCTRL_OSC48MSTUP_STARTUP(CONF_OSC48M_STARTUP)); +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_AMPGC == 1 + hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC48M_CONFIG == 1 +#if CONF_OSC48M_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_OSC48MRDY_bit(hw)) + ; +#endif +#if CONF_OSC48M_ONDEMAND == 1 + hri_oscctrl_set_OSC48MCTRL_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == 2 + hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); + hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} diff --git a/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm.c b/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm.c new file mode 100644 index 0000000000..03bbc4fdb3 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm.c @@ -0,0 +1,64 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: /* IDLE */ + case 4: /* STANDBY */ + case 5: /* BACKUP */ + case 6: /* OFF */ + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm_base.h b/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000000..5a50a914ad --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/bsp/microchip/samc21/bsp/hpl/port/hpl_gpio_base.h b/bsp/microchip/samc21/bsp/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000000..3cc1981f51 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/port/hpl_gpio_base.h @@ -0,0 +1,170 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +} diff --git a/bsp/microchip/samc21/bsp/hpl/sercom/hpl_sercom.c b/bsp/microchip/samc21/bsp/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000000..ee57a1112b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hpl/sercom/hpl_sercom.c @@ -0,0 +1,3002 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + uint32_t usart_freq, calc_baud, calc_frac; + uint8_t i = _usarts[_get_sercom_index(hw)].number; + + switch (i) { + case 0: +#ifdef CONF_GCLK_SERCOM0_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM0_CORE_FREQUENCY; +#endif + break; + + case 1: +#ifdef CONF_GCLK_SERCOM1_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM1_CORE_FREQUENCY; +#endif + break; + + case 2: +#ifdef CONF_GCLK_SERCOM2_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM2_CORE_FREQUENCY; +#endif + break; + + case 3: +#ifdef CONF_GCLK_SERCOM3_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM3_CORE_FREQUENCY; +#endif + break; + + case 4: +#ifdef CONF_GCLK_SERCOM4_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM4_CORE_FREQUENCY; +#endif + break; + + case 5: +#ifdef CONF_GCLK_SERCOM5_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM5_CORE_FREQUENCY; +#endif + break; + + case 6: +#ifdef CONF_GCLK_SERCOM6_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM6_CORE_FREQUENCY; +#endif + break; + + case 7: +#ifdef CONF_GCLK_SERCOM7_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM7_CORE_FREQUENCY; +#endif + break; + + default: + ASSERT(false); + } + + if(usart_freq >= (16U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 16U * baud_rate) / usart_freq); + calc_frac = 0; + } else if(usart_freq >= (8U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 8U * baud_rate) / usart_freq); + calc_frac = 2; + } else if(usart_freq >= (3U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 3U * baud_rate) / usart_freq); + calc_frac = 4; + } else { + /* Do nothing */ + } + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = calc_baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = calc_frac; + } else { + hri_sercomusart_write_BAUD_reg(hw, calc_baud); + } + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/bsp/microchip/samc21/bsp/hri/hri_ac_c21.h b/bsp/microchip/samc21/bsp/hri/hri_ac_c21.h new file mode 100644 index 0000000000..5a88b97d1d --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_ac_c21.h @@ -0,0 +1,2241 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_AC_COMPONENT_ +#ifndef _HRI_AC_C21_H_INCLUDED_ +#define _HRI_AC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP2) >> AC_INTFLAG_COMP2_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP2; +} + +static inline bool hri_ac_get_INTFLAG_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP3) >> AC_INTFLAG_COMP3_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP3; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_INTFLAG_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN1) >> AC_INTFLAG_WIN1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN1; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP2) >> AC_INTFLAG_COMP2_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP2; +} + +static inline bool hri_ac_get_interrupt_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP3) >> AC_INTFLAG_COMP3_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP3; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN1) >> AC_INTFLAG_WIN1_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN1; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP2; +} + +static inline bool hri_ac_get_INTEN_COMP2_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP2) >> AC_INTENSET_COMP2_Pos; +} + +static inline void hri_ac_write_INTEN_COMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP2; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP2; + } +} + +static inline void hri_ac_clear_INTEN_COMP2_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP2; +} + +static inline void hri_ac_set_INTEN_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP3; +} + +static inline bool hri_ac_get_INTEN_COMP3_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP3) >> AC_INTENSET_COMP3_Pos; +} + +static inline void hri_ac_write_INTEN_COMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP3; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP3; + } +} + +static inline void hri_ac_clear_INTEN_COMP3_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP3; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN1; +} + +static inline bool hri_ac_get_INTEN_WIN1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN1) >> AC_INTENSET_WIN1_Pos; +} + +static inline void hri_ac_write_INTEN_WIN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN1; + } +} + +static inline void hri_ac_clear_INTEN_WIN1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN1; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE2_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE2) >> AC_STATUSA_STATE2_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE3_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE3) >> AC_STATUSA_STATE3_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE1_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE1(mask)) >> AC_STATUSA_WSTATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE1_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE1_Msk) >> AC_STATUSA_WSTATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY2_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY2) >> AC_STATUSB_READY2_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY3_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY3) >> AC_STATUSB_READY3_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL2_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL2) >> AC_SYNCBUSY_COMPCTRL2_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL3_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL3) >> AC_SYNCBUSY_COMPCTRL3_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO2) >> AC_EVCTRL_COMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO2; + tmp |= value << AC_EVCTRL_COMPEO2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO3) >> AC_EVCTRL_COMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO3; + tmp |= value << AC_EVCTRL_COMPEO3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO1) >> AC_EVCTRL_WINEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO1; + tmp |= value << AC_EVCTRL_WINEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI2) >> AC_EVCTRL_COMPEI2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI2; + tmp |= value << AC_EVCTRL_COMPEI2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI3) >> AC_EVCTRL_COMPEI3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI3; + tmp |= value << AC_EVCTRL_COMPEI3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI2) >> AC_EVCTRL_INVEI2_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI2; + tmp |= value << AC_EVCTRL_INVEI2_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI2_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI2; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI3) >> AC_EVCTRL_INVEI3_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI3; + tmp |= value << AC_EVCTRL_INVEI3_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI3_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI3; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN1) >> AC_WINCTRL_WEN1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN1; + tmp |= value << AC_WINCTRL_WEN1_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN1; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL1(mask)) >> AC_WINCTRL_WINTSEL1_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL1_Msk; + tmp |= AC_WINCTRL_WINTSEL1(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL1_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL1(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL1_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL1_Msk) >> AC_WINCTRL_WINTSEL1_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_C21_H_INCLUDED */ +#endif /* _SAMC21_AC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_adc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_adc_c21.h new file mode 100644 index 0000000000..21d74dbf41 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_adc_c21.h @@ -0,0 +1,2847 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_ADC_COMPONENT_ +#ifndef _HRI_ADC_C21_H_INCLUDED_ +#define _HRI_ADC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlc_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_syncbusy_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_seqctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_ctrlb_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_seqstatus_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_adc_seqstatus_reg_t mask) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DIFFMODE; + tmp |= value << ADC_CTRLC_DIFFMODE_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_LEFTADJ; + tmp |= value << ADC_CTRLC_LEFTADJ_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_FREERUN; + tmp |= value << ADC_CTRLC_FREERUN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_CORREN; + tmp |= value << ADC_CTRLC_CORREN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_R2R; + tmp |= value << ADC_CTRLC_R2R_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_RESSEL_Msk; + tmp |= ADC_CTRLC_RESSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_WINMODE_Msk; + tmp |= ADC_CTRLC_WINMODE(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DUALSEL_Msk; + tmp |= ADC_CTRLC_DUALSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLC.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= ~ADC_SEQCTRL_SEQEN_Msk; + tmp |= ADC_SEQCTRL_SEQEN(data); + ((Adc *)hw)->SEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_C21_H_INCLUDED */ +#endif /* _SAMC21_ADC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_c21.h b/bsp/microchip/samc21/bsp/hri/hri_c21.h new file mode 100644 index 0000000000..8dd7d9b0d7 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_c21.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief SAM C21 HRI top-level header file + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_C21_H_INCLUDED_ +#define _HRI_C21_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_C21_H_INCLUDED_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_can_c21.h b/bsp/microchip/samc21/bsp/hri/hri_can_c21.h new file mode 100644 index 0000000000..42bf5eb768 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_can_c21.h @@ -0,0 +1,16997 @@ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_CAN_COMPONENT_ +#ifndef _HRI_CAN_C21_H_INCLUDED_ +#define _HRI_CAN_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_C21_H_INCLUDED */ +#endif /* _SAMC21_CAN_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_ccl_c21.h b/bsp/microchip/samc21/bsp/hri/hri_ccl_c21.h new file mode 100644 index 0000000000..e59ce0e567 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_ccl_c21.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_CCL_COMPONENT_ +#ifndef _HRI_CCL_C21_H_INCLUDED_ +#define _HRI_CCL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_C21_H_INCLUDED */ +#endif /* _SAMC21_CCL_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_dac_c21.h b/bsp/microchip/samc21/bsp/hri/hri_dac_c21.h new file mode 100644 index 0000000000..05736c3847 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_dac_c21.h @@ -0,0 +1,966 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DAC_COMPONENT_ +#ifndef _HRI_DAC_C21_H_INCLUDED_ +#define _HRI_DAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_interrupt_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN) >> DAC_INTENSET_UNDERRUN_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; +} + +static inline void hri_dac_set_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; +} + +static inline bool hri_dac_get_INTEN_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY) >> DAC_INTENSET_EMPTY_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY) >> DAC_STATUS_READY_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA) >> DAC_SYNCBUSY_DATA_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF) >> DAC_SYNCBUSY_DATABUF_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_RUNSTDBY) >> DAC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_RUNSTDBY; + tmp |= value << DAC_CTRLA_RUNSTDBY_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_EOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_EOEN) >> DAC_CTRLB_EOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_EOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_EOEN; + tmp |= value << DAC_CTRLB_EOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_IOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_IOEN) >> DAC_CTRLB_IOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_IOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_IOEN; + tmp |= value << DAC_CTRLB_IOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_LEFTADJ) >> DAC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_LEFTADJ; + tmp |= value << DAC_CTRLB_LEFTADJ_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_VPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_VPD) >> DAC_CTRLB_VPD_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_VPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_VPD; + tmp |= value << DAC_CTRLB_VPD_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DITHER_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DITHER) >> DAC_CTRLB_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DITHER_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DITHER; + tmp |= value << DAC_CTRLB_DITHER_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DITHER_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI) >> DAC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI; + tmp |= value << DAC_EVCTRL_STARTEI_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO) >> DAC_EVCTRL_EMPTYEO_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO; + tmp |= value << DAC_EVCTRL_EMPTYEO_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI) >> DAC_EVCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI; + tmp |= value << DAC_EVCTRL_INVEI_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_C21_H_INCLUDED */ +#endif /* _SAMC21_DAC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_divas_c21.h b/bsp/microchip/samc21/bsp/hri/hri_divas_c21.h new file mode 100644 index 0000000000..934fe12b60 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_divas_c21.h @@ -0,0 +1,546 @@ +/** + * \file + * + * \brief SAM DIVAS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DIVAS_COMPONENT_ +#ifndef _HRI_DIVAS_C21_H_INCLUDED_ +#define _HRI_DIVAS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DIVAS_CRITICAL_SECTIONS) +#define DIVAS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DIVAS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DIVAS_CRITICAL_SECTION_ENTER() +#define DIVAS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_divas_dividend_reg_t; +typedef uint32_t hri_divas_divisor_reg_t; +typedef uint32_t hri_divas_rem_reg_t; +typedef uint32_t hri_divas_result_reg_t; +typedef uint32_t hri_divas_sqrnum_reg_t; +typedef uint8_t hri_divas_ctrla_reg_t; +typedef uint8_t hri_divas_status_reg_t; + +static inline hri_divas_result_reg_t hri_divas_get_RESULT_RESULT_bf(const void *const hw, hri_divas_result_reg_t mask) +{ + return (((Divas *)hw)->RESULT.reg & DIVAS_RESULT_RESULT(mask)) >> DIVAS_RESULT_RESULT_Pos; +} + +static inline hri_divas_result_reg_t hri_divas_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Divas *)hw)->RESULT.reg & DIVAS_RESULT_RESULT_Msk) >> DIVAS_RESULT_RESULT_Pos; +} + +static inline hri_divas_result_reg_t hri_divas_get_RESULT_reg(const void *const hw, hri_divas_result_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_divas_result_reg_t hri_divas_read_RESULT_reg(const void *const hw) +{ + return ((Divas *)hw)->RESULT.reg; +} + +static inline hri_divas_rem_reg_t hri_divas_get_REM_REM_bf(const void *const hw, hri_divas_rem_reg_t mask) +{ + return (((Divas *)hw)->REM.reg & DIVAS_REM_REM(mask)) >> DIVAS_REM_REM_Pos; +} + +static inline hri_divas_rem_reg_t hri_divas_read_REM_REM_bf(const void *const hw) +{ + return (((Divas *)hw)->REM.reg & DIVAS_REM_REM_Msk) >> DIVAS_REM_REM_Pos; +} + +static inline hri_divas_rem_reg_t hri_divas_get_REM_reg(const void *const hw, hri_divas_rem_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->REM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_divas_rem_reg_t hri_divas_read_REM_reg(const void *const hw) +{ + return ((Divas *)hw)->REM.reg; +} + +static inline void hri_divas_set_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_CTRLA_SIGNED_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp = (tmp & DIVAS_CTRLA_SIGNED) >> DIVAS_CTRLA_SIGNED_Pos; + return (bool)tmp; +} + +static inline void hri_divas_write_CTRLA_SIGNED_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= ~DIVAS_CTRLA_SIGNED; + tmp |= value << DIVAS_CTRLA_SIGNED_Pos; + ((Divas *)hw)->CTRLA.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_SIGNED_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= DIVAS_CTRLA_SIGNED; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_set_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_CTRLA_DLZ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp = (tmp & DIVAS_CTRLA_DLZ) >> DIVAS_CTRLA_DLZ_Pos; + return (bool)tmp; +} + +static inline void hri_divas_write_CTRLA_DLZ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= ~DIVAS_CTRLA_DLZ; + tmp |= value << DIVAS_CTRLA_DLZ_Pos; + ((Divas *)hw)->CTRLA.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_DLZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= DIVAS_CTRLA_DLZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_set_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_ctrla_reg_t hri_divas_get_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_CTRLA_reg(const void *const hw, hri_divas_ctrla_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->CTRLA.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_ctrla_reg_t hri_divas_read_CTRLA_reg(const void *const hw) +{ + return ((Divas *)hw)->CTRLA.reg; +} + +static inline void hri_divas_set_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg |= DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_get_DIVIDEND_DIVIDEND_bf(const void *const hw, + hri_divas_dividend_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp = (tmp & DIVAS_DIVIDEND_DIVIDEND(mask)) >> DIVAS_DIVIDEND_DIVIDEND_Pos; + return tmp; +} + +static inline void hri_divas_write_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp &= ~DIVAS_DIVIDEND_DIVIDEND_Msk; + tmp |= DIVAS_DIVIDEND_DIVIDEND(data); + ((Divas *)hw)->DIVIDEND.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg &= ~DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVIDEND_DIVIDEND_bf(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg ^= DIVAS_DIVIDEND_DIVIDEND(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_read_DIVIDEND_DIVIDEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp = (tmp & DIVAS_DIVIDEND_DIVIDEND_Msk) >> DIVAS_DIVIDEND_DIVIDEND_Pos; + return tmp; +} + +static inline void hri_divas_set_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_get_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVIDEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVIDEND_reg(const void *const hw, hri_divas_dividend_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVIDEND.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_dividend_reg_t hri_divas_read_DIVIDEND_reg(const void *const hw) +{ + return ((Divas *)hw)->DIVIDEND.reg; +} + +static inline void hri_divas_set_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg |= DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_get_DIVISOR_DIVISOR_bf(const void *const hw, + hri_divas_divisor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp = (tmp & DIVAS_DIVISOR_DIVISOR(mask)) >> DIVAS_DIVISOR_DIVISOR_Pos; + return tmp; +} + +static inline void hri_divas_write_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp &= ~DIVAS_DIVISOR_DIVISOR_Msk; + tmp |= DIVAS_DIVISOR_DIVISOR(data); + ((Divas *)hw)->DIVISOR.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg &= ~DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVISOR_DIVISOR_bf(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg ^= DIVAS_DIVISOR_DIVISOR(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_read_DIVISOR_DIVISOR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp = (tmp & DIVAS_DIVISOR_DIVISOR_Msk) >> DIVAS_DIVISOR_DIVISOR_Pos; + return tmp; +} + +static inline void hri_divas_set_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_get_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->DIVISOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_DIVISOR_reg(const void *const hw, hri_divas_divisor_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->DIVISOR.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_divisor_reg_t hri_divas_read_DIVISOR_reg(const void *const hw) +{ + return ((Divas *)hw)->DIVISOR.reg; +} + +static inline void hri_divas_set_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg |= DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_get_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp = (tmp & DIVAS_SQRNUM_SQRNUM(mask)) >> DIVAS_SQRNUM_SQRNUM_Pos; + return tmp; +} + +static inline void hri_divas_write_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t data) +{ + uint32_t tmp; + DIVAS_CRITICAL_SECTION_ENTER(); + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp &= ~DIVAS_SQRNUM_SQRNUM_Msk; + tmp |= DIVAS_SQRNUM_SQRNUM(data); + ((Divas *)hw)->SQRNUM.reg = tmp; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg &= ~DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_SQRNUM_SQRNUM_bf(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg ^= DIVAS_SQRNUM_SQRNUM(mask); + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_read_SQRNUM_SQRNUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp = (tmp & DIVAS_SQRNUM_SQRNUM_Msk) >> DIVAS_SQRNUM_SQRNUM_Pos; + return tmp; +} + +static inline void hri_divas_set_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg |= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_get_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Divas *)hw)->SQRNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_write_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t data) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg = data; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_clear_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg &= ~mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_divas_toggle_SQRNUM_reg(const void *const hw, hri_divas_sqrnum_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->SQRNUM.reg ^= mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_sqrnum_reg_t hri_divas_read_SQRNUM_reg(const void *const hw) +{ + return ((Divas *)hw)->SQRNUM.reg; +} + +static inline bool hri_divas_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Divas *)hw)->STATUS.reg & DIVAS_STATUS_BUSY) >> DIVAS_STATUS_BUSY_Pos; +} + +static inline void hri_divas_clear_STATUS_BUSY_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = DIVAS_STATUS_BUSY; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_divas_get_STATUS_DBZ_bit(const void *const hw) +{ + return (((Divas *)hw)->STATUS.reg & DIVAS_STATUS_DBZ) >> DIVAS_STATUS_DBZ_Pos; +} + +static inline void hri_divas_clear_STATUS_DBZ_bit(const void *const hw) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = DIVAS_STATUS_DBZ; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_status_reg_t hri_divas_get_STATUS_reg(const void *const hw, hri_divas_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Divas *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_divas_clear_STATUS_reg(const void *const hw, hri_divas_status_reg_t mask) +{ + DIVAS_CRITICAL_SECTION_ENTER(); + ((Divas *)hw)->STATUS.reg = mask; + DIVAS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_divas_status_reg_t hri_divas_read_STATUS_reg(const void *const hw) +{ + return ((Divas *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DIVAS_C21_H_INCLUDED */ +#endif /* _SAMC21_DIVAS_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_dmac_c21.h b/bsp/microchip/samc21/bsp/hri/hri_dmac_c21.h new file mode 100644 index 0000000000..25eeed3302 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_dmac_c21.h @@ -0,0 +1,4339 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_C21_H_INCLUDED_ +#define _HRI_DMAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_C21_H_INCLUDED */ +#endif /* _SAMC21_DMAC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_dsu_c21.h b/bsp/microchip/samc21/bsp/hri/hri_dsu_c21.h new file mode 100644 index 0000000000..c9cce9cd07 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_dsu_c21.h @@ -0,0 +1,1187 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_DSU_COMPONENT_ +#ifndef _HRI_DSU_C21_H_INCLUDED_ +#define _HRI_DSU_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; +typedef uint8_t hri_dsu_statusc_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_get_STATUSC_STATE_bf(const void *const hw, hri_dsu_statusc_reg_t mask) +{ + return (((Dsu *)hw)->STATUSC.reg & DSU_STATUSC_STATE(mask)) >> DSU_STATUSC_STATE_Pos; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_read_STATUSC_STATE_bf(const void *const hw) +{ + return (((Dsu *)hw)->STATUSC.reg & DSU_STATUSC_STATE_Msk) >> DSU_STATUSC_STATE_Pos; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_get_STATUSC_reg(const void *const hw, hri_dsu_statusc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusc_reg_t hri_dsu_read_STATUSC_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSC.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_C21_H_INCLUDED */ +#endif /* _SAMC21_DSU_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_eic_c21.h b/bsp/microchip/samc21/bsp/hri/hri_eic_c21.h new file mode 100644 index 0000000000..d99e811f52 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_eic_c21.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_EIC_COMPONENT_ +#ifndef _HRI_EIC_C21_H_INCLUDED_ +#define _HRI_EIC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_C21_H_INCLUDED */ +#endif /* _SAMC21_EIC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_evsys_c21.h b/bsp/microchip/samc21/bsp/hri/hri_evsys_c21.h new file mode 100644 index 0000000000..aad1437e43 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_evsys_c21.h @@ -0,0 +1,1725 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_C21_H_INCLUDED_ +#define _HRI_EVSYS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; +} + +static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; + } +} + +static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; +} + +static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; +} + +static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; + } +} + +static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; +} + +static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; +} + +static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; + } +} + +static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; +} + +static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; +} + +static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; + } +} + +static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; +} + +static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; + } +} + +static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; +} + +static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; +} + +static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; + } +} + +static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; +} + +static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; +} + +static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; + } +} + +static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; +} + +static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; +} + +static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; + } +} + +static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->CHANNEL[index].reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_C21_H_INCLUDED */ +#endif /* _SAMC21_EVSYS_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_freqm_c21.h b/bsp/microchip/samc21/bsp/hri/hri_freqm_c21.h new file mode 100644 index 0000000000..616cec2048 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_freqm_c21.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_C21_H_INCLUDED_ +#define _HRI_FREQM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_C21_H_INCLUDED */ +#endif /* _SAMC21_FREQM_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_gclk_c21.h b/bsp/microchip/samc21/bsp/hri/hri_gclk_c21.h new file mode 100644 index 0000000000..0234e1e93a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_gclk_c21.h @@ -0,0 +1,790 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_C21_H_INCLUDED_ +#define _HRI_GCLK_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_C21_H_INCLUDED */ +#endif /* _SAMC21_GCLK_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_hmatrixb_c21.h b/bsp/microchip/samc21/bsp/hri/hri_hmatrixb_c21.h new file mode 100644 index 0000000000..95e0f8c972 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_hmatrixb_c21.h @@ -0,0 +1,408 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_C21_H_INCLUDED_ +#define _HRI_HMATRIXB_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_mcfg_reg_t; +typedef uint32_t hri_hmatrixb_mrcr_reg_t; +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixb_scfg_reg_t; +typedef uint32_t hri_hmatrixb_sfr_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixb_set_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mcfg_reg_t hri_hmatrixb_get_MCFG_reg(const void *const hw, uint8_t index, + hri_hmatrixb_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->MCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_MCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_mcfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MCFG[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mcfg_reg_t hri_hmatrixb_read_MCFG_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->MCFG[index].reg; +} + +static inline void hri_hmatrixb_set_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_scfg_reg_t hri_hmatrixb_get_SCFG_reg(const void *const hw, uint8_t index, + hri_hmatrixb_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->SCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_SCFG_reg(const void *const hw, uint8_t index, hri_hmatrixb_scfg_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SCFG[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_scfg_reg_t hri_hmatrixb_read_SCFG_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->SCFG[index].reg; +} + +static inline void hri_hmatrixb_set_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mrcr_reg_t hri_hmatrixb_get_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->MRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_MRCR_reg(const void *const hw, hri_hmatrixb_mrcr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->MRCR.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_mrcr_reg_t hri_hmatrixb_read_MRCR_reg(const void *const hw) +{ + return ((Hmatrixb *)hw)->MRCR.reg; +} + +static inline void hri_hmatrixb_set_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_get_SFR_reg(const void *const hw, uint8_t index, + hri_hmatrixb_sfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->SFR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_read_SFR_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->SFR[index].reg; +} + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_C21_H_INCLUDED */ +#endif /* _SAMC21_HMATRIXB_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_mclk_c21.h b/bsp/microchip/samc21/bsp/hri/hri_mclk_c21.h new file mode 100644 index 0000000000..50253df58c --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_mclk_c21.h @@ -0,0 +1,2490 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_C21_H_INCLUDED_ +#define _HRI_MCLK_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; + tmp |= MCLK_CPUDIV_CPUDIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIXHS) >> MCLK_AHBMASK_HMATRIXHS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIXHS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIXHS; + tmp |= value << MCLK_AHBMASK_HMATRIXHS_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DIVAS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DIVAS) >> MCLK_AHBMASK_DIVAS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DIVAS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DIVAS; + tmp |= value << MCLK_AHBMASK_DIVAS_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DIVAS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DIVAS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TSENS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TSENS) >> MCLK_APBAMASK_TSENS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TSENS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TSENS; + tmp |= value << MCLK_APBAMASK_TSENS_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TSENS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TSENS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIXHS) >> MCLK_APBBMASK_HMATRIXHS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIXHS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIXHS; + tmp |= value << MCLK_APBBMASK_HMATRIXHS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIXHS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIXHS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_EVSYS; + tmp |= value << MCLK_APBCMASK_EVSYS_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM0; + tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM1; + tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM2; + tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM3; + tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM4; + tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM5; + tmp |= value << MCLK_APBCMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC0; + tmp |= value << MCLK_APBCMASK_TCC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC1) >> MCLK_APBCMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC1; + tmp |= value << MCLK_APBCMASK_TCC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC0; + tmp |= value << MCLK_APBCMASK_TC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC1; + tmp |= value << MCLK_APBCMASK_TC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC2; + tmp |= value << MCLK_APBCMASK_TC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC3; + tmp |= value << MCLK_APBCMASK_TC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ADC0) >> MCLK_APBCMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ADC0; + tmp |= value << MCLK_APBCMASK_ADC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ADC1) >> MCLK_APBCMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ADC1; + tmp |= value << MCLK_APBCMASK_ADC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SDADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SDADC) >> MCLK_APBCMASK_SDADC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SDADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SDADC; + tmp |= value << MCLK_APBCMASK_SDADC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SDADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SDADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_DAC) >> MCLK_APBCMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_DAC; + tmp |= value << MCLK_APBCMASK_DAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PTC; + tmp |= value << MCLK_APBCMASK_PTC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_C21_H_INCLUDED */ +#endif /* _SAMC21_MCLK_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_mpu_c21.h b/bsp/microchip/samc21/bsp/hri/hri_mpu_c21.h new file mode 100644 index 0000000000..ef2b76cf4b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_mpu_c21.h @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief SAM MPU + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MPU_COMPONENT_ +#ifndef _HRI_MPU_C21_H_INCLUDED_ +#define _HRI_MPU_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MPU_CRITICAL_SECTIONS) +#define MPU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MPU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MPU_CRITICAL_SECTION_ENTER() +#define MPU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mpu_ctrl_reg_t; +typedef uint32_t hri_mpu_rasr_reg_t; +typedef uint32_t hri_mpu_rbar_reg_t; +typedef uint32_t hri_mpu_rnr_reg_t; +typedef uint32_t hri_mpu_type_reg_t; + +static inline bool hri_mpu_get_TYPE_SEPARATE_bit(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_SEPARATE) >> 0; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_DREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION(mask)) >> 8; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_DREGION_bf(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION_Msk) >> 8; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_IREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION(mask)) >> 16; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_IREGION_bf(const void *const hw) +{ + return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION_Msk) >> 16; +} + +static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_reg(const void *const hw, hri_mpu_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_reg(const void *const hw) +{ + return ((Mpu *)hw)->TYPE.reg; +} + +static inline void hri_mpu_set_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_ctrl_reg_t hri_mpu_get_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->CTRL.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_ctrl_reg_t hri_mpu_read_CTRL_reg(const void *const hw) +{ + return ((Mpu *)hw)->CTRL.reg; +} + +static inline void hri_mpu_set_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rnr_reg_t hri_mpu_get_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RNR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RNR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rnr_reg_t hri_mpu_read_RNR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RNR.reg; +} + +static inline void hri_mpu_set_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rbar_reg_t hri_mpu_get_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RBAR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rbar_reg_t hri_mpu_read_RBAR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RBAR.reg; +} + +static inline void hri_mpu_set_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg |= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rasr_reg_t hri_mpu_get_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mpu *)hw)->RASR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mpu_write_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t data) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg = data; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_clear_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg &= ~mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mpu_toggle_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) +{ + MPU_CRITICAL_SECTION_ENTER(); + ((Mpu *)hw)->RASR.reg ^= mask; + MPU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mpu_rasr_reg_t hri_mpu_read_RASR_reg(const void *const hw) +{ + return ((Mpu *)hw)->RASR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MPU_C21_H_INCLUDED */ +#endif /* _SAMC21_MPU_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_mtb_c21.h b/bsp/microchip/samc21/bsp/hri/hri_mtb_c21.h new file mode 100644 index 0000000000..fb603723c6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_mtb_c21.h @@ -0,0 +1,551 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_MTB_COMPONENT_ +#ifndef _HRI_MTB_C21_H_INCLUDED_ +#define _HRI_MTB_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_C21_H_INCLUDED */ +#endif /* _SAMC21_MTB_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_nvic_c21.h b/bsp/microchip/samc21/bsp/hri/hri_nvic_c21.h new file mode 100644 index 0000000000..aea356bc7a --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_nvic_c21.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_C21_H_INCLUDED_ +#define _HRI_NVIC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_icer_reg_t; +typedef uint32_t hri_nvic_icpr_reg_t; +typedef uint32_t hri_nvic_ipr_reg_t; +typedef uint32_t hri_nvic_iser_reg_t; +typedef uint32_t hri_nvic_ispr_reg_t; + +static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISER.reg; +} + +static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICER.reg; +} + +static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISPR.reg; +} + +static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICPR.reg; +} + +static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->IPR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) +{ + return ((Nvic *)hw)->IPR[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_C21_H_INCLUDED */ +#endif /* _SAMC21_NVIC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_nvmctrl_c21.h b/bsp/microchip/samc21/bsp/hri/hri_nvmctrl_c21.h new file mode 100644 index 0000000000..76ebdb33b9 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_nvmctrl_c21.h @@ -0,0 +1,1103 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_C21_H_INCLUDED_ +#define _HRI_NVMCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata0_reg_t; +typedef uint32_t hri_nvmctrl_pbldata1_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline hri_nvmctrl_pbldata0_reg_t hri_nvmctrl_get_PBLDATA0_reg(const void *const hw, + hri_nvmctrl_pbldata0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata0_reg_t hri_nvmctrl_read_PBLDATA0_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PBLDATA0.reg; +} + +static inline hri_nvmctrl_pbldata1_reg_t hri_nvmctrl_get_PBLDATA1_reg(const void *const hw, + hri_nvmctrl_pbldata1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata1_reg_t hri_nvmctrl_read_PBLDATA1_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PBLDATA1.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_CACHEDIS_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS(mask)) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS_Msk; + tmp |= NVMCTRL_CTRLB_CACHEDIS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_CACHEDIS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS_Msk) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, + hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; + tmp |= NVMCTRL_PARAM_RWWEEP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_NVMCTRL_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_osc32kctrl_c21.h b/bsp/microchip/samc21/bsp/hri/hri_osc32kctrl_c21.h new file mode 100644 index 0000000000..32b14b9ff4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_osc32kctrl_c21.h @@ -0,0 +1,1500 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_C21_H_INCLUDED_ +#define _HRI_OSC32KCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osc32k_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_rtcctrl_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY) >> OSC32KCTRL_STATUS_OSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ENABLE) >> OSC32KCTRL_OSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ENABLE; + tmp |= value << OSC32KCTRL_OSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN32K) >> OSC32KCTRL_OSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN32K; + tmp |= value << OSC32KCTRL_OSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN1K) >> OSC32KCTRL_OSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN1K; + tmp |= value << OSC32KCTRL_OSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_RUNSTDBY) >> OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ONDEMAND) >> OSC32KCTRL_OSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_OSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_WRTLOCK) >> OSC32KCTRL_OSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP(mask)) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_OSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP_Msk) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB(mask)) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSC32K_CALIB(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB_Msk) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_reg(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_OSC32KCTRL_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_oscctrl_c21.h b/bsp/microchip/samc21/bsp/hri/hri_oscctrl_c21.h new file mode 100644 index 0000000000..a2fba3f299 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_oscctrl_c21.h @@ -0,0 +1,2509 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_C21_H_INCLUDED_ +#define _HRI_OSCCTRL_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrl_cal48m_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_osc48msyncbusy_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint8_t hri_oscctrl_cfdpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_dpllpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllstatus_reg_t; +typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrl_osc48mctrl_reg_t; +typedef uint8_t hri_oscctrl_osc48mdiv_reg_t; +typedef uint8_t hri_oscctrl_osc48mstup_reg_t; + +static inline void hri_oscctrl_osc48msyncbusy_wait_for_sync(const void *const hw, hri_oscctrl_osc48msyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_osc48msyncbusy_is_syncing(const void *const hw, hri_oscctrl_osc48msyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_dpllsyncbusy_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_dpllsyncbusy_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTFLAG_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC48MRDY) >> OSCCTRL_INTFLAG_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_interrupt_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC48MRDY) >> OSCCTRL_INTFLAG_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL; +} + +static inline void hri_oscctrl_set_INTEN_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC48MRDY; +} + +static inline bool hri_oscctrl_get_INTEN_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC48MRDY) >> OSCCTRL_INTENSET_OSC48MRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_OSC48MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC48MRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC48MRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_OSC48MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC48MRDY; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_OSC48MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC48MRDY) >> OSCCTRL_STATUS_OSC48MRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline bool hri_oscctrl_get_OSC48MSYNCBUSY_OSC48MDIV_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->OSC48MSYNCBUSY.reg & OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV) + >> OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos; +} + +static inline hri_oscctrl_osc48msyncbusy_reg_t hri_oscctrl_get_OSC48MSYNCBUSY_reg(const void *const hw, + hri_oscctrl_osc48msyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_osc48msyncbusy_reg_t hri_oscctrl_read_OSC48MSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; + tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; + tmp |= OSCCTRL_XOSCCTRL_GAIN(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->XOSCCTRL.reg; +} + +static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk; + tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data); + ((Oscctrl *)hw)->CFDPRESC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const hw, + hri_oscctrl_cfdpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->CFDPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CFDPRESC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->CFDPRESC.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO; + tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_ENABLE) >> OSCCTRL_OSC48MCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_ENABLE; + tmp |= value << OSCCTRL_OSC48MCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_RUNSTDBY) >> OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC48MCTRL_ONDEMAND) >> OSCCTRL_OSC48MCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= ~OSCCTRL_OSC48MCTRL_ONDEMAND; + tmp |= value << OSCCTRL_OSC48MCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->OSC48MCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= OSCCTRL_OSC48MCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mctrl_reg_t hri_oscctrl_get_OSC48MCTRL_reg(const void *const hw, + hri_oscctrl_osc48mctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MCTRL_reg(const void *const hw, hri_oscctrl_osc48mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mctrl_reg_t hri_oscctrl_read_OSC48MCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg |= OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_get_OSC48MDIV_DIV_bf(const void *const hw, + hri_oscctrl_osc48mdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp = (tmp & OSCCTRL_OSC48MDIV_DIV(mask)) >> OSCCTRL_OSC48MDIV_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp &= ~OSCCTRL_OSC48MDIV_DIV_Msk; + tmp |= OSCCTRL_OSC48MDIV_DIV(data); + ((Oscctrl *)hw)->OSC48MDIV.reg = tmp; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg &= ~OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MDIV_DIV_bf(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg ^= OSCCTRL_OSC48MDIV_DIV(mask); + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_read_OSC48MDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp = (tmp & OSCCTRL_OSC48MDIV_DIV_Msk) >> OSCCTRL_OSC48MDIV_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg |= mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_get_OSC48MDIV_reg(const void *const hw, + hri_oscctrl_osc48mdiv_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->OSC48MDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg = data; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg &= ~mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MDIV_reg(const void *const hw, hri_oscctrl_osc48mdiv_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MDIV.reg ^= mask; + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mdiv_reg_t hri_oscctrl_read_OSC48MDIV_reg(const void *const hw) +{ + hri_oscctrl_osc48msyncbusy_wait_for_sync(hw, OSCCTRL_OSC48MSYNCBUSY_MASK); + return ((Oscctrl *)hw)->OSC48MDIV.reg; +} + +static inline void hri_oscctrl_set_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg |= OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_get_OSC48MSTUP_STARTUP_bf(const void *const hw, + hri_oscctrl_osc48mstup_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp = (tmp & OSCCTRL_OSC48MSTUP_STARTUP(mask)) >> OSCCTRL_OSC48MSTUP_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp &= ~OSCCTRL_OSC48MSTUP_STARTUP_Msk; + tmp |= OSCCTRL_OSC48MSTUP_STARTUP(data); + ((Oscctrl *)hw)->OSC48MSTUP.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg &= ~OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MSTUP_STARTUP_bf(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg ^= OSCCTRL_OSC48MSTUP_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_read_OSC48MSTUP_STARTUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp = (tmp & OSCCTRL_OSC48MSTUP_STARTUP_Msk) >> OSCCTRL_OSC48MSTUP_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_get_OSC48MSTUP_reg(const void *const hw, + hri_oscctrl_osc48mstup_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC48MSTUP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC48MSTUP_reg(const void *const hw, hri_oscctrl_osc48mstup_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC48MSTUP.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc48mstup_reg_t hri_oscctrl_read_OSC48MSTUP_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->OSC48MSTUP.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; + tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; + tmp |= OSCCTRL_DPLLPRESC_PRESC(data); + ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg = data; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) +{ + hri_oscctrl_dpllsyncbusy_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLPRESC.reg; +} + +static inline void hri_oscctrl_set_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_FCAL_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FCAL(mask)) >> OSCCTRL_CAL48M_FCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_FCAL_Msk; + tmp |= OSCCTRL_CAL48M_FCAL(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_FCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_FCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_FCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FCAL_Msk) >> OSCCTRL_CAL48M_FCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_FRANGE_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FRANGE(mask)) >> OSCCTRL_CAL48M_FRANGE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_FRANGE_Msk; + tmp |= OSCCTRL_CAL48M_FRANGE(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_FRANGE_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_FRANGE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_FRANGE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_FRANGE_Msk) >> OSCCTRL_CAL48M_FRANGE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_TCAL_bf(const void *const hw, + hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_TCAL(mask)) >> OSCCTRL_CAL48M_TCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= ~OSCCTRL_CAL48M_TCAL_Msk; + tmp |= OSCCTRL_CAL48M_TCAL(data); + ((Oscctrl *)hw)->CAL48M.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_TCAL_bf(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= OSCCTRL_CAL48M_TCAL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_TCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp = (tmp & OSCCTRL_CAL48M_TCAL_Msk) >> OSCCTRL_CAL48M_TCAL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_get_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->CAL48M.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_CAL48M_reg(const void *const hw, hri_oscctrl_cal48m_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->CAL48M.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_cal48m_reg_t hri_oscctrl_read_CAL48M_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->CAL48M.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_C21_H_INCLUDED */ +#endif /* _SAMC21_OSCCTRL_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_pac_c21.h b/bsp/microchip/samc21/bsp/hri/hri_pac_c21.h new file mode 100644 index 0000000000..8072936c7b --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_pac_c21.h @@ -0,0 +1,1176 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PAC_COMPONENT_ +#ifndef _HRI_PAC_C21_H_INCLUDED_ +#define _HRI_PAC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMDMAC) >> PAC_INTFLAGAHB_LPRAMDMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMDMAC; +} + +static inline bool hri_pac_get_INTFLAGAHB_DIVAS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_DIVAS) >> PAC_INTFLAGAHB_DIVAS_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_DIVAS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_DIVAS; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_TSENS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TSENS) >> PAC_INTFLAGA_TSENS_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TSENS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TSENS; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIXHS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIXHS) >> PAC_INTFLAGB_HMATRIXHS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIXHS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIXHS; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; +} + +static inline bool hri_pac_get_INTFLAGC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC1) >> PAC_INTFLAGC_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; +} + +static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC0) >> PAC_INTFLAGC_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC0; +} + +static inline bool hri_pac_get_INTFLAGC_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC1) >> PAC_INTFLAGC_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC1; +} + +static inline bool hri_pac_get_INTFLAGC_SDADC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SDADC) >> PAC_INTFLAGC_SDADC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SDADC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SDADC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_DAC) >> PAC_INTFLAGC_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_DAC; +} + +static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_TSENS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TSENS) >> PAC_STATUSA_TSENS_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIXHS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIXHS) >> PAC_STATUSB_HMATRIXHS_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC1) >> PAC_STATUSC_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC0) >> PAC_STATUSC_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC1) >> PAC_STATUSC_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SDADC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SDADC) >> PAC_STATUSC_SDADC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_DAC) >> PAC_STATUSC_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_C21_H_INCLUDED */ +#endif /* _SAMC21_PAC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_pm_c21.h b/bsp/microchip/samc21/bsp/hri/hri_pm_c21.h new file mode 100644 index 0000000000..f4a26759e7 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_pm_c21.h @@ -0,0 +1,279 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PM_COMPONENT_ +#ifndef _HRI_PM_C21_H_INCLUDED_ +#define _HRI_PM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pm_stdbycfg_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASHS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASHS_Msk; + tmp |= value << PM_STDBYCFG_BBIASHS_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS_Msk; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; + tmp |= PM_STDBYCFG_VREGSMOD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_C21_H_INCLUDED */ +#endif /* _SAMC21_PM_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_port_c21.h b/bsp/microchip/samc21/bsp/hri/hri_port_c21.h new file mode 100644 index 0000000000..76845a2759 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_port_c21.h @@ -0,0 +1,2357 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_PORT_COMPONENT_ +#ifndef _HRI_PORT_C21_H_INCLUDED_ +#define _HRI_PORT_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_C21_H_INCLUDED */ +#endif /* _SAMC21_PORT_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_rstc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_rstc_c21.h new file mode 100644 index 0000000000..e72770b49e --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_rstc_c21.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_C21_H_INCLUDED_ +#define _HRI_RSTC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_C21_H_INCLUDED */ +#endif /* _SAMC21_RSTC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_rtc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_rtc_c21.h new file mode 100644 index 0000000000..950968ceb1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_rtc_c21.h @@ -0,0 +1,6175 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_RTC_COMPONENT_ +#ifndef _HRI_RTC_C21_H_INCLUDED_ +#define _HRI_RTC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_C21_H_INCLUDED */ +#endif /* _SAMC21_RTC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_sdadc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_sdadc_c21.h new file mode 100644 index 0000000000..286e91101f --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_sdadc_c21.h @@ -0,0 +1,2543 @@ +/** + * \file + * + * \brief SAM SDADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SDADC_COMPONENT_ +#ifndef _HRI_SDADC_C21_H_INCLUDED_ +#define _HRI_SDADC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDADC_CRITICAL_SECTIONS) +#define SDADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDADC_CRITICAL_SECTION_ENTER() +#define SDADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdadc_ctrlb_reg_t; +typedef uint16_t hri_sdadc_gaincorr_reg_t; +typedef uint32_t hri_sdadc_offsetcorr_reg_t; +typedef uint32_t hri_sdadc_result_reg_t; +typedef uint32_t hri_sdadc_syncbusy_reg_t; +typedef uint32_t hri_sdadc_winlt_reg_t; +typedef uint32_t hri_sdadc_winut_reg_t; +typedef uint8_t hri_sdadc_anactrl_reg_t; +typedef uint8_t hri_sdadc_ctrla_reg_t; +typedef uint8_t hri_sdadc_ctrlc_reg_t; +typedef uint8_t hri_sdadc_dbgctrl_reg_t; +typedef uint8_t hri_sdadc_evctrl_reg_t; +typedef uint8_t hri_sdadc_inputctrl_reg_t; +typedef uint8_t hri_sdadc_intenset_reg_t; +typedef uint8_t hri_sdadc_intflag_reg_t; +typedef uint8_t hri_sdadc_refctrl_reg_t; +typedef uint8_t hri_sdadc_seqctrl_reg_t; +typedef uint8_t hri_sdadc_seqstatus_reg_t; +typedef uint8_t hri_sdadc_shiftcorr_reg_t; +typedef uint8_t hri_sdadc_swtrig_reg_t; +typedef uint8_t hri_sdadc_winctrl_reg_t; + +static inline void hri_sdadc_wait_for_sync(const void *const hw, hri_sdadc_syncbusy_reg_t reg) +{ + while (((Sdadc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sdadc_is_syncing(const void *const hw, hri_sdadc_syncbusy_reg_t reg) +{ + return ((Sdadc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_sdadc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_RESRDY) >> SDADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_RESRDY; +} + +static inline bool hri_sdadc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_OVERRUN) >> SDADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_OVERRUN; +} + +static inline bool hri_sdadc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_WINMON) >> SDADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_sdadc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_WINMON; +} + +static inline bool hri_sdadc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_RESRDY) >> SDADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_sdadc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_RESRDY; +} + +static inline bool hri_sdadc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_OVERRUN) >> SDADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_sdadc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_OVERRUN; +} + +static inline bool hri_sdadc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTFLAG.reg & SDADC_INTFLAG_WINMON) >> SDADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_sdadc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTFLAG.reg = SDADC_INTFLAG_WINMON; +} + +static inline hri_sdadc_intflag_reg_t hri_sdadc_get_INTFLAG_reg(const void *const hw, hri_sdadc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_intflag_reg_t hri_sdadc_read_INTFLAG_reg(const void *const hw) +{ + return ((Sdadc *)hw)->INTFLAG.reg; +} + +static inline void hri_sdadc_clear_INTFLAG_reg(const void *const hw, hri_sdadc_intflag_reg_t mask) +{ + ((Sdadc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_sdadc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_RESRDY; +} + +static inline bool hri_sdadc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_RESRDY) >> SDADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_sdadc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_RESRDY; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_RESRDY; + } +} + +static inline void hri_sdadc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_RESRDY; +} + +static inline void hri_sdadc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_OVERRUN; +} + +static inline bool hri_sdadc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_OVERRUN) >> SDADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_sdadc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_OVERRUN; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_OVERRUN; + } +} + +static inline void hri_sdadc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_OVERRUN; +} + +static inline void hri_sdadc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_WINMON; +} + +static inline bool hri_sdadc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Sdadc *)hw)->INTENSET.reg & SDADC_INTENSET_WINMON) >> SDADC_INTENSET_WINMON_Pos; +} + +static inline void hri_sdadc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_WINMON; + } else { + ((Sdadc *)hw)->INTENSET.reg = SDADC_INTENSET_WINMON; + } +} + +static inline void hri_sdadc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Sdadc *)hw)->INTENCLR.reg = SDADC_INTENSET_WINMON; +} + +static inline void hri_sdadc_set_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + ((Sdadc *)hw)->INTENSET.reg = mask; +} + +static inline hri_sdadc_intenset_reg_t hri_sdadc_get_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_intenset_reg_t hri_sdadc_read_INTEN_reg(const void *const hw) +{ + return ((Sdadc *)hw)->INTENSET.reg; +} + +static inline void hri_sdadc_write_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t data) +{ + ((Sdadc *)hw)->INTENSET.reg = data; + ((Sdadc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_sdadc_clear_INTEN_reg(const void *const hw, hri_sdadc_intenset_reg_t mask) +{ + ((Sdadc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_sdadc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQBUSY) >> SDADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_sdadc_seqstatus_reg_t mask) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE(mask)) >> SDADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Sdadc *)hw)->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE_Msk) >> SDADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_get_SEQSTATUS_reg(const void *const hw, + hri_sdadc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_seqstatus_reg_t hri_sdadc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SWRST) >> SDADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_ENABLE) >> SDADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_CTRLC) >> SDADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_INPUTCTRL) >> SDADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINCTRL) >> SDADC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINLT) >> SDADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_WINUT) >> SDADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_OFFSETCORR) >> SDADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_GAINCORR) >> SDADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SHIFTCORR_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SHIFTCORR) >> SDADC_SYNCBUSY_SHIFTCORR_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_SWTRIG) >> SDADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline bool hri_sdadc_get_SYNCBUSY_ANACTRL_bit(const void *const hw) +{ + return (((Sdadc *)hw)->SYNCBUSY.reg & SDADC_SYNCBUSY_ANACTRL) >> SDADC_SYNCBUSY_ANACTRL_Pos; +} + +static inline hri_sdadc_syncbusy_reg_t hri_sdadc_get_SYNCBUSY_reg(const void *const hw, hri_sdadc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdadc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_syncbusy_reg_t hri_sdadc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SYNCBUSY.reg; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_RESULT_bf(const void *const hw, hri_sdadc_result_reg_t mask) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESULT(mask)) >> SDADC_RESULT_RESULT_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESULT_Msk) >> SDADC_RESULT_RESULT_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_RESERVED_bf(const void *const hw, hri_sdadc_result_reg_t mask) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESERVED(mask)) >> SDADC_RESULT_RESERVED_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_RESERVED_bf(const void *const hw) +{ + return (((Sdadc *)hw)->RESULT.reg & SDADC_RESULT_RESERVED_Msk) >> SDADC_RESULT_RESERVED_Pos; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_get_RESULT_reg(const void *const hw, hri_sdadc_result_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdadc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdadc_result_reg_t hri_sdadc_read_RESULT_reg(const void *const hw) +{ + return ((Sdadc *)hw)->RESULT.reg; +} + +static inline void hri_sdadc_set_CTRLA_SWRST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_SWRST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_SWRST) >> SDADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_ENABLE) >> SDADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_ENABLE; + tmp |= value << SDADC_CTRLA_ENABLE_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_ENABLE; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_RUNSTDBY) >> SDADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_RUNSTDBY; + tmp |= value << SDADC_CTRLA_RUNSTDBY_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_RUNSTDBY; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp = (tmp & SDADC_CTRLA_ONDEMAND) >> SDADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= ~SDADC_CTRLA_ONDEMAND; + tmp |= value << SDADC_CTRLA_ONDEMAND_Pos; + ((Sdadc *)hw)->CTRLA.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= SDADC_CTRLA_ONDEMAND; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrla_reg_t hri_sdadc_get_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + tmp = ((Sdadc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLA_reg(const void *const hw, hri_sdadc_ctrla_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLA.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrla_reg_t hri_sdadc_read_CTRLA_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SWRST | SDADC_SYNCBUSY_ENABLE); + return ((Sdadc *)hw)->CTRLA.reg; +} + +static inline void hri_sdadc_set_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_ONREFBUF) >> SDADC_REFCTRL_ONREFBUF_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_REFCTRL_ONREFBUF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_ONREFBUF; + tmp |= value << SDADC_REFCTRL_ONREFBUF_Pos; + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_ONREFBUF_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_ONREFBUF; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_REFSEL_bf(const void *const hw, + hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFSEL(mask)) >> SDADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_REFSEL_Msk; + tmp |= SDADC_REFCTRL_REFSEL(data); + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_REFSEL(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFSEL_Msk) >> SDADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_set_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_REFRANGE_bf(const void *const hw, + hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFRANGE(mask)) >> SDADC_REFCTRL_REFRANGE_Pos; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= ~SDADC_REFCTRL_REFRANGE_Msk; + tmp |= SDADC_REFCTRL_REFRANGE(data); + ((Sdadc *)hw)->REFCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_REFRANGE_bf(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= SDADC_REFCTRL_REFRANGE(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_REFRANGE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp = (tmp & SDADC_REFCTRL_REFRANGE_Msk) >> SDADC_REFCTRL_REFRANGE_Pos; + return tmp; +} + +static inline void hri_sdadc_set_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_get_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_REFCTRL_reg(const void *const hw, hri_sdadc_refctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->REFCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_refctrl_reg_t hri_sdadc_read_REFCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->REFCTRL.reg; +} + +static inline void hri_sdadc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_PRESCALER(mask)) >> SDADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_PRESCALER_Msk; + tmp |= SDADC_CTRLB_PRESCALER(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_PRESCALER(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_PRESCALER_Msk) >> SDADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_OSR(mask)) >> SDADC_CTRLB_OSR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_OSR_Msk; + tmp |= SDADC_CTRLB_OSR(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_OSR_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_OSR(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_OSR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_OSR_Msk) >> SDADC_CTRLB_OSR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_SKPCNT(mask)) >> SDADC_CTRLB_SKPCNT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= ~SDADC_CTRLB_SKPCNT_Msk; + tmp |= SDADC_CTRLB_SKPCNT(data); + ((Sdadc *)hw)->CTRLB.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_SKPCNT_bf(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= SDADC_CTRLB_SKPCNT(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_SKPCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp = (tmp & SDADC_CTRLB_SKPCNT_Msk) >> SDADC_CTRLB_SKPCNT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_get_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdadc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLB_reg(const void *const hw, hri_sdadc_ctrlb_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLB.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlb_reg_t hri_sdadc_read_CTRLB_reg(const void *const hw) +{ + return ((Sdadc *)hw)->CTRLB.reg; +} + +static inline void hri_sdadc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_FLUSHEI) >> SDADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_FLUSHEI; + tmp |= value << SDADC_EVCTRL_FLUSHEI_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_FLUSHEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_STARTEI) >> SDADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_STARTEI; + tmp |= value << SDADC_EVCTRL_STARTEI_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_STARTEI; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_FLUSHINV) >> SDADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_FLUSHINV; + tmp |= value << SDADC_EVCTRL_FLUSHINV_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_FLUSHINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_STARTINV) >> SDADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_STARTINV; + tmp |= value << SDADC_EVCTRL_STARTINV_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_STARTINV; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_RESRDYEO) >> SDADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_RESRDYEO; + tmp |= value << SDADC_EVCTRL_RESRDYEO_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_RESRDYEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp = (tmp & SDADC_EVCTRL_WINMONEO) >> SDADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= ~SDADC_EVCTRL_WINMONEO; + tmp |= value << SDADC_EVCTRL_WINMONEO_Pos; + ((Sdadc *)hw)->EVCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= SDADC_EVCTRL_WINMONEO; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_evctrl_reg_t hri_sdadc_get_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_EVCTRL_reg(const void *const hw, hri_sdadc_evctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->EVCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_evctrl_reg_t hri_sdadc_read_EVCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->EVCTRL.reg; +} + +static inline void hri_sdadc_set_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg |= SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_get_INPUTCTRL_MUXSEL_bf(const void *const hw, + hri_sdadc_inputctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp = (tmp & SDADC_INPUTCTRL_MUXSEL(mask)) >> SDADC_INPUTCTRL_MUXSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_write_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp &= ~SDADC_INPUTCTRL_MUXSEL_Msk; + tmp |= SDADC_INPUTCTRL_MUXSEL(data); + ((Sdadc *)hw)->INPUTCTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg &= ~SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_INPUTCTRL_MUXSEL_bf(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg ^= SDADC_INPUTCTRL_MUXSEL(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_read_INPUTCTRL_MUXSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp = (tmp & SDADC_INPUTCTRL_MUXSEL_Msk) >> SDADC_INPUTCTRL_MUXSEL_Pos; + return tmp; +} + +static inline void hri_sdadc_set_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_get_INPUTCTRL_reg(const void *const hw, + hri_sdadc_inputctrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_INPUTCTRL_reg(const void *const hw, hri_sdadc_inputctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->INPUTCTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_inputctrl_reg_t hri_sdadc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_sdadc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg |= SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp = (tmp & SDADC_CTRLC_FREERUN) >> SDADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp &= ~SDADC_CTRLC_FREERUN; + tmp |= value << SDADC_CTRLC_FREERUN_Pos; + ((Sdadc *)hw)->CTRLC.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg &= ~SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg ^= SDADC_CTRLC_FREERUN; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlc_reg_t hri_sdadc_get_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_CTRLC_reg(const void *const hw, hri_sdadc_ctrlc_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->CTRLC.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_ctrlc_reg_t hri_sdadc_read_CTRLC_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->CTRLC.reg; +} + +static inline void hri_sdadc_set_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg |= SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_get_WINCTRL_WINMODE_bf(const void *const hw, + hri_sdadc_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp = (tmp & SDADC_WINCTRL_WINMODE(mask)) >> SDADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp &= ~SDADC_WINCTRL_WINMODE_Msk; + tmp |= SDADC_WINCTRL_WINMODE(data); + ((Sdadc *)hw)->WINCTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg &= ~SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINCTRL_WINMODE_bf(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg ^= SDADC_WINCTRL_WINMODE(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_read_WINCTRL_WINMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp = (tmp & SDADC_WINCTRL_WINMODE_Msk) >> SDADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_get_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINCTRL_reg(const void *const hw, hri_sdadc_winctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINCTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winctrl_reg_t hri_sdadc_read_WINCTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->WINCTRL.reg; +} + +static inline void hri_sdadc_set_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg |= SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_get_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp = (tmp & SDADC_WINLT_WINLT(mask)) >> SDADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp &= ~SDADC_WINLT_WINLT_Msk; + tmp |= SDADC_WINLT_WINLT(data); + ((Sdadc *)hw)->WINLT.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg &= ~SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINLT_WINLT_bf(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg ^= SDADC_WINLT_WINLT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp = (tmp & SDADC_WINLT_WINLT_Msk) >> SDADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_get_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + tmp = ((Sdadc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINLT_reg(const void *const hw, hri_sdadc_winlt_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINLT.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winlt_reg_t hri_sdadc_read_WINLT_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINLT); + return ((Sdadc *)hw)->WINLT.reg; +} + +static inline void hri_sdadc_set_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg |= SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_get_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp = (tmp & SDADC_WINUT_WINUT(mask)) >> SDADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_sdadc_write_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp &= ~SDADC_WINUT_WINUT_Msk; + tmp |= SDADC_WINUT_WINUT(data); + ((Sdadc *)hw)->WINUT.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg &= ~SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINUT_WINUT_bf(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg ^= SDADC_WINUT_WINUT(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp = (tmp & SDADC_WINUT_WINUT_Msk) >> SDADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_sdadc_set_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_get_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + tmp = ((Sdadc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_WINUT_reg(const void *const hw, hri_sdadc_winut_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->WINUT.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_winut_reg_t hri_sdadc_read_WINUT_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_WINUT); + return ((Sdadc *)hw)->WINUT.reg; +} + +static inline void hri_sdadc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg |= SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_sdadc_offsetcorr_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp = (tmp & SDADC_OFFSETCORR_OFFSETCORR(mask)) >> SDADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t data) +{ + uint32_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp &= ~SDADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= SDADC_OFFSETCORR_OFFSETCORR(data); + ((Sdadc *)hw)->OFFSETCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg &= ~SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg ^= SDADC_OFFSETCORR_OFFSETCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp = (tmp & SDADC_OFFSETCORR_OFFSETCORR_Msk) >> SDADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_get_OFFSETCORR_reg(const void *const hw, + hri_sdadc_offsetcorr_reg_t mask) +{ + uint32_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + tmp = ((Sdadc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_OFFSETCORR_reg(const void *const hw, hri_sdadc_offsetcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->OFFSETCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_offsetcorr_reg_t hri_sdadc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_OFFSETCORR); + return ((Sdadc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_sdadc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg |= SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_get_GAINCORR_GAINCORR_bf(const void *const hw, + hri_sdadc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp = (tmp & SDADC_GAINCORR_GAINCORR(mask)) >> SDADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t data) +{ + uint16_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp &= ~SDADC_GAINCORR_GAINCORR_Msk; + tmp |= SDADC_GAINCORR_GAINCORR(data); + ((Sdadc *)hw)->GAINCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg &= ~SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg ^= SDADC_GAINCORR_GAINCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp = (tmp & SDADC_GAINCORR_GAINCORR_Msk) >> SDADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_get_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + tmp = ((Sdadc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_GAINCORR_reg(const void *const hw, hri_sdadc_gaincorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->GAINCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_gaincorr_reg_t hri_sdadc_read_GAINCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_GAINCORR); + return ((Sdadc *)hw)->GAINCORR.reg; +} + +static inline void hri_sdadc_set_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg |= SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_get_SHIFTCORR_SHIFTCORR_bf(const void *const hw, + hri_sdadc_shiftcorr_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp = (tmp & SDADC_SHIFTCORR_SHIFTCORR(mask)) >> SDADC_SHIFTCORR_SHIFTCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_write_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp &= ~SDADC_SHIFTCORR_SHIFTCORR_Msk; + tmp |= SDADC_SHIFTCORR_SHIFTCORR(data); + ((Sdadc *)hw)->SHIFTCORR.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg &= ~SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SHIFTCORR_SHIFTCORR_bf(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg ^= SDADC_SHIFTCORR_SHIFTCORR(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_read_SHIFTCORR_SHIFTCORR_bf(const void *const hw) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp = (tmp & SDADC_SHIFTCORR_SHIFTCORR_Msk) >> SDADC_SHIFTCORR_SHIFTCORR_Pos; + return tmp; +} + +static inline void hri_sdadc_set_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_get_SHIFTCORR_reg(const void *const hw, + hri_sdadc_shiftcorr_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + tmp = ((Sdadc *)hw)->SHIFTCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SHIFTCORR_reg(const void *const hw, hri_sdadc_shiftcorr_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SHIFTCORR.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_shiftcorr_reg_t hri_sdadc_read_SHIFTCORR_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_SHIFTCORR); + return ((Sdadc *)hw)->SHIFTCORR.reg; +} + +static inline void hri_sdadc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp = (tmp & SDADC_SWTRIG_FLUSH) >> SDADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= ~SDADC_SWTRIG_FLUSH; + tmp |= value << SDADC_SWTRIG_FLUSH_Pos; + ((Sdadc *)hw)->SWTRIG.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= SDADC_SWTRIG_FLUSH; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp = (tmp & SDADC_SWTRIG_START) >> SDADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= ~SDADC_SWTRIG_START; + tmp |= value << SDADC_SWTRIG_START_Pos; + ((Sdadc *)hw)->SWTRIG.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_START_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= SDADC_SWTRIG_START; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_swtrig_reg_t hri_sdadc_get_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SWTRIG_reg(const void *const hw, hri_sdadc_swtrig_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SWTRIG.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_swtrig_reg_t hri_sdadc_read_SWTRIG_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->SWTRIG.reg; +} + +static inline void hri_sdadc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg |= SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp = (tmp & SDADC_SEQCTRL_SEQEN(mask)) >> SDADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_sdadc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp &= ~SDADC_SEQCTRL_SEQEN_Msk; + tmp |= SDADC_SEQCTRL_SEQEN(data); + ((Sdadc *)hw)->SEQCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg &= ~SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg ^= SDADC_SEQCTRL_SEQEN(mask); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp = (tmp & SDADC_SEQCTRL_SEQEN_Msk) >> SDADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_sdadc_set_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_get_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_SEQCTRL_reg(const void *const hw, hri_sdadc_seqctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->SEQCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_seqctrl_reg_t hri_sdadc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->SEQCTRL.reg; +} + +static inline void hri_sdadc_set_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_ANACTRL_ONCHOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_ONCHOP) >> SDADC_ANACTRL_ONCHOP_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_ANACTRL_ONCHOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_ONCHOP; + tmp |= value << SDADC_ANACTRL_ONCHOP_Pos; + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_ONCHOP_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_ONCHOP; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_ANACTRL_BUFTEST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_BUFTEST) >> SDADC_ANACTRL_BUFTEST_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_ANACTRL_BUFTEST_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_BUFTEST; + tmp |= value << SDADC_ANACTRL_BUFTEST_Pos; + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_BUFTEST_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_BUFTEST; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_get_ANACTRL_CTRSDADC_bf(const void *const hw, + hri_sdadc_anactrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_CTRSDADC(mask)) >> SDADC_ANACTRL_CTRSDADC_Pos; + return tmp; +} + +static inline void hri_sdadc_write_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t data) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= ~SDADC_ANACTRL_CTRSDADC_Msk; + tmp |= SDADC_ANACTRL_CTRSDADC(data); + ((Sdadc *)hw)->ANACTRL.reg = tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_CTRSDADC_bf(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= SDADC_ANACTRL_CTRSDADC(mask); + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_read_ANACTRL_CTRSDADC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp = (tmp & SDADC_ANACTRL_CTRSDADC_Msk) >> SDADC_ANACTRL_CTRSDADC_Pos; + return tmp; +} + +static inline void hri_sdadc_set_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg |= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_get_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + uint8_t tmp; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + tmp = ((Sdadc *)hw)->ANACTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg = data; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg &= ~mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_ANACTRL_reg(const void *const hw, hri_sdadc_anactrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->ANACTRL.reg ^= mask; + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_anactrl_reg_t hri_sdadc_read_ANACTRL_reg(const void *const hw) +{ + hri_sdadc_wait_for_sync(hw, SDADC_SYNCBUSY_MASK); + return ((Sdadc *)hw)->ANACTRL.reg; +} + +static inline void hri_sdadc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg |= SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdadc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp = (tmp & SDADC_DBGCTRL_DBGRUN) >> SDADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdadc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDADC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp &= ~SDADC_DBGCTRL_DBGRUN; + tmp |= value << SDADC_DBGCTRL_DBGRUN_Pos; + ((Sdadc *)hw)->DBGCTRL.reg = tmp; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg &= ~SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg ^= SDADC_DBGCTRL_DBGRUN; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_set_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg |= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_dbgctrl_reg_t hri_sdadc_get_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdadc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdadc_write_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t data) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg = data; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_clear_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg &= ~mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdadc_toggle_DBGCTRL_reg(const void *const hw, hri_sdadc_dbgctrl_reg_t mask) +{ + SDADC_CRITICAL_SECTION_ENTER(); + ((Sdadc *)hw)->DBGCTRL.reg ^= mask; + SDADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdadc_dbgctrl_reg_t hri_sdadc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sdadc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDADC_C21_H_INCLUDED */ +#endif /* _SAMC21_SDADC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_sercom_c21.h b/bsp/microchip/samc21/bsp/hri/hri_sercom_c21.h new file mode 100644 index 0000000000..45d6580400 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_sercom_c21.h @@ -0,0 +1,7754 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_C21_H_INCLUDED_ +#define _HRI_SERCOM_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_C21_H_INCLUDED */ +#endif /* _SAMC21_SERCOM_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_supc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_supc_c21.h new file mode 100644 index 0000000000..23d7c42267 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_supc_c21.h @@ -0,0 +1,1560 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_C21_H_INCLUDED_ +#define _HRI_SUPC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bodcore_reg_t; +typedef uint32_t hri_supc_bodvdd_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDRDY) >> SUPC_INTFLAG_BODVDDRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY; +} + +static inline bool hri_supc_get_INTFLAG_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDDET) >> SUPC_INTFLAG_BODVDDDET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET; +} + +static inline bool hri_supc_get_INTFLAG_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BVDDSRDY) >> SUPC_INTFLAG_BVDDSRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BVDDSRDY; +} + +static inline bool hri_supc_get_INTFLAG_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCORERDY) >> SUPC_INTFLAG_BODCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCORERDY; +} + +static inline bool hri_supc_get_INTFLAG_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCOREDET) >> SUPC_INTFLAG_BODCOREDET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCOREDET; +} + +static inline bool hri_supc_get_INTFLAG_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BCORESRDY) >> SUPC_INTFLAG_BCORESRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BCORESRDY; +} + +static inline bool hri_supc_get_interrupt_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDRDY) >> SUPC_INTFLAG_BODVDDRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY; +} + +static inline bool hri_supc_get_interrupt_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODVDDDET) >> SUPC_INTFLAG_BODVDDDET_Pos; +} + +static inline void hri_supc_clear_interrupt_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET; +} + +static inline bool hri_supc_get_interrupt_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BVDDSRDY) >> SUPC_INTFLAG_BVDDSRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BVDDSRDY; +} + +static inline bool hri_supc_get_interrupt_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCORERDY) >> SUPC_INTFLAG_BODCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCORERDY; +} + +static inline bool hri_supc_get_interrupt_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BODCOREDET) >> SUPC_INTFLAG_BODCOREDET_Pos; +} + +static inline void hri_supc_clear_interrupt_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BODCOREDET; +} + +static inline bool hri_supc_get_interrupt_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BCORESRDY) >> SUPC_INTFLAG_BCORESRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BCORESRDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDRDY; +} + +static inline bool hri_supc_get_INTEN_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODVDDRDY) >> SUPC_INTENSET_BODVDDRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BODVDDRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDRDY; + } +} + +static inline void hri_supc_clear_INTEN_BODVDDRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDRDY; +} + +static inline void hri_supc_set_INTEN_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDDET; +} + +static inline bool hri_supc_get_INTEN_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODVDDDET) >> SUPC_INTENSET_BODVDDDET_Pos; +} + +static inline void hri_supc_write_INTEN_BODVDDDET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDDET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODVDDDET; + } +} + +static inline void hri_supc_clear_INTEN_BODVDDDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODVDDDET; +} + +static inline void hri_supc_set_INTEN_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BVDDSRDY; +} + +static inline bool hri_supc_get_INTEN_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BVDDSRDY) >> SUPC_INTENSET_BVDDSRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BVDDSRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BVDDSRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BVDDSRDY; + } +} + +static inline void hri_supc_clear_INTEN_BVDDSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BVDDSRDY; +} + +static inline void hri_supc_set_INTEN_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCORERDY; +} + +static inline bool hri_supc_get_INTEN_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODCORERDY) >> SUPC_INTENSET_BODCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_BODCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_BODCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCORERDY; +} + +static inline void hri_supc_set_INTEN_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCOREDET; +} + +static inline bool hri_supc_get_INTEN_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BODCOREDET) >> SUPC_INTENSET_BODCOREDET_Pos; +} + +static inline void hri_supc_write_INTEN_BODCOREDET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCOREDET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BODCOREDET; + } +} + +static inline void hri_supc_clear_INTEN_BODCOREDET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BODCOREDET; +} + +static inline void hri_supc_set_INTEN_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BCORESRDY; +} + +static inline bool hri_supc_get_INTEN_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BCORESRDY) >> SUPC_INTENSET_BCORESRDY_Pos; +} + +static inline void hri_supc_write_INTEN_BCORESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BCORESRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BCORESRDY; + } +} + +static inline void hri_supc_clear_INTEN_BCORESRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BCORESRDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BODVDDRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODVDDRDY) >> SUPC_STATUS_BODVDDRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODVDDDET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODVDDDET) >> SUPC_STATUS_BODVDDDET_Pos; +} + +static inline bool hri_supc_get_STATUS_BVDDSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BVDDSRDY) >> SUPC_STATUS_BVDDSRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODCORERDY) >> SUPC_STATUS_BODCORERDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BODCOREDET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BODCOREDET) >> SUPC_STATUS_BODCOREDET_Pos; +} + +static inline bool hri_supc_get_STATUS_BCORESRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BCORESRDY) >> SUPC_STATUS_BCORESRDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline void hri_supc_set_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ENABLE) >> SUPC_BODVDD_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ENABLE; + tmp |= value << SUPC_BODVDD_ENABLE_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_HYST) >> SUPC_BODVDD_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_HYST; + tmp |= value << SUPC_BODVDD_HYST_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_STDBYCFG) >> SUPC_BODVDD_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_STDBYCFG; + tmp |= value << SUPC_BODVDD_STDBYCFG_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_RUNSTDBY) >> SUPC_BODVDD_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_RUNSTDBY; + tmp |= value << SUPC_BODVDD_RUNSTDBY_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODVDD_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTCFG) >> SUPC_BODVDD_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODVDD_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ACTCFG; + tmp |= value << SUPC_BODVDD_ACTCFG_Pos; + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTION(mask)) >> SUPC_BODVDD_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_ACTION_Msk; + tmp |= SUPC_BODVDD_ACTION(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_ACTION_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_ACTION_Msk) >> SUPC_BODVDD_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_PSEL(mask)) >> SUPC_BODVDD_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_PSEL_Msk; + tmp |= SUPC_BODVDD_PSEL(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_PSEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_PSEL_Msk) >> SUPC_BODVDD_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_LEVEL(mask)) >> SUPC_BODVDD_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= ~SUPC_BODVDD_LEVEL_Msk; + tmp |= SUPC_BODVDD_LEVEL(data); + ((Supc *)hw)->BODVDD.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_LEVEL_bf(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= SUPC_BODVDD_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp = (tmp & SUPC_BODVDD_LEVEL_Msk) >> SUPC_BODVDD_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_get_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODVDD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODVDD_reg(const void *const hw, hri_supc_bodvdd_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODVDD.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodvdd_reg_t hri_supc_read_BODVDD_reg(const void *const hw) +{ + return ((Supc *)hw)->BODVDD.reg; +} + +static inline void hri_supc_set_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ENABLE) >> SUPC_BODCORE_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ENABLE; + tmp |= value << SUPC_BODCORE_ENABLE_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_HYST) >> SUPC_BODCORE_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_HYST; + tmp |= value << SUPC_BODCORE_HYST_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_STDBYCFG) >> SUPC_BODCORE_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_STDBYCFG; + tmp |= value << SUPC_BODCORE_STDBYCFG_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_RUNSTDBY) >> SUPC_BODCORE_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_RUNSTDBY; + tmp |= value << SUPC_BODCORE_RUNSTDBY_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BODCORE_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTCFG) >> SUPC_BODCORE_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BODCORE_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ACTCFG; + tmp |= value << SUPC_BODCORE_ACTCFG_Pos; + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTION(mask)) >> SUPC_BODCORE_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_ACTION_Msk; + tmp |= SUPC_BODCORE_ACTION(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_ACTION_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_ACTION_Msk) >> SUPC_BODCORE_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_PSEL(mask)) >> SUPC_BODCORE_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_PSEL_Msk; + tmp |= SUPC_BODCORE_PSEL(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_PSEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_PSEL_Msk) >> SUPC_BODCORE_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_LEVEL(mask)) >> SUPC_BODCORE_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= ~SUPC_BODCORE_LEVEL_Msk; + tmp |= SUPC_BODCORE_LEVEL(data); + ((Supc *)hw)->BODCORE.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_LEVEL_bf(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= SUPC_BODCORE_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp = (tmp & SUPC_BODCORE_LEVEL_Msk) >> SUPC_BODCORE_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_get_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BODCORE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BODCORE_reg(const void *const hw, hri_supc_bodcore_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BODCORE.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bodcore_reg_t hri_supc_read_BODCORE_reg(const void *const hw) +{ + return ((Supc *)hw)->BODCORE.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNSTDBY; + tmp |= value << SUPC_VREG_RUNSTDBY_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_C21_H_INCLUDED */ +#endif /* _SAMC21_SUPC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_systemcontrol_c21.h b/bsp/microchip/samc21/bsp/hri/hri_systemcontrol_c21.h new file mode 100644 index 0000000000..9008bafe30 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_systemcontrol_c21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_C21_H_INCLUDED_ +#define _HRI_SystemControl_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_dfsr_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shcsr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, + hri_systemcontrol_shcsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHCSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHCSR.reg; +} + +static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, + hri_systemcontrol_dfsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->DFSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->DFSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_C21_H_INCLUDED */ +#endif /* _SAMC21_SystemControl_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_systick_c21.h b/bsp/microchip/samc21/bsp/hri/hri_systick_c21.h new file mode 100644 index 0000000000..9ef6146513 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_systick_c21.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_C21_H_INCLUDED_ +#define _HRI_SysTick_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_C21_H_INCLUDED */ +#endif /* _SAMC21_SysTick_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_tc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_tc_c21.h new file mode 100644 index 0000000000..6f36089148 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_tc_c21.h @@ -0,0 +1,2899 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TC_COMPONENT_ +#ifndef _HRI_TC_C21_H_INCLUDED_ +#define _HRI_TC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_C21_H_INCLUDED */ +#endif /* _SAMC21_TC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_tcc_c21.h b/bsp/microchip/samc21/bsp/hri/hri_tcc_c21.h new file mode 100644 index 0000000000..bbaa631cb1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_tcc_c21.h @@ -0,0 +1,9462 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TCC_COMPONENT_ +#ifndef _HRI_TCC_C21_H_INCLUDED_ +#define _HRI_TCC_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_C21_H_INCLUDED */ +#endif /* _SAMC21_TCC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_tsens_c21.h b/bsp/microchip/samc21/bsp/hri/hri_tsens_c21.h new file mode 100644 index 0000000000..596ad8a629 --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_tsens_c21.h @@ -0,0 +1,1396 @@ +/** + * \file + * + * \brief SAM TSENS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_TSENS_COMPONENT_ +#ifndef _HRI_TSENS_C21_H_INCLUDED_ +#define _HRI_TSENS_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TSENS_CRITICAL_SECTIONS) +#define TSENS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TSENS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TSENS_CRITICAL_SECTION_ENTER() +#define TSENS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_tsens_cal_reg_t; +typedef uint32_t hri_tsens_gain_reg_t; +typedef uint32_t hri_tsens_offset_reg_t; +typedef uint32_t hri_tsens_syncbusy_reg_t; +typedef uint32_t hri_tsens_value_reg_t; +typedef uint32_t hri_tsens_winlt_reg_t; +typedef uint32_t hri_tsens_winut_reg_t; +typedef uint8_t hri_tsens_ctrla_reg_t; +typedef uint8_t hri_tsens_ctrlb_reg_t; +typedef uint8_t hri_tsens_ctrlc_reg_t; +typedef uint8_t hri_tsens_dbgctrl_reg_t; +typedef uint8_t hri_tsens_evctrl_reg_t; +typedef uint8_t hri_tsens_intenset_reg_t; +typedef uint8_t hri_tsens_intflag_reg_t; +typedef uint8_t hri_tsens_status_reg_t; + +static inline void hri_tsens_wait_for_sync(const void *const hw, hri_tsens_syncbusy_reg_t reg) +{ + while (((Tsens *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tsens_is_syncing(const void *const hw, hri_tsens_syncbusy_reg_t reg) +{ + return ((Tsens *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tsens_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_RESRDY) >> TSENS_INTFLAG_RESRDY_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_RESRDY; +} + +static inline bool hri_tsens_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVERRUN) >> TSENS_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVERRUN; +} + +static inline bool hri_tsens_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_WINMON) >> TSENS_INTFLAG_WINMON_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_WINMON; +} + +static inline bool hri_tsens_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVF) >> TSENS_INTFLAG_OVF_Pos; +} + +static inline void hri_tsens_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVF; +} + +static inline bool hri_tsens_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_RESRDY) >> TSENS_INTFLAG_RESRDY_Pos; +} + +static inline void hri_tsens_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_RESRDY; +} + +static inline bool hri_tsens_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVERRUN) >> TSENS_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_tsens_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVERRUN; +} + +static inline bool hri_tsens_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_WINMON) >> TSENS_INTFLAG_WINMON_Pos; +} + +static inline void hri_tsens_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_WINMON; +} + +static inline bool hri_tsens_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTFLAG.reg & TSENS_INTFLAG_OVF) >> TSENS_INTFLAG_OVF_Pos; +} + +static inline void hri_tsens_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTFLAG.reg = TSENS_INTFLAG_OVF; +} + +static inline hri_tsens_intflag_reg_t hri_tsens_get_INTFLAG_reg(const void *const hw, hri_tsens_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_intflag_reg_t hri_tsens_read_INTFLAG_reg(const void *const hw) +{ + return ((Tsens *)hw)->INTFLAG.reg; +} + +static inline void hri_tsens_clear_INTFLAG_reg(const void *const hw, hri_tsens_intflag_reg_t mask) +{ + ((Tsens *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tsens_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_RESRDY; +} + +static inline bool hri_tsens_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_RESRDY) >> TSENS_INTENSET_RESRDY_Pos; +} + +static inline void hri_tsens_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_RESRDY; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_RESRDY; + } +} + +static inline void hri_tsens_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_RESRDY; +} + +static inline void hri_tsens_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVERRUN; +} + +static inline bool hri_tsens_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_OVERRUN) >> TSENS_INTENSET_OVERRUN_Pos; +} + +static inline void hri_tsens_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVERRUN; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVERRUN; + } +} + +static inline void hri_tsens_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVERRUN; +} + +static inline void hri_tsens_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_WINMON; +} + +static inline bool hri_tsens_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_WINMON) >> TSENS_INTENSET_WINMON_Pos; +} + +static inline void hri_tsens_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_WINMON; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_WINMON; + } +} + +static inline void hri_tsens_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_WINMON; +} + +static inline void hri_tsens_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVF; +} + +static inline bool hri_tsens_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->INTENSET.reg & TSENS_INTENSET_OVF) >> TSENS_INTENSET_OVF_Pos; +} + +static inline void hri_tsens_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVF; + } else { + ((Tsens *)hw)->INTENSET.reg = TSENS_INTENSET_OVF; + } +} + +static inline void hri_tsens_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tsens *)hw)->INTENCLR.reg = TSENS_INTENSET_OVF; +} + +static inline void hri_tsens_set_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + ((Tsens *)hw)->INTENSET.reg = mask; +} + +static inline hri_tsens_intenset_reg_t hri_tsens_get_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_intenset_reg_t hri_tsens_read_INTEN_reg(const void *const hw) +{ + return ((Tsens *)hw)->INTENSET.reg; +} + +static inline void hri_tsens_write_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t data) +{ + ((Tsens *)hw)->INTENSET.reg = data; + ((Tsens *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tsens_clear_INTEN_reg(const void *const hw, hri_tsens_intenset_reg_t mask) +{ + ((Tsens *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tsens_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Tsens *)hw)->STATUS.reg & TSENS_STATUS_OVF) >> TSENS_STATUS_OVF_Pos; +} + +static inline hri_tsens_status_reg_t hri_tsens_get_STATUS_reg(const void *const hw, hri_tsens_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_status_reg_t hri_tsens_read_STATUS_reg(const void *const hw) +{ + return ((Tsens *)hw)->STATUS.reg; +} + +static inline bool hri_tsens_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tsens *)hw)->SYNCBUSY.reg & TSENS_SYNCBUSY_SWRST) >> TSENS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tsens_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tsens *)hw)->SYNCBUSY.reg & TSENS_SYNCBUSY_ENABLE) >> TSENS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_tsens_syncbusy_reg_t hri_tsens_get_SYNCBUSY_reg(const void *const hw, hri_tsens_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_syncbusy_reg_t hri_tsens_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tsens *)hw)->SYNCBUSY.reg; +} + +static inline hri_tsens_value_reg_t hri_tsens_get_VALUE_VALUE_bf(const void *const hw, hri_tsens_value_reg_t mask) +{ + return (((Tsens *)hw)->VALUE.reg & TSENS_VALUE_VALUE(mask)) >> TSENS_VALUE_VALUE_Pos; +} + +static inline hri_tsens_value_reg_t hri_tsens_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Tsens *)hw)->VALUE.reg & TSENS_VALUE_VALUE_Msk) >> TSENS_VALUE_VALUE_Pos; +} + +static inline hri_tsens_value_reg_t hri_tsens_get_VALUE_reg(const void *const hw, hri_tsens_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tsens_value_reg_t hri_tsens_read_VALUE_reg(const void *const hw) +{ + return ((Tsens *)hw)->VALUE.reg; +} + +static inline void hri_tsens_set_CTRLA_SWRST_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_SWRST; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_SWRST) >> TSENS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_ENABLE) >> TSENS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= ~TSENS_CTRLA_ENABLE; + tmp |= value << TSENS_CTRLA_ENABLE_Pos; + ((Tsens *)hw)->CTRLA.reg = tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= TSENS_CTRLA_ENABLE; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_SWRST | TSENS_SYNCBUSY_ENABLE); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp = (tmp & TSENS_CTRLA_RUNSTDBY) >> TSENS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= ~TSENS_CTRLA_RUNSTDBY; + tmp |= value << TSENS_CTRLA_RUNSTDBY_Pos; + ((Tsens *)hw)->CTRLA.reg = tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= TSENS_CTRLA_RUNSTDBY; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg |= mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrla_reg_t hri_tsens_get_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + tmp = ((Tsens *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg = data; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg &= ~mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLA_reg(const void *const hw, hri_tsens_ctrla_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLA.reg ^= mask; + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrla_reg_t hri_tsens_read_CTRLA_reg(const void *const hw) +{ + hri_tsens_wait_for_sync(hw, TSENS_SYNCBUSY_MASK); + return ((Tsens *)hw)->CTRLA.reg; +} + +static inline void hri_tsens_set_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_FREERUN) >> TSENS_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= ~TSENS_CTRLC_FREERUN; + tmp |= value << TSENS_CTRLC_FREERUN_Pos; + ((Tsens *)hw)->CTRLC.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= TSENS_CTRLC_FREERUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_get_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_WINMODE(mask)) >> TSENS_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_tsens_write_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t data) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= ~TSENS_CTRLC_WINMODE_Msk; + tmp |= TSENS_CTRLC_WINMODE(data); + ((Tsens *)hw)->CTRLC.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= TSENS_CTRLC_WINMODE(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp = (tmp & TSENS_CTRLC_WINMODE_Msk) >> TSENS_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_tsens_set_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_get_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CTRLC_reg(const void *const hw, hri_tsens_ctrlc_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLC.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_ctrlc_reg_t hri_tsens_read_CTRLC_reg(const void *const hw) +{ + return ((Tsens *)hw)->CTRLC.reg; +} + +static inline void hri_tsens_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_STARTEI) >> TSENS_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_STARTEI; + tmp |= value << TSENS_EVCTRL_STARTEI_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_STARTEI; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_STARTINV) >> TSENS_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_STARTINV; + tmp |= value << TSENS_EVCTRL_STARTINV_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_STARTINV; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_EVCTRL_WINEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp = (tmp & TSENS_EVCTRL_WINEO) >> TSENS_EVCTRL_WINEO_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_EVCTRL_WINEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= ~TSENS_EVCTRL_WINEO; + tmp |= value << TSENS_EVCTRL_WINEO_Pos; + ((Tsens *)hw)->EVCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_WINEO_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= TSENS_EVCTRL_WINEO; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_evctrl_reg_t hri_tsens_get_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_EVCTRL_reg(const void *const hw, hri_tsens_evctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->EVCTRL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_evctrl_reg_t hri_tsens_read_EVCTRL_reg(const void *const hw) +{ + return ((Tsens *)hw)->EVCTRL.reg; +} + +static inline void hri_tsens_set_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg |= TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_get_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp = (tmp & TSENS_WINLT_WINLT(mask)) >> TSENS_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_tsens_write_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->WINLT.reg; + tmp &= ~TSENS_WINLT_WINLT_Msk; + tmp |= TSENS_WINLT_WINLT(data); + ((Tsens *)hw)->WINLT.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg &= ~TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINLT_WINLT_bf(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg ^= TSENS_WINLT_WINLT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_read_WINLT_WINLT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp = (tmp & TSENS_WINLT_WINLT_Msk) >> TSENS_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_tsens_set_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_get_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINLT_reg(const void *const hw, hri_tsens_winlt_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINLT.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winlt_reg_t hri_tsens_read_WINLT_reg(const void *const hw) +{ + return ((Tsens *)hw)->WINLT.reg; +} + +static inline void hri_tsens_set_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg |= TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_get_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp = (tmp & TSENS_WINUT_WINUT(mask)) >> TSENS_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_tsens_write_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->WINUT.reg; + tmp &= ~TSENS_WINUT_WINUT_Msk; + tmp |= TSENS_WINUT_WINUT(data); + ((Tsens *)hw)->WINUT.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg &= ~TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINUT_WINUT_bf(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg ^= TSENS_WINUT_WINUT(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_read_WINUT_WINUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp = (tmp & TSENS_WINUT_WINUT_Msk) >> TSENS_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_tsens_set_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_get_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_WINUT_reg(const void *const hw, hri_tsens_winut_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->WINUT.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_winut_reg_t hri_tsens_read_WINUT_reg(const void *const hw) +{ + return ((Tsens *)hw)->WINUT.reg; +} + +static inline void hri_tsens_set_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg |= TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_get_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp = (tmp & TSENS_GAIN_GAIN(mask)) >> TSENS_GAIN_GAIN_Pos; + return tmp; +} + +static inline void hri_tsens_write_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->GAIN.reg; + tmp &= ~TSENS_GAIN_GAIN_Msk; + tmp |= TSENS_GAIN_GAIN(data); + ((Tsens *)hw)->GAIN.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg &= ~TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_GAIN_GAIN_bf(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg ^= TSENS_GAIN_GAIN(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_read_GAIN_GAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp = (tmp & TSENS_GAIN_GAIN_Msk) >> TSENS_GAIN_GAIN_Pos; + return tmp; +} + +static inline void hri_tsens_set_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_get_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->GAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_GAIN_reg(const void *const hw, hri_tsens_gain_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->GAIN.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_gain_reg_t hri_tsens_read_GAIN_reg(const void *const hw) +{ + return ((Tsens *)hw)->GAIN.reg; +} + +static inline void hri_tsens_set_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg |= TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_get_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp = (tmp & TSENS_OFFSET_OFFSETC(mask)) >> TSENS_OFFSET_OFFSETC_Pos; + return tmp; +} + +static inline void hri_tsens_write_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp &= ~TSENS_OFFSET_OFFSETC_Msk; + tmp |= TSENS_OFFSET_OFFSETC(data); + ((Tsens *)hw)->OFFSET.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg &= ~TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_OFFSET_OFFSETC_bf(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg ^= TSENS_OFFSET_OFFSETC(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_read_OFFSET_OFFSETC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp = (tmp & TSENS_OFFSET_OFFSETC_Msk) >> TSENS_OFFSET_OFFSETC_Pos; + return tmp; +} + +static inline void hri_tsens_set_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_get_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->OFFSET.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_OFFSET_reg(const void *const hw, hri_tsens_offset_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->OFFSET.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_offset_reg_t hri_tsens_read_OFFSET_reg(const void *const hw) +{ + return ((Tsens *)hw)->OFFSET.reg; +} + +static inline void hri_tsens_set_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_FCAL(mask)) >> TSENS_CAL_FCAL_Pos; + return tmp; +} + +static inline void hri_tsens_write_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= ~TSENS_CAL_FCAL_Msk; + tmp |= TSENS_CAL_FCAL(data); + ((Tsens *)hw)->CAL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_FCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= TSENS_CAL_FCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_FCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_FCAL_Msk) >> TSENS_CAL_FCAL_Pos; + return tmp; +} + +static inline void hri_tsens_set_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_TCAL(mask)) >> TSENS_CAL_TCAL_Pos; + return tmp; +} + +static inline void hri_tsens_write_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t data) +{ + uint32_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= ~TSENS_CAL_TCAL_Msk; + tmp |= TSENS_CAL_TCAL(data); + ((Tsens *)hw)->CAL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_TCAL_bf(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= TSENS_CAL_TCAL(mask); + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_TCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp = (tmp & TSENS_CAL_TCAL_Msk) >> TSENS_CAL_TCAL_Pos; + return tmp; +} + +static inline void hri_tsens_set_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_get_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tsens *)hw)->CAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_CAL_reg(const void *const hw, hri_tsens_cal_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_CAL_reg(const void *const hw, hri_tsens_cal_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CAL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_cal_reg_t hri_tsens_read_CAL_reg(const void *const hw) +{ + return ((Tsens *)hw)->CAL.reg; +} + +static inline void hri_tsens_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg |= TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tsens_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp = (tmp & TSENS_DBGCTRL_DBGRUN) >> TSENS_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tsens_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TSENS_CRITICAL_SECTION_ENTER(); + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp &= ~TSENS_DBGCTRL_DBGRUN; + tmp |= value << TSENS_DBGCTRL_DBGRUN_Pos; + ((Tsens *)hw)->DBGCTRL.reg = tmp; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg &= ~TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg ^= TSENS_DBGCTRL_DBGRUN; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_set_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg |= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_dbgctrl_reg_t hri_tsens_get_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tsens *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tsens_write_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_clear_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg &= ~mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tsens_toggle_DBGCTRL_reg(const void *const hw, hri_tsens_dbgctrl_reg_t mask) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->DBGCTRL.reg ^= mask; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tsens_dbgctrl_reg_t hri_tsens_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tsens *)hw)->DBGCTRL.reg; +} + +static inline void hri_tsens_write_CTRLB_reg(const void *const hw, hri_tsens_ctrlb_reg_t data) +{ + TSENS_CRITICAL_SECTION_ENTER(); + ((Tsens *)hw)->CTRLB.reg = data; + TSENS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TSENS_C21_H_INCLUDED */ +#endif /* _SAMC21_TSENS_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/hri/hri_wdt_c21.h b/bsp/microchip/samc21/bsp/hri/hri_wdt_c21.h new file mode 100644 index 0000000000..21ca7381af --- /dev/null +++ b/bsp/microchip/samc21/bsp/hri/hri_wdt_c21.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAMC21_WDT_COMPONENT_ +#ifndef _HRI_WDT_C21_H_INCLUDED_ +#define _HRI_WDT_C21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_C21_H_INCLUDED */ +#endif /* _SAMC21_WDT_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/iar-project-connection.ipcf b/bsp/microchip/samc21/bsp/iar-project-connection.ipcf new file mode 100644 index 0000000000..f7a1ebb377 --- /dev/null +++ b/bsp/microchip/samc21/bsp/iar-project-connection.ipcf @@ -0,0 +1,412 @@ + + + + ATSAMC21J18A + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\can + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\divas + $PROJ_DIR$\hpl\dmac + $PROJ_DIR$\hpl\gclk + $PROJ_DIR$\hpl\mclk + $PROJ_DIR$\hpl\nvmctrl + $PROJ_DIR$\hpl\osc32kctrl + $PROJ_DIR$\hpl\oscctrl + $PROJ_DIR$\hpl\pm + $PROJ_DIR$\hpl\port + $PROJ_DIR$\hpl\sercom + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\samc21\include + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\can + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\divas + $PROJ_DIR$\hpl\dmac + $PROJ_DIR$\hpl\gclk + $PROJ_DIR$\hpl\mclk + $PROJ_DIR$\hpl\nvmctrl + $PROJ_DIR$\hpl\osc32kctrl + $PROJ_DIR$\hpl\oscctrl + $PROJ_DIR$\hpl\pm + $PROJ_DIR$\hpl\port + $PROJ_DIR$\hpl\sercom + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\samc21\include + + + + __SAMC21J18A__ + F_CPU=40001536 + + + + __SAMC21J18A__ + + + + True + $PROJ_DIR$\samc21\iar\iar\samc21j18a_flash.icf + + + + + atmel_start.c + atmel_start.h + atmel_start_pins.h + driver_init.c + driver_init.h + main.c + + + + CMSIS/Core/Include/cmsis_armcc.h + CMSIS/Core/Include/cmsis_armclang.h + CMSIS/Core/Include/cmsis_compiler.h + CMSIS/Core/Include/cmsis_gcc.h + CMSIS/Core/Include/cmsis_iccarm.h + CMSIS/Core/Include/cmsis_version.h + CMSIS/Core/Include/core_armv8mbl.h + CMSIS/Core/Include/core_armv8mml.h + CMSIS/Core/Include/core_cm0.h + CMSIS/Core/Include/core_cm0plus.h + CMSIS/Core/Include/core_cm1.h + CMSIS/Core/Include/core_cm23.h + CMSIS/Core/Include/core_cm3.h + CMSIS/Core/Include/core_cm33.h + CMSIS/Core/Include/core_cm4.h + CMSIS/Core/Include/core_cm7.h + CMSIS/Core/Include/core_sc000.h + CMSIS/Core/Include/core_sc300.h + CMSIS/Core/Include/mpu_armv7.h + CMSIS/Core/Include/mpu_armv8.h + CMSIS/Core/Include/tz_context.h + + + + config/hpl_can_config.h + config/hpl_divas_config.h + config/hpl_dmac_config.h + config/hpl_gclk_config.h + config/hpl_mclk_config.h + config/hpl_nvmctrl_config.h + config/hpl_osc32kctrl_config.h + config/hpl_oscctrl_config.h + config/hpl_port_config.h + config/hpl_sercom_config.h + config/peripheral_clk_config.h + + + + examples/driver_examples.c + examples/driver_examples.h + + + + hal/include/hal_atomic.h + hal/include/hal_can_async.h + hal/include/hal_delay.h + hal/include/hal_flash.h + hal/include/hal_gpio.h + hal/include/hal_init.h + hal/include/hal_io.h + hal/include/hal_sleep.h + hal/include/hal_usart_sync.h + hal/include/hpl_can.h + hal/include/hpl_can_async.h + hal/include/hpl_core.h + hal/include/hpl_delay.h + hal/include/hpl_div.h + hal/include/hpl_dma.h + hal/include/hpl_flash.h + hal/include/hpl_gpio.h + hal/include/hpl_i2c_m_async.h + hal/include/hpl_i2c_m_sync.h + hal/include/hpl_i2c_s_async.h + hal/include/hpl_i2c_s_sync.h + hal/include/hpl_init.h + hal/include/hpl_irq.h + hal/include/hpl_missing_features.h + hal/include/hpl_reset.h + hal/include/hpl_sleep.h + hal/include/hpl_spi.h + hal/include/hpl_spi_async.h + hal/include/hpl_spi_m_async.h + hal/include/hpl_spi_m_dma.h + hal/include/hpl_spi_m_sync.h + hal/include/hpl_spi_s_async.h + hal/include/hpl_spi_s_sync.h + hal/include/hpl_spi_sync.h + hal/include/hpl_usart.h + hal/include/hpl_usart_async.h + hal/include/hpl_usart_sync.h + hal/include/hpl_user_area.h + + + + hal/src/hal_atomic.c + hal/src/hal_can_async.c + hal/src/hal_delay.c + hal/src/hal_flash.c + hal/src/hal_gpio.c + hal/src/hal_init.c + hal/src/hal_io.c + hal/src/hal_sleep.c + hal/src/hal_usart_sync.c + + + + hal/utils/include/compiler.h + hal/utils/include/err_codes.h + hal/utils/include/events.h + hal/utils/include/parts.h + hal/utils/include/utils.h + hal/utils/include/utils_assert.h + hal/utils/include/utils_event.h + hal/utils/include/utils_increment_macro.h + hal/utils/include/utils_list.h + hal/utils/include/utils_repeat_macro.h + + + + hal/utils/src/utils_assert.c + hal/utils/src/utils_event.c + hal/utils/src/utils_list.c + + + + hpl/can/hpl_can.c + hpl/can/hpl_can_base.h + + + + hpl/core/hpl_core_m0plus_base.c + hpl/core/hpl_core_port.h + hpl/core/hpl_init.c + + + + hpl/divas/hpl_divas.c + + + + hpl/dmac/hpl_dmac.c + + + + hpl/gclk/hpl_gclk.c + hpl/gclk/hpl_gclk_base.h + + + + hpl/mclk/hpl_mclk.c + + + + hpl/nvmctrl/hpl_nvmctrl.c + + + + hpl/osc32kctrl/hpl_osc32kctrl.c + + + + hpl/oscctrl/hpl_oscctrl.c + + + + hpl/pm/hpl_pm.c + hpl/pm/hpl_pm_base.h + + + + hpl/port/hpl_gpio_base.h + + + + hpl/sercom/hpl_sercom.c + + + + hri/hri_ac_c21.h + hri/hri_adc_c21.h + hri/hri_c21.h + hri/hri_can_c21.h + hri/hri_ccl_c21.h + hri/hri_dac_c21.h + hri/hri_divas_c21.h + hri/hri_dmac_c21.h + hri/hri_dsu_c21.h + hri/hri_eic_c21.h + hri/hri_evsys_c21.h + hri/hri_freqm_c21.h + hri/hri_gclk_c21.h + hri/hri_hmatrixb_c21.h + hri/hri_mclk_c21.h + hri/hri_mpu_c21.h + hri/hri_mtb_c21.h + hri/hri_nvic_c21.h + hri/hri_nvmctrl_c21.h + hri/hri_osc32kctrl_c21.h + hri/hri_oscctrl_c21.h + hri/hri_pac_c21.h + hri/hri_pm_c21.h + hri/hri_port_c21.h + hri/hri_rstc_c21.h + hri/hri_rtc_c21.h + hri/hri_sdadc_c21.h + hri/hri_sercom_c21.h + hri/hri_supc_c21.h + hri/hri_systemcontrol_c21.h + hri/hri_systick_c21.h + hri/hri_tc_c21.h + hri/hri_tcc_c21.h + hri/hri_tsens_c21.h + hri/hri_wdt_c21.h + + + + samc21/iar/system_samc21.c + + + + samc21/iar/iar/startup_samc21.c + + + + samc21/include/component-version.h + samc21/include/sam.h + samc21/include/sam.h + samc21/include/samc21.h + samc21/include/samc21e15a.h + samc21/include/samc21e16a.h + samc21/include/samc21e17a.h + samc21/include/samc21e18a.h + samc21/include/samc21g15a.h + samc21/include/samc21g16a.h + samc21/include/samc21g17a.h + samc21/include/samc21g18a.h + samc21/include/samc21j15a.h + samc21/include/samc21j16a.h + samc21/include/samc21j17a.h + samc21/include/samc21j17au.h + samc21/include/samc21j18a.h + samc21/include/samc21j18au.h + samc21/include/system_samc21.h + + + + samc21/include/component/ac.h + samc21/include/component/adc.h + samc21/include/component/can.h + samc21/include/component/ccl.h + samc21/include/component/dac.h + samc21/include/component/divas.h + samc21/include/component/dmac.h + samc21/include/component/dsu.h + samc21/include/component/eic.h + samc21/include/component/evsys.h + samc21/include/component/freqm.h + samc21/include/component/gclk.h + samc21/include/component/hmatrixb.h + samc21/include/component/mclk.h + samc21/include/component/mtb.h + samc21/include/component/nvmctrl.h + samc21/include/component/osc32kctrl.h + samc21/include/component/oscctrl.h + samc21/include/component/pac.h + samc21/include/component/pm.h + samc21/include/component/port.h + samc21/include/component/rstc.h + samc21/include/component/rtc.h + samc21/include/component/sdadc.h + samc21/include/component/sercom.h + samc21/include/component/supc.h + samc21/include/component/tc.h + samc21/include/component/tcc.h + samc21/include/component/tsens.h + samc21/include/component/wdt.h + + + + samc21/include/instance/ac.h + samc21/include/instance/adc0.h + samc21/include/instance/adc1.h + samc21/include/instance/can0.h + samc21/include/instance/can1.h + samc21/include/instance/ccl.h + samc21/include/instance/dac.h + samc21/include/instance/divas.h + samc21/include/instance/dmac.h + samc21/include/instance/dsu.h + samc21/include/instance/eic.h + samc21/include/instance/evsys.h + samc21/include/instance/freqm.h + samc21/include/instance/gclk.h + samc21/include/instance/hmatrixhs.h + samc21/include/instance/mclk.h + samc21/include/instance/mtb.h + samc21/include/instance/nvmctrl.h + samc21/include/instance/osc32kctrl.h + samc21/include/instance/oscctrl.h + samc21/include/instance/pac.h + samc21/include/instance/pm.h + samc21/include/instance/port.h + samc21/include/instance/ptc.h + samc21/include/instance/rstc.h + samc21/include/instance/rtc.h + samc21/include/instance/sdadc.h + samc21/include/instance/sercom0.h + samc21/include/instance/sercom1.h + samc21/include/instance/sercom2.h + samc21/include/instance/sercom3.h + samc21/include/instance/sercom4.h + samc21/include/instance/sercom5.h + samc21/include/instance/supc.h + samc21/include/instance/tc0.h + samc21/include/instance/tc1.h + samc21/include/instance/tc2.h + samc21/include/instance/tc3.h + samc21/include/instance/tc4.h + samc21/include/instance/tcc0.h + samc21/include/instance/tcc1.h + samc21/include/instance/tcc2.h + samc21/include/instance/tsens.h + samc21/include/instance/wdt.h + + + + samc21/include/pio/samc21e15a.h + samc21/include/pio/samc21e16a.h + samc21/include/pio/samc21e17a.h + samc21/include/pio/samc21e18a.h + samc21/include/pio/samc21g15a.h + samc21/include/pio/samc21g16a.h + samc21/include/pio/samc21g17a.h + samc21/include/pio/samc21g18a.h + samc21/include/pio/samc21j15a.h + samc21/include/pio/samc21j16a.h + samc21/include/pio/samc21j17a.h + samc21/include/pio/samc21j17au.h + samc21/include/pio/samc21j18a.h + samc21/include/pio/samc21j18au.h + + + \ No newline at end of file diff --git a/bsp/microchip/samc21/bsp/main.c b/bsp/microchip/samc21/bsp/main.c new file mode 100644 index 0000000000..1bab456623 --- /dev/null +++ b/bsp/microchip/samc21/bsp/main.c @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief RWWEE Flash Array Read-Write Example + * + * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include "driver_init.h" + +static uint8_t src_buff[128]; +static uint8_t chk_buff[128]; + +/** + * Example of using FLASH to read and write Flash RWWEE array. + */ +void rww_flash(void) +{ + uint32_t page_size; + uint16_t i; + bool is_corrupted = false; + + /* Init source data */ + page_size = _rww_flash_get_page_size(&FLASH_0.dev); + + for (i = 0; i < page_size; i++) { + src_buff[i] = i; + } + + /* Write data to RWWEE flash */ + if (_rww_flash_write(&FLASH_0.dev, NVMCTRL_RWW_EEPROM_ADDR, src_buff, page_size) != ERR_NONE) { + printf("RWW flash write failed."); + } + + /* Read data from RWWEE flash */ + if (_rww_flash_read(&FLASH_0.dev, NVMCTRL_RWW_EEPROM_ADDR, chk_buff, page_size) != ERR_NONE) { + printf("RWW flash read failed."); + } + + /* Check data */ + for (i = 0; i < page_size; i++) { + if (src_buff[i] != chk_buff[i]) { + is_corrupted = true; + printf("RWW Flash data verification failed."); + break; + } + } + + if (!is_corrupted) { + printf("One page Write - Read is successful in RWW Flash memory"); + } +} + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* Read and write Flash RWWEE array */ + rww_flash(); + + while (1) { + } +} diff --git a/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.s b/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.s new file mode 100644 index 0000000000..d28188589c --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.s @@ -0,0 +1,252 @@ +;/**************************************************************************//** +; * @file startup_SAMC21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMC21 Device Series +; * @version V1.0.0 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD SYSTEM_Handler ; 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ; 1 Watchdog Timer + DCD RTC_Handler ; 2 Real-Time Counter + DCD EIC_Handler ; 3 External Interrupt Controller + DCD FREQM_Handler ; 4 Frequency Meter + DCD TSENS_Handler ; 5 Temperature Sensor + DCD NVMCTRL_Handler ; 6 Non-Volatile Memory Controller + DCD DMAC_Handler ; 7 Direct Memory Access Controller + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD CAN0_Handler ; 15 Control Area Network 0 + DCD CAN1_Handler ; 16 Control Area Network 1 + DCD TCC0_Handler ; 17 Timer Counter Control 0 + DCD TCC1_Handler ; 18 Timer Counter Control 1 + DCD TCC2_Handler ; 19 Timer Counter Control 2 + DCD TC0_Handler ; 20 Basic Timer Counter 0 + DCD TC1_Handler ; 21 Basic Timer Counter 1 + DCD TC2_Handler ; 22 Basic Timer Counter 2 + DCD TC3_Handler ; 23 Basic Timer Counter 3 + DCD TC4_Handler ; 24 Basic Timer Counter 4 + DCD ADC0_Handler ; 25 Analog Digital Converter 0 + DCD ADC1_Handler ; 26 Analog Digital Converter 1 + DCD AC_Handler ; 27 Analog Comparators + DCD DAC_Handler ; 28 Digital Analog Converter + DCD SDADC_Handler ; 29 Sigma-Delta Analog Digital Converter + DCD PTC_Handler ; 30 Peripheral Touch Controller +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT FREQM_Handler [WEAK] + EXPORT TSENS_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT CAN0_Handler [WEAK] + EXPORT CAN1_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC0_Handler [WEAK] + EXPORT ADC1_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT SDADC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +FREQM_Handler +TSENS_Handler +NVMCTRL_Handler +DMAC_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +CAN0_Handler +CAN1_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC0_Handler +ADC1_Handler +AC_Handler +DAC_Handler +SDADC_Handler +PTC_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/system_samc21.c b/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/system_samc21.c new file mode 100644 index 0000000000..1efa3d979a --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/armcc/Device/SAMC21/Source/system_samc21.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_flash.ld b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_flash.ld new file mode 100644 index 0000000000..42ae9c9797 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_flash.ld @@ -0,0 +1,148 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + __bss_end = _end; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_sram.ld b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_sram.ld new file mode 100644 index 0000000000..7ba753b549 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_sram.ld @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/bsp/microchip/samc21/bsp/samc21/gcc/gcc/startup_samc21.c b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/startup_samc21.c new file mode 100644 index 0000000000..2dffb6344b --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/gcc/gcc/startup_samc21.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief gcc starttup file for SAMC21 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TSENS +void TSENS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN0 +void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TCC1 +void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TCC2 +void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_ADC0 +void ADC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_ADC1 +void ADC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDADC +void SDADC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__((section(".vectors"))) const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pvReservedM12 = (void *)(0UL), /* Reserved */ + .pvReservedM11 = (void *)(0UL), /* Reserved */ + .pvReservedM10 = (void *)(0UL), /* Reserved */ + .pvReservedM9 = (void *)(0UL), /* Reserved */ + .pvReservedM8 = (void *)(0UL), /* Reserved */ + .pvReservedM7 = (void *)(0UL), /* Reserved */ + .pvReservedM6 = (void *)(0UL), /* Reserved */ + .pfnSVCall_Handler = (void *)SVCall_Handler, + .pvReservedM4 = (void *)(0UL), /* Reserved */ + .pvReservedM3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnSYSTEM_Handler = (void *)SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, + Peripheral Access Controller, Power Manager, Supply Controller, + Trigger Allocator */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 1 Watchdog Timer */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 2 Real-Time Counter */ + .pfnEIC_Handler = (void *)EIC_Handler, /* 3 External Interrupt Controller */ + .pfnFREQM_Handler = (void *)FREQM_Handler, /* 4 Frequency Meter */ +#ifdef ID_TSENS + .pfnTSENS_Handler = (void *)TSENS_Handler, /* 5 Temperature Sensor */ +#else + .pvReserved5 = (void *)(0UL), /* 5 Reserved */ +#endif + .pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void *)DMAC_Handler, /* 7 Direct Memory Access Controller */ + .pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void *)(0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void *)(0UL), /* 14 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void *)CAN0_Handler, /* 15 Control Area Network 0 */ +#else + .pvReserved15 = (void *)(0UL), /* 15 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void *)CAN1_Handler, /* 16 Control Area Network 1 */ +#else + .pvReserved16 = (void *)(0UL), /* 16 Reserved */ +#endif + .pfnTCC0_Handler = (void *)TCC0_Handler, /* 17 Timer Counter Control 0 */ +#ifdef ID_TCC1 + .pfnTCC1_Handler = (void *)TCC1_Handler, /* 18 Timer Counter Control 1 */ +#else + .pvReserved18 = (void *)(0UL), /* 18 Reserved */ +#endif +#ifdef ID_TCC2 + .pfnTCC2_Handler = (void *)TCC2_Handler, /* 19 Timer Counter Control 2 */ +#else + .pvReserved19 = (void *)(0UL), /* 19 Reserved */ +#endif + .pfnTC0_Handler = (void *)TC0_Handler, /* 20 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void *)TC1_Handler, /* 21 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void *)TC2_Handler, /* 22 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 23 Basic Timer Counter 3 */ + .pfnTC4_Handler = (void *)TC4_Handler, /* 24 Basic Timer Counter 4 */ +#ifdef ID_ADC0 + .pfnADC0_Handler = (void *)ADC0_Handler, /* 25 Analog Digital Converter 0 */ +#else + .pvReserved25 = (void *)(0UL), /* 25 Reserved */ +#endif +#ifdef ID_ADC1 + .pfnADC1_Handler = (void *)ADC1_Handler, /* 26 Analog Digital Converter 1 */ +#else + .pvReserved26 = (void *)(0UL), /* 26 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void *)AC_Handler, /* 27 Analog Comparators */ +#else + .pvReserved27 = (void *)(0UL), /* 27 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void *)DAC_Handler, /* 28 Digital Analog Converter */ +#else + .pvReserved28 = (void *)(0UL), /* 28 Reserved */ +#endif +#ifdef ID_SDADC + .pfnSDADC_Handler = (void *)SDADC_Handler, /* 29 Sigma-Delta Analog Digital Converter */ +#else + .pvReserved29 = (void *)(0UL), /* 29 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void *)PTC_Handler /* 30 Peripheral Touch Controller */ +#else + .pvReserved30 = (void *)(0UL) /* 30 Reserved */ +#endif +}; + +int rtthread_startup(void); + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to rtthread_startup function */ + rtthread_startup(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/samc21/bsp/samc21/gcc/system_samc21.c b/bsp/microchip/samc21/bsp/samc21/gcc/system_samc21.c new file mode 100644 index 0000000000..6b77150d29 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/gcc/system_samc21.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf new file mode 100644 index 0000000000..892080e9f4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_flash.icf @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf new file mode 100644 index 0000000000..e6cc6d91d6 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/samc21j18a_sram.icf @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x2000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; diff --git a/bsp/microchip/samc21/bsp/samc21/iar/iar/startup_samc21.c b/bsp/microchip/samc21/bsp/samc21/iar/iar/startup_samc21.c new file mode 100644 index 0000000000..bda7ca5dc7 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/iar/iar/startup_samc21.c @@ -0,0 +1,252 @@ +/** + * \file + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +typedef void (*intfunc)(void); +typedef union { + intfunc __fun; + void * __ptr; +} intvec_elem; + +void __iar_program_start(void); +int __low_level_init(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +#pragma weak NonMaskableInt_Handler = Dummy_Handler +#pragma weak HardFault_Handler = Dummy_Handler +#pragma weak SVCall_Handler = Dummy_Handler +#pragma weak PendSV_Handler = Dummy_Handler +#pragma weak SysTick_Handler = Dummy_Handler + +/* Peripherals handlers */ +#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +#pragma weak WDT_Handler = Dummy_Handler +#pragma weak RTC_Handler = Dummy_Handler +#pragma weak EIC_Handler = Dummy_Handler +#pragma weak FREQM_Handler = Dummy_Handler +#ifdef ID_TSENS +#pragma weak TSENS_Handler = Dummy_Handler +#endif +#pragma weak NVMCTRL_Handler = Dummy_Handler +#pragma weak DMAC_Handler = Dummy_Handler +#pragma weak EVSYS_Handler = Dummy_Handler +#pragma weak SERCOM0_Handler = Dummy_Handler +#pragma weak SERCOM1_Handler = Dummy_Handler +#pragma weak SERCOM2_Handler = Dummy_Handler +#pragma weak SERCOM3_Handler = Dummy_Handler +#ifdef ID_SERCOM4 +#pragma weak SERCOM4_Handler = Dummy_Handler +#endif +#ifdef ID_SERCOM5 +#pragma weak SERCOM5_Handler = Dummy_Handler +#endif +#ifdef ID_CAN0 +#pragma weak CAN0_Handler = Dummy_Handler +#endif +#ifdef ID_CAN1 +#pragma weak CAN1_Handler = Dummy_Handler +#endif +#pragma weak TCC0_Handler = Dummy_Handler +#ifdef ID_TCC1 +#pragma weak TCC1_Handler = Dummy_Handler +#endif +#ifdef ID_TCC2 +#pragma weak TCC2_Handler = Dummy_Handler +#endif +#pragma weak TC0_Handler = Dummy_Handler +#pragma weak TC1_Handler = Dummy_Handler +#pragma weak TC2_Handler = Dummy_Handler +#pragma weak TC3_Handler = Dummy_Handler +#pragma weak TC4_Handler = Dummy_Handler +#ifdef ID_ADC0 +#pragma weak ADC0_Handler = Dummy_Handler +#endif +#ifdef ID_ADC1 +#pragma weak ADC1_Handler = Dummy_Handler +#endif +#ifdef ID_AC +#pragma weak AC_Handler = Dummy_Handler +#endif +#ifdef ID_DAC +#pragma weak DAC_Handler = Dummy_Handler +#endif +#ifdef ID_SDADC +#pragma weak SDADC_Handler = Dummy_Handler +#endif +#ifdef ID_PTC +#pragma weak PTC_Handler = Dummy_Handler +#endif + +/* Exception Table */ +#pragma language = extended +#pragma segment = "CSTACK" + +/* The name "__vector_table" has special meaning for C-SPY: */ +/* it is where the SP start value is found, and the NVIC vector */ +/* table register (VTOR) is initialized to this address if != 0 */ + +#pragma section = ".intvec" +#pragma location = ".intvec" +const DeviceVectors __vector_table[] = { + (void *)__sfe("CSTACK"), + (void *)Reset_Handler, + (void *)NonMaskableInt_Handler, + (void *)HardFault_Handler, + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)SVCall_Handler, + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)PendSV_Handler, + (void *)SysTick_Handler, + + /* Configurable interrupts */ + (void *)SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access + Controller, Power Manager, Supply Controller, Trigger Allocator */ + (void *)WDT_Handler, /* 1 Watchdog Timer */ + (void *)RTC_Handler, /* 2 Real-Time Counter */ + (void *)EIC_Handler, /* 3 External Interrupt Controller */ + (void *)FREQM_Handler, /* 4 Frequency Meter */ +#ifdef ID_TSENS + (void *)TSENS_Handler, /* 5 Temperature Sensor */ +#else + (void *)(0UL), /* 5 Reserved */ +#endif + (void *)NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */ + (void *)DMAC_Handler, /* 7 Direct Memory Access Controller */ + (void *)EVSYS_Handler, /* 8 Event System Interface */ + (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + (void *)(0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + (void *)(0UL), /* 14 Reserved */ +#endif +#ifdef ID_CAN0 + (void *)CAN0_Handler, /* 15 Control Area Network 0 */ +#else + (void *)(0UL), /* 15 Reserved */ +#endif +#ifdef ID_CAN1 + (void *)CAN1_Handler, /* 16 Control Area Network 1 */ +#else + (void *)(0UL), /* 16 Reserved */ +#endif + (void *)TCC0_Handler, /* 17 Timer Counter Control 0 */ +#ifdef ID_TCC1 + (void *)TCC1_Handler, /* 18 Timer Counter Control 1 */ +#else + (void *)(0UL), /* 18 Reserved */ +#endif +#ifdef ID_TCC2 + (void *)TCC2_Handler, /* 19 Timer Counter Control 2 */ +#else + (void *)(0UL), /* 19 Reserved */ +#endif + (void *)TC0_Handler, /* 20 Basic Timer Counter 0 */ + (void *)TC1_Handler, /* 21 Basic Timer Counter 1 */ + (void *)TC2_Handler, /* 22 Basic Timer Counter 2 */ + (void *)TC3_Handler, /* 23 Basic Timer Counter 3 */ + (void *)TC4_Handler, /* 24 Basic Timer Counter 4 */ +#ifdef ID_ADC0 + (void *)ADC0_Handler, /* 25 Analog Digital Converter 0 */ +#else + (void *)(0UL), /* 25 Reserved */ +#endif +#ifdef ID_ADC1 + (void *)ADC1_Handler, /* 26 Analog Digital Converter 1 */ +#else + (void *)(0UL), /* 26 Reserved */ +#endif +#ifdef ID_AC + (void *)AC_Handler, /* 27 Analog Comparators */ +#else + (void *)(0UL), /* 27 Reserved */ +#endif +#ifdef ID_DAC + (void *)DAC_Handler, /* 28 Digital Analog Converter */ +#else + (void *)(0UL), /* 28 Reserved */ +#endif +#ifdef ID_SDADC + (void *)SDADC_Handler, /* 29 Sigma-Delta Analog Digital Converter */ +#else + (void *)(0UL), /* 29 Reserved */ +#endif +#ifdef ID_PTC + (void *)PTC_Handler /* 30 Peripheral Touch Controller */ +#else + (void *)(0UL) /* 30 Reserved */ +#endif +}; + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +int __low_level_init(void) +{ + uint32_t *pSrc = __section_begin(".intvec"); + + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + return 1; /* if return 0, the data sections will not be initialized */ +} + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __iar_program_start(); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/samc21/bsp/samc21/iar/system_samc21.c b/bsp/microchip/samc21/bsp/samc21/iar/system_samc21.c new file mode 100644 index 0000000000..6b77150d29 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/iar/system_samc21.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samc21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/samc21/bsp/samc21/include/component-version.h b/bsp/microchip/samc21/bsp/samc21/include/component-version.h new file mode 100644 index 0000000000..17d41e744c --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 176 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-12-18 12:46:52" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/ac.h b/bsp/microchip/samc21/bsp/samc21/include/component/ac.h new file mode 100644 index 0000000000..451c6e87a4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/ac.h @@ -0,0 +1,652 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_AC_COMPONENT_ +#define _SAMC21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMC21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x111 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t START2:1; /*!< bit: 2 Comparator 2 Start Comparison */ + uint8_t START3:1; /*!< bit: 3 Comparator 3 Start Comparison */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:4; /*!< bit: 0.. 3 Comparator x Start Comparison */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START2_Pos 2 /**< \brief (AC_CTRLB) Comparator 2 Start Comparison */ +#define AC_CTRLB_START2 (_U_(1) << AC_CTRLB_START2_Pos) +#define AC_CTRLB_START3_Pos 3 /**< \brief (AC_CTRLB) Comparator 3 Start Comparison */ +#define AC_CTRLB_START3 (_U_(1) << AC_CTRLB_START3_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0xF) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x0F) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t COMPEO2:1; /*!< bit: 2 Comparator 2 Event Output Enable */ + uint16_t COMPEO3:1; /*!< bit: 3 Comparator 3 Event Output Enable */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t WINEO1:1; /*!< bit: 5 Window 1 Event Output Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t COMPEI2:1; /*!< bit: 10 Comparator 2 Event Input Enable */ + uint16_t COMPEI3:1; /*!< bit: 11 Comparator 3 Event Input Enable */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t INVEI2:1; /*!< bit: 14 Comparator 2 Input Event Invert Enable */ + uint16_t INVEI3:1; /*!< bit: 15 Comparator 3 Input Event Invert Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:4; /*!< bit: 0.. 3 Comparator x Event Output Enable */ + uint16_t WINEO:2; /*!< bit: 4.. 5 Window x Event Output Enable */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t COMPEI:4; /*!< bit: 8..11 Comparator x Event Input Enable */ + uint16_t INVEI:4; /*!< bit: 12..15 Comparator x Input Event Invert Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO2_Pos 2 /**< \brief (AC_EVCTRL) Comparator 2 Event Output Enable */ +#define AC_EVCTRL_COMPEO2 (_U_(1) << AC_EVCTRL_COMPEO2_Pos) +#define AC_EVCTRL_COMPEO3_Pos 3 /**< \brief (AC_EVCTRL) Comparator 3 Event Output Enable */ +#define AC_EVCTRL_COMPEO3 (_U_(1) << AC_EVCTRL_COMPEO3_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0xF) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO1_Pos 5 /**< \brief (AC_EVCTRL) Window 1 Event Output Enable */ +#define AC_EVCTRL_WINEO1 (_U_(1) << AC_EVCTRL_WINEO1_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x3) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI2_Pos 10 /**< \brief (AC_EVCTRL) Comparator 2 Event Input Enable */ +#define AC_EVCTRL_COMPEI2 (_U_(1) << AC_EVCTRL_COMPEI2_Pos) +#define AC_EVCTRL_COMPEI3_Pos 11 /**< \brief (AC_EVCTRL) Comparator 3 Event Input Enable */ +#define AC_EVCTRL_COMPEI3 (_U_(1) << AC_EVCTRL_COMPEI3_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0xF) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI2_Pos 14 /**< \brief (AC_EVCTRL) Comparator 2 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI2 (_U_(1) << AC_EVCTRL_INVEI2_Pos) +#define AC_EVCTRL_INVEI3_Pos 15 /**< \brief (AC_EVCTRL) Comparator 3 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI3 (_U_(1) << AC_EVCTRL_INVEI3_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0xF) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0xFF3F) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Enable */ + uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Enable */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x Interrupt Enable */ + uint8_t WIN:2; /*!< bit: 4.. 5 Window x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP2_Pos 2 /**< \brief (AC_INTENCLR) Comparator 2 Interrupt Enable */ +#define AC_INTENCLR_COMP2 (_U_(1) << AC_INTENCLR_COMP2_Pos) +#define AC_INTENCLR_COMP3_Pos 3 /**< \brief (AC_INTENCLR) Comparator 3 Interrupt Enable */ +#define AC_INTENCLR_COMP3 (_U_(1) << AC_INTENCLR_COMP3_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0xF) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN1_Pos 5 /**< \brief (AC_INTENCLR) Window 1 Interrupt Enable */ +#define AC_INTENCLR_WIN1 (_U_(1) << AC_INTENCLR_WIN1_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x3) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x3F) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Enable */ + uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Enable */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x Interrupt Enable */ + uint8_t WIN:2; /*!< bit: 4.. 5 Window x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP2_Pos 2 /**< \brief (AC_INTENSET) Comparator 2 Interrupt Enable */ +#define AC_INTENSET_COMP2 (_U_(1) << AC_INTENSET_COMP2_Pos) +#define AC_INTENSET_COMP3_Pos 3 /**< \brief (AC_INTENSET) Comparator 3 Interrupt Enable */ +#define AC_INTENSET_COMP3 (_U_(1) << AC_INTENSET_COMP3_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0xF) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN1_Pos 5 /**< \brief (AC_INTENSET) Window 1 Interrupt Enable */ +#define AC_INTENSET_WIN1 (_U_(1) << AC_INTENSET_WIN1_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x3) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x3F) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t COMP2:1; /*!< bit: 2 Comparator 2 */ + __I uint8_t COMP3:1; /*!< bit: 3 Comparator 3 */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t WIN1:1; /*!< bit: 5 Window 1 */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x */ + __I uint8_t WIN:2; /*!< bit: 4.. 5 Window x */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP2_Pos 2 /**< \brief (AC_INTFLAG) Comparator 2 */ +#define AC_INTFLAG_COMP2 (_U_(1) << AC_INTFLAG_COMP2_Pos) +#define AC_INTFLAG_COMP3_Pos 3 /**< \brief (AC_INTFLAG) Comparator 3 */ +#define AC_INTFLAG_COMP3 (_U_(1) << AC_INTFLAG_COMP3_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0xF) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN1_Pos 5 /**< \brief (AC_INTFLAG) Window 1 */ +#define AC_INTFLAG_WIN1 (_U_(1) << AC_INTFLAG_WIN1_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x3) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x3F) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t STATE2:1; /*!< bit: 2 Comparator 2 Current State */ + uint8_t STATE3:1; /*!< bit: 3 Comparator 3 Current State */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t WSTATE1:2; /*!< bit: 6.. 7 Window 1 Current State */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:4; /*!< bit: 0.. 3 Comparator x Current State */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE2_Pos 2 /**< \brief (AC_STATUSA) Comparator 2 Current State */ +#define AC_STATUSA_STATE2 (_U_(1) << AC_STATUSA_STATE2_Pos) +#define AC_STATUSA_STATE3_Pos 3 /**< \brief (AC_STATUSA) Comparator 3 Current State */ +#define AC_STATUSA_STATE3 (_U_(1) << AC_STATUSA_STATE3_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0xF) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE1_Pos 6 /**< \brief (AC_STATUSA) Window 1 Current State */ +#define AC_STATUSA_WSTATE1_Msk (_U_(0x3) << AC_STATUSA_WSTATE1_Pos) +#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & ((value) << AC_STATUSA_WSTATE1_Pos)) +#define AC_STATUSA_WSTATE1_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE1_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE1_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos) +#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos) +#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos) +#define AC_STATUSA_MASK _U_(0xFF) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t READY2:1; /*!< bit: 2 Comparator 2 Ready */ + uint8_t READY3:1; /*!< bit: 3 Comparator 3 Ready */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:4; /*!< bit: 0.. 3 Comparator x Ready */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY2_Pos 2 /**< \brief (AC_STATUSB) Comparator 2 Ready */ +#define AC_STATUSB_READY2 (_U_(1) << AC_STATUSB_READY2_Pos) +#define AC_STATUSB_READY3_Pos 3 /**< \brief (AC_STATUSB) Comparator 3 Ready */ +#define AC_STATUSB_READY3 (_U_(1) << AC_STATUSB_READY3_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0xF) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x0F) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t WEN1:1; /*!< bit: 4 Window 1 Mode Enable */ + uint8_t WINTSEL1:2; /*!< bit: 5.. 6 Window 1 Interrupt Selection */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WEN1_Pos 4 /**< \brief (AC_WINCTRL) Window 1 Mode Enable */ +#define AC_WINCTRL_WEN1 (_U_(0x1) << AC_WINCTRL_WEN1_Pos) +#define AC_WINCTRL_WINTSEL1_Pos 5 /**< \brief (AC_WINCTRL) Window 1 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL1_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL1_Pos) +#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & ((value) << AC_WINCTRL_WINTSEL1_Pos)) +#define AC_WINCTRL_WINTSEL1_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL1_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL1_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos) +#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) +#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos) +#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos) +#define AC_WINCTRL_MASK _U_(0x77) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x370BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t COMPCTRL2:1; /*!< bit: 5 COMPCTRL 2 Synchronization Busy */ + uint32_t COMPCTRL3:1; /*!< bit: 6 COMPCTRL 3 Synchronization Busy */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:4; /*!< bit: 3.. 6 COMPCTRL x Synchronization Busy */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL2_Pos 5 /**< \brief (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL2 (_U_(1) << AC_SYNCBUSY_COMPCTRL2_Pos) +#define AC_SYNCBUSY_COMPCTRL3_Pos 6 /**< \brief (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL3 (_U_(1) << AC_SYNCBUSY_COMPCTRL3_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000007F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[4]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + __IO AC_COMPCTRL_Type COMPCTRL[4]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMC21_AC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/adc.h b/bsp/microchip/samc21/bsp/samc21/include/component/adc.h new file mode 100644 index 0000000000..2b2d525d06 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/adc.h @@ -0,0 +1,725 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_ADC_COMPONENT_ +#define _SAMC21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMC21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x220 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :3; /*!< bit: 2.. 4 Reserved */ + uint8_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run During Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run During Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK _U_(0xE3) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_DAC_Val _U_(0x4) /**< \brief (ADC_REFCTRL) DAC */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :1; /*!< bit: 6 Reserved */ + uint16_t R2R:1; /*!< bit: 7 Rail-to-Rail mode enable */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 12..13 Dual Mode Trigger Selection */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) +#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_R2R_Pos 7 /**< \brief (ADC_CTRLC) Rail-to-Rail mode enable */ +#define ADC_CTRLC_R2R (_U_(0x1) << ADC_CTRLC_R2R_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) +#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_DUALSEL_Pos 12 /**< \brief (ADC_CTRLC) Dual Mode Trigger Selection */ +#define ADC_CTRLC_DUALSEL_Msk (_U_(0x3) << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & ((value) << ADC_CTRLC_DUALSEL_Pos)) +#define ADC_CTRLC_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLC) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos) +#define ADC_CTRLC_MASK _U_(0x37BF) /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) +#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMC21_ADC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/can.h b/bsp/microchip/samc21/bsp/samc21/include/component/can.h new file mode 100644 index 0000000000..6e9c69f3be --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/can.h @@ -0,0 +1,3187 @@ +/** + * \file + * + * \brief Component description for CAN + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_CAN_COMPONENT_ +#define _SAMC21_CAN_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CAN */ +/* ========================================================================== */ +/** \addtogroup SAMC21_CAN Control Area Network */ +/*@{*/ + +#define CAN_U2003 +#define REV_CAN 0x200 + +/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :20; /*!< bit: 0..19 Reserved */ + uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /*!< bit: 28..31 Core Release */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CREL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ +#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */ + +#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ +#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ +#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ +#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */ + +/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ENDN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ +#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */ + +#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ +#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */ + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_MRCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ +#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ + +#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ +#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */ + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ + uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ + uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ + uint32_t :2; /*!< bit: 21..22 Reserved */ + uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_DBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ +#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ + +#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ +#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ +#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ +#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ +#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ +#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) +#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */ + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ + uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ + uint32_t RX:1; /*!< bit: 7 Receive Pin */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TEST_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ +#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */ + +#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ +#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) +#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ +#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ +#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) +#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */ + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ + uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RWD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ +#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */ + +#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ +#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ +#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */ + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INIT:1; /*!< bit: 0 Initialization */ + uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ + uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ + uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ + uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ + uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ + uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ + uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ + uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ + uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ + uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ + uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ + uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CCCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ +#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */ + +#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ +#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) +#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ +#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) +#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ +#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) +#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ +#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) +#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ +#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) +#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ +#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) +#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ +#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) +#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ +#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) +#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ +#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) +#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ +#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) +#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ +#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) +#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ +#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) +#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ +#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) +#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ +#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) +#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */ + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ + uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ + uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ +#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ + +#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ +#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ +#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ +#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ +#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */ + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ + uint32_t :14; /*!< bit: 2..15 Reserved */ + uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ +#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ + +#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ +#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ +#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */ + +/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ +#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ + +#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ +#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */ + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ +#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ + +#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ +#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) +#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ +#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ +#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */ + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ +#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ + +#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ +#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */ + +/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ + uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ECR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ +#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */ + +#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ +#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ +#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) +#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ +#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */ + +/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ + uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ + uint32_t EP:1; /*!< bit: 5 Error Passive */ + uint32_t EW:1; /*!< bit: 6 Warning Status */ + uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ + uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ + uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ + uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ + uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ +#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */ + +#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ +#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ +#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ +#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) +#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ +#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) +#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ +#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) +#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ +#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ +#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) +#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ +#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) +#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ +#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) +#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ +#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) +#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ +#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */ + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TDCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ +#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ + +#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ +#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ +#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */ + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ + uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ + uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ + uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ + uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ + uint32_t HPM:1; /*!< bit: 8 High Priority Message */ + uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ + uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ + uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ + uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ + uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /*!< bit: 23 Error Passive */ + uint32_t EW:1; /*!< bit: 24 Warning Status */ + uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ +#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */ + +#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ +#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) +#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ +#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) +#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ +#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) +#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ +#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) +#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ +#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) +#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ +#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) +#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ +#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) +#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ +#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) +#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ +#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) +#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ +#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) +#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ +#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) +#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ +#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) +#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ +#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) +#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ +#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) +#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ +#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) +#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ +#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) +#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ +#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) +#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ +#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) +#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ +#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) +#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ +#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) +#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ +#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) +#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ +#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) +#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ +#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) +#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ +#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) +#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ +#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) +#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ +#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) +#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ +#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) +#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ +#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) +#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ +#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) +#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ +#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) +#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */ + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ + uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ + uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ + uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ + uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ + uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ + uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ + uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ +#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */ + +#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ +#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) +#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) +#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ +#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) +#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ +#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) +#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ +#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) +#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) +#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ +#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) +#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ +#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) +#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ +#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) +#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ +#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) +#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) +#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ +#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) +#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) +#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) +#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) +#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ +#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) +#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ +#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) +#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ +#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) +#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ +#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) +#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ +#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) +#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ +#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) +#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) +#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ +#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) +#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ +#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) +#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ +#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) +#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ +#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) +#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ +#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) +#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ +#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) +#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ +#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) +#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ +#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) +#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */ + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ + uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ + uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ + uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ + uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ + uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ + uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ + uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ +#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ + +#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ +#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) +#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) +#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ +#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) +#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ +#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) +#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ +#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) +#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) +#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ +#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) +#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ +#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) +#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ +#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) +#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ +#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) +#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) +#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ +#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) +#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) +#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) +#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) +#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ +#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) +#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ +#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) +#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ +#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) +#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ +#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) +#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ +#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) +#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ +#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) +#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) +#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ +#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) +#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ +#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) +#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ +#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) +#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ +#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) +#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ +#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) +#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ +#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) +#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ +#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) +#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ +#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) +#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */ + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ +#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ + +#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ +#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) +#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ +#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) +#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */ + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_GFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ +#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ + +#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ +#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) +#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ +#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) +#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ +#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ +#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */ + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ + uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ +#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ + +#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ +#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ +#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */ + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ + uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ +#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ + +#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ +#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ +#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */ + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ +#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ + +#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ +#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */ + +/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ + uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ + uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ + uint32_t FLST:1; /*!< bit: 15 Filter List */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_HPMS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ +#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ + +#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ +#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ +#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ +#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ +#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) +#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */ + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND0:1; /*!< bit: 0 New Data 0 */ + uint32_t ND1:1; /*!< bit: 1 New Data 1 */ + uint32_t ND2:1; /*!< bit: 2 New Data 2 */ + uint32_t ND3:1; /*!< bit: 3 New Data 3 */ + uint32_t ND4:1; /*!< bit: 4 New Data 4 */ + uint32_t ND5:1; /*!< bit: 5 New Data 5 */ + uint32_t ND6:1; /*!< bit: 6 New Data 6 */ + uint32_t ND7:1; /*!< bit: 7 New Data 7 */ + uint32_t ND8:1; /*!< bit: 8 New Data 8 */ + uint32_t ND9:1; /*!< bit: 9 New Data 9 */ + uint32_t ND10:1; /*!< bit: 10 New Data 10 */ + uint32_t ND11:1; /*!< bit: 11 New Data 11 */ + uint32_t ND12:1; /*!< bit: 12 New Data 12 */ + uint32_t ND13:1; /*!< bit: 13 New Data 13 */ + uint32_t ND14:1; /*!< bit: 14 New Data 14 */ + uint32_t ND15:1; /*!< bit: 15 New Data 15 */ + uint32_t ND16:1; /*!< bit: 16 New Data 16 */ + uint32_t ND17:1; /*!< bit: 17 New Data 17 */ + uint32_t ND18:1; /*!< bit: 18 New Data 18 */ + uint32_t ND19:1; /*!< bit: 19 New Data 19 */ + uint32_t ND20:1; /*!< bit: 20 New Data 20 */ + uint32_t ND21:1; /*!< bit: 21 New Data 21 */ + uint32_t ND22:1; /*!< bit: 22 New Data 22 */ + uint32_t ND23:1; /*!< bit: 23 New Data 23 */ + uint32_t ND24:1; /*!< bit: 24 New Data 24 */ + uint32_t ND25:1; /*!< bit: 25 New Data 25 */ + uint32_t ND26:1; /*!< bit: 26 New Data 26 */ + uint32_t ND27:1; /*!< bit: 27 New Data 27 */ + uint32_t ND28:1; /*!< bit: 28 New Data 28 */ + uint32_t ND29:1; /*!< bit: 29 New Data 29 */ + uint32_t ND30:1; /*!< bit: 30 New Data 30 */ + uint32_t ND31:1; /*!< bit: 31 New Data 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ +#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ + +#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ +#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) +#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ +#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) +#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ +#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) +#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ +#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) +#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ +#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) +#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ +#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) +#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ +#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) +#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ +#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) +#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ +#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) +#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ +#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) +#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ +#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) +#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ +#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) +#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ +#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) +#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ +#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) +#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ +#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) +#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ +#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) +#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ +#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) +#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ +#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) +#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ +#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) +#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ +#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) +#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ +#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) +#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ +#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) +#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ +#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) +#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ +#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) +#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ +#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) +#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ +#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) +#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ +#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) +#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ +#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) +#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ +#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) +#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ +#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) +#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ +#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) +#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ +#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) +#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */ + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND32:1; /*!< bit: 0 New Data 32 */ + uint32_t ND33:1; /*!< bit: 1 New Data 33 */ + uint32_t ND34:1; /*!< bit: 2 New Data 34 */ + uint32_t ND35:1; /*!< bit: 3 New Data 35 */ + uint32_t ND36:1; /*!< bit: 4 New Data 36 */ + uint32_t ND37:1; /*!< bit: 5 New Data 37 */ + uint32_t ND38:1; /*!< bit: 6 New Data 38 */ + uint32_t ND39:1; /*!< bit: 7 New Data 39 */ + uint32_t ND40:1; /*!< bit: 8 New Data 40 */ + uint32_t ND41:1; /*!< bit: 9 New Data 41 */ + uint32_t ND42:1; /*!< bit: 10 New Data 42 */ + uint32_t ND43:1; /*!< bit: 11 New Data 43 */ + uint32_t ND44:1; /*!< bit: 12 New Data 44 */ + uint32_t ND45:1; /*!< bit: 13 New Data 45 */ + uint32_t ND46:1; /*!< bit: 14 New Data 46 */ + uint32_t ND47:1; /*!< bit: 15 New Data 47 */ + uint32_t ND48:1; /*!< bit: 16 New Data 48 */ + uint32_t ND49:1; /*!< bit: 17 New Data 49 */ + uint32_t ND50:1; /*!< bit: 18 New Data 50 */ + uint32_t ND51:1; /*!< bit: 19 New Data 51 */ + uint32_t ND52:1; /*!< bit: 20 New Data 52 */ + uint32_t ND53:1; /*!< bit: 21 New Data 53 */ + uint32_t ND54:1; /*!< bit: 22 New Data 54 */ + uint32_t ND55:1; /*!< bit: 23 New Data 55 */ + uint32_t ND56:1; /*!< bit: 24 New Data 56 */ + uint32_t ND57:1; /*!< bit: 25 New Data 57 */ + uint32_t ND58:1; /*!< bit: 26 New Data 58 */ + uint32_t ND59:1; /*!< bit: 27 New Data 59 */ + uint32_t ND60:1; /*!< bit: 28 New Data 60 */ + uint32_t ND61:1; /*!< bit: 29 New Data 61 */ + uint32_t ND62:1; /*!< bit: 30 New Data 62 */ + uint32_t ND63:1; /*!< bit: 31 New Data 63 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ +#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ + +#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ +#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) +#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ +#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) +#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ +#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) +#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ +#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) +#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ +#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) +#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ +#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) +#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ +#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) +#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ +#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) +#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ +#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) +#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ +#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) +#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ +#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) +#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ +#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) +#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ +#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) +#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ +#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) +#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ +#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) +#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ +#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) +#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ +#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) +#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ +#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) +#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ +#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) +#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ +#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) +#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ +#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) +#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ +#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) +#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ +#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) +#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ +#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) +#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ +#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) +#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ +#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) +#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ +#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) +#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ +#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) +#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ +#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) +#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ +#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) +#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ +#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) +#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ +#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) +#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */ + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ + uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ + uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ +#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ + +#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ +#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ +#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ +#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ +#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) +#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */ + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ +#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ + +#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ +#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ +#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ +#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ +#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) +#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ +#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) +#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */ + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ + +#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ +#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */ + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ +#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ + +#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ +#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */ + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ + uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ + uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ +#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ + +#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ +#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ +#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ +#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ +#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) +#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */ + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ + uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ + uint32_t :4; /*!< bit: 26..29 Reserved */ + uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ +#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ + +#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ +#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ +#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ +#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ +#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) +#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ +#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) +#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ +#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */ + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ + +#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ +#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */ + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ +#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ + +#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ +#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ +#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ +#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */ + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ +#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ + +#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ +#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ +#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ +#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ +#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) +#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */ + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXFQS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ +#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ + +#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ +#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ +#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ +#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ +#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) +#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */ + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ +#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ + +#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ +#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */ + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ + uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ + uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ + uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ + uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ + uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ + uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ + uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ + uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ + uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ + uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ + uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ + uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ + uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ + uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ + uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ + uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ + uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ + uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ + uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ + uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ + uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ + uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ + uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ + uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ + uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ + uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ + uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ + uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ + uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ + uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ + uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBRP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ +#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ + +#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ +#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) +#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ +#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) +#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ +#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) +#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ +#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) +#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ +#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) +#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ +#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) +#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ +#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) +#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ +#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) +#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ +#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) +#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ +#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) +#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ +#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) +#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ +#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) +#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ +#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) +#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ +#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) +#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ +#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) +#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ +#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) +#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ +#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) +#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ +#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) +#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ +#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) +#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ +#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) +#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ +#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) +#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ +#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) +#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ +#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) +#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ +#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) +#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ +#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) +#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ +#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) +#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ +#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) +#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ +#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) +#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ +#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) +#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ +#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) +#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ +#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) +#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ +#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) +#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */ + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ + uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ + uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ + uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ + uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ + uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ + uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ + uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ + uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ + uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ + uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ + uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ + uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ + uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ + uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ + uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ + uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ + uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ + uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ + uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ + uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ + uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ + uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ + uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ + uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ + uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ + uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ + uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ + uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ + uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ + uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ + uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ +#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ + +#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ +#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) +#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ +#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) +#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ +#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) +#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ +#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) +#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ +#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) +#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ +#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) +#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ +#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) +#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ +#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) +#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ +#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) +#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ +#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) +#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ +#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) +#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ +#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) +#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ +#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) +#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ +#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) +#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ +#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) +#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ +#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) +#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ +#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) +#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ +#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) +#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ +#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) +#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ +#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) +#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ +#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) +#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ +#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) +#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ +#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) +#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ +#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) +#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ +#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) +#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ +#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) +#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ +#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) +#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ +#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) +#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ +#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) +#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ +#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) +#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ +#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) +#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ +#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) +#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */ + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ + uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ + uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ + uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ + uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ + uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ + uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ + uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ + uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ + uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ + uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ + uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ + uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ + uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ + uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ + uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ + uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ + uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ + uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ + uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ + uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ + uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ + uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ + uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ + uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ + uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ + uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ + uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ + uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ + uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ + uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ + uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ +#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ + +#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ +#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) +#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ +#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) +#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ +#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) +#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ +#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) +#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ +#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) +#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ +#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) +#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ +#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) +#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ +#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) +#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ +#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) +#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ +#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) +#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ +#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) +#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ +#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) +#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ +#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) +#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ +#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) +#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ +#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) +#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ +#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) +#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ +#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) +#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ +#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) +#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ +#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) +#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ +#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) +#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ +#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) +#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ +#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) +#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ +#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) +#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ +#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) +#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ +#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) +#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ +#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) +#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ +#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) +#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ +#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) +#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ +#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) +#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ +#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) +#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ +#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) +#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ +#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) +#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */ + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ + uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ + uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ + uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ + uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ + uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ + uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ + uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ + uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ + uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ + uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ + uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ + uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ + uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ + uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ + uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ + uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ + uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ + uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ + uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ + uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ + uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ + uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ + uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ + uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ + uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ + uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ + uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ + uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ + uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ + uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ + uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ + +#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ +#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) +#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ +#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) +#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ +#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) +#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ +#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) +#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ +#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) +#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ +#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) +#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ +#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) +#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ +#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) +#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ +#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) +#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ +#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) +#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ +#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) +#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ +#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) +#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ +#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) +#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ +#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) +#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ +#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) +#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ +#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) +#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ +#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) +#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ +#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) +#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ +#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) +#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ +#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) +#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ +#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) +#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ +#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) +#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ +#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) +#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ +#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) +#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ +#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) +#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ +#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) +#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ +#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) +#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ +#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) +#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ +#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) +#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ +#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) +#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ +#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) +#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ +#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) +#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */ + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ + uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ + uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ + uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ + uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ + uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ + uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ + uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ + uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ + uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ + uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ + uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ + uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ + uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ + uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ + uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ + uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ + uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ + uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ + uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ + uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ + uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ + uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ + uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ + uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ + uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ + uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ + uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ + uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ + uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ + uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ + uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ + +#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ +#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) +#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ +#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) +#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ +#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) +#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ +#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) +#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ +#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) +#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ +#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) +#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ +#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) +#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ +#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) +#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ +#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) +#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ +#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) +#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ +#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) +#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ +#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) +#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ +#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) +#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ +#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) +#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ +#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) +#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ +#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) +#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ +#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) +#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ +#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) +#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ +#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) +#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ +#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) +#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ +#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) +#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ +#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) +#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ +#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) +#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ +#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) +#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ +#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) +#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ +#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) +#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ +#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) +#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ +#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) +#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ +#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) +#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ +#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) +#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ +#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) +#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ +#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) +#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */ + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ + uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ + uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ + uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ + uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ + uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ + uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ + uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ + uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ + uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ + uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ + uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ + uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ + uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ + uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ + uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ + uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ + uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ + uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ + uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ + uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ + uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ + uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ + uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ + uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ + uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ + uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ + uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ + uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ + uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ + uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ + uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ + +#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ +#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) +#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ +#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) +#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ +#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) +#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ +#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) +#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ +#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) +#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ +#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) +#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ +#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) +#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ +#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) +#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ +#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) +#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ +#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) +#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ +#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) +#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ +#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) +#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ +#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) +#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ +#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) +#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ +#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) +#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ +#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) +#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ +#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) +#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ +#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) +#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ +#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) +#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ +#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) +#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ +#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) +#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ +#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) +#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ +#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) +#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ +#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) +#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ +#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) +#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ +#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) +#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ +#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) +#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ +#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) +#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ +#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) +#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ +#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) +#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ +#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) +#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ +#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) +#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */ + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ + uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ + uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ + uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ + uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ + uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ + uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ + uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ + uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ + uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ + uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ + uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ + uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ + uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ + uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ + uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ + uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ + uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ + uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ + uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ + uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ + uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ + uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ + uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ + uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ + uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ + uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ + uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ + uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ + uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ + uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ + uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ + +#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ +#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) +#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ +#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) +#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ +#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) +#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ +#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) +#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ +#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) +#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ +#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) +#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ +#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) +#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ +#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) +#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ +#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) +#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ +#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) +#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ +#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) +#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ +#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) +#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ +#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) +#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ +#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) +#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ +#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) +#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ +#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) +#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ +#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) +#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ +#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) +#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ +#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) +#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ +#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) +#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ +#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) +#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ +#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) +#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ +#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) +#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ +#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) +#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ +#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) +#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ +#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) +#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ +#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) +#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ +#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) +#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ +#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) +#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ +#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) +#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ +#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) +#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ +#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) +#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */ + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ + uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ +#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ + +#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ +#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ +#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ +#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */ + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /*!< bit: 21..23 Reserved */ + uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ +#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ + +#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ +#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ +#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ +#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ +#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) +#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ +#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) +#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */ + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ + +#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ +#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ +#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ + +#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ +#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ +#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) +#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ +#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) +#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ +#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) +#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */ + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ +#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ + +#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ +#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ +#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ +#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) +#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ +#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) +#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ +#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ +#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) +#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */ + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ +#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ + +#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ +#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ +#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ +#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ +#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */ + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ +#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ + +#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ +#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ +#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) +#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ +#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) +#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ +#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) +#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */ + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ +#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ + +#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ +#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ +#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ +#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) +#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ +#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) +#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ +#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ +#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) +#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */ + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ +#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ + +#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ +#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ +#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ +#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ +#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */ + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ +#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ + +#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ +#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ +#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) +#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ +#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) +#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ +#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) +#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */ + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ +#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ + +#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ +#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ +#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ +#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) +#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ +#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) +#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ +#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ +#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) +#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */ + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ +#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ + +#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ +#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ +#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ +#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ +#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */ + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /*!< bit: 11..15 Reserved */ + uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ +#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ + +#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ +#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ +#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ +#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ +#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */ + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ +#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ + +#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ +#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ +#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) +#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ +#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) +#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ +#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) +#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */ + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t DLC:4; /*!< bit: 16..19 Identifier */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ +#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ + +#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ +#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ +#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) +#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ +#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) +#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ +#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) +#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ +#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */ + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ +#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ + +#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ +#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ +#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ +#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ +#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */ + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ +#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ + +#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ +#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ +#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) +#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ +#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) +#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ +#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) +#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */ + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t ET:2; /*!< bit: 22..23 Event Type */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ +#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ + +#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ +#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ +#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ +#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) +#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ +#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) +#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ +#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ +#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */ + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ +#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ + +#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ +#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ +#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */ + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ +#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ + +#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ +#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ +#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */ + +/** \brief CAN APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ + __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ + __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ + __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ + __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ + RoReg8 Reserved1[0x10]; + __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ + __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ + __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved2[0x4]; + __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ + __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ + RoReg8 Reserved3[0x20]; + __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved4[0x4]; + __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ + __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ + __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + RoReg8 Reserved5[0x8]; + __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} CanMramRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf0e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} CanMramRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf1e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} CanMramRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_sidfe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ +} CanMramSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} CanMramTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txefe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} CanMramTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_xifde hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} CanMramXifde +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_CAN_MRAM_RXBE +#define SECTION_CAN_MRAM_RXF0E +#define SECTION_CAN_MRAM_RXF1E +#define SECTION_CAN_MRAM_SIDFE +#define SECTION_CAN_MRAM_TXBE +#define SECTION_CAN_MRAM_TXEFE +#define SECTION_CAN_MRAM_XIFDE + +/*@}*/ + +#endif /* _SAMC21_CAN_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/ccl.h b/bsp/microchip/samc21/bsp/samc21/include/component/ccl.h new file mode 100644 index 0000000000..959ee927d2 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/ccl.h @@ -0,0 +1,188 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_CCL_COMPONENT_ +#define _SAMC21_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAMC21_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x101 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMC21_CCL_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/dac.h b/bsp/microchip/samc21/bsp/samc21/include/component/dac.h new file mode 100644 index 0000000000..7ff810af9b --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/dac.h @@ -0,0 +1,315 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_DAC_COMPONENT_ +#define _SAMC21_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMC21_DAC Digital Analog Converter */ +/*@{*/ + +#define DAC_U2214 +#define REV_DAC 0x201 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (DAC_CTRLA) Run in Standby */ +#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) +#define DAC_CTRLA_MASK _U_(0x43) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t DITHER:1; /*!< bit: 5 Dither Enable */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ +#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos) +#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ +#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos) +#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ +#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos) +#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ +#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos) +#define DAC_CTRLB_DITHER_Pos 5 /**< \brief (DAC_CTRLB) Dither Enable */ +#define DAC_CTRLB_DITHER (_U_(0x1) << DAC_CTRLB_DITHER_Pos) +#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0xEF) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t INVEI:1; /*!< bit: 2 Invert Event Input */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ +#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ +#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_INVEI_Pos 2 /**< \brief (DAC_EVCTRL) Invert Event Input */ +#define DAC_EVCTRL_INVEI (_U_(0x1) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_MASK _U_(0x07) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_MASK _U_(0x03) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_MASK _U_(0x03) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ +#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ +#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_MASK _U_(0x03) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY:1; /*!< bit: 0 Ready */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) Ready */ +#define DAC_STATUS_READY (_U_(0x1) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_MASK _U_(0x01) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x08 /**< \brief (DAC_DATA offset) Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x0C /**< \brief (DAC_DATABUF offset) Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t DATA:1; /*!< bit: 2 Data */ + uint32_t DATABUF:1; /*!< bit: 3 Data Buffer */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x10 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) Enable */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data */ +#define DAC_SYNCBUSY_DATA (_U_(0x1) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 3 /**< \brief (DAC_SYNCBUSY) Data Buffer */ +#define DAC_SYNCBUSY_DATABUF (_U_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_MASK _U_(0x0000000F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x14 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __O DAC_DATA_Type DATA; /**< \brief Offset: 0x08 ( /W 16) Data */ + RoReg8 Reserved2[0x2]; + __O DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0x0C ( /W 16) Data Buffer */ + RoReg8 Reserved3[0x2]; + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Busy */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x14 (R/W 8) Debug Control */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMC21_DAC_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/divas.h b/bsp/microchip/samc21/bsp/samc21/include/component/divas.h new file mode 100644 index 0000000000..0474ca4ef5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/divas.h @@ -0,0 +1,191 @@ +/** + * \file + * + * \brief Component description for DIVAS + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_DIVAS_COMPONENT_ +#define _SAMC21_DIVAS_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DIVAS */ +/* ========================================================================== */ +/** \addtogroup SAMC21_DIVAS Divide and Square Root Accelerator */ +/*@{*/ + +#define DIVAS_U2258 +#define REV_DIVAS 0x100 + +/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SIGNED:1; /*!< bit: 0 Signed */ + uint8_t DLZ:1; /*!< bit: 1 Disable Leading Zero Optimization */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DIVAS_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_CTRLA_OFFSET 0x00 /**< \brief (DIVAS_CTRLA offset) Control */ +#define DIVAS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DIVAS_CTRLA reset_value) Control */ + +#define DIVAS_CTRLA_SIGNED_Pos 0 /**< \brief (DIVAS_CTRLA) Signed */ +#define DIVAS_CTRLA_SIGNED (_U_(0x1) << DIVAS_CTRLA_SIGNED_Pos) +#define DIVAS_CTRLA_DLZ_Pos 1 /**< \brief (DIVAS_CTRLA) Disable Leading Zero Optimization */ +#define DIVAS_CTRLA_DLZ (_U_(0x1) << DIVAS_CTRLA_DLZ_Pos) +#define DIVAS_CTRLA_MASK _U_(0x03) /**< \brief (DIVAS_CTRLA) MASK Register */ + +/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BUSY:1; /*!< bit: 0 DIVAS Accelerator Busy */ + uint8_t DBZ:1; /*!< bit: 1 Writing a one to this bit clears DBZ to zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DIVAS_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_STATUS_OFFSET 0x04 /**< \brief (DIVAS_STATUS offset) Status */ +#define DIVAS_STATUS_RESETVALUE _U_(0x00) /**< \brief (DIVAS_STATUS reset_value) Status */ + +#define DIVAS_STATUS_BUSY_Pos 0 /**< \brief (DIVAS_STATUS) DIVAS Accelerator Busy */ +#define DIVAS_STATUS_BUSY (_U_(0x1) << DIVAS_STATUS_BUSY_Pos) +#define DIVAS_STATUS_DBZ_Pos 1 /**< \brief (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero */ +#define DIVAS_STATUS_DBZ (_U_(0x1) << DIVAS_STATUS_DBZ_Pos) +#define DIVAS_STATUS_MASK _U_(0x03) /**< \brief (DIVAS_STATUS) MASK Register */ + +/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DIVIDEND:32; /*!< bit: 0..31 DIVIDEND */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DIVAS_DIVIDEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_DIVIDEND_OFFSET 0x08 /**< \brief (DIVAS_DIVIDEND offset) Dividend */ +#define DIVAS_DIVIDEND_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVIDEND reset_value) Dividend */ + +#define DIVAS_DIVIDEND_DIVIDEND_Pos 0 /**< \brief (DIVAS_DIVIDEND) DIVIDEND */ +#define DIVAS_DIVIDEND_DIVIDEND_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) +#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & ((value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) +#define DIVAS_DIVIDEND_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVIDEND) MASK Register */ + +/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DIVISOR:32; /*!< bit: 0..31 DIVISOR */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DIVAS_DIVISOR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_DIVISOR_OFFSET 0x0C /**< \brief (DIVAS_DIVISOR offset) Divisor */ +#define DIVAS_DIVISOR_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVISOR reset_value) Divisor */ + +#define DIVAS_DIVISOR_DIVISOR_Pos 0 /**< \brief (DIVAS_DIVISOR) DIVISOR */ +#define DIVAS_DIVISOR_DIVISOR_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) +#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & ((value) << DIVAS_DIVISOR_DIVISOR_Pos)) +#define DIVAS_DIVISOR_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVISOR) MASK Register */ + +/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) (R/ 32) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RESULT:32; /*!< bit: 0..31 RESULT */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DIVAS_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_RESULT_OFFSET 0x10 /**< \brief (DIVAS_RESULT offset) Result */ +#define DIVAS_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_RESULT reset_value) Result */ + +#define DIVAS_RESULT_RESULT_Pos 0 /**< \brief (DIVAS_RESULT) RESULT */ +#define DIVAS_RESULT_RESULT_Msk (_U_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) +#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & ((value) << DIVAS_RESULT_RESULT_Pos)) +#define DIVAS_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_RESULT) MASK Register */ + +/* -------- DIVAS_REM : (DIVAS Offset: 0x14) (R/ 32) Remainder -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t REM:32; /*!< bit: 0..31 REM */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DIVAS_REM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_REM_OFFSET 0x14 /**< \brief (DIVAS_REM offset) Remainder */ +#define DIVAS_REM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_REM reset_value) Remainder */ + +#define DIVAS_REM_REM_Pos 0 /**< \brief (DIVAS_REM) REM */ +#define DIVAS_REM_REM_Msk (_U_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) +#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & ((value) << DIVAS_REM_REM_Pos)) +#define DIVAS_REM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_REM) MASK Register */ + +/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SQRNUM:32; /*!< bit: 0..31 Square Root Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DIVAS_SQRNUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DIVAS_SQRNUM_OFFSET 0x18 /**< \brief (DIVAS_SQRNUM offset) Square Root Input */ +#define DIVAS_SQRNUM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_SQRNUM reset_value) Square Root Input */ + +#define DIVAS_SQRNUM_SQRNUM_Pos 0 /**< \brief (DIVAS_SQRNUM) Square Root Input */ +#define DIVAS_SQRNUM_SQRNUM_Msk (_U_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) +#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & ((value) << DIVAS_SQRNUM_SQRNUM_Pos)) +#define DIVAS_SQRNUM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_SQRNUM) MASK Register */ + +/** \brief DIVAS hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DIVAS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO DIVAS_STATUS_Type STATUS; /**< \brief Offset: 0x04 (R/W 8) Status */ + RoReg8 Reserved2[0x3]; + __IO DIVAS_DIVIDEND_Type DIVIDEND; /**< \brief Offset: 0x08 (R/W 32) Dividend */ + __IO DIVAS_DIVISOR_Type DIVISOR; /**< \brief Offset: 0x0C (R/W 32) Divisor */ + __I DIVAS_RESULT_Type RESULT; /**< \brief Offset: 0x10 (R/ 32) Result */ + __I DIVAS_REM_Type REM; /**< \brief Offset: 0x14 (R/ 32) Remainder */ + __IO DIVAS_SQRNUM_Type SQRNUM; /**< \brief Offset: 0x18 (R/W 32) Square Root Input */ +} Divas; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMC21_DIVAS_COMPONENT_ */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/component/dmac.h b/bsp/microchip/samc21/bsp/samc21/include/component/dmac.h new file mode 100644 index 0000000000..b28b2e7519 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/component/dmac.h @@ -0,0 +1,1069 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21_DMAC_COMPONENT_ +#define _SAMC21_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAMC21_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x223 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U_(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK _U_(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK _U_(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ +#define DMAC_QOSCTRL_RESETVALUE _U_(0x2A) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ + +#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ +#define DMAC_QOSCTRL_WRBQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) +#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ +#define DMAC_QOSCTRL_FQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) +#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_FQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_FQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ +#define DMAC_QOSCTRL_DQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) +#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_MASK _U_(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U_(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U_(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U_(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK _U_(0x0F) /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ +#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_MASK _U_(0x43) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U_(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21E15A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21E15A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21E15A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21E15A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21E15A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21E15A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21E15A Serial Communication Interface 3 (SERCOM3) */ + CAN0_IRQn = 15, /**< 15 SAMC21E15A Control Area Network 0 (CAN0) */ + TCC0_IRQn = 17, /**< 17 SAMC21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21E15A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21E15A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21E15A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21E15A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21E15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21E15A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21E15A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21E15A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21E15A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21E15A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21E15A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21E15A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21e15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1101050D) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */ +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21E15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21E15A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21e16a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21e16a.h new file mode 100644 index 0000000000..7211f4a3cb --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21e16a.h @@ -0,0 +1,638 @@ +/** + * \file + * + * \brief Header file for SAMC21E16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21E16A_ +#define _SAMC21E16A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21E16A_definitions SAMC21E16A definitions + * This file defines all structures and symbols for SAMC21E16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21E16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21E16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21E16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21E16A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21E16A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21E16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21E16A Serial Communication Interface 3 (SERCOM3) */ + CAN0_IRQn = 15, /**< 15 SAMC21E16A Control Area Network 0 (CAN0) */ + TCC0_IRQn = 17, /**< 17 SAMC21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21E16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21E16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21E16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21E16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21E16A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21E16A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21E16A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21E16A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21E16A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21E16A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21E16A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21e16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1101050C) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21E16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21E16A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21e17a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21e17a.h new file mode 100644 index 0000000000..0fb457fb5e --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21e17a.h @@ -0,0 +1,638 @@ +/** + * \file + * + * \brief Header file for SAMC21E17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21E17A_ +#define _SAMC21E17A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21E17A_definitions SAMC21E17A definitions + * This file defines all structures and symbols for SAMC21E17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21E17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21E17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21E17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21E17A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21E17A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21E17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21E17A Serial Communication Interface 3 (SERCOM3) */ + CAN0_IRQn = 15, /**< 15 SAMC21E17A Control Area Network 0 (CAN0) */ + TCC0_IRQn = 17, /**< 17 SAMC21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21E17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21E17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21E17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21E17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21E17A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21E17A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21E17A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21E17A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21E17A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21E17A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21E17A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21e17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1101050B) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21E17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21E17A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21e18a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21e18a.h new file mode 100644 index 0000000000..3c6ccd4359 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21e18a.h @@ -0,0 +1,638 @@ +/** + * \file + * + * \brief Header file for SAMC21E18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21E18A_ +#define _SAMC21E18A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21E18A_definitions SAMC21E18A definitions + * This file defines all structures and symbols for SAMC21E18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21E18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21E18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21E18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21E18A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21E18A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21E18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21E18A Serial Communication Interface 3 (SERCOM3) */ + CAN0_IRQn = 15, /**< 15 SAMC21E18A Control Area Network 0 (CAN0) */ + TCC0_IRQn = 17, /**< 17 SAMC21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21E18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21E18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21E18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21E18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21E18A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21E18A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21E18A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21E18A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21E18A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21E18A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21E18A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pvReserved16; + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void CAN0_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21E18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21e18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1101050A) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21E18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21E18A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21g15a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21g15a.h new file mode 100644 index 0000000000..1b71d5b39a --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21g15a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21G15A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21G15A_ +#define _SAMC21G15A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21G15A_definitions SAMC21G15A definitions + * This file defines all structures and symbols for SAMC21G15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21G15A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21G15A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21G15A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21G15A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21G15A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21G15A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21G15A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21G15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21G15A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21G15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21G15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21G15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21G15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21G15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21G15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21G15A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21G15A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21G15A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21G15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21G15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21G15A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21G15A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21G15A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21G15A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21G15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21G15A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21G15A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21G15A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21G15A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21G15A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21G15A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21G15A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21g15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010508) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21G15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21G15A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21g16a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21g16a.h new file mode 100644 index 0000000000..cac21f20ee --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21g16a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21G16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21G16A_ +#define _SAMC21G16A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21G16A_definitions SAMC21G16A definitions + * This file defines all structures and symbols for SAMC21G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21G16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21G16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21G16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21G16A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21G16A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21G16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21G16A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21G16A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21G16A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21G16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21G16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21G16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21G16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21G16A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21G16A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21G16A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21G16A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21G16A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21G16A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21G16A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010507) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21G16A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21g17a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21g17a.h new file mode 100644 index 0000000000..7d2d2a0f13 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21g17a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21G17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21G17A_ +#define _SAMC21G17A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21G17A_definitions SAMC21G17A definitions + * This file defines all structures and symbols for SAMC21G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21G17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21G17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21G17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21G17A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21G17A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21G17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21G17A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21G17A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21G17A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21G17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21G17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21G17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21G17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21G17A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21G17A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21G17A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21G17A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21G17A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21G17A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21G17A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010506) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21G17A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21g18a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21g18a.h new file mode 100644 index 0000000000..03b7af1fdd --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21g18a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21G18A_ +#define _SAMC21G18A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21G18A_definitions SAMC21G18A definitions + * This file defines all structures and symbols for SAMC21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21G18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21G18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21G18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21G18A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21G18A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21G18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21G18A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21G18A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21G18A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21G18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21G18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21G18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21G18A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21G18A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21G18A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21G18A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21G18A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21G18A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21G18A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010505) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21G18A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j15a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j15a.h new file mode 100644 index 0000000000..6742fb576c --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j15a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J15A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J15A_ +#define _SAMC21J15A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J15A_definitions SAMC21J15A definitions + * This file defines all structures and symbols for SAMC21J15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J15A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J15A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J15A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J15A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J15A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J15A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J15A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J15A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J15A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J15A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J15A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J15A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J15A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J15A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J15A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J15A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J15A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J15A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J15A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J15A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J15A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J15A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010503) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J15A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j16a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j16a.h new file mode 100644 index 0000000000..c3915660f4 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j16a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J16A_ +#define _SAMC21J16A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J16A_definitions SAMC21J16A definitions + * This file defines all structures and symbols for SAMC21J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J16A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J16A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J16A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J16A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J16A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J16A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J16A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J16A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J16A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J16A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J16A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J16A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J16A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J16A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J16A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J16A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J16A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J16A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J16A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J16A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010502) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J16A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j17a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j17a.h new file mode 100644 index 0000000000..92082d1ba1 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j17a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J17A_ +#define _SAMC21J17A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J17A_definitions SAMC21J17A definitions + * This file defines all structures and symbols for SAMC21J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J17A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J17A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J17A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J17A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J17A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J17A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J17A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J17A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J17A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J17A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J17A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J17A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J17A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J17A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J17A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J17A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J17A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J17A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J17A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J17A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010501) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J17A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j17au.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j17au.h new file mode 100644 index 0000000000..ba916eefd5 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j17au.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J17AU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J17AU_ +#define _SAMC21J17AU_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J17AU_definitions SAMC21J17AU definitions + * This file defines all structures and symbols for SAMC21J17AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J17AU-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J17AU System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J17AU Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J17AU Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J17AU External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J17AU Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J17AU Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J17AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J17AU Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J17AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J17AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J17AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J17AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J17AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J17AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J17AU Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J17AU Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J17AU Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J17AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J17AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J17AU Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J17AU Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J17AU Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J17AU Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J17AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J17AU Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J17AU Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J17AU Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J17AU Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J17AU Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J17AU Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J17AU Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J17AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j17au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010510) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J17AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J17AU_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j18a.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j18a.h new file mode 100644 index 0000000000..27afccbe38 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j18a.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J18A_ +#define _SAMC21J18A_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J18A_definitions SAMC21J18A definitions + * This file defines all structures and symbols for SAMC21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J18A External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J18A Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J18A Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J18A Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J18A Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J18A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J18A Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J18A Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J18A Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J18A Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J18A Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J18A Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J18A Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J18A Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x11010500) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J18A_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/samc21j18au.h b/bsp/microchip/samc21/bsp/samc21/include/samc21j18au.h new file mode 100644 index 0000000000..976e882231 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/samc21j18au.h @@ -0,0 +1,656 @@ +/** + * \file + * + * \brief Header file for SAMC21J18AU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMC21J18AU_ +#define _SAMC21J18AU_ + +/** + * \ingroup SAMC21_definitions + * \addtogroup SAMC21J18AU_definitions SAMC21J18AU definitions + * This file defines all structures and symbols for SAMC21J18AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMC21J18AU-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAMC21J18AU System Interrupts */ + WDT_IRQn = 1, /**< 1 SAMC21J18AU Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAMC21J18AU Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAMC21J18AU External Interrupt Controller (EIC) */ + FREQM_IRQn = 4, /**< 4 SAMC21J18AU Frequency Meter (FREQM) */ + TSENS_IRQn = 5, /**< 5 SAMC21J18AU Temperature Sensor (TSENS) */ + NVMCTRL_IRQn = 6, /**< 6 SAMC21J18AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 7, /**< 7 SAMC21J18AU Direct Memory Access Controller (DMAC) */ + EVSYS_IRQn = 8, /**< 8 SAMC21J18AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMC21J18AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMC21J18AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMC21J18AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMC21J18AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMC21J18AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMC21J18AU Serial Communication Interface 5 (SERCOM5) */ + CAN0_IRQn = 15, /**< 15 SAMC21J18AU Control Area Network 0 (CAN0) */ + CAN1_IRQn = 16, /**< 16 SAMC21J18AU Control Area Network 1 (CAN1) */ + TCC0_IRQn = 17, /**< 17 SAMC21J18AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 18, /**< 18 SAMC21J18AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 19, /**< 19 SAMC21J18AU Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 20, /**< 20 SAMC21J18AU Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 21, /**< 21 SAMC21J18AU Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 22, /**< 22 SAMC21J18AU Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 23, /**< 23 SAMC21J18AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 24, /**< 24 SAMC21J18AU Basic Timer Counter 4 (TC4) */ + ADC0_IRQn = 25, /**< 25 SAMC21J18AU Analog Digital Converter 0 (ADC0) */ + ADC1_IRQn = 26, /**< 26 SAMC21J18AU Analog Digital Converter 1 (ADC1) */ + AC_IRQn = 27, /**< 27 SAMC21J18AU Analog Comparators (AC) */ + DAC_IRQn = 28, /**< 28 SAMC21J18AU Digital Analog Converter (DAC) */ + SDADC_IRQn = 29, /**< 29 SAMC21J18AU Sigma-Delta Analog Digital Converter (SDADC) */ + PTC_IRQn = 30, /**< 30 SAMC21J18AU Peripheral Touch Controller (PTC) */ + + PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnFREQM_Handler; /* 4 Frequency Meter */ + void* pfnTSENS_Handler; /* 5 Temperature Sensor */ + void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ + void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ + void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ + void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ + void* pfnAC_Handler; /* 27 Analog Comparators */ + void* pfnDAC_Handler; /* 28 Digital Analog Converter */ + void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ + void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void FREQM_Handler ( void ); +void TSENS_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC0_Handler ( void ); +void ADC1_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void SDADC_Handler ( void ); +void PTC_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samc21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/divas.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdadc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/tsens.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/divas.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrixhs.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdadc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tsens.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ + +// Peripheral instances on HPB1 bridge +#define ID_PORT 32 /**< \brief Port Module (PORT) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ + +// Peripheral instances on HPB2 bridge +#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ +#define ID_AC 84 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on AHB (as if on bridge 3) +#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */ + +#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42005000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ +#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ +#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ +#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ +#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ +#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ +#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ +#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ +#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ +#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ + +#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 37 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ +#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ +#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ +#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ +#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ +/** \defgroup SAMC21J18AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samc21j18au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1101050F) +#define AC_PAIRS 2 +#define DMAC_CH_NUM 12 +#define EVSYS_CHANNELS 12 +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMC21J18AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMC21J18AU_H */ diff --git a/bsp/microchip/samc21/bsp/samc21/include/system_samc21.h b/bsp/microchip/samc21/bsp/samc21/include/system_samc21.h new file mode 100644 index 0000000000..e46685f058 --- /dev/null +++ b/bsp/microchip/samc21/bsp/samc21/include/system_samc21.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMC21_H_INCLUDED_ +#define _SYSTEM_SAMC21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMC21_H_INCLUDED */ diff --git a/bsp/microchip/samc21/rtconfig.h b/bsp/microchip/samc21/rtconfig.h new file mode 100644 index 0000000000..f9df6f8303 --- /dev/null +++ b/bsp/microchip/samc21/rtconfig.h @@ -0,0 +1,180 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 200 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40100 +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* POSIX extension functions */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_SAMC21J18 + +/* Onboard Peripheral Drivers */ + +#define SAMC21_CAN0 +#define SAMC21_ADC0 + +/* Application Demo Config */ + +#define SAM_CAN_EXAMPLE +#define SAM_ADC_EXAMPLE +#define SOC_SAMC21 + +#endif diff --git a/bsp/microchip/samc21/rtconfig.py b/bsp/microchip/samc21/rtconfig.py new file mode 100644 index 0000000000..23ed9c87e2 --- /dev/null +++ b/bsp/microchip/samc21/rtconfig.py @@ -0,0 +1,67 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m0' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +DEVICE_SERIES = 'SAMC21' +#DEVICE_SERIES = 'SAMC20' +DEVICE_TYPE = '__SAMC21J18A__' +#DEVICE_TYPE = '__SAMC21G18A__' +DEVICE_PART = 'samc21' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/workspace/tools/embedcpp/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections -mlong-calls' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T bsp/samc21/gcc/gcc/samc21j18a_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + diff --git a/bsp/microchip/same54/.config b/bsp/microchip/same54/.config new file mode 100644 index 0000000000..1d00d6b9d6 --- /dev/null +++ b/bsp/microchip/same54/.config @@ -0,0 +1,649 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40100 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +# CONFIG_RT_USING_MSH is not set +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SAME54P20=y +# CONFIG_SOC_SAME54N20 is not set +# CONFIG_SOC_SAME53J20 is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_SAME5X_CAN0=y +CONFIG_SAME5X_ADC0=y + +# +# Application Demo Config +# +CONFIG_SAM_CAN_EXAMPLE=y +CONFIG_SAM_ADC_EXAMPLE=y +CONFIG_SOC_SAME54=y diff --git a/bsp/microchip/same54/.ignore_format.yml b/bsp/microchip/same54/.ignore_format.yml new file mode 100644 index 0000000000..988269df37 --- /dev/null +++ b/bsp/microchip/same54/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- bsp diff --git a/bsp/microchip/same54/Kconfig b/bsp/microchip/same54/Kconfig new file mode 100644 index 0000000000..9d8529609b --- /dev/null +++ b/bsp/microchip/same54/Kconfig @@ -0,0 +1,31 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default: "rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config SOC_SAME54 + bool + select ARCH_ARM + select ARCH_ARM_CORTEX_M + select ARCH_ARM_CORTEX_M4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/microchip/same54/README.md b/bsp/microchip/same54/README.md new file mode 100644 index 0000000000..2b814de380 --- /dev/null +++ b/bsp/microchip/same54/README.md @@ -0,0 +1,106 @@ +# SAME54P20A BSP Introduction + +[中文](README_zh.md) +- MCU: ATSAME54P20A @120MHz, 1MB FLASH, 256KB RAM +- E54: Cortex-M4F + Advanced Feature Set + Ethernet + 2x CAN-FD +- Pin: G=48 pins, J=64 pins, N=100 pins, P=128 pins +- Flash: 18=256KB, 19=512KB, 20=1024KB (size=2^n) +- SRAM : 128KB(Flash 256KB), 192KB(Flash 512KB), 256KB(Flash 1MB) +- Datasheet: + +#### KEY FEATURES + +#### Core + - 32-bit Arm® Cortex®-M4 core with single-precision FPU and 4 KB combined instruction cache and data cache; frequency up to 120 MHz, MPU, 403 CoreMark® at 120 MHz, and DSP instructions + +#### Memories + - 1 MB/512 KB/256 KB in-system self-programmable Flash with: + - Error Correction Code (ECC) + - Dual bank with Read-While-Write (RWW) support + - EEPROM hardware emulation + - 128 KB, 192 KB, 256 KB SRAM main memory + - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option + - Up to 4 KB of Tightly Coupled Memory (TCM) + - Up to 8 KB additional SRAM + - Can be retained in backup mode + - Eight 32-bit backup registers + +#### System + - Power-on Reset (POR) and Brown-out detection (BOD) + - Internal and external clock options + - External Interrupt Controller (EIC) + - 16 external interrupts + - One non-maskable interrupt + - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface + +#### High-Performance Peripherals + - 32-channel Direct Memory Access Controller (DMAC) + - Up to two SD/MMC Host Controller (SDHC) + - Up to 50 MHz operation + - 4-bit or 1-bit interface + - Compatibility with SD and SDHC memory card specification version 3.01 + - Compatibility with SDIO specification version 3.0 + - Compliant with JDEC specification, MMC memory cards V4.51 + - One Quad I/O Serial Peripheral Interface (QSPI) + - Dedicated AHB memory zone + - One Ethernet MAC (SAM E53 and SAM E54)– 10/100 Mbps in MII and RMII with dedicated DMA + - IEEE® 1588 Precision Time Protocol (PTP) support + - IEEE 1588 Time Stamping Unit (TSU) support + - IEEE802.3AZ energy efficiency support + - Support for 802.1AS and 1588 precision clock synchronization protocol + - Wake on LAN support + - Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54) + - Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016) + - One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface + - Embedded host and device function + - Eight endpoints + - On-chip transceiver with integrated serial resistor + +#### System Peripherals + - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination + - Five Parallel Input/Output Controllers (PIO) + - 32-channel Event System + - Up to eight Serial Communication Interfaces (SERCOM), can be configured as USART/I2C/SPI + - Up to eight 16-bit Timers/Counters (TC), can be configured as 8/16/32bit TC. + - Two 24-bit Timer/Counters for Control (TCC), with extended functions + - Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions. + - 32-bit Real Time Counter (RTC) with clock/calendar function + - Up to 4 wake-up pins with tamper detection and debouncing filter + - Watchdog Timer (WDT) with Window mode + - CRC-32 generator + - One two-channel Inter-IC Sound Interface (I2S) + - Position Decoder (PDEC) + - Frequency meter (FREQM) + - Four Configurable Custom Logic (CCL) + - Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each: + - Dual 12-bit, 1 MSPS output Digital-to-Analog Converter (DAC) + - Two Analog Comparators (AC) with Window Compare function + - One temperature sensor + - Parallel Capture Controller (PCC) + - Peripheral Touch Controller (PTC) - Capacitive Touch buttons, sliders, and wheels + +#### Cryptography + - One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate + - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR) + - Supports counter with CBC-MAC mode + - Galois Counter Mode (GCM) - True Random Number Generator (TRNG) + - Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL) + - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p) + - Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted + +#### I/O + - Up to 99 programmable I/O pins + +#### Qualification + - AEC-Q100 Grade 1 (-40°C to 125°C) + +#### Package Type + - VQFN48, 48-lead VQFN, 7x7 mm, pitch 0.5 mm, I/O Pins up to 37 + - VQFN64, 64-lead VQFN, 9x9 mm, pitch 0.5 mm, I/O Pins up to 51 + - TQFP64, 64-lead TQFP, 10x10 mm, pitch 0.5 mm, I/O Pins up to 51 + - TQFP100, 100-lead TQFP, 14x14 mm, pitch 0.5 mm, I/O Pins up to 81 + - TQFP128, 128-lead TQFP, 14x14 mm, pitch 0.4 mm, I/O Pins up to 99 + - TFBGA120, 120-ball TFBGA, 8x8 mm, pitch 0.5 mm, I/O Pins up to 90 + +#### Board info +- [SAM E54 XPLAINED PRO](https://www.microchip.com/en-us/development-tool/DM320019-BNDL) diff --git a/bsp/microchip/same54/README_zh.md b/bsp/microchip/same54/README_zh.md new file mode 100644 index 0000000000..98cb48d679 --- /dev/null +++ b/bsp/microchip/same54/README_zh.md @@ -0,0 +1,106 @@ +# SAME54P20A BSP 介绍 + +[English](README.md) +- MCU: ATSAME54P20A @120MHz, 1MB FLASH, 256KB RAM +- E54: Cortex-M4F + 100M Ethernet + 2路CAN-FD +- 管脚: G系列-48 pins, J系列-64 pins, N系列-100 pins, P系列-128 pins +- Flash: 尾缀18=256KB, 19=512KB, 20=1024KB (size=2^n) +- SRAM : 128KB(Flash 256KB), 192KB(Flash 512KB), 256KB(Flash 1MB) +- 手册: + +#### 关键特性 + +#### 内核 + - 32-bit Arm® Cortex®-M4 内核 + 单精度FPU + 4 KB 复用的指令和数据Cache，最大工作主频120 MHz, 带MPU, 403 CoreMark®@120 MHz, 支持 DSP指令集 + +#### 内存 + - 1 MB/512 KB/256 KB in-system self-programmable Flash with: + - Error Correction Code (ECC) + - Dual bank with Read-While-Write (RWW) support + - EEPROM hardware emulation + - 128 KB, 192 KB, 256 KB SRAM main memory + - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option + - Up to 4 KB of Tightly Coupled Memory (TCM) + - Up to 8 KB additional SRAM + - Can be retained in backup mode + - Eight 32-bit backup registers + +#### 系统特性 + - Power-on Reset (POR) and Brown-out detection (BOD) + - Internal and external clock options + - External Interrupt Controller (EIC) + - 16 external interrupts + - One non-maskable interrupt + - Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface + +#### 高性能外设 + - 32-channel Direct Memory Access Controller (DMAC) + - Up to two SD/MMC Host Controller (SDHC) + - Up to 50 MHz operation + - 4-bit or 1-bit interface + - Compatibility with SD and SDHC memory card specification version 3.01 + - Compatibility with SDIO specification version 3.0 + - Compliant with JDEC specification, MMC memory cards V4.51 + - One Quad I/O Serial Peripheral Interface (QSPI) + - Dedicated AHB memory zone + - One Ethernet MAC (SAM E53 and SAM E54)– 10/100 Mbps in MII and RMII with dedicated DMA + - IEEE® 1588 Precision Time Protocol (PTP) support + - IEEE 1588 Time Stamping Unit (TSU) support + - IEEE802.3AZ energy efficiency support + - Support for 802.1AS and 1588 precision clock synchronization protocol + - Wake on LAN support + - Up to two Controller Area Network (CAN) (that is., SAM E51 and SAM E54) + - Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO 11898-1:2016) + - One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface + - Embedded host and device function + - Eight endpoints + - On-chip transceiver with integrated serial resistor + +#### 系统外设 + - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination + - Five Parallel Input/Output Controllers (PIO) + - 32-channel Event System + - Up to eight Serial Communication Interfaces (SERCOM), can be configured as USART/I2C/SPI + - Up to eight 16-bit Timers/Counters (TC), can be configured as 8/16/32bit TC. + - Two 24-bit Timer/Counters for Control (TCC), with extended functions + - Up to Three 16-bit Timer/Counters for Control (TCC) with extended functions. + - 32-bit Real Time Counter (RTC) with clock/calendar function + - Up to 4 wake-up pins with tamper detection and debouncing filter + - Watchdog Timer (WDT) with Window mode + - CRC-32 generator + - One two-channel Inter-IC Sound Interface (I2S) + - Position Decoder (PDEC) + - Frequency meter (FREQM) + - Four Configurable Custom Logic (CCL) + - Dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) with up to 16 channels each: + - Dual 12-bit, 1 MSPS output Digital-to-Analog Converter (DAC) + - Two Analog Comparators (AC) with Window Compare function + - One temperature sensor + - Parallel Capture Controller (PCC) + - Peripheral Touch Controller (PTC) - Capacitive Touch buttons, sliders, and wheels + +#### 加密功能 + - One Advanced Encryption System (AES) with 256-bit key length and up to 2 MB/s data rate + - Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR) + - Supports counter with CBC-MAC mode + - Galois Counter Mode (GCM) - True Random Number Generator (TRNG) + - Public Key Cryptography Controller (PUKCC) and associated Classical Public Key Cryptography Library (PUKCL) + - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p) + - Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA assisted + +#### I/O管脚 + - 最多提供99个用户可编程I/O管脚 + +#### 汽车应用 + - AEC-Q100 Grade 1 (-40°C to 125°C) + +#### 封装 + - VQFN48, 48-lead VQFN, 7x7 mm, pitch 0.5 mm, I/O Pins up to 37 + - VQFN64, 64-lead VQFN, 9x9 mm, pitch 0.5 mm, I/O Pins up to 51 + - TQFP64, 64-lead TQFP, 10x10 mm, pitch 0.5 mm, I/O Pins up to 51 + - TQFP100, 100-lead TQFP, 14x14 mm, pitch 0.5 mm, I/O Pins up to 81 + - TQFP128, 128-lead TQFP, 14x14 mm, pitch 0.4 mm, I/O Pins up to 99 + - TFBGA120, 120-ball TFBGA, 8x8 mm, pitch 0.5 mm, I/O Pins up to 90 + +#### 官方开发板信息 +- [SAM E54 XPLAINED PRO](https://www.microchip.com/en-us/development-tool/DM320019-BNDL) \ No newline at end of file diff --git a/bsp/microchip/same54/SConscript b/bsp/microchip/same54/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/microchip/same54/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/microchip/same54/SConstruct b/bsp/microchip/same54/SConstruct new file mode 100644 index 0000000000..4d91cd5ba5 --- /dev/null +++ b/bsp/microchip/same54/SConstruct @@ -0,0 +1,41 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/microchip/same54/applications/SConscript b/bsp/microchip/same54/applications/SConscript new file mode 100644 index 0000000000..e806dae56e --- /dev/null +++ b/bsp/microchip/same54/applications/SConscript @@ -0,0 +1,10 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/microchip/same54/applications/can_demo.c b/bsp/microchip/same54/applications/can_demo.c new file mode 100644 index 0000000000..a21f755725 --- /dev/null +++ b/bsp/microchip/same54/applications/can_demo.c @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include "driver_init.h" +#include "utils.h" + +#include "can_demo.h" + +#ifdef SAM_CAN_EXAMPLE + +static volatile enum can_async_interrupt_type can_errors; +static rt_sem_t can_txdone; +static rt_sem_t can_rxdone; +static rt_uint8_t can_stack[ 512 ]; +static struct rt_thread can_thread; + +/** + * @brief Callback function and should be invoked after call can_async_write. + * + * @note + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_tx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_txdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after remote device send. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_rx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after CAN device IRQ handler detects errors happened. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_err_callback(struct can_async_descriptor *const descr, + enum can_async_interrupt_type type) +{ + rt_err_t result; + + if (type == CAN_IRQ_EW) + { + /* Error warning, Error counter has reached the error warning limit of 96, + * An error count value greater than about 96 indicates a heavily disturbed + * bus. It may be of advantage to provide means to test for this condition. + */ + } + else if (type == CAN_IRQ_EA) + { + /* Error Active State, The CAN node normally take part in bus communication + * and sends an ACTIVE ERROR FLAG when an error has been detected. + */ + } + else if (type == CAN_IRQ_EP) + { + /* Error Passive State, The Can node goes into error passive state if at least + * one of its error counters is greater than 127. It still takes part in bus + * activities, but it sends a passive error frame only, on errors. + */ + } + else if (type == CAN_IRQ_BO) + { + /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is + * greater than or equal to 256. + */ + + /* Suspend CAN task and re-initialize CAN module. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } + else if (type == CAN_IRQ_DO) + { + /* Data Overrun in receive queue. A message was lost because the messages in + * the queue was not reading and releasing fast enough. There is not enough + * space for a new message in receive queue. + */ + + /* Suggest to delete CAN task and re-initialize it. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } +}; + +/** + * @brief Initialize CAN module before task run. + * + * @note This function will set CAN Tx/Rx callback function and filters. + * + * @param None. + * + * @return None. + */ + +static inline void can_demo_init(void) +{ + struct can_filter filter; + + /** + * CAN_Node0_tx_callback callback should be invoked after call + * can_async_write, and remote device should receive message with ID=0x45A + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback); + + + /* Should set at least one CAN standard & message filter before enable it. */ + + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + /* If set second standard message filter, should increase filter index + * and filter algorithm + * For example: index should set to 1, otherwise it will replace filter 0. + * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */ + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter); + + can_async_enable(&CAN_0); +} + +/** + * @brief CAN task. + * + * @note This task will waiting for CAN RX semaphore and then process input. + * + * @param parameter - task input parameter. + * + * @return None. + */ + +static void can_thread_entry(void* parameter) +{ + int32_t ret; + rt_err_t result; + uint8_t data[64]; + uint32_t count=0; + struct can_message msg; + + while (1) + { +#ifndef RT_USING_FINSH + rt_kprintf("can task run count : %d\r\n",count); +#endif + count++; + + result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER); + if (RT_EOK != result) + continue; + + do + { + /* Process the incoming packet. */ + ret = can_async_read(&CAN_0, &msg); + if (ret == ERR_NONE) + { +#ifndef RT_USING_FINSH + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_TYPE_DATA ? "data" : "remote"); + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_FMT_STDID ? "Standard" : "Extended"); + rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len); + rt_kprintf("CAN RX Message content: "); + for (uint8_t i = 0; i < msg.len; i++) + rt_kprintf("0x%02X ", data[i]); + rt_kprintf("\r\n"); +#endif + } + } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */ + + /* CAN task got CAN error message, handler CAN Error Status */ + if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO)) + { + can_async_init(&CAN_0, CAN1); + } + } +} + +/** + * @brief Call this function will to send a CAN message. + * + * @note + * + * @param msg - message to be sent, timeouts - wait timeouts for Tx completion. + * + * @return RT_OK or RT_ERROR. + */ + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts) +{ + rt_err_t result; + + if (RT_NULL == msg) + { + rt_kprintf("can_send_message input message error\r\n"); + return RT_ERROR; + } + + can_async_write(&CAN_0, msg); + result = rt_sem_take(can_rxdone, timeouts); + + return result; +} + +/** + * @brief Call this function will create a CAN task. + * + * @note Should create Tx/Rx semaphore before run task. + * + * @param None. + * + * @return RT_OK or -RT_ERROR. + */ + +rt_err_t can_demo_run(void) +{ + rt_err_t result; + + can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_rxdone) + { + rt_kprintf("can_rx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_txdone) + { + rt_kprintf("can_tx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_demo_init(); + + /* initialize CAN thread */ + result = rt_thread_init(&can_thread, + "can", + can_thread_entry, + RT_NULL, + (rt_uint8_t*)&can_stack[0], + sizeof(can_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&can_thread); + } + + return result; +} +#endif + +/*@}*/ diff --git a/bsp/microchip/same54/applications/can_demo.h b/bsp/microchip/same54/applications/can_demo.h new file mode 100644 index 0000000000..499d0390f8 --- /dev/null +++ b/bsp/microchip/same54/applications/can_demo.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __APPLICATION_CAN_H_ +#define __APPLICATION_CAN_H_ + +#include + +/** + * @brief External function definitions + * + */ +rt_err_t can_demo_run(void); + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts); + +#endif // __APPLICATION_CAN_H_ diff --git a/bsp/microchip/same54/applications/main.c b/bsp/microchip/same54/applications/main.c new file mode 100644 index 0000000000..8985159058 --- /dev/null +++ b/bsp/microchip/same54/applications/main.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include + +#ifdef SAM_CAN_EXAMPLE +#include "can_demo.h" +#endif + +static rt_uint8_t led_stack[ 512 ]; +static struct rt_thread led_thread; + +static void led_thread_entry(void* parameter) +{ + unsigned int count=0; + + while (1) + { + /* toggle led */ +#ifndef RT_USING_FINSH + rt_kprintf("led toggle, count : %d\r\n",count); +#endif + count++; + gpio_toggle_pin_level(LED0); + rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */ + } +} + +int main(void) +{ + rt_err_t result; + + /* initialize led thread */ + result = rt_thread_init(&led_thread, + "led", + led_thread_entry, + RT_NULL, + (rt_uint8_t*)&led_stack[0], + sizeof(led_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&led_thread); + } + +#ifdef SAM_CAN_EXAMPLE + can_demo_run(); +#endif + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/same54/board/Kconfig b/bsp/microchip/same54/board/Kconfig new file mode 100644 index 0000000000..33a8121227 --- /dev/null +++ b/bsp/microchip/same54/board/Kconfig @@ -0,0 +1,52 @@ +menu "Hardware Drivers Config" + +choice + prompt "select chip type" + default SOC_SAME54P20 + + config SOC_SAME54P20 + bool "SOC_SAME54P20" + help + Refer to SAME54 DataSheet + + config SOC_SAME54N20 + bool "SOC_SAME54N20" + help + Refer to SAME54 DataSheet + + config SOC_SAME53J20 + bool "SOC_SAME53J20" + help + Refer to SAME54 DataSheet + +endchoice +endmenu + +menu "Onboard Peripheral Drivers" + depends on SOC_SAME54P20 || SOC_SAME54N20 + + config SAME5X_CAN0 + bool "Enable CAN0" + default false + + config SAME5X_ADC0 + bool "Enable ADC0" + default false +endmenu + +menu "Application Demo Config" + config SAM_CAN_EXAMPLE + bool "Enable SAM CAN Example" + depends on SAME5X_CAN0 + default true + help + Add CAN example task to project + + config SAM_ADC_EXAMPLE + bool "Enable SAM ADC Example" + depends on SAME5X_ADC0 + default true + help + Add ADC example task to project + +endmenu diff --git a/bsp/microchip/same54/board/SConscript b/bsp/microchip/same54/board/SConscript new file mode 100644 index 0000000000..3c6e1cad63 --- /dev/null +++ b/bsp/microchip/same54/board/SConscript @@ -0,0 +1,17 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +#remove other no use files +#SrcRemove(src, '*.c') + +# You can select chips from the list above +CPPDEFINES = ['SAME54xxx'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/microchip/same54/board/board.c b/bsp/microchip/same54/board/board.c new file mode 100644 index 0000000000..72f31efa6b --- /dev/null +++ b/bsp/microchip/same54/board/board.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#include +#include "peripheral_clk_config.h" + +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +extern int rt_hw_uart_init(void); +#endif + +static struct io_descriptor* g_stdio; + +void rt_hw_console_output(const char *str) +{ + io_write(g_stdio, (uint8_t *)str, strlen(str)); +} +RTM_EXPORT(rt_hw_console_output); + +static inline void hw_board_init_usart(void) +{ + usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio); + usart_sync_enable(&TARGET_IO); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial SAME54 board. + */ +void rt_hw_board_init(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* enable USART stdout module */ + hw_board_init_usart(); + + /* UART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + + /* init systick */ + SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND); + + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + +#ifdef RT_USING_HEAP + #if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END); + #elif __ICCARM__ + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END); + #endif +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/*@}*/ diff --git a/bsp/microchip/same54/board/board.h b/bsp/microchip/same54/board/board.h new file mode 100644 index 0000000000..e0bf12cb83 --- /dev/null +++ b/bsp/microchip/same54/board/board.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +// Internal SRAM memory size[Kbytes] <128-256> +// Default: 256 +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAME53J18A__) || defined(__ATSAME53J18A__) + #define SAME5x_SRAM_SIZE 128 +#elif defined(__SAME53J19A__) || defined(__ATSAME53J19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME53J20A__) || defined(__ATSAME53J20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAME53N19A__) || defined(__ATSAME53N19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME53N20A__) || defined(__ATSAME53N20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAME51J18A__) || defined(__ATSAME51J18A__) + #define SAME5x_SRAM_SIZE 128 +#elif defined(__SAME51J19A__) || defined(__ATSAME51J19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME51J20A__) || defined(__ATSAME51J20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAME51N19A__) || defined(__ATSAME51N19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAME51N20A__) || defined(__ATSAME51N20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) + #define SAME5x_SRAM_SIZE 128 +#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) + #define SAME5x_SRAM_SIZE 256 +#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) + #define SAME5x_SRAM_SIZE 192 +#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) + #define SAME5x_SRAM_SIZE 256 +#else + #error Board does not support the specified device. +#endif + +#define SAME5x_SRAM_END (0x20000000 + SAME5x_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_begin("HEAP")) +#define HEAP_END (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#define HEAP_END SAME5x_SRAM_END +#endif + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/microchip/same54/board/serial.c b/bsp/microchip/same54/board/serial.c new file mode 100644 index 0000000000..28ba104dbe --- /dev/null +++ b/bsp/microchip/same54/board/serial.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include +#include + +#include + +/* SAM MCU serial device */ +static struct rt_serial_device sam_serial; + +/** + * @brief Configure serial port + * + * This function will configure UART baudrate, parity and so on. + * + * @return RT_EOK. + */ +static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + usart_sync_disable(desc); + + /* Set baudrate */ + usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate); + + /* Set stop bit */ + if (cfg->stop_bits == STOP_BITS_1) + usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE); + else if (cfg->stop_bits == STOP_BITS_2) + usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO); + + if (cfg->bit_order == BIT_ORDER_LSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB); + else if (cfg->bit_order == BIT_ORDER_MSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB); + + /* Set character size */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS); + break; + case DATA_BITS_6: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS); + break; + case DATA_BITS_7: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS); + break; + case DATA_BITS_8: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS); + break; + case DATA_BITS_9: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS); + break; + default: + break; + } + + if (cfg->parity == PARITY_NONE) + usart_sync_set_parity(desc, USART_PARITY_NONE); + else if (cfg->parity == PARITY_ODD) + usart_sync_set_parity(desc, USART_PARITY_ODD); + else if (cfg->parity == PARITY_EVEN) + usart_sync_set_parity(desc, USART_PARITY_EVEN); + + usart_sync_enable(desc); + + return RT_EOK; +} + +/** + * @brief Control serial port + * + * This function provide UART enable/disable control. + * + * @return RT_EOK. + */ +static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + usart_sync_disable(desc); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + usart_sync_enable(desc); + break; + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + break; + } + + return RT_EOK; +} + +/** + * @brief Serial sends a char + * + * This function will send a char to the UART + * + * @return 1. + */ +static int serial_putc(struct rt_serial_device *serial, char c) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + io_write(&desc->io, (const uint8_t *)&c, 1); + + return 1; +} + +/** + * @brief Serial gets a char + * + * This function will get a char from the UART + * + * @return received char character or -1 if no char received. + */ +static int serial_getc(struct rt_serial_device *serial) +{ + char c; + int ch; + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + ch = -1; + if (usart_sync_is_rx_not_empty(desc)) + { + io_read(&desc->io, (uint8_t *)&c, 1);; + ch = c & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops sam_serial_ops = +{ + serial_configure, + serial_control, + serial_putc, + serial_getc, +}; + +/** + * @brief Initialize the UART + * + * This function initialize the UART + * + * @return None. + */ +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + sam_serial.ops = &sam_serial_ops; + sam_serial.config = config; + sam_serial.serial_rx = RT_NULL; + sam_serial.serial_rx = RT_NULL; + rt_hw_serial_register(&sam_serial, "uart0", + RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO); + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/same54/board/serial.h b/bsp/microchip/same54/board/serial.h new file mode 100644 index 0000000000..12e6811231 --- /dev/null +++ b/bsp/microchip/same54/board/serial.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __BOARD_SERIAL_H_ +#define __BOARD_SERIAL_H_ + +#include + +/** + * @brief External function definitions + * + */ +int rt_hw_uart_init(void); + +#endif // __BOARD_SERIAL_H_ diff --git a/bsp/microchip/same54/bsp/AtmelStart.env_conf b/bsp/microchip/same54/bsp/AtmelStart.env_conf new file mode 100644 index 0000000000..2033451072 --- /dev/null +++ b/bsp/microchip/same54/bsp/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/bsp/microchip/same54/bsp/AtmelStart.gpdsc b/bsp/microchip/same54/bsp/AtmelStart.gpdsc new file mode 100644 index 0000000000..0c0dab608c --- /dev/null +++ b/bsp/microchip/same54/bsp/AtmelStart.gpdsc @@ -0,0 +1,212 @@ + + Atmel + SAME54 LED switcher + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + + + + + + + + +
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-M):

+ +
+

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
+
+

+Processor Support

+

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

+

+Cortex-M Reference Manuals

+

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

+ +

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

+ +

+Armv8-M Architecture

+

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

+

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

+
+

+Tested and Verified Toolchains

+

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

+
    +
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • Arm: Arm Compiler 6.9
    • +
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • +
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • +
+
+
+
+ + + + diff --git a/bsp/microchip/same54/bsp/SConscript b/bsp/microchip/same54/bsp/SConscript new file mode 100644 index 0000000000..fa2e7a16c1 --- /dev/null +++ b/bsp/microchip/same54/bsp/SConscript @@ -0,0 +1,59 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +#var defined +CPPDEFINES = [] + +#common lib define +CPPDEFINES += [rtconfig.DEVICE_TYPE] + +# The set of source files associated with this SConscript file. +src = Glob('hal/src/*.c') +src += Glob('hal/utils/src/*.c') +src += Glob('hpl/aes/*.c') +src += Glob('hpl/can/*.c') +src += Glob('hpl/cmcc/*.c') +src += Glob('hpl/core/*.c') +src += Glob('hpl/dmac/*.c') +src += Glob('hpl/gclk/*.c') +src += Glob('hpl/mclk/*.c') +src += Glob('hpl/osc32kctrl/*.c') +src += Glob('hpl/oscctrl/*.c') +src += Glob('hpl/pm/*.c') +src += Glob('hpl/port/*.c') +src += Glob('hpl/ramecc/*.c') +src += Glob('hpl/sercom/*.c') +src += [cwd + '/atmel_start.c'] +src += [cwd + '/driver_init.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/gcc/system_same54.c'] + src += [cwd + '/gcc/gcc/startup_same54.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/armcc/arm_addon/armcc/' + 'system_same54.c'] + src += [cwd + '/armcc/arm_addon/armcc/arm/' + 'startup_same54.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/iar/' + 'system_same54.c'] + src += [cwd + '/iar/iar/' + 'startup_same54.c'] + +path = [ + cwd, + cwd + '/CMSIS/Core/Include', + cwd + '/config', + cwd + '/hal/include', + cwd + '/hal/utils/include', + cwd + '/hpl/can', + cwd + '/hpl/core', + cwd + '/hpl/gclk', + cwd + '/hpl/pm', + cwd + '/hpl/port', + cwd + '/hri', + cwd + '/include',] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/microchip/same54/bsp/armcc/Makefile b/bsp/microchip/same54/bsp/armcc/Makefile new file mode 100644 index 0000000000..2c08b246d7 --- /dev/null +++ b/bsp/microchip/same54/bsp/armcc/Makefile @@ -0,0 +1,225 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/pm \ +hpl/osc32kctrl \ +hpl/can \ +hpl/ramecc \ +hpl/dmac \ +hal/src \ +hpl/mclk \ +hpl/aes \ +hpl/sercom \ +examples \ +hpl/gclk \ +hpl/oscctrl \ +hal/utils/src \ +armcc/arm_addon/armcc/arm \ +armcc/arm_addon/armcc \ +hpl/core \ +hpl/cmcc + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hal/src/hal_can_async.o \ +armcc/arm_addon/armcc/system_same54.o \ +hpl/can/hpl_can.o \ +hpl/core/hpl_core_m4.o \ +hal/src/hal_cache.o \ +hpl/aes/hpl_aes.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/gclk/hpl_gclk.o \ +hal/utils/src/utils_list.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hal/src/hal_usart_sync.o \ +hpl/mclk/hpl_mclk.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/src/hal_init.o \ +main.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +examples/driver_examples.o \ +driver_init.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +hal/src/hal_aes_sync.o \ +hpl/cmcc/hpl_cmcc.o \ +atmel_start.o \ +hal/src/hal_atomic.o \ +armcc/arm_addon/armcc/arm/startup_same54.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hal/src/hal_can_async.o" \ +"armcc/arm_addon/armcc/system_same54.o" \ +"hpl/can/hpl_can.o" \ +"hpl/core/hpl_core_m4.o" \ +"hal/src/hal_cache.o" \ +"hpl/aes/hpl_aes.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/utils/src/utils_list.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/src/hal_init.o" \ +"main.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"hal/src/hal_aes_sync.o" \ +"hpl/cmcc/hpl_cmcc.o" \ +"atmel_start.o" \ +"hal/src/hal_atomic.o" \ +"armcc/arm_addon/armcc/arm/startup_same54.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"armcc/arm_addon/armcc/system_same54.d" \ +"hal/src/hal_can_async.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/can/hpl_can.d" \ +"hpl/aes/hpl_aes.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/cmcc/hpl_cmcc.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"hpl/mclk/hpl_mclk.d" \ +"driver_init.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"hal/src/hal_cache.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hal/src/hal_aes_sync.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"armcc/arm_addon/armcc/arm/startup_same54.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARMCC Linker + $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ +--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ +--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ +-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \ +$(OBJS_AS_ARGS) + + @echo Finished building target: $@ + +# Compiler target(s) + + + + +%.o: %.c + @echo Building file: $< + @echo ARMCC Compiler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARMCC Assembler + $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$(@:%.o=%.d)" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARMCC Preprocessing Assembler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/arm/startup_same54.s b/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/arm/startup_same54.s new file mode 100644 index 0000000000..3cd00bcbe9 --- /dev/null +++ b/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/arm/startup_same54.s @@ -0,0 +1,588 @@ +;/***************************************************************************** +; * @file startup_SAME54.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAME54 Device Series +; * @version V1.0.0 +; * @date 16. January 2017 +; * +; * @note +; * Copyright (C) 2017 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD MCLK_Handler ; 1 Main Clock + DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 + DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 + DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY + DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 + DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 + DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control + DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY + DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET + DCD WDT_Handler ; 10 Watchdog Timer + DCD RTC_Handler ; 11 Real-Time Counter + DCD EIC_0_Handler ; 12 EIC_EXTINT_0 + DCD EIC_1_Handler ; 13 EIC_EXTINT_1 + DCD EIC_2_Handler ; 14 EIC_EXTINT_2 + DCD EIC_3_Handler ; 15 EIC_EXTINT_3 + DCD EIC_4_Handler ; 16 EIC_EXTINT_4 + DCD EIC_5_Handler ; 17 EIC_EXTINT_5 + DCD EIC_6_Handler ; 18 EIC_EXTINT_6 + DCD EIC_7_Handler ; 19 EIC_EXTINT_7 + DCD EIC_8_Handler ; 20 EIC_EXTINT_8 + DCD EIC_9_Handler ; 21 EIC_EXTINT_9 + DCD EIC_10_Handler ; 22 EIC_EXTINT_10 + DCD EIC_11_Handler ; 23 EIC_EXTINT_11 + DCD EIC_12_Handler ; 24 EIC_EXTINT_12 + DCD EIC_13_Handler ; 25 EIC_EXTINT_13 + DCD EIC_14_Handler ; 26 EIC_EXTINT_14 + DCD EIC_15_Handler ; 27 EIC_EXTINT_15 + DCD FREQM_Handler ; 28 Frequency Meter + DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 + DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 + DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 + DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 + DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 + DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 + DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 + DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0 + DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1 + DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2 + DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3 + DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 + DCD PAC_Handler ; 41 Peripheral Access Controller + DCD TAL_0_Handler ; 42 TAL_BRK + DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1 + DCD 0 ; 44 Reserved + DCD RAMECC_Handler ; 45 RAM ECC + DCD SERCOM0_0_Handler ; 46 SERCOM0_0 + DCD SERCOM0_1_Handler ; 47 SERCOM0_1 + DCD SERCOM0_2_Handler ; 48 SERCOM0_2 + DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 + DCD SERCOM1_0_Handler ; 50 SERCOM1_0 + DCD SERCOM1_1_Handler ; 51 SERCOM1_1 + DCD SERCOM1_2_Handler ; 52 SERCOM1_2 + DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 + DCD SERCOM2_0_Handler ; 54 SERCOM2_0 + DCD SERCOM2_1_Handler ; 55 SERCOM2_1 + DCD SERCOM2_2_Handler ; 56 SERCOM2_2 + DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 + DCD SERCOM3_0_Handler ; 58 SERCOM3_0 + DCD SERCOM3_1_Handler ; 59 SERCOM3_1 + DCD SERCOM3_2_Handler ; 60 SERCOM3_2 + DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 + DCD SERCOM4_0_Handler ; 62 SERCOM4_0 + DCD SERCOM4_1_Handler ; 63 SERCOM4_1 + DCD SERCOM4_2_Handler ; 64 SERCOM4_2 + DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 + DCD SERCOM5_0_Handler ; 66 SERCOM5_0 + DCD SERCOM5_1_Handler ; 67 SERCOM5_1 + DCD SERCOM5_2_Handler ; 68 SERCOM5_2 + DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 + DCD SERCOM6_0_Handler ; 70 SERCOM6_0 + DCD SERCOM6_1_Handler ; 71 SERCOM6_1 + DCD SERCOM6_2_Handler ; 72 SERCOM6_2 + DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 + DCD SERCOM7_0_Handler ; 74 SERCOM7_0 + DCD SERCOM7_1_Handler ; 75 SERCOM7_1 + DCD SERCOM7_2_Handler ; 76 SERCOM7_2 + DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 + DCD CAN0_Handler ; 78 Control Area Network 0 + DCD CAN1_Handler ; 79 Control Area Network 1 + DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP + DCD USB_1_Handler ; 81 USB_SOF_HSOF + DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 + DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 + DCD GMAC_Handler ; 84 Ethernet MAC + DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A + DCD TCC0_1_Handler ; 86 TCC0_MC_0 + DCD TCC0_2_Handler ; 87 TCC0_MC_1 + DCD TCC0_3_Handler ; 88 TCC0_MC_2 + DCD TCC0_4_Handler ; 89 TCC0_MC_3 + DCD TCC0_5_Handler ; 90 TCC0_MC_4 + DCD TCC0_6_Handler ; 91 TCC0_MC_5 + DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A + DCD TCC1_1_Handler ; 93 TCC1_MC_0 + DCD TCC1_2_Handler ; 94 TCC1_MC_1 + DCD TCC1_3_Handler ; 95 TCC1_MC_2 + DCD TCC1_4_Handler ; 96 TCC1_MC_3 + DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A + DCD TCC2_1_Handler ; 98 TCC2_MC_0 + DCD TCC2_2_Handler ; 99 TCC2_MC_1 + DCD TCC2_3_Handler ; 100 TCC2_MC_2 + DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A + DCD TCC3_1_Handler ; 102 TCC3_MC_0 + DCD TCC3_2_Handler ; 103 TCC3_MC_1 + DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A + DCD TCC4_1_Handler ; 105 TCC4_MC_0 + DCD TCC4_2_Handler ; 106 TCC4_MC_1 + DCD TC0_Handler ; 107 Basic Timer Counter 0 + DCD TC1_Handler ; 108 Basic Timer Counter 1 + DCD TC2_Handler ; 109 Basic Timer Counter 2 + DCD TC3_Handler ; 110 Basic Timer Counter 3 + DCD TC4_Handler ; 111 Basic Timer Counter 4 + DCD TC5_Handler ; 112 Basic Timer Counter 5 + DCD TC6_Handler ; 113 Basic Timer Counter 6 + DCD TC7_Handler ; 114 Basic Timer Counter 7 + DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A + DCD PDEC_1_Handler ; 116 PDEC_MC_0 + DCD PDEC_2_Handler ; 117 PDEC_MC_1 + DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON + DCD ADC0_1_Handler ; 119 ADC0_RESRDY + DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON + DCD ADC1_1_Handler ; 121 ADC1_RESRDY + DCD AC_Handler ; 122 Analog Comparators + DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 + DCD DAC_1_Handler ; 124 DAC_EMPTY_0 + DCD DAC_2_Handler ; 125 DAC_EMPTY_1 + DCD DAC_3_Handler ; 126 DAC_RESRDY_0 + DCD DAC_4_Handler ; 127 DAC_RESRDY_1 + DCD I2S_Handler ; 128 Inter-IC Sound Interface + DCD PCC_Handler ; 129 Parallel Capture Controller + DCD AES_Handler ; 130 Advanced Encryption Standard + DCD TRNG_Handler ; 131 True Random Generator + DCD ICM_Handler ; 132 Integrity Check Monitor + DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller + DCD QSPI_Handler ; 134 Quad SPI interface + DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0 + DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT MCLK_Handler [WEAK] + EXPORT OSCCTRL_0_Handler [WEAK] + EXPORT OSCCTRL_1_Handler [WEAK] + EXPORT OSCCTRL_2_Handler [WEAK] + EXPORT OSCCTRL_3_Handler [WEAK] + EXPORT OSCCTRL_4_Handler [WEAK] + EXPORT OSC32KCTRL_Handler [WEAK] + EXPORT SUPC_0_Handler [WEAK] + EXPORT SUPC_1_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_0_Handler [WEAK] + EXPORT EIC_1_Handler [WEAK] + EXPORT EIC_2_Handler [WEAK] + EXPORT EIC_3_Handler [WEAK] + EXPORT EIC_4_Handler [WEAK] + EXPORT EIC_5_Handler [WEAK] + EXPORT EIC_6_Handler [WEAK] + EXPORT EIC_7_Handler [WEAK] + EXPORT EIC_8_Handler [WEAK] + EXPORT EIC_9_Handler [WEAK] + EXPORT EIC_10_Handler [WEAK] + EXPORT EIC_11_Handler [WEAK] + EXPORT EIC_12_Handler [WEAK] + EXPORT EIC_13_Handler [WEAK] + EXPORT EIC_14_Handler [WEAK] + EXPORT EIC_15_Handler [WEAK] + EXPORT FREQM_Handler [WEAK] + EXPORT NVMCTRL_0_Handler [WEAK] + EXPORT NVMCTRL_1_Handler [WEAK] + EXPORT DMAC_0_Handler [WEAK] + EXPORT DMAC_1_Handler [WEAK] + EXPORT DMAC_2_Handler [WEAK] + EXPORT DMAC_3_Handler [WEAK] + EXPORT DMAC_4_Handler [WEAK] + EXPORT EVSYS_0_Handler [WEAK] + EXPORT EVSYS_1_Handler [WEAK] + EXPORT EVSYS_2_Handler [WEAK] + EXPORT EVSYS_3_Handler [WEAK] + EXPORT EVSYS_4_Handler [WEAK] + EXPORT PAC_Handler [WEAK] + EXPORT TAL_0_Handler [WEAK] + EXPORT TAL_1_Handler [WEAK] + EXPORT RAMECC_Handler [WEAK] + EXPORT SERCOM0_0_Handler [WEAK] + EXPORT SERCOM0_1_Handler [WEAK] + EXPORT SERCOM0_2_Handler [WEAK] + EXPORT SERCOM0_3_Handler [WEAK] + EXPORT SERCOM1_0_Handler [WEAK] + EXPORT SERCOM1_1_Handler [WEAK] + EXPORT SERCOM1_2_Handler [WEAK] + EXPORT SERCOM1_3_Handler [WEAK] + EXPORT SERCOM2_0_Handler [WEAK] + EXPORT SERCOM2_1_Handler [WEAK] + EXPORT SERCOM2_2_Handler [WEAK] + EXPORT SERCOM2_3_Handler [WEAK] + EXPORT SERCOM3_0_Handler [WEAK] + EXPORT SERCOM3_1_Handler [WEAK] + EXPORT SERCOM3_2_Handler [WEAK] + EXPORT SERCOM3_3_Handler [WEAK] + EXPORT SERCOM4_0_Handler [WEAK] + EXPORT SERCOM4_1_Handler [WEAK] + EXPORT SERCOM4_2_Handler [WEAK] + EXPORT SERCOM4_3_Handler [WEAK] + EXPORT SERCOM5_0_Handler [WEAK] + EXPORT SERCOM5_1_Handler [WEAK] + EXPORT SERCOM5_2_Handler [WEAK] + EXPORT SERCOM5_3_Handler [WEAK] + EXPORT SERCOM6_0_Handler [WEAK] + EXPORT SERCOM6_1_Handler [WEAK] + EXPORT SERCOM6_2_Handler [WEAK] + EXPORT SERCOM6_3_Handler [WEAK] + EXPORT SERCOM7_0_Handler [WEAK] + EXPORT SERCOM7_1_Handler [WEAK] + EXPORT SERCOM7_2_Handler [WEAK] + EXPORT SERCOM7_3_Handler [WEAK] + EXPORT CAN0_Handler [WEAK] + EXPORT CAN1_Handler [WEAK] + EXPORT USB_0_Handler [WEAK] + EXPORT USB_1_Handler [WEAK] + EXPORT USB_2_Handler [WEAK] + EXPORT USB_3_Handler [WEAK] + EXPORT GMAC_Handler [WEAK] + EXPORT TCC0_0_Handler [WEAK] + EXPORT TCC0_1_Handler [WEAK] + EXPORT TCC0_2_Handler [WEAK] + EXPORT TCC0_3_Handler [WEAK] + EXPORT TCC0_4_Handler [WEAK] + EXPORT TCC0_5_Handler [WEAK] + EXPORT TCC0_6_Handler [WEAK] + EXPORT TCC1_0_Handler [WEAK] + EXPORT TCC1_1_Handler [WEAK] + EXPORT TCC1_2_Handler [WEAK] + EXPORT TCC1_3_Handler [WEAK] + EXPORT TCC1_4_Handler [WEAK] + EXPORT TCC2_0_Handler [WEAK] + EXPORT TCC2_1_Handler [WEAK] + EXPORT TCC2_2_Handler [WEAK] + EXPORT TCC2_3_Handler [WEAK] + EXPORT TCC3_0_Handler [WEAK] + EXPORT TCC3_1_Handler [WEAK] + EXPORT TCC3_2_Handler [WEAK] + EXPORT TCC4_0_Handler [WEAK] + EXPORT TCC4_1_Handler [WEAK] + EXPORT TCC4_2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT PDEC_0_Handler [WEAK] + EXPORT PDEC_1_Handler [WEAK] + EXPORT PDEC_2_Handler [WEAK] + EXPORT ADC0_0_Handler [WEAK] + EXPORT ADC0_1_Handler [WEAK] + EXPORT ADC1_0_Handler [WEAK] + EXPORT ADC1_1_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_0_Handler [WEAK] + EXPORT DAC_1_Handler [WEAK] + EXPORT DAC_2_Handler [WEAK] + EXPORT DAC_3_Handler [WEAK] + EXPORT DAC_4_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT PCC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT ICM_Handler [WEAK] + EXPORT PUKCC_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT SDHC0_Handler [WEAK] + EXPORT SDHC1_Handler [WEAK] + +PM_Handler +MCLK_Handler +OSCCTRL_0_Handler +OSCCTRL_1_Handler +OSCCTRL_2_Handler +OSCCTRL_3_Handler +OSCCTRL_4_Handler +OSC32KCTRL_Handler +SUPC_0_Handler +SUPC_1_Handler +WDT_Handler +RTC_Handler +EIC_0_Handler +EIC_1_Handler +EIC_2_Handler +EIC_3_Handler +EIC_4_Handler +EIC_5_Handler +EIC_6_Handler +EIC_7_Handler +EIC_8_Handler +EIC_9_Handler +EIC_10_Handler +EIC_11_Handler +EIC_12_Handler +EIC_13_Handler +EIC_14_Handler +EIC_15_Handler +FREQM_Handler +NVMCTRL_0_Handler +NVMCTRL_1_Handler +DMAC_0_Handler +DMAC_1_Handler +DMAC_2_Handler +DMAC_3_Handler +DMAC_4_Handler +EVSYS_0_Handler +EVSYS_1_Handler +EVSYS_2_Handler +EVSYS_3_Handler +EVSYS_4_Handler +PAC_Handler +TAL_0_Handler +TAL_1_Handler +RAMECC_Handler +SERCOM0_0_Handler +SERCOM0_1_Handler +SERCOM0_2_Handler +SERCOM0_3_Handler +SERCOM1_0_Handler +SERCOM1_1_Handler +SERCOM1_2_Handler +SERCOM1_3_Handler +SERCOM2_0_Handler +SERCOM2_1_Handler +SERCOM2_2_Handler +SERCOM2_3_Handler +SERCOM3_0_Handler +SERCOM3_1_Handler +SERCOM3_2_Handler +SERCOM3_3_Handler +SERCOM4_0_Handler +SERCOM4_1_Handler +SERCOM4_2_Handler +SERCOM4_3_Handler +SERCOM5_0_Handler +SERCOM5_1_Handler +SERCOM5_2_Handler +SERCOM5_3_Handler +SERCOM6_0_Handler +SERCOM6_1_Handler +SERCOM6_2_Handler +SERCOM6_3_Handler +SERCOM7_0_Handler +SERCOM7_1_Handler +SERCOM7_2_Handler +SERCOM7_3_Handler +CAN0_Handler +CAN1_Handler +USB_0_Handler +USB_1_Handler +USB_2_Handler +USB_3_Handler +GMAC_Handler +TCC0_0_Handler +TCC0_1_Handler +TCC0_2_Handler +TCC0_3_Handler +TCC0_4_Handler +TCC0_5_Handler +TCC0_6_Handler +TCC1_0_Handler +TCC1_1_Handler +TCC1_2_Handler +TCC1_3_Handler +TCC1_4_Handler +TCC2_0_Handler +TCC2_1_Handler +TCC2_2_Handler +TCC2_3_Handler +TCC3_0_Handler +TCC3_1_Handler +TCC3_2_Handler +TCC4_0_Handler +TCC4_1_Handler +TCC4_2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +PDEC_0_Handler +PDEC_1_Handler +PDEC_2_Handler +ADC0_0_Handler +ADC0_1_Handler +ADC1_0_Handler +ADC1_1_Handler +AC_Handler +DAC_0_Handler +DAC_1_Handler +DAC_2_Handler +DAC_3_Handler +DAC_4_Handler +I2S_Handler +PCC_Handler +AES_Handler +TRNG_Handler +ICM_Handler +PUKCC_Handler +QSPI_Handler +SDHC0_Handler +SDHC1_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/system_same54.c b/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/system_same54.c new file mode 100644 index 0000000000..95d303607e --- /dev/null +++ b/bsp/microchip/same54/bsp/armcc/arm_addon/armcc/system_same54.c @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/same54/bsp/atmel_start.c b/bsp/microchip/same54/bsp/atmel_start.c new file mode 100644 index 0000000000..79f252aed9 --- /dev/null +++ b/bsp/microchip/same54/bsp/atmel_start.c @@ -0,0 +1,9 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/bsp/microchip/same54/bsp/atmel_start.h b/bsp/microchip/same54/bsp/atmel_start.h new file mode 100644 index 0000000000..0de62f528d --- /dev/null +++ b/bsp/microchip/same54/bsp/atmel_start.h @@ -0,0 +1,18 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/microchip/same54/bsp/atmel_start_config.atstart b/bsp/microchip/same54/bsp/atmel_start_config.atstart new file mode 100644 index 0000000000..00521a1385 --- /dev/null +++ b/bsp/microchip/same54/bsp/atmel_start_config.atstart @@ -0,0 +1,1102 @@ +format_version: '2' +name: SAME54 LED switcher +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: SAME54XplainedPro + device: SAME54P20A-AU +details: null +application: + definition: 'Atmel:Application_Examples:0.0.1::Application:AES_Demo:' + configuration: null +middlewares: {} +drivers: + CRYPTOGRAPHY_0: + user_label: CRYPTOGRAPHY_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::AES::driver_config_definition::AES::HAL:Driver:AES.Sync + functionality: Cryptography + api: HAL:Driver:AES_Sync + configuration: + aes_dbgctrl: false + optional_signals: [] + variant: null + clocks: + domain_group: null + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: true + cmcc_clock_gating_disable: true + cmcc_data_cache_disable: true + cmcc_enable: true + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 120000000 + $input_id: Digital Phase Locked Loop (DPLL0) + RESERVED_InputFreq: 120000000 + RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL0) + _$freq_output_Generic clock generator 0: 120000000 + _$freq_output_Generic clock generator 1: 3000000 + _$freq_output_Generic clock generator 10: 12000000 + _$freq_output_Generic clock generator 11: 12000000 + _$freq_output_Generic clock generator 2: 3000000 + _$freq_output_Generic clock generator 3: 40000000 + _$freq_output_Generic clock generator 4: 12000000 + _$freq_output_Generic clock generator 5: 12000000 + _$freq_output_Generic clock generator 6: 12000000 + _$freq_output_Generic clock generator 7: 12000000 + _$freq_output_Generic clock generator 8: 12000000 + _$freq_output_Generic clock generator 9: 12000000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: true + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: true + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: true + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: true + gclk_arch_gen_1_idc: true + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: true + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: true + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 4 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_2_div: 4 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 3 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 120000000 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 120000000 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 120000000 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 8 + nvm_wait_states: '5' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: false + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 125092us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 40000000 + $input_id: Generic clock generator 3 + RESERVED_InputFreq: 40000000 + RESERVED_InputFreq_id: Generic clock generator 3 + _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 + _$freq_output_Digital Phase Locked Loop (DPLL0): 120000000 + _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000 + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: true + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: true + fdpll0_arch_dcoen: false + fdpll0_arch_enable: true + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: false + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: GCLK clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 39 + fdpll0_ldrfrac: 0 + fdpll0_ref_clock: Generic clock generator 2 + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: true + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 7813us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + portd_event_action_0: Output register of pin will be set to level of event + portd_event_action_1: Output register of pin will be set to level of event + portd_event_action_2: Output register of pin will be set to level of event + portd_event_action_3: Output register of pin will be set to level of event + portd_event_pin_identifier_0: 0 + portd_event_pin_identifier_1: 0 + portd_event_pin_identifier_2: 0 + portd_event_pin_identifier_3: 0 + portd_input_event_enable_0: false + portd_input_event_enable_1: false + portd_input_event_enable_2: false + portd_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 115200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM2/PAD/0 + pad: PB25 + label: TX + - name: SERCOM2/PAD/1 + pad: PB24 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 1 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 1 + CAN_0: + user_label: CAN_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CAN1::driver_config_definition::CAN::HAL:Driver:CAN.Async + functionality: CAN + api: HAL:Driver:CAN_Async + configuration: + can_btp_brp: 4 + can_btp_sjw: 10 + can_btp_tseg1: 31 + can_btp_tseg2: 8 + can_cccr_brse: false + can_cccr_fdoe: false + can_dbtp_dbrp: 4 + can_dbtp_dsjw: 4 + can_dbtp_dtseg1: 31 + can_dbtp_dtseg2: 8 + can_dbtp_tdc: false + can_gfc_anfe: Reject + can_gfc_anfs: Reject + can_gfc_rrfe: Filter remote frames with 29-bit standard IDs + can_gfc_rrfs: Filter remote frames with 11-bit standard IDs + can_ie_bo: true + can_ie_do: true + can_ie_ea: true + can_ie_ep: true + can_ie_ew: true + can_mrcfg_dqos: Sensitive latency + can_mrcfg_runstandby: false + can_rxesc_f0ds: 8 byte data field. + can_rxf0c_f0om: blocking mode + can_rxf0c_f0s: 32 + can_rxf0c_f0wm: 0 + can_sidfc_lss: 128 + can_txbc_tfqs: 32 + can_txefc_efs: 32 + can_txefc_efwm: 0 + can_txesc_tbds: 8 byte data field. + can_xidam_eidm: 0 + can_xidfc_lss: 64 + optional_signals: + - identifier: CAN_0:RX + pad: PB13 + mode: Enabled + configuration: null + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::CAN1.RX + name: CAN1/RX + label: RX + - identifier: CAN_0:TX + pad: PB12 + mode: Enabled + configuration: null + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::CAN1.TX + name: CAN1/TX + label: TX + variant: null + clocks: + domain_group: + nodes: + - name: CAN + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + can_gclk_selection: Generic clock generator 3 +pads: + PB12: + name: PB12 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB12 + mode: Peripheral IO + user_label: PB12 + configuration: null + PB13: + name: PB13 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB13 + mode: Peripheral IO + user_label: PB13 + configuration: null + LED0: + name: PC18 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC18 + mode: Digital output + user_label: LED0 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 + configuration: null +toolchain_options: [] +static_files: [] diff --git a/bsp/microchip/same54/bsp/atmel_start_pins.h b/bsp/microchip/same54/bsp/atmel_start_pins.h new file mode 100644 index 0000000000..170b507e0c --- /dev/null +++ b/bsp/microchip/same54/bsp/atmel_start_pins.h @@ -0,0 +1,36 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAME54 has 14 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 +#define GPIO_PIN_FUNCTION_J 9 +#define GPIO_PIN_FUNCTION_K 10 +#define GPIO_PIN_FUNCTION_L 11 +#define GPIO_PIN_FUNCTION_M 12 +#define GPIO_PIN_FUNCTION_N 13 + +#define PB12 GPIO(GPIO_PORTB, 12) +#define PB13 GPIO(GPIO_PORTB, 13) +#define PB24 GPIO(GPIO_PORTB, 24) +#define PB25 GPIO(GPIO_PORTB, 25) +#define LED0 GPIO(GPIO_PORTC, 18) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/bsp/microchip/same54/bsp/config/hpl_aes_config.h b/bsp/microchip/same54/bsp/config/hpl_aes_config.h new file mode 100644 index 0000000000..4aeb9246e0 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_aes_config.h @@ -0,0 +1,20 @@ +/* Auto-generated config file hpl_aes_config.h */ +#ifndef HPL_AES_CONFIG_H +#define HPL_AES_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced configurations + +// Run In Debug +// Indicates whether the AES to continue normal operation during debug mode +// aes_dbgctrl +#ifndef CONF_AES_DBGCTRL +#define CONF_AES_DBGCTRL 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_AES_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_can_config.h b/bsp/microchip/same54/bsp/config/hpl_can_config.h new file mode 100644 index 0000000000..922468fcd8 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_can_config.h @@ -0,0 +1,391 @@ +/* Auto-generated config file hpl_can_config.h */ +#ifndef HPL_CAN_CONFIG_H +#define HPL_CAN_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_CAN1_ENABLED +#define CONF_CAN1_ENABLED 1 +#endif +// Basic Configuration + +// FD Operation Enable +// Enable CAN FD operation +// can_cccr_fdoe +#ifndef CONF_CAN1_CCCR_FDOE +#define CONF_CAN1_CCCR_FDOE 0 +#endif + +// Bit Rate Switch Enable +// Bit Rate Switch Enable +// can_cccr_brse +#ifndef CONF_CAN1_CCCR_BRSE +#define CONF_CAN1_CCCR_BRSE 0 +#endif + +// Run In Standby is invalid for C21/E5x/D5x devices +// Run In Standby +// Indicates whether to not disable CAN during standby sleep mode +// can_mrcfg_runstandby +#ifndef CONF_CAN1_MRCFG_RUNSTANDBY +#define CONF_CAN1_MRCFG_RUNSTANDBY 0 +#endif +// + +// Data Quality of Service +// Select he memory priority access during the Message RAM read/write data operation. +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// can_mrcfg_dqos +#ifndef CONF_CAN1_MRCFG_DQOS +#define CONF_CAN1_MRCFG_DQOS 2 +#endif + +// + +// Normal Bit Timing and Prescaler Configuration + +// Baud Rate Prescaler <1-512> +// Baud Rate Prescale +// can_btp_brp +#ifndef CONF_CAN1_BTP_BRP +#define CONF_CAN1_BTP_BRP 4 +#endif + +// time segment before sample point <2-256> +// time segment before sample point +// can_btp_tseg1 +#ifndef CONF_CAN1_BTP_TSEG1 +#define CONF_CAN1_BTP_TSEG1 31 +#endif + +// time segment after sample point <1-128> +// time segment after sample point +// can_btp_tseg2 +#ifndef CONF_CAN1_BTP_TSEG2 +#define CONF_CAN1_BTP_TSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-128> +// (Re)Syncronization Jump Width +// can_btp_sjw +#ifndef CONF_CAN1_BTP_SJW +#define CONF_CAN1_BTP_SJW 10 +#endif + +// + +// Data Bit Timing and Prescaler Configuration + +// Transceiver Delay Compensation Enable +// Transceiver Delay Compensation Enable +// can_dbtp_tdc +#ifndef CONF_CAN1_DBTP_TDC +#define CONF_CAN1_DBTP_TDC 0 +#endif + +// Data Baud Rate Prescaler <1-32> +// Data Baud Rate Prescaler +// can_dbtp_dbrp +#ifndef CONF_CAN1_DBTP_DBRP +#define CONF_CAN1_DBTP_DBRP 4 +#endif + +// Fast time segment before sample point <1-32> +// Fast time segment before sample point +// can_dbtp_dtseg1 +#ifndef CONF_CAN1_DBTP_DTSEG1 +#define CONF_CAN1_DBTP_DTSEG1 31 +#endif + +// Data time segment after sample point <1-16> +// Fast time segment after sample point +// can_dbtp_dtseg2 +#ifndef CONF_CAN1_DBTP_DTSEG2 +#define CONF_CAN1_DBTP_DTSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-16> +// Fast Syncronization Jump Width +// can_dbtp_dsjw +#ifndef CONF_CAN1_DBTP_DSJW +#define CONF_CAN1_DBTP_DSJW 4 +#endif + +// + +// RX FIFO Configuration + +// Operation Mode +// Select Operation Mode +// <0=> blocking mode +// <1=> overwrite mode +// can_rxf0c_f0om +#ifndef CONF_CAN1_RXF0C_F0OM +#define CONF_CAN1_RXF0C_F0OM 0 +#endif + +// Watermark <0-64> +// Watermark, 0 for disable watermark interrupt +// can_rxf0c_f0wm +#ifndef CONF_CAN1_RXF0C_F0WM +#define CONF_CAN1_RXF0C_F0WM 0 +#endif + +// Size <0-64> +// Number of Rx FIFO 0 element +// can_rxf0c_f0s +#ifndef CONF_CAN1_RXF0C_F0S +#define CONF_CAN1_RXF0C_F0S 32 +#endif + +// Data Field Size +// Rx FIFO 0 Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_rxesc_f0ds +#ifndef CONF_CAN1_RXESC_F0DS +#define CONF_CAN1_RXESC_F0DS 0 +#endif + +/* Bytes size for CAN FIFO 0 element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN1_F0DS +#define CONF_CAN1_F0DS \ + ((CONF_CAN1_RXESC_F0DS < 5) ? ((CONF_CAN1_RXESC_F0DS << 2) + 16) : (40 + ((CONF_CAN1_RXESC_F0DS % 5) << 4))) + +// + +// TX FIFO Configuration + +// Transmit FIFO Size <0-32> +// Number of Tx Buffers used for Tx FIFO +// can_txbc_tfqs +#ifndef CONF_CAN1_TXBC_TFQS +#define CONF_CAN1_TXBC_TFQS 32 +#endif + +// Tx Buffer Data Field Size +// Tx Buffer Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_txesc_tbds +#ifndef CONF_CAN1_TXESC_TBDS +#define CONF_CAN1_TXESC_TBDS 0 +#endif + +/* Bytes size for CAN Transmit Buffer element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN1_TBDS +#define CONF_CAN1_TBDS \ + ((CONF_CAN1_TXESC_TBDS < 5) ? ((CONF_CAN1_TXESC_TBDS << 2) + 16) : (40 + ((CONF_CAN1_TXESC_TBDS % 5) << 4))) + +// + +// TX Event Configuration + +// Watermark <0-32> +// Watermark, 0 for disable watermark interrupt +// can_txefc_efwm +#ifndef CONF_CAN1_TXEFC_EFWM +#define CONF_CAN1_TXEFC_EFWM 0 +#endif + +// Size <0-32> +// Number of Event FIFO element +// can_txefc_efs +#ifndef CONF_CAN1_TXEFC_EFS +#define CONF_CAN1_TXEFC_EFS 32 +#endif + +// + +// Filter Configuration + +// Accept Non-matching Frames Standard +// Defines how received messages with 11-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfs +#ifndef CONF_CAN1_GFC_ANFS +#define CONF_CAN1_GFC_ANFS 2 +#endif + +// Accept Non-matching Frames Extended +// Defines how received messages with 29-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfe +#ifndef CONF_CAN1_GFC_ANFE +#define CONF_CAN1_GFC_ANFE 2 +#endif + +// Reject Remote Frames Standard +// Defines how received remote frames with 11-bit standard IDs. +// <0=> Filter remote frames with 11-bit standard IDs +// <1=> Reject all remote frames with 11-bit standard IDs +// can_gfc_rrfs +#ifndef CONF_CAN1_GFC_RRFS +#define CONF_CAN1_GFC_RRFS 0 +#endif + +// Reject Remote Frames Extended +// Defines how received remote frames with 29-bit standard IDs. +// <0=> Filter remote frames with 29-bit standard IDs +// <1=> Reject all remote frames with 29-bit standard IDs +// can_gfc_rrfe +#ifndef CONF_CAN1_GFC_RRFE +#define CONF_CAN1_GFC_RRFE 0 +#endif + +// Number of standard Message ID filter elements <0-128> +// Number of standard Message ID filter elements +// can_sidfc_lss +#ifndef CONF_CAN1_SIDFC_LSS +#define CONF_CAN1_SIDFC_LSS 128 +#endif + +// Number of Extended Message ID filter elements <0-128> +// Number of Extended Message ID filter elements +// can_xidfc_lss +#ifndef CONF_CAN1_XIDFC_LSS +#define CONF_CAN1_XIDFC_LSS 64 +#endif + +// Extended ID Mask <0x0000-0x1FFFFFFF> +// For acceptance filtering of extended frames the Extended ID AND Mask is +// ANDed with the Message ID of a received frame. Intended for masking of +// 29-bit IDs in SAE J1939. With the reset value of all bits set to one the +// mask is not active. +// can_xidam_eidm +#ifndef CONF_CAN1_XIDAM_EIDM +#define CONF_CAN1_XIDAM_EIDM 0x0 +#endif + +// + +// Interrupt Configuration + +// Error Warning +// Indicates whether to not disable CAN error warning interrupt +// can_ie_ew +#ifndef CONF_CAN1_IE_EW +#define CONF_CAN1_IE_EW 1 +#endif + +// Error Active +// Indicates whether to not disable CAN error active interrupt +// can_ie_ea +#ifndef CONF_CAN1_IE_EA +#define CONF_CAN1_IE_EA 1 +#endif + +// Error Passive +// Indicates whether to not disable CAN error passive interrupt +// can_ie_ep +#ifndef CONF_CAN1_IE_EP +#define CONF_CAN1_IE_EP 1 +#endif + +// Bus Off +// Indicates whether to not disable CAN bus off interrupt +// can_ie_bo +#ifndef CONF_CAN1_IE_BO +#define CONF_CAN1_IE_BO 1 +#endif + +// Data Overrun +// Indicates whether to not disable CAN data overrun interrupt +// can_ie_do +#ifndef CONF_CAN1_IE_DO +#define CONF_CAN1_IE_DO 1 +#endif + +// + +#ifndef CONF_CAN1_CCCR_REG +#define CONF_CAN1_CCCR_REG (CONF_CAN1_CCCR_FDOE << CAN_CCCR_FDOE_Pos) | (CONF_CAN1_CCCR_BRSE << CAN_CCCR_BRSE_Pos) +#endif + +#ifndef CONF_CAN1_MRCFG_REG +#define CONF_CAN1_MRCFG_REG CAN_MRCFG_QOS(CONF_CAN1_MRCFG_DQOS) +#endif + +#ifndef CONF_CAN1_BTP_REG +#define CONF_CAN1_BTP_REG \ + CAN_NBTP_NBRP(CONF_CAN1_BTP_BRP - 1) | CAN_NBTP_NTSEG1(CONF_CAN1_BTP_TSEG1 - 1) \ + | CAN_NBTP_NTSEG2(CONF_CAN1_BTP_TSEG2 - 1) | CAN_NBTP_NSJW(CONF_CAN1_BTP_SJW - 1) +#endif + +#ifndef CONF_CAN1_DBTP_REG +#define CONF_CAN1_DBTP_REG \ + (CONF_CAN1_DBTP_TDC << CAN_DBTP_TDC_Pos) | CAN_DBTP_DBRP(CONF_CAN1_DBTP_DBRP - 1) \ + | CAN_DBTP_DTSEG1(CONF_CAN1_DBTP_DTSEG1 - 1) | CAN_DBTP_DTSEG2(CONF_CAN1_DBTP_DTSEG2 - 1) \ + | CAN_DBTP_DSJW(CONF_CAN1_DBTP_DSJW - 1) +#endif + +#ifndef CONF_CAN1_RXF0C_REG +#define CONF_CAN1_RXF0C_REG \ + (CONF_CAN1_RXF0C_F0OM << CAN_RXF0C_F0OM_Pos) | CAN_RXF0C_F0WM(CONF_CAN1_RXF0C_F0WM) \ + | CAN_RXF0C_F0S(CONF_CAN1_RXF0C_F0S) +#endif + +#ifndef CONF_CAN1_RXESC_REG +#define CONF_CAN1_RXESC_REG CAN_RXESC_F0DS(CONF_CAN1_RXESC_F0DS) +#endif + +#ifndef CONF_CAN1_TXESC_REG +#define CONF_CAN1_TXESC_REG CAN_TXESC_TBDS(CONF_CAN1_TXESC_TBDS) +#endif + +#ifndef CONF_CAN1_TXBC_REG +#define CONF_CAN1_TXBC_REG CAN_TXBC_TFQS(CONF_CAN1_TXBC_TFQS) +#endif + +#ifndef CONF_CAN1_TXEFC_REG +#define CONF_CAN1_TXEFC_REG CAN_TXEFC_EFWM(CONF_CAN1_TXEFC_EFWM) | CAN_TXEFC_EFS(CONF_CAN1_TXEFC_EFS) +#endif + +#ifndef CONF_CAN1_GFC_REG +#define CONF_CAN1_GFC_REG \ + CAN_GFC_ANFS(CONF_CAN1_GFC_ANFS) | CAN_GFC_ANFE(CONF_CAN1_GFC_ANFE) | (CONF_CAN1_GFC_RRFS << CAN_GFC_RRFS_Pos) \ + | (CONF_CAN1_GFC_RRFE << CAN_GFC_RRFE_Pos) +#endif + +#ifndef CONF_CAN1_SIDFC_REG +#define CONF_CAN1_SIDFC_REG CAN_SIDFC_LSS(CONF_CAN1_SIDFC_LSS) +#endif + +#ifndef CONF_CAN1_XIDFC_REG +#define CONF_CAN1_XIDFC_REG CAN_XIDFC_LSE(CONF_CAN1_XIDFC_LSS) +#endif + +#ifndef CONF_CAN1_XIDAM_REG +#define CONF_CAN1_XIDAM_REG CAN_XIDAM_EIDM(CONF_CAN1_XIDAM_EIDM) +#endif + +#ifndef CONF_CAN0_IE_REG +#define CONF_CAN0_IE_REG \ + (CONF_CAN1_IE_EW << CAN_IR_EW_Pos) | (CONF_CAN1_IE_EA << CAN_IR_EP_Pos) | (CONF_CAN1_IE_EP << CAN_IR_EP_Pos) \ + | (CONF_CAN1_IE_BO << CAN_IR_BO_Pos) | (CONF_CAN1_IE_DO << CAN_IR_RF0L_Pos) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_CAN_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_cmcc_config.h b/bsp/microchip/same54/bsp/config/hpl_cmcc_config.h new file mode 100644 index 0000000000..d1699befd9 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_cmcc_config.h @@ -0,0 +1,54 @@ +/* Auto-generated config file hpl_cmcc_config.h */ +#ifndef HPL_CMCC_CONFIG_H +#define HPL_CMCC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration + +// Cache enable +// Defines the cache should be enabled or not. +// cmcc_enable +#ifndef CONF_CMCC_ENABLE +#define CONF_CMCC_ENABLE 0x1 +#endif + +// Cache Size +// Defines the cache memory size to be configured. +// <0x0=>1 KB +// <0x1=>2 KB +// <0x2=>4 KB +// cache_size +#ifndef CONF_CMCC_CACHE_SIZE +#define CONF_CMCC_CACHE_SIZE 0x2 +#endif + +// Advanced Configuration +// cmcc_advanced_configuration +// Data cache disable +// Defines the data cache should be disabled or not. +// cmcc_data_cache_disable +#ifndef CONF_CMCC_DATA_CACHE_DISABLE +#define CONF_CMCC_DATA_CACHE_DISABLE 0x1 +#endif + +// Instruction cache disable +// Defines the Instruction cache should be disabled or not. +// cmcc_inst_cache_disable +#ifndef CONF_CMCC_INST_CACHE_DISABLE +#define CONF_CMCC_INST_CACHE_DISABLE 0x0 +#endif + +// Clock Gating disable +// Defines the clock gating should be disabled or not. +// cmcc_clock_gating_disable +#ifndef CONF_CMCC_CLK_GATING_DISABLE +#define CONF_CMCC_CLK_GATING_DISABLE 0x1 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_CMCC_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_dmac_config.h b/bsp/microchip/same54/bsp/config/hpl_dmac_config.h new file mode 100644 index 0000000000..90499fc27f --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_gclk_config.h b/bsp/microchip/same54/bsp/config/hpl_gclk_config.h new file mode 100644 index 0000000000..c6e9db4173 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_gclk_config.h @@ -0,0 +1,920 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 1 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 4 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 4 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 3 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_mclk_config.h b/bsp/microchip/same54/bsp/config/hpl_mclk_config.h new file mode 100644 index 0000000000..bd9f652919 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV8_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 5 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_osc32kctrl_config.h b/bsp/microchip/same54/bsp/config/hpl_osc32kctrl_config.h new file mode 100644 index 0000000000..114d5c1982 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_osc32kctrl_config.h @@ -0,0 +1,165 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_oscctrl_config.h b/bsp/microchip/same54/bsp/config/hpl_oscctrl_config.h new file mode 100644 index 0000000000..9f4c1fd2d5 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_oscctrl_config.h @@ -0,0 +1,640 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 1 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 8 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 1 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK2_Val +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x0 +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 0x27 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_port_config.h b/bsp/microchip/same54/bsp/config/hpl_port_config.h new file mode 100644 index 0000000000..b5315f0854 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_port_config.h @@ -0,0 +1,522 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT C + +// PORTC Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled +// portc_input_event_enable_0 +#ifndef CONF_PORTC_EVCTRL_PORTEI_0 +#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTC Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_0 +#ifndef CONF_PORTC_EVCTRL_PID_0 +#define CONF_PORTC_EVCTRL_PID_0 0x0 +#endif + +// PORTC Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 0 +// portc_event_action_0 +#ifndef CONF_PORTC_EVCTRL_EVACT_0 +#define CONF_PORTC_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT D + +// PORTD Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled +// portd_input_event_enable_0 +#ifndef CONF_PORTD_EVCTRL_PORTEI_0 +#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTD Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_0 +#ifndef CONF_PORTD_EVCTRL_PID_0 +#define CONF_PORTD_EVCTRL_PID_0 0x0 +#endif + +// PORTD Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 0 +// portd_event_action_0 +#ifndef CONF_PORTD_EVCTRL_EVACT_0 +#define CONF_PORTD_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT C + +// PORTC Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled +// portc_input_event_enable_1 +#ifndef CONF_PORTC_EVCTRL_PORTEI_1 +#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTC Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_1 +#ifndef CONF_PORTC_EVCTRL_PID_1 +#define CONF_PORTC_EVCTRL_PID_1 0x0 +#endif + +// PORTC Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 1 +// portc_event_action_1 +#ifndef CONF_PORTC_EVCTRL_EVACT_1 +#define CONF_PORTC_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT D + +// PORTD Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled +// portd_input_event_enable_1 +#ifndef CONF_PORTD_EVCTRL_PORTEI_1 +#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTD Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_1 +#ifndef CONF_PORTD_EVCTRL_PID_1 +#define CONF_PORTD_EVCTRL_PID_1 0x0 +#endif + +// PORTD Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 1 +// portd_event_action_1 +#ifndef CONF_PORTD_EVCTRL_EVACT_1 +#define CONF_PORTD_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT C + +// PORTC Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled +// portc_input_event_enable_2 +#ifndef CONF_PORTC_EVCTRL_PORTEI_2 +#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTC Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_2 +#ifndef CONF_PORTC_EVCTRL_PID_2 +#define CONF_PORTC_EVCTRL_PID_2 0x0 +#endif + +// PORTC Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 2 +// portc_event_action_2 +#ifndef CONF_PORTC_EVCTRL_EVACT_2 +#define CONF_PORTC_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT D + +// PORTD Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled +// portd_input_event_enable_2 +#ifndef CONF_PORTD_EVCTRL_PORTEI_2 +#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTD Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_2 +#ifndef CONF_PORTD_EVCTRL_PID_2 +#define CONF_PORTD_EVCTRL_PID_2 0x0 +#endif + +// PORTD Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 2 +// portd_event_action_2 +#ifndef CONF_PORTD_EVCTRL_EVACT_2 +#define CONF_PORTD_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT C + +// PORTC Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled +// portc_input_event_enable_3 +#ifndef CONF_PORTC_EVCTRL_PORTEI_3 +#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTC Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_3 +#ifndef CONF_PORTC_EVCTRL_PID_3 +#define CONF_PORTC_EVCTRL_PID_3 0x0 +#endif + +// PORTC Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 3 +// portc_event_action_3 +#ifndef CONF_PORTC_EVCTRL_EVACT_3 +#define CONF_PORTC_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT D + +// PORTD Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled +// portd_input_event_enable_3 +#ifndef CONF_PORTD_EVCTRL_PORTEI_3 +#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTD Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_3 +#ifndef CONF_PORTD_EVCTRL_PID_3 +#define CONF_PORTD_EVCTRL_PID_3 0x0 +#endif + +// PORTD Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 3 +// portd_event_action_3 +#ifndef CONF_PORTD_EVCTRL_EVACT_3 +#define CONF_PORTD_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) +#define CONF_PORTC_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) +#define CONF_PORTD_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ + | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ + | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/hpl_sercom_config.h b/bsp/microchip/same54/bsp/config/hpl_sercom_config.h new file mode 100644 index 0000000000..c5ccfe82d1 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/hpl_sercom_config.h @@ -0,0 +1,278 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-6250000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 115200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 4 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/bsp/microchip/same54/bsp/config/peripheral_clk_config.h b/bsp/microchip/same54/bsp/config/peripheral_clk_config.h new file mode 100644 index 0000000000..46f79b4eb0 --- /dev/null +++ b/bsp/microchip/same54/bsp/config/peripheral_clk_config.h @@ -0,0 +1,137 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 120000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 120000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 3000000 +#endif + +// CAN1 Clock Source +// can_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CAN1. +#ifndef CONF_GCLK_CAN1_SRC +#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_CAN1_FREQUENCY + * \brief CAN1's Clock frequency + */ +#ifndef CONF_GCLK_CAN1_FREQUENCY +#define CONF_GCLK_CAN1_FREQUENCY 40000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/bsp/microchip/same54/bsp/documentation/aes_demo.rst b/bsp/microchip/same54/bsp/documentation/aes_demo.rst new file mode 100644 index 0000000000..bbbb1c36c2 --- /dev/null +++ b/bsp/microchip/same54/bsp/documentation/aes_demo.rst @@ -0,0 +1,29 @@ +======== +AES Demo +======== + +The example demonstrates how to use different AES modes. + +For each mode the example does crypt and decrypt tests. +It crypt predefined plain text and check if the encode output cipher matches +expectation. +It decrypt predefined cipher data and check if the decode output matches +the plain text. + +All of the test information and testing results are put to debug console so that +the result can be reviewed. + +Drivers & middleware +-------------------- +* AES +* STDIO +* Synchronous USART + +Default interface settings +-------------------------- +* USART + + * No parity + * 8-bit character size + * 1 stop bit + * 9600 baud-rate diff --git a/bsp/microchip/same54/bsp/driver_init.c b/bsp/microchip/same54/bsp/driver_init.c new file mode 100644 index 0000000000..b44c15af7a --- /dev/null +++ b/bsp/microchip/same54/bsp/driver_init.c @@ -0,0 +1,95 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct aes_sync_descriptor CRYPTOGRAPHY_0; +struct can_async_descriptor CAN_0; + +struct usart_sync_descriptor TARGET_IO; + +/** + * \brief AES initialization function + * + * Enables AES peripheral, clocks and initializes AES driver + */ +void CRYPTOGRAPHY_0_init(void) +{ + hri_mclk_set_APBCMASK_AES_bit(MCLK); + aes_sync_init(&CRYPTOGRAPHY_0, AES); +} + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); + + gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); +} + +void TARGET_IO_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + usart_sync_init(&TARGET_IO, SERCOM2, (void *)NULL); + TARGET_IO_PORT_init(); +} + +void CAN_0_PORT_init(void) +{ + + gpio_set_pin_function(PB13, PINMUX_PB13H_CAN1_RX); + + gpio_set_pin_function(PB12, PINMUX_PB12H_CAN1_TX); +} +/** + * \brief CAN initialization function + * + * Enables CAN peripheral, clocks and initializes CAN driver + */ +void CAN_0_init(void) +{ + hri_mclk_set_AHBMASK_CAN1_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, CAN1_GCLK_ID, CONF_GCLK_CAN1_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + can_async_init(&CAN_0, CAN1); + CAN_0_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + // GPIO on PC18 + + gpio_set_pin_level(LED0, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(LED0, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF); + + CRYPTOGRAPHY_0_init(); + + TARGET_IO_init(); + CAN_0_init(); +} diff --git a/bsp/microchip/same54/bsp/driver_init.h b/bsp/microchip/same54/bsp/driver_init.h new file mode 100644 index 0000000000..c043185dc9 --- /dev/null +++ b/bsp/microchip/same54/bsp/driver_init.h @@ -0,0 +1,47 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +extern struct aes_sync_descriptor CRYPTOGRAPHY_0; + +extern struct usart_sync_descriptor TARGET_IO; +extern struct can_async_descriptor CAN_0; + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/bsp/microchip/same54/bsp/examples/driver_examples.c b/bsp/microchip/same54/bsp/examples/driver_examples.c new file mode 100644 index 0000000000..fef41e889e --- /dev/null +++ b/bsp/microchip/same54/bsp/examples/driver_examples.c @@ -0,0 +1,107 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +static uint8_t aes_plain_text[16] + = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a}; +static uint8_t aes_key[16] + = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; +static uint8_t aes_cipher_text[16] + = {0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97}; +uint8_t aes_output[16] = {0x00}; +/** + * Example of using CRYPTOGRAPHY_0 to Encrypt/Decrypt datas. + */ +void CRYPTOGRAPHY_0_example(void) +{ + int32_t i; + aes_sync_enable(&CRYPTOGRAPHY_0); + aes_sync_set_encrypt_key(&CRYPTOGRAPHY_0, aes_key, AES_KEY_128); + aes_sync_ecb_crypt(&CRYPTOGRAPHY_0, AES_ENCRYPT, aes_plain_text, aes_output); + for (i = 0; i < 16; i++) { + while (aes_output[i] != aes_cipher_text[i]) + ; + } +} + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void CAN_0_tx_callback(struct can_async_descriptor *const descr) +{ + (void)descr; +} +void CAN_0_rx_callback(struct can_async_descriptor *const descr) +{ + struct can_message msg; + uint8_t data[64]; + msg.data = data; + can_async_read(descr, &msg); + return; +} + +/** + * Example of using CAN_0 to Encrypt/Decrypt datas. + */ +void CAN_0_example(void) +{ + struct can_message msg; + struct can_filter filter; + uint8_t send_data[4]; + send_data[0] = 0x00; + send_data[1] = 0x01; + send_data[2] = 0x02; + send_data[3] = 0x03; + + msg.id = 0x45A; + msg.type = CAN_TYPE_DATA; + msg.data = send_data; + msg.len = 4; + msg.fmt = CAN_FMT_STDID; + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)CAN_0_tx_callback); + can_async_enable(&CAN_0); + + /** + * CAN_0_tx_callback callback should be invoked after call + * can_async_write, and remote device should recieve message with ID=0x45A + */ + can_async_write(&CAN_0, &msg); + + msg.id = 0x100000A5; + msg.fmt = CAN_FMT_EXTID; + /** + * remote device should recieve message with ID=0x100000A5 + */ + can_async_write(&CAN_0, &msg); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)CAN_0_rx_callback); + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 1, CAN_FMT_EXTID, &filter); +} diff --git a/bsp/microchip/same54/bsp/examples/driver_examples.h b/bsp/microchip/same54/bsp/examples/driver_examples.h new file mode 100644 index 0000000000..54c2aa1b5a --- /dev/null +++ b/bsp/microchip/same54/bsp/examples/driver_examples.h @@ -0,0 +1,24 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void CRYPTOGRAPHY_0_example(void); + +void TARGET_IO_example(void); + +void CAN_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_flash.ld b/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_flash.ld new file mode 100644 index 0000000000..fe3748b716 --- /dev/null +++ b/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_flash.ld @@ -0,0 +1,178 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + __bss_end = _end; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_sram.ld b/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_sram.ld new file mode 100644 index 0000000000..6219f4afef --- /dev/null +++ b/bsp/microchip/same54/bsp/gcc/gcc/same54p20a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/bsp/microchip/same54/bsp/gcc/gcc/startup_same54.c b/bsp/microchip/same54/bsp/gcc/gcc/startup_same54.c new file mode 100644 index 0000000000..8deab5e17b --- /dev/null +++ b/bsp/microchip/same54/bsp/gcc/gcc/startup_same54.c @@ -0,0 +1,548 @@ +/** + * \file + * + * \brief gcc starttup file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ +void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ +void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ +void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ +void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ +void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ +void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ +void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ +void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ +void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ +void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ +void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ +void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ +void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ +void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ +void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ +void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ +void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ +void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ +void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ +void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ +void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ +void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ +void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ +void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ +void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ +void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_USB +void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ +void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ +void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ +void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ +void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ +void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ +void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ +void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ +void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ +void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ +void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ +void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ +void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ +void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ +void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ +#ifdef ID_TCC3 +void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ +void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ +void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ +#endif +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC4 +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC5 +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC6 +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ +void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ +void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ +void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ +void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ +void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ +void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ +void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ +void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ +#ifdef ID_I2S +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ICM +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PUKCC +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SDHC0 +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDHC1 +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManagement_Handler = (void*) MemManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + .pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + .pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + .pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + .pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + .pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + .pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + .pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + .pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + .pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + .pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + .pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + .pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + .pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + .pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + .pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + .pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + .pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + .pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + .pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + .pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + .pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + .pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + .pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + .pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + .pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + .pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + .pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pvReserved63 = (void*) (0UL), /* 63 Reserved */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + .pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + .pvReserved66 = (void*) (0UL), /* 66 Reserved */ + .pvReserved67 = (void*) (0UL), /* 67 Reserved */ + .pvReserved68 = (void*) (0UL), /* 68 Reserved */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + .pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + .pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */ +#else + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */ +#else + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + .pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + .pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */ + .pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + .pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + .pvReserved80 = (void*) (0UL), /* 80 Reserved */ + .pvReserved81 = (void*) (0UL), /* 81 Reserved */ + .pvReserved82 = (void*) (0UL), /* 82 Reserved */ + .pvReserved83 = (void*) (0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ +#else + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ +#endif + .pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + .pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */ + .pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */ + .pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */ + .pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */ + .pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */ + .pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */ + .pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + .pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */ + .pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */ + .pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */ + .pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */ + .pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + .pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */ + .pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */ + .pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + .pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + .pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */ + .pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + .pvReserved101 = (void*) (0UL), /* 101 Reserved */ + .pvReserved102 = (void*) (0UL), /* 102 Reserved */ + .pvReserved103 = (void*) (0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + .pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + .pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */ + .pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + .pvReserved104 = (void*) (0UL), /* 104 Reserved */ + .pvReserved105 = (void*) (0UL), /* 105 Reserved */ + .pvReserved106 = (void*) (0UL), /* 106 Reserved */ +#endif + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + .pvReserved111 = (void*) (0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + .pvReserved112 = (void*) (0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ +#endif + .pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + .pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */ + .pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */ + .pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + .pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */ + .pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + .pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + .pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + .pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + .pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + .pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + .pvReserved128 = (void*) (0UL), /* 128 Reserved */ +#endif + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ +#else + .pvReserved132 = (void*) (0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + .pvReserved133 = (void*) (0UL), /* 133 Reserved */ +#endif + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + .pvReserved135 = (void*) (0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + .pvReserved136 = (void*) (0UL) /* 136 Reserved */ +#endif +}; + +int rtthread_startup(void); + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to rtthread_startup function */ + rtthread_startup(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/same54/bsp/gcc/system_same54.c b/bsp/microchip/same54/bsp/gcc/system_same54.c new file mode 100644 index 0000000000..468990e468 --- /dev/null +++ b/bsp/microchip/same54/bsp/gcc/system_same54.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/same54/bsp/hal/documentation/aes_sync.rst b/bsp/microchip/same54/bsp/hal/documentation/aes_sync.rst new file mode 100644 index 0000000000..3451aba135 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/documentation/aes_sync.rst @@ -0,0 +1,56 @@ +====================== +AES Synchronous driver +====================== + +The Advanced Encryption Standard (AES) is a specification for the encryption of +electronic data established by the U.S. National Institute of Standards and +Technology (NIST) in 2001. AES operates on a 128-bit block of input data. The +key size used for an AES cipher specifies the number of repetitions of +transformation rounds that convert the input, called the plaintext, into the +final output, called the ciphertext. The AES works on a symmetric-key +algorithm, meaning the same key is used for both encrypting and decrypting the +data. + +The driver supports ECB/CBC/CFB/OFB/CTR mode for data encryption, and GCM/CCM +for authenticated encryption. Before use any encrypt mode of AES, the key must +be set firstly. And for privacy situaion, after encrypt/decrypt data, the key +should be cleared by application. Common practice is set the key to zero. + +Features +-------- + +* Initialization and de-initialization +* Enabling and Disabling +* Set 128/192/256 bit cryptographic key +* Electronic Code Book (ECB) +* Cipher Block Chaining (CBC) +* Cipher Feedback (CFB) in 8,16,32,64,128 bits size +* Output Feedback (OFB) +* Counter (CTR) +* CCM (Counter with CBC-MAC) mode for authenticated encryption +* GCM (Galois Counter mode) encryption and authentication + +Applications +------------ +* Encrypt plain data to ciphered data, or decrypt ciphered data to plain text with + the same authentication key, the ciphered data cannot be recovered without + authentication key. + +Dependencies +------------ +* AES capable hardware + +Concurrency +----------- +N/A + +Limitations +----------- +* GCM only support known length data process, that mean the aes_sync_gcm_update + cannot be invoke multiple times, application should assembly all data into a + data buffer and then call once aes_sync_gcm_update to encrypt/decrypt data. + +Known issues and workarounds +---------------------------- +N/A + diff --git a/bsp/microchip/same54/bsp/hal/documentation/can_async.rst b/bsp/microchip/same54/bsp/hal/documentation/can_async.rst new file mode 100644 index 0000000000..7574b19ddb --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/documentation/can_async.rst @@ -0,0 +1,42 @@ +================================================= +CAN (Controller Area Network) Asynchronous Driver +================================================= + +The Controller Area Network (CAN) performs communication according to +ISO11898-1 (Bosch CAN specification 2.0 part A,B) + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* CAN message transfer: transmission, reception +* Callback on message transmited, recepted, error +* Callback on error warning, error active, error passive, bus off, data overrun +* Set CAN mode: normal, monitoring + +Applications +------------ + +Transmission and reception CAN meesage in a CAN Network. + +Dependencies +------------ + +CAN capable hardware compatible with the ISO11898-1 (Bosch CAN specification +2.0 part A,B) + +Concurrency +----------- + +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/same54/bsp/hal/documentation/usart_sync.rst b/bsp/microchip/same54/bsp/hal/documentation/usart_sync.rst new file mode 100644 index 0000000000..15e4b13885 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/same54/bsp/hal/include/hal_aes_sync.h b/bsp/microchip/same54/bsp/hal/include/hal_aes_sync.h new file mode 100644 index 0000000000..77e252571f --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_aes_sync.h @@ -0,0 +1,375 @@ +/** + * \file + * + * \brief AES Advanced Encryption Standard(Sync) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_AES_SYNC_H_INCLUDED +#define HAL_AES_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_crypto_aes_sync + * + * @{ + */ + +struct aes_sync_descriptor { + struct _aes_sync_device dev; /*!< AES HPL device descriptor */ +}; + +/** + * \brief Initialize AES Descriptor + * + * \param[in] desc The AES descriptor to be initialized + * \param[in] hw The pointer to hardware instance + */ +int32_t aes_sync_init(struct aes_sync_descriptor *descr, void *const hw); + +/** + * \brief Deinitialize AES Descriptor + * + * \param[in] desc The AES descriptor to be deinitialized + */ +int32_t aes_sync_deinit(struct aes_sync_descriptor *desc); + +/** + * \brief Enable AES + * + * \param[in] desc The AES descriptor + */ +int32_t aes_sync_enable(struct aes_sync_descriptor *desc); + +/** + * \brief Disable AES + * + * \param[in] desc The AES descriptor + */ +int32_t aes_sync_disable(struct aes_sync_descriptor *desc); + +/** + * \brief Set AES Key (encryption). + * + * \param[in] desc The AES descriptor + * \param[in] key Encryption key + * \param[in] size Bit length of key + */ +int32_t aes_sync_set_encrypt_key(struct aes_sync_descriptor *descr, const uint8_t *key, const enum aes_keysize size); + +/** + * \brief Set AES Key (decryption). + * + * \param[in] desc The AES descriptor + * \param[in] key Decryption key + * \param[in] size Bit length of key + */ +int32_t aes_sync_set_decrypt_key(struct aes_sync_descriptor *descr, const uint8_t *key, const enum aes_keysize size); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input 16-byte input data + * \param[out] output 16-byte output data + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_ecb_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output); + +/** + * \brief The AES-CBC block encryption/decryption + * length should be a multiple of 16 bytes + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input 16-byte input data + * \param[out] output 16-byte output data + * \param[in] length Byte length of the input data + * \param[in, out] iv Initialization vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cbc_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t iv[16]); + +/** + * \brief AES-CFB128 block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb128_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst); + +/** + * \brief AES-CFB64 block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb64_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst); + +/** + * \brief AES-CFB32 block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb32_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst); + +/** + * \brief AES-CFB16 block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb16_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst); + +/** + * \brief AES-CFB8 block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in, out] iv Initialization Vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb8_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-OFB block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + + * \return ERR_NONE if successful + */ +int32_t aes_sync_ofb_crypt(struct aes_sync_descriptor *descr, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv, uint32_t *iv_ofst); + +/** + * \brief AES-CTR block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] buffer Stream block for resuming + * \param[in] nc The 128-bit nonce and counter + * \param[in] nc_ofst The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer + * should be 0 at the start of a stream. + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_ctr_crypt(struct aes_sync_descriptor *descr, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t buffer[16], uint8_t nc[16], uint32_t *nc_ofst); + +/** + * \brief AES-GCM block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[out] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_gcm_crypt_and_tag(struct aes_sync_descriptor *const descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, uint8_t *tag, + uint32_t tag_len); +/** + * \brief AES-GCM block encryption + * + * \param[in] desc The AES descriptor + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[in] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_gcm_auth_decrypt(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, const uint8_t *tag, uint32_t tag_len); + +/** + * \brief AES-GCM block start + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of the IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_gcm_start(struct aes_sync_descriptor *const descr, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len); + +/** + * \brief AES-GCM block update + * + * \param[in] descr The AES descriptor + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_gcm_update(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length); + +/** + * \brief AES-GCM block finish + * + * \param[in] descr The AES descriptor + * \param[out] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_gcm_finish(struct aes_sync_descriptor *const descr, uint8_t *tag, uint32_t tag_len); + +/** + * \brief AES-CCM block encryption/decryption + * + * \param[in] descr The AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[in] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_ccm_crypt_and_tag(struct aes_sync_descriptor *const descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, uint8_t *tag, + uint32_t tag_len); + +/** + * \brief AES-CCM block authenticated decryption + * + * \param[in] descr The AES descriptor + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[in] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_ccm_auth_decrypt(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, const uint8_t *tag, uint32_t tag_len); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t aes_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_AES_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_atomic.h b/bsp/microchip/same54/bsp/hal/include/hal_atomic.h new file mode 100644 index 0000000000..82151fc5d5 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_cache.h b/bsp/microchip/same54/bsp/hal/include/hal_cache.h new file mode 100644 index 0000000000..071486b7c6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_cache.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HAL_CACHE_H_ +#define HAL_CACHE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_enable(const void *hw); + +/** + * \brief Disable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_disable(const void *hw); + +/** + * \brief Initialize cache module + * + * This function initialize cache module configuration. + * + * \return status of operation + */ +int32_t cache_init(void); + +/** + * \brief Configure cache module + * + * \param[in] pointer pointing to the starting address of cache module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache); + +/** + * \brief Invalidate entire cache entries + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_invalidate_all(const void *hw); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CACHE_H_ */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_can_async.h b/bsp/microchip/same54/bsp/hal/include/hal_can_async.h new file mode 100644 index 0000000000..4ed993eb8f --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_can_async.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_CAN_ASYNC_H_INCLUDED +#define HAL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \addtogroup doc_driver_hal_can_async + * + *@{ + */ + +/** + * \brief CAN Asynchronous descriptor + * + * The CAN descriptor forward declaration. + */ +struct can_async_descriptor; + +/** + * Callback for CAN interrupt + */ +typedef void (*can_cb_t)(struct can_async_descriptor *const descr); + +/** + * \brief CAN callbacks + */ +struct can_callbacks { + can_cb_t tx_done; + can_cb_t rx_done; + void (*irq_handler)(struct can_async_descriptor *const descr, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN descriptor + */ +struct can_async_descriptor { + struct _can_async_device dev; /*!< CAN HPL device descriptor */ + struct can_callbacks cb; /*!< CAN Interrupt Callbacks handler */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN descriptor. + * + * \param[in, out] descr A CAN descriptor to initialize. + * \param[in] hw The pointer to hardware instance. + * + * \return Initialization status. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given CAN descriptor. + * + * \param[in, out] descr The CAN descriptor to deinitialize. + * + * \return De-initialization status. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr); + +/** + * \brief Enable CAN + * + * This function enables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to enable. + * + * \return Enabling status. + */ +int32_t can_async_enable(struct can_async_descriptor *const descr); + +/** + * \brief Disable CAN + * + * This function disables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to disable. + * + * \return Disabling status. + */ +int32_t can_async_disable(struct can_async_descriptor *const descr); + +/** + * \brief Read a CAN message + * + * \param[in] descr The CAN descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] descr The CAN descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Register CAN callback function to interrupt + * + * \param[in] descr The CAN descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL will de-register any + * registered callback + * + * \return The status of callback assignment. + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb); + +/** + * \brief Return number of read errors + * + * This function returns the number of read errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of read errors. + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr); + +/** + * \brief Return number of write errors + * + * This function returns the number of write errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of write errors. + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr); + +/** + * \brief Set CAN to the specified mode + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] mode The CAN operation mode + * + * \return Status of the operation. + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode); + +/** + * \brief Set CAN Filter + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] index Index of Filter list + * \param[in] fmt CAN Indentify Type + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation. + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/** + * \brief Retrieve the current driver version + * + * \return The current driver version. + */ +uint32_t can_async_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_delay.h b/bsp/microchip/same54/bsp/hal/include/hal_delay.h new file mode 100644 index 0000000000..9d4aa5c1bc --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_gpio.h b/bsp/microchip/same54/bsp/hal/include/hal_gpio.h new file mode 100644 index 0000000000..fbfa2d4aec --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/same54/bsp/hal/include/hal_init.h b/bsp/microchip/same54/bsp/hal/include/hal_init.h new file mode 100644 index 0000000000..d7bc6fe209 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_io.h b/bsp/microchip/same54/bsp/hal/include/hal_io.h new file mode 100644 index 0000000000..f50401d7a6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_sleep.h b/bsp/microchip/same54/bsp/hal/include/hal_sleep.h new file mode 100644 index 0000000000..b90ef6a5b6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hal_usart_sync.h b/bsp/microchip/same54/bsp/hal/include/hal_usart_sync.h new file mode 100644 index 0000000000..1ef22fc63f --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_aes.h b/bsp/microchip/same54/bsp/hal/include/hpl_aes.h new file mode 100644 index 0000000000..a9981e294b --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_aes.h @@ -0,0 +1,43 @@ +/** + * \file + * + * \brief AES Advanced Encryption Standard(Sync) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_AES_H_INCLUDED +#define HPL_AES_H_INCLUDED + +#include + +enum aes_action { AES_DECRYPT, AES_ENCRYPT }; + +enum aes_keysize { AES_KEY_128, AES_KEY_192, AES_KEY_256 }; + +#endif /* HPL_AES_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_aes_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_aes_sync.h new file mode 100644 index 0000000000..e713ad55e7 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_aes_sync.h @@ -0,0 +1,318 @@ +/** + * \file + * + * \brief AES Advanced Encryption Standard(Sync) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_AES_SYNC_H_INCLUDED +#define HPL_AES_SYNC_H_INCLUDED +#include "hpl_aes.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +COMPILER_PACK_SET(4) +struct _aes_sync_device { + void * hw; /*!< Hardware module instance handler */ + uint8_t key[32]; /*!< Key value 128/192/256 bits */ + uint8_t iv[16]; /*!< Initialization Vector */ + uint32_t aad_len; /*!< length of additional data(GCM) */ + enum aes_keysize keysize; /*!< bit length of key */ +}; +COMPILER_PACK_RESET() + +/** + * \brief Initialize AES + * + * \param[in] dev The pointer to device instance + * \param[in] hw The pointer to hardware instance + */ +int32_t _aes_sync_init(struct _aes_sync_device *const dev, void *const hw); + +/** + * \brief Deinitialize AES + * + * \param[in] dev The pointer to device instance + */ +int32_t _aes_sync_deinit(struct _aes_sync_device *const dev); + +/** + * \brief Enable AES + * + * \param[in] dev The pointer to device instance + */ +int32_t _aes_sync_enable(struct _aes_sync_device *const dev); + +/** + * \brief Disable AES + * + * \param[in] dev The pointer to device instance + */ +int32_t _aes_sync_disable(struct _aes_sync_device *const dev); + +/** + * \brief Set AES Key (encryption/decryption) + * + * \param[in] dev The pointer to device instance + * \param[in] key Encryption/decryption key + * \param[in] size Bit length of key + */ +int32_t _aes_sync_set_key(struct _aes_sync_device *const dev, const uint8_t *key, const enum aes_keysize size); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input 16-byte input data + * \param[out] output 16-byte output data + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_ecb_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output); + +/** + * \brief AES-CBC block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input 16-byte input data + * \param[out] output 16-byte output data + * \param[in] length Byte length of the input data + * \param[in, out] iv Initialization vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cbc_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t iv[16]); + +/** + * \brief AES-CFB128 block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cfb128_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-CFB64 block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cfb64_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-CFB32 block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cfb32_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-CFB16 block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cfb16_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-CFB8 block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in, out] iv Initialization Vector (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_cfb8_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv); + +/** + * \brief AES-OFB block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[out] length Byte length of the input data + * \param[in, out] iv Initialization Vector (updated after use) + * \param[in, out] iv_ofst Offset in IV (updated after use) + + * \return ERR_NONE if successful + */ +int32_t _aes_sync_ofb_crypt(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv); + +/** + * \brief AES-CTR block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] nc The 128-bit nonce and counter + * \param[in] nc_ofst The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_ctr_crypt(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t nc[16]); + +/** + * \brief AES-GCM block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[out] tag Buffer holding the input data + * \param[out] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_gcm_crypt_and_tag(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, const uint8_t *iv, uint32_t iv_len, + const uint8_t *aad, uint32_t aad_len, uint8_t *tag, uint32_t tag_len); + +/** + * \brief AES-GCM block start + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of the IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_gcm_start(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len); + +/** + * \brief AES-GCM block update + * + * \param[in] dev The pointer to device instance + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_gcm_update(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length); + +/** + * \brief AES-GCM block finish + * + * \param[in] dev The pointer to device instance + * \param[out] tag Buffer holding the input data + * \param[out] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_gcm_finish(struct _aes_sync_device *const dev, uint8_t *tag, uint32_t tag_len); + +/** + * \brief AES-CCM block encryption/decryption + * + * \param[in] dev The pointer to device instance + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input Buffer holding the input data + * \param[out] output Buffer holding the output data + * \param[in] length Byte length of the input data + * \param[in] iv Initialization Vector + * \param[in] iv_len Length of IV + * \param[in] aad Additional data + * \param[in] aad_len Length of additional data + * \param[in] tag Buffer holding the input data + * \param[in] tag_len Length of tag + * + * \return ERR_NONE if successful + */ +int32_t _aes_sync_ccm_crypt_and_tag(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, const uint8_t *iv, uint32_t iv_len, + const uint8_t *aad, uint32_t aad_len, uint8_t *tag, uint32_t tag_len); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t _aes_sync_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_AES_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_can.h b/bsp/microchip/same54/bsp/hal/include/hpl_can.h new file mode 100644 index 0000000000..80b53138d3 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_can.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_H_INCLUDED +#define HPL_CAN_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can CAN Common declaration + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN Message Format + */ +enum can_format { + CAN_FMT_STDID, /*!< Standard Format, 11 bits identifier */ + CAN_FMT_EXTID /*!< Extended Format, 29 bits identifier */ +}; + +/** + * \brief CAN Message Type + */ +enum can_type { + CAN_TYPE_DATA, /*!< A DATA FRAME carries data from a transmitter to the + receivers.*/ + CAN_TYPE_REMOTE /*!< A REMOTE FRAME is transmitted by a bus unit to request + the transmission of the DATA FRAME with the same + IDENTIFIER */ +}; + +/** + * \brief CAN Bus Mode + */ +enum can_mode { + /** Normal operation Mode */ + CAN_MODE_NORMAL, + /** In Bus Monitoring mode (see ISO11898-1, 10.12 Bus monitoring), the CAN + * is able to receive valid data frames and valid remote frames, but + * cannot start a transmission. In this mode, it sends only recessive bits + * on the CAN bus. If the CAN is required to send a dominant bit (ACK bit, + * overload flag, active error flag), the bit is rerouted internally so + * that the CAN monitors this dominant bit, although the CAN bus may + * remain in recessive state. + * The Bus Monitoring mode can be used to analyze the traffic on a CAN bus + * without affecting it by the transmission of dominant bits. + */ + CAN_MODE_MONITORING +}; + +/** + * \brief CAN Message + */ +struct can_message { + uint32_t id; /* Message identifier */ + enum can_type type; /* Message Type */ + uint8_t * data; /* Pointer to Message Data */ + uint8_t len; /* Message Length */ + enum can_format fmt; /* Identifier format, CAN_STD, CAN_EXT */ +}; + +/** + * \brief CAN Filter + */ +struct can_filter { + uint32_t id; /* Message identifier */ + uint32_t mask; /* The mask applied to the id */ +}; + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_can_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_can_async.h new file mode 100644 index 0000000000..ba82672549 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_can_async.h @@ -0,0 +1,245 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_ASYNC_H_INCLUDED +#define HPL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can_async CAN HPL Driver + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN device descriptor forware declaration + */ +struct _can_async_device; + +/** + * \brief CAN callback types + */ +enum can_async_callback_type { + CAN_ASYNC_RX_CB, /*!< A new message arrived */ + CAN_ASYNC_TX_CB, /*!< A message transmitted */ + CAN_ASYNC_IRQ_CB /*!< Message error of some kind on the CAN bus IRQ */ +}; + +enum can_async_interrupt_type { + CAN_IRQ_EW, /*!< Error warning, Error counter has reached the + error warning limit of 96, An error count value + greater than about 96 indicates a heavily disturbed + bus. It may be of advantage to provide means to test + for this condition. Refer to ISO 11898-1 (Bosch CAN + specification 2.0 part A,B) + */ + CAN_IRQ_EA, /*!< Error Active State, The CAN node normally take + part in bus communication and sends an ACTIVE ERROR + FLAG when an error has been detected. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_EP, /*!< Error Passive State, The Can node goes into error + passive state if at least one of its error counters is + greater than 127. It still takes part in bus + activities, but it sends a passive error frame only, + on errors. Refer to ISO 11898-1 (7) + */ + CAN_IRQ_BO, /*!< Bus Off State, The CAN node is 'bus off' when the + TRANSMIT ERROR COUNT is greater than or equal to 256. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_DO /*!< Data Overrun in receive queue. A message was lost + because the messages in the queue was not reading and + releasing fast enough. There is not enough space for + a new message in receive queue. + */ +}; +/** + * \brief CAN interrupt handlers structure + */ +struct _can_async_callback { + void (*tx_done)(struct _can_async_device *dev); + void (*rx_done)(struct _can_async_device *dev); + void (*irq_handler)(struct _can_async_device *dev, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN device descriptor + */ +struct _can_async_device { + void * hw; /*!< CAN hardware pointer */ + struct _can_async_callback cb; /*!< CAN interrupt handler */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * context; /*!< CAN hardware context */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN device descriptor. + * + * \param[in, out] dev A CAN device descriptor to initialize + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev); + +/** + * \brief Enable CAN + * + * This function enable CAN by the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to enable + * + * \return Enabling status. + */ +int32_t _can_async_enable(struct _can_async_device *const dev); + +/** + * \brief Disable CAN + * + * This function disable CAN by the given can device descriptor. + * + * \param[in] dev The CAN descriptor to disable + * + * \return Disabling status. + */ +int32_t _can_async_disable(struct _can_async_device *const dev); + +/** + * \brief Read a CAN message + * + * \param[in] dev The CAN device descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] dev The CAN device descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Set CAN Interrupt State + * + * \param[in] dev The CAN device descriptor + * \param[in] type Callback type + * \param[in] state ture for enable or false for disable + * + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state); + +/** + * \brief Return number of read errors + * + * This function return number of read errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of read errors. + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev); + +/** + * \brief Return number of write errors + * + * This function return number of write errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of write errors. + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] mode CAN operation mode + * + * \return Status of the operation + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] index Index of Filter list + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_cmcc.h b/bsp/microchip/same54/bsp/hal/include/hpl_cmcc.h new file mode 100644 index 0000000000..cb260913b5 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_cmcc.h @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HPL_CMCC_H_ +#define HPL_CMCC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \Cache driver MACROS + */ +#define CMCC_DISABLE 0U +#define CMCC_ENABLE 1U +#define IS_CMCC_DISABLED 0U +#define IS_CMCC_ENABLED 1U +#define CMCC_WAY_NOS 4U +#define CMCC_LINE_NOS 64U +#define CMCC_MONITOR_DISABLE 0U + +/** + * \brief Cache size configurations + */ +enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; + +/** + * \brief Way Numbers + */ +enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; + +/** + * \brief Cache monitor configurations + */ +enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; + +/** + * \brief Cache configuration structure + */ +struct _cache_cfg { + enum conf_cache_size cache_size; + bool data_cache_disable; + bool inst_cache_disable; + bool gclk_gate_disable; +}; + +/** + * \brief Cache enable status + */ +static inline bool _is_cache_enabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); +} + +/** + * \brief Cache disable status + */ +static inline bool _is_cache_disabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); +} + +/** + * \brief Cache enable + */ +static inline int32_t _cmcc_enable(const void *hw) +{ + int32_t return_value; + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); + return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NO_CHANGE; + } + + return return_value; +} + +/** + * \brief Cache disable + */ +static inline int32_t _cmcc_disable(const void *hw) +{ + hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); + while (!(_is_cache_disabled(hw))) + ; + + return ERR_NONE; +} + +/** + * \brief Initialize Cache Module + * + * This function initialize low level cmcc module configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void); + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value); + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value); + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value); + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index); + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw); + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw); + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw); + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw); + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw); + +#ifdef __cplusplus +} +#endif +#endif /* HPL_CMCC_H_ */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_core.h b/bsp/microchip/same54/bsp/hal/include/hpl_core.h new file mode 100644 index 0000000000..9324c43e7c --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_delay.h b/bsp/microchip/same54/bsp/hal/include/hpl_delay.h new file mode 100644 index 0000000000..a0f1ac8125 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_dma.h b/bsp/microchip/same54/bsp/hal/include/hpl_dma.h new file mode 100644 index 0000000000..1e08434a16 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_gpio.h b/bsp/microchip/same54/bsp/hal/include/hpl_gpio.h new file mode 100644 index 0000000000..5cdd387b89 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000000..8a9491debb --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000000..ce173ae29a --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000000..92a5765d16 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000000..93b593456c --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_init.h b/bsp/microchip/same54/bsp/hal/include/hpl_init.h new file mode 100644 index 0000000000..71bf49c98e --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_irq.h b/bsp/microchip/same54/bsp/hal/include/hpl_irq.h new file mode 100644 index 0000000000..2894944a0d --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_missing_features.h b/bsp/microchip/same54/bsp/hal/include/hpl_missing_features.h new file mode 100644 index 0000000000..7071db297c --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_ramecc.h b/bsp/microchip/same54/bsp/hal/include/hpl_ramecc.h new file mode 100644 index 0000000000..d79d514180 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_ramecc.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief RAMECC related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAMECC_H_INCLUDED +#define _HPL_RAMECC_H_INCLUDED + +/** + * \addtogroup HPL RAMECC + * + * \section hpl_ramecc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief RAMECC callback type + */ +typedef void (*ramecc_cb_t)(const uint32_t data); + +/** + * \brief RAMECC callback types + */ +enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; + +/** + * \brief RAMECC interrupt callbacks + */ +struct _ramecc_callbacks { + ramecc_cb_t dual_bit_err; + ramecc_cb_t single_bit_err; +}; + +/** + * \brief RAMECC device structure + */ +struct _ramecc_device { + struct _ramecc_callbacks ramecc_cb; + struct _irq_descriptor irq; +}; + +/** + * \brief Initialize RAMECC + * + * This function does low level RAMECC configuration. + * + * \return initialize status + */ +int32_t _ramecc_init(void); + +/** + * \brief Register RAMECC callback + * + * \param[in] type The type of callback + * \param[in] cb A callback function + */ +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_reset.h b/bsp/microchip/same54/bsp/hal/include/hpl_reset.h new file mode 100644 index 0000000000..d627ea6507 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_reset.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_NVM = 8, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_sleep.h b/bsp/microchip/same54/bsp/hal/include/hpl_sleep.h new file mode 100644 index 0000000000..6731ec30e4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi.h new file mode 100644 index 0000000000..a5652e5061 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_async.h new file mode 100644 index 0000000000..8e5a84856c --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000000..8d3555ed67 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_dma.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000000..2b48300ed5 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000000..38df15b463 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000000..564724390c --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000000..ff4c811af7 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_spi_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000000..dc88648f8e --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_usart.h b/bsp/microchip/same54/bsp/hal/include/hpl_usart.h new file mode 100644 index 0000000000..0e09501d7a --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_usart_async.h b/bsp/microchip/same54/bsp/hal/include/hpl_usart_async.h new file mode 100644 index 0000000000..3f833d1ae1 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/include/hpl_usart_sync.h b/bsp/microchip/same54/bsp/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000000..abc7264f2d --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/src/hal_aes_sync.c b/bsp/microchip/same54/bsp/hal/src/hal_aes_sync.c new file mode 100644 index 0000000000..d790bb19d0 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_aes_sync.c @@ -0,0 +1,481 @@ +/** + * \file + * + * \brief AES Advanced Encryption Standard(Sync) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +#define DRIVER_VERSION 0x00000001u + +static inline void aes_sync_cfb_crypt_first_unaligned_data(const enum aes_action enc, const uint8_t **input, + uint8_t **output, uint32_t *length, uint8_t *iv, + uint32_t *iv_ofst, uint32_t block_bytes); + +static inline void aes_sync_cfb_crypt_last_unaligned_data(struct aes_sync_descriptor *descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv, uint32_t *iv_ofst); +/** + * \brief Initialize AES. + */ +int32_t aes_sync_init(struct aes_sync_descriptor *descr, void *const hw) +{ + ASSERT(descr && hw); + + return _aes_sync_init(&descr->dev, hw); +} + +/** + * \brief Deinitialize AES. + */ +int32_t aes_sync_deinit(struct aes_sync_descriptor *descr) +{ + ASSERT(descr); + + return _aes_sync_deinit(&descr->dev); +} + +/** + * \brief Enable AES + */ +int32_t aes_sync_enable(struct aes_sync_descriptor *descr) +{ + ASSERT(descr); + + return _aes_sync_enable(&descr->dev); +} + +/** + * \brief Disable AES + */ +int32_t aes_sync_disable(struct aes_sync_descriptor *descr) +{ + ASSERT(descr); + + return _aes_sync_disable(&descr->dev); +} + +/** + * \brief Set AES Key (encryption) + */ +int32_t aes_sync_set_encrypt_key(struct aes_sync_descriptor *descr, const uint8_t *key, const enum aes_keysize size) +{ + ASSERT(descr && key); + return _aes_sync_set_key(&descr->dev, key, size); +} + +/** + * \brief Set AES Key (decryption) + */ +int32_t aes_sync_set_decrypt_key(struct aes_sync_descriptor *descr, const uint8_t *key, const enum aes_keysize size) +{ + ASSERT(descr && key); + return _aes_sync_set_key(&descr->dev, key, size); +} + +/** + * \brief AES-ECB block encryption/decryption + */ +int32_t aes_sync_ecb_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output) +{ + ASSERT(descr && input && output); + return _aes_sync_ecb_crypt(&descr->dev, enc, input, output); +} + +/** + * \brief AES-CBC block encryption/decryption + */ +int32_t aes_sync_cbc_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t iv[16]) +{ + ASSERT(descr && input && output && length && iv); + return _aes_sync_cbc_crypt(&descr->dev, enc, input, output, length, iv); +} + +/** + * \brief AES-CFB encryption/decryption first block unaligned data + */ +static inline void aes_sync_cfb_crypt_first_unaligned_data(const enum aes_action enc, const uint8_t **input, + uint8_t **output, uint32_t *length, uint8_t *iv, + uint32_t *iv_ofst, uint32_t block_bytes) +{ + if (*iv_ofst) { + while (((*iv_ofst) < block_bytes) && *length) { + **output = (**input) ^ iv[*iv_ofst]; + /* Update IV for next crypt */ + iv[*iv_ofst] = (enc == AES_ENCRYPT) ? (**output) : (**input); + (*input)++; + (*output)++; + (*iv_ofst)++; + (*length)--; + } + *iv_ofst &= (block_bytes - 1); + } +} + +/** + * \brief AES-CFB encryption/decryption last block unaligned data + */ +static inline void aes_sync_cfb_crypt_last_unaligned_data(struct aes_sync_descriptor *descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv, uint32_t *iv_ofst) +{ + if (length) { + _aes_sync_ecb_crypt(&descr->dev, AES_ENCRYPT, iv, iv); + while ((*iv_ofst) < length) { + *output = (*input) ^ iv[*iv_ofst]; + /* Update IV for next crypt */ + iv[*iv_ofst] = (enc == AES_ENCRYPT) ? (*output) : (*input); + input++; + output++; + (*iv_ofst)++; + } + } +} + +/** + * \brief AES-CFB128 block encryption/decryption + */ +int32_t aes_sync_cfb128_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst) +{ + ASSERT(descr && input && output && length && iv && iv_ofst && *iv_ofst < 16); + + aes_sync_cfb_crypt_first_unaligned_data(enc, &input, &output, &length, iv, iv_ofst, 16); + /* if left length more than 1 block, then use cfb128 encrypt */ + if (length >> 4) { + _aes_sync_cfb128_crypt(&descr->dev, enc, input, output, (length & ~0xF), iv); + input += (length & ~0xF); + output += (length & ~0xF); + length = length & 0xF; + } + aes_sync_cfb_crypt_last_unaligned_data(descr, enc, input, output, length, iv, iv_ofst); + + return ERR_NONE; +} + +/** + * \brief AES-CFB64 block encryption/decryption + */ +int32_t aes_sync_cfb64_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst) +{ + ASSERT(descr && input && output && length && iv && iv_ofst && *iv_ofst < 8); + + aes_sync_cfb_crypt_first_unaligned_data(enc, &input, &output, &length, iv, iv_ofst, 8); + /* if left length more than 1 block, then use cfb64 encrypt */ + if (length >> 3) { + _aes_sync_cfb64_crypt(&descr->dev, enc, input, output, (length & ~0x7), iv); + input += (length & ~0x7); + output += (length & ~0x7); + length = length & 0x7; + } + aes_sync_cfb_crypt_last_unaligned_data(descr, enc, input, output, length, iv, iv_ofst); + + return ERR_NONE; +} + +/** + * \brief AES-CFB32 block encryption/decryption + * + * \param[in] desc AES descriptor + * \param[in] enc AES_SYNC_ENCRYPT or AES_SYNC_DECRYPT + * \param[in] input buffer holding the input data + * \param[out] output buffer holding the output data + * \param[out] length byte length of the input data + * \param[in, out] iv initialization Vector (updated after use) + * \param[in, out] iv_ofst offset in IV (updated after use) + * + * \return ERR_NONE if successful + */ +int32_t aes_sync_cfb32_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst) +{ + ASSERT(descr && input && output && length && iv && iv_ofst && *iv_ofst < 4); + + aes_sync_cfb_crypt_first_unaligned_data(enc, &input, &output, &length, iv, iv_ofst, 4); + /* if left length more than 1 block, then use cfb32 encrypt */ + if (length >> 2) { + _aes_sync_cfb32_crypt(&descr->dev, enc, input, output, (length & ~0x3), iv); + input += (length & ~0x3); + output += (length & ~0x3); + length = length & 0x3; + } + aes_sync_cfb_crypt_last_unaligned_data(descr, enc, input, output, length, iv, iv_ofst); + + return ERR_NONE; +} + +/** + * \brief AES-CFB16 block encryption/decryption + */ +int32_t aes_sync_cfb16_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv, uint32_t *iv_ofst) +{ + ASSERT(descr && input && output && length && iv && iv_ofst && *iv_ofst < 2); + + aes_sync_cfb_crypt_first_unaligned_data(enc, &input, &output, &length, iv, iv_ofst, 2); + + /* if left length more than 1 block, then use cfb16 encrypt */ + if (length >> 1) { + _aes_sync_cfb16_crypt(&descr->dev, enc, input, output, (length & ~0x1), iv); + input += (length & ~0x1); + output += (length & ~0x1); + length = length & 0x1; + } + aes_sync_cfb_crypt_last_unaligned_data(descr, enc, input, output, length, iv, iv_ofst); + + return ERR_NONE; +} + +/** + * \brief AES-CFB8 block encryption/decryption + */ +int32_t aes_sync_cfb8_crypt(struct aes_sync_descriptor *descr, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + ASSERT(descr && input && output && length && iv); + return _aes_sync_cfb8_crypt(&descr->dev, enc, input, output, length, iv); +} + +/** + * \brief AES-OFB block encryption/decryption + */ +int32_t aes_sync_ofb_crypt(struct aes_sync_descriptor *descr, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv, uint32_t *iv_ofst) +{ + ASSERT(descr && input && output && length && iv && iv_ofst && *iv_ofst < 16); + + /* Encrypt first unaligned block data */ + if (*iv_ofst) { + while ((*iv_ofst) < 16 && length) { + *output = (uint8_t)((*input) ^ iv[*iv_ofst]); + input++; + output++; + (*iv_ofst)++; + length--; + } + *iv_ofst &= 0xF; + } + + /* if left length more than 1 block, then use cfb128 encrypt */ + if (length >> 4) { + _aes_sync_ofb_crypt(&descr->dev, input, output, (length & ~0xF), iv); + input += (length & ~0xF); + output += (length & ~0xF); + length = length & 0xF; + *iv_ofst = 0; + } + /* Encrypt last unaligned data and update iv */ + if (length) { + _aes_sync_ecb_crypt(&descr->dev, AES_ENCRYPT, iv, iv); + while ((*iv_ofst) < length) { + *output = (*input) ^ iv[*iv_ofst]; + input++; + output++; + (*iv_ofst)++; + } + } + return ERR_NONE; +} + +/** + * \brief AES-CTR block encryption/decryption + */ +int32_t aes_sync_ctr_crypt(struct aes_sync_descriptor *descr, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t buffer[16], uint8_t nc[16], uint32_t *nc_ofst) +{ + int32_t i; + ASSERT(descr && input && output && length && nc && nc_ofst && *nc_ofst < 16); + + /* Encrypt first unaligned block data */ + if (*nc_ofst) { + while ((*nc_ofst) < 16 && length) { + *output++ = (*input) ^ buffer[*nc_ofst]; + input++; + (*nc_ofst)++; + length--; + } + *nc_ofst &= 0xF; + } + /* if left length more than 1 block, then use ctr encrypt */ + if (length >> 4) { + _aes_sync_ctr_crypt(&descr->dev, input, output, (length & ~0xF), nc); + input += (length & ~0xF); + output += (length & ~0xF); + length = length & 0xF; + } + /* Encrypt last unaligned data and update buffer */ + if (length) { + _aes_sync_ecb_crypt(&descr->dev, AES_ENCRYPT, nc, buffer); + for (i = 16; i > 0; i--) { + if (++nc[i - 1] != 0) + break; + } + while (*nc_ofst < length) { + *output++ = (*input) ^ buffer[*nc_ofst]; + input++; + (*nc_ofst)++; + } + } + + return ERR_NONE; +} + +/** + * \brief AES-GCM block encryption/decryption + */ +int32_t aes_sync_gcm_crypt_and_tag(struct aes_sync_descriptor *const descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, uint8_t *tag, + uint32_t tag_len) +{ + ASSERT(descr && iv && iv_len); + ASSERT((input && output && length) || (!length)); + ASSERT(((aad && aad_len) || !aad_len)); + ASSERT((tag && tag_len && (tag_len <= 16)) || !tag_len); + return _aes_sync_gcm_crypt_and_tag(&descr->dev, enc, input, output, length, iv, iv_len, aad, aad_len, tag, tag_len); +} + +/** + * \brief AES-GCM block encryption + */ +int32_t aes_sync_gcm_auth_decrypt(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, const uint8_t *tag, uint32_t tag_len) +{ + uint8_t vtag[16]; + uint32_t index; + int32_t result; + + ASSERT(descr && iv && iv_len); + ASSERT((input && output && length) || (!length)); + ASSERT(((aad && aad_len) || !aad_len)); + ASSERT((tag && tag_len && (tag_len <= 16)) || !tag_len); + + result = _aes_sync_gcm_crypt_and_tag( + &descr->dev, AES_DECRYPT, input, output, length, iv, iv_len, aad, aad_len, vtag, tag_len); + if (result != ERR_NONE) { + return result; + } + for (index = 0; index < tag_len; index++) { + if (vtag[index] != tag[index]) { + return ERR_INVALID_DATA; + } + } + return ERR_NONE; +} + +/** + * \brief AES-GCM block start + */ +int32_t aes_sync_gcm_start(struct aes_sync_descriptor *const descr, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len) +{ + ASSERT(descr && iv && iv_len); + ASSERT((aad && aad_len) || !aad_len); + return _aes_sync_gcm_start(&descr->dev, enc, iv, iv_len, aad, aad_len); +} + +/** + * \brief AES-GCM block update + */ +int32_t aes_sync_gcm_update(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length) +{ + ASSERT(descr); + ASSERT((input && output && length) || (!length)); + return _aes_sync_gcm_update(&descr->dev, input, output, length); +} + +/** + * \brief AES-GCM block finish + */ +int32_t aes_sync_gcm_finish(struct aes_sync_descriptor *const descr, uint8_t *tag, uint32_t tag_len) +{ + ASSERT(descr && ((tag && tag_len && (tag_len <= 16)) || !tag_len)); + return _aes_sync_gcm_finish(&descr->dev, tag, tag_len); +} + +/** + * \brief AES-CCM block encryption/decryption + */ +int32_t aes_sync_ccm_crypt_and_tag(struct aes_sync_descriptor *const descr, const enum aes_action enc, + const uint8_t *input, uint8_t *output, uint32_t length, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, uint8_t *tag, + uint32_t tag_len) +{ + ASSERT(descr && input && output && length && iv); + ASSERT((aad && aad_len) || !aad_len); + /* Length requirements follow the SP800-38C A.1 */ + ASSERT(tag && (tag_len >= 4) && (tag_len <= 16) && !(tag_len % 2)); + ASSERT((iv_len >= 7) && (iv_len <= 13)); + + return _aes_sync_ccm_crypt_and_tag(&descr->dev, enc, input, output, length, iv, iv_len, aad, aad_len, tag, tag_len); +} + +/** + * \brief AES-CCM block authenticated decryption + */ +int32_t aes_sync_ccm_auth_decrypt(struct aes_sync_descriptor *const descr, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, const uint8_t *tag, uint32_t tag_len) +{ + uint8_t vtag[16]; + uint32_t index; + int32_t result; + + ASSERT(descr && input && output && length && iv); + ASSERT((aad && aad_len) || !aad_len); + /* Length requirements follow the SP800-38C A.1 */ + ASSERT(tag && (tag_len >= 4) && (tag_len <= 16) && !(tag_len % 2)); + ASSERT((iv_len >= 7) && (iv_len <= 13)); + + result = _aes_sync_ccm_crypt_and_tag( + &descr->dev, AES_DECRYPT, input, output, length, iv, iv_len, aad, aad_len, vtag, tag_len); + if (result != ERR_NONE) { + return result; + } + for (index = 0; index < tag_len; index++) { + if (vtag[index] != tag[index]) { + return ERR_INVALID_DATA; + } + } + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t aes_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_atomic.c b/bsp/microchip/same54/bsp/hal/src/hal_atomic.c new file mode 100644 index 0000000000..f56418ee6f --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_cache.c b/bsp/microchip/same54/bsp/hal/src/hal_cache.c new file mode 100644 index 0000000000..b2e75aa722 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_cache.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +/** + * \brief Initialize cache module + */ +int32_t cache_init(void) +{ + return _cmcc_init(); +} + +/** + * \brief Enable cache module + */ +int32_t cache_enable(const void *hw) +{ + return _cmcc_enable(hw); +} + +/** + * \brief Disable cache module + */ +int32_t cache_disable(const void *hw) +{ + return _cmcc_disable(hw); +} + +/** + * \brief Configure cache module + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache) +{ + return _cmcc_configure(hw, cache); +} + +/** + * \brief Invalidate entire cache entries + */ +int32_t cache_invalidate_all(const void *hw) +{ + return _cmcc_invalidate_all(hw); +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_can_async.c b/bsp/microchip/same54/bsp/hal/src/hal_can_async.c new file mode 100644 index 0000000000..84c75c45cd --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_can_async.c @@ -0,0 +1,230 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +#define DRIVER_VERSION 0x00000001u + +/** + * \internal Callback of CAN Message Write finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_tx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Message Read finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_rx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Interrupt + * + * \param[in] dev The pointer to CAN device structure + * \param[in] type Interrupt source type + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type); + +/** + * \brief Initialize CAN. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw) +{ + int32_t rc; + + ASSERT(descr && hw); + + rc = _can_async_init(&descr->dev, hw); + if (rc) { + return rc; + } + descr->dev.cb.tx_done = can_tx_done; + descr->dev.cb.rx_done = can_rx_done; + descr->dev.cb.irq_handler = can_irq_handler; + + return ERR_NONE; +} + +/** + * \brief Deinitialize CAN. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_deinit(&descr->dev); +} + +/** + * \brief Enable CAN + */ +int32_t can_async_enable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_enable(&descr->dev); +} + +/** + * \brief Disable CAN + */ +int32_t can_async_disable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_disable(&descr->dev); +} + +/** + * \brief Read a CAN message + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_read(&descr->dev, msg); +} + +/** + * \brief Write a CAN message + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_write(&descr->dev, msg); +} + +/** + * \brief Register CAN callback function to interrupt + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb) +{ + ASSERT(descr); + + switch (type) { + case CAN_ASYNC_RX_CB: + descr->cb.rx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_TX_CB: + descr->cb.tx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_IRQ_CB: + descr->cb.irq_handler + = (cb != NULL) ? (void (*)(struct can_async_descriptor *const, enum can_async_interrupt_type))cb : NULL; + break; + default: + return ERR_INVALID_ARG; + } + + _can_async_set_irq_state(&descr->dev, type, NULL != cb); + + return ERR_NONE; +} + +/** + * \brief Return number of read errors + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_rxerr(&descr->dev); +} + +/** + * \brief Return number of write errors + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_txerr(&descr->dev); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode) +{ + ASSERT(descr); + return _can_async_set_mode(&descr->dev, mode); +} + +/** + * \brief Set CAN filter + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + ASSERT(descr); + return _can_async_set_filter(&descr->dev, index, fmt, filter); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t can_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Callback of CAN Message Write finished + */ +static void can_tx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.tx_done) { + descr->cb.tx_done(descr); + } +} + +/** + * \internal Callback of CAN Message Read finished + */ +static void can_rx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.rx_done) { + descr->cb.rx_done(descr); + } +} + +/** + * \internal Callback of CAN Interrupt + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.irq_handler) { + descr->cb.irq_handler(descr, type); + } +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_delay.c b/bsp/microchip/same54/bsp/hal/src/hal_delay.c new file mode 100644 index 0000000000..6f77cc7064 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_gpio.c b/bsp/microchip/same54/bsp/hal/src/hal_gpio.c new file mode 100644 index 0000000000..00dfea6f70 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_init.c b/bsp/microchip/same54/bsp/hal/src/hal_init.c new file mode 100644 index 0000000000..fb65341fb6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_io.c b/bsp/microchip/same54/bsp/hal/src/hal_io.c new file mode 100644 index 0000000000..7e8feb0453 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_sleep.c b/bsp/microchip/same54/bsp/hal/src/hal_sleep.c new file mode 100644 index 0000000000..89472f156a --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same54/bsp/hal/src/hal_usart_sync.c b/bsp/microchip/same54/bsp/hal/src/hal_usart_sync.c new file mode 100644 index 0000000000..ab99c1d166 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/bsp/microchip/same54/bsp/hal/utils/include/compiler.h b/bsp/microchip/same54/bsp/hal/utils/include/compiler.h new file mode 100644 index 0000000000..f35db3df8e --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/err_codes.h b/bsp/microchip/same54/bsp/hal/utils/include/err_codes.h new file mode 100644 index 0000000000..a7aff01893 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/bsp/microchip/same54/bsp/hal/utils/include/events.h b/bsp/microchip/same54/bsp/hal/utils/include/events.h new file mode 100644 index 0000000000..3ee891a73e --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/parts.h b/bsp/microchip/same54/bsp/hal/utils/include/parts.h new file mode 100644 index 0000000000..98bb969034 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "same54.h" + +#include "hri_e54.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils.h b/bsp/microchip/same54/bsp/hal/utils/include/utils.h new file mode 100644 index 0000000000..1cf2699690 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils_assert.h b/bsp/microchip/same54/bsp/hal/utils/include/utils_assert.h new file mode 100644 index 0000000000..c2328d6c31 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils_event.h b/bsp/microchip/same54/bsp/hal/utils/include/utils_event.h new file mode 100644 index 0000000000..13067c4fec --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils_increment_macro.h b/bsp/microchip/same54/bsp/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000000..464c6cbb72 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils_list.h b/bsp/microchip/same54/bsp/hal/utils/include/utils_list.h new file mode 100644 index 0000000000..977e8ccad4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hal/utils/include/utils_repeat_macro.h b/bsp/microchip/same54/bsp/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000000..89e6f52d5b --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/bsp/microchip/same54/bsp/hal/utils/src/utils_assert.c b/bsp/microchip/same54/bsp/hal/utils/src/utils_assert.c new file mode 100644 index 0000000000..b376c9700f --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/bsp/microchip/same54/bsp/hal/utils/src/utils_event.c b/bsp/microchip/same54/bsp/hal/utils/src/utils_event.c new file mode 100644 index 0000000000..d1af9d0cf1 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/bsp/microchip/same54/bsp/hal/utils/src/utils_list.c b/bsp/microchip/same54/bsp/hal/utils/src/utils_list.c new file mode 100644 index 0000000000..4006a01933 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/bsp/microchip/same54/bsp/hal/utils/src/utils_syscalls.c b/bsp/microchip/same54/bsp/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000000..d8c6357e15 --- /dev/null +++ b/bsp/microchip/same54/bsp/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} +#if 0 +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} +#endif +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/bsp/microchip/same54/bsp/hpl/aes/hpl_aes.c b/bsp/microchip/same54/bsp/hpl/aes/hpl_aes.c new file mode 100644 index 0000000000..a4d7c7a95f --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/aes/hpl_aes.c @@ -0,0 +1,1293 @@ +/** + * \file + * + * \brief AES Advanced Encryption Standard(Sync) functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Update the AES KEY Register + */ +static inline void __aes_sync_set_key(struct _aes_sync_device *const dev); + +/** + * \brief Update the Initialization Vector Register + */ +static inline void __aes_sync_set_iv(struct _aes_sync_device *const dev, uint8_t *iv); + +/** + * \brief Update the INDATA Register + */ +static inline void __aes_sync_set_indata(struct _aes_sync_device *const dev, const uint8_t *data, uint32_t words); + +/** + * \brief Get data from INDATA Register + */ +static inline void __aes_sync_get_indata(struct _aes_sync_device *const dev, uint8_t *output, uint32_t words); + +/** + * \brief UPDATE CFB IV after encrypt/decrypt + */ +static inline void __aes_sync_update_cfb_iv(const enum aes_action enc, const uint8_t *input, uint8_t *output, + uint32_t length, uint8_t *iv); +/** + * GCM crypt function, start->update->generate_tag, should be invoke + * by sequence. + */ +static void __aes_sync_gcm_start(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len); +static void __aes_sync_gcm_update(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length); +static void __aes_sync_gcm_generate_tag(struct _aes_sync_device *const dev, uint8_t *tag, uint32_t tag_len); +/** + * CCM encrypt decrypt function + */ +int32_t __aes_sync_ccm_crypt_and_tag(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, uint8_t *tag, uint32_t tag_len); +int32_t __aes_sync_ccm_decrypt_and_tag(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, uint8_t *tag, uint32_t tag_len); +/** + * \brief AES configuration type + */ +struct aes_configuration { + hri_aes_dbgctrl_reg_t dbgctrl; /*!< Debug Control */ +}; + +/** + * \brief Array of AES configurations + */ +static struct aes_configuration _aes = {(CONF_AES_DBGCTRL << AES_DBGCTRL_DBGRUN_Pos)}; + +static inline void __aes_sync_set_key(struct _aes_sync_device *const dev) +{ + int i; + + for (i = 0; i < ((dev->keysize + 2) << 1); i++) { + hri_aes_write_KEYWORD_reg(dev->hw, i, (((uint32_t *)(dev->key))[i])); + } +} + +static inline void __aes_sync_set_iv(struct _aes_sync_device *const dev, uint8_t *iv) +{ + int i; + + for (i = 0; i < 4; i++) { + if (((uint32_t)iv) & 0x3) { + hri_aes_write_INTVECTV_reg(dev->hw, + i, + ((uint8_t *)iv)[i << 2] | ((uint8_t *)iv)[(i << 2) + 1] >> 8 + | ((uint8_t *)iv)[(i << 2) + 2] >> 16 | ((uint8_t *)iv)[(i << 2) + 3] >> 24); + } else { + hri_aes_write_INTVECTV_reg(dev->hw, i, ((uint32_t *)iv)[i]); + } + } +} + +static inline void __aes_sync_set_indata(struct _aes_sync_device *const dev, const uint8_t *data, uint32_t words) +{ + uint32_t i; + + for (i = 0; i < words; i++) { + if (((uint32_t)data) & 0x3) { + hri_aes_write_INDATA_reg(dev->hw, + ((uint8_t *)data)[i << 2] | ((uint8_t *)data)[(i << 2) + 1] << 8 + | ((uint8_t *)data)[(i << 2) + 2] << 16 + | ((uint8_t *)data)[(i << 2) + 3] << 24); + } else { + hri_aes_write_INDATA_reg(dev->hw, ((uint32_t *)data)[i]); + } + } +} + +static inline void __aes_sync_get_indata(struct _aes_sync_device *const dev, uint8_t *output, uint32_t words) +{ + uint32_t i; + uint32_t buf; + + for (i = 0; i < words; i++) { + if (((uint32_t)output) & 0x3) { + buf = (uint32_t)hri_aes_read_INDATA_reg(dev->hw); + *output++ = buf & 0xFF; + *output++ = (buf >> 8) & 0xFF; + *output++ = (buf >> 16) & 0xFF; + *output++ = (buf >> 24) & 0xFF; + } else { + ((uint32_t *)output)[i] = hri_aes_read_INDATA_reg(dev->hw); + } + } +} + +static inline void __aes_sync_update_cfb_iv(const enum aes_action enc, const uint8_t *input, uint8_t *output, + uint32_t length, uint8_t *iv) +{ + const uint8_t *ptr = ((enc == AES_ENCRYPT) ? output : input); + + if (length >= 16) { + memcpy(iv, ptr + length - 16, 16); + } else { + memcpy(iv, iv + length, 16 - length); + memcpy(iv + 16 - length, ptr, length); + } +} +/** + * \brief Initialize AES. + */ +int32_t _aes_sync_init(struct _aes_sync_device *const dev, void *const hw) +{ + hri_aes_write_CTRLA_reg(hw, 0); + hri_aes_write_CTRLA_reg(hw, AES_CTRLA_SWRST); + + dev->hw = hw; + + hri_aes_write_DBGCTRL_reg(dev->hw, _aes.dbgctrl); + + return ERR_NONE; +} + +/** + * \brief De-initialize AES. + */ +int32_t _aes_sync_deinit(struct _aes_sync_device *dev) +{ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_set_CTRLA_SWRST_bit(dev->hw); + dev->hw = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable AES + */ +int32_t _aes_sync_enable(struct _aes_sync_device *const dev) +{ + (void)dev; + return ERR_NONE; +} + +/** + * \brief Disable AES + */ +int32_t _aes_sync_disable(struct _aes_sync_device *const dev) +{ + (void)dev; + return ERR_NONE; +} + +/** + * \brief Set AES Key (encryption/decryption) + */ +int32_t _aes_sync_set_key(struct _aes_sync_device *const dev, const uint8_t *key, const enum aes_keysize size) +{ + + dev->keysize = size; + memcpy(dev->key, key, (size + 2) << 3); + return ERR_NONE; +} + +/** + * \brief AES-ECB block encryption/decryption + */ +int32_t _aes_sync_ecb_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output) +{ + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLB_reg(dev->hw, 0); + hri_aes_write_CTRLA_reg(dev->hw, AES_CTRLA_KEYSIZE(dev->keysize) | (enc << AES_CTRLA_CIPHER_Pos)); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + /* Key must be set for each ECB encrypt */ + __aes_sync_set_key(dev); + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, input, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, output, 4); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} + +/** + * \brief AES-CBC block encryption/decryption + */ +int32_t _aes_sync_cbc_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t iv[16]) +{ + // uint8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLA_reg(dev->hw, + AES_CTRLA_AESMODE(1) | AES_CTRLA_KEYSIZE(dev->keysize) | (enc << AES_CTRLA_CIPHER_Pos)); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLB_reg(dev->hw, 0); + + /* The Key must be write before CBC crypt */ + __aes_sync_set_key(dev); + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 4); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 4); + inptr += 16; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 4); + outptr += 16; + } + + /* IV equals last cipher text */ + memcpy(iv, (enc == AES_ENCRYPT) ? output + length - 16 : input + length - 16, 16); + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} + +/** + * \brief AES-CFB128 block encryption/decryption + */ +int32_t _aes_sync_cfb128_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + uint8_t block; /* Number of blocks (16 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, enc); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 3); + hri_aes_clear_CTRLA_CFBS_bf(dev->hw, 0x7u); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 4); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 4); + inptr += 16; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 4); + outptr += 16; + } + + __aes_sync_update_cfb_iv(enc, input, output, length, iv); + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} + +/** + * \brief AES-CFB64 block encryption/decryption + */ +int32_t _aes_sync_cfb64_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + uint8_t block; /* Number of blocks (8 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, enc); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 3); + hri_aes_write_CTRLA_CFBS_bf(dev->hw, 1); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 3); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 2); + inptr += 8; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 2); + outptr += 8; + } + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + + __aes_sync_update_cfb_iv(enc, input, output, length, iv); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-CFB32 block encryption/decryption + */ +int32_t _aes_sync_cfb32_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + uint8_t block; /* Number of blocks (4 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, enc); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 3); + hri_aes_write_CTRLA_CFBS_bf(dev->hw, 2); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 2); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 1); + inptr += 4; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 1); + outptr += 4; + } + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_update_cfb_iv(enc, input, output, length, iv); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-CFB16 block encryption/decryption + */ +int32_t _aes_sync_cfb16_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + uint8_t block; /* Number of blocks (2 bytes) */ + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, enc); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 3); + hri_aes_write_CTRLA_CFBS_bf(dev->hw, 3); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + for (block = 0; block < (length >> 1); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + hri_aes_write_INDATA_reg(dev->hw, ((uint16_t *)input)[block]); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + ((uint16_t *)output)[block] = hri_aes_read_INDATA_reg(dev->hw) & 0xFFFF; + } + + __aes_sync_update_cfb_iv(enc, input, output, length, iv); + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-CFB8 block encryption/decryption + */ +int32_t _aes_sync_cfb8_crypt(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, uint8_t *iv) +{ + uint8_t block; /* Number of blocks (1 bytes) */ + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, enc); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 3); + hri_aes_write_CTRLA_CFBS_bf(dev->hw, 4); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + for (block = 0; block < length; block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + hri_aes_write_INDATA_reg(dev->hw, ((uint8_t *)input)[block]); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + ((uint8_t *)output)[block] = hri_aes_read_INDATA_reg(dev->hw) & 0xFF; + } + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + + __aes_sync_update_cfb_iv(enc, input, output, length, iv); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-OFB block encryption/decryption + */ +int32_t _aes_sync_ofb_crypt(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t *iv) +{ + uint8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLB_reg(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 2); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, iv); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 4); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 4); + inptr += 16; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 4); + outptr += 16; + } + + /* IV equals last plain text xor cipher text */ + for (index = 0; index < 16; index++) { + iv[index] = input[length - 16 + index] ^ output[length - 16 + index]; + } + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-CTR block encryption/decryption + */ +int32_t _aes_sync_ctr_crypt(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, uint32_t length, + uint8_t nc[16]) +{ + uint8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + const uint8_t *inptr; + uint8_t * outptr; + + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0x00); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 4); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + /* Write IV */ + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_set_iv(dev, nc); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + for (block = 0; block < (length >> 4); block++) { + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_indata(dev, inptr, 4); + inptr += 16; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, outptr, 4); + outptr += 16; + + /* NC equals last NC + 1 */ + for (index = 0; index < 16; index++) { + nc[15 - index] += 1; + if (nc[15 - index]) { + break; + } + } + } + + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief AES-GCM block encryption/decryption + */ +int32_t _aes_sync_gcm_crypt_and_tag(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, const uint8_t *iv, uint32_t iv_len, + const uint8_t *aad, uint32_t aad_len, uint8_t *tag, uint32_t tag_len) +{ + uint8_t iv_initialized[16] = {0}; + + __aes_sync_gcm_start(dev, enc, iv, iv_len, aad, aad_len); + + /* Copy the initialized IV for tag generation */ + memcpy(iv_initialized, dev->iv, 16); + + __aes_sync_gcm_update(dev, input, output, length); + + /* Restore IV before generating tag */ + memcpy(dev->iv, iv_initialized, 16); + + __aes_sync_gcm_generate_tag(dev, tag, tag_len); + + return ERR_NONE; +} + +/** + * \brief AES-GCM block start + */ +int32_t _aes_sync_gcm_start(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len) +{ + __aes_sync_gcm_start(dev, enc, iv, iv_len, aad, aad_len); + return ERR_NONE; +} + +/** + * \brief AES-GCM block update + */ +int32_t _aes_sync_gcm_update(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, uint32_t length) +{ + __aes_sync_gcm_update(dev, input, output, length); + return ERR_NONE; +} + +/** + * \brief AES-GCM block finish + */ +int32_t _aes_sync_gcm_finish(struct _aes_sync_device *const dev, uint8_t *tag, uint32_t tag_len) +{ + /* Generate Tag, The final GHash should be present at GHASHx reg now */ + __aes_sync_gcm_generate_tag(dev, tag, tag_len); + return ERR_NONE; +} + +/** + * \brief AES-CCM block encryption/decryption + */ +int32_t _aes_sync_ccm_crypt_and_tag(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *input, + uint8_t *output, uint32_t length, const uint8_t *iv, uint32_t iv_len, + const uint8_t *aad, uint32_t aad_len, uint8_t *tag, uint32_t tag_len) +{ + if (enc) { + __aes_sync_ccm_crypt_and_tag(dev, input, output, length, iv, iv_len, aad, aad_len, tag, tag_len); + } else { + __aes_sync_ccm_decrypt_and_tag(dev, input, output, length, iv, iv_len, aad, aad_len, tag, tag_len); + } + return ERR_NONE; +} + +static void __aes_sync_gcm_start(struct _aes_sync_device *const dev, const enum aes_action enc, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len) +{ + uint8_t index; + uint32_t use_len; + int32_t left_len; + uint8_t workbuf[16]; + const uint8_t *ptr; + + /* Step 1 Generate HASHKEY */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_clear_CTRLA_AESMODE_bf(dev->hw, 0x7u); /* 0: ECB */ + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + for (index = 0; index < 4; index++) { + hri_aes_write_INDATA_reg(dev->hw, 0); + } + hri_aes_set_CTRLB_START_bit(dev->hw); + /* HashKey is ready*/ + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + /* Change to GCM mode */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_STARTMODE_bit(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 6); /* GCM */ + hri_aes_clear_CTRLA_CTYPE_bf(dev->hw, 0xFu); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + hri_aes_set_CTRLB_GFMUL_bit(dev->hw); + + /* Step 2: Generate pre-counter block j0 from the IV */ + if (iv_len == 12) { + memcpy(dev->iv, iv, 12); + memset(dev->iv + 12, 0, 3); + dev->iv[15] = 0x01; + } else { + /* If iv_len != 96, then j0 = GHASH(H, {}, IV) */ + for (index = 0; index < 4; index++) { + hri_aes_write_INDATA_reg(dev->hw, 0x00); + } + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + + /* GHASH IV */ + ptr = iv; + left_len = iv_len; + while (left_len >= 0) { + use_len = (left_len < 16) ? left_len : 16; + if (use_len == 16) { + __aes_sync_set_indata(dev, ptr, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + } else { + memset(workbuf, 0, 16); + memcpy(workbuf, ptr, use_len); + __aes_sync_set_indata(dev, workbuf, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + } + left_len -= use_len; + ptr += use_len; + left_len = left_len ? left_len : -1; + } + /* GHASH len(IV)64 */ + memset(workbuf, 0, 12); + workbuf[12] = ((iv_len << 3) >> 24) & 0xFF; + workbuf[13] = ((iv_len << 3) >> 16) & 0xFF; + workbuf[14] = ((iv_len << 3) >> 8) & 0xFF; + workbuf[15] = (iv_len << 3) & 0xFF; + + __aes_sync_set_indata(dev, workbuf, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + /* Get j0 from GHASH reg */ + for (index = 0; index < 4; index++) { + ((uint32_t *)dev->iv)[index] = hri_aes_read_GHASH_reg(dev->hw, index); + hri_aes_write_GHASH_reg(dev->hw, index, 0x00); + } + } + + /* Step 3: GHASH AAD */ + ptr = aad; + left_len = aad_len; + while (left_len >= 0) { + use_len = (left_len < 16) ? left_len : 16; + if (use_len == 16) { + __aes_sync_set_indata(dev, ptr, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + } else { + memset(workbuf, 0, 16); + memcpy(workbuf, ptr, use_len); + __aes_sync_set_indata(dev, workbuf, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + } + left_len -= use_len; + ptr += use_len; + left_len = left_len ? left_len : -1; + } + + /* GFMUL must be clear, otherwise the interrupt flag cannot be set when + * en/decrypt text */ + hri_aes_clear_CTRLB_GFMUL_bit(dev->hw); + + dev->aad_len = aad_len; + + /* Step 3: Change enc/dec */ + if (enc == 0) { + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 0); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + } + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + return; +} + +static void __aes_sync_gcm_update(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length) +{ + int8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + uint8_t workbuf[16]; + const uint8_t *inptr; + uint8_t * outptr; + + /* Set iv = j1 = j0 + 1 */ + for (index = 16; index > 12; index--) { + if (++dev->iv[index - 1] != 0) + break; + } + memcpy(workbuf, dev->iv, 16); + + /* Step 2 Plain text Processing */ + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + hri_aes_clear_interrupt_ENCCMP_bit(dev->hw); + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_write_CIPLEN_reg(dev->hw, length); + + /* Step 2 Set J1 to IV */ + __aes_sync_set_iv(dev, workbuf); + + /* Enc/Dec plain text */ + inptr = input; + outptr = output; + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + for (block = 0; block < (length >> 4); block++) { + if (((length & 0xF) == 0) && block == ((length >> 4) - 1)) { + hri_aes_set_CTRLB_EOM_bit(dev->hw); + } + __aes_sync_set_indata(dev, inptr, 4); + inptr += 16; + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_clear_CTRLB_EOM_bit(dev->hw); + __aes_sync_get_indata(dev, outptr, 4); + outptr += 16; + } + /* If length it not 16 bytes align, then process last one */ + if (length & 0xF) { + memset(workbuf, 0, 16); + memcpy(workbuf, input + (length & ~0xF), length & 0xF); + + hri_aes_set_CTRLB_EOM_bit(dev->hw); + __aes_sync_set_indata(dev, workbuf, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + __aes_sync_get_indata(dev, workbuf, 4); + memcpy(output + (length & ~0xF), workbuf, length & 0xF); + } + + /* Generate Final GHASH by GHASH(H, A, C) */ + memset(workbuf, 0, 16); + ((uint8_t *)workbuf)[4] = ((dev->aad_len << 3) >> 24) & 0xFF; + ((uint8_t *)workbuf)[5] = ((dev->aad_len << 3) >> 16) & 0xFF; + ((uint8_t *)workbuf)[6] = ((dev->aad_len << 3) >> 8) & 0xFF; + ((uint8_t *)workbuf)[7] = (dev->aad_len << 3) & 0xFF; + ((uint8_t *)workbuf)[12] = ((length << 3) >> 24) & 0xFF; + ((uint8_t *)workbuf)[13] = ((length << 3) >> 16) & 0xFF; + ((uint8_t *)workbuf)[14] = ((length << 3) >> 8) & 0xFF; + ((uint8_t *)workbuf)[15] = (length << 3) & 0xFF; + + __aes_sync_set_indata(dev, workbuf, 4); + hri_aes_set_CTRLB_GFMUL_bit(dev->hw); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_GFMCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_GFMUL_bit(dev->hw); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); +} + +/** + * \brief Generate Tag, The final GHash should be present at + * GHASHx reg now + */ +static void __aes_sync_gcm_generate_tag(struct _aes_sync_device *const dev, uint8_t *tag, uint32_t tag_len) +{ + int8_t index; + uint8_t j0[16]; + + memcpy(j0, dev->iv, 16); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + /* When change to Counter mode, all CTRLA should be reset */ + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 4); /* Counter */ + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLB_reg(dev->hw, 0); + + __aes_sync_set_key(dev); + + hri_aes_clear_DATABUFPTR_INDATAPTR_bf(dev->hw, 0x3u); + __aes_sync_set_iv(dev, j0); + for (index = 0; index < 4; index++) { + hri_aes_write_INDATA_reg(dev->hw, (uint32_t)hri_aes_read_GHASH_reg(dev->hw, index)); + } + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + __aes_sync_get_indata(dev, j0, 4); + memcpy(tag, j0, tag_len); + + /* Cleanup, Must be done after GCM crypt, otherwise + * it will effect next GCM crypt. + */ + for (index = 0; index < 4; index++) { + hri_aes_write_GHASH_reg(dev->hw, index, 0x00); + hri_aes_write_HASHKEY_reg(dev->hw, index, 0x00); + hri_aes_write_INDATA_reg(dev->hw, 0x00); + } + hri_aes_write_CIPLEN_reg(dev->hw, 0x00); + hri_aes_write_DATABUFPTR_reg(dev->hw, 0x00); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); +} + +/* + * Encrypt CCM Data, the process follow the SP800-38C + * Section 6.1 Generation-Encryption Process + */ +int32_t __aes_sync_ccm_crypt_and_tag(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, uint8_t *tag, uint32_t tag_len) +{ + int8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + uint8_t q; + uint8_t b[16]; + uint8_t ctr[16]; + const uint8_t *src; + uint8_t * dst; + uint8_t len_left; + uint8_t len_use; + + /* Step 1 (SP800-38C, 6.1): Apply the formatting function to (N,A,P) to + * produce the blocks B0,...Br */ + /* Generate first block B0 */ + memset(b, 0, 16); + q = (16 - 1 - (uint8_t)iv_len); + b[0] = 0; + b[0] |= (aad_len > 0) << 6; + b[0] |= ((tag_len - 2) / 2) << 3; + b[0] |= q - 1; + memcpy(b + 1, iv, iv_len); + for (index = 0, block = length; index < q; index++, block >>= 8) { + b[15 - index] = (uint8_t)(block & 0xFF); + } + if (block > 0) { + return ERR_INVALID_ARG; + } + + /* Prepare CBC-MAC */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLB_reg(dev->hw, 0); + hri_aes_write_CTRLA_STARTMODE_bit(dev->hw, 0); + hri_aes_write_CTRLA_CIPHER_bit(dev->hw, 1); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 5); /* CCM */ + hri_aes_set_CTRLA_LOD_bit(dev->hw); /* CBC-MAC */ + hri_aes_clear_CTRLA_CTYPE_bf(dev->hw, 0xFu); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLB_reg(dev->hw, 0); + hri_aes_write_DATABUFPTR_reg(dev->hw, 0); + __aes_sync_set_key(dev); + /* For CBC-MAC, zero block is used as the IV (SP800-38C, 5.2) */ + for (index = 0; index < 4; index++) { + hri_aes_write_INTVECTV_reg(dev->hw, index, 0x00); + } + + /* Step 2(SP800-38C, 6.1): CBC-MAC for block0 */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + /* Not necessary read out DATA to clear ENCCMP, the ENCCMP flag is + * automatically cleared by writing into the INDATA register. + */ + + /* Step 3(SP800-38C, 6.1) Continue process B1 to Br */ + /* Process additional data if have */ + if (aad_len > 0) { + len_left = aad_len; + src = aad; + + memset(b, 0, 16); + b[0] = (uint8_t)((aad_len >> 8) & 0xFF); + b[1] = (uint8_t)((aad_len)&0xFF); + + len_use = len_left < 16 - 2 ? len_left : 16 - 2; + for (index = 2; index < len_use + 2; index++) { + b[index] = *src; + src++; + } + len_left -= len_use; + + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + while (len_left > 0) { + len_use = len_left > 16 ? 16 : len_left; + memset(b, 0, 16); + memcpy(b, src, len_use); + src += len_use; + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + len_left -= len_use; + } + } + + /* Step Process plain text */ + len_left = length; + src = input; + dst = output; + while (len_left > 0) { + len_use = len_left > 16 ? 16 : len_left; + + if (len_use < 16) { + memset(b, 0, 16); + } + memcpy(b, src, len_use); + src += len_use; + + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + len_left -= len_use; + } + /* Step 4 (800-38C, 6.1) Get Tag from MSB(Br), + * Temporary save to output tag, the tag + * will be update at the final step. + */ + __aes_sync_get_indata(dev, b, 4); + memcpy(tag, b, tag_len); + + /* Step 5,6,7 (800-38C, 6.1) Change to counter mode and encrypt plain text + * Make sure set the CTRLB->NEWMSG bit after set/change INTVECTV + */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_clear_CTRLA_LOD_bit(dev->hw); /* Counter MODE */ + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + __aes_sync_set_key(dev); + /* + * Prepare counter block for encryption: + */ + memset(ctr, 0, 16); + ctr[0] = q - 1; + memcpy(ctr + 1, iv, iv_len); + ctr[15] = 1; + __aes_sync_set_iv(dev, ctr); + + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + len_left = length; + src = input; + dst = output; + while (len_left > 0) { + len_use = len_left > 16 ? 16 : len_left; + if (len_use < 16) { + memset(b, 0, 16); + } + memcpy(b, src, len_use); + src += len_use; + + /* UPDATE Cipher text */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_get_indata(dev, b, 4); + memcpy(dst, b, len_use); + dst += len_use; + len_left -= len_use; + } + + /* Step 8 (800-38C, 6.1) Update Tag = Tag XOR MSBtlen(S0) */ + ctr[15] = 0; + __aes_sync_set_iv(dev, ctr); + if (tag_len < 16) { + memset(b, 0, 16); + } + memcpy(b, tag, tag_len); + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_get_indata(dev, b, 4); + memcpy(tag, b, tag_len); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} +/* + * Encrypt CCM Data, the process follow the SP800-38C + * Section 6.2 Decryption-Verification Process + */ +int32_t __aes_sync_ccm_decrypt_and_tag(struct _aes_sync_device *const dev, const uint8_t *input, uint8_t *output, + uint32_t length, const uint8_t *iv, uint32_t iv_len, const uint8_t *aad, + uint32_t aad_len, uint8_t *tag, uint32_t tag_len) +{ + int8_t index; + uint8_t block; /* Number of blocks (16 bytes) */ + uint8_t q; + uint8_t b[16]; + uint8_t ctr[16]; + const uint8_t *src; + uint8_t * dst; + uint8_t len_left; + uint8_t len_use; + + /* Step 2(SP800-38C, 6.2) Prepare Counter for decrypt cipher text */ + memset(ctr, 0, 16); + q = (16 - 1 - (uint8_t)iv_len); + ctr[0] = q - 1; + memcpy(ctr + 1, iv, iv_len); + ctr[15] = 1; + + /* Step 3,4,5(SP800-38C, 6.2) Decrypt cipher text */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLB_reg(dev->hw, 0); + hri_aes_write_CTRLA_STARTMODE_bit(dev->hw, 0); + hri_aes_clear_CTRLA_CIPHER_bit(dev->hw); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 5); /* CCM */ + hri_aes_clear_CTRLA_LOD_bit(dev->hw); /* Counter mode */ + hri_aes_clear_CTRLA_CTYPE_bf(dev->hw, 0xFu); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + __aes_sync_set_key(dev); + + __aes_sync_set_iv(dev, ctr); + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + len_left = length; + src = input; + dst = output; + while (len_left > 0) { + size_t len_use = len_left > 16 ? 16 : len_left; + { + if (len_use < 16) { + memset(b, 0, 16); + } + memcpy(b, src, len_use); + src += len_use; + /* UPDATE Cipher text */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_get_indata(dev, b, 4); + memcpy(dst, b, len_use); + dst += len_use; + } + len_left -= len_use; + } + + /* Step 6(SP800-38C, 6.2) this step was skipped, the input tag will be + * checked in HAL, below step will generate tag from plain text(output) + */ + /* Step 7(SP800-38C, 6.2) Prepare CBC-MAC */ + hri_aes_write_CTRLA_reg(dev->hw, 0); + hri_aes_write_CTRLA_STARTMODE_bit(dev->hw, 0); + hri_aes_write_CTRLA_KEYSIZE_bf(dev->hw, dev->keysize); + hri_aes_write_CTRLA_AESMODE_bf(dev->hw, 5); /* CCM */ + hri_aes_set_CTRLA_LOD_bit(dev->hw); /* CBC-MAC */ + hri_aes_set_CTRLA_CIPHER_bit(dev->hw); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + + __aes_sync_set_key(dev); + /* For CBC-MAC, zero block is used as the IV (SP800-38C, 5.2)*/ + for (index = 0; index < 4; index++) { + hri_aes_write_INTVECTV_reg(dev->hw, index, 0x00); + } + + /* Step 8(SP800-38C, 6.2) CBC-MAC for block0 */ + /* Prepare block0 (first block) */ + b[0] = 0; + b[0] |= (aad_len > 0) << 6; + b[0] |= ((tag_len - 2) / 2) << 3; + b[0] |= q - 1; + memcpy(b + 1, iv, iv_len); + for (index = 0, block = length; index < q; index++, block >>= 8) { + b[15 - index] = (uint8_t)(block & 0xFF); + } + if (block > 0) { + return ERR_INVALID_ARG; + } + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + /* Not necessary read out DATA to clear ENCCMP, the ENCCMP flag is + * automatically cleared by writing into the INDATA register. + * (From DataSheet) + */ + /* Step (SP800-38C, 6.2) Continue process B1 to Br */ + /* Process additional data */ + if (aad_len > 0) { + len_left = aad_len; + src = aad; + memset(b, 0, 16); + b[0] = (uint8_t)((aad_len >> 8) & 0xFF); + b[1] = (uint8_t)((aad_len)&0xFF); + + len_use = len_left < 16 - 2 ? len_left : 16 - 2; + for (index = 2; index < len_use + 2; index++) { + b[index] = *src; + src++; + } + len_left -= len_use; + + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + while (len_left > 0) { + len_use = len_left > 16 ? 16 : len_left; + + if (len_use < 16) { + memset(b, 0, 16); + } + memcpy(b, src, len_use); + src += len_use; + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + len_left -= len_use; + } + } + /* Process plain text */ + len_left = length; + src = output; + while (len_left > 0) { + len_use = len_left > 16 ? 16 : len_left; + if (len_use != 16) { + memset(b, 0, 16); + } + memcpy(b, src, len_use); + src += len_use; + + /* UPDATE CBC-MAC */ + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + + len_left -= len_use; + } + /* Step 10(SP800-38C, 6.2) Get Tag from MSBtlen(Yr) */ + __aes_sync_get_indata(dev, b, 4); + memcpy(tag, b, tag_len); + /* Update Tag = Tag XOR MSBtlen(Yr) */ + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + hri_aes_clear_CTRLA_LOD_bit(dev->hw); + hri_aes_set_CTRLA_ENABLE_bit(dev->hw); + ctr[15] = 0; + __aes_sync_set_iv(dev, ctr); + __aes_sync_set_key(dev); + if (tag_len < 16) { + memset(b, 0, 16); + } + memcpy(b, tag, tag_len); + __aes_sync_set_indata(dev, b, 4); + hri_aes_set_CTRLB_NEWMSG_bit(dev->hw); + hri_aes_set_CTRLB_START_bit(dev->hw); + while (hri_aes_get_interrupt_ENCCMP_bit(dev->hw) == 0) + ; + hri_aes_clear_CTRLB_NEWMSG_bit(dev->hw); + __aes_sync_get_indata(dev, b, 4); + memcpy(tag, b, tag_len); + hri_aes_clear_CTRLA_ENABLE_bit(dev->hw); + + return ERR_NONE; +} diff --git a/bsp/microchip/same54/bsp/hpl/can/hpl_can.c b/bsp/microchip/same54/bsp/hpl/can/hpl_can.c new file mode 100644 index 0000000000..016270cce3 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/can/hpl_can.c @@ -0,0 +1,423 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +#ifdef CONF_CAN0_ENABLED +COMPILER_ALIGNED(4) +uint8_t can0_rx_fifo[CONF_CAN0_F0DS * CONF_CAN0_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can0_tx_fifo[CONF_CAN0_TBDS * CONF_CAN0_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can0_tx_event_fifo[CONF_CAN0_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can0_rx_std_filter[CONF_CAN0_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can0_rx_ext_filter[CONF_CAN0_XIDFC_LSS]; + +struct _can_context _can0_context = {.rx_fifo = can0_rx_fifo, + .tx_fifo = can0_tx_fifo, + .tx_event = can0_tx_event_fifo, + .rx_std_filter = can0_rx_std_filter, + .rx_ext_filter = can0_rx_ext_filter}; +static struct _can_async_device *_can0_dev = NULL; /*!< Pointer to hpl device */ + +#endif /* CONF_CAN0_ENABLED */ + +#ifdef CONF_CAN1_ENABLED +COMPILER_ALIGNED(4) +uint8_t can1_rx_fifo[CONF_CAN1_F0DS * CONF_CAN1_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can1_tx_fifo[CONF_CAN1_TBDS * CONF_CAN1_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can1_tx_event_fifo[CONF_CAN1_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can1_rx_std_filter[CONF_CAN1_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can1_rx_ext_filter[CONF_CAN1_XIDFC_LSS]; + +struct _can_context _can1_context = {.rx_fifo = can1_rx_fifo, + .tx_fifo = can1_tx_fifo, + .tx_event = can1_tx_event_fifo, + .rx_std_filter = can1_rx_std_filter, + .rx_ext_filter = can1_rx_ext_filter}; +static struct _can_async_device *_can1_dev = NULL; /*!< Pointer to hpl device */ + +#endif /* CONF_CAN1_ENABLED */ + +/** + * \brief Initialize CAN. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw) +{ + dev->hw = hw; + hri_can_set_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_can_set_CCCR_CCE_bit(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (hw == CAN0) { + _can0_dev = dev; + dev->context = (void *)&_can0_context; + hri_can_set_CCCR_reg(dev->hw, CONF_CAN0_CCCR_REG); + hri_can_write_MRCFG_reg(dev->hw, CONF_CAN0_MRCFG_REG); + hri_can_write_NBTP_reg(dev->hw, CONF_CAN0_BTP_REG); + hri_can_write_DBTP_reg(dev->hw, CONF_CAN0_DBTP_REG); + hri_can_write_RXF0C_reg(dev->hw, CONF_CAN0_RXF0C_REG | CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo)); + hri_can_write_RXESC_reg(dev->hw, CONF_CAN0_RXESC_REG); + hri_can_write_TXESC_reg(dev->hw, CONF_CAN0_TXESC_REG); + hri_can_write_TXBC_reg(dev->hw, CONF_CAN0_TXBC_REG | CAN_TXBC_TBSA((uint32_t)can0_tx_fifo)); + hri_can_write_TXEFC_reg(dev->hw, CONF_CAN0_TXEFC_REG | CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo)); + hri_can_write_GFC_reg(dev->hw, CONF_CAN0_GFC_REG); + hri_can_write_SIDFC_reg(dev->hw, CONF_CAN0_SIDFC_REG | CAN_SIDFC_FLSSA((uint32_t)can0_rx_std_filter)); + hri_can_write_XIDFC_reg(dev->hw, CONF_CAN0_XIDFC_REG | CAN_XIDFC_FLESA((uint32_t)can0_rx_ext_filter)); + hri_can_write_XIDAM_reg(dev->hw, CONF_CAN0_XIDAM_REG); + + NVIC_DisableIRQ(CAN0_IRQn); + NVIC_ClearPendingIRQ(CAN0_IRQn); + NVIC_EnableIRQ(CAN0_IRQn); + hri_can_write_ILE_reg(dev->hw, CAN_ILE_EINT0); + } +#endif + +#ifdef CONF_CAN1_ENABLED + if (hw == CAN1) { + _can1_dev = dev; + dev->context = (void *)&_can1_context; + hri_can_set_CCCR_reg(dev->hw, CONF_CAN1_CCCR_REG); + hri_can_write_MRCFG_reg(dev->hw, CONF_CAN1_MRCFG_REG); + hri_can_write_NBTP_reg(dev->hw, CONF_CAN1_BTP_REG); + hri_can_write_DBTP_reg(dev->hw, CONF_CAN1_DBTP_REG); + hri_can_write_RXF0C_reg(dev->hw, CONF_CAN1_RXF0C_REG | CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo)); + hri_can_write_RXESC_reg(dev->hw, CONF_CAN1_RXESC_REG); + hri_can_write_TXESC_reg(dev->hw, CONF_CAN1_TXESC_REG); + hri_can_write_TXBC_reg(dev->hw, CONF_CAN1_TXBC_REG | CAN_TXBC_TBSA((uint32_t)can1_tx_fifo)); + hri_can_write_TXEFC_reg(dev->hw, CONF_CAN1_TXEFC_REG | CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo)); + hri_can_write_GFC_reg(dev->hw, CONF_CAN1_GFC_REG); + hri_can_write_SIDFC_reg(dev->hw, CONF_CAN1_SIDFC_REG | CAN_SIDFC_FLSSA((uint32_t)can1_rx_std_filter)); + hri_can_write_XIDFC_reg(dev->hw, CONF_CAN1_XIDFC_REG | CAN_XIDFC_FLESA((uint32_t)can1_rx_ext_filter)); + hri_can_write_XIDAM_reg(dev->hw, CONF_CAN1_XIDAM_REG); + + NVIC_DisableIRQ(CAN1_IRQn); + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_EnableIRQ(CAN1_IRQn); + hri_can_write_ILE_reg(dev->hw, CAN_ILE_EINT0); + } +#endif + + /* Disable CCE to prevent Configuration Change */ + hri_can_clear_CCCR_CCE_bit(dev->hw); + hri_can_clear_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw)) { + }; + + return ERR_NONE; +} + +/** + * \brief De-initialize CAN. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + dev->hw = NULL; + return ERR_NONE; +} + +/** + * \brief Enable CAN + */ +int32_t _can_async_enable(struct _can_async_device *const dev) +{ + hri_can_clear_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Disable CAN + */ +int32_t _can_async_disable(struct _can_async_device *const dev) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Read a CAN message + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_rx_fifo_entry *f = NULL; + hri_can_rxf0s_reg_t get_index; + + if (!hri_can_read_RXF0S_F0FL_bf(dev->hw)) { + return ERR_NOT_FOUND; + } + + get_index = hri_can_read_RXF0S_F0GI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == CAN0) { + f = (struct _can_rx_fifo_entry *)(can0_rx_fifo + get_index * CONF_CAN0_F0DS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == CAN1) { + f = (struct _can_rx_fifo_entry *)(can1_rx_fifo + get_index * CONF_CAN1_F0DS); + } +#endif + + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (f->R0.bit.XTD == 1) { + msg->fmt = CAN_FMT_EXTID; + msg->id = f->R0.bit.ID; + } else { + msg->fmt = CAN_FMT_STDID; + /* A standard identifier is stored into ID[28:18] */ + msg->id = f->R0.bit.ID >> 18; + } + + if (f->R0.bit.RTR == 1) { + msg->type = CAN_TYPE_REMOTE; + } + + const uint8_t dlc2len[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + msg->len = dlc2len[f->R1.bit.DLC]; + + memcpy(msg->data, f->data, msg->len); + + hri_can_write_RXF0A_F0AI_bf(dev->hw, get_index); + + return ERR_NONE; +} + +/** + * \brief Write a CAN message + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_tx_fifo_entry *f = NULL; + hri_can_txfqs_reg_t put_index; + + if (hri_can_get_TXFQS_TFQF_bit(dev->hw)) { + return ERR_NO_RESOURCE; + } + + put_index = hri_can_read_TXFQS_TFQPI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == CAN0) { + f = (struct _can_tx_fifo_entry *)(can0_tx_fifo + put_index * CONF_CAN0_TBDS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == CAN1) { + f = (struct _can_tx_fifo_entry *)(can1_tx_fifo + put_index * CONF_CAN1_TBDS); + } +#endif + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (msg->fmt == CAN_FMT_EXTID) { + f->T0.val = msg->id; + f->T0.bit.XTD = 1; + } else { + /* A standard identifier is stored into ID[28:18] */ + f->T0.val = msg->id << 18; + } + + if (msg->len <= 8) { + f->T1.bit.DLC = msg->len; + } else if (msg->len <= 12) { + f->T1.bit.DLC = 0x9; + } else if (msg->len <= 16) { + f->T1.bit.DLC = 0xA; + } else if (msg->len <= 20) { + f->T1.bit.DLC = 0xB; + } else if (msg->len <= 24) { + f->T1.bit.DLC = 0xC; + } else if (msg->len <= 32) { + f->T1.bit.DLC = 0xD; + } else if (msg->len <= 48) { + f->T1.bit.DLC = 0xE; + } else if (msg->len <= 64) { + f->T1.bit.DLC = 0xF; + } + + f->T1.bit.FDF = hri_can_get_CCCR_FDOE_bit(dev->hw); + f->T1.bit.BRS = hri_can_get_CCCR_BRSE_bit(dev->hw); + + memcpy(f->data, msg->data, msg->len); + + hri_can_write_TXBAR_reg(dev->hw, 1 << hri_can_read_TXFQS_TFQPI_bf(dev->hw)); + return ERR_NONE; +} + +/** + * \brief Set CAN Interrupt State + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state) +{ + uint32_t ie; + + if (type == CAN_ASYNC_RX_CB) { + hri_can_write_IE_RF0NE_bit(dev->hw, state); + } else if (type == CAN_ASYNC_TX_CB) { + hri_can_write_IE_TCE_bit(dev->hw, state); + hri_can_write_TXBTIE_reg(dev->hw, CAN_TXBTIE_MASK); + } else if (type == CAN_ASYNC_IRQ_CB) { + ie = hri_can_get_IE_reg(dev->hw, CAN_IE_RF0NE | CAN_IE_TCE); + hri_can_write_IE_reg(dev->hw, ie | CONF_CAN0_IE_REG); + } + + return; +} + +/** + * \brief Return number of read errors + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev) +{ + return hri_can_read_ECR_REC_bf(dev->hw); +} + +/** + * \brief Return number of write errors + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev) +{ + return hri_can_read_ECR_TEC_bf(dev->hw); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode) +{ + hri_can_set_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_can_set_CCCR_CCE_bit(dev->hw); + + if (mode == CAN_MODE_MONITORING) { + hri_can_set_CCCR_MON_bit(dev->hw); + } else { + hri_can_clear_CCCR_MON_bit(dev->hw); + } + + /* Disable CCE to prevent Configuration Change */ + hri_can_clear_CCCR_CCE_bit(dev->hw); + hri_can_clear_CCCR_INIT_bit(dev->hw); + while (hri_can_get_CCCR_INIT_bit(dev->hw)) + ; + + return ERR_NONE; +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + struct _can_standard_message_filter_element *sf; + struct _can_extended_message_filter_element *ef; + + sf = &((struct _can_context *)dev->context)->rx_std_filter[index]; + ef = &((struct _can_context *)dev->context)->rx_ext_filter[index]; + + if (fmt == CAN_FMT_STDID) { + if (filter == NULL) { + sf->S0.val = 0; + return ERR_NONE; + } + sf->S0.val = filter->mask; + sf->S0.bit.SFID1 = filter->id; + sf->S0.bit.SFT = _CAN_SFT_CLASSIC; + sf->S0.bit.SFEC = _CAN_SFEC_STF0M; + } else if (fmt == CAN_FMT_EXTID) { + if (filter == NULL) { + ef->F0.val = 0; + return ERR_NONE; + } + ef->F0.val = filter->id; + ef->F0.bit.EFEC = _CAN_EFEC_STF0M; + ef->F1.val = filter->mask; + ef->F1.bit.EFT = _CAN_EFT_CLASSIC; + } + + return ERR_NONE; +} + +/* + * \brief CAN interrupt handler + */ +void CAN1_Handler(void) +{ + struct _can_async_device *dev = _can1_dev; + uint32_t ir; + ir = hri_can_read_IR_reg(dev->hw); + + if (ir & CAN_IR_RF0N) { + dev->cb.rx_done(dev); + } + + if (ir & CAN_IR_TC) { + dev->cb.tx_done(dev); + } + + if (ir & CAN_IR_BO) { + dev->cb.irq_handler(dev, CAN_IRQ_BO); + } + + if (ir & CAN_IR_EW) { + dev->cb.irq_handler(dev, CAN_IRQ_EW); + } + + if (ir & CAN_IR_EP) { + dev->cb.irq_handler(dev, hri_can_get_PSR_EP_bit(dev->hw) ? CAN_IRQ_EP : CAN_IRQ_EA); + } + + if (ir & CAN_IR_RF0L) { + dev->cb.irq_handler(dev, CAN_IRQ_DO); + } + + hri_can_write_IR_reg(dev->hw, ir); +} diff --git a/bsp/microchip/same54/bsp/hpl/can/hpl_can_base.h b/bsp/microchip/same54/bsp/hpl/can/hpl_can_base.h new file mode 100644 index 0000000000..8e820d6a6a --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/can/hpl_can_base.h @@ -0,0 +1,204 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_BASE_H_INCLUDED +#define HPL_CAN_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief CAN receive FIFO element. + */ +struct _can_rx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R0; + __IO union { + struct { + uint32_t RXTS : 16; /*!< Rx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t : 2; /*!< Reserved */ + uint32_t FIDX : 7; /*!< Filter Index */ + uint32_t ANMF : 1; /*!< Accepted Non-matching Frame */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit FIFO element. + */ +struct _can_tx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T0; + __IO union { + struct { + uint32_t : 16; /*!< Reserved */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t : 1; /*!< Reserved */ + uint32_t EFC : 1; /*!< Event FIFO Control */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit Event element. + */ +struct _can_tx_event_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R0; + __IO union { + struct { + uint32_t TXTS : 16; /*!< Tx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t ET : 2; /*!< Event Type */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R1; +}; + +/** + * \brief CAN standard message ID filter element structure. + * + * Common element structure for standard message ID filter element. + */ +struct _can_standard_message_filter_element { + __IO union { + struct { + uint32_t SFID2 : 11; /*!< Standard Filter ID 2 */ + uint32_t : 5; /*!< Reserved */ + uint32_t SFID1 : 11; /*!< Standard Filter ID 1 */ + uint32_t SFEC : 3; /*!< Standard Filter Configuration */ + uint32_t SFT : 2; /*!< Standard Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } S0; +}; + +#define _CAN_SFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_SFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_SFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_SFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_SFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_SFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_SFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_SFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_SFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_SFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_SFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ + +#define _CAN_EFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_EFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_EFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_EFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_EFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_EFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_EFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_EFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_EFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_EFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_EFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ +/** + * \brief CAN extended message ID filter element structure. + * + * Common element structure for extended message ID filter element. + */ +struct _can_extended_message_filter_element { + __IO union { + struct { + uint32_t EFID1 : 29; /*!< bit: Extended Filter ID 1 */ + uint32_t EFEC : 3; /*!< bit: Extended Filter Configuration */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F0; + __IO union { + struct { + uint32_t EFID2 : 29; /*!< bit: Extended Filter ID 2 */ + uint32_t : 1; /*!< bit: Reserved */ + uint32_t EFT : 2; /*!< bit: Extended Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F1; +}; + +struct _can_context { + uint8_t * rx_fifo; /*!< receive message fifo */ + uint8_t * tx_fifo; /*!< transfer message fifo */ + struct _can_tx_event_entry *tx_event; /*!< transfer event fifo */ + /* Standard filter List */ + struct _can_standard_message_filter_element *rx_std_filter; + /* Extended filter List */ + struct _can_extended_message_filter_element *rx_ext_filter; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_BASE_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hpl/cmcc/hpl_cmcc.c b/bsp/microchip/same54/bsp/hpl/cmcc/hpl_cmcc.c new file mode 100644 index 0000000000..bddf0e1f0c --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/cmcc/hpl_cmcc.c @@ -0,0 +1,354 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include + +/** + * \brief Initialize Cache Module + * + * This function does low level cache configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void) +{ + int32_t return_value; + + _cmcc_disable(CMCC); + + if (_is_cache_disabled(CMCC)) { + hri_cmcc_write_CFG_reg( + CMCC, + (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) + | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); + + _cmcc_enable(CMCC); + return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) +{ + int32_t return_value; + + _cmcc_disable(hw); + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CFG_reg( + hw, + (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) + | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); + + return_value = ERR_NONE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_DCDIS; + tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_ICDIS; + tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp |= value; + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= (~CMCC_CFG_CSIZESW_Msk); + tmp |= (size << CMCC_CFG_CSIZESW_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp |= CMCC_LCKWAY_LCKWAY(num); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp &= (~CMCC_LCKWAY_LCKWAY(num)); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) +{ + int32_t return_value; + + if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { + _cmcc_disable(hw); + while (!(_is_cache_disabled(hw))) + ; + hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); + return_value = ERR_NONE; + } else { + return_value = ERR_INVALID_ARG; + } + + return return_value; +} + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw) +{ + int32_t return_value; + + _cmcc_disable(hw); + if (_is_cache_disabled(hw)) { + hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); + return_value = ERR_NONE; + } else { + return_value = ERR_FAILURE; + } + + return return_value; +} + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) +{ + hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); + + return ERR_NONE; +} + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); + + return ERR_NONE; +} + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); + + return ERR_NONE; +} + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw) +{ + hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); + + return ERR_NONE; +} + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw) +{ + return hri_cmcc_read_MSR_reg(hw); +} diff --git a/bsp/microchip/same54/bsp/hpl/core/hpl_core_m4.c b/bsp/microchip/same54/bsp/hpl/core/hpl_core_m4.c new file mode 100644 index 0000000000..4680ec3102 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/core/hpl_core_m4.c @@ -0,0 +1,241 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#elif CONF_CPU_FREQUENCY < 1000000000 +#define CPU_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) + 2) / 3; + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000) + 2) / 3 * 1000; + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ + __asm(".syntax unified\n" + ".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi.n __delay\n"); +#endif +#endif +} diff --git a/bsp/microchip/same54/bsp/hpl/core/hpl_core_port.h b/bsp/microchip/same54/bsp/hpl/core/hpl_core_port.h new file mode 100644 index 0000000000..3f3e8f282e --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hpl/core/hpl_init.c b/bsp/microchip/same54/bsp/hpl/core/hpl_init.c new file mode 100644 index 0000000000..651d03d565 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/core/hpl_init.c @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Referenced GCLKs (out of 0~11), should be initialized firstly + * - GCLK 2 for FDPLL0 + */ +#define _GCLK_INIT_1ST 0x00000004 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x00000FFB + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif + +#if CONF_CMCC_ENABLE + cache_init(); +#endif +} diff --git a/bsp/microchip/same54/bsp/hpl/dmac/hpl_dmac.c b/bsp/microchip/same54/bsp/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000000..c7b03b0095 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/dmac/hpl_dmac.c @@ -0,0 +1,263 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM]; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* DMAC interrupt handler */ +static void _dmac_handler(void); + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ + | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ + DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ + (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ + | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t ctrla; + uint8_t prilvl; + uint8_t evctrl; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); + hri_dmac_set_CTRL_SWRST_bit(DMAC); + while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) + ; + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); + hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); + hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + for (i = 0; i < 5; i++) { + NVIC_DisableIRQ(DMAC_0_IRQn + i); + NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); + NVIC_EnableIRQ(DMAC_0_IRQn + i); + } + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); + + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} +/** + * \internal DMAC interrupt handler + */ +static void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); + struct _dma_resource *tmp_resource = &_resources[channel]; + + if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_0_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_1_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_2_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_3_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_4_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk.c b/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000000..211ccc3ff6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk.c @@ -0,0 +1,312 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + if (bm & (1ul << 9)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + if (bm & (1ul << 10)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + if (bm & (1ul << 11)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); + } +#endif +} diff --git a/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk_base.h b/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000000..3e7d282576 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hpl/mclk/hpl_mclk.c b/bsp/microchip/same54/bsp/hpl/mclk/hpl_mclk.c new file mode 100644 index 0000000000..66843205bd --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/mclk/hpl_mclk.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} diff --git a/bsp/microchip/same54/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c b/bsp/microchip/same54/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 0000000000..8859b42ebf --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,82 @@ + +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | +#ifdef CONF_XOSC32K_CGM + OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | +#endif + (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/bsp/microchip/same54/bsp/hpl/oscctrl/hpl_oscctrl.c b/bsp/microchip/same54/bsp/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 0000000000..9f55076331 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,230 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC0_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 0, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) + | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC0_CONFIG == 1 +#if CONF_XOSC0_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) + ; +#endif +#if CONF_XOSC0_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); +#endif +#if CONF_XOSC0_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_XOSC1_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 1, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) + | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC1_CONFIG == 1 +#if CONF_XOSC1_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) + ; +#endif +#if CONF_XOSC1_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); +#endif +#if CONF_XOSC1_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DFLL_CONFIG == 1 + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; + uint8_t tmp; + hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) + ; + + hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; + + tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; + hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); + while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) + ; + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) + | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) + | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; + hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 0, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) + | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 0, + (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 1, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) + | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 1, + (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + ; +#endif +#if CONF_FDPLL0_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) + ; +#endif +#if CONF_FDPLL1_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; +#endif + (void)hw; +} diff --git a/bsp/microchip/same54/bsp/hpl/pm/hpl_pm.c b/bsp/microchip/same54/bsp/hpl/pm/hpl_pm.c new file mode 100644 index 0000000000..55dc4dbeb6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/pm/hpl_pm.c @@ -0,0 +1,68 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + uint8_t delay = 10; + + switch (mode) { + case 2: + case 4: + case 5: + case 6: + case 7: + hri_pm_write_SLEEPCFG_reg(PM, mode); + /* A small latency happens between the store instruction and actual + * writing of the SLEEPCFG register due to bridges. Software has to make + * sure the SLEEPCFG register reads the wanted value before issuing WFI + * instruction. + */ + do { + if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { + break; + } + } while (--delay); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/bsp/microchip/same54/bsp/hpl/pm/hpl_pm_base.h b/bsp/microchip/same54/bsp/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000000..5a50a914ad --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/hpl/port/hpl_gpio_base.h b/bsp/microchip/same54/bsp/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000000..f32c40f7d4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/port/hpl_gpio_base.h @@ -0,0 +1,172 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT, port, mask); + } else { + hri_port_clear_OUT_reg(PORT, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); +} diff --git a/bsp/microchip/same54/bsp/hpl/ramecc/hpl_ramecc.c b/bsp/microchip/same54/bsp/hpl/ramecc/hpl_ramecc.c new file mode 100644 index 0000000000..4c158b2035 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/ramecc/hpl_ramecc.c @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Generic RAMECC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/* RAMECC device descriptor */ +struct _ramecc_device device; + +/** + * \brief Initialize RAMECC + */ +int32_t _ramecc_init(void) +{ + if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { + return ERR_ABORTED; + } + + NVIC_DisableIRQ(RAMECC_IRQn); + NVIC_ClearPendingIRQ(RAMECC_IRQn); + NVIC_EnableIRQ(RAMECC_IRQn); + + return ERR_NONE; +} + +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) +{ + if (RAMECC_DUAL_ERROR_CB == type) { + device.ramecc_cb.dual_bit_err = cb; + hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); + } else if (RAMECC_SINGLE_ERROR_CB == type) { + device.ramecc_cb.single_bit_err = cb; + hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); + } +} + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} diff --git a/bsp/microchip/same54/bsp/hpl/sercom/hpl_sercom.c b/bsp/microchip/same54/bsp/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000000..770278f523 --- /dev/null +++ b/bsp/microchip/same54/bsp/hpl/sercom/hpl_sercom.c @@ -0,0 +1,3032 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ + | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ + | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ + | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ + | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_ctrlc_reg_t ctrl_c; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ + Sercom *const sercom_modules[] = SERCOM_INSTS; + /* Find index for SERCOM instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + return i; + } + } + return 0; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + uint32_t usart_freq, calc_baud, calc_frac; + uint8_t i = _usarts[_get_sercom_index(hw)].number; + + switch (i) { + case 0: +#ifdef CONF_GCLK_SERCOM0_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM0_CORE_FREQUENCY; +#endif + break; + + case 1: +#ifdef CONF_GCLK_SERCOM1_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM1_CORE_FREQUENCY; +#endif + break; + + case 2: +#ifdef CONF_GCLK_SERCOM2_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM2_CORE_FREQUENCY; +#endif + break; + + case 3: +#ifdef CONF_GCLK_SERCOM3_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM3_CORE_FREQUENCY; +#endif + break; + + case 4: +#ifdef CONF_GCLK_SERCOM4_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM4_CORE_FREQUENCY; +#endif + break; + + case 5: +#ifdef CONF_GCLK_SERCOM5_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM5_CORE_FREQUENCY; +#endif + break; + + case 6: +#ifdef CONF_GCLK_SERCOM6_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM6_CORE_FREQUENCY; +#endif + break; + + case 7: +#ifdef CONF_GCLK_SERCOM7_CORE_FREQUENCY + usart_freq = CONF_GCLK_SERCOM7_CORE_FREQUENCY; +#endif + break; + + default: + ASSERT(false); + } + + if(usart_freq >= (16U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 16U * baud_rate) / usart_freq); + calc_frac = 0; + } else if(usart_freq >= (8U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 8U * baud_rate) / usart_freq); + calc_frac = 2; + } else if(usart_freq >= (3U * baud_rate)) { + calc_baud = 65536U - (uint32_t)(((uint64_t)65536U * 3U * baud_rate) / usart_freq); + calc_frac = 4; + } else { + /* Do nothing */ + } + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = calc_baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = calc_frac; + } else { + hri_sercomusart_write_BAUD_reg(hw, calc_baud); + } + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_EnableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/bsp/microchip/same54/bsp/hri/hri_ac_e54.h b/bsp/microchip/same54/bsp/hri/hri_ac_e54.h new file mode 100644 index 0000000000..588499e456 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_ac_e54.h @@ -0,0 +1,1836 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AC_COMPONENT_ +#ifndef _HRI_AC_E54_H_INCLUDED_ +#define _HRI_AC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_calib_reg_t; +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= ~AC_CALIB_BIAS0_Msk; + tmp |= AC_CALIB_BIAS0(data); + ((Ac *)hw)->CALIB.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) +{ + return ((Ac *)hw)->CALIB.reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_E54_H_INCLUDED */ +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_adc_e54.h b/bsp/microchip/same54/bsp/hri/hri_adc_e54.h new file mode 100644 index 0000000000..7bb7e6f8d9 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_adc_e54.h @@ -0,0 +1,3663 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ADC_COMPONENT_ +#ifndef _HRI_ADC_E54_H_INCLUDED_ +#define _HRI_ADC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrla_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_ress_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_dseqctrl_reg_t; +typedef uint32_t hri_adc_dseqdata_reg_t; +typedef uint32_t hri_adc_dseqstat_reg_t; +typedef uint32_t hri_adc_syncbusy_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQSTAT.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) +{ + return ((Adc *)hw)->RESS.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_R2R; + tmp |= value << ADC_CTRLA_R2R_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_DUALSEL_Msk; + tmp |= ADC_CTRLA_DUALSEL(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_PRESCALER_Msk; + tmp |= ADC_CTRLA_PRESCALER(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DIFFMODE; + tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DSEQSTOP; + tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINSS; + tmp |= value << ADC_CTRLB_WINSS_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINMODE_Msk; + tmp |= ADC_CTRLB_WINMODE(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_INPUTCTRL; + tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_CTRLB; + tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_REFCTRL; + tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AVGCTRL; + tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_SAMPCTRL; + tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINLT; + tmp |= value << ADC_DSEQCTRL_WINLT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINUT; + tmp |= value << ADC_DSEQCTRL_WINUT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_GAINCORR; + tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_OFFSETCORR; + tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AUTOSTART; + tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg = data; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASR2R_Msk; + tmp |= ADC_CALIB_BIASR2R(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQDATA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_E54_H_INCLUDED */ +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_aes_e54.h b/bsp/microchip/same54/bsp/hri/hri_aes_e54.h new file mode 100644 index 0000000000..c1070e2ac9 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_aes_e54.h @@ -0,0 +1,1287 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AES_COMPONENT_ +#ifndef _HRI_AES_E54_H_INCLUDED_ +#define _HRI_AES_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= ~AES_DBGCTRL_DBGRUN; + tmp |= value << AES_DBGCTRL_DBGRUN_Pos; + ((Aes *)hw)->DBGCTRL.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) +{ + return ((Aes *)hw)->DBGCTRL.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_E54_H_INCLUDED */ +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_can_e54.h b/bsp/microchip/same54/bsp/hri/hri_can_e54.h new file mode 100644 index 0000000000..2c02884619 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_can_e54.h @@ -0,0 +1,16997 @@ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CAN_COMPONENT_ +#ifndef _HRI_CAN_E54_H_INCLUDED_ +#define _HRI_CAN_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_E54_H_INCLUDED */ +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_ccl_e54.h b/bsp/microchip/same54/bsp/hri/hri_ccl_e54.h new file mode 100644 index 0000000000..c5c48675af --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_ccl_e54.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CCL_COMPONENT_ +#ifndef _HRI_CCL_E54_H_INCLUDED_ +#define _HRI_CCL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_E54_H_INCLUDED */ +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_cmcc_e54.h b/bsp/microchip/same54/bsp/hri/hri_cmcc_e54.h new file mode 100644 index 0000000000..c973d357d4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_cmcc_e54.h @@ -0,0 +1,361 @@ +/** + * \file + * + * \brief SAM CMCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CMCC_COMPONENT_ +#ifndef _HRI_CMCC_E54_H_INCLUDED_ +#define _HRI_CMCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) +#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CMCC_CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_cmcc_cfg_reg_t; +typedef uint32_t hri_cmcc_ctrl_reg_t; +typedef uint32_t hri_cmcc_lckway_reg_t; +typedef uint32_t hri_cmcc_maint0_reg_t; +typedef uint32_t hri_cmcc_maint1_reg_t; +typedef uint32_t hri_cmcc_mcfg_reg_t; +typedef uint32_t hri_cmcc_mctrl_reg_t; +typedef uint32_t hri_cmcc_men_reg_t; +typedef uint32_t hri_cmcc_msr_reg_t; +typedef uint32_t hri_cmcc_sr_reg_t; +typedef uint32_t hri_cmcc_type_reg_t; + +static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; +} + +static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; +} + +static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) +{ + return ((Cmcc *)hw)->TYPE.reg; +} + +static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) +{ + return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->SR.reg; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MSR.reg; +} + +static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->CFG.reg; +} + +static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->LCKWAY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) +{ + return ((Cmcc *)hw)->LCKWAY.reg; +} + +static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MCFG.reg; +} + +static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MEN.reg; +} + +static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT0.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT1.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CMCC_E54_H_INCLUDED */ +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_dac_e54.h b/bsp/microchip/same54/bsp/hri/hri_dac_e54.h new file mode 100644 index 0000000000..911dd52931 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_dac_e54.h @@ -0,0 +1,1706 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DAC_COMPONENT_ +#ifndef _HRI_DAC_E54_H_INCLUDED_ +#define _HRI_DAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint16_t hri_dac_result_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; +} + +static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; +} + +static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; +} + +static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; +} + +static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; +} + +static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; +} + +static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; +} + +static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->RESULT[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->RESULT[index].reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO0; + tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO1; + tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_FEXT; + tmp |= value << DAC_DACCTRL_FEXT_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_OSR_Msk; + tmp |= DAC_DACCTRL_OSR(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_E54_H_INCLUDED */ +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_dmac_e54.h b/bsp/microchip/same54/bsp/hri/hri_dmac_e54.h new file mode 100644 index 0000000000..b4a6ba1eb2 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_dmac_e54.h @@ -0,0 +1,6800 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_E54_H_INCLUDED_ +#define _HRI_DMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrla_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacchannel_chctrla_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrlb_reg_t; +typedef uint8_t hri_dmac_chevctrl_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chprilvl_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmacchannel_chctrlb_reg_t; +typedef uint8_t hri_dmacchannel_chevctrl_reg_t; +typedef uint8_t hri_dmacchannel_chintenset_reg_t; +typedef uint8_t hri_dmacchannel_chintflag_reg_t; +typedef uint8_t hri_dmacchannel_chprilvl_reg_t; +typedef uint8_t hri_dmacchannel_chstatus_reg_t; + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; + tmp |= DMAC_CRCCTRL_CRCMODE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS0_Msk; + tmp |= DMAC_PRICTRL0_QOS0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS1_Msk; + tmp |= DMAC_PRICTRL0_QOS1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS2_Msk; + tmp |= DMAC_PRICTRL0_QOS2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS3_Msk; + tmp |= DMAC_PRICTRL0_QOS3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_CRCERR; + tmp |= value << DMAC_INTPEND_CRCERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; + tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = data; + ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((DmacChannel *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLB.reg; +} + +static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((DmacChannel *)hw)->CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHPRILVL.reg; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHEVCTRL.reg; +} + +static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHSTATUS.reg; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; +} + +static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; +} + +static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_E54_H_INCLUDED */ +#endif /* _SAME54_DMAC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_dsu_e54.h b/bsp/microchip/same54/bsp/hri/hri_dsu_e54.h new file mode 100644 index 0000000000..b192276ff4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_dsu_e54.h @@ -0,0 +1,1256 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DSU_COMPONENT_ +#ifndef _HRI_DSU_E54_H_INCLUDED_ +#define _HRI_DSU_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cfg_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_ETBRAMEN; + tmp |= value << DSU_CFG_ETBRAMEN_Pos; + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_LQOS_Msk; + tmp |= DSU_CFG_LQOS(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; + tmp |= DSU_CFG_DCCDMALEVEL(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) +{ + return ((Dsu *)hw)->CFG.reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_E54_H_INCLUDED */ +#endif /* _SAME54_DSU_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_e54.h b/bsp/microchip/same54/bsp/hri/hri_e54.h new file mode 100644 index 0000000000..46e77ca0d3 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_e54.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief SAM E54 HRI top-level header file + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HRI_E54_H_INCLUDED_ +#define _HRI_E54_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_E54_H_INCLUDED_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_eic_e54.h b/bsp/microchip/same54/bsp/hri/hri_eic_e54.h new file mode 100644 index 0000000000..f86e452c04 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_eic_e54.h @@ -0,0 +1,1838 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EIC_COMPONENT_ +#ifndef _HRI_EIC_E54_H_INCLUDED_ +#define _HRI_EIC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_debouncen_reg_t; +typedef uint32_t hri_eic_dprescaler_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_pinstate_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->PINSTATE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) +{ + return ((Eic *)hw)->PINSTATE.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, + hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; + tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); + ((Eic *)hw)->DEBOUNCEN.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) +{ + return ((Eic *)hw)->DEBOUNCEN.reg; +} + +static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES0; + tmp |= value << EIC_DPRESCALER_STATES0_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES1; + tmp |= value << EIC_DPRESCALER_STATES1_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_TICKON; + tmp |= value << EIC_DPRESCALER_TICKON_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; + tmp |= EIC_DPRESCALER_PRESCALER0(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; + tmp |= EIC_DPRESCALER_PRESCALER1(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) +{ + return ((Eic *)hw)->DPRESCALER.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_E54_H_INCLUDED */ +#endif /* _SAME54_EIC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_evsys_e54.h b/bsp/microchip/same54/bsp/hri/hri_evsys_e54.h new file mode 100644 index 0000000000..cd4a98a405 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_evsys_e54.h @@ -0,0 +1,1707 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_E54_H_INCLUDED_ +#define _HRI_EVSYS_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_intpend_reg_t; +typedef uint32_t hri_evsys_busych_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_intstatus_reg_t; +typedef uint32_t hri_evsys_readyusr_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsyschannel_channel_reg_t; +typedef uint8_t hri_evsys_chintenset_reg_t; +typedef uint8_t hri_evsys_chintflag_reg_t; +typedef uint8_t hri_evsys_chstatus_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; +typedef uint8_t hri_evsys_prictrl_reg_t; +typedef uint8_t hri_evsyschannel_chintenset_reg_t; +typedef uint8_t hri_evsyschannel_chintflag_reg_t; +typedef uint8_t hri_evsyschannel_chstatus_reg_t; + +static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, + hri_evsys_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTSTATUS.reg; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) +{ + return ((Evsys *)hw)->BUSYCH.reg; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->READYUSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) +{ + return ((Evsys *)hw)->READYUSR.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_RREN; + tmp |= value << EVSYS_PRICTRL_RREN_Pos; + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_PRI_Msk; + tmp |= EVSYS_PRICTRL_PRI(data); + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) +{ + return ((Evsys *)hw)->PRICTRL.reg; +} + +static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_OVR; + tmp |= value << EVSYS_INTPEND_OVR_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_EVD; + tmp |= value << EVSYS_INTPEND_EVD_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_READY; + tmp |= value << EVSYS_INTPEND_READY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_BUSY; + tmp |= value << EVSYS_INTPEND_BUSY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_ID_Msk; + tmp |= EVSYS_INTPEND_ID(data); + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTPEND.reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = data; + ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHANNEL.reg; +} + +static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t data) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_E54_H_INCLUDED */ +#endif /* _SAME54_EVSYS_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_freqm_e54.h b/bsp/microchip/same54/bsp/hri/hri_freqm_e54.h new file mode 100644 index 0000000000..8cbc484f66 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_freqm_e54.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_E54_H_INCLUDED_ +#define _HRI_FREQM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_E54_H_INCLUDED */ +#endif /* _SAME54_FREQM_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_gclk_e54.h b/bsp/microchip/same54/bsp/hri/hri_gclk_e54.h new file mode 100644 index 0000000000..f83af2a0ce --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_gclk_e54.h @@ -0,0 +1,805 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_E54_H_INCLUDED_ +#define _HRI_GCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_E54_H_INCLUDED */ +#endif /* _SAME54_GCLK_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_gmac_e54.h b/bsp/microchip/same54/bsp/hri/hri_gmac_e54.h new file mode 100644 index 0000000000..287506100e --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_gmac_e54.h @@ -0,0 +1,3766 @@ +/** + * \file + * + * \brief SAM GMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GMAC_COMPONENT_ +#ifndef _HRI_GMAC_E54_H_INCLUDED_ +#define _HRI_GMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) +#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GMAC_CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gmac_ae_reg_t; +typedef uint32_t hri_gmac_bcfr_reg_t; +typedef uint32_t hri_gmac_bcft_reg_t; +typedef uint32_t hri_gmac_bfr64_reg_t; +typedef uint32_t hri_gmac_bft64_reg_t; +typedef uint32_t hri_gmac_cse_reg_t; +typedef uint32_t hri_gmac_dcfgr_reg_t; +typedef uint32_t hri_gmac_dtf_reg_t; +typedef uint32_t hri_gmac_ec_reg_t; +typedef uint32_t hri_gmac_efrn_reg_t; +typedef uint32_t hri_gmac_efrsh_reg_t; +typedef uint32_t hri_gmac_efrsl_reg_t; +typedef uint32_t hri_gmac_eftn_reg_t; +typedef uint32_t hri_gmac_eftsh_reg_t; +typedef uint32_t hri_gmac_eftsl_reg_t; +typedef uint32_t hri_gmac_fcse_reg_t; +typedef uint32_t hri_gmac_fr_reg_t; +typedef uint32_t hri_gmac_ft_reg_t; +typedef uint32_t hri_gmac_gtbft1518_reg_t; +typedef uint32_t hri_gmac_hrb_reg_t; +typedef uint32_t hri_gmac_hrt_reg_t; +typedef uint32_t hri_gmac_ihce_reg_t; +typedef uint32_t hri_gmac_imr_reg_t; +typedef uint32_t hri_gmac_ipgs_reg_t; +typedef uint32_t hri_gmac_isr_reg_t; +typedef uint32_t hri_gmac_jr_reg_t; +typedef uint32_t hri_gmac_lc_reg_t; +typedef uint32_t hri_gmac_lffe_reg_t; +typedef uint32_t hri_gmac_man_reg_t; +typedef uint32_t hri_gmac_mcf_reg_t; +typedef uint32_t hri_gmac_mfr_reg_t; +typedef uint32_t hri_gmac_mft_reg_t; +typedef uint32_t hri_gmac_ncfgr_reg_t; +typedef uint32_t hri_gmac_ncr_reg_t; +typedef uint32_t hri_gmac_nsc_reg_t; +typedef uint32_t hri_gmac_nsr_reg_t; +typedef uint32_t hri_gmac_ofr_reg_t; +typedef uint32_t hri_gmac_orhi_reg_t; +typedef uint32_t hri_gmac_orlo_reg_t; +typedef uint32_t hri_gmac_othi_reg_t; +typedef uint32_t hri_gmac_otlo_reg_t; +typedef uint32_t hri_gmac_pefrn_reg_t; +typedef uint32_t hri_gmac_pefrsh_reg_t; +typedef uint32_t hri_gmac_pefrsl_reg_t; +typedef uint32_t hri_gmac_peftn_reg_t; +typedef uint32_t hri_gmac_peftsh_reg_t; +typedef uint32_t hri_gmac_peftsl_reg_t; +typedef uint32_t hri_gmac_pfr_reg_t; +typedef uint32_t hri_gmac_pft_reg_t; +typedef uint32_t hri_gmac_rbqb_reg_t; +typedef uint32_t hri_gmac_rjfml_reg_t; +typedef uint32_t hri_gmac_rlpiti_reg_t; +typedef uint32_t hri_gmac_rlpitr_reg_t; +typedef uint32_t hri_gmac_roe_reg_t; +typedef uint32_t hri_gmac_rpq_reg_t; +typedef uint32_t hri_gmac_rpsf_reg_t; +typedef uint32_t hri_gmac_rre_reg_t; +typedef uint32_t hri_gmac_rse_reg_t; +typedef uint32_t hri_gmac_rsr_reg_t; +typedef uint32_t hri_gmac_sab_reg_t; +typedef uint32_t hri_gmac_samb1_reg_t; +typedef uint32_t hri_gmac_samt1_reg_t; +typedef uint32_t hri_gmac_sat_reg_t; +typedef uint32_t hri_gmac_scf_reg_t; +typedef uint32_t hri_gmac_sch_reg_t; +typedef uint32_t hri_gmac_scl_reg_t; +typedef uint32_t hri_gmac_svlan_reg_t; +typedef uint32_t hri_gmac_ta_reg_t; +typedef uint32_t hri_gmac_tbfr1023_reg_t; +typedef uint32_t hri_gmac_tbfr127_reg_t; +typedef uint32_t hri_gmac_tbfr1518_reg_t; +typedef uint32_t hri_gmac_tbfr255_reg_t; +typedef uint32_t hri_gmac_tbfr511_reg_t; +typedef uint32_t hri_gmac_tbft1023_reg_t; +typedef uint32_t hri_gmac_tbft127_reg_t; +typedef uint32_t hri_gmac_tbft1518_reg_t; +typedef uint32_t hri_gmac_tbft255_reg_t; +typedef uint32_t hri_gmac_tbft511_reg_t; +typedef uint32_t hri_gmac_tbqb_reg_t; +typedef uint32_t hri_gmac_tce_reg_t; +typedef uint32_t hri_gmac_ti_reg_t; +typedef uint32_t hri_gmac_tidm_reg_t; +typedef uint32_t hri_gmac_tisubn_reg_t; +typedef uint32_t hri_gmac_tlpiti_reg_t; +typedef uint32_t hri_gmac_tlpitr_reg_t; +typedef uint32_t hri_gmac_tmxbfr_reg_t; +typedef uint32_t hri_gmac_tn_reg_t; +typedef uint32_t hri_gmac_tpfcp_reg_t; +typedef uint32_t hri_gmac_tpq_reg_t; +typedef uint32_t hri_gmac_tpsf_reg_t; +typedef uint32_t hri_gmac_tsh_reg_t; +typedef uint32_t hri_gmac_tsl_reg_t; +typedef uint32_t hri_gmac_tsr_reg_t; +typedef uint32_t hri_gmac_tssn_reg_t; +typedef uint32_t hri_gmac_tsssl_reg_t; +typedef uint32_t hri_gmac_tur_reg_t; +typedef uint32_t hri_gmac_uce_reg_t; +typedef uint32_t hri_gmac_ufr_reg_t; +typedef uint32_t hri_gmac_ur_reg_t; +typedef uint32_t hri_gmac_wol_reg_t; +typedef uint32_t hri_gmacsa_sab_reg_t; +typedef uint32_t hri_gmacsa_sat_reg_t; + +static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAB.reg; +} + +static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAT.reg; +} + +static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; +} + +static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; +} + +static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; +} + +static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; +} + +static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; + } +} + +static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; +} + +static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; +} + +static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; + } +} + +static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; +} + +static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; +} + +static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; + } +} + +static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; +} + +static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; +} + +static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; + } +} + +static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; +} + +static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; +} + +static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; +} + +static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; + } +} + +static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; +} + +static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; +} + +static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; +} + +static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; + } +} + +static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; +} + +static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; +} + +static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; +} + +static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; + } +} + +static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; +} + +static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; +} + +static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; +} + +static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; +} + +static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; +} + +static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; + } +} + +static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; +} + +static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; +} + +static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; +} + +static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; + } +} + +static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; +} + +static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; +} + +static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; +} + +static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; + } +} + +static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; +} + +static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; +} + +static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; +} + +static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; + } +} + +static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; +} + +static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; +} + +static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; +} + +static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; + } +} + +static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; +} + +static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; +} + +static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; +} + +static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; + } +} + +static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; +} + +static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; +} + +static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; + } +} + +static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; +} + +static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; +} + +static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; +} + +static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; + } +} + +static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; +} + +static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; +} + +static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; + } +} + +static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; +} + +static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; +} + +static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; +} + +static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; + } +} + +static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; +} + +static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; +} + +static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; +} + +static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; +} + +static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; +} + +static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; +} + +static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; +} + +static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; +} + +static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; +} + +static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; +} + +static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; +} + +static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; + } +} + +static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; +} + +static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; +} + +static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; +} + +static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; + } +} + +static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; +} + +static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; +} + +static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; +} + +static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; + } +} + +static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; +} + +static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IER.reg = mask; +} + +static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) +{ + return ((Gmac *)hw)->IMR.reg; +} + +static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) +{ + ((Gmac *)hw)->IER.reg = data; + ((Gmac *)hw)->IDR.reg = ~data; +} + +static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IDR.reg = mask; +} + +static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; +} + +static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSR.reg; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPQ.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPQ.reg; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSH.reg; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSH.reg; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSH.reg; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSH.reg; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTLO.reg; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTHI.reg; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) +{ + return ((Gmac *)hw)->FT.reg; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFT.reg; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFT.reg; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFT.reg; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFT64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFT64.reg; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT127.reg; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT255.reg; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT511.reg; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1023.reg; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1518.reg; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, + hri_gmac_gtbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GTBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GTBFT1518.reg; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TUR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TUR.reg; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCF.reg; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->MCF.reg; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) +{ + return ((Gmac *)hw)->EC.reg; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) +{ + return ((Gmac *)hw)->LC.reg; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DTF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) +{ + return ((Gmac *)hw)->DTF.reg; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->CSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->CSE.reg; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORLO.reg; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORHI.reg; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) +{ + return ((Gmac *)hw)->FR.reg; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFR.reg; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFR.reg; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFR.reg; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFR64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFR64.reg; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR127.reg; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR255.reg; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR511.reg; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1023.reg; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1518.reg; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TMXBFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TMXBFR.reg; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UFR.reg; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->OFR.reg; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->JR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) +{ + return ((Gmac *)hw)->JR.reg; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FCSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->FCSE.reg; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LFFE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) +{ + return ((Gmac *)hw)->LFFE.reg; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSE.reg; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->AE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) +{ + return ((Gmac *)hw)->AE.reg; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RRE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RRE.reg; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ROE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) +{ + return ((Gmac *)hw)->ROE.reg; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IHCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->IHCE.reg; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->TCE.reg; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->UCE.reg; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSL.reg; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTN.reg; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSL.reg; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRN.reg; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSL.reg; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTN.reg; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSL.reg; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRN.reg; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITR.reg; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITI.reg; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITR.reg; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITI.reg; +} + +static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCR.reg; +} + +static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCFGR.reg; +} + +static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UR.reg; +} + +static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->DCFGR.reg; +} + +static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSR.reg; +} + +static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->RBQB.reg; +} + +static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBQB.reg; +} + +static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSR.reg; +} + +static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) +{ + return ((Gmac *)hw)->ISR.reg; +} + +static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->MAN.reg; +} + +static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPQ.reg; +} + +static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPSF.reg; +} + +static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPSF.reg; +} + +static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RJFML.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) +{ + return ((Gmac *)hw)->RJFML.reg; +} + +static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRB.reg; +} + +static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRT.reg; +} + +static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TIDM[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->TIDM[index].reg; +} + +static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->WOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) +{ + return ((Gmac *)hw)->WOL.reg; +} + +static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IPGS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) +{ + return ((Gmac *)hw)->IPGS.reg; +} + +static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SVLAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->SVLAN.reg; +} + +static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPFCP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPFCP.reg; +} + +static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMB1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMB1.reg; +} + +static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMT1.reg; +} + +static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSC.reg; +} + +static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCL.reg; +} + +static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCH.reg; +} + +static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TISUBN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TISUBN.reg; +} + +static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSH.reg; +} + +static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSSL.reg; +} + +static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSN.reg; +} + +static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSL.reg; +} + +static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TN.reg; +} + +static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TI.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TI.reg; +} + +static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TA.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GMAC_E54_H_INCLUDED */ +#endif /* _SAME54_GMAC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_hmatrixb_e54.h b/bsp/microchip/same54/bsp/hri/hri_hmatrixb_e54.h new file mode 100644 index 0000000000..2ef06845df --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_hmatrixb_e54.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ +#define _HRI_HMATRIXB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ +#endif /* _SAME54_HMATRIXB_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_i2s_e54.h b/bsp/microchip/same54/bsp/hri/hri_i2s_e54.h new file mode 100644 index 0000000000..42b88dc095 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_i2s_e54.h @@ -0,0 +1,3032 @@ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_I2S_COMPONENT_ +#ifndef _HRI_I2S_E54_H_INCLUDED_ +#define _HRI_I2S_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_rxctrl_reg_t; +typedef uint32_t hri_i2s_rxdata_reg_t; +typedef uint32_t hri_i2s_txctrl_reg_t; +typedef uint32_t hri_i2s_txdata_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return ((I2s *)hw)->RXDATA.reg; +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_TXEN; + tmp |= value << I2S_CTRLA_TXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_RXEN; + tmp |= value << I2S_CTRLA_RXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXSAME; + tmp |= value << I2S_TXCTRL_TXSAME_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTADJ; + tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_WORDADJ; + tmp |= value << I2S_TXCTRL_WORDADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_BITREV; + tmp |= value << I2S_TXCTRL_BITREV_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS0; + tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS1; + tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS2; + tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS3; + tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS4; + tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS5; + tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS6; + tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS7; + tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_MONO; + tmp |= value << I2S_TXCTRL_MONO_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DMA; + tmp |= value << I2S_TXCTRL_DMA_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; + tmp |= I2S_TXCTRL_TXDEFAULT(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DATASIZE_Msk; + tmp |= I2S_TXCTRL_DATASIZE(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_EXTEND_Msk; + tmp |= I2S_TXCTRL_EXTEND(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->TXCTRL.reg; +} + +static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_CLKSEL; + tmp |= value << I2S_RXCTRL_CLKSEL_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTADJ; + tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_WORDADJ; + tmp |= value << I2S_RXCTRL_WORDADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_BITREV; + tmp |= value << I2S_RXCTRL_BITREV_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS0; + tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS1; + tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS2; + tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS3; + tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS4; + tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS5; + tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS6; + tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS7; + tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_MONO; + tmp |= value << I2S_RXCTRL_MONO_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DMA; + tmp |= value << I2S_RXCTRL_DMA_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_RXLOOP; + tmp |= value << I2S_RXCTRL_RXLOOP_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SERMODE_Msk; + tmp |= I2S_RXCTRL_SERMODE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DATASIZE_Msk; + tmp |= I2S_RXCTRL_DATASIZE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_EXTEND_Msk; + tmp |= I2S_RXCTRL_EXTEND(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->RXCTRL.reg; +} + +static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXDATA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_E54_H_INCLUDED */ +#endif /* _SAME54_I2S_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_icm_e54.h b/bsp/microchip/same54/bsp/hri/hri_icm_e54.h new file mode 100644 index 0000000000..374caa4f43 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_icm_e54.h @@ -0,0 +1,761 @@ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ICM_COMPONENT_ +#ifndef _HRI_ICM_E54_H_INCLUDED_ +#define _HRI_ICM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; +typedef uint32_t hri_icmdescriptor_raddr_reg_t; +typedef uint32_t hri_icmdescriptor_rcfg_reg_t; +typedef uint32_t hri_icmdescriptor_rctrl_reg_t; +typedef uint32_t hri_icmdescriptor_rnext_reg_t; + +static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, + hri_icmdescriptor_raddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RADDR.reg; +} + +static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, + hri_icmdescriptor_rcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCFG.reg; +} + +static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, + hri_icmdescriptor_rctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCTRL.reg; +} + +static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, + hri_icmdescriptor_rnext_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RNEXT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RNEXT.reg; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; + } else { + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->IMR.reg; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = data; + ((Icm *)hw)->IDR.reg = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = mask; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->SR.reg; +} + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ISR.reg; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->UASR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->UASR.reg; +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->CFG.reg; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->DSCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->DSCR.reg; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->HASH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->HASH.reg; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->UIHVAL[index].reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_E54_H_INCLUDED */ +#endif /* _SAME54_ICM_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_mclk_e54.h b/bsp/microchip/same54/bsp/hri/hri_mclk_e54.h new file mode 100644 index 0000000000..7e3963b192 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_mclk_e54.h @@ -0,0 +1,3556 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_E54_H_INCLUDED_ +#define _HRI_MCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_hsdiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->HSDIV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->HSDIV.reg; +} + +static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_DIV_Msk; + tmp |= MCLK_CPUDIV_DIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIX; + tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CMCC; + tmp |= value << MCLK_AHBMASK_CMCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_BKUPRAM; + tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI; + tmp |= value << MCLK_AHBMASK_QSPI_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_GMAC; + tmp |= value << MCLK_AHBMASK_GMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC0; + tmp |= value << MCLK_AHBMASK_SDHC0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC1; + tmp |= value << MCLK_AHBMASK_SDHC1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_ICM; + tmp |= value << MCLK_AHBMASK_ICM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PUKCC; + tmp |= value << MCLK_AHBMASK_PUKCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI_2X; + tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM0; + tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM1; + tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC0; + tmp |= value << MCLK_APBAMASK_TC0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC1; + tmp |= value << MCLK_APBAMASK_TC1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIX; + tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_EVSYS; + tmp |= value << MCLK_APBBMASK_EVSYS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM2; + tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM3; + tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC0; + tmp |= value << MCLK_APBBMASK_TCC0_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC1; + tmp |= value << MCLK_APBBMASK_TCC1_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC2; + tmp |= value << MCLK_APBBMASK_TC2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC3; + tmp |= value << MCLK_APBBMASK_TC3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_RAMECC; + tmp |= value << MCLK_APBBMASK_RAMECC_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_GMAC; + tmp |= value << MCLK_APBCMASK_GMAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC3; + tmp |= value << MCLK_APBCMASK_TCC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC5; + tmp |= value << MCLK_APBCMASK_TC5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PDEC; + tmp |= value << MCLK_APBCMASK_PDEC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ICM; + tmp |= value << MCLK_APBCMASK_ICM_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_QSPI; + tmp |= value << MCLK_APBCMASK_QSPI_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM4; + tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM6; + tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM7; + tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TCC4; + tmp |= value << MCLK_APBDMASK_TCC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC6; + tmp |= value << MCLK_APBDMASK_TC6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC7; + tmp |= value << MCLK_APBDMASK_TC7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC0; + tmp |= value << MCLK_APBDMASK_ADC0_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC1; + tmp |= value << MCLK_APBDMASK_ADC1_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_DAC; + tmp |= value << MCLK_APBDMASK_DAC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_I2S; + tmp |= value << MCLK_APBDMASK_I2S_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PCC; + tmp |= value << MCLK_APBDMASK_PCC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_E54_H_INCLUDED */ +#endif /* _SAME54_MCLK_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_nvmctrl_e54.h b/bsp/microchip/same54/bsp/hri/hri_nvmctrl_e54.h new file mode 100644 index 0000000000..12d4022382 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_nvmctrl_e54.h @@ -0,0 +1,1618 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ +#define _HRI_NVMCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_ctrlb_reg_t; +typedef uint16_t hri_nvmctrl_intenset_reg_t; +typedef uint16_t hri_nvmctrl_intflag_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_eccerr_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata_reg_t; +typedef uint32_t hri_nvmctrl_runlock_reg_t; +typedef uint32_t hri_nvmctrl_seestat_reg_t; +typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; +typedef uint8_t hri_nvmctrl_seecfg_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; +} + +static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; +} + +static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; +} + +static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; + } +} + +static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; +} + +static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, + hri_nvmctrl_status_reg_t mask) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->RUNLOCK.reg; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) +{ + return ((Nvmctrl *)hw)->PBLDATA[index].reg; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ECCERR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ECCERR.reg; +} + +static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->SEESTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEESTAT.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AUTOWS; + tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_SUSPEN; + tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS0; + tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS1; + tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; + tmp |= NVMCTRL_CTRLA_WMODE(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_PRM_Msk; + tmp |= NVMCTRL_CTRLA_PRM(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_RWS_Msk; + tmp |= NVMCTRL_CTRLA_RWS(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; + tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; + tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, + hri_nvmctrl_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->DBGCTRL.reg; +} + +static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_WMODE; + tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_APRDIS; + tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEECFG.reg; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_NVMCTRL_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_osc32kctrl_e54.h b/bsp/microchip/same54/bsp/hri/hri_osc32kctrl_e54.h new file mode 100644 index 0000000000..2eabbca0b1 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_osc32kctrl_e54.h @@ -0,0 +1,1199 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ +#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; + tmp |= OSC32KCTRL_XOSC32K_CGM(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_oscctrl_e54.h b/bsp/microchip/same54/bsp/hri/hri_oscctrl_e54.h new file mode 100644 index 0000000000..f331410945 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_oscctrl_e54.h @@ -0,0 +1,4441 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ +#define _HRI_OSCCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_dpllstatus_reg_t; +typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint32_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; +typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; +typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_dfllctrla_reg_t; +typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; + +static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((OscctrlDpll *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) + >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t +hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO0; + tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO1; + tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENALC; + tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IMULT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; + tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Oscctrl *)hw)->XOSCCTRL[index].reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, + hri_oscctrl_dfllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_MODE; + tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; + tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; + tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, + hri_oscctrl_dfllctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; + tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSCCTRL_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_pac_e54.h b/bsp/microchip/same54/bsp/hri/hri_pac_e54.h new file mode 100644 index 0000000000..896313541c --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_pac_e54.h @@ -0,0 +1,1514 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PAC_COMPONENT_ +#ifndef _HRI_PAC_E54_H_INCLUDED_ +#define _HRI_PAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; +} + +static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; +} + +static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; +} + +static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; +} + +static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; +} + +static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; +} + +static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; +} + +static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; +} + +static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; +} + +static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; +} + +static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; +} + +static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; +} + +static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; +} + +static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; +} + +static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; +} + +static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; +} + +static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; +} + +static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; +} + +static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; +} + +static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; +} + +static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; +} + +static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; +} + +static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; +} + +static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; +} + +static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; +} + +static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_E54_H_INCLUDED */ +#endif /* _SAME54_PAC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_pcc_e54.h b/bsp/microchip/same54/bsp/hri/hri_pcc_e54.h new file mode 100644 index 0000000000..42a560001d --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_pcc_e54.h @@ -0,0 +1,298 @@ +/** + * \file + * + * \brief SAM PCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PCC_COMPONENT_ +#ifndef _HRI_PCC_E54_H_INCLUDED_ +#define _HRI_PCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PCC_CRITICAL_SECTIONS) +#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PCC_CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pcc_imr_reg_t; +typedef uint32_t hri_pcc_isr_reg_t; +typedef uint32_t hri_pcc_mr_reg_t; +typedef uint32_t hri_pcc_rhr_reg_t; +typedef uint32_t hri_pcc_wpmr_reg_t; +typedef uint32_t hri_pcc_wpsr_reg_t; + +static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; +} + +static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; +} + +static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; + } +} + +static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; +} + +static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; +} + +static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; +} + +static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; + } +} + +static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; +} + +static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IER.reg = mask; +} + +static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->IMR.reg; +} + +static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) +{ + ((Pcc *)hw)->IER.reg = data; + ((Pcc *)hw)->IDR.reg = ~data; +} + +static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IDR.reg = mask; +} + +static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; +} + +static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; +} + +static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) +{ + return ((Pcc *)hw)->ISR.reg; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->RHR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) +{ + return ((Pcc *)hw)->RHR.reg; +} + +static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPSR.reg; +} + +static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->MR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) +{ + return ((Pcc *)hw)->MR.reg; +} + +static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPMR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PCC_E54_H_INCLUDED */ +#endif /* _SAME54_PCC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_pdec_e54.h b/bsp/microchip/same54/bsp/hri/hri_pdec_e54.h new file mode 100644 index 0000000000..ec7ce303e0 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_pdec_e54.h @@ -0,0 +1,2684 @@ +/** + * \file + * + * \brief SAM PDEC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PDEC_COMPONENT_ +#ifndef _HRI_PDEC_E54_H_INCLUDED_ +#define _HRI_PDEC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) +#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PDEC_CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pdec_evctrl_reg_t; +typedef uint16_t hri_pdec_status_reg_t; +typedef uint32_t hri_pdec_cc_reg_t; +typedef uint32_t hri_pdec_ccbuf_reg_t; +typedef uint32_t hri_pdec_count_reg_t; +typedef uint32_t hri_pdec_ctrla_reg_t; +typedef uint32_t hri_pdec_syncbusy_reg_t; +typedef uint8_t hri_pdec_ctrlbset_reg_t; +typedef uint8_t hri_pdec_dbgctrl_reg_t; +typedef uint8_t hri_pdec_filter_reg_t; +typedef uint8_t hri_pdec_filterbuf_reg_t; +typedef uint8_t hri_pdec_intenset_reg_t; +typedef uint8_t hri_pdec_intflag_reg_t; +typedef uint8_t hri_pdec_presc_reg_t; +typedef uint8_t hri_pdec_prescbuf_reg_t; + +static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + while (((Pdec *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + return ((Pdec *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTFLAG.reg; +} + +static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + ((Pdec *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; +} + +static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; + } else { + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; + } +} + +static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; +} + +static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); + ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); +} + +static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLBSET.reg; +} + +static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = data; + ((Pdec *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; +} + +static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; +} + +static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; + } +} + +static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; +} + +static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; +} + +static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; +} + +static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; + } +} + +static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; +} + +static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; +} + +static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; +} + +static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; + } +} + +static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; +} + +static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; +} + +static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; +} + +static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; + } +} + +static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; +} + +static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; +} + +static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; +} + +static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; + } +} + +static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; +} + +static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; +} + +static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; +} + +static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; + } +} + +static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; +} + +static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENSET.reg = mask; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTENSET.reg; +} + +static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) +{ + ((Pdec *)hw)->INTENSET.reg = data; + ((Pdec *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Pdec *)hw)->SYNCBUSY.reg; +} + +static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ENABLE; + tmp |= value << PDEC_CTRLA_ENABLE_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_RUNSTDBY; + tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ALOCK; + tmp |= value << PDEC_CTRLA_ALOCK_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_SWAP; + tmp |= value << PDEC_CTRLA_SWAP_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PEREN; + tmp |= value << PDEC_CTRLA_PEREN_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN0; + tmp |= value << PDEC_CTRLA_PINEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN1; + tmp |= value << PDEC_CTRLA_PINEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN2; + tmp |= value << PDEC_CTRLA_PINEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN0; + tmp |= value << PDEC_CTRLA_PINVEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN1; + tmp |= value << PDEC_CTRLA_PINVEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN2; + tmp |= value << PDEC_CTRLA_PINVEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MODE_Msk; + tmp |= PDEC_CTRLA_MODE(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_CONF_Msk; + tmp |= PDEC_CTRLA_CONF(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ANGULAR_Msk; + tmp |= PDEC_CTRLA_ANGULAR(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MAXCMP_Msk; + tmp |= PDEC_CTRLA_MAXCMP(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + return ((Pdec *)hw)->CTRLA.reg; +} + +static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_OVFEO; + tmp |= value << PDEC_EVCTRL_OVFEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_ERREO; + tmp |= value << PDEC_EVCTRL_ERREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_DIREO; + tmp |= value << PDEC_EVCTRL_DIREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_VLCEO; + tmp |= value << PDEC_EVCTRL_VLCEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO0; + tmp |= value << PDEC_EVCTRL_MCEO0_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO1; + tmp |= value << PDEC_EVCTRL_MCEO1_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVACT_Msk; + tmp |= PDEC_EVCTRL_EVACT(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVINV_Msk; + tmp |= PDEC_EVCTRL_EVINV(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVEI_Msk; + tmp |= PDEC_EVCTRL_EVEI(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->EVCTRL.reg; +} + +static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= ~PDEC_DBGCTRL_DBGRUN; + tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; + ((Pdec *)hw)->DBGCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->DBGCTRL.reg; +} + +static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= ~PDEC_PRESC_PRESC_Msk; + tmp |= PDEC_PRESC_PRESC(data); + ((Pdec *)hw)->PRESC.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + return ((Pdec *)hw)->PRESC.reg; +} + +static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= ~PDEC_FILTER_FILTER_Msk; + tmp |= PDEC_FILTER_FILTER(data); + ((Pdec *)hw)->FILTER.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + return ((Pdec *)hw)->FILTER.reg; +} + +static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, + hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; + tmp |= PDEC_PRESCBUF_PRESCBUF(data); + ((Pdec *)hw)->PRESCBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->PRESCBUF.reg; +} + +static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, + hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; + tmp |= PDEC_FILTERBUF_FILTERBUF(data); + ((Pdec *)hw)->FILTERBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->FILTERBUF.reg; +} + +static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= ~PDEC_COUNT_COUNT_Msk; + tmp |= PDEC_COUNT_COUNT(data); + ((Pdec *)hw)->COUNT.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + return ((Pdec *)hw)->COUNT.reg; +} + +static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= ~PDEC_CC_CC_Msk; + tmp |= PDEC_CC_CC(data); + ((Pdec *)hw)->CC[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + return ((Pdec *)hw)->CC[index].reg; +} + +static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= ~PDEC_CCBUF_CCBUF_Msk; + tmp |= PDEC_CCBUF_CCBUF(data); + ((Pdec *)hw)->CCBUF[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->CCBUF[index].reg; +} + +static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; +} + +static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; +} + +static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + uint16_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PDEC_E54_H_INCLUDED */ +#endif /* _SAME54_PDEC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_pm_e54.h b/bsp/microchip/same54/bsp/hri/hri_pm_e54.h new file mode 100644 index 0000000000..0b91beef19 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_pm_e54.h @@ -0,0 +1,820 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PM_COMPONENT_ +#ifndef _HRI_PM_E54_H_INCLUDED_ +#define _HRI_PM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_pm_bkupcfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_hibcfg_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; +typedef uint8_t hri_pm_stdbycfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; +} + +static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; +} + +static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; + } +} + +static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_RAMCFG_Msk; + tmp |= PM_STDBYCFG_RAMCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; + tmp |= PM_STDBYCFG_FASTWKUP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_RAMCFG_Msk; + tmp |= PM_HIBCFG_RAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_BRAMCFG_Msk; + tmp |= PM_HIBCFG_BRAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->HIBCFG.reg; +} + +static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; + tmp |= PM_BKUPCFG_BRAMCFG(data); + ((Pm *)hw)->BKUPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->BKUPCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_E54_H_INCLUDED */ +#endif /* _SAME54_PM_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_port_e54.h b/bsp/microchip/same54/bsp/hri/hri_port_e54.h new file mode 100644 index 0000000000..261fcf57d4 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_port_e54.h @@ -0,0 +1,2528 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PORT_COMPONENT_ +#ifndef _HRI_PORT_E54_H_INCLUDED_ +#define _HRI_PORT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_E54_H_INCLUDED */ +#endif /* _SAME54_PORT_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_qspi_e54.h b/bsp/microchip/same54/bsp/hri/hri_qspi_e54.h new file mode 100644 index 0000000000..23742bce48 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_qspi_e54.h @@ -0,0 +1,2058 @@ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_E54_H_INCLUDED_ +#define _HRI_QSPI_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_baud_reg_t; +typedef uint32_t hri_qspi_ctrla_reg_t; +typedef uint32_t hri_qspi_ctrlb_reg_t; +typedef uint32_t hri_qspi_instraddr_reg_t; +typedef uint32_t hri_qspi_instrctrl_reg_t; +typedef uint32_t hri_qspi_instrframe_reg_t; +typedef uint32_t hri_qspi_intenset_reg_t; +typedef uint32_t hri_qspi_intflag_reg_t; +typedef uint32_t hri_qspi_rxdata_reg_t; +typedef uint32_t hri_qspi_scrambctrl_reg_t; +typedef uint32_t hri_qspi_scrambkey_reg_t; +typedef uint32_t hri_qspi_status_reg_t; +typedef uint32_t hri_qspi_txdata_reg_t; + +static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTFLAG.reg; +} + +static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + ((Qspi *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; +} + +static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; +} + +static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; + } +} + +static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; +} + +static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; +} + +static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; +} + +static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; + } +} + +static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; +} + +static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; +} + +static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; +} + +static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; + } +} + +static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; +} + +static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; +} + +static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; +} + +static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; + } +} + +static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; +} + +static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; +} + +static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; +} + +static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; + } +} + +static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; +} + +static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; +} + +static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; +} + +static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; + } +} + +static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; +} + +static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENSET.reg = mask; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTENSET.reg; +} + +static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) +{ + ((Qspi *)hw)->INTENSET.reg = data; + ((Qspi *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENCLR.reg = mask; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) +{ + return ((Qspi *)hw)->RXDATA.reg; +} + +static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; +} + +static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; +} + +static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) +{ + return ((Qspi *)hw)->STATUS.reg; +} + +static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_ENABLE; + tmp |= value << QSPI_CTRLA_ENABLE_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_LASTXFER; + tmp |= value << QSPI_CTRLA_LASTXFER_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLA.reg; +} + +static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_MODE; + tmp |= value << QSPI_CTRLB_MODE_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_LOOPEN; + tmp |= value << QSPI_CTRLB_LOOPEN_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_WDRBT; + tmp |= value << QSPI_CTRLB_WDRBT_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_SMEMREG; + tmp |= value << QSPI_CTRLB_SMEMREG_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_CSMODE_Msk; + tmp |= QSPI_CTRLB_CSMODE(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DATALEN_Msk; + tmp |= QSPI_CTRLB_DATALEN(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYBCT_Msk; + tmp |= QSPI_CTRLB_DLYBCT(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYCS_Msk; + tmp |= QSPI_CTRLB_DLYCS(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLB.reg; +} + +static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPOL; + tmp |= value << QSPI_BAUD_CPOL_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPHA; + tmp |= value << QSPI_BAUD_CPHA_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_BAUD_Msk; + tmp |= QSPI_BAUD_BAUD(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_DLYBS_Msk; + tmp |= QSPI_BAUD_DLYBS(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) +{ + return ((Qspi *)hw)->BAUD.reg; +} + +static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, + hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= ~QSPI_INSTRADDR_ADDR_Msk; + tmp |= QSPI_INSTRADDR_ADDR(data); + ((Qspi *)hw)->INSTRADDR.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRADDR.reg; +} + +static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; + tmp |= QSPI_INSTRCTRL_INSTR(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; + tmp |= QSPI_INSTRCTRL_OPTCODE(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRCTRL.reg; +} + +static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_INSTREN; + tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDREN; + tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; + tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DATAEN; + tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDRLEN; + tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_CRMODE; + tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DDREN; + tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; + tmp |= QSPI_INSTRFRAME_WIDTH(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; + tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; + tmp |= QSPI_INSTRFRAME_TFRTYPE(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; + tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRFRAME.reg; +} + +static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_ENABLE; + tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, + hri_qspi_scrambctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->SCRAMBCTRL.reg; +} + +static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->TXDATA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBKEY.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_E54_H_INCLUDED */ +#endif /* _SAME54_QSPI_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_ramecc_e54.h b/bsp/microchip/same54/bsp/hri/hri_ramecc_e54.h new file mode 100644 index 0000000000..6031cce1cc --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_ramecc_e54.h @@ -0,0 +1,362 @@ +/** + * \file + * + * \brief SAM RAMECC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RAMECC_COMPONENT_ +#ifndef _HRI_RAMECC_E54_H_INCLUDED_ +#define _HRI_RAMECC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) +#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RAMECC_CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ramecc_erraddr_reg_t; +typedef uint8_t hri_ramecc_dbgctrl_reg_t; +typedef uint8_t hri_ramecc_intenset_reg_t; +typedef uint8_t hri_ramecc_intflag_reg_t; +typedef uint8_t hri_ramecc_status_reg_t; + +static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; +} + +static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + ((Ramecc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; +} + +static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; + } +} + +static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; +} + +static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; +} + +static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; + } +} + +static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; +} + +static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENSET.reg = mask; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTENSET.reg; +} + +static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) +{ + ((Ramecc *)hw)->INTENSET.reg = data; + ((Ramecc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) +{ + return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) +{ + return ((Ramecc *)hw)->STATUS.reg; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, + hri_ramecc_erraddr_reg_t mask) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ramecc *)hw)->ERRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; +} + +static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCDIS; + tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCELOG; + tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg = data; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ramecc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RAMECC_E54_H_INCLUDED */ +#endif /* _SAME54_RAMECC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_rstc_e54.h b/bsp/microchip/same54/bsp/hri/hri_rstc_e54.h new file mode 100644 index 0000000000..bf5592a9d6 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_rstc_e54.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_E54_H_INCLUDED_ +#define _HRI_RSTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_E54_H_INCLUDED */ +#endif /* _SAME54_RSTC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_rtc_e54.h b/bsp/microchip/same54/bsp/hri/hri_rtc_e54.h new file mode 100644 index 0000000000..2f2fa3b414 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_rtc_e54.h @@ -0,0 +1,10139 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RTC_COMPONENT_ +#ifndef _HRI_RTC_E54_H_INCLUDED_ +#define _HRI_RTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_bkup_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtc_tampctrl_reg_t; +typedef uint32_t hri_rtc_tampid_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP2EN; + tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP2EN; + tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP2EN; + tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_E54_H_INCLUDED */ +#endif /* _SAME54_RTC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_sdhc_e54.h b/bsp/microchip/same54/bsp/hri/hri_sdhc_e54.h new file mode 100644 index 0000000000..0b7f609e18 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_sdhc_e54.h @@ -0,0 +1,7477 @@ +/** + * \file + * + * \brief SAM SDHC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SDHC_COMPONENT_ +#ifndef _HRI_SDHC_E54_H_INCLUDED_ +#define _HRI_SDHC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) +#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDHC_CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdhc_acesr_reg_t; +typedef uint16_t hri_sdhc_bcr_reg_t; +typedef uint16_t hri_sdhc_bsr_reg_t; +typedef uint16_t hri_sdhc_ccr_reg_t; +typedef uint16_t hri_sdhc_cr_reg_t; +typedef uint16_t hri_sdhc_eisier_reg_t; +typedef uint16_t hri_sdhc_eister_reg_t; +typedef uint16_t hri_sdhc_eistr_reg_t; +typedef uint16_t hri_sdhc_feraces_reg_t; +typedef uint16_t hri_sdhc_fereis_reg_t; +typedef uint16_t hri_sdhc_hc2r_reg_t; +typedef uint16_t hri_sdhc_hcvr_reg_t; +typedef uint16_t hri_sdhc_nisier_reg_t; +typedef uint16_t hri_sdhc_nister_reg_t; +typedef uint16_t hri_sdhc_nistr_reg_t; +typedef uint16_t hri_sdhc_pvr_reg_t; +typedef uint16_t hri_sdhc_sisr_reg_t; +typedef uint16_t hri_sdhc_tmr_reg_t; +typedef uint32_t hri_sdhc_acr_reg_t; +typedef uint32_t hri_sdhc_arg1r_reg_t; +typedef uint32_t hri_sdhc_asar_reg_t; +typedef uint32_t hri_sdhc_bdpr_reg_t; +typedef uint32_t hri_sdhc_ca0r_reg_t; +typedef uint32_t hri_sdhc_ca1r_reg_t; +typedef uint32_t hri_sdhc_cacr_reg_t; +typedef uint32_t hri_sdhc_cc2r_reg_t; +typedef uint32_t hri_sdhc_mccar_reg_t; +typedef uint32_t hri_sdhc_psr_reg_t; +typedef uint32_t hri_sdhc_rr_reg_t; +typedef uint32_t hri_sdhc_ssar_reg_t; +typedef uint8_t hri_sdhc_aesr_reg_t; +typedef uint8_t hri_sdhc_bgcr_reg_t; +typedef uint8_t hri_sdhc_dbgr_reg_t; +typedef uint8_t hri_sdhc_hc1r_reg_t; +typedef uint8_t hri_sdhc_mc1r_reg_t; +typedef uint8_t hri_sdhc_mc2r_reg_t; +typedef uint8_t hri_sdhc_pcr_reg_t; +typedef uint8_t hri_sdhc_srr_reg_t; +typedef uint8_t hri_sdhc_tcr_reg_t; +typedef uint8_t hri_sdhc_wcr_reg_t; + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->RR[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->RR[index].reg; +} + +static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; +} + +static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; +} + +static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PSR.reg; +} + +static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; +} + +static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->ACESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACESR.reg; +} + +static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA0R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA0R.reg; +} + +static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA1R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA1R.reg; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->MCCAR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MCCAR.reg; +} + +static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->AESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->AESR.reg; +} + +static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->SISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SISR.reg; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HCVR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HCVR.reg; +} + +static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_ADDR_Msk; + tmp |= SDHC_SSAR_ADDR(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; + tmp |= SDHC_SSAR_CMD23_ARG2(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; + tmp |= SDHC_BSR_BLOCKSIZE(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BOUNDARY_Msk; + tmp |= SDHC_BSR_BOUNDARY(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BSR.reg; +} + +static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= ~SDHC_BCR_BCNT_Msk; + tmp |= SDHC_BCR_BCNT(data); + ((Sdhc *)hw)->BCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BCR.reg; +} + +static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= ~SDHC_ARG1R_ARG_Msk; + tmp |= SDHC_ARG1R_ARG(data); + ((Sdhc *)hw)->ARG1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ARG1R.reg; +} + +static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DMAEN; + tmp |= value << SDHC_TMR_DMAEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_BCEN; + tmp |= value << SDHC_TMR_BCEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DTDSEL; + tmp |= value << SDHC_TMR_DTDSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_MSBSEL; + tmp |= value << SDHC_TMR_MSBSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_ACMDEN_Msk; + tmp |= SDHC_TMR_ACMDEN(data); + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TMR.reg; +} + +static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDCCEN; + tmp |= value << SDHC_CR_CMDCCEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDICEN; + tmp |= value << SDHC_CR_CMDICEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_DPSEL; + tmp |= value << SDHC_CR_DPSEL_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_RESPTYP_Msk; + tmp |= SDHC_CR_RESPTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDTYP_Msk; + tmp |= SDHC_CR_CMDTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDIDX_Msk; + tmp |= SDHC_CR_CMDIDX(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CR.reg; +} + +static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= ~SDHC_BDPR_BUFDATA_Msk; + tmp |= SDHC_BDPR_BUFDATA(data); + ((Sdhc *)hw)->BDPR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BDPR.reg; +} + +static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_LEDCTRL; + tmp |= value << SDHC_HC1R_LEDCTRL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DW; + tmp |= value << SDHC_HC1R_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_HSEN; + tmp |= value << SDHC_HC1R_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDTL; + tmp |= value << SDHC_HC1R_CARDDTL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDSEL; + tmp |= value << SDHC_HC1R_CARDDSEL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DMASEL_Msk; + tmp |= SDHC_HC1R_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBPWR; + tmp |= value << SDHC_PCR_SDBPWR_Pos; + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBVSEL_Msk; + tmp |= SDHC_PCR_SDBVSEL(data); + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PCR.reg; +} + +static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_STPBGR; + tmp |= value << SDHC_BGCR_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_CONTR; + tmp |= value << SDHC_BGCR_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_RWCTRL; + tmp |= value << SDHC_BGCR_RWCTRL_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_INTBG; + tmp |= value << SDHC_BGCR_INTBG_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINT; + tmp |= value << SDHC_WCR_WKENCINT_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINS; + tmp |= value << SDHC_WCR_WKENCINS_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCREM; + tmp |= value << SDHC_WCR_WKENCREM_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->WCR.reg; +} + +static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKEN; + tmp |= value << SDHC_CCR_INTCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKS; + tmp |= value << SDHC_CCR_INTCLKS_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKEN; + tmp |= value << SDHC_CCR_SDCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_CLKGSEL; + tmp |= value << SDHC_CCR_CLKGSEL_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; + tmp |= SDHC_CCR_USDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; + tmp |= SDHC_CCR_SDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CCR.reg; +} + +static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= ~SDHC_TCR_DTCVAL_Msk; + tmp |= SDHC_TCR_DTCVAL(data); + ((Sdhc *)hw)->TCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TCR.reg; +} + +static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTALL; + tmp |= value << SDHC_SRR_SWRSTALL_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTCMD; + tmp |= value << SDHC_SRR_SWRSTCMD_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTDAT; + tmp |= value << SDHC_SRR_SWRSTDAT_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SRR.reg; +} + +static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CMDC; + tmp |= value << SDHC_NISTR_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_TRFC; + tmp |= value << SDHC_NISTR_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BLKGE; + tmp |= value << SDHC_NISTR_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_DMAINT; + tmp |= value << SDHC_NISTR_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BWRRDY; + tmp |= value << SDHC_NISTR_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BRDRDY; + tmp |= value << SDHC_NISTR_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINS; + tmp |= value << SDHC_NISTR_CINS_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CREM; + tmp |= value << SDHC_NISTR_CREM_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINT; + tmp |= value << SDHC_NISTR_CINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BOOTAR; + tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_ERRINT; + tmp |= value << SDHC_NISTR_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDTEO; + tmp |= value << SDHC_EISTR_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDCRC; + tmp |= value << SDHC_EISTR_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDEND; + tmp |= value << SDHC_EISTR_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDIDX; + tmp |= value << SDHC_EISTR_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATTEO; + tmp |= value << SDHC_EISTR_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATCRC; + tmp |= value << SDHC_EISTR_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATEND; + tmp |= value << SDHC_EISTR_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CURLIM; + tmp |= value << SDHC_EISTR_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ACMD; + tmp |= value << SDHC_EISTR_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ADMA; + tmp |= value << SDHC_EISTR_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_BOOTAE; + tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CMDC; + tmp |= value << SDHC_NISTER_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_TRFC; + tmp |= value << SDHC_NISTER_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BLKGE; + tmp |= value << SDHC_NISTER_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_DMAINT; + tmp |= value << SDHC_NISTER_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BWRRDY; + tmp |= value << SDHC_NISTER_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BRDRDY; + tmp |= value << SDHC_NISTER_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINS; + tmp |= value << SDHC_NISTER_CINS_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CREM; + tmp |= value << SDHC_NISTER_CREM_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINT; + tmp |= value << SDHC_NISTER_CINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BOOTAR; + tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDTEO; + tmp |= value << SDHC_EISTER_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDCRC; + tmp |= value << SDHC_EISTER_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDEND; + tmp |= value << SDHC_EISTER_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDIDX; + tmp |= value << SDHC_EISTER_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATTEO; + tmp |= value << SDHC_EISTER_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATCRC; + tmp |= value << SDHC_EISTER_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATEND; + tmp |= value << SDHC_EISTER_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CURLIM; + tmp |= value << SDHC_EISTER_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ACMD; + tmp |= value << SDHC_EISTER_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ADMA; + tmp |= value << SDHC_EISTER_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_BOOTAE; + tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CMDC; + tmp |= value << SDHC_NISIER_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_TRFC; + tmp |= value << SDHC_NISIER_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BLKGE; + tmp |= value << SDHC_NISIER_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_DMAINT; + tmp |= value << SDHC_NISIER_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BWRRDY; + tmp |= value << SDHC_NISIER_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BRDRDY; + tmp |= value << SDHC_NISIER_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINS; + tmp |= value << SDHC_NISIER_CINS_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CREM; + tmp |= value << SDHC_NISIER_CREM_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINT; + tmp |= value << SDHC_NISIER_CINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BOOTAR; + tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDTEO; + tmp |= value << SDHC_EISIER_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDCRC; + tmp |= value << SDHC_EISIER_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDEND; + tmp |= value << SDHC_EISIER_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDIDX; + tmp |= value << SDHC_EISIER_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATTEO; + tmp |= value << SDHC_EISIER_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATCRC; + tmp |= value << SDHC_EISIER_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATEND; + tmp |= value << SDHC_EISIER_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CURLIM; + tmp |= value << SDHC_EISIER_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ACMD; + tmp |= value << SDHC_EISIER_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ADMA; + tmp |= value << SDHC_EISIER_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_BOOTAE; + tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_VS18EN; + tmp |= value << SDHC_HC2R_VS18EN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EXTUN; + tmp |= value << SDHC_HC2R_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_SLCKSEL; + tmp |= value << SDHC_HC2R_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_ASINTEN; + tmp |= value << SDHC_HC2R_ASINTEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_PVALEN; + tmp |= value << SDHC_HC2R_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_UHSMS_Msk; + tmp |= SDHC_HC2R_UHSMS(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; + tmp |= SDHC_HC2R_EMMC_HS200EN(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_DRVSEL_Msk; + tmp |= SDHC_HC2R_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, + hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= ~SDHC_ASAR_ADMASA_Msk; + tmp |= SDHC_ASAR_ADMASA(data); + ((Sdhc *)hw)->ASAR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->ASAR[index].reg; +} + +static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_CLKGSEL; + tmp |= value << SDHC_PVR_CLKGSEL_Pos; + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; + tmp |= SDHC_PVR_SDCLKFSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_DRVSEL_Msk; + tmp |= SDHC_PVR_DRVSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->PVR[index].reg; +} + +static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_DDR; + tmp |= value << SDHC_MC1R_DDR_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_OPD; + tmp |= value << SDHC_MC1R_OPD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_BOOTA; + tmp |= value << SDHC_MC1R_BOOTA_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_RSTN; + tmp |= value << SDHC_MC1R_RSTN_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_FCD; + tmp |= value << SDHC_MC1R_FCD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_CMDTYP_Msk; + tmp |= SDHC_MC1R_CMDTYP(data); + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MC1R.reg; +} + +static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= ~SDHC_ACR_BMAX_Msk; + tmp |= SDHC_ACR_BMAX(data); + ((Sdhc *)hw)->ACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACR.reg; +} + +static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= ~SDHC_CC2R_FSDCLKD; + tmp |= value << SDHC_CC2R_FSDCLKD_Pos; + ((Sdhc *)hw)->CC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CC2R.reg; +} + +static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_CAPWREN; + tmp |= value << SDHC_CACR_CAPWREN_Pos; + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_KEY_Msk; + tmp |= SDHC_CACR_KEY(data); + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CACR.reg; +} + +static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= ~SDHC_DBGR_NIDBG; + tmp |= value << SDHC_DBGR_NIDBG_Pos; + ((Sdhc *)hw)->DBGR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->DBGR.reg; +} + +static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FERACES.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FEREIS.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) +#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) +#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) +#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) +#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) +#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) +#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) +#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) +#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) +#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) +#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) +#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) +#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) +#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) +#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) +#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) +#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) +#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) +#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) +#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) +#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) +#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) +#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) +#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) +#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) +#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) +#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) +#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) +#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) +#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) +#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) +#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) +#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) +#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) +#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) +#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) +#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) +#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) +#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) +#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) +#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) +#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) +#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) +#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) +#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) +#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) +#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) +#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) +#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) +#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) +#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) +#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) +#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) +#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) +#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) +#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) +#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) +#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) +#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) +#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) +#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) +#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) +#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) +#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) +#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) +#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) +#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) +#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) +#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) +#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) +#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) +#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) +#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) +#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) +#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) +#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDHC_E54_H_INCLUDED */ +#endif /* _SAME54_SDHC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_sercom_e54.h b/bsp/microchip/same54/bsp/hri/hri_sercom_e54.h new file mode 100644 index 0000000000..fed00ff459 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_sercom_e54.h @@ -0,0 +1,8892 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_E54_H_INCLUDED_ +#define _HRI_SERCOM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_length_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_length_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_length_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cm_data_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cs_data_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_ctrlc_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_data_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, + hri_sercomi2cm_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLC.reg; +} + +static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; + tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLC.reg; +} + +static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_DATA32B; + tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; + tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLC.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; + tmp |= SERCOM_USART_CTRLC_DATA32B(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LENEN; + tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; + tmp |= SERCOM_I2CS_LENGTH_LEN(data); + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.LENGTH.reg; +} + +static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LENEN; + tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; + tmp |= SERCOM_SPI_LENGTH_LEN(data); + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.LENGTH.reg; +} + +static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; + tmp |= SERCOM_USART_LENGTH_LEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; + tmp |= SERCOM_USART_LENGTH_LENEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.LENGTH.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_E54_H_INCLUDED */ +#endif /* _SAME54_SERCOM_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_supc_e54.h b/bsp/microchip/same54/bsp/hri/hri_supc_e54.h new file mode 100644 index 0000000000..501c36f5ec --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_supc_e54.h @@ -0,0 +1,1769 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_E54_H_INCLUDED_ +#define _HRI_SUPC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNHIB; + tmp |= value << SUPC_BOD33_RUNHIB_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST_Msk; + tmp |= SUPC_BOD33_HYST(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; + tmp |= SUPC_BOD33_VBATLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL; + tmp |= value << SUPC_VREG_SEL_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNBKUP; + tmp |= value << SUPC_VREG_RUNBKUP_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSEN; + tmp |= value << SUPC_VREG_VSEN_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF; + tmp |= value << SUPC_BBPS_CONF_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_E54_H_INCLUDED */ +#endif /* _SAME54_SUPC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_tc_e54.h b/bsp/microchip/same54/bsp/hri/hri_tc_e54.h new file mode 100644 index 0000000000..a31cb2cf7b --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_tc_e54.h @@ -0,0 +1,3003 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TC_COMPONENT_ +#ifndef _HRI_TC_E54_H_INCLUDED_ +#define _HRI_TC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE0_Msk; + tmp |= TC_CTRLA_CAPTMODE0(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE1_Msk; + tmp |= TC_CTRLA_CAPTMODE1(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_E54_H_INCLUDED */ +#endif /* _SAME54_TC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_tcc_e54.h b/bsp/microchip/same54/bsp/hri/hri_tcc_e54.h new file mode 100644 index 0000000000..55f46bd624 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_tcc_e54.h @@ -0,0 +1,9992 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TCC_COMPONENT_ +#ifndef _HRI_TCC_E54_H_INCLUDED_ +#define _HRI_TCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; +} + +static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; +} + +static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; + } +} + +static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; +} + +static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; +} + +static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; +} + +static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; + } +} + +static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN4; + tmp |= value << TCC_CTRLA_CPTEN4_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN5; + tmp |= value << TCC_CTRLA_CPTEN5_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI4; + tmp |= value << TCC_EVCTRL_MCEI4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI5; + tmp |= value << TCC_EVCTRL_MCEI5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO4; + tmp |= value << TCC_EVCTRL_MCEO4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO5; + tmp |= value << TCC_EVCTRL_MCEO5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL4; + tmp |= value << TCC_WAVE_POL4_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL5; + tmp |= value << TCC_WAVE_POL5_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_E54_H_INCLUDED */ +#endif /* _SAME54_TCC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_trng_e54.h b/bsp/microchip/same54/bsp/hri/hri_trng_e54.h new file mode 100644 index 0000000000..e42caabca8 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_trng_e54.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_E54_H_INCLUDED_ +#define _HRI_TRNG_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_E54_H_INCLUDED */ +#endif /* _SAME54_TRNG_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_usb_e54.h b/bsp/microchip/same54/bsp/hri/hri_usb_e54.h new file mode 100644 index 0000000000..34b5e02e7c --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_usb_e54.h @@ -0,0 +1,9335 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_USB_COMPONENT_ +#ifndef _HRI_USB_E54_H_INCLUDED_ +#define _HRI_USB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_E54_H_INCLUDED */ +#endif /* _SAME54_USB_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/hri/hri_wdt_e54.h b/bsp/microchip/same54/bsp/hri/hri_wdt_e54.h new file mode 100644 index 0000000000..3549e2f675 --- /dev/null +++ b/bsp/microchip/same54/bsp/hri/hri_wdt_e54.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_WDT_COMPONENT_ +#ifndef _HRI_WDT_E54_H_INCLUDED_ +#define _HRI_WDT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_E54_H_INCLUDED */ +#endif /* _SAME54_WDT_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/iar-project-connection.ipcf b/bsp/microchip/same54/bsp/iar-project-connection.ipcf new file mode 100644 index 0000000000..dfb94898fd --- /dev/null +++ b/bsp/microchip/same54/bsp/iar-project-connection.ipcf @@ -0,0 +1,431 @@ + + + + ATSAME54P20A + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\aes + $PROJ_DIR$\hpl\can + $PROJ_DIR$\hpl\cmcc + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\dmac + $PROJ_DIR$\hpl\gclk + $PROJ_DIR$\hpl\mclk + $PROJ_DIR$\hpl\osc32kctrl + $PROJ_DIR$\hpl\oscctrl + $PROJ_DIR$\hpl\pm + $PROJ_DIR$\hpl\port + $PROJ_DIR$\hpl\ramecc + $PROJ_DIR$\hpl\sercom + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\include + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\aes + $PROJ_DIR$\hpl\can + $PROJ_DIR$\hpl\cmcc + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\dmac + $PROJ_DIR$\hpl\gclk + $PROJ_DIR$\hpl\mclk + $PROJ_DIR$\hpl\osc32kctrl + $PROJ_DIR$\hpl\oscctrl + $PROJ_DIR$\hpl\pm + $PROJ_DIR$\hpl\port + $PROJ_DIR$\hpl\ramecc + $PROJ_DIR$\hpl\sercom + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\include + + + + __SAME54P20A__ + F_CPU=120000000 + + + + __SAME54P20A__ + + + + True + $PROJ_DIR$\iar\iar\same54p20a_flash.icf + + + + + atmel_start.c + atmel_start.h + atmel_start_pins.h + driver_init.c + driver_init.h + main.c + + + + CMSIS/Core/Include/cmsis_armcc.h + CMSIS/Core/Include/cmsis_armclang.h + CMSIS/Core/Include/cmsis_compiler.h + CMSIS/Core/Include/cmsis_gcc.h + CMSIS/Core/Include/cmsis_iccarm.h + CMSIS/Core/Include/cmsis_version.h + CMSIS/Core/Include/core_armv8mbl.h + CMSIS/Core/Include/core_armv8mml.h + CMSIS/Core/Include/core_cm0.h + CMSIS/Core/Include/core_cm0plus.h + CMSIS/Core/Include/core_cm1.h + CMSIS/Core/Include/core_cm23.h + CMSIS/Core/Include/core_cm3.h + CMSIS/Core/Include/core_cm33.h + CMSIS/Core/Include/core_cm4.h + CMSIS/Core/Include/core_cm7.h + CMSIS/Core/Include/core_sc000.h + CMSIS/Core/Include/core_sc300.h + CMSIS/Core/Include/mpu_armv7.h + CMSIS/Core/Include/mpu_armv8.h + CMSIS/Core/Include/tz_context.h + + + + config/hpl_aes_config.h + config/hpl_can_config.h + config/hpl_cmcc_config.h + config/hpl_dmac_config.h + config/hpl_gclk_config.h + config/hpl_mclk_config.h + config/hpl_osc32kctrl_config.h + config/hpl_oscctrl_config.h + config/hpl_port_config.h + config/hpl_sercom_config.h + config/peripheral_clk_config.h + + + + examples/driver_examples.c + examples/driver_examples.h + + + + hal/include/hal_aes_sync.h + hal/include/hal_atomic.h + hal/include/hal_cache.h + hal/include/hal_can_async.h + hal/include/hal_delay.h + hal/include/hal_gpio.h + hal/include/hal_init.h + hal/include/hal_io.h + hal/include/hal_sleep.h + hal/include/hal_usart_sync.h + hal/include/hpl_aes.h + hal/include/hpl_aes_sync.h + hal/include/hpl_can.h + hal/include/hpl_can_async.h + hal/include/hpl_cmcc.h + hal/include/hpl_core.h + hal/include/hpl_delay.h + hal/include/hpl_dma.h + hal/include/hpl_gpio.h + hal/include/hpl_i2c_m_async.h + hal/include/hpl_i2c_m_sync.h + hal/include/hpl_i2c_s_async.h + hal/include/hpl_i2c_s_sync.h + hal/include/hpl_init.h + hal/include/hpl_irq.h + hal/include/hpl_missing_features.h + hal/include/hpl_ramecc.h + hal/include/hpl_reset.h + hal/include/hpl_sleep.h + hal/include/hpl_spi.h + hal/include/hpl_spi_async.h + hal/include/hpl_spi_m_async.h + hal/include/hpl_spi_m_dma.h + hal/include/hpl_spi_m_sync.h + hal/include/hpl_spi_s_async.h + hal/include/hpl_spi_s_sync.h + hal/include/hpl_spi_sync.h + hal/include/hpl_usart.h + hal/include/hpl_usart_async.h + hal/include/hpl_usart_sync.h + + + + hal/src/hal_aes_sync.c + hal/src/hal_atomic.c + hal/src/hal_cache.c + hal/src/hal_can_async.c + hal/src/hal_delay.c + hal/src/hal_gpio.c + hal/src/hal_init.c + hal/src/hal_io.c + hal/src/hal_sleep.c + hal/src/hal_usart_sync.c + + + + hal/utils/include/compiler.h + hal/utils/include/err_codes.h + hal/utils/include/events.h + hal/utils/include/parts.h + hal/utils/include/utils.h + hal/utils/include/utils_assert.h + hal/utils/include/utils_event.h + hal/utils/include/utils_increment_macro.h + hal/utils/include/utils_list.h + hal/utils/include/utils_repeat_macro.h + + + + hal/utils/src/utils_assert.c + hal/utils/src/utils_event.c + hal/utils/src/utils_list.c + + + + hpl/aes/hpl_aes.c + + + + hpl/can/hpl_can.c + hpl/can/hpl_can_base.h + + + + hpl/cmcc/hpl_cmcc.c + + + + hpl/core/hpl_core_m4.c + hpl/core/hpl_core_port.h + hpl/core/hpl_init.c + + + + hpl/dmac/hpl_dmac.c + + + + hpl/gclk/hpl_gclk.c + hpl/gclk/hpl_gclk_base.h + + + + hpl/mclk/hpl_mclk.c + + + + hpl/osc32kctrl/hpl_osc32kctrl.c + + + + hpl/oscctrl/hpl_oscctrl.c + + + + hpl/pm/hpl_pm.c + hpl/pm/hpl_pm_base.h + + + + hpl/port/hpl_gpio_base.h + + + + hpl/ramecc/hpl_ramecc.c + + + + hpl/sercom/hpl_sercom.c + + + + hri/hri_ac_e54.h + hri/hri_adc_e54.h + hri/hri_aes_e54.h + hri/hri_can_e54.h + hri/hri_ccl_e54.h + hri/hri_cmcc_e54.h + hri/hri_dac_e54.h + hri/hri_dmac_e54.h + hri/hri_dsu_e54.h + hri/hri_e54.h + hri/hri_eic_e54.h + hri/hri_evsys_e54.h + hri/hri_freqm_e54.h + hri/hri_gclk_e54.h + hri/hri_gmac_e54.h + hri/hri_hmatrixb_e54.h + hri/hri_i2s_e54.h + hri/hri_icm_e54.h + hri/hri_mclk_e54.h + hri/hri_nvmctrl_e54.h + hri/hri_osc32kctrl_e54.h + hri/hri_oscctrl_e54.h + hri/hri_pac_e54.h + hri/hri_pcc_e54.h + hri/hri_pdec_e54.h + hri/hri_pm_e54.h + hri/hri_port_e54.h + hri/hri_qspi_e54.h + hri/hri_ramecc_e54.h + hri/hri_rstc_e54.h + hri/hri_rtc_e54.h + hri/hri_sdhc_e54.h + hri/hri_sercom_e54.h + hri/hri_supc_e54.h + hri/hri_tc_e54.h + hri/hri_tcc_e54.h + hri/hri_trng_e54.h + hri/hri_usb_e54.h + hri/hri_wdt_e54.h + + + + iar/system_same54.c + + + + iar/iar/startup_same54.c + + + + include/component-version.h + include/sam.h + include/sam.h + include/same54.h + include/same54n19a.h + include/same54n20a.h + include/same54p19a.h + include/same54p20a.h + include/system_same54.h + + + + include/component/ac.h + include/component/adc.h + include/component/aes.h + include/component/can.h + include/component/ccl.h + include/component/cmcc.h + include/component/dac.h + include/component/dmac.h + include/component/dsu.h + include/component/eic.h + include/component/evsys.h + include/component/freqm.h + include/component/gclk.h + include/component/gmac.h + include/component/hmatrixb.h + include/component/i2s.h + include/component/icm.h + include/component/mclk.h + include/component/nvmctrl.h + include/component/osc32kctrl.h + include/component/oscctrl.h + include/component/pac.h + include/component/pcc.h + include/component/pdec.h + include/component/picop.h + include/component/pm.h + include/component/port.h + include/component/qspi.h + include/component/ramecc.h + include/component/rstc.h + include/component/rtc.h + include/component/sdhc.h + include/component/sercom.h + include/component/supc.h + include/component/tc.h + include/component/tcc.h + include/component/trng.h + include/component/usb.h + include/component/wdt.h + + + + include/instance/ac.h + include/instance/adc0.h + include/instance/adc1.h + include/instance/aes.h + include/instance/can0.h + include/instance/can1.h + include/instance/ccl.h + include/instance/cmcc.h + include/instance/dac.h + include/instance/dmac.h + include/instance/dsu.h + include/instance/eic.h + include/instance/evsys.h + include/instance/freqm.h + include/instance/gclk.h + include/instance/gmac.h + include/instance/hmatrix.h + include/instance/i2s.h + include/instance/icm.h + include/instance/mclk.h + include/instance/nvmctrl.h + include/instance/osc32kctrl.h + include/instance/oscctrl.h + include/instance/pac.h + include/instance/pcc.h + include/instance/pdec.h + include/instance/picop.h + include/instance/pm.h + include/instance/port.h + include/instance/pukcc.h + include/instance/qspi.h + include/instance/ramecc.h + include/instance/rstc.h + include/instance/rtc.h + include/instance/sdhc0.h + include/instance/sdhc1.h + include/instance/sercom0.h + include/instance/sercom1.h + include/instance/sercom2.h + include/instance/sercom3.h + include/instance/sercom4.h + include/instance/sercom5.h + include/instance/sercom6.h + include/instance/sercom7.h + include/instance/supc.h + include/instance/tc0.h + include/instance/tc1.h + include/instance/tc2.h + include/instance/tc3.h + include/instance/tc4.h + include/instance/tc5.h + include/instance/tc6.h + include/instance/tc7.h + include/instance/tcc0.h + include/instance/tcc1.h + include/instance/tcc2.h + include/instance/tcc3.h + include/instance/tcc4.h + include/instance/trng.h + include/instance/usb.h + include/instance/wdt.h + + + + include/pio/same54n19a.h + include/pio/same54n20a.h + include/pio/same54p19a.h + include/pio/same54p20a.h + + + \ No newline at end of file diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf new file mode 100644 index 0000000000..5a1c3e3d18 --- /dev/null +++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_flash.icf @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000; +define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF; +define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000; +define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x10000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__]; +define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +initialize manually { section .qspi }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; +place in BKUPRAM_region { section .bkupram }; +place in QSPI_region { section .qspi }; diff --git a/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf new file mode 100644 index 0000000000..5f8d451acd --- /dev/null +++ b/bsp/microchip/same54/bsp/iar/iar/same54p20a_sram.icf @@ -0,0 +1,68 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_BKUPRAM_start__ = 0x47000000; +define symbol __ICFEDIT_region_BKUPRAM_end__ = 0x47001FFF; +define symbol __ICFEDIT_region_QSPI_start__ = 0x04000000; +define symbol __ICFEDIT_region_QSPI_end__ = 0x04FFFFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x10000; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region BKUPRAM_region = mem:[from __ICFEDIT_region_BKUPRAM_start__ to __ICFEDIT_region_BKUPRAM_end__]; +define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; +initialize manually { section .qspi }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite }; +place at end of RAM_region { block CSTACK, block HEAP }; +place in BKUPRAM_region { section .bkupram }; +place in QSPI_region { section .qspi }; diff --git a/bsp/microchip/same54/bsp/iar/iar/startup_same54.c b/bsp/microchip/same54/bsp/iar/iar/startup_same54.c new file mode 100644 index 0000000000..310808707e --- /dev/null +++ b/bsp/microchip/same54/bsp/iar/iar/startup_same54.c @@ -0,0 +1,600 @@ +/** + * \file + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +typedef void (*intfunc)(void); +typedef union { + intfunc __fun; + void * __ptr; +} intvec_elem; + +void __iar_program_start(void); +int __low_level_init(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +#pragma weak NonMaskableInt_Handler = Dummy_Handler +#pragma weak HardFault_Handler = Dummy_Handler +#pragma weak MemManagement_Handler = Dummy_Handler +#pragma weak BusFault_Handler = Dummy_Handler +#pragma weak UsageFault_Handler = Dummy_Handler +#pragma weak SVCall_Handler = Dummy_Handler +#pragma weak DebugMonitor_Handler = Dummy_Handler +#pragma weak PendSV_Handler = Dummy_Handler +#pragma weak SysTick_Handler = Dummy_Handler + +/* Peripherals handlers */ +#pragma weak PM_Handler = Dummy_Handler +#pragma weak MCLK_Handler = Dummy_Handler +#pragma weak OSCCTRL_0_Handler = Dummy_Handler /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +#pragma weak OSCCTRL_1_Handler = Dummy_Handler /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +#pragma weak OSCCTRL_2_Handler \ + = Dummy_Handler /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ +#pragma weak OSCCTRL_3_Handler \ + = Dummy_Handler /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +#pragma weak OSCCTRL_4_Handler \ + = Dummy_Handler /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +#pragma weak OSC32KCTRL_Handler = Dummy_Handler +#pragma weak SUPC_0_Handler \ + = Dummy_Handler /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ +#pragma weak SUPC_1_Handler = Dummy_Handler /* SUPC_BOD12DET, SUPC_BOD33DET */ +#pragma weak WDT_Handler = Dummy_Handler +#pragma weak RTC_Handler = Dummy_Handler +#pragma weak EIC_0_Handler = Dummy_Handler /* EIC_EXTINT_0 */ +#pragma weak EIC_1_Handler = Dummy_Handler /* EIC_EXTINT_1 */ +#pragma weak EIC_2_Handler = Dummy_Handler /* EIC_EXTINT_2 */ +#pragma weak EIC_3_Handler = Dummy_Handler /* EIC_EXTINT_3 */ +#pragma weak EIC_4_Handler = Dummy_Handler /* EIC_EXTINT_4 */ +#pragma weak EIC_5_Handler = Dummy_Handler /* EIC_EXTINT_5 */ +#pragma weak EIC_6_Handler = Dummy_Handler /* EIC_EXTINT_6 */ +#pragma weak EIC_7_Handler = Dummy_Handler /* EIC_EXTINT_7 */ +#pragma weak EIC_8_Handler = Dummy_Handler /* EIC_EXTINT_8 */ +#pragma weak EIC_9_Handler = Dummy_Handler /* EIC_EXTINT_9 */ +#pragma weak EIC_10_Handler = Dummy_Handler /* EIC_EXTINT_10 */ +#pragma weak EIC_11_Handler = Dummy_Handler /* EIC_EXTINT_11 */ +#pragma weak EIC_12_Handler = Dummy_Handler /* EIC_EXTINT_12 */ +#pragma weak EIC_13_Handler = Dummy_Handler /* EIC_EXTINT_13 */ +#pragma weak EIC_14_Handler = Dummy_Handler /* EIC_EXTINT_14 */ +#pragma weak EIC_15_Handler = Dummy_Handler /* EIC_EXTINT_15 */ +#pragma weak FREQM_Handler = Dummy_Handler +#pragma weak NVMCTRL_0_Handler \ + = Dummy_Handler /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ +#pragma weak NVMCTRL_1_Handler = Dummy_Handler /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +#pragma weak DMAC_0_Handler = Dummy_Handler /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +#pragma weak DMAC_1_Handler = Dummy_Handler /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +#pragma weak DMAC_2_Handler = Dummy_Handler /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +#pragma weak DMAC_3_Handler = Dummy_Handler /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +#pragma weak DMAC_4_Handler = Dummy_Handler /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, \ + DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, \ + DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, \ + DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, \ + DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, \ + DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, \ + DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, \ + DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, \ + DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, \ + DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, \ + DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, \ + DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, \ + DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, \ + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, \ + DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, \ + DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, \ + DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, \ + DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +#pragma weak EVSYS_0_Handler = Dummy_Handler /* EVSYS_EVD_0, EVSYS_OVR_0 */ +#pragma weak EVSYS_1_Handler = Dummy_Handler /* EVSYS_EVD_1, EVSYS_OVR_1 */ +#pragma weak EVSYS_2_Handler = Dummy_Handler /* EVSYS_EVD_2, EVSYS_OVR_2 */ +#pragma weak EVSYS_3_Handler = Dummy_Handler /* EVSYS_EVD_3, EVSYS_OVR_3 */ +#pragma weak EVSYS_4_Handler = Dummy_Handler /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, \ + EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, \ + EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, \ + EVSYS_OVR_9 */ +#pragma weak PAC_Handler = Dummy_Handler +#pragma weak RAMECC_Handler = Dummy_Handler +#pragma weak SERCOM0_0_Handler = Dummy_Handler /* SERCOM0_0 */ +#pragma weak SERCOM0_1_Handler = Dummy_Handler /* SERCOM0_1 */ +#pragma weak SERCOM0_2_Handler = Dummy_Handler /* SERCOM0_2 */ +#pragma weak SERCOM0_3_Handler = Dummy_Handler /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +#pragma weak SERCOM1_0_Handler = Dummy_Handler /* SERCOM1_0 */ +#pragma weak SERCOM1_1_Handler = Dummy_Handler /* SERCOM1_1 */ +#pragma weak SERCOM1_2_Handler = Dummy_Handler /* SERCOM1_2 */ +#pragma weak SERCOM1_3_Handler = Dummy_Handler /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +#pragma weak SERCOM2_0_Handler = Dummy_Handler /* SERCOM2_0 */ +#pragma weak SERCOM2_1_Handler = Dummy_Handler /* SERCOM2_1 */ +#pragma weak SERCOM2_2_Handler = Dummy_Handler /* SERCOM2_2 */ +#pragma weak SERCOM2_3_Handler = Dummy_Handler /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +#pragma weak SERCOM3_0_Handler = Dummy_Handler /* SERCOM3_0 */ +#pragma weak SERCOM3_1_Handler = Dummy_Handler /* SERCOM3_1 */ +#pragma weak SERCOM3_2_Handler = Dummy_Handler /* SERCOM3_2 */ +#pragma weak SERCOM3_3_Handler = Dummy_Handler /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +#pragma weak SERCOM4_0_Handler = Dummy_Handler /* SERCOM4_0 */ +#pragma weak SERCOM4_1_Handler = Dummy_Handler /* SERCOM4_1 */ +#pragma weak SERCOM4_2_Handler = Dummy_Handler /* SERCOM4_2 */ +#pragma weak SERCOM4_3_Handler = Dummy_Handler /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +#pragma weak SERCOM5_0_Handler = Dummy_Handler /* SERCOM5_0 */ +#pragma weak SERCOM5_1_Handler = Dummy_Handler /* SERCOM5_1 */ +#pragma weak SERCOM5_2_Handler = Dummy_Handler /* SERCOM5_2 */ +#pragma weak SERCOM5_3_Handler = Dummy_Handler /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +#pragma weak SERCOM6_0_Handler = Dummy_Handler /* SERCOM6_0 */ +#pragma weak SERCOM6_1_Handler = Dummy_Handler /* SERCOM6_1 */ +#pragma weak SERCOM6_2_Handler = Dummy_Handler /* SERCOM6_2 */ +#pragma weak SERCOM6_3_Handler = Dummy_Handler /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +#pragma weak SERCOM7_0_Handler = Dummy_Handler /* SERCOM7_0 */ +#pragma weak SERCOM7_1_Handler = Dummy_Handler /* SERCOM7_1 */ +#pragma weak SERCOM7_2_Handler = Dummy_Handler /* SERCOM7_2 */ +#pragma weak SERCOM7_3_Handler = Dummy_Handler /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +#pragma weak CAN0_Handler = Dummy_Handler +#endif +#ifdef ID_CAN1 +#pragma weak CAN1_Handler = Dummy_Handler +#endif +#ifdef ID_USB +#pragma weak USB_0_Handler = Dummy_Handler /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, \ + USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, \ + USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, \ + USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, \ + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, \ + USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, \ + USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, \ + USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, \ + USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, \ + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, \ + USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, \ + USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, \ + USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, \ + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +#pragma weak USB_1_Handler = Dummy_Handler /* USB_SOF_HSOF */ +#pragma weak USB_2_Handler = Dummy_Handler /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, \ + USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ +#pragma weak USB_3_Handler = Dummy_Handler /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, \ + USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +#pragma weak GMAC_Handler = Dummy_Handler +#endif +#pragma weak TCC0_0_Handler = Dummy_Handler /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, \ + TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +#pragma weak TCC0_1_Handler = Dummy_Handler /* TCC0_MC_0 */ +#pragma weak TCC0_2_Handler = Dummy_Handler /* TCC0_MC_1 */ +#pragma weak TCC0_3_Handler = Dummy_Handler /* TCC0_MC_2 */ +#pragma weak TCC0_4_Handler = Dummy_Handler /* TCC0_MC_3 */ +#pragma weak TCC0_5_Handler = Dummy_Handler /* TCC0_MC_4 */ +#pragma weak TCC0_6_Handler = Dummy_Handler /* TCC0_MC_5 */ +#pragma weak TCC1_0_Handler = Dummy_Handler /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, \ + TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +#pragma weak TCC1_1_Handler = Dummy_Handler /* TCC1_MC_0 */ +#pragma weak TCC1_2_Handler = Dummy_Handler /* TCC1_MC_1 */ +#pragma weak TCC1_3_Handler = Dummy_Handler /* TCC1_MC_2 */ +#pragma weak TCC1_4_Handler = Dummy_Handler /* TCC1_MC_3 */ +#pragma weak TCC2_0_Handler = Dummy_Handler /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, \ + TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +#pragma weak TCC2_1_Handler = Dummy_Handler /* TCC2_MC_0 */ +#pragma weak TCC2_2_Handler = Dummy_Handler /* TCC2_MC_1 */ +#pragma weak TCC2_3_Handler = Dummy_Handler /* TCC2_MC_2 */ +#ifdef ID_TCC3 +#pragma weak TCC3_0_Handler = Dummy_Handler /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, \ + TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +#pragma weak TCC3_1_Handler = Dummy_Handler /* TCC3_MC_0 */ +#pragma weak TCC3_2_Handler = Dummy_Handler /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +#pragma weak TCC4_0_Handler = Dummy_Handler /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, \ + TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +#pragma weak TCC4_1_Handler = Dummy_Handler /* TCC4_MC_0 */ +#pragma weak TCC4_2_Handler = Dummy_Handler /* TCC4_MC_1 */ +#endif +#pragma weak TC0_Handler = Dummy_Handler +#pragma weak TC1_Handler = Dummy_Handler +#pragma weak TC2_Handler = Dummy_Handler +#pragma weak TC3_Handler = Dummy_Handler +#ifdef ID_TC4 +#pragma weak TC4_Handler = Dummy_Handler +#endif +#ifdef ID_TC5 +#pragma weak TC5_Handler = Dummy_Handler +#endif +#ifdef ID_TC6 +#pragma weak TC6_Handler = Dummy_Handler +#endif +#ifdef ID_TC7 +#pragma weak TC7_Handler = Dummy_Handler +#endif +#pragma weak PDEC_0_Handler = Dummy_Handler /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +#pragma weak PDEC_1_Handler = Dummy_Handler /* PDEC_MC_0 */ +#pragma weak PDEC_2_Handler = Dummy_Handler /* PDEC_MC_1 */ +#pragma weak ADC0_0_Handler = Dummy_Handler /* ADC0_OVERRUN, ADC0_WINMON */ +#pragma weak ADC0_1_Handler = Dummy_Handler /* ADC0_RESRDY */ +#pragma weak ADC1_0_Handler = Dummy_Handler /* ADC1_OVERRUN, ADC1_WINMON */ +#pragma weak ADC1_1_Handler = Dummy_Handler /* ADC1_RESRDY */ +#pragma weak AC_Handler = Dummy_Handler +#pragma weak DAC_0_Handler = Dummy_Handler /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +#pragma weak DAC_1_Handler = Dummy_Handler /* DAC_EMPTY_0 */ +#pragma weak DAC_2_Handler = Dummy_Handler /* DAC_EMPTY_1 */ +#pragma weak DAC_3_Handler = Dummy_Handler /* DAC_RESRDY_0 */ +#pragma weak DAC_4_Handler = Dummy_Handler /* DAC_RESRDY_1 */ +#ifdef ID_I2S +#pragma weak I2S_Handler = Dummy_Handler +#endif +#pragma weak PCC_Handler = Dummy_Handler +#pragma weak AES_Handler = Dummy_Handler +#pragma weak TRNG_Handler = Dummy_Handler +#ifdef ID_ICM +#pragma weak ICM_Handler = Dummy_Handler +#endif +#ifdef ID_PUKCC +#pragma weak PUKCC_Handler = Dummy_Handler +#endif +#pragma weak QSPI_Handler = Dummy_Handler +#ifdef ID_SDHC0 +#pragma weak SDHC0_Handler = Dummy_Handler +#endif +#ifdef ID_SDHC1 +#pragma weak SDHC1_Handler = Dummy_Handler +#endif + +/* Exception Table */ +#pragma language = extended +#pragma segment = "CSTACK" + +/* The name "__vector_table" has special meaning for C-SPY: */ +/* it is where the SP start value is found, and the NVIC vector */ +/* table register (VTOR) is initialized to this address if != 0 */ + +#pragma section = ".intvec" +#pragma location = ".intvec" +const DeviceVectors __vector_table[] = { + (void *)__sfe("CSTACK"), + (void *)Reset_Handler, + (void *)NonMaskableInt_Handler, + (void *)HardFault_Handler, + (void *)MemManagement_Handler, + (void *)BusFault_Handler, + (void *)UsageFault_Handler, + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)(0UL), /* Reserved */ + (void *)SVCall_Handler, + (void *)DebugMonitor_Handler, + (void *)(0UL), /* Reserved */ + (void *)PendSV_Handler, + (void *)SysTick_Handler, + + /* Configurable interrupts */ + (void *)PM_Handler, /* 0 Power Manager */ + (void *)MCLK_Handler, /* 1 Main Clock */ + (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, + OSCCTRL_DFLLRDY */ + (void *)OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + (void *)OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + (void *) + SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + (void *)WDT_Handler, /* 10 Watchdog Timer */ + (void *)RTC_Handler, /* 11 Real-Time Counter */ + (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + (void *)FREQM_Handler, /* 28 Frequency Meter */ + (void *)NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, + NVMCTRL_7 */ + (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + (void *) + DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, + DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, + DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, + DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, + DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, + DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, + DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, + DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, + DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, + DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, + DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, + DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, + DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, + EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, + EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + (void *)PAC_Handler, /* 41 Peripheral Access Controller */ + (void *)(0UL), /* 42 Reserved */ + (void *)(0UL), /* 43 Reserved */ + (void *)(0UL), /* 44 Reserved */ + (void *)RAMECC_Handler, /* 45 RAM ECC */ + (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + (void *)(0UL), /* 62 Reserved */ + (void *)(0UL), /* 63 Reserved */ + (void *)(0UL), /* 64 Reserved */ + (void *)(0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + (void *)(0UL), /* 66 Reserved */ + (void *)(0UL), /* 67 Reserved */ + (void *)(0UL), /* 68 Reserved */ + (void *)(0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + (void *)(0UL), /* 70 Reserved */ + (void *)(0UL), /* 71 Reserved */ + (void *)(0UL), /* 72 Reserved */ + (void *)(0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + (void *)(0UL), /* 74 Reserved */ + (void *)(0UL), /* 75 Reserved */ + (void *)(0UL), /* 76 Reserved */ + (void *)(0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + (void *)CAN0_Handler, /* 78 Control Area Network 0 */ +#else + (void *)(0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + (void *)CAN1_Handler, /* 79 Control Area Network 1 */ +#else + (void *)(0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + (void *)USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, + USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, + USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, + USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, + USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, + USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, + USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, + USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */ + (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, + USB_TRCPT0_6, USB_TRCPT0_7 */ + (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, + USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + (void *)(0UL), /* 80 Reserved */ + (void *)(0UL), /* 81 Reserved */ + (void *)(0UL), /* 82 Reserved */ + (void *)(0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + (void *)GMAC_Handler, /* 84 Ethernet MAC */ +#else + (void *)(0UL), /* 84 Reserved */ +#endif + (void *)TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, + TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */ + (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */ + (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */ + (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */ + (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */ + (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */ + (void *)TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, + TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */ + (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */ + (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */ + (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */ + (void *)TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, + TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */ + (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */ + (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, + TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */ + (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + (void *)(0UL), /* 101 Reserved */ + (void *)(0UL), /* 102 Reserved */ + (void *)(0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, + TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */ + (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + (void *)(0UL), /* 104 Reserved */ + (void *)(0UL), /* 105 Reserved */ + (void *)(0UL), /* 106 Reserved */ +#endif + (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */ + (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */ + (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */ + (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + (void *)(0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + (void *)(0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + (void *)(0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + (void *)(0UL), /* 114 Reserved */ +#endif + (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */ + (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */ + (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */ + (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */ + (void *)AC_Handler, /* 122 Analog Comparators */ + (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + (void *)(0UL), /* 128 Reserved */ +#endif + (void *)PCC_Handler, /* 129 Parallel Capture Controller */ + (void *)AES_Handler, /* 130 Advanced Encryption Standard */ + (void *)TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + (void *)ICM_Handler, /* 132 Integrity Check Monitor */ +#else + (void *)(0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + (void *)(0UL), /* 133 Reserved */ +#endif + (void *)QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + (void *)(0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + (void *)(0UL) /* 136 Reserved */ +#endif +}; + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +int __low_level_init(void) +{ + uint32_t *pSrc = __section_begin(".intvec"); + + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + return 1; /* if return 0, the data sections will not be initialized */ +} + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __iar_program_start(); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/same54/bsp/iar/system_same54.c b/bsp/microchip/same54/bsp/iar/system_same54.c new file mode 100644 index 0000000000..468990e468 --- /dev/null +++ b/bsp/microchip/same54/bsp/iar/system_same54.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/bsp/microchip/same54/bsp/include/component-version.h b/bsp/microchip/same54/bsp/include/component-version.h new file mode 100644 index 0000000000..27f8da2db1 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 1 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10001 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 134 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.1" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2019-04-09 08:16:19" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/bsp/microchip/same54/bsp/include/component/ac.h b/bsp/microchip/same54/bsp/include/component/ac.h new file mode 100644 index 0000000000..c3bd888d21 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/ac.h @@ -0,0 +1,598 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AC_COMPONENT_ +#define _SAME54_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAME54_AC Analog Comparators */ +/*@{*/ + +#define AC_U2501 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ + uint16_t :14; /*!< bit: 2..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} AC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ +#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ + +#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/adc.h b/bsp/microchip/same54/bsp/include/component/adc.h new file mode 100644 index 0000000000..4434c85539 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/adc.h @@ -0,0 +1,871 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ADC_COMPONENT_ +#define _SAME54_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAME54_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2500 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ + uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :4; /*!< bit: 11..14 Reserved */ + uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ +#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :2; /*!< bit: 5.. 6 Reserved */ + uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :2; /*!< bit: 13..14 Reserved */ + uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ +#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ +#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ +#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ +#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ + uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ + uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ + uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ + uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ + uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ + uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ + uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ + uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ +#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ + +#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ +#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ +#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ +#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ +#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ +#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ +#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ +#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ +#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ +#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ +#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ +#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ +#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ +#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ +#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ +#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ +#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ +#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ +#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ +#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ +#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ +#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ + +#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ + RoReg8 Reserved1[0x1]; + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x17]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ + __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ + RoReg8 Reserved3[0x2]; + __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ + RoReg8 Reserved4[0x2]; + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/aes.h b/bsp/microchip/same54/bsp/include/component/aes.h new file mode 100644 index 0000000000..71942116de --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/aes.h @@ -0,0 +1,375 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AES_COMPONENT_ +#define _SAME54_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAME54_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x220 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ + uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ + uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ + uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/can.h b/bsp/microchip/same54/bsp/include/component/can.h new file mode 100644 index 0000000000..8f191fc11c --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/can.h @@ -0,0 +1,3187 @@ +/** + * \file + * + * \brief Component description for CAN + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CAN_COMPONENT_ +#define _SAME54_CAN_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CAN */ +/* ========================================================================== */ +/** \addtogroup SAME54_CAN Control Area Network */ +/*@{*/ + +#define CAN_U2003 +#define REV_CAN 0x321 + +/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :20; /*!< bit: 0..19 Reserved */ + uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /*!< bit: 28..31 Core Release */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CREL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ +#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */ + +#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ +#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ +#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ +#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */ + +/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ENDN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ +#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */ + +#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ +#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */ + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_MRCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ +#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ + +#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ +#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */ + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ + uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ + uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ + uint32_t :2; /*!< bit: 21..22 Reserved */ + uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_DBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ +#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ + +#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ +#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ +#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ +#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ +#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ +#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) +#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */ + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ + uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ + uint32_t RX:1; /*!< bit: 7 Receive Pin */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TEST_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ +#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */ + +#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ +#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) +#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ +#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ +#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) +#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */ + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ + uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RWD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ +#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */ + +#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ +#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ +#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */ + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INIT:1; /*!< bit: 0 Initialization */ + uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ + uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ + uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ + uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ + uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ + uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ + uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ + uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ + uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ + uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ + uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ + uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CCCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ +#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */ + +#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ +#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) +#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ +#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) +#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ +#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) +#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ +#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) +#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ +#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) +#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ +#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) +#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ +#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) +#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ +#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) +#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ +#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) +#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ +#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) +#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ +#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) +#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ +#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) +#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ +#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) +#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ +#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) +#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */ + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ + uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ + uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ +#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ + +#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ +#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ +#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ +#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ +#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */ + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ + uint32_t :14; /*!< bit: 2..15 Reserved */ + uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ +#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ + +#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ +#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ +#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */ + +/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ +#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ + +#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ +#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */ + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ +#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ + +#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ +#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) +#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ +#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ +#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */ + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ +#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ + +#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ +#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */ + +/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ + uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ECR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ +#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */ + +#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ +#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ +#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) +#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ +#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */ + +/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ + uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ + uint32_t EP:1; /*!< bit: 5 Error Passive */ + uint32_t EW:1; /*!< bit: 6 Warning Status */ + uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ + uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ + uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ + uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ + uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ +#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */ + +#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ +#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ +#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ +#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) +#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ +#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) +#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ +#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) +#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ +#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ +#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) +#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ +#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) +#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ +#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) +#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ +#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) +#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ +#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */ + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TDCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ +#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ + +#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ +#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ +#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */ + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ + uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ + uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ + uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ + uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ + uint32_t HPM:1; /*!< bit: 8 High Priority Message */ + uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ + uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ + uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ + uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ + uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /*!< bit: 23 Error Passive */ + uint32_t EW:1; /*!< bit: 24 Warning Status */ + uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ +#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */ + +#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ +#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) +#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ +#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) +#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ +#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) +#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ +#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) +#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ +#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) +#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ +#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) +#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ +#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) +#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ +#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) +#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ +#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) +#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ +#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) +#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ +#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) +#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ +#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) +#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ +#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) +#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ +#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) +#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ +#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) +#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ +#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) +#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ +#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) +#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ +#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) +#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ +#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) +#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ +#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) +#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ +#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) +#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ +#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) +#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ +#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) +#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ +#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) +#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ +#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) +#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ +#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) +#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ +#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) +#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ +#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) +#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ +#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) +#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ +#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) +#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */ + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ + uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ + uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ + uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ + uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ + uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ + uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ + uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ +#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */ + +#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ +#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) +#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) +#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ +#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) +#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ +#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) +#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ +#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) +#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) +#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ +#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) +#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ +#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) +#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ +#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) +#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ +#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) +#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) +#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ +#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) +#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) +#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) +#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) +#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ +#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) +#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ +#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) +#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ +#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) +#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ +#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) +#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ +#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) +#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ +#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) +#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) +#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ +#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) +#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ +#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) +#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ +#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) +#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ +#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) +#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ +#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) +#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ +#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) +#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ +#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) +#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ +#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) +#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */ + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ + uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ + uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ + uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ + uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ + uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ + uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ + uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ +#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ + +#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ +#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) +#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) +#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ +#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) +#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ +#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) +#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ +#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) +#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) +#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ +#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) +#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ +#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) +#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ +#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) +#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ +#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) +#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) +#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ +#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) +#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) +#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) +#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) +#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ +#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) +#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ +#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) +#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ +#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) +#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ +#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) +#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ +#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) +#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ +#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) +#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) +#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ +#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) +#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ +#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) +#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ +#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) +#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ +#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) +#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ +#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) +#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ +#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) +#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ +#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) +#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ +#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) +#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */ + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ +#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ + +#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ +#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) +#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ +#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) +#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */ + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_GFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ +#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ + +#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ +#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) +#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ +#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) +#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ +#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ +#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */ + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ + uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ +#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ + +#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ +#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ +#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */ + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ + uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ +#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ + +#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ +#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ +#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */ + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ +#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ + +#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ +#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */ + +/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ + uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ + uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ + uint32_t FLST:1; /*!< bit: 15 Filter List */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_HPMS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ +#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ + +#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ +#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ +#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ +#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ +#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) +#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */ + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND0:1; /*!< bit: 0 New Data 0 */ + uint32_t ND1:1; /*!< bit: 1 New Data 1 */ + uint32_t ND2:1; /*!< bit: 2 New Data 2 */ + uint32_t ND3:1; /*!< bit: 3 New Data 3 */ + uint32_t ND4:1; /*!< bit: 4 New Data 4 */ + uint32_t ND5:1; /*!< bit: 5 New Data 5 */ + uint32_t ND6:1; /*!< bit: 6 New Data 6 */ + uint32_t ND7:1; /*!< bit: 7 New Data 7 */ + uint32_t ND8:1; /*!< bit: 8 New Data 8 */ + uint32_t ND9:1; /*!< bit: 9 New Data 9 */ + uint32_t ND10:1; /*!< bit: 10 New Data 10 */ + uint32_t ND11:1; /*!< bit: 11 New Data 11 */ + uint32_t ND12:1; /*!< bit: 12 New Data 12 */ + uint32_t ND13:1; /*!< bit: 13 New Data 13 */ + uint32_t ND14:1; /*!< bit: 14 New Data 14 */ + uint32_t ND15:1; /*!< bit: 15 New Data 15 */ + uint32_t ND16:1; /*!< bit: 16 New Data 16 */ + uint32_t ND17:1; /*!< bit: 17 New Data 17 */ + uint32_t ND18:1; /*!< bit: 18 New Data 18 */ + uint32_t ND19:1; /*!< bit: 19 New Data 19 */ + uint32_t ND20:1; /*!< bit: 20 New Data 20 */ + uint32_t ND21:1; /*!< bit: 21 New Data 21 */ + uint32_t ND22:1; /*!< bit: 22 New Data 22 */ + uint32_t ND23:1; /*!< bit: 23 New Data 23 */ + uint32_t ND24:1; /*!< bit: 24 New Data 24 */ + uint32_t ND25:1; /*!< bit: 25 New Data 25 */ + uint32_t ND26:1; /*!< bit: 26 New Data 26 */ + uint32_t ND27:1; /*!< bit: 27 New Data 27 */ + uint32_t ND28:1; /*!< bit: 28 New Data 28 */ + uint32_t ND29:1; /*!< bit: 29 New Data 29 */ + uint32_t ND30:1; /*!< bit: 30 New Data 30 */ + uint32_t ND31:1; /*!< bit: 31 New Data 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ +#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ + +#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ +#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) +#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ +#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) +#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ +#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) +#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ +#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) +#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ +#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) +#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ +#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) +#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ +#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) +#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ +#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) +#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ +#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) +#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ +#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) +#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ +#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) +#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ +#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) +#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ +#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) +#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ +#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) +#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ +#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) +#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ +#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) +#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ +#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) +#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ +#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) +#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ +#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) +#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ +#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) +#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ +#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) +#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ +#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) +#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ +#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) +#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ +#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) +#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ +#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) +#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ +#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) +#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ +#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) +#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ +#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) +#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ +#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) +#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ +#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) +#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ +#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) +#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ +#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) +#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */ + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND32:1; /*!< bit: 0 New Data 32 */ + uint32_t ND33:1; /*!< bit: 1 New Data 33 */ + uint32_t ND34:1; /*!< bit: 2 New Data 34 */ + uint32_t ND35:1; /*!< bit: 3 New Data 35 */ + uint32_t ND36:1; /*!< bit: 4 New Data 36 */ + uint32_t ND37:1; /*!< bit: 5 New Data 37 */ + uint32_t ND38:1; /*!< bit: 6 New Data 38 */ + uint32_t ND39:1; /*!< bit: 7 New Data 39 */ + uint32_t ND40:1; /*!< bit: 8 New Data 40 */ + uint32_t ND41:1; /*!< bit: 9 New Data 41 */ + uint32_t ND42:1; /*!< bit: 10 New Data 42 */ + uint32_t ND43:1; /*!< bit: 11 New Data 43 */ + uint32_t ND44:1; /*!< bit: 12 New Data 44 */ + uint32_t ND45:1; /*!< bit: 13 New Data 45 */ + uint32_t ND46:1; /*!< bit: 14 New Data 46 */ + uint32_t ND47:1; /*!< bit: 15 New Data 47 */ + uint32_t ND48:1; /*!< bit: 16 New Data 48 */ + uint32_t ND49:1; /*!< bit: 17 New Data 49 */ + uint32_t ND50:1; /*!< bit: 18 New Data 50 */ + uint32_t ND51:1; /*!< bit: 19 New Data 51 */ + uint32_t ND52:1; /*!< bit: 20 New Data 52 */ + uint32_t ND53:1; /*!< bit: 21 New Data 53 */ + uint32_t ND54:1; /*!< bit: 22 New Data 54 */ + uint32_t ND55:1; /*!< bit: 23 New Data 55 */ + uint32_t ND56:1; /*!< bit: 24 New Data 56 */ + uint32_t ND57:1; /*!< bit: 25 New Data 57 */ + uint32_t ND58:1; /*!< bit: 26 New Data 58 */ + uint32_t ND59:1; /*!< bit: 27 New Data 59 */ + uint32_t ND60:1; /*!< bit: 28 New Data 60 */ + uint32_t ND61:1; /*!< bit: 29 New Data 61 */ + uint32_t ND62:1; /*!< bit: 30 New Data 62 */ + uint32_t ND63:1; /*!< bit: 31 New Data 63 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ +#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ + +#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ +#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) +#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ +#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) +#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ +#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) +#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ +#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) +#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ +#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) +#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ +#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) +#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ +#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) +#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ +#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) +#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ +#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) +#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ +#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) +#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ +#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) +#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ +#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) +#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ +#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) +#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ +#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) +#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ +#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) +#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ +#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) +#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ +#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) +#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ +#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) +#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ +#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) +#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ +#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) +#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ +#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) +#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ +#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) +#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ +#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) +#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ +#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) +#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ +#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) +#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ +#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) +#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ +#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) +#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ +#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) +#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ +#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) +#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ +#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) +#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ +#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) +#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ +#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) +#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */ + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ + uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ + uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ +#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ + +#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ +#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ +#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ +#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ +#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) +#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */ + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ +#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ + +#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ +#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ +#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ +#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ +#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) +#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ +#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) +#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */ + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ + +#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ +#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */ + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ +#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ + +#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ +#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */ + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ + uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ + uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ +#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ + +#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ +#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ +#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ +#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ +#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) +#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */ + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ + uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ + uint32_t :4; /*!< bit: 26..29 Reserved */ + uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ +#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ + +#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ +#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ +#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ +#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ +#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) +#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ +#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) +#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ +#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */ + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ + +#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ +#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */ + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ +#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ + +#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ +#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ +#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ +#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */ + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ +#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ + +#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ +#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ +#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ +#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ +#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) +#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */ + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXFQS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ +#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ + +#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ +#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ +#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ +#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ +#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) +#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */ + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ +#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ + +#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ +#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */ + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ + uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ + uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ + uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ + uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ + uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ + uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ + uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ + uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ + uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ + uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ + uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ + uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ + uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ + uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ + uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ + uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ + uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ + uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ + uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ + uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ + uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ + uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ + uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ + uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ + uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ + uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ + uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ + uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ + uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ + uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ + uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBRP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ +#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ + +#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ +#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) +#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ +#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) +#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ +#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) +#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ +#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) +#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ +#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) +#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ +#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) +#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ +#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) +#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ +#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) +#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ +#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) +#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ +#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) +#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ +#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) +#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ +#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) +#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ +#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) +#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ +#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) +#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ +#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) +#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ +#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) +#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ +#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) +#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ +#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) +#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ +#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) +#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ +#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) +#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ +#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) +#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ +#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) +#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ +#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) +#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ +#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) +#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ +#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) +#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ +#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) +#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ +#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) +#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ +#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) +#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ +#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) +#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ +#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) +#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ +#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) +#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ +#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) +#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */ + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ + uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ + uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ + uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ + uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ + uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ + uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ + uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ + uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ + uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ + uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ + uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ + uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ + uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ + uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ + uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ + uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ + uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ + uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ + uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ + uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ + uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ + uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ + uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ + uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ + uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ + uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ + uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ + uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ + uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ + uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ + uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ +#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ + +#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ +#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) +#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ +#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) +#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ +#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) +#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ +#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) +#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ +#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) +#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ +#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) +#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ +#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) +#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ +#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) +#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ +#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) +#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ +#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) +#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ +#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) +#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ +#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) +#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ +#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) +#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ +#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) +#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ +#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) +#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ +#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) +#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ +#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) +#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ +#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) +#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ +#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) +#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ +#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) +#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ +#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) +#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ +#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) +#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ +#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) +#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ +#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) +#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ +#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) +#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ +#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) +#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ +#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) +#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ +#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) +#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ +#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) +#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ +#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) +#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ +#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) +#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ +#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) +#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */ + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ + uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ + uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ + uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ + uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ + uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ + uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ + uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ + uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ + uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ + uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ + uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ + uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ + uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ + uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ + uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ + uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ + uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ + uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ + uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ + uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ + uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ + uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ + uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ + uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ + uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ + uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ + uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ + uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ + uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ + uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ + uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ +#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ + +#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ +#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) +#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ +#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) +#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ +#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) +#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ +#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) +#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ +#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) +#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ +#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) +#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ +#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) +#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ +#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) +#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ +#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) +#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ +#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) +#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ +#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) +#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ +#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) +#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ +#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) +#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ +#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) +#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ +#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) +#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ +#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) +#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ +#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) +#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ +#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) +#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ +#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) +#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ +#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) +#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ +#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) +#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ +#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) +#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ +#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) +#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ +#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) +#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ +#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) +#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ +#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) +#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ +#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) +#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ +#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) +#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ +#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) +#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ +#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) +#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ +#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) +#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ +#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) +#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */ + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ + uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ + uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ + uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ + uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ + uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ + uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ + uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ + uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ + uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ + uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ + uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ + uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ + uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ + uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ + uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ + uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ + uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ + uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ + uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ + uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ + uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ + uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ + uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ + uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ + uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ + uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ + uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ + uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ + uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ + uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ + uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ + +#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ +#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) +#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ +#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) +#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ +#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) +#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ +#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) +#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ +#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) +#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ +#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) +#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ +#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) +#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ +#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) +#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ +#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) +#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ +#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) +#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ +#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) +#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ +#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) +#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ +#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) +#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ +#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) +#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ +#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) +#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ +#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) +#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ +#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) +#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ +#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) +#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ +#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) +#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ +#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) +#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ +#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) +#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ +#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) +#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ +#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) +#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ +#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) +#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ +#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) +#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ +#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) +#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ +#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) +#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ +#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) +#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ +#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) +#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ +#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) +#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ +#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) +#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ +#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) +#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */ + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ + uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ + uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ + uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ + uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ + uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ + uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ + uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ + uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ + uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ + uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ + uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ + uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ + uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ + uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ + uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ + uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ + uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ + uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ + uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ + uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ + uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ + uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ + uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ + uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ + uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ + uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ + uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ + uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ + uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ + uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ + uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ + +#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ +#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) +#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ +#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) +#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ +#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) +#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ +#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) +#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ +#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) +#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ +#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) +#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ +#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) +#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ +#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) +#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ +#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) +#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ +#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) +#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ +#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) +#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ +#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) +#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ +#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) +#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ +#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) +#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ +#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) +#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ +#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) +#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ +#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) +#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ +#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) +#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ +#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) +#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ +#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) +#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ +#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) +#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ +#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) +#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ +#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) +#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ +#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) +#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ +#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) +#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ +#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) +#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ +#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) +#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ +#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) +#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ +#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) +#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ +#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) +#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ +#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) +#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ +#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) +#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */ + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ + uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ + uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ + uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ + uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ + uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ + uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ + uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ + uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ + uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ + uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ + uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ + uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ + uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ + uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ + uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ + uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ + uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ + uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ + uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ + uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ + uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ + uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ + uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ + uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ + uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ + uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ + uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ + uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ + uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ + uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ + uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ + +#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ +#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) +#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ +#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) +#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ +#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) +#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ +#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) +#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ +#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) +#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ +#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) +#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ +#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) +#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ +#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) +#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ +#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) +#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ +#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) +#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ +#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) +#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ +#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) +#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ +#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) +#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ +#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) +#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ +#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) +#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ +#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) +#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ +#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) +#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ +#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) +#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ +#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) +#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ +#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) +#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ +#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) +#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ +#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) +#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ +#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) +#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ +#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) +#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ +#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) +#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ +#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) +#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ +#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) +#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ +#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) +#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ +#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) +#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ +#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) +#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ +#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) +#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ +#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) +#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */ + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ + uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ + uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ + uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ + uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ + uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ + uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ + uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ + uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ + uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ + uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ + uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ + uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ + uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ + uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ + uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ + uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ + uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ + uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ + uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ + uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ + uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ + uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ + uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ + uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ + uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ + uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ + uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ + uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ + uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ + uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ + uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ + +#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ +#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) +#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ +#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) +#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ +#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) +#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ +#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) +#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ +#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) +#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ +#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) +#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ +#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) +#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ +#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) +#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ +#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) +#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ +#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) +#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ +#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) +#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ +#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) +#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ +#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) +#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ +#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) +#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ +#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) +#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ +#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) +#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ +#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) +#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ +#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) +#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ +#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) +#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ +#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) +#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ +#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) +#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ +#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) +#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ +#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) +#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ +#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) +#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ +#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) +#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ +#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) +#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ +#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) +#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ +#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) +#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ +#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) +#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ +#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) +#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ +#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) +#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ +#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) +#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */ + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ + uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ +#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ + +#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ +#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ +#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ +#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */ + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /*!< bit: 21..23 Reserved */ + uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ +#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ + +#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ +#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ +#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ +#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ +#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) +#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ +#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) +#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */ + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ + +#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ +#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ +#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ + +#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ +#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ +#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) +#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ +#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) +#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ +#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) +#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */ + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ +#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ + +#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ +#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ +#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ +#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) +#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ +#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) +#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ +#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ +#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) +#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */ + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ +#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ + +#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ +#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ +#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ +#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ +#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */ + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ +#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ + +#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ +#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ +#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) +#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ +#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) +#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ +#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) +#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */ + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ +#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ + +#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ +#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ +#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ +#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) +#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ +#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) +#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ +#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ +#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) +#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */ + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ +#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ + +#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ +#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ +#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ +#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ +#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */ + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ +#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ + +#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ +#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ +#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) +#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ +#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) +#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ +#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) +#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */ + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ +#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ + +#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ +#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ +#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ +#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) +#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ +#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) +#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ +#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ +#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) +#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */ + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ +#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ + +#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ +#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ +#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ +#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ +#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */ + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /*!< bit: 11..15 Reserved */ + uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ +#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ + +#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ +#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ +#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ +#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ +#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */ + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ +#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ + +#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ +#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ +#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) +#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ +#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) +#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ +#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) +#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */ + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t DLC:4; /*!< bit: 16..19 Identifier */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ +#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ + +#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ +#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ +#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) +#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ +#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) +#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ +#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) +#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ +#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */ + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ +#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ + +#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ +#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ +#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ +#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ +#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */ + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ +#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ + +#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ +#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ +#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) +#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ +#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) +#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ +#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) +#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */ + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t ET:2; /*!< bit: 22..23 Event Type */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ +#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ + +#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ +#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ +#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ +#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) +#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ +#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) +#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ +#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ +#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */ + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ +#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ + +#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ +#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ +#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */ + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ +#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ + +#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ +#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ +#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */ + +/** \brief CAN APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ + __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ + __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ + __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ + __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ + RoReg8 Reserved1[0x10]; + __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ + __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ + __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved2[0x4]; + __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ + __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ + RoReg8 Reserved3[0x20]; + __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved4[0x4]; + __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ + __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ + __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + RoReg8 Reserved5[0x8]; + __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} CanMramRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf0e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} CanMramRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf1e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} CanMramRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_sidfe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ +} CanMramSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} CanMramTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txefe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} CanMramTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_xifde hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} CanMramXifde +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_CAN_MRAM_RXBE +#define SECTION_CAN_MRAM_RXF0E +#define SECTION_CAN_MRAM_RXF1E +#define SECTION_CAN_MRAM_SIDFE +#define SECTION_CAN_MRAM_TXBE +#define SECTION_CAN_MRAM_TXEFE +#define SECTION_CAN_MRAM_XIFDE + +/*@}*/ + +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/ccl.h b/bsp/microchip/same54/bsp/include/component/ccl.h new file mode 100644 index 0000000000..b5f4eeb5c7 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/ccl.h @@ -0,0 +1,228 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CCL_COMPONENT_ +#define _SAME54_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAME54_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x110 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ + uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/cmcc.h b/bsp/microchip/same54/bsp/include/component/cmcc.h new file mode 100644 index 0000000000..b57ed9cc24 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/cmcc.h @@ -0,0 +1,357 @@ +/** + * \file + * + * \brief Component description for CMCC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CMCC_COMPONENT_ +#define _SAME54_CMCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CMCC */ +/* ========================================================================== */ +/** \addtogroup SAME54_CMCC Cortex M Cache Controller */ +/*@{*/ + +#define CMCC_U2015 +#define REV_CMCC 0x600 + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ + uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ + uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ + uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ + uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_TYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ + +#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ +#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ +#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ +#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ + uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ + +#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ +#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ +#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ + +#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ +#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_SR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ +#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ + +#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ +#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_LCKWAY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ + +#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ + +#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ +#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ + uint32_t :16; /*!< bit: 12..27 Reserved */ + uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ + +#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ + +#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ + +#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ +#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ + +#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ +#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ + +#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ + +/** \brief CMCC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ + __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ + __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ + __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + RoReg8 Reserved1[0xC]; + __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} Cmcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/dac.h b/bsp/microchip/same54/bsp/include/component/dac.h new file mode 100644 index 0000000000..6ce9a5fcf2 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/dac.h @@ -0,0 +1,544 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_DAC_COMPONENT_ +#define _SAME54_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAME54_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2502 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ + uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ +#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) +#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ +#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) +#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) +#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) +#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) +#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) +#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) +#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) +#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) +#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) +#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) +#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) +#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) +#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ + __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ + __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ + __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ + __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ + __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ + __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ + __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ +#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) +#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ +#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) +#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ +#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) +#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ +#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) +#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) +#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) +#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) +#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :1; /*!< bit: 12 Reserved */ + uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ +#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ +#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ +#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ +#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ + +#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ + __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ + __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x3]; + __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/bsp/microchip/same54/bsp/include/component/dmac.h b/bsp/microchip/same54/bsp/include/component/dmac.h new file mode 100644 index 0000000000..702a5d731b --- /dev/null +++ b/bsp/microchip/same54/bsp/include/component/dmac.h @@ -0,0 +1,1416 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_DMAC_COMPONENT_ +#define _SAME54_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAME54_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2503 +#define REV_DMAC 0x101 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t :6; /*!< bit: 2.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ +#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) +#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ +#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ +#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) +#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ + uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ + uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ + uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ + uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ + uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ + uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ + uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ + uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ + uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ + uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ + uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ + uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ + uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ + uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ + uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ + uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ + uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ + uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ + uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ +#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) +#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ +#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) +#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ +#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) +#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ +#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) +#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ +#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ + uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ + uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ + uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ + uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ + uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ + uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ + uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ + uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ + uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ + uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ + uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ + uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ + uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ + uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ + uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) +#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) +#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) +#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) +#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) +#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) +#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) +#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) +#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) +#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) +#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) +#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) +#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) +#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) +#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) +#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ + uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ + uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ + uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ + uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ + uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ + uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ + uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ + uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ + uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ + uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ + uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ + uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ + uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ + uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ + uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ +#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) +#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ +#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) +#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ +#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) +#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ +#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) +#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ +#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) +#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ +#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) +#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ +#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) +#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ +#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) +#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ +#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) +#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ +#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) +#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ +#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) +#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ +#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) +#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ +#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) +#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ +#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) +#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ +#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) +#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ +#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ + uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ + uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ + uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ + uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ + uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ + uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ + uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ + uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ + uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ + uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ + uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ + uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ + uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ + uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ + uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ +#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) +#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ +#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) +#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ +#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) +#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ +#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) +#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ +#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) +#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ +#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) +#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ +#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) +#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ +#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) +#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ +#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) +#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ +#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) +#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ +#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) +#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ +#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) +#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ +#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) +#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ +#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) +#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ +#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) +#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ +#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ + uint32_t :5; /*!< bit: 15..19 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ + uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ +#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ +#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) +#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ +#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ +#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) +#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ +#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ +#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ +#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) +#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ +#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ +#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) +#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ +#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ + +#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHPRILVL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ +#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ + +#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ +#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) +#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ +#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ +#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ +#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ +#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ +#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ +#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ + +/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ + uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ + uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHEVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ +#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ + +#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ +#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) +#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ +#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ +#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ +#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ +#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ +#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ +#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ +#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ +#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) +#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ +#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) +#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ +#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ +#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) +#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits +#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 10 // Index of Generic Clock +#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value +#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value +#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented +#define USB_PIPE_NUM 8 // Number of USB pipes +#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system +#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested +#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode + +#endif /* _SAME54_USB_INSTANCE_ */ diff --git a/bsp/microchip/same54/bsp/include/instance/wdt.h b/bsp/microchip/same54/bsp/include/instance/wdt.h new file mode 100644 index 0000000000..7acc8b1d7a --- /dev/null +++ b/bsp/microchip/same54/bsp/include/instance/wdt.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_WDT_INSTANCE_ +#define _SAME54_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAME54_WDT_INSTANCE_ */ diff --git a/bsp/microchip/same54/bsp/include/pio/same54n19a.h b/bsp/microchip/same54/bsp/include/pio/same54n19a.h new file mode 100644 index 0000000000..703eb8303f --- /dev/null +++ b/bsp/microchip/same54/bsp/include/pio/same54n19a.h @@ -0,0 +1,2688 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_PIO_ +#define _SAME54N19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N19A_PIO_ */ diff --git a/bsp/microchip/same54/bsp/include/pio/same54n20a.h b/bsp/microchip/same54/bsp/include/pio/same54n20a.h new file mode 100644 index 0000000000..7616f101f6 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/pio/same54n20a.h @@ -0,0 +1,2688 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_PIO_ +#define _SAME54N20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N20A_PIO_ */ diff --git a/bsp/microchip/same54/bsp/include/pio/same54p19a.h b/bsp/microchip/same54/bsp/include/pio/same54p19a.h new file mode 100644 index 0000000000..334cdff4f8 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/pio/same54p19a.h @@ -0,0 +1,3010 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_PIO_ +#define _SAME54P19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P19A_PIO_ */ diff --git a/bsp/microchip/same54/bsp/include/pio/same54p20a.h b/bsp/microchip/same54/bsp/include/pio/same54p20a.h new file mode 100644 index 0000000000..9e7dd15689 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/pio/same54p20a.h @@ -0,0 +1,3010 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_PIO_ +#define _SAME54P20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P20A_PIO_ */ diff --git a/bsp/microchip/same54/bsp/include/sam.h b/bsp/microchip/same54/bsp/include/sam.h new file mode 100644 index 0000000000..3fa3b5f2e7 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/sam.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) +#include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) +#include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) +#include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) +#include "same54p20a.h" +#else +#error Library does not support the specified device +#endif + +#endif /* _SAM_ */ diff --git a/bsp/microchip/same54/bsp/include/same54.h b/bsp/microchip/same54/bsp/include/same54.h new file mode 100644 index 0000000000..de522e9849 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/same54.h @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief Top header file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ +#define _SAME54_ + +/** + * \defgroup SAME54_definitions SAME54 Device Definitions + * \brief SAME54 CMSIS Definitions. + */ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #include "same54p20a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME54_ */ diff --git a/bsp/microchip/same54/bsp/include/same54n19a.h b/bsp/microchip/same54/bsp/include/same54n19a.h new file mode 100644 index 0000000000..c26bab7a5d --- /dev/null +++ b/bsp/microchip/same54/bsp/include/same54n19a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_ +#define _SAME54N19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N19A_definitions SAME54N19A definitions + * This file defines all structures and symbols for SAME54N19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840303) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N19A_H */ diff --git a/bsp/microchip/same54/bsp/include/same54n20a.h b/bsp/microchip/same54/bsp/include/same54n20a.h new file mode 100644 index 0000000000..aaec273403 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/same54n20a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_ +#define _SAME54N20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N20A_definitions SAME54N20A definitions + * This file defines all structures and symbols for SAME54N20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840302) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N20A_H */ diff --git a/bsp/microchip/same54/bsp/include/same54p19a.h b/bsp/microchip/same54/bsp/include/same54p19a.h new file mode 100644 index 0000000000..7ad9f5bb9d --- /dev/null +++ b/bsp/microchip/same54/bsp/include/same54p19a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_ +#define _SAME54P19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P19A_definitions SAME54P19A definitions + * This file defines all structures and symbols for SAME54P19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840301) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P19A_H */ diff --git a/bsp/microchip/same54/bsp/include/same54p20a.h b/bsp/microchip/same54/bsp/include/same54p20a.h new file mode 100644 index 0000000000..bcab40a0bc --- /dev/null +++ b/bsp/microchip/same54/bsp/include/same54p20a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_ +#define _SAME54P20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P20A_definitions SAME54P20A definitions + * This file defines all structures and symbols for SAME54P20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840300) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P20A_H */ diff --git a/bsp/microchip/same54/bsp/include/system_same54.h b/bsp/microchip/same54/bsp/include/system_same54.h new file mode 100644 index 0000000000..5e2b8a1060 --- /dev/null +++ b/bsp/microchip/same54/bsp/include/system_same54.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAME54_H_INCLUDED_ +#define _SYSTEM_SAME54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAME54_H_INCLUDED */ diff --git a/bsp/microchip/same54/bsp/led_switcher_main.c b/bsp/microchip/same54/bsp/led_switcher_main.c new file mode 100644 index 0000000000..f8da027d77 --- /dev/null +++ b/bsp/microchip/same54/bsp/led_switcher_main.c @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief Application implement + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "atmel_start.h" +#include +#include + +int main(void) +{ + atmel_start_init(); + + gpio_set_pin_pull_mode(SW0, GPIO_PULL_UP); + + while (true) { + do { + delay_ms(100); + } while (gpio_get_pin_level(SW0)); + + gpio_toggle_pin_level(LED0); + + do { + delay_ms(100); + } while (!gpio_get_pin_level(SW0)); + } +} diff --git a/bsp/microchip/same54/bsp/stdio_start.c b/bsp/microchip/same54/bsp/stdio_start.c new file mode 100644 index 0000000000..db8d3625e5 --- /dev/null +++ b/bsp/microchip/same54/bsp/stdio_start.c @@ -0,0 +1,23 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ + +#include "atmel_start.h" +#include "stdio_start.h" + +void STDIO_REDIRECT_0_example(void) +{ + /* Print welcome message */ + printf("\r\nHello ATMEL World!\r\n"); +} + +void stdio_redirect_init(void) +{ + + usart_sync_enable(&TARGET_IO); + stdio_io_init(&TARGET_IO.io); +} diff --git a/bsp/microchip/same54/bsp/stdio_start.h b/bsp/microchip/same54/bsp/stdio_start.h new file mode 100644 index 0000000000..bee5325be1 --- /dev/null +++ b/bsp/microchip/same54/bsp/stdio_start.h @@ -0,0 +1,31 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef STDIO_MAIN_H +#define STDIO_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include + +#include +#include + +void STDIO_REDIRECT_0_example(void); + +/** + * \brief Initialize STDIO Redirect + */ +void stdio_redirect_init(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STDIO_MAIN_H */ diff --git a/bsp/microchip/same54/rtconfig.h b/bsp/microchip/same54/rtconfig.h new file mode 100644 index 0000000000..a2fe607b75 --- /dev/null +++ b/bsp/microchip/same54/rtconfig.h @@ -0,0 +1,182 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40100 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* POSIX extension functions */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_SAME54P20 + +/* Onboard Peripheral Drivers */ + +#define SAME5X_CAN0 +#define SAME5X_ADC0 + +/* Application Demo Config */ + +#define SAM_CAN_EXAMPLE +#define SAM_ADC_EXAMPLE +#define SOC_SAME54 + +#endif diff --git a/bsp/microchip/same54/rtconfig.py b/bsp/microchip/same54/rtconfig.py new file mode 100644 index 0000000000..289cea31ed --- /dev/null +++ b/bsp/microchip/same54/rtconfig.py @@ -0,0 +1,69 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +DEVICE_SERIES = 'SAME54' +#DEVICE_SERIES = 'SAME53' +#DEVICE_SERIES = 'SAME51' +#DEVICE_SERIES = 'SAMD51' +DEVICE_TYPE = '__SAME54P20A__' +#DEVICE_TYPE = '__SAME53N20A__' +DEVICE_PART = 'same54' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/workspace/tools/embedcpp/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -mlong-calls' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T bsp/gcc/gcc/same54p20a_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + diff --git a/bsp/microchip/same70/.config b/bsp/microchip/same70/.config new file mode 100644 index 0000000000..feb084ecef --- /dev/null +++ b/bsp/microchip/same70/.config @@ -0,0 +1,648 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40100 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +# CONFIG_RT_USING_MSH is not set +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# POSIX extension functions +# +# CONFIG_PKG_USING_POSIX_GETLINE is not set +# CONFIG_PKG_USING_POSIX_WCWIDTH is not set +# CONFIG_PKG_USING_POSIX_ITOA is not set +# CONFIG_PKG_USING_POSIX_STRINGS is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_SAME70Q21=y +# CONFIG_SOC_SAME70N21 is not set +# CONFIG_SOC_SAME70J21 is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_SAME70_CAN0=y +CONFIG_SAME70_ADC0=y + +# +# Application Demo Config +# +CONFIG_SAM_CAN_EXAMPLE=y +CONFIG_SOC_SAME70=y diff --git a/bsp/microchip/same70/.ignore_format.yml b/bsp/microchip/same70/.ignore_format.yml new file mode 100644 index 0000000000..988269df37 --- /dev/null +++ b/bsp/microchip/same70/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- bsp diff --git a/bsp/microchip/same70/Kconfig b/bsp/microchip/same70/Kconfig new file mode 100644 index 0000000000..896ed0a540 --- /dev/null +++ b/bsp/microchip/same70/Kconfig @@ -0,0 +1,31 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default: "rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config SOC_SAME70 + bool + select ARCH_ARM + select ARCH_ARM_CORTEX_M + select ARCH_ARM_CORTEX_M7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y diff --git a/bsp/microchip/same70/README.md b/bsp/microchip/same70/README.md new file mode 100644 index 0000000000..b53d7fd8f2 --- /dev/null +++ b/bsp/microchip/same70/README.md @@ -0,0 +1,69 @@ +# SAME70Q21B BSP Introduction + +[中文](README_zh.md) +- MCU: ATSAME70Q21B @300MHz, 2MB FLASH, 384KB RAM +- V71: Auto grade Cortex-M7 + Advanced Feature Set + Ethernet + 2x CAN-FD +- E70: Industrial Cortex-M7 + Advanced Feature Set + Ethernet + 2x CAN-FD +- S70: Industrial Cortex-M7 + Advanced Feature Set +- Pin: J=64 pins, N=100 pins, Q=144 pins +- Flash: 19=512KB, 20=1024KB, 21=2048KB (size=2^n) +- Datasheet: + +#### KEY FEATURES + +#### Core + - 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 300 MHz, MPU, 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions + +#### Memories + - Up to 2 Mbytes of embedded Flash with unique identifier and user signature for user-defined data + - Up to 384 Kbyte embedded Multi-port SRAM, can be configured as ITCM, DTCM. + - 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines + +#### Peripherals + - 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling + - 16-bit SDRAM Controller (SDRAMC) interfacing up to 128 MB and with on-the-fly scrambling + - One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE® 1588 PTP frames and 802.3az Energy-efficiency support. + - USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA + - 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI) + - Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission + - MediaLB® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks + - Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode. + - Five 2-wire UARTs with SleepWalking™ support + - Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support + - Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and onthe-fly scrambling + - Two Serial Peripheral Interfaces (SPI) + - One Serial Synchronous Controller (SSC) with I2S and TDM support + - Two Inter-IC Sound Controllers (I2SC) + - One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC) + - Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor + - Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control + - Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error correction feature. + - One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over Sampling modes + - One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis + +#### Cryptography + - True Random Number Generator (TRNG) + - AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications + - Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256. + +#### I/O + - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination + - Five Parallel Input/Output Controllers (PIO) + +#### Voltage + - Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices + - Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices + +#### Packages + - LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm + - LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm + - TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm + - UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm + - LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm + - TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm + - VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm + - LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm + - QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm with wettable flanks + +#### Board info +- [SAM E70 XPLAINED](https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD) diff --git a/bsp/microchip/same70/README_zh.md b/bsp/microchip/same70/README_zh.md new file mode 100644 index 0000000000..e25084876c --- /dev/null +++ b/bsp/microchip/same70/README_zh.md @@ -0,0 +1,69 @@ +# SAME70Q21B BSP 介绍 + +[English](README.md) +- MCU: ATSAME70Q21B @300MHz, 2MB FLASH, 384KB RAM +- V71: 汽车级产品 AEC-Q100 Cortex-M7内核 + 100M以太网 + 2路CAN-FD + 丰富外设 +- E70: 工业级产品 -40~105C Cortex-M7内核 + 100M以太网 + 2路CAN-FD + 丰富外设 +- S70: 工业级产品 -40~105C Cortex-M7内核 + 丰富外设 +- 管脚: J系列-64 pins, N系列-100 pins, Q系列-144 pins +- Flash: 尾缀19=512KB, 20=1024KB, 21=2048KB (flash容量=2^n) +- 手册: + +#### 关键特性 + +#### 内核 + - 32-bit Arm® Cortex®-M7 core + 双精度FPU + L1 cache: 16 Kbytes 数据DCache and 16 Kbytes 指令 Icache; 主频高达300 MHz, MPU, 2.14 DMIPS/MHz (Dhrystone 2.1), 支持 DSP指令集 + +#### 内存 + - 最大提供2MB 内嵌Flash，芯片内嵌独一无二的UID信息 + - 最大提供384KB 内嵌多端口SRAM, 可以将其配置为ITCM, DTCM. + - 内部集成16 Kbytes ROM，用于板载Bootloader(UART0, USB)和IAP应用. + +#### 外设 + - 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling + - 16-bit SDRAM Controller (SDRAMC) interfacing up to 128 MB and with on-the-fly scrambling + - One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE® 1588 PTP frames and 802.3az Energy-efficiency support. + - USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA + - 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI) + - Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission + - MediaLB® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks + - Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode. + - Five 2-wire UARTs with SleepWalking™ support + - Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support + - Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and onthe-fly scrambling + - Two Serial Peripheral Interfaces (SPI) + - One Serial Synchronous Controller (SSC) with I2S and TDM support + - Two Inter-IC Sound Controllers (I2SC) + - One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC) + - Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor + - Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control + - Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error correction feature. + - One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over Sampling modes + - One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis + +#### 加密模块 + - True Random Number Generator (TRNG) + - AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications + - Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256. + +#### I/O接口 + - Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination + - Five Parallel Input/Output Controllers (PIO) + +#### 工作电压 + - Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices + - Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices + +#### 封装 + - LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm + - LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm + - TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm + - UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm + - LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm + - TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm + - VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm + - LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm + - QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm with wettable flanks + +#### 官方开发板信息 +- [SAM E70 XPLAINED](https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD) diff --git a/bsp/microchip/same70/SConscript b/bsp/microchip/same70/SConscript new file mode 100644 index 0000000000..744d8d7821 --- /dev/null +++ b/bsp/microchip/same70/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/microchip/same70/SConstruct b/bsp/microchip/same70/SConstruct new file mode 100644 index 0000000000..4d91cd5ba5 --- /dev/null +++ b/bsp/microchip/same70/SConstruct @@ -0,0 +1,41 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread-' + rtconfig.DEVICE_PART + '.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread-'+ rtconfig.DEVICE_PART + '.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/microchip/same70/applications/SConscript b/bsp/microchip/same70/applications/SConscript new file mode 100644 index 0000000000..e806dae56e --- /dev/null +++ b/bsp/microchip/same70/applications/SConscript @@ -0,0 +1,10 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/microchip/same70/applications/can_demo.c b/bsp/microchip/same70/applications/can_demo.c new file mode 100644 index 0000000000..1c82466220 --- /dev/null +++ b/bsp/microchip/same70/applications/can_demo.c @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include "driver_init.h" +#include "utils.h" + +#include "can_demo.h" + +#ifdef SAM_CAN_EXAMPLE + +static volatile enum can_async_interrupt_type can_errors; +static rt_sem_t can_txdone; +static rt_sem_t can_rxdone; +static rt_uint8_t can_stack[ 512 ]; +static struct rt_thread can_thread; + +/** + * @brief Callback function and should be invoked after call can_async_write. + * + * @note + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_tx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_txdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after remote device send. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_rx_callback(struct can_async_descriptor *const descr) +{ + rt_err_t result; + + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); +} + +/** + * @brief Callback function and should be invoked after CAN device IRQ handler detects errors happened. + * + * @note This callback function will be called in CAN interrupt function + * + * @param descr is CAN device description. + * + * @return None. + */ + +static void can_err_callback(struct can_async_descriptor *const descr, + enum can_async_interrupt_type type) +{ + rt_err_t result; + + if (type == CAN_IRQ_EW) + { + /* Error warning, Error counter has reached the error warning limit of 96, + * An error count value greater than about 96 indicates a heavily disturbed + * bus. It may be of advantage to provide means to test for this condition. + */ + } + else if (type == CAN_IRQ_EA) + { + /* Error Active State, The CAN node normally take part in bus communication + * and sends an ACTIVE ERROR FLAG when an error has been detected. + */ + } + else if (type == CAN_IRQ_EP) + { + /* Error Passive State, The Can node goes into error passive state if at least + * one of its error counters is greater than 127. It still takes part in bus + * activities, but it sends a passive error frame only, on errors. + */ + } + else if (type == CAN_IRQ_BO) + { + /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is + * greater than or equal to 256. + */ + + /* Suspend CAN task and re-initialize CAN module. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } + else if (type == CAN_IRQ_DO) + { + /* Data Overrun in receive queue. A message was lost because the messages in + * the queue was not reading and releasing fast enough. There is not enough + * space for a new message in receive queue. + */ + + /* Suggest to delete CAN task and re-initialize it. */ + can_errors = type; + rt_interrupt_enter(); + result = rt_sem_release(can_rxdone); + if (RT_EOK != result) + { +#ifndef RT_USING_FINSH + rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__); +#endif + } + rt_interrupt_leave(); + } +}; + +/** + * @brief Initialize CAN module before task run. + * + * @note This function will set CAN Tx/Rx callback function and filters. + * + * @param None. + * + * @return None. + */ + +static inline void can_demo_init(void) +{ + struct can_filter filter; + + /** + * CAN_Node0_tx_callback callback should be invoked after call + * can_async_write, and remote device should receive message with ID=0x45A + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback); + + + /* Should set at least one CAN standard & message filter before enable it. */ + + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + /* If set second standard message filter, should increase filter index + * and filter algorithm + * For example: index should set to 1, otherwise it will replace filter 0. + * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */ + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter); + + can_async_enable(&CAN_0); +} + +/** + * @brief CAN task. + * + * @note This task will waiting for CAN RX semaphore and then process input. + * + * @param parameter - task input parameter. + * + * @return None. + */ + +static void can_thread_entry(void* parameter) +{ + int32_t ret; + rt_err_t result; + uint8_t data[64]; + uint32_t count=0; + struct can_message msg; + + while (1) + { +#ifndef RT_USING_FINSH + rt_kprintf("can task run count : %d\r\n",count); +#endif + count++; + + result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER); + if (RT_EOK != result) + continue; + + do + { + /* Process the incoming packet. */ + ret = can_async_read(&CAN_0, &msg); + if (ret == ERR_NONE) + { +#ifndef RT_USING_FINSH + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_TYPE_DATA ? "data" : "remote"); + rt_kprintf("CAN RX Message is % frame\r\n", + msg.type == CAN_FMT_STDID ? "Standard" : "Extended"); + rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len); + rt_kprintf("CAN RX Message content: "); + for (uint8_t i = 0; i < msg.len; i++) + rt_kprintf("0x%02X ", data[i]); + rt_kprintf("\r\n"); +#endif + } + } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */ + + /* CAN task got CAN error message, handler CAN Error Status */ + if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO)) + { + can_async_init(&CAN_0, MCAN1); + } + } +} + +/** + * @brief Call this function will to send a CAN message. + * + * @note + * + * @param msg - message to be sent, timeouts - wait timeouts for Tx completion. + * + * @return RT_OK or RT_ERROR. + */ + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts) +{ + rt_err_t result; + + if (RT_NULL == msg) + { + rt_kprintf("can_send_message input message error\r\n"); + return RT_ERROR; + } + + can_async_write(&CAN_0, msg); + result = rt_sem_take(can_rxdone, timeouts); + + return result; +} + +/** + * @brief Call this function will create a CAN task. + * + * @note Should create Tx/Rx semaphore before run task. + * + * @param None. + * + * @return RT_OK or -RT_ERROR. + */ + +rt_err_t can_demo_run(void) +{ + rt_err_t result; + + can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_rxdone) + { + rt_kprintf("can_rx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO); + if (RT_NULL == can_txdone) + { + rt_kprintf("can_tx semaphore create failed\r\n"); + return (-RT_ERROR); + } + + can_demo_init(); + + /* initialize CAN thread */ + result = rt_thread_init(&can_thread, + "can", + can_thread_entry, + RT_NULL, + (rt_uint8_t*)&can_stack[0], + sizeof(can_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&can_thread); + } + + return result; +} +#endif + +/*@}*/ diff --git a/bsp/microchip/same70/applications/can_demo.h b/bsp/microchip/same70/applications/can_demo.h new file mode 100644 index 0000000000..499d0390f8 --- /dev/null +++ b/bsp/microchip/same70/applications/can_demo.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __APPLICATION_CAN_H_ +#define __APPLICATION_CAN_H_ + +#include + +/** + * @brief External function definitions + * + */ +rt_err_t can_demo_run(void); + +rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts); + +#endif // __APPLICATION_CAN_H_ diff --git a/bsp/microchip/same70/applications/main.c b/bsp/microchip/same70/applications/main.c new file mode 100644 index 0000000000..8985159058 --- /dev/null +++ b/bsp/microchip/same70/applications/main.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#ifdef RT_USING_FINSH +#include +#include +#endif + +#include "atmel_start.h" +#include + +#ifdef SAM_CAN_EXAMPLE +#include "can_demo.h" +#endif + +static rt_uint8_t led_stack[ 512 ]; +static struct rt_thread led_thread; + +static void led_thread_entry(void* parameter) +{ + unsigned int count=0; + + while (1) + { + /* toggle led */ +#ifndef RT_USING_FINSH + rt_kprintf("led toggle, count : %d\r\n",count); +#endif + count++; + gpio_toggle_pin_level(LED0); + rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */ + } +} + +int main(void) +{ + rt_err_t result; + + /* initialize led thread */ + result = rt_thread_init(&led_thread, + "led", + led_thread_entry, + RT_NULL, + (rt_uint8_t*)&led_stack[0], + sizeof(led_stack), + RT_THREAD_PRIORITY_MAX/3, + 5); + if (result == RT_EOK) + { + rt_thread_startup(&led_thread); + } + +#ifdef SAM_CAN_EXAMPLE + can_demo_run(); +#endif + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/same70/board/Kconfig b/bsp/microchip/same70/board/Kconfig new file mode 100644 index 0000000000..19921f9eec --- /dev/null +++ b/bsp/microchip/same70/board/Kconfig @@ -0,0 +1,50 @@ +menu "Hardware Drivers Config" + +choice + prompt "select chip type" + default SOC_SAME70Q21 + + config SOC_SAME70Q21 + bool "SOC_SAME70Q21" + help + Refer to SAME70 DataSheet + + config SOC_SAME70N21 + bool "SOC_SAME70N21" + help + Refer to SAME70 DataSheet + + config SOC_SAME70J21 + bool "SOC_SAME70J21" + help + Refer to SAME70 DataSheet + +endchoice +endmenu + +menu "Onboard Peripheral Drivers" + config SAME70_CAN0 + bool "Enable CAN0" + default false + + config SAME70_ADC0 + bool "Enable ADC0" + default false +endmenu + +menu "Application Demo Config" + config SAM_CAN_EXAMPLE + bool "Enable SAM CAN Example" + depends on SAME70_CAN0 + default true + help + Add CAN example task to project + + config SAM_ADC_EXAMPLE + bool "Enable SAM ADC Example" + depends on SAME70_ADC0 + default true + help + Add ADC example task to project + +endmenu diff --git a/bsp/microchip/same70/board/SConscript b/bsp/microchip/same70/board/SConscript new file mode 100644 index 0000000000..0e5636b2f7 --- /dev/null +++ b/bsp/microchip/same70/board/SConscript @@ -0,0 +1,17 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +#remove other no use files +#SrcRemove(src, '*.c') + +# You can select chips from the list above +CPPDEFINES = ['SAME70xxx'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/microchip/same70/board/board.c b/bsp/microchip/same70/board/board.c new file mode 100644 index 0000000000..bd98d8bf88 --- /dev/null +++ b/bsp/microchip/same70/board/board.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include + +#include +#include "peripheral_clk_config.h" + +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +extern int rt_hw_uart_init(void); +#endif + +static struct io_descriptor* g_stdio; + +void rt_hw_console_output(const char *str) +{ + io_write(g_stdio, (uint8_t *)str, strlen(str)); +} +RTM_EXPORT(rt_hw_console_output); + +static inline void hw_board_init_usart(void) +{ + usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio); + usart_sync_enable(&TARGET_IO); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial SAME70 board. + */ +void rt_hw_board_init(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; + + SCB_EnableICache(); + + /* enable USART stdout module */ + hw_board_init_usart(); + + /* UART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + + /* init systick */ + SysTick_Config(CONF_CPU_FREQUENCY / RT_TICK_PER_SECOND); + + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + +#ifdef RT_USING_HEAP + #if defined(__CC_ARM) || defined(__CLANG_ARM) + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)HEAP_END); + #elif __ICCARM__ + rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)HEAP_END); + #endif +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +/*@}*/ diff --git a/bsp/microchip/same70/board/board.h b/bsp/microchip/same70/board/board.h new file mode 100644 index 0000000000..2f5027c041 --- /dev/null +++ b/bsp/microchip/same70/board/board.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "sam.h" + +// Internal SRAM memory size[Kbytes] <256-384> +// Default: 384 +#if defined(__SAME70J19B__) || defined(__ATSAME70J19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAME70J20B__) || defined(__ATSAME70J20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAME70J21B__) || defined(__ATSAME70J21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAME70N19B__) || defined(__ATSAME70N19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAME70N20B__) || defined(__ATSAME70N20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAME70N21B__) || defined(__ATSAME70N21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAME70Q19B__) || defined(__ATSAME70Q19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAME70Q20B__) || defined(__ATSAME70Q20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAME70Q21B__) || defined(__ATSAME70Q21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70J19B__) || defined(__ATSAMS70J19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMS70J20B__) || defined(__ATSAMS70J20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70J21B__) || defined(__ATSAMS70J21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70N19B__) || defined(__ATSAMS70N19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMS70N20B__) || defined(__ATSAMS70N20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70N21B__) || defined(__ATSAMS70N21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70Q19B__) || defined(__ATSAMS70Q19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMS70Q20B__) || defined(__ATSAMS70Q20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMS70Q21B__) || defined(__ATSAMS70Q21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70J19B__) || defined(__ATSAMV70J19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV70J20B__) || defined(__ATSAMV70J20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70J21B__) || defined(__ATSAMV70J21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70N19B__) || defined(__ATSAMV70N19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV70N20B__) || defined(__ATSAMV70N20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70N21B__) || defined(__ATSAMV70N21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70Q19B__) || defined(__ATSAMV70Q19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV70Q20B__) || defined(__ATSAMV70Q20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV70Q21B__) || defined(__ATSAMV70Q21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71J19B__) || defined(__ATSAMV71J19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV71J20B__) || defined(__ATSAMV71J20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71J21B__) || defined(__ATSAMV71J21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71N19B__) || defined(__ATSAMV71N19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV71N20B__) || defined(__ATSAMV71N20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71N21B__) || defined(__ATSAMV71N21B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71Q19B__) || defined(__ATSAMV71Q19B__) + #define SAME70_SRAM_SIZE 256 +#elif defined(__SAMV71Q20B__) || defined(__ATSAMV71Q20B__) + #define SAME70_SRAM_SIZE 384 +#elif defined(__SAMV71Q21B__) || defined(__ATSAMV71Q21B__) + #define SAME70_SRAM_SIZE 384 +#else +#error Board does not support the specified device +#endif + +#define SAME70_SRAM_END (0x20400000 + SAME70_SRAM_SIZE * 1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_begin("HEAP")) +#define HEAP_END (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#define HEAP_END SAME70_SRAM_END +#endif + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/microchip/same70/board/serial.c b/bsp/microchip/same70/board/serial.c new file mode 100644 index 0000000000..28ba104dbe --- /dev/null +++ b/bsp/microchip/same70/board/serial.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#include +#include + +#include + +/* SAM MCU serial device */ +static struct rt_serial_device sam_serial; + +/** + * @brief Configure serial port + * + * This function will configure UART baudrate, parity and so on. + * + * @return RT_EOK. + */ +static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + usart_sync_disable(desc); + + /* Set baudrate */ + usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate); + + /* Set stop bit */ + if (cfg->stop_bits == STOP_BITS_1) + usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE); + else if (cfg->stop_bits == STOP_BITS_2) + usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO); + + if (cfg->bit_order == BIT_ORDER_LSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB); + else if (cfg->bit_order == BIT_ORDER_MSB) + usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB); + + /* Set character size */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS); + break; + case DATA_BITS_6: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS); + break; + case DATA_BITS_7: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS); + break; + case DATA_BITS_8: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS); + break; + case DATA_BITS_9: + usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS); + break; + default: + break; + } + + if (cfg->parity == PARITY_NONE) + usart_sync_set_parity(desc, USART_PARITY_NONE); + else if (cfg->parity == PARITY_ODD) + usart_sync_set_parity(desc, USART_PARITY_ODD); + else if (cfg->parity == PARITY_EVEN) + usart_sync_set_parity(desc, USART_PARITY_EVEN); + + usart_sync_enable(desc); + + return RT_EOK; +} + +/** + * @brief Control serial port + * + * This function provide UART enable/disable control. + * + * @return RT_EOK. + */ +static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + usart_sync_disable(desc); + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + usart_sync_enable(desc); + break; + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + break; + } + + return RT_EOK; +} + +/** + * @brief Serial sends a char + * + * This function will send a char to the UART + * + * @return 1. + */ +static int serial_putc(struct rt_serial_device *serial, char c) +{ + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + io_write(&desc->io, (const uint8_t *)&c, 1); + + return 1; +} + +/** + * @brief Serial gets a char + * + * This function will get a char from the UART + * + * @return received char character or -1 if no char received. + */ +static int serial_getc(struct rt_serial_device *serial) +{ + char c; + int ch; + struct usart_sync_descriptor* desc; + + RT_ASSERT(serial != RT_NULL); + desc = (struct usart_sync_descriptor *)serial->parent.user_data; + + RT_ASSERT(desc != RT_NULL); + + ch = -1; + if (usart_sync_is_rx_not_empty(desc)) + { + io_read(&desc->io, (uint8_t *)&c, 1);; + ch = c & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops sam_serial_ops = +{ + serial_configure, + serial_control, + serial_putc, + serial_getc, +}; + +/** + * @brief Initialize the UART + * + * This function initialize the UART + * + * @return None. + */ +int rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + sam_serial.ops = &sam_serial_ops; + sam_serial.config = config; + sam_serial.serial_rx = RT_NULL; + sam_serial.serial_rx = RT_NULL; + rt_hw_serial_register(&sam_serial, "uart0", + RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO); + + return 0; +} + +/*@}*/ diff --git a/bsp/microchip/same70/board/serial.h b/bsp/microchip/same70/board/serial.h new file mode 100644 index 0000000000..12e6811231 --- /dev/null +++ b/bsp/microchip/same70/board/serial.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Email Notes + * 2019-07-16 Kevin.Liu kevin.liu.mchp@gmail.com First Release + */ + +#ifndef __BOARD_SERIAL_H_ +#define __BOARD_SERIAL_H_ + +#include + +/** + * @brief External function definitions + * + */ +int rt_hw_uart_init(void); + +#endif // __BOARD_SERIAL_H_ diff --git a/bsp/microchip/same70/bsp/AtmelStart.env_conf b/bsp/microchip/same70/bsp/AtmelStart.env_conf new file mode 100644 index 0000000000..4d05fd5090 --- /dev/null +++ b/bsp/microchip/same70/bsp/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/bsp/microchip/same70/bsp/AtmelStart.gpdsc b/bsp/microchip/same70/bsp/AtmelStart.gpdsc new file mode 100644 index 0000000000..ace1a9358b --- /dev/null +++ b/bsp/microchip/same70/bsp/AtmelStart.gpdsc @@ -0,0 +1,179 @@ + + Atmel + SAME70 LED switcher + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + + + + + + + + +
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-M):

+ +
+

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
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+Processor Support

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CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

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+Cortex-M Reference Manuals

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The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

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The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

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+Armv8-M Architecture

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Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

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The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

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+Tested and Verified Toolchains

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The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

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  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
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  • Arm: Arm Compiler 6.9
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  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
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  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
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  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
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+ + + + diff --git a/bsp/microchip/same70/bsp/SConscript b/bsp/microchip/same70/bsp/SConscript new file mode 100644 index 0000000000..246544ed8c --- /dev/null +++ b/bsp/microchip/same70/bsp/SConscript @@ -0,0 +1,54 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +#var defined +CPPDEFINES = [] + +#common lib define +CPPDEFINES += [rtconfig.DEVICE_TYPE] + +# The set of source files associated with this SConscript file. + +src = Glob('hal/src/*.c') +src += Glob('hal/utils/src/*.c') +src += Glob('hpl/core/*.c') +src += Glob('hpl/mcan/*.c') +src += Glob('hpl/pmc/*.c') +src += Glob('hpl/systick/*.c') +src += Glob('hpl/usart/*.c') +src += Glob('hpl/xdmac/*.c') +src += [cwd + '/atmel_start.c'] +src += [cwd + '/driver_init.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src += [cwd + '/same70b/gcc/system_same70q21b.c'] + src += [cwd + '/same70b/gcc/gcc/startup_same70q21b.c'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [cwd + '/same70b/armcc/Source/' + 'system_same70q21b.c'] + src += [cwd + '/same70b/armcc/Source/ARM/' + 'startup_SAME70.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [cwd + '/same70b/iar/' + 'system_same70q21b.c'] + src += [cwd + '/same70b/iar/iar/' + 'startup_same70q21b.c'] + +path = [ + cwd, + cwd + '/CMSIS/Core/Include', + cwd + '/config', + cwd + '/hal/include', + cwd + '/hal/utils/include', + cwd + '/hpl/core', + cwd + '/hpl/mcan', + cwd + '/hpl/pio', + cwd + '/hpl/pmc', + cwd + '/hpl/systick', + cwd + '/hpl/usart', + cwd + '/hri', + cwd + '/same70b/include',] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/microchip/same70/bsp/atmel_start.c b/bsp/microchip/same70/bsp/atmel_start.c new file mode 100644 index 0000000000..79f252aed9 --- /dev/null +++ b/bsp/microchip/same70/bsp/atmel_start.c @@ -0,0 +1,9 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/bsp/microchip/same70/bsp/atmel_start.h b/bsp/microchip/same70/bsp/atmel_start.h new file mode 100644 index 0000000000..0de62f528d --- /dev/null +++ b/bsp/microchip/same70/bsp/atmel_start.h @@ -0,0 +1,18 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/microchip/same70/bsp/atmel_start_config.atstart b/bsp/microchip/same70/bsp/atmel_start_config.atstart new file mode 100644 index 0000000000..fdb95a78d9 --- /dev/null +++ b/bsp/microchip/same70/bsp/atmel_start_config.atstart @@ -0,0 +1,585 @@ +format_version: '2' +name: SAME70 LED switcher +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: SAME70Xplained + device: ATSAME70Q21B-AN +details: null +application: + definition: 'Atmel:Application_Examples:0.0.1::Application:LED_switcher:' + configuration: null +middlewares: {} +drivers: + PMC: + user_label: PMC + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::PMC::driver_config_definition::PMC::HAL:HPL:PMC + functionality: System + api: HAL:HPL:PMC + configuration: + $input: 240000000 + $input_id: UDPLL with Divider (MCKR UPLLDIV2) + RESERVED_InputFreq: 240000000 + RESERVED_InputFreq_id: UDPLL with Divider (MCKR UPLLDIV2) + _$freq_output_32kHz External Crystal Oscillator (XOSC32K): 0 + _$freq_output_32kHz High Accuracy Internal Oscillator (OSC32K): 0 + _$freq_output_Embedded 4/8/12MHz RC Oscillator (OSC12M): '12000000' + _$freq_output_External 3-20MHz Oscillator (XOSC20M): 12000000 + _$freq_output_External Clock: 1 + _$freq_output_Generic Clock 0 (GCLK0) for I2SC0: 75000000 + _$freq_output_Generic Clock 1 (GCLK1) for I2SC1: 100000000 + _$freq_output_MCK / 8 for USART: 18750000 + _$freq_output_Master Clock (MCK): 150000000 + _$freq_output_Master Clock Controller (PMC_MCKR): 300000000 + _$freq_output_PLLA Clock (PLLACK): 300000000 + _$freq_output_Programmable Clock Controller 0 (PMC_PCK0): 12000000 + _$freq_output_Programmable Clock Controller 1 (PMC_PCK1): 6000000 + _$freq_output_Programmable Clock Controller 2 (PMC_PCK2): 4000000 + _$freq_output_Programmable Clock Controller 3 (PMC_PCK3): 3000000 + _$freq_output_Programmable Clock Controller 4 (PMC_PCK4): 2400000 + _$freq_output_Programmable Clock Controller 5 (PMC_PCK5): 40000000 + _$freq_output_Programmable Clock Controller 6 (PMC_PCK6): 1714285.7142857143 + _$freq_output_SysTick External Clock: 37500000 + _$freq_output_UDPLL with Divider (MCKR UPLLDIV2): 240000000 + _$freq_output_USB 480M Clock (UPLLCK): 480000000 + _$freq_output_USB Clock Controller (USB_48M): 300000000 + clk_gen_cfden_enable: false + clk_gen_fclk_oscillator: Master Clock Controller (PMC_MCKR) + clk_gen_gclk0_arch_enable: true + clk_gen_gclk0_oscillator: Master Clock (MCK) + clk_gen_gclk1_arch_enable: true + clk_gen_gclk1_oscillator: PLLA Clock (PLLACK) + clk_gen_mainck_arch_enable: true + clk_gen_mainck_oscillator: External 3-20MHz Oscillator (XOSC20M) + clk_gen_mck_oscillator: Master Clock Controller (PMC_MCKR) + clk_gen_mckr_arch_enable: true + clk_gen_mckr_oscillator: PLLA Clock (PLLACK) + clk_gen_pck0_arch_enable: false + clk_gen_pck0_oscillator: Main Clock (MAINCK) + clk_gen_pck1_arch_enable: false + clk_gen_pck1_oscillator: Main Clock (MAINCK) + clk_gen_pck2_arch_enable: false + clk_gen_pck2_oscillator: Main Clock (MAINCK) + clk_gen_pck3_arch_enable: false + clk_gen_pck3_oscillator: Main Clock (MAINCK) + clk_gen_pck4_arch_enable: false + clk_gen_pck4_oscillator: Main Clock (MAINCK) + clk_gen_pck5_arch_enable: true + clk_gen_pck5_oscillator: UDPLL with Divider (MCKR UPLLDIV2) + clk_gen_pck6_arch_enable: false + clk_gen_pck6_oscillator: Main Clock (MAINCK) + clk_gen_slck2_oscillator: Slow Clock (SLCK) + clk_gen_slck_arch_enable: true + clk_gen_slck_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K) + clk_gen_systick_oscillator: Master Clock Controller (PMC_MCKR) + clk_gen_usb_480m_oscillator: USB 480M Clock (UPLLCK) + clk_gen_usb_48m_arch_enable: false + clk_gen_usb_48m_oscillator: PLLA Clock (PLLACK) + dummy_ext_clk_src: External Clock Input + dummy_ext_src: Specific clock input from specific pin + efc_fws: 6 cycles + enable_clk_gen_fclk: true + enable_clk_gen_gclk0: true + enable_clk_gen_gclk1: true + enable_clk_gen_mainck: true + enable_clk_gen_mck: true + enable_clk_gen_mckr: true + enable_clk_gen_pck0: true + enable_clk_gen_pck1: true + enable_clk_gen_pck2: true + enable_clk_gen_pck3: true + enable_clk_gen_pck4: true + enable_clk_gen_pck5: true + enable_clk_gen_pck6: true + enable_clk_gen_slck: true + enable_clk_gen_slck2: true + enable_clk_gen_systick: true + enable_clk_gen_usb_480m: true + enable_clk_gen_usb_48m: true + enable_dummy_ext: true + enable_dummy_ext_clk: true + enable_hclk_clock: true + enable_mck_div_8: false + enable_osc12m: false + enable_osc32k: true + enable_pllack: true + enable_systick_clk_clock: true + enable_upllck: true + enable_upllckdiv: true + enable_xosc20m: true + enable_xosc32k: false + gclk0_div: 2 + gclk0_gclken_enable: false + gclk1_div: 3 + gclk1_gclken_enable: false + hclk_clock_source: Master Clock Controller (PMC_MCKR) + mck_div: '2' + mck_div_8_src: Master Clock (MCK) + mckr_presc: '1' + osc12m_arch_enable: false + osc12m_selector: '12000000' + osc32k_arch_enable: false + pck0_presc: 1 + pck1_presc: 2 + pck2_presc: 3 + pck3_presc: 4 + pck4_presc: 5 + pck5_presc: 6 + pck6_presc: 7 + pllack_arch_enable: true + pllack_div: 1 + pllack_mul: 25 + pllack_ref_clock: Main Clock (MAINCK) + systick_clk_clock_div: '8' + systick_clk_clock_source: Master Clock Controller (PMC_MCKR) + systick_clock_div: '8' + upllck_arch_enable: true + upllck_ref_clock: External 3-20MHz Oscillator (XOSC20M) + upllckdiv_div: '2' + upllckdiv_ref_clock: USB 480M Clock (UPLLCK) + usb_48m_div: 1 + xosc20m_arch_enable: true + xosc20m_bypass: The external crystal oscillator is not bypassed. + xosc20m_selector: 12000000 + xosc20m_startup_time: 62 + xosc32k_arch_enable: false + xosc32k_bypass: The 32kHz crystal oscillator is not bypassed. + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + DELAY_0: + user_label: DELAY_0 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::SysTick::driver_config_definition::Delay::HAL:Driver:Delay + functionality: Delay + api: HAL:Driver:Delay + configuration: + systick_arch_tickint: false + optional_signals: [] + variant: null + clocks: + domain_group: null + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::USART1::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_9bits_enable: false + usart__inack: The NACK is not generated + usart__oversampling_mode: 16 Oversampling + usart_advanced: false + usart_arch_fractional: 0 + usart_arch_msbf: LSB is transmitted first + usart_baud_rate: 115200 + usart_channel_mode: Normal Mode + usart_character_size: 8 bits + usart_clock_output_select: The USART does not drive the SCK pin + usart_dsnack: NACK is sent on the ISO line as soon as a parity error occurs + usart_invdata: Data isn't inverted, nomal mode + usart_manchester_filter_enable: false + usart_manchester_synchronization_mode: The Manchester start bit is a 0 to 1 + transition + usart_max_iteration: 0 + usart_parity: No parity + usart_receive_filter_enable: false + usart_start_frame_delimiter: Start frame delimiter is COMMAND or DATA SYNC + usart_stop_bit: 1 stop bit + variable_sync: User defined configuration + optional_signals: + - identifier: TARGET_IO:RXD/1 + pad: PA21 + mode: Enabled + configuration: null + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::USART1.RXD.1 + name: USART1/RXD/1 + label: RXD/1 + - identifier: TARGET_IO:TXD/1 + pad: PB4 + mode: Enabled + configuration: null + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::USART1.TXD.1 + name: USART1/TXD/1 + label: TXD/1 + variant: null + clocks: + domain_group: + nodes: + - name: USART + input: Master Clock (MCK) + external: false + external_frequency: 0 + configuration: + usart_clock_source: Master Clock (MCK) + XDMAC: + user_label: XDMAC + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::XDMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dma_des_interface_0: AHB_IF0 + dma_des_interface_1: AHB_IF0 + dma_des_interface_10: AHB_IF0 + dma_des_interface_11: AHB_IF0 + dma_des_interface_12: AHB_IF0 + dma_des_interface_13: AHB_IF0 + dma_des_interface_14: AHB_IF0 + dma_des_interface_15: AHB_IF0 + dma_des_interface_16: AHB_IF0 + dma_des_interface_17: AHB_IF0 + dma_des_interface_18: AHB_IF0 + dma_des_interface_19: AHB_IF0 + dma_des_interface_2: AHB_IF0 + dma_des_interface_20: AHB_IF0 + dma_des_interface_21: AHB_IF0 + dma_des_interface_22: AHB_IF0 + dma_des_interface_23: AHB_IF0 + dma_des_interface_3: AHB_IF0 + dma_des_interface_4: AHB_IF0 + dma_des_interface_5: AHB_IF0 + dma_des_interface_6: AHB_IF0 + dma_des_interface_7: AHB_IF0 + dma_des_interface_8: AHB_IF0 + dma_des_interface_9: AHB_IF0 + dma_src_interface_0: AHB_IF0 + dma_src_interface_1: AHB_IF0 + dma_src_interface_10: AHB_IF0 + dma_src_interface_11: AHB_IF0 + dma_src_interface_12: AHB_IF0 + dma_src_interface_13: AHB_IF0 + dma_src_interface_14: AHB_IF0 + dma_src_interface_15: AHB_IF0 + dma_src_interface_16: AHB_IF0 + dma_src_interface_17: AHB_IF0 + dma_src_interface_18: AHB_IF0 + dma_src_interface_19: AHB_IF0 + dma_src_interface_2: AHB_IF0 + dma_src_interface_20: AHB_IF0 + dma_src_interface_21: AHB_IF0 + dma_src_interface_22: AHB_IF0 + dma_src_interface_23: AHB_IF0 + dma_src_interface_3: AHB_IF0 + dma_src_interface_4: AHB_IF0 + dma_src_interface_5: AHB_IF0 + dma_src_interface_6: AHB_IF0 + dma_src_interface_7: AHB_IF0 + dma_src_interface_8: AHB_IF0 + dma_src_interface_9: AHB_IF0 + dma_trans_type_0: Memory to Memory Transfer + dma_trans_type_1: Memory to Memory Transfer + dma_trans_type_10: Memory to Memory Transfer + dma_trans_type_11: Memory to Memory Transfer + dma_trans_type_12: Memory to Memory Transfer + dma_trans_type_13: Memory to Memory Transfer + dma_trans_type_14: Memory to Memory Transfer + dma_trans_type_15: Memory to Memory Transfer + dma_trans_type_16: Memory to Memory Transfer + dma_trans_type_17: Memory to Memory Transfer + dma_trans_type_18: Memory to Memory Transfer + dma_trans_type_19: Memory to Memory Transfer + dma_trans_type_2: Memory to Memory Transfer + dma_trans_type_20: Memory to Memory Transfer + dma_trans_type_21: Memory to Memory Transfer + dma_trans_type_22: Memory to Memory Transfer + dma_trans_type_23: Memory to Memory Transfer + dma_trans_type_3: Memory to Memory Transfer + dma_trans_type_4: Memory to Memory Transfer + dma_trans_type_5: Memory to Memory Transfer + dma_trans_type_6: Memory to Memory Transfer + dma_trans_type_7: Memory to Memory Transfer + dma_trans_type_8: Memory to Memory Transfer + dma_trans_type_9: Memory to Memory Transfer + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_burstsize_0: 1 burst size + dmac_burstsize_1: 1 burst size + dmac_burstsize_10: 1 burst size + dmac_burstsize_11: 1 burst size + dmac_burstsize_12: 1 burst size + dmac_burstsize_13: 1 burst size + dmac_burstsize_14: 1 burst size + dmac_burstsize_15: 1 burst size + dmac_burstsize_16: 1 burst size + dmac_burstsize_17: 1 burst size + dmac_burstsize_18: 1 burst size + dmac_burstsize_19: 1 burst size + dmac_burstsize_2: 1 burst size + dmac_burstsize_20: 1 burst size + dmac_burstsize_21: 1 burst size + dmac_burstsize_22: 1 burst size + dmac_burstsize_23: 1 burst size + dmac_burstsize_3: 1 burst size + dmac_burstsize_4: 1 burst size + dmac_burstsize_5: 1 burst size + dmac_burstsize_6: 1 burst size + dmac_burstsize_7: 1 burst size + dmac_burstsize_8: 1 burst size + dmac_burstsize_9: 1 burst size + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_chunksize_0: 1 data transferred + dmac_chunksize_1: 1 data transferred + dmac_chunksize_10: 1 data transferred + dmac_chunksize_11: 1 data transferred + dmac_chunksize_12: 1 data transferred + dmac_chunksize_13: 1 data transferred + dmac_chunksize_14: 1 data transferred + dmac_chunksize_15: 1 data transferred + dmac_chunksize_16: 1 data transferred + dmac_chunksize_17: 1 data transferred + dmac_chunksize_18: 1 data transferred + dmac_chunksize_19: 1 data transferred + dmac_chunksize_2: 1 data transferred + dmac_chunksize_20: 1 data transferred + dmac_chunksize_21: 1 data transferred + dmac_chunksize_22: 1 data transferred + dmac_chunksize_23: 1 data transferred + dmac_chunksize_3: 1 data transferred + dmac_chunksize_4: 1 data transferred + dmac_chunksize_5: 1 data transferred + dmac_chunksize_6: 1 data transferred + dmac_chunksize_7: 1 data transferred + dmac_chunksize_8: 1 data transferred + dmac_chunksize_9: 1 data transferred + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_trifsrc_0: Software Trigger + dmac_trifsrc_1: Software Trigger + dmac_trifsrc_10: Software Trigger + dmac_trifsrc_11: Software Trigger + dmac_trifsrc_12: Software Trigger + dmac_trifsrc_13: Software Trigger + dmac_trifsrc_14: Software Trigger + dmac_trifsrc_15: Software Trigger + dmac_trifsrc_16: Software Trigger + dmac_trifsrc_17: Software Trigger + dmac_trifsrc_18: Software Trigger + dmac_trifsrc_19: Software Trigger + dmac_trifsrc_2: Software Trigger + dmac_trifsrc_20: Software Trigger + dmac_trifsrc_21: Software Trigger + dmac_trifsrc_22: Software Trigger + dmac_trifsrc_23: Software Trigger + dmac_trifsrc_3: Software Trigger + dmac_trifsrc_4: Software Trigger + dmac_trifsrc_5: Software Trigger + dmac_trifsrc_6: Software Trigger + dmac_trifsrc_7: Software Trigger + dmac_trifsrc_8: Software Trigger + dmac_trifsrc_9: Software Trigger + xdmac_enable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + CAN_0: + user_label: CAN_0 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::MCAN1::driver_config_definition::CAN::HAL:Driver:CAN.Async + functionality: CAN + api: HAL:Driver:CAN_Async + configuration: + can_cccr_niso: ISO11898_1 + can_dbtp_dbrp: 1 + can_dbtp_dsjw: 4 + can_dbtp_dtseg1: 31 + can_dbtp_dtseg2: 8 + can_dbtp_tdc: false + can_gfc_anfe: Reject + can_gfc_anfs: Reject + can_gfc_rrfe: Filter remote frames with 29-bit standard IDs + can_gfc_rrfs: Filter remote frames with 11-bit standard IDs + can_ie_bo: true + can_ie_do: true + can_ie_ea: true + can_ie_ep: true + can_ie_ew: true + can_nbtp_nbrp: 4 + can_nbtp_nsjw: 10 + can_nbtp_ntseg1: 31 + can_nbtp_ntseg2: 8 + can_rxesc_f0ds: 8 byte data field. + can_rxf0c_f0om: blocking mode + can_rxf0c_f0s: 32 + can_rxf0c_f0wm: 0 + can_sidfc_lss: 128 + can_tdcr_tdcf: 11 + can_tdcr_tdco: 11 + can_txbc_tfqs: 32 + can_txefc_efs: 32 + can_txefc_efwm: 0 + can_txesc_tbds: 8 byte data field. + can_xidam_eidm: 0 + can_xidfc_lss: 64 + optional_signals: + - identifier: CAN_0:CANRX/1 + pad: PC12 + mode: Enabled + configuration: null + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::MCAN1.CANRX.1 + name: MCAN1/CANRX/1 + label: CANRX/1 + - identifier: CAN_0:CANTX/1 + pad: PC14 + mode: Enabled + configuration: null + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::optional_signal_definition::MCAN1.CANTX.1 + name: MCAN1/CANTX/1 + label: CANTX/1 + variant: null + clocks: + domain_group: + nodes: + - name: MCAN + input: Programmable Clock Controller 5 (PMC_PCK5) + external: false + external_frequency: 0 + configuration: + mcan_clock_source: Programmable Clock Controller 5 (PMC_PCK5) +pads: + PC12: + name: PC12 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC12 + mode: Peripheral IO + user_label: PC12 + configuration: null + PA21: + name: PA21 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PA21 + mode: Peripheral IO + user_label: PA21 + configuration: null + SW0: + name: PA11 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PA11 + mode: Digital input + user_label: SW0 + configuration: + pad_pull_config: Pull-up + LED0: + name: PC8 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC8 + mode: Digital output + user_label: LED0 + configuration: + pad_initial_level: High + PC14: + name: PC14 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PC14 + mode: Peripheral IO + user_label: PC14 + configuration: null + PB4: + name: PB4 + definition: Atmel:SAME70B_Drivers:0.0.1::ATSAME70Q21B-AN::pad::PB4 + mode: Peripheral IO + user_label: PB4 + configuration: null +toolchain_options: [] +static_files: [] diff --git a/bsp/microchip/same70/bsp/atmel_start_pins.h b/bsp/microchip/same70/bsp/atmel_start_pins.h new file mode 100644 index 0000000000..5a93767aeb --- /dev/null +++ b/bsp/microchip/same70/bsp/atmel_start_pins.h @@ -0,0 +1,27 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAME70 has 4 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 + +#define SW0 GPIO(GPIO_PORTA, 11) +#define PA21 GPIO(GPIO_PORTA, 21) +#define PB4 GPIO(GPIO_PORTB, 4) +#define LED0 GPIO(GPIO_PORTC, 8) +#define PC12 GPIO(GPIO_PORTC, 12) +#define PC14 GPIO(GPIO_PORTC, 14) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/bsp/microchip/same70/bsp/config/hpl_mcan_config.h b/bsp/microchip/same70/bsp/config/hpl_mcan_config.h new file mode 100644 index 0000000000..5f99865ebb --- /dev/null +++ b/bsp/microchip/same70/bsp/config/hpl_mcan_config.h @@ -0,0 +1,379 @@ +/* Auto-generated config file hpl_mcan_config.h */ +#ifndef HPL_MCAN_CONFIG_H +#define HPL_MCAN_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_CAN1_ENABLED +#define CONF_CAN1_ENABLED 1 +#endif +// Basic Configuration + +// CAN Mode Enable +// decide whether enable CAN FD mode +// <0=> ISO11898_1 +// <1=> FD +// can_cccr_niso +#ifndef CONF_CAN1_CCCR_NISO +#define CONF_CAN1_CCCR_NISO 0 +#endif + +// + +// Normal Bit Timing and Prescaler Configuration + +// Baud Rate Prescaler <1-512> +// The value by which the oscillator frequency is divided for generating the CAN time quanta. CAN time quantum (tq) = (This value) x CAN core clock cycles (tcore clock) +// can_nbtp_nbrp +#ifndef CONF_CAN1_NBTP_NBRP +#define CONF_CAN1_NBTP_NBRP 4 +#endif + +// time segment before sample point <2-256> +// The duration of time segment = (This value) x CAN time quantum (tq) +// can_nbtp_ntseg1 +#ifndef CONF_CAN1_NBTP_NTSEG1 +#define CONF_CAN1_NBTP_NTSEG1 31 +#endif + +// time segment after sample point <2-128> +// The duration of time segment = (This value) x CAN time quantum (tq) +// can_nbtp_ntseg2 +#ifndef CONF_CAN1_NBTP_NTSEG2 +#define CONF_CAN1_NBTP_NTSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-128> +// The duration of a synchronization jump = (This value) x CAN time quantum (tq) +// can_nbtp_nsjw +#ifndef CONF_CAN1_NBTP_NSJW +#define CONF_CAN1_NBTP_NSJW 10 +#endif + +// +// Data Bit Timing and Prescaler Configuration + +// Data Baud Rate Prescaler <1-32> +// The value by which the peripheral clock is divided for generating the bit time quanta. CAN time quantum (tq) = (This value) x CAN core clock cycles (tcore clock) +// can_dbtp_dbrp +#ifndef CONF_CAN1_DBTP_DBRP +#define CONF_CAN1_DBTP_DBRP 1 +#endif + +// Data time segment before sample point <2-32> +// The duration of time segment = (This value) x CAN time quantum (tq) +// can_dbtp_dtseg1 +#ifndef CONF_CAN1_DBTP_DTSEG1 +#define CONF_CAN1_DBTP_DTSEG1 31 +#endif + +// Data time segment after sample point <1-16> +// The duration of time segment = (This value) x CAN time quantum (tq) +// can_dbtp_dtseg2 +#ifndef CONF_CAN1_DBTP_DTSEG2 +#define CONF_CAN1_DBTP_DTSEG2 8 +#endif + +// Data (Re)Syncronization Jump Width <1-8> +// The duration of a synchronization jump = (This value) x CAN time quantum (tq) +// can_dbtp_dsjw +#ifndef CONF_CAN1_DBTP_DSJW +#define CONF_CAN1_DBTP_DSJW 4 +#endif + +// Transceiver Delay Compensation Enable +// Transceiver Delay Compensation Enable +// can_dbtp_tdc +#ifndef CONF_CAN1_DBTP_TDC +#define CONF_CAN1_DBTP_TDC 0 +#endif + +// Transceiver Delay Compensation Offset <0-127> +// Transceiver Delay Compensation Offset +// can_tdcr_tdco +#ifndef CONF_CAN1_TDCR_TDCO +#define CONF_CAN1_TDCR_TDCO 11 +#endif + +// Transmitter Delay Compensation Filter <0-127> +// Transmitter Delay Compensation Filter +// can_tdcr_tdcf +#ifndef CONF_CAN1_TDCR_TDCF +#define CONF_CAN1_TDCR_TDCF 11 +#endif + +// + +// RX FIFO Configuration + +// Operation Mode +// Select Operation Mode +// <0=> blocking mode +// <1=> overwrite mode +// can_rxf0c_f0om +#ifndef CONF_CAN1_RXF0C_F0OM +#define CONF_CAN1_RXF0C_F0OM 0 +#endif + +// Watermark <0-64> +// Watermark, 0 for disable watermark interrupt +// can_rxf0c_f0wm +#ifndef CONF_CAN1_RXF0C_F0WM +#define CONF_CAN1_RXF0C_F0WM 0 +#endif + +// Size <0-64> +// Number of Rx FIFO 0 element +// can_rxf0c_f0s +#ifndef CONF_CAN1_RXF0C_F0S +#define CONF_CAN1_RXF0C_F0S 32 +#endif + +// Data Field Size +// Rx FIFO 0 Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_rxesc_f0ds +#ifndef CONF_CAN1_RXESC_F0DS +#define CONF_CAN1_RXESC_F0DS 0 +#endif + +/* Bytes size for CAN FIFO 0 element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN1_F0DS +#define CONF_CAN1_F0DS \ + ((CONF_CAN1_RXESC_F0DS < 5) ? ((CONF_CAN1_RXESC_F0DS << 2) + 16) : (40 + ((CONF_CAN1_RXESC_F0DS % 5) << 4))) + +// + +// TX FIFO Configuration + +// Transmit FIFO Size <0-32> +// Number of Tx Buffers used for Tx FIFO +// can_txbc_tfqs +#ifndef CONF_CAN1_TXBC_TFQS +#define CONF_CAN1_TXBC_TFQS 32 +#endif + +// Tx Buffer Data Field Size +// Tx Buffer Data Field Size +// <0=> 8 byte data field. +// <1=> 12 byte data field. +// <2=> 16 byte data field. +// <3=> 20 byte data field. +// <4=> 24 byte data field. +// <5=> 32 byte data field. +// <6=> 48 byte data field. +// <7=> 64 byte data field. +// can_txesc_tbds +#ifndef CONF_CAN1_TXESC_TBDS +#define CONF_CAN1_TXESC_TBDS 0 +#endif + +/* Bytes size for CAN Transmit Buffer element, plus 8 bytes for R0,R1 */ +#undef CONF_CAN1_TBDS +#define CONF_CAN1_TBDS \ + ((CONF_CAN1_TXESC_TBDS < 5) ? ((CONF_CAN1_TXESC_TBDS << 2) + 16) : (40 + ((CONF_CAN1_TXESC_TBDS % 5) << 4))) + +// + +// TX Event Configuration + +// Watermark <0-32> +// Watermark, 0 for disable watermark interrupt +// can_txefc_efwm +#ifndef CONF_CAN1_TXEFC_EFWM +#define CONF_CAN1_TXEFC_EFWM 0 +#endif + +// Size <0-32> +// Number of Event FIFO element +// can_txefc_efs +#ifndef CONF_CAN1_TXEFC_EFS +#define CONF_CAN1_TXEFC_EFS 32 +#endif + +// + +// Filter Configuration + +// Accept Non-matching Frames Standard +// Defines how received messages with 11-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfs +#ifndef CONF_CAN1_GFC_ANFS +#define CONF_CAN1_GFC_ANFS 2 +#endif + +// Accept Non-matching Frames Extended +// Defines how received messages with 29-bit IDs that do not match any +// element of the filter list are treated. +// <0=> Accept in Rx FIFO 0 +// <1=> Accept in Rx FIFO 1 +// <2=> Reject +// can_gfc_anfe +#ifndef CONF_CAN1_GFC_ANFE +#define CONF_CAN1_GFC_ANFE 2 +#endif + +// Reject Remote Frames Standard +// Defines how received remote frames with 11-bit standard IDs. +// <0=> Filter remote frames with 11-bit standard IDs +// <1=> Reject all remote frames with 11-bit standard IDs +// can_gfc_rrfs +#ifndef CONF_CAN1_GFC_RRFS +#define CONF_CAN1_GFC_RRFS 0 +#endif + +// Reject Remote Frames Extended +// Defines how received remote frames with 29-bit standard IDs. +// <0=> Filter remote frames with 29-bit standard IDs +// <1=> Reject all remote frames with 29-bit standard IDs +// can_gfc_rrfe +#ifndef CONF_CAN1_GFC_RRFE +#define CONF_CAN1_GFC_RRFE 0 +#endif + +// Number of standard Message ID filter elements <0-128> +// Number of standard Message ID filter elements +// can_sidfc_lss +#ifndef CONF_CAN1_SIDFC_LSS +#define CONF_CAN1_SIDFC_LSS 128 +#endif + +// Number of Extended Message ID filter elements <0-64> +// Number of Extended Message ID filter elements +// can_xidfc_lss +#ifndef CONF_CAN1_XIDFC_LSS +#define CONF_CAN1_XIDFC_LSS 64 +#endif + +// Extended ID Mask <0x0000-0x1FFFFFFF> +// For acceptance filtering of extended frames the Extended ID AND Mask is +// ANDed with the Message ID of a received frame. Intended for masking of +// 29-bit IDs in SAE J1939. With the reset value of all bits set to one the +// mask is not active. +// can_xidam_eidm +#ifndef CONF_CAN1_XIDAM_EIDM +#define CONF_CAN1_XIDAM_EIDM 0x0 +#endif + +// + +// Interrupt Configuration + +// Error Warning +// Indicates whether to not disable CAN error warning interrupt +// can_ie_ew +#ifndef CONF_CAN1_IE_EW +#define CONF_CAN1_IE_EW 1 +#endif + +// Error Active +// Indicates whether to not disable CAN error active interrupt +// can_ie_ea +#ifndef CONF_CAN1_IE_EA +#define CONF_CAN1_IE_EA 1 +#endif + +// Error Passive +// Indicates whether to not disable CAN error passive interrupt +// can_ie_ep +#ifndef CONF_CAN1_IE_EP +#define CONF_CAN1_IE_EP 1 +#endif + +// Bus Off +// Indicates whether to not disable CAN bus off interrupt +// can_ie_bo +#ifndef CONF_CAN1_IE_BO +#define CONF_CAN1_IE_BO 1 +#endif + +// Data Overrun +// Indicates whether to not disable CAN data overrun interrupt +// can_ie_do +#ifndef CONF_CAN1_IE_DO +#define CONF_CAN1_IE_DO 1 +#endif + +// + +#ifndef CONF_CAN1_CCCR_REG +#define CONF_CAN1_CCCR_REG (CONF_CAN1_CCCR_NISO << MCAN_CCCR_NISO_Pos) +#endif + +#ifndef CONF_CAN1_NBTP_REG +#define CONF_CAN1_NBTP_REG \ + MCAN_NBTP_NBRP(CONF_CAN1_NBTP_NBRP - 1) | MCAN_NBTP_NTSEG1(CONF_CAN1_NBTP_NTSEG1 - 1) \ + | MCAN_NBTP_NTSEG2(CONF_CAN1_NBTP_NTSEG2 - 1) | MCAN_NBTP_NSJW(CONF_CAN1_NBTP_NSJW - 1) +#endif + +#ifndef CONF_CAN1_DBTP_REG +#define CONF_CAN1_DBTP_REG \ + (CONF_CAN1_DBTP_TDC << MCAN_DBTP_TDC_Pos) | MCAN_DBTP_DBRP(CONF_CAN1_DBTP_DBRP - 1) \ + | MCAN_DBTP_DTSEG1(CONF_CAN1_DBTP_DTSEG1 - 1) | MCAN_DBTP_DTSEG2(CONF_CAN1_DBTP_DTSEG2 - 1) \ + | MCAN_DBTP_DSJW(CONF_CAN1_DBTP_DSJW - 1) +#endif + +#ifndef CONF_CAN1_TDCR_REG +#define CONF_CAN1_TDCR_REG MCAN_TDCR_TDCF(CONF_CAN1_TDCR_TDCF) | MCAN_TDCR_TDCO(CONF_CAN1_TDCR_TDCO) +#endif + +#ifndef CONF_CAN1_RXF0C_REG +#define CONF_CAN1_RXF0C_REG \ + (CONF_CAN1_RXF0C_F0OM << MCAN_RXF0C_F0OM_Pos) | MCAN_RXF0C_F0WM(CONF_CAN1_RXF0C_F0WM) \ + | MCAN_RXF0C_F0S(CONF_CAN1_RXF0C_F0S) +#endif + +#ifndef CONF_CAN1_RXESC_REG +#define CONF_CAN1_RXESC_REG MCAN_RXESC_F0DS(CONF_CAN1_RXESC_F0DS) +#endif + +#ifndef CONF_CAN1_TXESC_REG +#define CONF_CAN1_TXESC_REG MCAN_TXESC_TBDS(CONF_CAN1_TXESC_TBDS) +#endif + +#ifndef CONF_CAN1_TXBC_REG +#define CONF_CAN1_TXBC_REG MCAN_TXBC_TFQS(CONF_CAN1_TXBC_TFQS) +#endif + +#ifndef CONF_CAN1_TXEFC_REG +#define CONF_CAN1_TXEFC_REG MCAN_TXEFC_EFWM(CONF_CAN1_TXEFC_EFWM) | MCAN_TXEFC_EFS(CONF_CAN1_TXEFC_EFS) +#endif + +#ifndef CONF_CAN1_GFC_REG +#define CONF_CAN1_GFC_REG \ + MCAN_GFC_ANFS(CONF_CAN1_GFC_ANFS) | MCAN_GFC_ANFE(CONF_CAN1_GFC_ANFE) | (CONF_CAN1_GFC_RRFS << MCAN_GFC_RRFS_Pos) \ + | (CONF_CAN1_GFC_RRFE << MCAN_GFC_RRFE_Pos) +#endif + +#ifndef CONF_CAN1_SIDFC_REG +#define CONF_CAN1_SIDFC_REG MCAN_SIDFC_LSS(CONF_CAN1_SIDFC_LSS) +#endif + +#ifndef CONF_CAN1_XIDFC_REG +#define CONF_CAN1_XIDFC_REG MCAN_XIDFC_LSE(CONF_CAN1_XIDFC_LSS) +#endif + +#ifndef CONF_CAN1_XIDAM_REG +#define CONF_CAN1_XIDAM_REG MCAN_XIDAM_EIDM(CONF_CAN1_XIDAM_EIDM) +#endif + +#ifndef CONF_CAN0_IE_REG +#define CONF_CAN0_IE_REG \ + (CONF_CAN1_IE_EW << MCAN_IR_EW_Pos) | (CONF_CAN1_IE_EA << MCAN_IR_EP_Pos) | (CONF_CAN1_IE_EP << MCAN_IR_EP_Pos) \ + | (CONF_CAN1_IE_BO << MCAN_IR_BO_Pos) | (CONF_CAN1_IE_DO << MCAN_IR_RF0L_Pos) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_MCAN_CONFIG_H diff --git a/bsp/microchip/same70/bsp/config/hpl_pmc_config.h b/bsp/microchip/same70/bsp/config/hpl_pmc_config.h new file mode 100644 index 0000000000..b8e82184f3 --- /dev/null +++ b/bsp/microchip/same70/bsp/config/hpl_pmc_config.h @@ -0,0 +1,1053 @@ +/* Auto-generated config file hpl_pmc_config.h */ +#ifndef HPL_PMC_CONFIG_H +#define HPL_PMC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#define CLK_SRC_OPTION_OSC32K 0 +#define CLK_SRC_OPTION_XOSC32K 1 +#define CLK_SRC_OPTION_OSC12M 2 +#define CLK_SRC_OPTION_XOSC20M 3 + +#define CLK_SRC_OPTION_SLCK 0 +#define CLK_SRC_OPTION_MAINCK 1 +#define CLK_SRC_OPTION_PLLACK 2 +#define CLK_SRC_OPTION_UPLLCKDIV 3 +#define CLK_SRC_OPTION_MCK 4 + +#define CLK_SRC_OPTION_UPLLCK 3 + +#define CONF_RC_4M 0 +#define CONF_RC_8M 1 +#define CONF_RC_12M 2 + +#define CONF_XOSC32K_NO_BYPASS 0 +#define CONF_XOSC32K_BYPASS 1 + +#define CONF_XOSC20M_NO_BYPASS 0 +#define CONF_XOSC20M_BYPASS 1 + +// Clock_SLCK configuration +// Indicates whether SLCK configuration is enabled or not +// enable_clk_gen_slck +#ifndef CONF_CLK_SLCK_CONFIG +#define CONF_CLK_SLCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator SLCK source + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// This defines the clock source for SLCK +// clk_gen_slck_oscillator +#ifndef CONF_CLK_GEN_SLCK_SRC +#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K +#endif + +// Enable Clock_SLCK +// Indicates whether SLCK is enabled or disable +// clk_gen_slck_arch_enable +#ifndef CONF_CLK_SLCK_ENABLE +#define CONF_CLK_SLCK_ENABLE 1 +#endif + +// + +// + +// +// // Clock_MAINCK configuration +// Indicates whether MAINCK configuration is enabled or not +// enable_clk_gen_mainck +#ifndef CONF_CLK_MAINCK_CONFIG +#define CONF_CLK_MAINCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator MAINCK source + +// Embedded 4/8/12MHz RC Oscillator (OSC12M) + +// External 3-20MHz Oscillator (XOSC20M) + +// This defines the clock source for MAINCK +// clk_gen_mainck_oscillator +#ifndef CONF_CLK_GEN_MAINCK_SRC +#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M +#endif + +// Enable Clock_MAINCK +// Indicates whether MAINCK is enabled or disable +// clk_gen_mainck_arch_enable +#ifndef CONF_CLK_MAINCK_ENABLE +#define CONF_CLK_MAINCK_ENABLE 1 +#endif + +// Enable Main Clock Failure Detection +// Indicates whether Main Clock Failure Detection is enabled or disable. +// The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK. +// clk_gen_cfden_enable +#ifndef CONF_CLK_CFDEN_ENABLE +#define CONF_CLK_CFDEN_ENABLE 0 +#endif + +// + +// + +// +// // Clock_MCKR configuration +// Indicates whether MCKR configuration is enabled or not +// enable_clk_gen_mckr +#ifndef CONF_CLK_MCKR_CONFIG +#define CONF_CLK_MCKR_CONFIG 1 +#endif + +// Clock Generator +// clock generator MCKR source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// PLLA Clock (PLLACK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// This defines the clock source for MCKR +// clk_gen_mckr_oscillator +#ifndef CONF_CLK_GEN_MCKR_SRC +#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK +#endif + +// Enable Clock_MCKR +// Indicates whether MCKR is enabled or disable +// clk_gen_mckr_arch_enable +#ifndef CONF_CLK_MCKR_ENABLE +#define CONF_CLK_MCKR_ENABLE 1 +#endif + +// + +// + +// Master Clock Prescaler +// <0=> 1 +// <1=> 2 +// <2=> 4 +// <3=> 8 +// <4=> 16 +// <5=> 32 +// <6=> 64 +// <7=> 3 +// Select the clock prescaler. +// mckr_presc +#ifndef CONF_MCKR_PRESC +#define CONF_MCKR_PRESC 0 +#endif + +// +// // Clock_MCK configuration +// Indicates whether MCK configuration is enabled or not +// enable_clk_gen_mck +#ifndef CONF_CLK_MCK_CONFIG +#define CONF_CLK_MCK_CONFIG 1 +#endif + +// Clock Generator +// clock generator MCK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for MCK +// clk_gen_mck_oscillator +#ifndef CONF_CLK_GEN_MCK_SRC +#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// Master Clock Controller Divider MCK divider +// <0=> 1 +// <1=> 2 +// <3=> 3 +// <2=> 4 +// Select the master clock divider. +// mck_div +#ifndef CONF_MCK_DIV +#define CONF_MCK_DIV 1 +#endif + +// +// // Clock_SYSTICK configuration +// Indicates whether SYSTICK configuration is enabled or not +// enable_clk_gen_systick +#ifndef CONF_CLK_SYSTICK_CONFIG +#define CONF_CLK_SYSTICK_CONFIG 1 +#endif + +// Clock Generator +// clock generator SYSTICK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for SYSTICK +// clk_gen_systick_oscillator +#ifndef CONF_CLK_GEN_SYSTICK_SRC +#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// Systick clock divider +// <8=> 8 +// Select systick clock divider +// systick_clock_div +#ifndef CONF_SYSTICK_DIV +#define CONF_SYSTICK_DIV 8 +#endif + +// +// // Clock_FCLK configuration +// Indicates whether FCLK configuration is enabled or not +// enable_clk_gen_fclk +#ifndef CONF_CLK_FCLK_CONFIG +#define CONF_CLK_FCLK_CONFIG 1 +#endif + +// Clock Generator +// clock generator FCLK source + +// Master Clock Controller (PMC_MCKR) + +// This defines the clock source for FCLK +// clk_gen_fclk_oscillator +#ifndef CONF_CLK_GEN_FCLK_SRC +#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR +#endif + +// + +// + +// +// // Clock_GCLK0 configuration +// Indicates whether GCLK0 configuration is enabled or not +// enable_clk_gen_gclk0 +#ifndef CONF_CLK_GCLK0_CONFIG +#define CONF_CLK_GCLK0_CONFIG 1 +#endif + +// Clock Generator +// clock generator GCLK0 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// USB 480M Clock (UPLLCK) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for GCLK0 +// clk_gen_gclk0_oscillator +#ifndef CONF_CLK_GEN_GCLK0_SRC +#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK +#endif + +// Enable Clock_GCLK0 +// Indicates whether GCLK0 is enabled or disable +// clk_gen_gclk0_arch_enable +#ifndef CONF_CLK_GCLK0_ENABLE +#define CONF_CLK_GCLK0_ENABLE 1 +#endif + +// + +// +// Enable GCLK0 GCLKEN +// Indicates whether GCLK0 GCLKEN is enabled or disable +// gclk0_gclken_enable +#ifndef CONF_GCLK0_GCLKEN_ENABLE +#define CONF_GCLK0_GCLKEN_ENABLE 0 +#endif + +// Generic Clock GCLK0 divider <1-256> +// Select the clock divider (divider = GCLKDIV + 1). +// gclk0_div +#ifndef CONF_GCLK0_DIV +#define CONF_GCLK0_DIV 2 +#endif + +// +// // Clock_GCLK1 configuration +// Indicates whether GCLK1 configuration is enabled or not +// enable_clk_gen_gclk1 +#ifndef CONF_CLK_GCLK1_CONFIG +#define CONF_CLK_GCLK1_CONFIG 1 +#endif + +// Clock Generator +// clock generator GCLK1 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// USB 480M Clock (UPLLCK) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for GCLK1 +// clk_gen_gclk1_oscillator +#ifndef CONF_CLK_GEN_GCLK1_SRC +#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK +#endif + +// Enable Clock_GCLK1 +// Indicates whether GCLK1 is enabled or disable +// clk_gen_gclk1_arch_enable +#ifndef CONF_CLK_GCLK1_ENABLE +#define CONF_CLK_GCLK1_ENABLE 1 +#endif + +// + +// +// Enable GCLK1 GCLKEN +// Indicates whether GCLK1 GCLKEN is enabled or disable +// gclk1_gclken_enable +#ifndef CONF_GCLK1_GCLKEN_ENABLE +#define CONF_GCLK1_GCLKEN_ENABLE 0 +#endif + +// Generic Clock GCLK1 divider <1-256> +// Select the clock divider (divider = GCLKDIV + 1). +// gclk1_div +#ifndef CONF_GCLK1_DIV +#define CONF_GCLK1_DIV 3 +#endif + +// +// // Clock_PCK0 configuration +// Indicates whether PCK0 configuration is enabled or not +// enable_clk_gen_pck0 +#ifndef CONF_CLK_PCK0_CONFIG +#define CONF_CLK_PCK0_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK0 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK0 +// clk_gen_pck0_oscillator +#ifndef CONF_CLK_GEN_PCK0_SRC +#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK0 +// Indicates whether PCK0 is enabled or disable +// clk_gen_pck0_arch_enable +#ifndef CONF_CLK_PCK0_ENABLE +#define CONF_CLK_PCK0_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck0_presc +#ifndef CONF_PCK0_PRESC +#define CONF_PCK0_PRESC 1 +#endif + +// +// // Clock_PCK1 configuration +// Indicates whether PCK1 configuration is enabled or not +// enable_clk_gen_pck1 +#ifndef CONF_CLK_PCK1_CONFIG +#define CONF_CLK_PCK1_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK1 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK1 +// clk_gen_pck1_oscillator +#ifndef CONF_CLK_GEN_PCK1_SRC +#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK1 +// Indicates whether PCK1 is enabled or disable +// clk_gen_pck1_arch_enable +#ifndef CONF_CLK_PCK1_ENABLE +#define CONF_CLK_PCK1_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck1_presc +#ifndef CONF_PCK1_PRESC +#define CONF_PCK1_PRESC 2 +#endif + +// +// // Clock_PCK2 configuration +// Indicates whether PCK2 configuration is enabled or not +// enable_clk_gen_pck2 +#ifndef CONF_CLK_PCK2_CONFIG +#define CONF_CLK_PCK2_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK2 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK2 +// clk_gen_pck2_oscillator +#ifndef CONF_CLK_GEN_PCK2_SRC +#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK2 +// Indicates whether PCK2 is enabled or disable +// clk_gen_pck2_arch_enable +#ifndef CONF_CLK_PCK2_ENABLE +#define CONF_CLK_PCK2_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck2_presc +#ifndef CONF_PCK2_PRESC +#define CONF_PCK2_PRESC 3 +#endif + +// +// // Clock_PCK3 configuration +// Indicates whether PCK3 configuration is enabled or not +// enable_clk_gen_pck3 +#ifndef CONF_CLK_PCK3_CONFIG +#define CONF_CLK_PCK3_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK3 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK3 +// clk_gen_pck3_oscillator +#ifndef CONF_CLK_GEN_PCK3_SRC +#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK3 +// Indicates whether PCK3 is enabled or disable +// clk_gen_pck3_arch_enable +#ifndef CONF_CLK_PCK3_ENABLE +#define CONF_CLK_PCK3_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck3_presc +#ifndef CONF_PCK3_PRESC +#define CONF_PCK3_PRESC 4 +#endif + +// +// // Clock_PCK4 configuration +// Indicates whether PCK4 configuration is enabled or not +// enable_clk_gen_pck4 +#ifndef CONF_CLK_PCK4_CONFIG +#define CONF_CLK_PCK4_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK4 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK4 +// clk_gen_pck4_oscillator +#ifndef CONF_CLK_GEN_PCK4_SRC +#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK4 +// Indicates whether PCK4 is enabled or disable +// clk_gen_pck4_arch_enable +#ifndef CONF_CLK_PCK4_ENABLE +#define CONF_CLK_PCK4_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck4_presc +#ifndef CONF_PCK4_PRESC +#define CONF_PCK4_PRESC 5 +#endif + +// +// // Clock_PCK5 configuration +// Indicates whether PCK5 configuration is enabled or not +// enable_clk_gen_pck5 +#ifndef CONF_CLK_PCK5_CONFIG +#define CONF_CLK_PCK5_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK5 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK5 +// clk_gen_pck5_oscillator +#ifndef CONF_CLK_GEN_PCK5_SRC +#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_UPLLCKDIV +#endif + +// Enable Clock_PCK5 +// Indicates whether PCK5 is enabled or disable +// clk_gen_pck5_arch_enable +#ifndef CONF_CLK_PCK5_ENABLE +#define CONF_CLK_PCK5_ENABLE 1 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck5_presc +#ifndef CONF_PCK5_PRESC +#define CONF_PCK5_PRESC 6 +#endif + +// +// // Clock_PCK6 configuration +// Indicates whether PCK6 configuration is enabled or not +// enable_clk_gen_pck6 +#ifndef CONF_CLK_PCK6_CONFIG +#define CONF_CLK_PCK6_CONFIG 1 +#endif + +// Clock Generator +// clock generator PCK6 source + +// Slow Clock (SLCK) + +// Main Clock (MAINCK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// PLLA Clock (PLLACK) + +// Master Clock (MCK) + +// This defines the clock source for PCK6 +// clk_gen_pck6_oscillator +#ifndef CONF_CLK_GEN_PCK6_SRC +#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK +#endif + +// Enable Clock_PCK6 +// Indicates whether PCK6 is enabled or disable +// clk_gen_pck6_arch_enable +#ifndef CONF_CLK_PCK6_ENABLE +#define CONF_CLK_PCK6_ENABLE 0 +#endif + +// + +// + +// Programmable Clock Controller Prescaler <1-256> +// Select the clock prescaler (prescaler = PRESC + 1). +// pck6_presc +#ifndef CONF_PCK6_PRESC +#define CONF_PCK6_PRESC 7 +#endif + +// +// // Clock_USB_480M configuration +// Indicates whether USB_480M configuration is enabled or not +// enable_clk_gen_usb_480m +#ifndef CONF_CLK_USB_480M_CONFIG +#define CONF_CLK_USB_480M_CONFIG 1 +#endif + +// Clock Generator +// clock generator USB_480M source + +// USB 480M Clock (UPLLCK) + +// This defines the clock source for USB_480M +// clk_gen_usb_480m_oscillator +#ifndef CONF_CLK_GEN_USB_480M_SRC +#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK +#endif + +// + +// + +// +// // Clock_USB_48M configuration +// Indicates whether USB_48M configuration is enabled or not +// enable_clk_gen_usb_48m +#ifndef CONF_CLK_USB_48M_CONFIG +#define CONF_CLK_USB_48M_CONFIG 1 +#endif + +// Clock Generator +// clock generator USB_48M source + +// PLLA Clock (PLLACK) + +// UDPLL with Divider (MCKR UPLLDIV2) + +// This defines the clock source for USB_48M +// clk_gen_usb_48m_oscillator +#ifndef CONF_CLK_GEN_USB_48M_SRC +#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_PLLACK +#endif + +// Enable Clock_USB_48M +// Indicates whether USB_48M is enabled or disable +// clk_gen_usb_48m_arch_enable +#ifndef CONF_CLK_USB_48M_ENABLE +#define CONF_CLK_USB_48M_ENABLE 0 +#endif + +// + +// + +// USB Clock Controller Divider <1-16> +// Select the USB clock divider (divider = USBDIV + 1). +// usb_48m_div +#ifndef CONF_USB_48M_DIV +#define CONF_USB_48M_DIV 1 +#endif + +// +// // Clock_SLCK2 configuration +// Indicates whether SLCK2 configuration is enabled or not +// enable_clk_gen_slck2 +#ifndef CONF_CLK_SLCK2_CONFIG +#define CONF_CLK_SLCK2_CONFIG 1 +#endif + +// Clock Generator +// clock generator SLCK2 source + +// Slow Clock (SLCK) + +// This defines the clock source for SLCK2 +// clk_gen_slck2_oscillator +#ifndef CONF_CLK_GEN_SLCK2_SRC +#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK +#endif + +// + +// + +// +// + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_hclk_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Processor Clock Settings +// Processor Clock source +// Master Clock Controller (PMC_MCKR) +// This defines the clock source for the HCLK (Processor clock) +// hclk_clock_source +#ifndef CONF_HCLK_SRC +#define CONF_HCLK_SRC MCKR +#endif + +// Flash Wait State +// <0=> 1 cycle +// <1=> 2 cycles +// <2=> 3 cycles +// <3=> 4 cycles +// <4=> 5 cycles +// <5=> 6 cycles +// <6=> 7 cycles +// This field defines the number of wait states for read and write operations. +// efc_fws +#ifndef CONF_EFC_WAIT_STATE +#define CONF_EFC_WAIT_STATE 5 +#endif + +// +// + +// SysTick Clock +// enable_systick_clk_clock +#ifndef CONF_SYSTICK_CLK_CONFIG +#define CONF_SYSTICK_CLK_CONFIG 1 +#endif + +// SysTick Clock source +// Master Clock Controller (PMC_MCKR) +// This defines the clock source for the SysTick Clock +// systick_clk_clock_source +#ifndef CONF_SYSTICK_CLK_SRC +#define CONF_SYSTICK_CLK_SRC MCKR +#endif + +// SysTick Clock Divider +// <8=> 8 +// Fixed to 8 if Systick is not using Processor clock +// systick_clk_clock_div +#ifndef CONF_SYSTICK_CLK_DIV +#define CONF_SYSTICK_CLK_DIV 8 +#endif + +// + +// OSC32K Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 1 +#endif + +// OSC32K Oscillator Control +// OSC32K Oscillator Enable +// Indicates whether OSC32K Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif +// +// + +// XOSC32K Oscillator Configuration +// Indicates whether configuration for XOSC32K is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// XOSC32K Oscillator Control +// Oscillator Bypass Select +// The 32kHz crystal oscillator is not bypassed. +// The 32kHz crystal oscillator is bypassed. +// Indicates whether XOSC32K is bypassed. +// xosc32k_bypass +#ifndef CONF_XOSC32K +#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS +#endif + +// XOSC32K Oscillator Enable +// Indicates whether XOSC32K Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif +// +// + +// OSC12M Oscillator Configuration +// Indicates whether configuration for OSC12M is enabled or not +// enable_osc12m +#ifndef CONF_OSC12M_CONFIG +#define CONF_OSC12M_CONFIG 0 +#endif + +// OSC12M Oscillator Control +// OSC12M Oscillator Enable +// Indicates whether OSC12M Oscillator is enabled or not. +// osc12m_arch_enable +#ifndef CONF_OSC12M_ENABLE +#define CONF_OSC12M_ENABLE 0 +#endif + +// OSC12M selector +// <0=> 4000000 +// <1=> 8000000 +// <2=> 12000000 +// Select the frequency of embedded fast RC oscillator. +// osc12m_selector +#ifndef CONF_OSC12M_SELECTOR +#define CONF_OSC12M_SELECTOR 2 +#endif +// +// + +// XOSC20M Oscillator Configuration +// Indicates whether configuration for XOSC20M is enabled or not. +// enable_xosc20m +#ifndef CONF_XOSC20M_CONFIG +#define CONF_XOSC20M_CONFIG 1 +#endif + +// XOSC20M Oscillator Control +// XOSC20M selector <3000000-20000000> +// Select the frequency of crystal or ceramic resonator oscillator. +// xosc20m_selector +#ifndef CONF_XOSC20M_SELECTOR +#define CONF_XOSC20M_SELECTOR 12000000 +#endif + +// Start up time for the external oscillator (ms): <0-256> +// Select start-up time. +// xosc20m_startup_time +#ifndef CONF_XOSC20M_STARTUP_TIME +#define CONF_XOSC20M_STARTUP_TIME 62 +#endif + +// Oscillator Bypass Select +// The external crystal oscillator is not bypassed. +// The external crystal oscillator is bypassed. +// Indicates whether XOSC20M is bypassed. +// xosc20m_bypass +#ifndef CONF_XOSC20M +#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS +#endif + +// XOSC20M Oscillator Enable +// Indicates whether XOSC20M Oscillator is enabled or not +// xosc20m_arch_enable +#ifndef CONF_XOSC20M_ENABLE +#define CONF_XOSC20M_ENABLE 1 +#endif +// +// + +// PLLACK Oscillator Configuration +// Indicates whether configuration for PLLACK is enabled or not +// enable_pllack +#ifndef CONF_PLLACK_CONFIG +#define CONF_PLLACK_CONFIG 1 +#endif + +// PLLACK Reference Clock Source +// Main Clock (MAINCK) +// Select the clock source. +// pllack_ref_clock +#ifndef CONF_PLLACK_CLK +#define CONF_PLLACK_CLK MAINCK +#endif + +// PLLACK Oscillator Control +// PLLACK Oscillator Enable +// Indicates whether PLLACK Oscillator is enabled or not +// pllack_arch_enable +#ifndef CONF_PLLACK_ENABLE +#define CONF_PLLACK_ENABLE 1 +#endif + +// PLLA Frontend Divider (DIVA) <1-255> +// Select the clock divider +// pllack_div +#ifndef CONF_PLLACK_DIV +#define CONF_PLLACK_DIV 1 +#endif + +// PLLACK Muliplier <1-62> +// Indicates PLLA multiplier (multiplier = MULA + 1). +// pllack_mul +#ifndef CONF_PLLACK_MUL +#define CONF_PLLACK_MUL 25 +#endif +// +// + +// UPLLCK Oscillator Configuration +// Indicates whether configuration for UPLLCK is enabled or not +// enable_upllck +#ifndef CONF_UPLLCK_CONFIG +#define CONF_UPLLCK_CONFIG 1 +#endif + +// UPLLCK Reference Clock Source +// External 3-20MHz Oscillator (XOSC20M) +// Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M. +// upllck_ref_clock +#ifndef CONF_UPLLCK_CLK +#define CONF_UPLLCK_CLK XOSC20M +#endif + +// UPLLCK Oscillator Control +// UPLLCK Oscillator Enable +// Indicates whether UPLLCK Oscillator is enabled or not +// upllck_arch_enable +#ifndef CONF_UPLLCK_ENABLE +#define CONF_UPLLCK_ENABLE 1 +#endif +// +// + +// UPLLCKDIV Oscillator Configuration +// Indicates whether configuration for UPLLCKDIV is enabled or not +// enable_upllckdiv +#ifndef CONF_UPLLCKDIV_CONFIG +#define CONF_UPLLCKDIV_CONFIG 1 +#endif + +// UPLLCKDIV Reference Clock Source +// USB 480M Clock (UPLLCK) +// Select the clock source. +// upllckdiv_ref_clock +#ifndef CONF_UPLLCKDIV_CLK +#define CONF_UPLLCKDIV_CLK UPLLCK +#endif + +// UPLLCKDIV Oscillator Control +// UPLLCKDIV Clock Divider +// <0=> 1 +// <1=> 2 +// Select the clock divider. +// upllckdiv_div +#ifndef CONF_UPLLCKDIV_DIV +#define CONF_UPLLCKDIV_DIV 1 +#endif +// +// + +// MCK/8 +// enable_mck_div_8 +#ifndef CONF_MCK_DIV_8_CONFIG +#define CONF_MCK_DIV_8_CONFIG 0 +#endif + +// MCK/8 Source +// <0=> Master Clock (MCK) +// mck_div_8_src +#ifndef CONF_MCK_DIV_8_SRC +#define CONF_MCK_DIV_8_SRC 0 +#endif +// + +// External Clock Input Configuration +// enable_dummy_ext +#ifndef CONF_DUMMY_EXT_CONFIG +#define CONF_DUMMY_EXT_CONFIG 1 +#endif + +// External Clock Input Source +// All here are dummy values +// Refer to the peripherals settings for actual input information +// <0=> Specific clock input from specific pin +// dummy_ext_src +#ifndef CONF_DUMMY_EXT_SRC +#define CONF_DUMMY_EXT_SRC 0 +#endif +// + +// External Clock Configuration +// enable_dummy_ext_clk +#ifndef CONF_DUMMY_EXT_CLK_CONFIG +#define CONF_DUMMY_EXT_CLK_CONFIG 1 +#endif + +// External Clock Source +// All here are dummy values +// Refer to the peripherals settings for actual input information +// <0=> External Clock Input +// dummy_ext_clk_src +#ifndef CONF_DUMMY_EXT_CLK_SRC +#define CONF_DUMMY_EXT_CLK_SRC 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_PMC_CONFIG_H diff --git a/bsp/microchip/same70/bsp/config/hpl_systick_ARMv7_config.h b/bsp/microchip/same70/bsp/config/hpl_systick_ARMv7_config.h new file mode 100644 index 0000000000..48108a7fe9 --- /dev/null +++ b/bsp/microchip/same70/bsp/config/hpl_systick_ARMv7_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_ARMv7_config.h */ +#ifndef HPL_SYSTICK_ARMV7_CONFIG_H +#define HPL_SYSTICK_ARMV7_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_ARMV7_CONFIG_H diff --git a/bsp/microchip/same70/bsp/config/hpl_usart_config.h b/bsp/microchip/same70/bsp/config/hpl_usart_config.h new file mode 100644 index 0000000000..8eafe26d45 --- /dev/null +++ b/bsp/microchip/same70/bsp/config/hpl_usart_config.h @@ -0,0 +1,215 @@ +/* Auto-generated config file hpl_usart_config.h */ +#ifndef HPL_USART_CONFIG_H +#define HPL_USART_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_USART_1_ENABLE +#define CONF_USART_1_ENABLE 1 +#endif + +// Basic Configuration + +// Frame parity +// <0x0=>Even parity +// <0x1=>Odd parity +// <0x2=>Parity forced to 0 +// <0x3=>Parity forced to 1 +// <0x4=>No parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_USART_1_PARITY +#define CONF_USART_1_PARITY 0x4 +#endif + +// Character Size +// <0x0=>5 bits +// <0x1=>6 bits +// <0x2=>7 bits +// <0x3=>8 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_USART_1_CHSIZE +#define CONF_USART_1_CHSIZE 0x3 +#endif + +// Stop Bit +// <0=>1 stop bit +// <1=>1.5 stop bits +// <2=>2 stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_USART_1_SBMODE +#define CONF_USART_1_SBMODE 0 +#endif + +// Clock Output Select +// <0=>The USART does not drive the SCK pin +// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK +// Clock Output Select in USART sck, if in usrt master mode, please drive SCK. +// usart_clock_output_select +#ifndef CONF_USART_1_CLKO +#define CONF_USART_1_CLKO 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_USART_1_BAUD +#define CONF_USART_1_BAUD 115200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_USART_1_ADVANCED_CONFIG +#define CONF_USART_1_ADVANCED_CONFIG 1 +#endif + +// Channel Mode +// <0=>Normal Mode +// <1=>Automatic Echo +// <2=>Local Loopback +// <3=>Remote Loopback +// Channel mode in USART frame +// usart_channel_mode +#ifndef CONF_USART_1_CHMODE +#define CONF_USART_1_CHMODE 0 +#endif + +// 9 bits character enable +// Enable 9 bits character, this has high priority than 5/6/7/8 bits. +// usart_9bits_enable +#ifndef CONF_USART_1_MODE9 +#define CONF_USART_1_MODE9 0 +#endif + +// Variable Sync +// <0=>User defined configuration +// <1=>sync field is updated when a character is written into US_THR +// Variable Synchronization of Command/Data Sync Start Frarm Delimiter +// variable_sync +#ifndef CONF_USART_1_VAR_SYNC +#define CONF_USART_1_VAR_SYNC 0 +#endif + +// Oversampling Mode +// <0=>16 Oversampling +// <1=>8 Oversampling +// Oversampling Mode in UART mode +// usart__oversampling_mode +#ifndef CONF_USART_1_OVER +#define CONF_USART_1_OVER 0 +#endif + +// Inhibit Non Ack +// <0=>The NACK is generated +// <1=>The NACK is not generated +// Inhibit Non Acknowledge +// usart__inack +#ifndef CONF_USART_1_INACK +#define CONF_USART_1_INACK 1 +#endif + +// Disable Successive NACK +// <0=>NACK is sent on the ISO line as soon as a parity error occurs +// <1=>Many parity errors generate a NACK on the ISO line +// Disable Successive NACK +// usart_dsnack +#ifndef CONF_USART_1_DSNACK +#define CONF_USART_1_DSNACK 0 +#endif + +// Inverted Data +// <0=>Data isn't inverted, nomal mode +// <1=>Data is inverted +// Inverted Data +// usart_invdata +#ifndef CONF_USART_1_INVDATA +#define CONF_USART_1_INVDATA 0 +#endif + +// Maximum Number of Automatic Iteration <0-7> +// Defines the maximum number of iterations in mode ISO7816, protocol T = 0. +// usart_max_iteration +#ifndef CONF_USART_1_MAX_ITERATION +#define CONF_USART_1_MAX_ITERATION 0 +#endif + +// Receive Line Filter enable +// whether the USART filters the receive line using a three-sample filter +// usart_receive_filter_enable +#ifndef CONF_USART_1_FILTER +#define CONF_USART_1_FILTER 0 +#endif + +// Manchester Encoder/Decoder Enable +// whether the USART Manchester Encoder/Decoder +// usart_manchester_filter_enable +#ifndef CONF_USART_1_MAN +#define CONF_USART_1_MAN 0 +#endif + +// Manchester Synchronization Mode +// <0=>The Manchester start bit is a 0 to 1 transition +// <1=>The Manchester start bit is a 1 to 0 transition +// Manchester Synchronization Mode +// usart_manchester_synchronization_mode +#ifndef CONF_USART_1_MODSYNC +#define CONF_USART_1_MODSYNC 0 +#endif + +// Start Frame Delimiter Selector +// <0=>Start frame delimiter is COMMAND or DATA SYNC +// <1=>Start frame delimiter is one bit +// Start Frame Delimiter Selector +// usart_start_frame_delimiter +#ifndef CONF_USART_1_ONEBIT +#define CONF_USART_1_ONEBIT 0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_USART_1_FRACTIONAL +#define CONF_USART_1_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>LSB is transmitted first +// <1=>MSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_msbf +#ifndef CONF_USART_1_MSBF +#define CONF_USART_1_MSBF 0 +#endif + +// + +#define CONF_USART_1_MODE 0x0 + +// Calculate BAUD register value in UART mode +#if CONF_USART1_CK_SRC < 3 +#ifndef CONF_USART_1_BAUD_CD +#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER)) +#endif +#ifndef CONF_USART_1_BAUD_FP +#define CONF_USART_1_BAUD_FP \ + ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD) +#endif +#elif CONF_USART1_CK_SRC == 3 +// No division is active. The value written in US_BRGR has no effect. +#ifndef CONF_USART_1_BAUD_CD +#define CONF_USART_1_BAUD_CD 1 +#endif +#ifndef CONF_USART_1_BAUD_FP +#define CONF_USART_1_BAUD_FP 1 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_USART_CONFIG_H diff --git a/bsp/microchip/same70/bsp/config/hpl_xdmac_config.h b/bsp/microchip/same70/bsp/config/hpl_xdmac_config.h new file mode 100644 index 0000000000..a3d62c6fc4 --- /dev/null +++ b/bsp/microchip/same70/bsp/config/hpl_xdmac_config.h @@ -0,0 +1,4400 @@ +/* Auto-generated config file hpl_xdmac_config.h */ +#ifndef HPL_XDMAC_CONFIG_H +#define HPL_XDMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// XDMAC enable +// Indicates whether xdmac is enabled or not +// xdmac_enable +#ifndef CONF_DMA_ENABLE +#define CONF_DMA_ENABLE 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_0 +#ifndef CONF_DMAC_BURSTSIZE_0 +#define CONF_DMAC_BURSTSIZE_0 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_0 +#ifndef CONF_DMAC_CHUNKSIZE_0 +#define CONF_DMAC_CHUNKSIZE_0 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_0 +#ifndef CONF_DMAC_SRC_INTERFACE_0 +#define CONF_DMAC_SRC_INTERFACE_0 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_0 +#ifndef CONF_DMAC_DES_INTERFACE_0 +#define CONF_DMAC_DES_INTERFACE_0 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_0 +#ifndef CONF_DMAC_TRANS_TYPE_0 +#define CONF_DMAC_TRANS_TYPE_0 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_0 == 0 +#define CONF_DMAC_TYPE_0 0 +#define CONF_DMAC_DSYNC_0 0 +#elif CONF_DMAC_TRANS_TYPE_0 == 1 +#define CONF_DMAC_TYPE_0 1 +#define CONF_DMAC_DSYNC_0 0 +#elif CONF_DMAC_TRANS_TYPE_0 == 2 +#define CONF_DMAC_TYPE_0 1 +#define CONF_DMAC_DSYNC_0 1 +#endif + +#if CONF_DMAC_TRIGSRC_0 == 0xFF +#define CONF_DMAC_SWREQ_0 1 +#else +#define CONF_DMAC_SWREQ_0 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0))) +#if (!CONF_DMAC_SRCINC_0) +#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_0) +#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_0 +#define CONF_DMAC_SRC_STRIDE_0 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_0 +#define CONF_DMAC_DES_STRIDE_0 0 +#endif + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_1 +#ifndef CONF_DMAC_BURSTSIZE_1 +#define CONF_DMAC_BURSTSIZE_1 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_1 +#ifndef CONF_DMAC_CHUNKSIZE_1 +#define CONF_DMAC_CHUNKSIZE_1 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_1 +#ifndef CONF_DMAC_SRC_INTERFACE_1 +#define CONF_DMAC_SRC_INTERFACE_1 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_1 +#ifndef CONF_DMAC_DES_INTERFACE_1 +#define CONF_DMAC_DES_INTERFACE_1 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_1 +#ifndef CONF_DMAC_TRANS_TYPE_1 +#define CONF_DMAC_TRANS_TYPE_1 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_1 == 0 +#define CONF_DMAC_TYPE_1 0 +#define CONF_DMAC_DSYNC_1 0 +#elif CONF_DMAC_TRANS_TYPE_1 == 1 +#define CONF_DMAC_TYPE_1 1 +#define CONF_DMAC_DSYNC_1 0 +#elif CONF_DMAC_TRANS_TYPE_1 == 2 +#define CONF_DMAC_TYPE_1 1 +#define CONF_DMAC_DSYNC_1 1 +#endif + +#if CONF_DMAC_TRIGSRC_1 == 0xFF +#define CONF_DMAC_SWREQ_1 1 +#else +#define CONF_DMAC_SWREQ_1 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1))) +#if (!CONF_DMAC_SRCINC_1) +#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_1) +#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_1 +#define CONF_DMAC_SRC_STRIDE_1 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_1 +#define CONF_DMAC_DES_STRIDE_1 0 +#endif + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_2 +#ifndef CONF_DMAC_BURSTSIZE_2 +#define CONF_DMAC_BURSTSIZE_2 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_2 +#ifndef CONF_DMAC_CHUNKSIZE_2 +#define CONF_DMAC_CHUNKSIZE_2 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_2 +#ifndef CONF_DMAC_SRC_INTERFACE_2 +#define CONF_DMAC_SRC_INTERFACE_2 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_2 +#ifndef CONF_DMAC_DES_INTERFACE_2 +#define CONF_DMAC_DES_INTERFACE_2 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_2 +#ifndef CONF_DMAC_TRANS_TYPE_2 +#define CONF_DMAC_TRANS_TYPE_2 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_2 == 0 +#define CONF_DMAC_TYPE_2 0 +#define CONF_DMAC_DSYNC_2 0 +#elif CONF_DMAC_TRANS_TYPE_2 == 1 +#define CONF_DMAC_TYPE_2 1 +#define CONF_DMAC_DSYNC_2 0 +#elif CONF_DMAC_TRANS_TYPE_2 == 2 +#define CONF_DMAC_TYPE_2 1 +#define CONF_DMAC_DSYNC_2 1 +#endif + +#if CONF_DMAC_TRIGSRC_2 == 0xFF +#define CONF_DMAC_SWREQ_2 1 +#else +#define CONF_DMAC_SWREQ_2 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2))) +#if (!CONF_DMAC_SRCINC_2) +#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_2) +#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_2 +#define CONF_DMAC_SRC_STRIDE_2 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_2 +#define CONF_DMAC_DES_STRIDE_2 0 +#endif + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_3 +#ifndef CONF_DMAC_BURSTSIZE_3 +#define CONF_DMAC_BURSTSIZE_3 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_3 +#ifndef CONF_DMAC_CHUNKSIZE_3 +#define CONF_DMAC_CHUNKSIZE_3 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_3 +#ifndef CONF_DMAC_SRC_INTERFACE_3 +#define CONF_DMAC_SRC_INTERFACE_3 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_3 +#ifndef CONF_DMAC_DES_INTERFACE_3 +#define CONF_DMAC_DES_INTERFACE_3 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_3 +#ifndef CONF_DMAC_TRANS_TYPE_3 +#define CONF_DMAC_TRANS_TYPE_3 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_3 == 0 +#define CONF_DMAC_TYPE_3 0 +#define CONF_DMAC_DSYNC_3 0 +#elif CONF_DMAC_TRANS_TYPE_3 == 1 +#define CONF_DMAC_TYPE_3 1 +#define CONF_DMAC_DSYNC_3 0 +#elif CONF_DMAC_TRANS_TYPE_3 == 2 +#define CONF_DMAC_TYPE_3 1 +#define CONF_DMAC_DSYNC_3 1 +#endif + +#if CONF_DMAC_TRIGSRC_3 == 0xFF +#define CONF_DMAC_SWREQ_3 1 +#else +#define CONF_DMAC_SWREQ_3 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3))) +#if (!CONF_DMAC_SRCINC_3) +#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_3) +#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_3 +#define CONF_DMAC_SRC_STRIDE_3 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_3 +#define CONF_DMAC_DES_STRIDE_3 0 +#endif + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_4 +#ifndef CONF_DMAC_BURSTSIZE_4 +#define CONF_DMAC_BURSTSIZE_4 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_4 +#ifndef CONF_DMAC_CHUNKSIZE_4 +#define CONF_DMAC_CHUNKSIZE_4 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_4 +#ifndef CONF_DMAC_SRC_INTERFACE_4 +#define CONF_DMAC_SRC_INTERFACE_4 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_4 +#ifndef CONF_DMAC_DES_INTERFACE_4 +#define CONF_DMAC_DES_INTERFACE_4 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_4 +#ifndef CONF_DMAC_TRANS_TYPE_4 +#define CONF_DMAC_TRANS_TYPE_4 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_4 == 0 +#define CONF_DMAC_TYPE_4 0 +#define CONF_DMAC_DSYNC_4 0 +#elif CONF_DMAC_TRANS_TYPE_4 == 1 +#define CONF_DMAC_TYPE_4 1 +#define CONF_DMAC_DSYNC_4 0 +#elif CONF_DMAC_TRANS_TYPE_4 == 2 +#define CONF_DMAC_TYPE_4 1 +#define CONF_DMAC_DSYNC_4 1 +#endif + +#if CONF_DMAC_TRIGSRC_4 == 0xFF +#define CONF_DMAC_SWREQ_4 1 +#else +#define CONF_DMAC_SWREQ_4 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4))) +#if (!CONF_DMAC_SRCINC_4) +#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_4) +#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_4 +#define CONF_DMAC_SRC_STRIDE_4 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_4 +#define CONF_DMAC_DES_STRIDE_4 0 +#endif + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_5 +#ifndef CONF_DMAC_BURSTSIZE_5 +#define CONF_DMAC_BURSTSIZE_5 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_5 +#ifndef CONF_DMAC_CHUNKSIZE_5 +#define CONF_DMAC_CHUNKSIZE_5 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_5 +#ifndef CONF_DMAC_SRC_INTERFACE_5 +#define CONF_DMAC_SRC_INTERFACE_5 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_5 +#ifndef CONF_DMAC_DES_INTERFACE_5 +#define CONF_DMAC_DES_INTERFACE_5 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_5 +#ifndef CONF_DMAC_TRANS_TYPE_5 +#define CONF_DMAC_TRANS_TYPE_5 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_5 == 0 +#define CONF_DMAC_TYPE_5 0 +#define CONF_DMAC_DSYNC_5 0 +#elif CONF_DMAC_TRANS_TYPE_5 == 1 +#define CONF_DMAC_TYPE_5 1 +#define CONF_DMAC_DSYNC_5 0 +#elif CONF_DMAC_TRANS_TYPE_5 == 2 +#define CONF_DMAC_TYPE_5 1 +#define CONF_DMAC_DSYNC_5 1 +#endif + +#if CONF_DMAC_TRIGSRC_5 == 0xFF +#define CONF_DMAC_SWREQ_5 1 +#else +#define CONF_DMAC_SWREQ_5 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5))) +#if (!CONF_DMAC_SRCINC_5) +#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_5) +#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_5 +#define CONF_DMAC_SRC_STRIDE_5 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_5 +#define CONF_DMAC_DES_STRIDE_5 0 +#endif + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_6 +#ifndef CONF_DMAC_BURSTSIZE_6 +#define CONF_DMAC_BURSTSIZE_6 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_6 +#ifndef CONF_DMAC_CHUNKSIZE_6 +#define CONF_DMAC_CHUNKSIZE_6 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_6 +#ifndef CONF_DMAC_SRC_INTERFACE_6 +#define CONF_DMAC_SRC_INTERFACE_6 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_6 +#ifndef CONF_DMAC_DES_INTERFACE_6 +#define CONF_DMAC_DES_INTERFACE_6 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_6 +#ifndef CONF_DMAC_TRANS_TYPE_6 +#define CONF_DMAC_TRANS_TYPE_6 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_6 == 0 +#define CONF_DMAC_TYPE_6 0 +#define CONF_DMAC_DSYNC_6 0 +#elif CONF_DMAC_TRANS_TYPE_6 == 1 +#define CONF_DMAC_TYPE_6 1 +#define CONF_DMAC_DSYNC_6 0 +#elif CONF_DMAC_TRANS_TYPE_6 == 2 +#define CONF_DMAC_TYPE_6 1 +#define CONF_DMAC_DSYNC_6 1 +#endif + +#if CONF_DMAC_TRIGSRC_6 == 0xFF +#define CONF_DMAC_SWREQ_6 1 +#else +#define CONF_DMAC_SWREQ_6 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6))) +#if (!CONF_DMAC_SRCINC_6) +#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_6) +#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_6 +#define CONF_DMAC_SRC_STRIDE_6 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_6 +#define CONF_DMAC_DES_STRIDE_6 0 +#endif + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_7 +#ifndef CONF_DMAC_BURSTSIZE_7 +#define CONF_DMAC_BURSTSIZE_7 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_7 +#ifndef CONF_DMAC_CHUNKSIZE_7 +#define CONF_DMAC_CHUNKSIZE_7 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_7 +#ifndef CONF_DMAC_SRC_INTERFACE_7 +#define CONF_DMAC_SRC_INTERFACE_7 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_7 +#ifndef CONF_DMAC_DES_INTERFACE_7 +#define CONF_DMAC_DES_INTERFACE_7 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_7 +#ifndef CONF_DMAC_TRANS_TYPE_7 +#define CONF_DMAC_TRANS_TYPE_7 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_7 == 0 +#define CONF_DMAC_TYPE_7 0 +#define CONF_DMAC_DSYNC_7 0 +#elif CONF_DMAC_TRANS_TYPE_7 == 1 +#define CONF_DMAC_TYPE_7 1 +#define CONF_DMAC_DSYNC_7 0 +#elif CONF_DMAC_TRANS_TYPE_7 == 2 +#define CONF_DMAC_TYPE_7 1 +#define CONF_DMAC_DSYNC_7 1 +#endif + +#if CONF_DMAC_TRIGSRC_7 == 0xFF +#define CONF_DMAC_SWREQ_7 1 +#else +#define CONF_DMAC_SWREQ_7 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7))) +#if (!CONF_DMAC_SRCINC_7) +#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_7) +#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_7 +#define CONF_DMAC_SRC_STRIDE_7 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_7 +#define CONF_DMAC_DES_STRIDE_7 0 +#endif + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_8 +#ifndef CONF_DMAC_BURSTSIZE_8 +#define CONF_DMAC_BURSTSIZE_8 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_8 +#ifndef CONF_DMAC_CHUNKSIZE_8 +#define CONF_DMAC_CHUNKSIZE_8 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_8 +#ifndef CONF_DMAC_SRC_INTERFACE_8 +#define CONF_DMAC_SRC_INTERFACE_8 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_8 +#ifndef CONF_DMAC_DES_INTERFACE_8 +#define CONF_DMAC_DES_INTERFACE_8 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_8 +#ifndef CONF_DMAC_TRANS_TYPE_8 +#define CONF_DMAC_TRANS_TYPE_8 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_8 == 0 +#define CONF_DMAC_TYPE_8 0 +#define CONF_DMAC_DSYNC_8 0 +#elif CONF_DMAC_TRANS_TYPE_8 == 1 +#define CONF_DMAC_TYPE_8 1 +#define CONF_DMAC_DSYNC_8 0 +#elif CONF_DMAC_TRANS_TYPE_8 == 2 +#define CONF_DMAC_TYPE_8 1 +#define CONF_DMAC_DSYNC_8 1 +#endif + +#if CONF_DMAC_TRIGSRC_8 == 0xFF +#define CONF_DMAC_SWREQ_8 1 +#else +#define CONF_DMAC_SWREQ_8 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8))) +#if (!CONF_DMAC_SRCINC_8) +#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_8) +#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_8 +#define CONF_DMAC_SRC_STRIDE_8 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_8 +#define CONF_DMAC_DES_STRIDE_8 0 +#endif + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_9 +#ifndef CONF_DMAC_BURSTSIZE_9 +#define CONF_DMAC_BURSTSIZE_9 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_9 +#ifndef CONF_DMAC_CHUNKSIZE_9 +#define CONF_DMAC_CHUNKSIZE_9 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_9 +#ifndef CONF_DMAC_SRC_INTERFACE_9 +#define CONF_DMAC_SRC_INTERFACE_9 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_9 +#ifndef CONF_DMAC_DES_INTERFACE_9 +#define CONF_DMAC_DES_INTERFACE_9 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_9 +#ifndef CONF_DMAC_TRANS_TYPE_9 +#define CONF_DMAC_TRANS_TYPE_9 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_9 == 0 +#define CONF_DMAC_TYPE_9 0 +#define CONF_DMAC_DSYNC_9 0 +#elif CONF_DMAC_TRANS_TYPE_9 == 1 +#define CONF_DMAC_TYPE_9 1 +#define CONF_DMAC_DSYNC_9 0 +#elif CONF_DMAC_TRANS_TYPE_9 == 2 +#define CONF_DMAC_TYPE_9 1 +#define CONF_DMAC_DSYNC_9 1 +#endif + +#if CONF_DMAC_TRIGSRC_9 == 0xFF +#define CONF_DMAC_SWREQ_9 1 +#else +#define CONF_DMAC_SWREQ_9 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9))) +#if (!CONF_DMAC_SRCINC_9) +#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_9) +#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_9 +#define CONF_DMAC_SRC_STRIDE_9 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_9 +#define CONF_DMAC_DES_STRIDE_9 0 +#endif + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_10 +#ifndef CONF_DMAC_BURSTSIZE_10 +#define CONF_DMAC_BURSTSIZE_10 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_10 +#ifndef CONF_DMAC_CHUNKSIZE_10 +#define CONF_DMAC_CHUNKSIZE_10 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_10 +#ifndef CONF_DMAC_SRC_INTERFACE_10 +#define CONF_DMAC_SRC_INTERFACE_10 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_10 +#ifndef CONF_DMAC_DES_INTERFACE_10 +#define CONF_DMAC_DES_INTERFACE_10 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_10 +#ifndef CONF_DMAC_TRANS_TYPE_10 +#define CONF_DMAC_TRANS_TYPE_10 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_10 == 0 +#define CONF_DMAC_TYPE_10 0 +#define CONF_DMAC_DSYNC_10 0 +#elif CONF_DMAC_TRANS_TYPE_10 == 1 +#define CONF_DMAC_TYPE_10 1 +#define CONF_DMAC_DSYNC_10 0 +#elif CONF_DMAC_TRANS_TYPE_10 == 2 +#define CONF_DMAC_TYPE_10 1 +#define CONF_DMAC_DSYNC_10 1 +#endif + +#if CONF_DMAC_TRIGSRC_10 == 0xFF +#define CONF_DMAC_SWREQ_10 1 +#else +#define CONF_DMAC_SWREQ_10 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2 \ + && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10))) +#if (!CONF_DMAC_SRCINC_10) +#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_10) +#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_10 +#define CONF_DMAC_SRC_STRIDE_10 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_10 +#define CONF_DMAC_DES_STRIDE_10 0 +#endif + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_11 +#ifndef CONF_DMAC_BURSTSIZE_11 +#define CONF_DMAC_BURSTSIZE_11 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_11 +#ifndef CONF_DMAC_CHUNKSIZE_11 +#define CONF_DMAC_CHUNKSIZE_11 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_11 +#ifndef CONF_DMAC_SRC_INTERFACE_11 +#define CONF_DMAC_SRC_INTERFACE_11 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_11 +#ifndef CONF_DMAC_DES_INTERFACE_11 +#define CONF_DMAC_DES_INTERFACE_11 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_11 +#ifndef CONF_DMAC_TRANS_TYPE_11 +#define CONF_DMAC_TRANS_TYPE_11 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_11 == 0 +#define CONF_DMAC_TYPE_11 0 +#define CONF_DMAC_DSYNC_11 0 +#elif CONF_DMAC_TRANS_TYPE_11 == 1 +#define CONF_DMAC_TYPE_11 1 +#define CONF_DMAC_DSYNC_11 0 +#elif CONF_DMAC_TRANS_TYPE_11 == 2 +#define CONF_DMAC_TYPE_11 1 +#define CONF_DMAC_DSYNC_11 1 +#endif + +#if CONF_DMAC_TRIGSRC_11 == 0xFF +#define CONF_DMAC_SWREQ_11 1 +#else +#define CONF_DMAC_SWREQ_11 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2 \ + && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11))) +#if (!CONF_DMAC_SRCINC_11) +#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_11) +#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_11 +#define CONF_DMAC_SRC_STRIDE_11 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_11 +#define CONF_DMAC_DES_STRIDE_11 0 +#endif + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_12 +#ifndef CONF_DMAC_BURSTSIZE_12 +#define CONF_DMAC_BURSTSIZE_12 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_12 +#ifndef CONF_DMAC_CHUNKSIZE_12 +#define CONF_DMAC_CHUNKSIZE_12 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_12 +#ifndef CONF_DMAC_SRC_INTERFACE_12 +#define CONF_DMAC_SRC_INTERFACE_12 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_12 +#ifndef CONF_DMAC_DES_INTERFACE_12 +#define CONF_DMAC_DES_INTERFACE_12 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_12 +#ifndef CONF_DMAC_TRANS_TYPE_12 +#define CONF_DMAC_TRANS_TYPE_12 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_12 == 0 +#define CONF_DMAC_TYPE_12 0 +#define CONF_DMAC_DSYNC_12 0 +#elif CONF_DMAC_TRANS_TYPE_12 == 1 +#define CONF_DMAC_TYPE_12 1 +#define CONF_DMAC_DSYNC_12 0 +#elif CONF_DMAC_TRANS_TYPE_12 == 2 +#define CONF_DMAC_TYPE_12 1 +#define CONF_DMAC_DSYNC_12 1 +#endif + +#if CONF_DMAC_TRIGSRC_12 == 0xFF +#define CONF_DMAC_SWREQ_12 1 +#else +#define CONF_DMAC_SWREQ_12 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2 \ + && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12))) +#if (!CONF_DMAC_SRCINC_12) +#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_12) +#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_12 +#define CONF_DMAC_SRC_STRIDE_12 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_12 +#define CONF_DMAC_DES_STRIDE_12 0 +#endif + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_13 +#ifndef CONF_DMAC_BURSTSIZE_13 +#define CONF_DMAC_BURSTSIZE_13 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_13 +#ifndef CONF_DMAC_CHUNKSIZE_13 +#define CONF_DMAC_CHUNKSIZE_13 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_13 +#ifndef CONF_DMAC_SRC_INTERFACE_13 +#define CONF_DMAC_SRC_INTERFACE_13 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_13 +#ifndef CONF_DMAC_DES_INTERFACE_13 +#define CONF_DMAC_DES_INTERFACE_13 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_13 +#ifndef CONF_DMAC_TRANS_TYPE_13 +#define CONF_DMAC_TRANS_TYPE_13 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_13 == 0 +#define CONF_DMAC_TYPE_13 0 +#define CONF_DMAC_DSYNC_13 0 +#elif CONF_DMAC_TRANS_TYPE_13 == 1 +#define CONF_DMAC_TYPE_13 1 +#define CONF_DMAC_DSYNC_13 0 +#elif CONF_DMAC_TRANS_TYPE_13 == 2 +#define CONF_DMAC_TYPE_13 1 +#define CONF_DMAC_DSYNC_13 1 +#endif + +#if CONF_DMAC_TRIGSRC_13 == 0xFF +#define CONF_DMAC_SWREQ_13 1 +#else +#define CONF_DMAC_SWREQ_13 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2 \ + && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13))) +#if (!CONF_DMAC_SRCINC_13) +#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_13) +#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_13 +#define CONF_DMAC_SRC_STRIDE_13 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_13 +#define CONF_DMAC_DES_STRIDE_13 0 +#endif + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_14 +#ifndef CONF_DMAC_BURSTSIZE_14 +#define CONF_DMAC_BURSTSIZE_14 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_14 +#ifndef CONF_DMAC_CHUNKSIZE_14 +#define CONF_DMAC_CHUNKSIZE_14 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_14 +#ifndef CONF_DMAC_SRC_INTERFACE_14 +#define CONF_DMAC_SRC_INTERFACE_14 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_14 +#ifndef CONF_DMAC_DES_INTERFACE_14 +#define CONF_DMAC_DES_INTERFACE_14 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_14 +#ifndef CONF_DMAC_TRANS_TYPE_14 +#define CONF_DMAC_TRANS_TYPE_14 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_14 == 0 +#define CONF_DMAC_TYPE_14 0 +#define CONF_DMAC_DSYNC_14 0 +#elif CONF_DMAC_TRANS_TYPE_14 == 1 +#define CONF_DMAC_TYPE_14 1 +#define CONF_DMAC_DSYNC_14 0 +#elif CONF_DMAC_TRANS_TYPE_14 == 2 +#define CONF_DMAC_TYPE_14 1 +#define CONF_DMAC_DSYNC_14 1 +#endif + +#if CONF_DMAC_TRIGSRC_14 == 0xFF +#define CONF_DMAC_SWREQ_14 1 +#else +#define CONF_DMAC_SWREQ_14 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2 \ + && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14))) +#if (!CONF_DMAC_SRCINC_14) +#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_14) +#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_14 +#define CONF_DMAC_SRC_STRIDE_14 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_14 +#define CONF_DMAC_DES_STRIDE_14 0 +#endif + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_15 +#ifndef CONF_DMAC_BURSTSIZE_15 +#define CONF_DMAC_BURSTSIZE_15 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_15 +#ifndef CONF_DMAC_CHUNKSIZE_15 +#define CONF_DMAC_CHUNKSIZE_15 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_15 +#ifndef CONF_DMAC_SRC_INTERFACE_15 +#define CONF_DMAC_SRC_INTERFACE_15 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_15 +#ifndef CONF_DMAC_DES_INTERFACE_15 +#define CONF_DMAC_DES_INTERFACE_15 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_15 +#ifndef CONF_DMAC_TRANS_TYPE_15 +#define CONF_DMAC_TRANS_TYPE_15 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_15 == 0 +#define CONF_DMAC_TYPE_15 0 +#define CONF_DMAC_DSYNC_15 0 +#elif CONF_DMAC_TRANS_TYPE_15 == 1 +#define CONF_DMAC_TYPE_15 1 +#define CONF_DMAC_DSYNC_15 0 +#elif CONF_DMAC_TRANS_TYPE_15 == 2 +#define CONF_DMAC_TYPE_15 1 +#define CONF_DMAC_DSYNC_15 1 +#endif + +#if CONF_DMAC_TRIGSRC_15 == 0xFF +#define CONF_DMAC_SWREQ_15 1 +#else +#define CONF_DMAC_SWREQ_15 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2 \ + && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15))) +#if (!CONF_DMAC_SRCINC_15) +#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_15) +#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_15 +#define CONF_DMAC_SRC_STRIDE_15 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_15 +#define CONF_DMAC_DES_STRIDE_15 0 +#endif + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_16 +#ifndef CONF_DMAC_BURSTSIZE_16 +#define CONF_DMAC_BURSTSIZE_16 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_16 +#ifndef CONF_DMAC_CHUNKSIZE_16 +#define CONF_DMAC_CHUNKSIZE_16 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_16 +#ifndef CONF_DMAC_SRC_INTERFACE_16 +#define CONF_DMAC_SRC_INTERFACE_16 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_16 +#ifndef CONF_DMAC_DES_INTERFACE_16 +#define CONF_DMAC_DES_INTERFACE_16 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_16 +#ifndef CONF_DMAC_TRANS_TYPE_16 +#define CONF_DMAC_TRANS_TYPE_16 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_16 == 0 +#define CONF_DMAC_TYPE_16 0 +#define CONF_DMAC_DSYNC_16 0 +#elif CONF_DMAC_TRANS_TYPE_16 == 1 +#define CONF_DMAC_TYPE_16 1 +#define CONF_DMAC_DSYNC_16 0 +#elif CONF_DMAC_TRANS_TYPE_16 == 2 +#define CONF_DMAC_TYPE_16 1 +#define CONF_DMAC_DSYNC_16 1 +#endif + +#if CONF_DMAC_TRIGSRC_16 == 0xFF +#define CONF_DMAC_SWREQ_16 1 +#else +#define CONF_DMAC_SWREQ_16 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2 \ + && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16))) +#if (!CONF_DMAC_SRCINC_16) +#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_16) +#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_16 +#define CONF_DMAC_SRC_STRIDE_16 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_16 +#define CONF_DMAC_DES_STRIDE_16 0 +#endif + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_17 +#ifndef CONF_DMAC_BURSTSIZE_17 +#define CONF_DMAC_BURSTSIZE_17 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_17 +#ifndef CONF_DMAC_CHUNKSIZE_17 +#define CONF_DMAC_CHUNKSIZE_17 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_17 +#ifndef CONF_DMAC_SRC_INTERFACE_17 +#define CONF_DMAC_SRC_INTERFACE_17 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_17 +#ifndef CONF_DMAC_DES_INTERFACE_17 +#define CONF_DMAC_DES_INTERFACE_17 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_17 +#ifndef CONF_DMAC_TRANS_TYPE_17 +#define CONF_DMAC_TRANS_TYPE_17 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_17 == 0 +#define CONF_DMAC_TYPE_17 0 +#define CONF_DMAC_DSYNC_17 0 +#elif CONF_DMAC_TRANS_TYPE_17 == 1 +#define CONF_DMAC_TYPE_17 1 +#define CONF_DMAC_DSYNC_17 0 +#elif CONF_DMAC_TRANS_TYPE_17 == 2 +#define CONF_DMAC_TYPE_17 1 +#define CONF_DMAC_DSYNC_17 1 +#endif + +#if CONF_DMAC_TRIGSRC_17 == 0xFF +#define CONF_DMAC_SWREQ_17 1 +#else +#define CONF_DMAC_SWREQ_17 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2 \ + && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17))) +#if (!CONF_DMAC_SRCINC_17) +#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_17) +#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_17 +#define CONF_DMAC_SRC_STRIDE_17 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_17 +#define CONF_DMAC_DES_STRIDE_17 0 +#endif + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_18 +#ifndef CONF_DMAC_BURSTSIZE_18 +#define CONF_DMAC_BURSTSIZE_18 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_18 +#ifndef CONF_DMAC_CHUNKSIZE_18 +#define CONF_DMAC_CHUNKSIZE_18 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_18 +#ifndef CONF_DMAC_SRC_INTERFACE_18 +#define CONF_DMAC_SRC_INTERFACE_18 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_18 +#ifndef CONF_DMAC_DES_INTERFACE_18 +#define CONF_DMAC_DES_INTERFACE_18 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_18 +#ifndef CONF_DMAC_TRANS_TYPE_18 +#define CONF_DMAC_TRANS_TYPE_18 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_18 == 0 +#define CONF_DMAC_TYPE_18 0 +#define CONF_DMAC_DSYNC_18 0 +#elif CONF_DMAC_TRANS_TYPE_18 == 1 +#define CONF_DMAC_TYPE_18 1 +#define CONF_DMAC_DSYNC_18 0 +#elif CONF_DMAC_TRANS_TYPE_18 == 2 +#define CONF_DMAC_TYPE_18 1 +#define CONF_DMAC_DSYNC_18 1 +#endif + +#if CONF_DMAC_TRIGSRC_18 == 0xFF +#define CONF_DMAC_SWREQ_18 1 +#else +#define CONF_DMAC_SWREQ_18 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2 \ + && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18))) +#if (!CONF_DMAC_SRCINC_18) +#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_18) +#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_18 +#define CONF_DMAC_SRC_STRIDE_18 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_18 +#define CONF_DMAC_DES_STRIDE_18 0 +#endif + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_19 +#ifndef CONF_DMAC_BURSTSIZE_19 +#define CONF_DMAC_BURSTSIZE_19 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_19 +#ifndef CONF_DMAC_CHUNKSIZE_19 +#define CONF_DMAC_CHUNKSIZE_19 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_19 +#ifndef CONF_DMAC_SRC_INTERFACE_19 +#define CONF_DMAC_SRC_INTERFACE_19 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_19 +#ifndef CONF_DMAC_DES_INTERFACE_19 +#define CONF_DMAC_DES_INTERFACE_19 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_19 +#ifndef CONF_DMAC_TRANS_TYPE_19 +#define CONF_DMAC_TRANS_TYPE_19 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_19 == 0 +#define CONF_DMAC_TYPE_19 0 +#define CONF_DMAC_DSYNC_19 0 +#elif CONF_DMAC_TRANS_TYPE_19 == 1 +#define CONF_DMAC_TYPE_19 1 +#define CONF_DMAC_DSYNC_19 0 +#elif CONF_DMAC_TRANS_TYPE_19 == 2 +#define CONF_DMAC_TYPE_19 1 +#define CONF_DMAC_DSYNC_19 1 +#endif + +#if CONF_DMAC_TRIGSRC_19 == 0xFF +#define CONF_DMAC_SWREQ_19 1 +#else +#define CONF_DMAC_SWREQ_19 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2 \ + && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19))) +#if (!CONF_DMAC_SRCINC_19) +#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_19) +#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_19 +#define CONF_DMAC_SRC_STRIDE_19 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_19 +#define CONF_DMAC_DES_STRIDE_19 0 +#endif + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_20 +#ifndef CONF_DMAC_BURSTSIZE_20 +#define CONF_DMAC_BURSTSIZE_20 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_20 +#ifndef CONF_DMAC_CHUNKSIZE_20 +#define CONF_DMAC_CHUNKSIZE_20 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_20 +#ifndef CONF_DMAC_SRC_INTERFACE_20 +#define CONF_DMAC_SRC_INTERFACE_20 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_20 +#ifndef CONF_DMAC_DES_INTERFACE_20 +#define CONF_DMAC_DES_INTERFACE_20 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_20 +#ifndef CONF_DMAC_TRANS_TYPE_20 +#define CONF_DMAC_TRANS_TYPE_20 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_20 == 0 +#define CONF_DMAC_TYPE_20 0 +#define CONF_DMAC_DSYNC_20 0 +#elif CONF_DMAC_TRANS_TYPE_20 == 1 +#define CONF_DMAC_TYPE_20 1 +#define CONF_DMAC_DSYNC_20 0 +#elif CONF_DMAC_TRANS_TYPE_20 == 2 +#define CONF_DMAC_TYPE_20 1 +#define CONF_DMAC_DSYNC_20 1 +#endif + +#if CONF_DMAC_TRIGSRC_20 == 0xFF +#define CONF_DMAC_SWREQ_20 1 +#else +#define CONF_DMAC_SWREQ_20 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2 \ + && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20))) +#if (!CONF_DMAC_SRCINC_20) +#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_20) +#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_20 +#define CONF_DMAC_SRC_STRIDE_20 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_20 +#define CONF_DMAC_DES_STRIDE_20 0 +#endif + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_21 +#ifndef CONF_DMAC_BURSTSIZE_21 +#define CONF_DMAC_BURSTSIZE_21 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_21 +#ifndef CONF_DMAC_CHUNKSIZE_21 +#define CONF_DMAC_CHUNKSIZE_21 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_21 +#ifndef CONF_DMAC_SRC_INTERFACE_21 +#define CONF_DMAC_SRC_INTERFACE_21 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_21 +#ifndef CONF_DMAC_DES_INTERFACE_21 +#define CONF_DMAC_DES_INTERFACE_21 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_21 +#ifndef CONF_DMAC_TRANS_TYPE_21 +#define CONF_DMAC_TRANS_TYPE_21 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_21 == 0 +#define CONF_DMAC_TYPE_21 0 +#define CONF_DMAC_DSYNC_21 0 +#elif CONF_DMAC_TRANS_TYPE_21 == 1 +#define CONF_DMAC_TYPE_21 1 +#define CONF_DMAC_DSYNC_21 0 +#elif CONF_DMAC_TRANS_TYPE_21 == 2 +#define CONF_DMAC_TYPE_21 1 +#define CONF_DMAC_DSYNC_21 1 +#endif + +#if CONF_DMAC_TRIGSRC_21 == 0xFF +#define CONF_DMAC_SWREQ_21 1 +#else +#define CONF_DMAC_SWREQ_21 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2 \ + && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21))) +#if (!CONF_DMAC_SRCINC_21) +#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_21) +#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_21 +#define CONF_DMAC_SRC_STRIDE_21 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_21 +#define CONF_DMAC_DES_STRIDE_21 0 +#endif + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_22 +#ifndef CONF_DMAC_BURSTSIZE_22 +#define CONF_DMAC_BURSTSIZE_22 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_22 +#ifndef CONF_DMAC_CHUNKSIZE_22 +#define CONF_DMAC_CHUNKSIZE_22 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_22 +#ifndef CONF_DMAC_SRC_INTERFACE_22 +#define CONF_DMAC_SRC_INTERFACE_22 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_22 +#ifndef CONF_DMAC_DES_INTERFACE_22 +#define CONF_DMAC_DES_INTERFACE_22 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_22 +#ifndef CONF_DMAC_TRANS_TYPE_22 +#define CONF_DMAC_TRANS_TYPE_22 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_22 == 0 +#define CONF_DMAC_TYPE_22 0 +#define CONF_DMAC_DSYNC_22 0 +#elif CONF_DMAC_TRANS_TYPE_22 == 1 +#define CONF_DMAC_TYPE_22 1 +#define CONF_DMAC_DSYNC_22 0 +#elif CONF_DMAC_TRANS_TYPE_22 == 2 +#define CONF_DMAC_TYPE_22 1 +#define CONF_DMAC_DSYNC_22 1 +#endif + +#if CONF_DMAC_TRIGSRC_22 == 0xFF +#define CONF_DMAC_SWREQ_22 1 +#else +#define CONF_DMAC_SWREQ_22 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2 \ + && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22))) +#if (!CONF_DMAC_SRCINC_22) +#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_22) +#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_22 +#define CONF_DMAC_SRC_STRIDE_22 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_22 +#define CONF_DMAC_DES_STRIDE_22 0 +#endif + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Burst Size +// <0x0=> 1 burst size +// <0x1=> 4 burst size +// <0x2=> 8 burst size +// <0x3=> 16 burst size +// Define the memory burst size +// dmac_burstsize_23 +#ifndef CONF_DMAC_BURSTSIZE_23 +#define CONF_DMAC_BURSTSIZE_23 0x0 +#endif + +// Chunk Size +// <0x0=> 1 data transferred +// <0x1=> 2 data transferred +// <0x2=> 4 data transferred +// <0x3=> 8 data transferred +// <0x4=> 16 data transferred +// Define the peripheral chunk size +// dmac_chunksize_23 +#ifndef CONF_DMAC_CHUNKSIZE_23 +#define CONF_DMAC_CHUNKSIZE_23 0x0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0x0 +#endif + +// Source Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is read through the system bus interface 0 or 1 +// dma_src_interface_23 +#ifndef CONF_DMAC_SRC_INTERFACE_23 +#define CONF_DMAC_SRC_INTERFACE_23 0x0 +#endif + +// Destination Interface Identifier +// <0x0=> AHB_IF0 +// <0x1=> AHB_IF1 +// Define the data is written through the system bus interface 0 or 1 +// dma_des_interface_23 +#ifndef CONF_DMAC_DES_INTERFACE_23 +#define CONF_DMAC_DES_INTERFACE_23 0x0 +#endif + +// Source Address Increment +// Indicates whether the source address incremented as beat size or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incremented as beat size or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Transfer Type +// <0x0=> Memory to Memory Transfer +// <0x1=> Peripheral to Memory Transfer +// <0x2=> Memory to Peripheral Transfer +// Define the data transfer type +// dma_trans_type_23 +#ifndef CONF_DMAC_TRANS_TYPE_23 +#define CONF_DMAC_TRANS_TYPE_23 0x0 +#endif + +// Trigger source +// <0xFF=> Software Trigger +// <0x00=> HSMCI TX/RX Trigger +// <0x01=> SPI0 TX Trigger +// <0x02=> SPI0 RX Trigger +// <0x03=> SPI1 TX Trigger +// <0x04=> SPI1 RX Trigger +// <0x05=> QSPI TX Trigger +// <0x06=> QSPI RX Trigger +// <0x07=> USART0 TX Trigger +// <0x08=> USART0 RX Trigger +// <0x09=> USART1 TX Trigger +// <0x0A=> USART1 RX Trigger +// <0x0B=> USART2 TX Trigger +// <0x0C=> USART2 RX Trigger +// <0x0D=> PWM0 TX Trigger +// <0x0E=> TWIHS0 TX Trigger +// <0x0F=> TWIHS0 RX Trigger +// <0x10=> TWIHS1 TX Trigger +// <0x11=> TWIHS1 RX Trigger +// <0x12=> TWIHS2 TX Trigger +// <0x13=> TWIHS2 RX Trigger +// <0x14=> UART0 TX Trigger +// <0x15=> UART0 RX Trigger +// <0x16=> UART1 TX Trigger +// <0x17=> UART1 RX Trigger +// <0x18=> UART2 TX Trigger +// <0x19=> UART2 RX Trigger +// <0x1A=> UART3 TX Trigger +// <0x1B=> UART3 RX Trigger +// <0x1C=> UART4 TX Trigger +// <0x1D=> UART4 RX Trigger +// <0x1E=> DACC TX Trigger +// <0x20=> SSC TX Trigger +// <0x21=> SSC RX Trigger +// <0x22=> PIOA RX Trigger +// <0x23=> AFEC0 RX Trigger +// <0x24=> AFEC1 RX Trigger +// <0x25=> AES TX Trigger +// <0x26=> AES RX Trigger +// <0x27=> PWM1 TX Trigger +// <0x28=> TC0 RX Trigger +// <0x29=> TC3 RX Trigger +// <0x2A=> TC6 RX Trigger +// <0x2B=> TC9 RX Trigger +// <0x2C=> I2SC0 TX Left Trigger +// <0x2D=> I2SC0 RX Left Trigger +// <0x2E=> I2SC1 TX Left Trigger +// <0x2F=> I2SC1 RX Left Trigger +// <0x30=> I2SC0 TX Right Trigger +// <0x31=> I2SC0 RX Right Trigger +// <0x32=> I2SC1 TX Right Trigger +// <0x33=> I2SC1 RX Right Trigger +// Define the DMA trigger source +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0xff +#endif + +// + +#if CONF_DMAC_TRANS_TYPE_23 == 0 +#define CONF_DMAC_TYPE_23 0 +#define CONF_DMAC_DSYNC_23 0 +#elif CONF_DMAC_TRANS_TYPE_23 == 1 +#define CONF_DMAC_TYPE_23 1 +#define CONF_DMAC_DSYNC_23 0 +#elif CONF_DMAC_TRANS_TYPE_23 == 2 +#define CONF_DMAC_TYPE_23 1 +#define CONF_DMAC_DSYNC_23 1 +#endif + +#if CONF_DMAC_TRIGSRC_23 == 0xFF +#define CONF_DMAC_SWREQ_23 1 +#else +#define CONF_DMAC_SWREQ_23 0 +#endif + +/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address + * or fixed destination address mode, source and destination addresses are incremented + * by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing mode to + * use microblock and data striding with microblock stride set to 0 and data stride set to -1. + */ +#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2 \ + && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23))) +#if (!CONF_DMAC_SRCINC_23) +#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1)) +#endif +#if (!CONF_DMAC_DSTINC_23) +#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1)) +#endif +#endif + +#ifndef CONF_DMAC_SRC_STRIDE_23 +#define CONF_DMAC_SRC_STRIDE_23 0 +#endif + +#ifndef CONF_DMAC_DES_STRIDE_23 +#define CONF_DMAC_DES_STRIDE_23 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_XDMAC_CONFIG_H diff --git a/bsp/microchip/same70/bsp/config/peripheral_clk_config.h b/bsp/microchip/same70/bsp/config/peripheral_clk_config.h new file mode 100644 index 0000000000..ee87cce4a9 --- /dev/null +++ b/bsp/microchip/same70/bsp/config/peripheral_clk_config.h @@ -0,0 +1,99 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_HCLK_FREQUENCY + * \brief HCLK's Clock frequency + */ +#ifndef CONF_HCLK_FREQUENCY +#define CONF_HCLK_FREQUENCY 300000000 +#endif + +/** + * \def CONF_FCLK_FREQUENCY + * \brief FCLK's Clock frequency + */ +#ifndef CONF_FCLK_FREQUENCY +#define CONF_FCLK_FREQUENCY 300000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 300000000 +#endif + +/** + * \def CONF_SLCK_FREQUENCY + * \brief Slow Clock frequency + */ +#define CONF_SLCK_FREQUENCY 0 + +/** + * \def CONF_MCK_FREQUENCY + * \brief Master Clock frequency + */ +#define CONF_MCK_FREQUENCY 150000000 + +/** + * \def CONF_PCK6_FREQUENCY + * \brief Programmable Clock Controller 6 frequency + */ +#define CONF_PCK6_FREQUENCY 1714285 + +// USART Clock Settings +// USART Clock source + +// <0=> Master Clock (MCK) +// <1=> MCK / 8 for USART +// <2=> Programmable Clock Controller 4 (PMC_PCK4) +// <3=> External Clock +// This defines the clock source for the USART +// usart_clock_source +#ifndef CONF_USART1_CK_SRC +#define CONF_USART1_CK_SRC 0 +#endif + +// USART External Clock Input on SCK <1-4294967295> +// Inputs the external clock frequency on SCK +// usart_clock_freq +#ifndef CONF_USART1_SCK_FREQ +#define CONF_USART1_SCK_FREQ 10000000 +#endif + +// + +/** + * \def USART FREQUENCY + * \brief USART's Clock frequency + */ +#ifndef CONF_USART1_FREQUENCY +#define CONF_USART1_FREQUENCY 150000000 +#endif + +// MCAN Clock Settings +// MCAN Clock source +// Programmable Clock Controller 5 (PMC_PCK5) +// This defines the clock source for the MCAN +// mcan_clock_source +#ifndef CONF_MCAN1_SRC +#define CONF_MCAN1_SRC CONF_SRC_PCK5 +#endif +// + +/** + * \def MCAN FREQUENCY + * \brief MCAN's Clock frequency + */ +#ifndef CONF_MCAN1_FREQUENCY +#define CONF_MCAN1_FREQUENCY 40000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/bsp/microchip/same70/bsp/documentation/led_switcher.rst b/bsp/microchip/same70/bsp/documentation/led_switcher.rst new file mode 100644 index 0000000000..aa085e0afc --- /dev/null +++ b/bsp/microchip/same70/bsp/documentation/led_switcher.rst @@ -0,0 +1,11 @@ +=========== +LED Flasher +=========== + +This example toggles the on-board LED marked as LED0 every time the button SW0 +is pressed. + +Drivers +------- +* GPIO +* Delay diff --git a/bsp/microchip/same70/bsp/driver_init.c b/bsp/microchip/same70/bsp/driver_init.c new file mode 100644 index 0000000000..98cb54d45f --- /dev/null +++ b/bsp/microchip/same70/bsp/driver_init.c @@ -0,0 +1,124 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include +#include +#include + +struct can_async_descriptor CAN_0; + +struct usart_sync_descriptor TARGET_IO; + +void delay_driver_init(void) +{ + delay_init(SysTick); +} + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PA21, MUX_PA21A_USART1_RXD1); + + gpio_set_pin_function(PB4, MUX_PB4D_USART1_TXD1); +} + +void TARGET_IO_CLOCK_init(void) +{ + _pmc_enable_periph_clock(ID_USART1); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + TARGET_IO_PORT_init(); + usart_sync_init(&TARGET_IO, USART1, _usart_get_usart_sync()); +} + +/** + * \brief MCAN Clock initialization function + * + * Enables register interface and peripheral clock + */ +void CAN_0_CLOCK_init() +{ + _pmc_enable_periph_clock(ID_MCAN1); +} + +/** + * \brief MCAN pinmux initialization function + * + * Set each required pin to MCAN functionality + */ +void CAN_0_PORT_init(void) +{ + + gpio_set_pin_function(PC12, MUX_PC12C_MCAN1_CANRX1); + + gpio_set_pin_function(PC14, MUX_PC14C_MCAN1_CANTX1); +} +/** + * \brief CAN initialization function + * + * Enables CAN peripheral, clocks and initializes CAN driver + */ +void CAN_0_init(void) +{ + CAN_0_CLOCK_init(); + CAN_0_PORT_init(); + can_async_init(&CAN_0, MCAN1); +} + +void system_init(void) +{ + init_mcu(); + + _pmc_enable_periph_clock(ID_PIOA); + + _pmc_enable_periph_clock(ID_PIOC); + + /* Disable Watchdog */ + hri_wdt_set_MR_WDDIS_bit(WDT); + + /* GPIO on PA11 */ + + // Set pin direction to input + gpio_set_pin_direction(SW0, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(SW0, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_UP); + + gpio_set_pin_function(SW0, GPIO_PIN_FUNCTION_OFF); + + /* GPIO on PC8 */ + + gpio_set_pin_level(LED0, + // Initial level + // pad_initial_level + // Low + // High + true); + + // Set pin direction to output + gpio_set_pin_direction(LED0, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF); + + delay_driver_init(); + + TARGET_IO_init(); + + CAN_0_init(); +} diff --git a/bsp/microchip/same70/bsp/driver_init.h b/bsp/microchip/same70/bsp/driver_init.h new file mode 100644 index 0000000000..06cb71eca9 --- /dev/null +++ b/bsp/microchip/same70/bsp/driver_init.h @@ -0,0 +1,53 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_H_INCLUDED +#define DRIVER_INIT_H_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +extern struct usart_sync_descriptor TARGET_IO; +extern struct can_async_descriptor CAN_0; + +void delay_driver_init(void); + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +void CAN_0_PORT_init(void); +void CAN_0_CLOCK_init(void); +void CAN_0_init(void); +void CAN_0_example(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_H_INCLUDED diff --git a/bsp/microchip/same70/bsp/examples/driver_examples.c b/bsp/microchip/same70/bsp/examples/driver_examples.c new file mode 100644 index 0000000000..116cc2adb8 --- /dev/null +++ b/bsp/microchip/same70/bsp/examples/driver_examples.c @@ -0,0 +1,89 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +void delay_example(void) +{ + delay_ms(5000); +} + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void CAN_0_tx_callback(struct can_async_descriptor *const descr) +{ + (void)descr; +} +void CAN_0_rx_callback(struct can_async_descriptor *const descr) +{ + struct can_message msg; + uint8_t data[64]; + msg.data = data; + can_async_read(descr, &msg); + return; +} + +/** + * Example of using CAN_0 to Encrypt/Decrypt datas. + */ +void CAN_0_example(void) +{ + struct can_message msg; + struct can_filter filter; + uint8_t send_data[4]; + send_data[0] = 0x00; + send_data[1] = 0x01; + send_data[2] = 0x02; + send_data[3] = 0x03; + + msg.id = 0x45A; + msg.type = CAN_TYPE_DATA; + msg.data = send_data; + msg.len = 4; + msg.fmt = CAN_FMT_STDID; + can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)CAN_0_tx_callback); + can_async_enable(&CAN_0); + /** + * CAN_0_tx_callback callback should be invoked after call + * can_async_write, and remote device should recieve message with ID=0x45A + */ + can_async_write(&CAN_0, &msg); + + msg.id = 0x100000A5; + msg.fmt = CAN_FMT_EXTID; + /** + * remote device should recieve message with ID=0x100000A5 + */ + can_async_write(&CAN_0, &msg); + + /** + * CAN_0_rx_callback callback should be invoked after call + * can_async_set_filter and remote device send CAN Message with the same + * content as the filter. + */ + can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)CAN_0_rx_callback); + filter.id = 0x469; + filter.mask = 0; + can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter); + + filter.id = 0x10000096; + filter.mask = 0; + can_async_set_filter(&CAN_0, 1, CAN_FMT_EXTID, &filter); +} diff --git a/bsp/microchip/same70/bsp/examples/driver_examples.h b/bsp/microchip/same70/bsp/examples/driver_examples.h new file mode 100644 index 0000000000..5aa87ac195 --- /dev/null +++ b/bsp/microchip/same70/bsp/examples/driver_examples.h @@ -0,0 +1,29 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "atmel_start.h" +#include "utils.h" + +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void delay_example(void); + +void TARGET_IO_example(void); + +void CAN_0_example(void); + +#ifdef __cplusplus +} +#endif + +#endif // DRIVER_EXAMPLES_H_INCLUDEDD diff --git a/bsp/microchip/same70/bsp/hal/documentation/can_async.rst b/bsp/microchip/same70/bsp/hal/documentation/can_async.rst new file mode 100644 index 0000000000..7574b19ddb --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/documentation/can_async.rst @@ -0,0 +1,42 @@ +================================================= +CAN (Controller Area Network) Asynchronous Driver +================================================= + +The Controller Area Network (CAN) performs communication according to +ISO11898-1 (Bosch CAN specification 2.0 part A,B) + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* CAN message transfer: transmission, reception +* Callback on message transmited, recepted, error +* Callback on error warning, error active, error passive, bus off, data overrun +* Set CAN mode: normal, monitoring + +Applications +------------ + +Transmission and reception CAN meesage in a CAN Network. + +Dependencies +------------ + +CAN capable hardware compatible with the ISO11898-1 (Bosch CAN specification +2.0 part A,B) + +Concurrency +----------- + +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/same70/bsp/hal/documentation/usart_sync.rst b/bsp/microchip/same70/bsp/hal/documentation/usart_sync.rst new file mode 100644 index 0000000000..15e4b13885 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/bsp/microchip/same70/bsp/hal/include/hal_atomic.h b/bsp/microchip/same70/bsp/hal/include/hal_atomic.h new file mode 100644 index 0000000000..82151fc5d5 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_can_async.h b/bsp/microchip/same70/bsp/hal/include/hal_can_async.h new file mode 100644 index 0000000000..4ed993eb8f --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_can_async.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_CAN_ASYNC_H_INCLUDED +#define HAL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \addtogroup doc_driver_hal_can_async + * + *@{ + */ + +/** + * \brief CAN Asynchronous descriptor + * + * The CAN descriptor forward declaration. + */ +struct can_async_descriptor; + +/** + * Callback for CAN interrupt + */ +typedef void (*can_cb_t)(struct can_async_descriptor *const descr); + +/** + * \brief CAN callbacks + */ +struct can_callbacks { + can_cb_t tx_done; + can_cb_t rx_done; + void (*irq_handler)(struct can_async_descriptor *const descr, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN descriptor + */ +struct can_async_descriptor { + struct _can_async_device dev; /*!< CAN HPL device descriptor */ + struct can_callbacks cb; /*!< CAN Interrupt Callbacks handler */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN descriptor. + * + * \param[in, out] descr A CAN descriptor to initialize. + * \param[in] hw The pointer to hardware instance. + * + * \return Initialization status. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given CAN descriptor. + * + * \param[in, out] descr The CAN descriptor to deinitialize. + * + * \return De-initialization status. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr); + +/** + * \brief Enable CAN + * + * This function enables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to enable. + * + * \return Enabling status. + */ +int32_t can_async_enable(struct can_async_descriptor *const descr); + +/** + * \brief Disable CAN + * + * This function disables CAN by the given can descriptor. + * + * \param[in] descr The CAN descriptor to disable. + * + * \return Disabling status. + */ +int32_t can_async_disable(struct can_async_descriptor *const descr); + +/** + * \brief Read a CAN message + * + * \param[in] descr The CAN descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] descr The CAN descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg); + +/** + * \brief Register CAN callback function to interrupt + * + * \param[in] descr The CAN descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL will de-register any + * registered callback + * + * \return The status of callback assignment. + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb); + +/** + * \brief Return number of read errors + * + * This function returns the number of read errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of read errors. + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr); + +/** + * \brief Return number of write errors + * + * This function returns the number of write errors. + * + * \param[in] descr The CAN descriptor pointer + * + * \return The number of write errors. + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr); + +/** + * \brief Set CAN to the specified mode + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] mode The CAN operation mode + * + * \return Status of the operation. + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode); + +/** + * \brief Set CAN Filter + * + * This function sets CAN to a specified mode. + * + * \param[in] descr The CAN descriptor pointer + * \param[in] index Index of Filter list + * \param[in] fmt CAN Indentify Type + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation. + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/** + * \brief Retrieve the current driver version + * + * \return The current driver version. + */ +uint32_t can_async_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_delay.h b/bsp/microchip/same70/bsp/hal/include/hal_delay.h new file mode 100644 index 0000000000..9d4aa5c1bc --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_gpio.h b/bsp/microchip/same70/bsp/hal/include/hal_gpio.h new file mode 100644 index 0000000000..fbfa2d4aec --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/same70/bsp/hal/include/hal_init.h b/bsp/microchip/same70/bsp/hal/include/hal_init.h new file mode 100644 index 0000000000..d7bc6fe209 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_io.h b/bsp/microchip/same70/bsp/hal/include/hal_io.h new file mode 100644 index 0000000000..f50401d7a6 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_sleep.h b/bsp/microchip/same70/bsp/hal/include/hal_sleep.h new file mode 100644 index 0000000000..b90ef6a5b6 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hal_usart_sync.h b/bsp/microchip/same70/bsp/hal/include/hal_usart_sync.h new file mode 100644 index 0000000000..1ef22fc63f --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_can.h b/bsp/microchip/same70/bsp/hal/include/hpl_can.h new file mode 100644 index 0000000000..80b53138d3 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_can.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_H_INCLUDED +#define HPL_CAN_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can CAN Common declaration + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN Message Format + */ +enum can_format { + CAN_FMT_STDID, /*!< Standard Format, 11 bits identifier */ + CAN_FMT_EXTID /*!< Extended Format, 29 bits identifier */ +}; + +/** + * \brief CAN Message Type + */ +enum can_type { + CAN_TYPE_DATA, /*!< A DATA FRAME carries data from a transmitter to the + receivers.*/ + CAN_TYPE_REMOTE /*!< A REMOTE FRAME is transmitted by a bus unit to request + the transmission of the DATA FRAME with the same + IDENTIFIER */ +}; + +/** + * \brief CAN Bus Mode + */ +enum can_mode { + /** Normal operation Mode */ + CAN_MODE_NORMAL, + /** In Bus Monitoring mode (see ISO11898-1, 10.12 Bus monitoring), the CAN + * is able to receive valid data frames and valid remote frames, but + * cannot start a transmission. In this mode, it sends only recessive bits + * on the CAN bus. If the CAN is required to send a dominant bit (ACK bit, + * overload flag, active error flag), the bit is rerouted internally so + * that the CAN monitors this dominant bit, although the CAN bus may + * remain in recessive state. + * The Bus Monitoring mode can be used to analyze the traffic on a CAN bus + * without affecting it by the transmission of dominant bits. + */ + CAN_MODE_MONITORING +}; + +/** + * \brief CAN Message + */ +struct can_message { + uint32_t id; /* Message identifier */ + enum can_type type; /* Message Type */ + uint8_t * data; /* Pointer to Message Data */ + uint8_t len; /* Message Length */ + enum can_format fmt; /* Identifier format, CAN_STD, CAN_EXT */ +}; + +/** + * \brief CAN Filter + */ +struct can_filter { + uint32_t id; /* Message identifier */ + uint32_t mask; /* The mask applied to the id */ +}; + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_can_async.h b/bsp/microchip/same70/bsp/hal/include/hpl_can_async.h new file mode 100644 index 0000000000..ba82672549 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_can_async.h @@ -0,0 +1,245 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_ASYNC_H_INCLUDED +#define HPL_CAN_ASYNC_H_INCLUDED + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup hpl_can_async CAN HPL Driver + * + * \section can_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief CAN device descriptor forware declaration + */ +struct _can_async_device; + +/** + * \brief CAN callback types + */ +enum can_async_callback_type { + CAN_ASYNC_RX_CB, /*!< A new message arrived */ + CAN_ASYNC_TX_CB, /*!< A message transmitted */ + CAN_ASYNC_IRQ_CB /*!< Message error of some kind on the CAN bus IRQ */ +}; + +enum can_async_interrupt_type { + CAN_IRQ_EW, /*!< Error warning, Error counter has reached the + error warning limit of 96, An error count value + greater than about 96 indicates a heavily disturbed + bus. It may be of advantage to provide means to test + for this condition. Refer to ISO 11898-1 (Bosch CAN + specification 2.0 part A,B) + */ + CAN_IRQ_EA, /*!< Error Active State, The CAN node normally take + part in bus communication and sends an ACTIVE ERROR + FLAG when an error has been detected. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_EP, /*!< Error Passive State, The Can node goes into error + passive state if at least one of its error counters is + greater than 127. It still takes part in bus + activities, but it sends a passive error frame only, + on errors. Refer to ISO 11898-1 (7) + */ + CAN_IRQ_BO, /*!< Bus Off State, The CAN node is 'bus off' when the + TRANSMIT ERROR COUNT is greater than or equal to 256. + Refer to ISO 11898-1 (7) + */ + CAN_IRQ_DO /*!< Data Overrun in receive queue. A message was lost + because the messages in the queue was not reading and + releasing fast enough. There is not enough space for + a new message in receive queue. + */ +}; +/** + * \brief CAN interrupt handlers structure + */ +struct _can_async_callback { + void (*tx_done)(struct _can_async_device *dev); + void (*rx_done)(struct _can_async_device *dev); + void (*irq_handler)(struct _can_async_device *dev, enum can_async_interrupt_type type); +}; + +/** + * \brief CAN device descriptor + */ +struct _can_async_device { + void * hw; /*!< CAN hardware pointer */ + struct _can_async_callback cb; /*!< CAN interrupt handler */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * context; /*!< CAN hardware context */ +}; + +/** + * \brief Initialize CAN. + * + * This function initializes the given CAN device descriptor. + * + * \param[in, out] dev A CAN device descriptor to initialize + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw); + +/** + * \brief Deinitialize CAN. + * + * This function deinitializes the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev); + +/** + * \brief Enable CAN + * + * This function enable CAN by the given can device descriptor. + * + * \param[in] dev The CAN device descriptor to enable + * + * \return Enabling status. + */ +int32_t _can_async_enable(struct _can_async_device *const dev); + +/** + * \brief Disable CAN + * + * This function disable CAN by the given can device descriptor. + * + * \param[in] dev The CAN descriptor to disable + * + * \return Disabling status. + */ +int32_t _can_async_disable(struct _can_async_device *const dev); + +/** + * \brief Read a CAN message + * + * \param[in] dev The CAN device descriptor to read message. + * \param[in] msg The CAN message to read to. + * + * \return The status of read message. + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Write a CAN message + * + * \param[in] dev The CAN device descriptor to write message. + * \param[in] msg The CAN message to write. + * + * \return The status of write message. + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg); + +/** + * \brief Set CAN Interrupt State + * + * \param[in] dev The CAN device descriptor + * \param[in] type Callback type + * \param[in] state ture for enable or false for disable + * + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state); + +/** + * \brief Return number of read errors + * + * This function return number of read errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of read errors. + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev); + +/** + * \brief Return number of write errors + * + * This function return number of write errors + * + * \param[in] dev The CAN device descriptor pointer + * + * \return Number of write errors. + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] mode CAN operation mode + * + * \return Status of the operation + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode); + +/** + * \brief Set CAN to the specified mode + * + * This function set CAN to a specified mode + * + * \param[in] dev The CAN device descriptor pointer + * \param[in] index Index of Filter list + * \param[in] filter CAN Filter struct, NULL for clear filter + * + * \return Status of the operation + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_core.h b/bsp/microchip/same70/bsp/hal/include/hpl_core.h new file mode 100644 index 0000000000..9324c43e7c --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_delay.h b/bsp/microchip/same70/bsp/hal/include/hpl_delay.h new file mode 100644 index 0000000000..a0f1ac8125 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_dma.h b/bsp/microchip/same70/bsp/hal/include/hpl_dma.h new file mode 100644 index 0000000000..1e08434a16 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_ext_irq.h b/bsp/microchip/same70/bsp/hal/include/hpl_ext_irq.h new file mode 100644 index 0000000000..3a169b69da --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_ext_irq.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief External IRQ related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EXT_IRQ_H_INCLUDED +#define _HPL_EXT_IRQ_H_INCLUDED + +/** + * \addtogroup HPL EXT IRQ + * + * \section hpl_ext_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize external interrupt module + * + * This function does low level external interrupt configuration. + * + * \param[in] cb The pointer to callback function from external interrupt + * + * \return Initialization status. + * \retval -1 External irq module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); + +/** + * \brief Deinitialize external interrupt module + * + * \return Initialization status. + * \retval -1 External irq module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t _ext_irq_deinit(void); + +/** + * \brief Enable / disable external irq + * + * \param[in] pin Pin to enable external irq on + * \param[in] enable True to enable, false to disable + * + * \return Status of external irq enabling / disabling + * \retval -1 External irq module can't be enabled / disabled + * \retval 0 External irq module is enabled / disabled successfully + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EXT_IRQ_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_gpio.h b/bsp/microchip/same70/bsp/hal/include/hpl_gpio.h new file mode 100644 index 0000000000..5cdd387b89 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_init.h b/bsp/microchip/same70/bsp/hal/include/hpl_init.h new file mode 100644 index 0000000000..71bf49c98e --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_irq.h b/bsp/microchip/same70/bsp/hal/include/hpl_irq.h new file mode 100644 index 0000000000..2894944a0d --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_missing_features.h b/bsp/microchip/same70/bsp/hal/include/hpl_missing_features.h new file mode 100644 index 0000000000..7071db297c --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_reset.h b/bsp/microchip/same70/bsp/hal/include/hpl_reset.h new file mode 100644 index 0000000000..55afbcac9e --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_reset.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + + RESET_TYPE_GENERAL = 0, + RESET_TYPE_BACKUP = 1, + RESET_TYPE_WDT = 2, + RESET_TYPE_SOFT = 3, + RESET_TYPE_USER = 4, + RESET_TYPE_CPU_FAIL = 6, + RESET_TYPE_SLCK_XTA = 7 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_sleep.h b/bsp/microchip/same70/bsp/hal/include/hpl_sleep.h new file mode 100644 index 0000000000..6731ec30e4 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_time_measure.h b/bsp/microchip/same70/bsp/hal/include/hpl_time_measure.h new file mode 100644 index 0000000000..5d688df5f5 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_time_measure.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Time measure related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIME_MEASURE_H_INCLUDED +#define _HPL_TIME_MEASURE_H_INCLUDED + +/** + * \addtogroup HPL Time measure + * + * \section hpl_time_measure_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief System time type + */ +typedef uint32_t system_time_t; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_init(void *const hw); + +/** + * \brief Deinitialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_deinit(void *const hw); + +/** + * \brief Get system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get(const void *const hw); + +/** + * \brief Get maximum possible system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get_max_time_value(const void *const hw); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_usart.h b/bsp/microchip/same70/bsp/hal/include/hpl_usart.h new file mode 100644 index 0000000000..0e09501d7a --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_usart_async.h b/bsp/microchip/same70/bsp/hal/include/hpl_usart_async.h new file mode 100644 index 0000000000..3f833d1ae1 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_usart_dma.h b/bsp/microchip/same70/bsp/hal/include/hpl_usart_dma.h new file mode 100644 index 0000000000..881625d93c --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_usart_dma.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_DMA_H_INCLUDED +#define _HPL_USART_DMA_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum usart_dma_callback_type { USART_DMA_RX_DONE, USART_DMA_TX_DONE, USART_DMA_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_dma_device; + +/** + * \brief The prototype for callback on USART DMA. + */ +typedef void (*usart_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief USART interrupt callbacks + */ +struct _usart_dma_callbacks { + usart_dma_cb_t tx_done_cb; + usart_dma_cb_t rx_done_cb; + usart_dma_cb_t error_cb; +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_dma_device { + struct _usart_dma_callbacks usart_cb; + void * hw; + struct _dma_resource * resource; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize dmahronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_dma_init(struct _usart_dma_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_dma_deinit(struct _usart_dma_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_dma_enable(struct _usart_dma_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_dma_disable(struct _usart_dma_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_dma_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_dma_set_baud_rate(struct _usart_dma_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_dma_set_data_order(struct _usart_dma_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_dma_set_mode(struct _usart_dma_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_dma_set_parity(struct _usart_dma_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_dma_set_stop_bits(struct _usart_dma_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_dma_set_character_size(struct _usart_dma_device *const device, const enum usart_character_size size); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_dma_set_flow_control_state(struct _usart_dma_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Eanble dma write + * + * \param[in] device The pointer to USART device instance + * \param[in] txbuf Pointer to the transfer information + * \param[in] length spi transfer data length + * + * \return Operation status + * \retval ERR_NONE Success + * \retval ERR_INVALID_DATA Invalid data + */ +int32_t _usart_dma_write(struct _usart_dma_device *const device, uint8_t const *txbuf, const uint16_t length); + +/** + * \brief Eanble dma read + * + * \param[in] device The pointer to USART device instance + * \param[out] rxbuf Pointer to the receiver information + * \param[in] length spi receiver data length + * + * \return Operation status + * \retval ERR_NONE Success + * \retval ERR_INVALID_DATA Invalid data + */ +int32_t _usart_dma_read(struct _usart_dma_device *const device, uint8_t *const rxbuf, const uint16_t length); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_dma_register_callback(struct _usart_dma_device *const device, const enum usart_dma_callback_type type, + usart_dma_cb_t cb); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_DMA_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/include/hpl_usart_sync.h b/bsp/microchip/same70/bsp/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000000..abc7264f2d --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/src/hal_atomic.c b/bsp/microchip/same70/bsp/hal/src/hal_atomic.c new file mode 100644 index 0000000000..f56418ee6f --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_can_async.c b/bsp/microchip/same70/bsp/hal/src/hal_can_async.c new file mode 100644 index 0000000000..84c75c45cd --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_can_async.c @@ -0,0 +1,230 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +#define DRIVER_VERSION 0x00000001u + +/** + * \internal Callback of CAN Message Write finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_tx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Message Read finished + * + * \param[in] dev The pointer to CAN device structure + */ +static void can_rx_done(struct _can_async_device *dev); +/** + * \internal Callback of CAN Interrupt + * + * \param[in] dev The pointer to CAN device structure + * \param[in] type Interrupt source type + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type); + +/** + * \brief Initialize CAN. + */ +int32_t can_async_init(struct can_async_descriptor *const descr, void *const hw) +{ + int32_t rc; + + ASSERT(descr && hw); + + rc = _can_async_init(&descr->dev, hw); + if (rc) { + return rc; + } + descr->dev.cb.tx_done = can_tx_done; + descr->dev.cb.rx_done = can_rx_done; + descr->dev.cb.irq_handler = can_irq_handler; + + return ERR_NONE; +} + +/** + * \brief Deinitialize CAN. + */ +int32_t can_async_deinit(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_deinit(&descr->dev); +} + +/** + * \brief Enable CAN + */ +int32_t can_async_enable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_enable(&descr->dev); +} + +/** + * \brief Disable CAN + */ +int32_t can_async_disable(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_disable(&descr->dev); +} + +/** + * \brief Read a CAN message + */ +int32_t can_async_read(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_read(&descr->dev, msg); +} + +/** + * \brief Write a CAN message + */ +int32_t can_async_write(struct can_async_descriptor *const descr, struct can_message *msg) +{ + ASSERT(descr && msg); + return _can_async_write(&descr->dev, msg); +} + +/** + * \brief Register CAN callback function to interrupt + */ +int32_t can_async_register_callback(struct can_async_descriptor *const descr, enum can_async_callback_type type, + FUNC_PTR cb) +{ + ASSERT(descr); + + switch (type) { + case CAN_ASYNC_RX_CB: + descr->cb.rx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_TX_CB: + descr->cb.tx_done = (cb != NULL) ? (can_cb_t)cb : NULL; + break; + case CAN_ASYNC_IRQ_CB: + descr->cb.irq_handler + = (cb != NULL) ? (void (*)(struct can_async_descriptor *const, enum can_async_interrupt_type))cb : NULL; + break; + default: + return ERR_INVALID_ARG; + } + + _can_async_set_irq_state(&descr->dev, type, NULL != cb); + + return ERR_NONE; +} + +/** + * \brief Return number of read errors + */ +uint8_t can_async_get_rxerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_rxerr(&descr->dev); +} + +/** + * \brief Return number of write errors + */ +uint8_t can_async_get_txerr(struct can_async_descriptor *const descr) +{ + ASSERT(descr); + return _can_async_get_txerr(&descr->dev); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t can_async_set_mode(struct can_async_descriptor *const descr, enum can_mode mode) +{ + ASSERT(descr); + return _can_async_set_mode(&descr->dev, mode); +} + +/** + * \brief Set CAN filter + */ +int32_t can_async_set_filter(struct can_async_descriptor *const descr, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + ASSERT(descr); + return _can_async_set_filter(&descr->dev, index, fmt, filter); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t can_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Callback of CAN Message Write finished + */ +static void can_tx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.tx_done) { + descr->cb.tx_done(descr); + } +} + +/** + * \internal Callback of CAN Message Read finished + */ +static void can_rx_done(struct _can_async_device *dev) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.rx_done) { + descr->cb.rx_done(descr); + } +} + +/** + * \internal Callback of CAN Interrupt + */ +static void can_irq_handler(struct _can_async_device *dev, enum can_async_interrupt_type type) +{ + struct can_async_descriptor *const descr = CONTAINER_OF(dev, struct can_async_descriptor, dev); + + if (descr->cb.irq_handler) { + descr->cb.irq_handler(descr, type); + } +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_delay.c b/bsp/microchip/same70/bsp/hal/src/hal_delay.c new file mode 100644 index 0000000000..6f77cc7064 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_gpio.c b/bsp/microchip/same70/bsp/hal/src/hal_gpio.c new file mode 100644 index 0000000000..00dfea6f70 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_init.c b/bsp/microchip/same70/bsp/hal/src/hal_init.c new file mode 100644 index 0000000000..fb65341fb6 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_io.c b/bsp/microchip/same70/bsp/hal/src/hal_io.c new file mode 100644 index 0000000000..7e8feb0453 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_sleep.c b/bsp/microchip/same70/bsp/hal/src/hal_sleep.c new file mode 100644 index 0000000000..89472f156a --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/bsp/microchip/same70/bsp/hal/src/hal_usart_sync.c b/bsp/microchip/same70/bsp/hal/src/hal_usart_sync.c new file mode 100644 index 0000000000..ab99c1d166 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/bsp/microchip/same70/bsp/hal/utils/include/compiler.h b/bsp/microchip/same70/bsp/hal/utils/include/compiler.h new file mode 100644 index 0000000000..f35db3df8e --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/err_codes.h b/bsp/microchip/same70/bsp/hal/utils/include/err_codes.h new file mode 100644 index 0000000000..a7aff01893 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/bsp/microchip/same70/bsp/hal/utils/include/events.h b/bsp/microchip/same70/bsp/hal/utils/include/events.h new file mode 100644 index 0000000000..3ee891a73e --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/parts.h b/bsp/microchip/same70/bsp/hal/utils/include/parts.h new file mode 100644 index 0000000000..6b7a4f5e06 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "sam.h" + +#include "hri_e70b.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils.h b/bsp/microchip/same70/bsp/hal/utils/include/utils.h new file mode 100644 index 0000000000..1cf2699690 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_assert.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_assert.h new file mode 100644 index 0000000000..c2328d6c31 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_event.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_event.h new file mode 100644 index 0000000000..13067c4fec --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_increment_macro.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000000..464c6cbb72 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_list.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_list.h new file mode 100644 index 0000000000..977e8ccad4 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_repeat_macro.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000000..89e6f52d5b --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/bsp/microchip/same70/bsp/hal/utils/include/utils_ringbuffer.h b/bsp/microchip/same70/bsp/hal/utils/include/utils_ringbuffer.h new file mode 100644 index 0000000000..401d557246 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/include/utils_ringbuffer.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief Ringbuffer declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _UTILS_RINGBUFFER_H_INCLUDED +#define _UTILS_RINGBUFFER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_ringbuffer + * + * @{ + */ + +#include "compiler.h" +#include "utils_assert.h" + +/** + * \brief Ring buffer element type + */ +struct ringbuffer { + uint8_t *buf; /** Buffer base address */ + uint32_t size; /** Buffer size */ + uint32_t read_index; /** Buffer read index */ + uint32_t write_index; /** Buffer write index */ +}; + +/** + * \brief Ring buffer init + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] buf Space to store the data + * \param[in] size The buffer length, must be aligned with power of 2 + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size); + +/** + * \brief Get one byte from ring buffer, the user needs to handle the concurrent + * access on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte space to store the read data + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data); + +/** + * \brief Put one byte to ring buffer, the user needs to handle the concurrent access + * on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte data to be put into ring buffer + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data); + +/** + * \brief Return the element number of ring buffer + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return The number of elements in ring buffer [0, rb->size] + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb); + +/** + * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer + * via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return ERR_NONE on success, or an error code on failure. + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_RINGBUFFER_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hal/utils/src/utils_assert.c b/bsp/microchip/same70/bsp/hal/utils/src/utils_assert.c new file mode 100644 index 0000000000..b376c9700f --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/bsp/microchip/same70/bsp/hal/utils/src/utils_event.c b/bsp/microchip/same70/bsp/hal/utils/src/utils_event.c new file mode 100644 index 0000000000..d1af9d0cf1 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/bsp/microchip/same70/bsp/hal/utils/src/utils_list.c b/bsp/microchip/same70/bsp/hal/utils/src/utils_list.c new file mode 100644 index 0000000000..4006a01933 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/bsp/microchip/same70/bsp/hal/utils/src/utils_ringbuffer.c b/bsp/microchip/same70/bsp/hal/utils/src/utils_ringbuffer.c new file mode 100644 index 0000000000..45cac83fc6 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/src/utils_ringbuffer.c @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Ringbuffer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "utils_ringbuffer.h" + +/** + * \brief Ringbuffer init + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) +{ + ASSERT(rb && buf && size); + + /* + * buf size must be aligned to power of 2 + */ + if ((size & (size - 1)) != 0) { + return ERR_INVALID_ARG; + } + + /* size - 1 is faster in calculation */ + rb->size = size - 1; + rb->read_index = 0; + rb->write_index = rb->read_index; + rb->buf = (uint8_t *)buf; + + return ERR_NONE; +} + +/** + * \brief Get one byte from ringbuffer + * + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) +{ + ASSERT(rb && data); + + if (rb->write_index != rb->read_index) { + *data = rb->buf[rb->read_index & rb->size]; + rb->read_index++; + return ERR_NONE; + } + + return ERR_NOT_FOUND; +} + +/** + * \brief Put one byte to ringbuffer + * + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) +{ + ASSERT(rb); + + rb->buf[rb->write_index & rb->size] = data; + + /* + * buffer full strategy: new data will overwrite the oldest data in + * the buffer + */ + if ((rb->write_index - rb->read_index) > rb->size) { + rb->read_index = rb->write_index - rb->size; + } + + rb->write_index++; + + return ERR_NONE; +} + +/** + * \brief Return the element number of ringbuffer + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb) +{ + ASSERT(rb); + + return rb->write_index - rb->read_index; +} + +/** + * \brief Flush ringbuffer + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb) +{ + ASSERT(rb); + + rb->read_index = rb->write_index; + + return ERR_NONE; +} diff --git a/bsp/microchip/same70/bsp/hal/utils/src/utils_syscalls.c b/bsp/microchip/same70/bsp/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000000..d8c6357e15 --- /dev/null +++ b/bsp/microchip/same70/bsp/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} +#if 0 +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} +#endif +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/bsp/microchip/same70/bsp/hpl/core/hpl_core_m7_base.c b/bsp/microchip/same70/bsp/hpl/core/hpl_core_m7_base.c new file mode 100644 index 0000000000..315c6f4efa --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/core/hpl_core_m7_base.c @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_HCLK_FREQUENCY +#define CONF_HCLK_FREQUENCY 300000000 +#endif + +#if CONF_HCLK_FREQUENCY < 1000 +#define HCLK_FREQ_POWER 3 +#elif CONF_HCLK_FREQUENCY < 10000 +#define HCLK_FREQ_POWER 4 +#elif CONF_HCLK_FREQUENCY < 100000 +#define HCLK_FREQ_POWER 5 +#elif CONF_HCLK_FREQUENCY < 1000000 +#define HCLK_FREQ_POWER 6 +#elif CONF_HCLK_FREQUENCY < 10000000 +#define HCLK_FREQ_POWER 7 +#elif CONF_HCLK_FREQUENCY < 100000000 +#define HCLK_FREQ_POWER 8 +#elif CONF_HCLK_FREQUENCY < 1000000000 +#define HCLK_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_SR_RSTTYP_bf(RSTC); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) - 1) + 1; + case 8: + return (us * (freq / 100000) - 1) / 10 + 1; + case 7: + return (us * (freq / 10000) - 1) / 100 + 1; + case 6: + return (us * (freq / 1000) - 1) / 1000 + 1; + case 5: + return (us * (freq / 100) - 1) / 10000 + 1; + default: + return (us * freq - 1) / 1000000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_HCLK_FREQUENCY, HCLK_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000)) * 1000; + case 8: + return (ms * (freq / 100000)) * 100; + case 7: + return (ms * (freq / 10000)) * 10; + case 6: + return (ms * (freq / 1000)); + case 5: + return (ms * (freq / 100) - 1) / 10 + 1; + default: + return (ms * freq - 1) / 1000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_HCLK_FREQUENCY, HCLK_FREQ_POWER); +} diff --git a/bsp/microchip/same70/bsp/hpl/core/hpl_core_port.h b/bsp/microchip/same70/bsp/hpl/core/hpl_core_port.h new file mode 100644 index 0000000000..97cdb7770a --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/core/hpl_core_port.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Enable FPU + */ +static inline void _fpu_enable(void) +{ + CRITICAL_SECTION_ENTER() + /** Set bits 20-23 to enable CP10 and CP11 coprocessors */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); + CRITICAL_SECTION_LEAVE() +} + +/** + * \brief Disable FPU + */ +static inline void _fpu_disable(void) +{ + CRITICAL_SECTION_ENTER() + /** Clear bits 20-23 to enable CP10 and CP11 coprocessors */ + SCB->CPACR &= ~(0xFu << 20); + __DSB(); + __ISB(); + CRITICAL_SECTION_LEAVE() +} + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hpl/core/hpl_init.c b/bsp/microchip/same70/bsp/hpl/core/hpl_init.c new file mode 100644 index 0000000000..c24f4bcc10 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/core/hpl_init.c @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + _fpu_enable(); + hri_efc_write_EEFC_FMR_FWS_bf(EFC, CONF_EFC_WAIT_STATE); + +#if CONF_DMA_ENABLE + _pmc_enable_periph_clock(ID_XDMAC); + _dma_init(); + +#endif + _pmc_init(); +} diff --git a/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.c b/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.c new file mode 100644 index 0000000000..b02969b765 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.c @@ -0,0 +1,433 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +#ifdef CONF_CAN0_ENABLED +COMPILER_ALIGNED(4) +uint8_t can0_rx_fifo[CONF_CAN0_F0DS * CONF_CAN0_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can0_tx_fifo[CONF_CAN0_TBDS * CONF_CAN0_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can0_tx_event_fifo[CONF_CAN0_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can0_rx_std_filter[CONF_CAN0_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can0_rx_ext_filter[CONF_CAN0_XIDFC_LSS]; + +struct _can_context _can0_context = {.rx_fifo = can0_rx_fifo, + .tx_fifo = can0_tx_fifo, + .tx_event = can0_tx_event_fifo, + .rx_std_filter = can0_rx_std_filter, + .rx_ext_filter = can0_rx_ext_filter}; + +/** Pointer to hpl device */ +static struct _can_async_device *_can0_dev = NULL; +#endif /* CONF_CAN0_ENABLED */ + +#ifdef CONF_CAN1_ENABLED +COMPILER_ALIGNED(4) +uint8_t can1_rx_fifo[CONF_CAN1_F0DS * CONF_CAN1_RXF0C_F0S]; +COMPILER_ALIGNED(4) +uint8_t can1_tx_fifo[CONF_CAN1_TBDS * CONF_CAN1_TXBC_TFQS]; +COMPILER_ALIGNED(4) +static struct _can_tx_event_entry can1_tx_event_fifo[CONF_CAN1_TXEFC_EFS]; +COMPILER_ALIGNED(4) +static struct _can_standard_message_filter_element can1_rx_std_filter[CONF_CAN1_SIDFC_LSS]; +COMPILER_ALIGNED(4) +static struct _can_extended_message_filter_element can1_rx_ext_filter[CONF_CAN1_XIDFC_LSS]; + +struct _can_context _can1_context = {.rx_fifo = can1_rx_fifo, + .tx_fifo = can1_tx_fifo, + .tx_event = can1_tx_event_fifo, + .rx_std_filter = can1_rx_std_filter, + .rx_ext_filter = can1_rx_ext_filter}; + +/** Pointer to hpl device */ +static struct _can_async_device *_can1_dev = NULL; +#endif /* CONF_CAN1_ENABLED */ + +/** + * \brief Initialize CAN. + */ +int32_t _can_async_init(struct _can_async_device *const dev, void *const hw) +{ + dev->hw = hw; + hri_mcan_set_CCCR_INIT_bit(dev->hw); + while (hri_mcan_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_mcan_set_CCCR_CCE_bit(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (hw == MCAN0) { + dev->context = (void *)&_can0_context; + hri_mcan_set_CCCR_reg(dev->hw, CONF_CAN0_CCCR_REG); + hri_mcan_write_NBTP_reg(dev->hw, CONF_CAN0_NBTP_REG); + hri_mcan_write_DBTP_reg(dev->hw, CONF_CAN0_DBTP_REG); + hri_mcan_write_TDCR_reg(dev->hw, CONF_CAN0_TDCR_REG); + hri_mcan_write_RXF0C_reg(dev->hw, CONF_CAN0_RXF0C_REG | (((uint32_t)can0_rx_fifo) & 0xFFFF)); + hri_mcan_write_RXESC_reg(dev->hw, CONF_CAN0_RXESC_REG); + hri_mcan_write_TXESC_reg(dev->hw, CONF_CAN0_TXESC_REG); + hri_mcan_write_TXBC_reg(dev->hw, CONF_CAN0_TXBC_REG | (((uint32_t)can0_tx_fifo) & 0xFFFF)); + hri_mcan_write_TXEFC_reg(dev->hw, CONF_CAN0_TXEFC_REG | (((uint32_t)can0_tx_event_fifo) & 0xFFFF)); + hri_mcan_write_GFC_reg(dev->hw, CONF_CAN0_GFC_REG); + hri_mcan_write_SIDFC_reg(dev->hw, CONF_CAN0_SIDFC_REG | (((uint32_t)can0_rx_std_filter) & 0xFFFF)); + hri_mcan_write_XIDFC_reg(dev->hw, CONF_CAN0_XIDFC_REG | (((uint32_t)can0_rx_ext_filter) & 0xFFFF)); + hri_mcan_write_XIDAM_reg(dev->hw, CONF_CAN0_XIDAM_REG); + + _can0_dev = dev; + NVIC_DisableIRQ(MCAN0_INT0_IRQn); + NVIC_ClearPendingIRQ(MCAN0_INT0_IRQn); + NVIC_EnableIRQ(MCAN0_INT0_IRQn); + hri_mcan_write_ILE_reg(dev->hw, MCAN_ILE_EINT0); + } +#endif + +#ifdef CONF_CAN1_ENABLED + if (hw == MCAN1) { + dev->context = (void *)&_can1_context; + hri_mcan_set_CCCR_reg(dev->hw, CONF_CAN1_CCCR_REG); + hri_mcan_write_NBTP_reg(dev->hw, CONF_CAN1_NBTP_REG); + hri_mcan_write_DBTP_reg(dev->hw, CONF_CAN1_DBTP_REG); + hri_mcan_write_TDCR_reg(dev->hw, CONF_CAN1_TDCR_REG); + hri_mcan_write_RXF0C_reg(dev->hw, CONF_CAN1_RXF0C_REG | (((uint32_t)can1_rx_fifo) & 0xFFFF)); + hri_mcan_write_RXESC_reg(dev->hw, CONF_CAN1_RXESC_REG); + hri_mcan_write_TXESC_reg(dev->hw, CONF_CAN1_TXESC_REG); + hri_mcan_write_TXBC_reg(dev->hw, CONF_CAN1_TXBC_REG | (((uint32_t)can1_tx_fifo) & 0xFFFF)); + hri_mcan_write_TXEFC_reg(dev->hw, CONF_CAN1_TXEFC_REG | (((uint32_t)can1_tx_event_fifo) & 0xFFFF)); + hri_mcan_write_GFC_reg(dev->hw, CONF_CAN1_GFC_REG); + hri_mcan_write_SIDFC_reg(dev->hw, CONF_CAN1_SIDFC_REG | (((uint32_t)can1_rx_std_filter) & 0xFFFF)); + hri_mcan_write_XIDFC_reg(dev->hw, CONF_CAN1_XIDFC_REG | (((uint32_t)can1_rx_ext_filter) & 0xFFFF)); + hri_mcan_write_XIDAM_reg(dev->hw, CONF_CAN1_XIDAM_REG); + + _can1_dev = dev; + NVIC_DisableIRQ(MCAN1_INT0_IRQn); + NVIC_ClearPendingIRQ(MCAN1_INT0_IRQn); + NVIC_EnableIRQ(MCAN1_INT0_IRQn); + hri_mcan_write_ILE_reg(dev->hw, MCAN_ILE_EINT0); + } +#endif + + /* Disable CCE to prevent Configuration Change */ + hri_mcan_clear_CCCR_CCE_bit(dev->hw); + hri_mcan_clear_CCCR_INIT_bit(dev->hw); + while (hri_mcan_get_CCCR_INIT_bit(dev->hw)) { + }; + + return ERR_NONE; +} + +/** + * \brief De-initialize CAN. + */ +int32_t _can_async_deinit(struct _can_async_device *const dev) +{ + hri_mcan_set_CCCR_INIT_bit(dev->hw); + dev->hw = NULL; + return ERR_NONE; +} + +/** + * \brief Enable CAN + */ +int32_t _can_async_enable(struct _can_async_device *const dev) +{ + hri_mcan_clear_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Disable CAN + */ +int32_t _can_async_disable(struct _can_async_device *const dev) +{ + hri_mcan_set_CCCR_INIT_bit(dev->hw); + return ERR_NONE; +} + +/** + * \brief Read a CAN message + */ +int32_t _can_async_read(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_rx_fifo_entry *f = NULL; + hri_mcan_rxf0s_reg_t get_index; + + if (!hri_mcan_read_RXF0S_F0FL_bf(dev->hw)) { + return ERR_NOT_FOUND; + } + + get_index = hri_mcan_read_RXF0S_F0GI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == MCAN0) { + f = (struct _can_rx_fifo_entry *)(can0_rx_fifo + get_index * CONF_CAN0_F0DS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == MCAN1) { + f = (struct _can_rx_fifo_entry *)(can1_rx_fifo + get_index * CONF_CAN1_F0DS); + } +#endif + + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (f->R0.bit.XTD == 1) { + msg->fmt = CAN_FMT_EXTID; + msg->id = f->R0.bit.ID; + } else { + msg->fmt = CAN_FMT_STDID; + /* A standard identifier is stored into ID[28:18] */ + msg->id = f->R0.bit.ID >> 18; + } + + if (f->R0.bit.RTR == 1) { + msg->type = CAN_TYPE_REMOTE; + } + + const uint8_t dlc2len[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + msg->len = dlc2len[f->R1.bit.DLC]; + + memcpy(msg->data, f->data, msg->len); + + hri_mcan_write_RXF0A_F0AI_bf(dev->hw, get_index); + + return ERR_NONE; +} + +/** + * \brief Write a CAN message + */ +int32_t _can_async_write(struct _can_async_device *const dev, struct can_message *msg) +{ + struct _can_tx_fifo_entry *f = NULL; + hri_mcan_txfqs_reg_t put_index; + + if (hri_mcan_get_TXFQS_TFQF_bit(dev->hw)) { + return ERR_NO_RESOURCE; + } + + put_index = hri_mcan_read_TXFQS_TFQPI_bf(dev->hw); + +#ifdef CONF_CAN0_ENABLED + if (dev->hw == MCAN0) { + f = (struct _can_tx_fifo_entry *)(can0_tx_fifo + put_index * CONF_CAN0_TBDS); + } +#endif +#ifdef CONF_CAN1_ENABLED + if (dev->hw == MCAN1) { + f = (struct _can_tx_fifo_entry *)(can1_tx_fifo + put_index * CONF_CAN1_TBDS); + } +#endif + if (f == NULL) { + return ERR_NO_RESOURCE; + } + + if (msg->fmt == CAN_FMT_EXTID) { + f->T0.val = msg->id; + f->T0.bit.XTD = 1; + } else { + /* A standard identifier is stored into ID[28:18] */ + f->T0.val = msg->id << 18; + } + + if (msg->len <= 8) { + f->T1.bit.DLC = msg->len; + } else if (msg->len <= 12) { + f->T1.bit.DLC = 0x9; + } else if (msg->len <= 16) { + f->T1.bit.DLC = 0xA; + } else if (msg->len <= 20) { + f->T1.bit.DLC = 0xB; + } else if (msg->len <= 24) { + f->T1.bit.DLC = 0xC; + } else if (msg->len <= 32) { + f->T1.bit.DLC = 0xD; + } else if (msg->len <= 48) { + f->T1.bit.DLC = 0xE; + } else if (msg->len <= 64) { + f->T1.bit.DLC = 0xF; + } + + f->T1.bit.FDF = hri_mcan_get_CCCR_FDOE_bit(dev->hw); + f->T1.bit.BRS = hri_mcan_get_CCCR_BRSE_bit(dev->hw); + + memcpy(f->data, msg->data, msg->len); + + hri_mcan_write_TXBAR_reg(dev->hw, 1 << hri_mcan_read_TXFQS_TFQPI_bf(dev->hw)); + return ERR_NONE; +} + +/** + * \brief Set CAN Interrupt State + */ +void _can_async_set_irq_state(struct _can_async_device *const dev, enum can_async_callback_type type, bool state) +{ + uint32_t ie; + + if (type == CAN_ASYNC_RX_CB) { + hri_mcan_write_IE_RF0NE_bit(dev->hw, state); + } else if (type == CAN_ASYNC_TX_CB) { + hri_mcan_write_IE_TCE_bit(dev->hw, state); + hri_mcan_write_TXBTIE_reg(dev->hw, MCAN_TXBTIE_MASK); + } else if (type == CAN_ASYNC_IRQ_CB) { + ie = hri_mcan_get_IE_reg(dev->hw, MCAN_IE_RF0NE | MCAN_IE_TCE); + hri_mcan_write_IE_reg(dev->hw, ie | CONF_CAN0_IE_REG); + } + + return; +} + +/** + * \brief Return number of read errors + */ +uint8_t _can_async_get_rxerr(struct _can_async_device *const dev) +{ + return hri_mcan_read_ECR_REC_bf(dev->hw); +} + +/** + * \brief Return number of write errors + */ +uint8_t _can_async_get_txerr(struct _can_async_device *const dev) +{ + return hri_mcan_read_ECR_TEC_bf(dev->hw); +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_mode(struct _can_async_device *const dev, enum can_mode mode) +{ + hri_mcan_set_CCCR_INIT_bit(dev->hw); + while (hri_mcan_get_CCCR_INIT_bit(dev->hw) == 0) + ; + hri_mcan_set_CCCR_CCE_bit(dev->hw); + + if (mode == CAN_MODE_MONITORING) { + hri_mcan_set_CCCR_MON_bit(dev->hw); + } else { + hri_mcan_clear_CCCR_MON_bit(dev->hw); + } + + /* Disable CCE to prevent Configuration Change */ + hri_mcan_clear_CCCR_CCE_bit(dev->hw); + hri_mcan_clear_CCCR_INIT_bit(dev->hw); + while (hri_mcan_get_CCCR_INIT_bit(dev->hw)) + ; + + return ERR_NONE; +} + +/** + * \brief Set CAN to the specified mode + */ +int32_t _can_async_set_filter(struct _can_async_device *const dev, uint8_t index, enum can_format fmt, + struct can_filter *filter) +{ + struct _can_standard_message_filter_element *sf; + struct _can_extended_message_filter_element *ef; + + sf = &((struct _can_context *)dev->context)->rx_std_filter[index]; + ef = &((struct _can_context *)dev->context)->rx_ext_filter[index]; + + if (fmt == CAN_FMT_STDID) { + if (filter == NULL) { + sf->S0.val = 0; + return ERR_NONE; + } + sf->S0.val = filter->mask; + sf->S0.bit.SFID1 = filter->id; + sf->S0.bit.SFT = _CAN_SFT_CLASSIC; + sf->S0.bit.SFEC = _CAN_SFEC_STF0M; + } else if (fmt == CAN_FMT_EXTID) { + if (filter == NULL) { + ef->F0.val = 0; + return ERR_NONE; + } + ef->F0.val = filter->id; + ef->F0.bit.EFEC = _CAN_EFEC_STF0M; + ef->F1.val = filter->mask; + ef->F1.bit.EFT = _CAN_EFT_CLASSIC; + } + + return ERR_NONE; +} + +/* + * \brief CAN interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _can_irq_handler(struct _can_async_device *dev) +{ + uint32_t ir; + ir = hri_mcan_read_IR_reg(dev->hw); + + if (ir & MCAN_IR_RF0N) { + dev->cb.rx_done(dev); + } + + if (ir & MCAN_IR_TC) { + dev->cb.tx_done(dev); + } + + if (ir & MCAN_IR_BO) { + dev->cb.irq_handler(dev, CAN_IRQ_BO); + } + + if (ir & MCAN_IR_EW) { + dev->cb.irq_handler(dev, CAN_IRQ_EW); + } + + if (ir & MCAN_IR_EP) { + dev->cb.irq_handler(dev, hri_mcan_get_PSR_EP_bit(dev->hw) ? CAN_IRQ_EP : CAN_IRQ_EA); + } + + if (ir & MCAN_IR_RF0L) { + dev->cb.irq_handler(dev, CAN_IRQ_DO); + } + + hri_mcan_write_IR_reg(dev->hw, ir); +} + +/** + * \internal CAN interrupt handler + */ +void MCAN1_INT0_Handler(void) +{ + _can_irq_handler(_can1_dev); +} diff --git a/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.h b/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.h new file mode 100644 index 0000000000..062cbd77e6 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/mcan/hpl_mcan.h @@ -0,0 +1,204 @@ +/** + * \file + * + * \brief Control Area Network(CAN) functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef HPL_CAN_CANOPUS_H_INCLUDED +#define HPL_CAN_CANOPUS_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief CAN receive FIFO element. + */ +struct _can_rx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R0; + __IO union { + struct { + uint32_t RXTS : 16; /*!< Rx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t EDL : 1; /*!< FD Format */ + uint32_t : 2; /*!< Reserved */ + uint32_t FIDX : 7; /*!< Filter Index */ + uint32_t ANMF : 1; /*!< Accepted Non-matching Frame */ + } bit; + uint32_t val; /*!< Type used for register access */ + } R1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit FIFO element. + */ +struct _can_tx_fifo_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t : 1; /*!< Reserved */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T0; + __IO union { + struct { + uint32_t : 16; /*!< Reserved */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit rate Switching */ + uint32_t FDF : 1; /*!< FD Format */ + uint32_t : 1; /*!< Reserved */ + uint32_t EFCC : 1; /*!< Event FIFO Control, Don't use EFC to avoid conflict */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } T1; + uint8_t data[]; +}; + +/** + * \brief CAN transmit Event element. + */ +struct _can_tx_event_entry { + __IO union { + struct { + uint32_t ID : 29; /*!< Identifier */ + uint32_t RTR : 1; /*!< Remote Transmission Request */ + uint32_t XTD : 1; /*!< Extended Identifier */ + uint32_t ESI : 1; /*!< Error State Indicator */ + } bit; + uint32_t val; /*!< Type used for register access */ + } E0; + __IO union { + struct { + uint32_t TXTS : 16; /*!< Tx Timestamp */ + uint32_t DLC : 4; /*!< Data Length Code */ + uint32_t BRS : 1; /*!< Bit Rate Switch */ + uint32_t EDL : 1; /*!< FD Format */ + uint32_t ET : 2; /*!< Event Type */ + uint32_t MM : 8; /*!< Message Marker */ + } bit; + uint32_t val; /*!< Type used for register access */ + } E1; +}; + +/** + * \brief CAN standard message ID filter element structure. + * + * Common element structure for standard message ID filter element. + */ +struct _can_standard_message_filter_element { + __IO union { + struct { + uint32_t SFID2 : 11; /*!< Standard Filter ID 2 */ + uint32_t : 5; /*!< Reserved */ + uint32_t SFID1 : 11; /*!< Standard Filter ID 1 */ + uint32_t SFEC : 3; /*!< Standard Filter Configuration */ + uint32_t SFT : 2; /*!< Standard Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } S0; +}; + +#define _CAN_SFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_SFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_SFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_SFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_SFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_SFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_SFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_SFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_SFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_SFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_SFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ + +#define _CAN_EFT_RANGE 0 /*!< Range filter from SFID1 to SFID2 */ +#define _CAN_EFT_DUAL 1 /*!< Dual ID filter for SFID1 or SFID2 */ +#define _CAN_EFT_CLASSIC 2 /*!< Classic filter: SFID1 = filter, SFID2 = mask */ +#define _CAN_EFEC_DISABLE 0 /*!< Disable filter element */ +#define _CAN_EFEC_STF0M 1 /*!< Store in Rx FIFO 0 if filter matches */ +#define _CAN_EFEC_STF1M 2 /*!< Store in Rx FIFO 1 if filter matches */ +#define _CAN_EFEC_REJECT 3 /*!< Reject ID if filter matches */ +#define _CAN_EFEC_PRIORITY 4 /*!< Set priority if filter matches. */ +#define _CAN_EFEC_PRIF0M 5 /*!< Set priority and store in FIFO 0 if filter matches */ +#define _CAN_EFEC_PRIF1M 6 /*!< Set priority and store in FIFO 1 if filter matches. */ +#define _CAN_EFEC_STRXBUF 7 /*!< Store into Rx Buffer or as debug message, configuration of SFT[1:0] ignored. */ +/** + * \brief CAN extended message ID filter element structure. + * + * Common element structure for extended message ID filter element. + */ +struct _can_extended_message_filter_element { + __IO union { + struct { + uint32_t EFID1 : 29; /*!< bit: Extended Filter ID 1 */ + uint32_t EFEC : 3; /*!< bit: Extended Filter Configuration */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F0; + __IO union { + struct { + uint32_t EFID2 : 29; /*!< bit: Extended Filter ID 2 */ + uint32_t : 1; /*!< bit: Reserved */ + uint32_t EFT : 2; /*!< bit: Extended Filter Type */ + } bit; + uint32_t val; /*!< Type used for register access */ + } F1; +}; + +struct _can_context { + uint8_t * rx_fifo; /*!< receive message fifo */ + uint8_t * tx_fifo; /*!< transfer message fifo */ + struct _can_tx_event_entry *tx_event; /*!< transfer event fifo */ + /* Standard filter List */ + struct _can_standard_message_filter_element *rx_std_filter; + /* Extended filter List */ + struct _can_extended_message_filter_element *rx_ext_filter; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_CAN_CANOPUS_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hpl/pio/hpl_gpio_base.h b/bsp/microchip/same70/bsp/hpl/pio/hpl_gpio_base.h new file mode 100644 index 0000000000..f13417bdfe --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/pio/hpl_gpio_base.h @@ -0,0 +1,168 @@ + +/** + * \file + * + * \brief SAM PIO. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Transfer gpio_port to hardware address + */ +static inline void *port_to_reg(const enum gpio_port port) +{ + /* PIO instance offset is 0x200 */ + return (void *)((uint32_t)PIOA + port * 0x200); +} + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + void *const hw = port_to_reg(port); + switch (direction) { + case GPIO_DIRECTION_OFF: + case GPIO_DIRECTION_IN: + hri_pio_clear_OSR_reg(hw, mask); + break; + + case GPIO_DIRECTION_OUT: + hri_pio_set_OSR_reg(hw, mask); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + void *const hw = port_to_reg(port); + if (level) { + hri_pio_set_ODSR_reg(hw, mask); + } else { + hri_pio_clear_ODSR_reg(hw, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + uint32_t bits_clear, bits_set; + void *const hw = port_to_reg(port); + + bits_clear = hri_pio_get_ODSR_reg(hw, mask); + bits_set = (~bits_clear) & mask; + hri_pio_set_ODSR_reg(hw, bits_set); + hri_pio_clear_ODSR_reg(hw, bits_clear); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + void *const hw = port_to_reg(port); + tmp = hri_pio_read_PDSR_reg(hw); + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + void *const hw = port_to_reg(port); + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_pio_clear_PUSR_reg(hw, 1U << pin); + hri_pio_clear_PPDSR_reg(hw, 1U << pin); + break; + + case GPIO_PULL_UP: + hri_pio_clear_PPDSR_reg(hw, 1U << pin); + hri_pio_set_PUSR_reg(hw, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_pio_clear_PUSR_reg(hw, 1U << pin); + hri_pio_set_PPDSR_reg(hw, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + void *const hw = port_to_reg((enum gpio_port)port); + + if ((enum gpio_port)port == GPIO_PORTB) { + if ((pin == 4) || (pin == 5) || (pin == 6) || (pin == 7) || (pin == 12)) { + hri_matrix_set_CCFG_SYSIO_reg(MATRIX, (0x1 << pin)); + } + } + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_pio_set_PSR_reg(hw, 1U << pin); + } else { + if (function & 0x1) { + hri_pio_set_ABCDSR_reg(hw, 0, 1U << pin); + } else { + hri_pio_clear_ABCDSR_reg(hw, 0, 1U << pin); + } + + if (function & 0x2) { + hri_pio_set_ABCDSR_reg(hw, 1, 1U << pin); + } else { + hri_pio_clear_ABCDSR_reg(hw, 1, 1U << pin); + } + + hri_pio_clear_PSR_reg(hw, 1U << pin); + } +} diff --git a/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.c b/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.c new file mode 100644 index 0000000000..21c9333f7a --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.c @@ -0,0 +1,262 @@ +/** + * \file + * + * \brief Power Management Controller register related functionality. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +/** + * \brief Initializes clock generators + * + * All clock sources are running when this function returns. + */ +static void _pmc_init_sources(void) +{ + uint32_t data = 0; + +#if CONF_CLK_SLCK_ENABLE == 1 +#if (CONF_XOSC32K_ENABLE && (CONF_CLK_GEN_SLCK_SRC == CLK_SRC_OPTION_XOSC32K)) +#if (CONF_XOSC32K == CONF_XOSC32K_BYPASS) + hri_supc_set_MR_reg(SUPC, (SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS)); +#endif + hri_supc_write_CR_reg(SUPC, (SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL)); + while (!(hri_supc_get_SR_OSCSEL_bit(SUPC) && hri_pmc_get_SR_OSCSELS_bit(PMC))) { + /* Wait until the oscillator is ready */ + } +#endif +#endif + +#if (CONF_CLK_MAINCK_ENABLE == 1) +#if (CONF_OSC12M_ENABLE && (CONF_CLK_GEN_MAINCK_SRC == CLK_SRC_OPTION_OSC12M)) + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + hri_pmc_set_CKGR_MOR_reg(PMC, (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN)); + while (!hri_pmc_get_SR_MOSCRCS_bit(PMC)) { + /* Wait until the Fast RC to stabilize */ + } + /* Change Fast RC oscillator frequency */ + data = hri_pmc_read_CKGR_MOR_reg(PMC) & ~CKGR_MOR_MOSCRCF_Msk; + data |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCF(CONF_OSC12M_SELECTOR); + hri_pmc_write_CKGR_MOR_reg(PMC, data); + while (!hri_pmc_get_SR_MOSCRCS_bit(PMC)) { + /* Wait until the Fast RC to stabilize */ + } + /* Switch to Fast RC */ + data = hri_pmc_read_CKGR_MOR_reg(PMC) & ~CKGR_MOR_MOSCSEL; + data |= CKGR_MOR_KEY_PASSWD; + hri_pmc_write_CKGR_MOR_reg(PMC, data); +#endif + +#if (CONF_XOSC20M_ENABLE && (CONF_CLK_GEN_MAINCK_SRC == CLK_SRC_OPTION_XOSC20M)) +#if (CONF_XOSC20M == CONF_XOSC20M_BYPASS) + /* Enable Main XTAL oscillator */ + data = hri_pmc_read_CKGR_MOR_reg(PMC) & ~CKGR_MOR_MOSCXTEN; + data |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCSEL; + hri_pmc_write_CKGR_MOR_reg(PMC, data); +#else + data = hri_pmc_read_CKGR_MOR_reg(PMC) & ~CKGR_MOR_MOSCXTBY; + data |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(CONF_XOSC20M_STARTUP_TIME); + hri_pmc_write_CKGR_MOR_reg(PMC, data); + while (!hri_pmc_get_SR_MOSCXTS_bit(PMC)) { + /* Wait until the XTAL to stabilize */ + } + hri_pmc_set_CKGR_MOR_reg(PMC, CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL); +#endif +#endif +#endif + +#if (CONF_PLLACK_ENABLE == 1) + data = CKGR_PLLAR_MULA(CONF_PLLACK_MUL - 1) | CKGR_PLLAR_DIVA(CONF_PLLACK_DIV) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); + /* Stop PLL first */ + hri_pmc_write_CKGR_PLLAR_MULA_bf(PMC, 0); + hri_pmc_write_CKGR_PLLAR_reg(PMC, (CKGR_PLLAR_ONE | data)); + while (!hri_pmc_get_SR_LOCKA_bit(PMC)) { + /* Wait until PLLACK stabilize */ + } +#endif + +#if (CONF_UPLLCK_ENABLE == 1) + data = CKGR_UCKR_UPLLCOUNT(PLL_COUNT); + hri_pmc_write_CKGR_UCKR_reg(PMC, (CKGR_UCKR_UPLLEN | data)); + while (!hri_pmc_get_SR_LOCKU_bit(PMC)) { + /* Wait until USB UTMI stabilize */ + } +#endif + +#if ((CONF_CLK_GEN_MCKR_SRC == CLK_SRC_OPTION_MAINCK) && (CONF_CLK_GEN_MAINCK_SRC == CLK_SRC_OPTION_OSC12M)) +#if (CONF_CLK_CFDEN_ENABLE == 1) + /* Enable main clock failure detection */ + hri_pmc_set_CKGR_MOR_CFDEN_bit(PMC); +#endif +#endif +} + +/** + * \brief Initializes master clock generators + * + * Master clock are running when this function returns. + */ +static void _pmc_init_master_clock(void) +{ +#if (CONF_CLK_MCKR_ENABLE == 1) +#if (CONF_UPLLCK_ENABLE == 1) + hri_pmc_write_MCKR_UPLLDIV2_bit(PMC, CONF_UPLLCKDIV_DIV); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } +#endif + +#if ((CONF_CLK_GEN_MCKR_SRC == CLK_SRC_OPTION_SLCK) || (CONF_CLK_GEN_MCKR_SRC == CLK_SRC_OPTION_MAINCK)) + hri_pmc_write_MCKR_CSS_bf(PMC, CONF_CLK_GEN_MCKR_SRC); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } + hri_pmc_write_MCKR_PRES_bf(PMC, CONF_MCKR_PRESC); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } + hri_pmc_write_MCKR_MDIV_bf(PMC, CONF_MCK_DIV); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } +#elif ((CONF_CLK_GEN_MCKR_SRC == CLK_SRC_OPTION_PLLACK) || (CONF_CLK_GEN_MCKR_SRC == CLK_SRC_OPTION_UPLLCKDIV)) + hri_pmc_write_MCKR_PRES_bf(PMC, CONF_MCKR_PRESC); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } + hri_pmc_write_MCKR_MDIV_bf(PMC, CONF_MCK_DIV); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } + hri_pmc_write_MCKR_CSS_bf(PMC, CONF_CLK_GEN_MCKR_SRC); + while (!hri_pmc_get_SR_MCKRDY_bit(PMC)) { + /* Wait until master clock is ready */ + } +#endif +#endif +} + +/** + * \brief Initializes programmable clock generators + * + * Programmable clock are running when this function returns. + */ +static void _pmc_init_program_clock(void) +{ +#if (CONF_CLK_PCK0_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 0, PMC_PCK_CSS(CONF_CLK_GEN_PCK0_SRC) | PMC_PCK_PRES(CONF_PCK0_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY0_bit(PMC)) { + /* Wait until PCK0 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK0); +#endif + +#if (CONF_CLK_PCK1_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 1, PMC_PCK_CSS(CONF_CLK_GEN_PCK1_SRC) | PMC_PCK_PRES(CONF_PCK1_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY1_bit(PMC)) { + /* Wait until PCK1 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK1); +#endif + +#if (CONF_CLK_PCK2_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 2, PMC_PCK_CSS(CONF_CLK_GEN_PCK2_SRC) | PMC_PCK_PRES(CONF_PCK2_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY2_bit(PMC)) { + /* Wait until PCK2 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK2); +#endif + +#if (CONF_CLK_PCK3_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 3, PMC_PCK_CSS(CONF_CLK_GEN_PCK3_SRC) | PMC_PCK_PRES(CONF_PCK3_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY3_bit(PMC)) { + /* Wait until PCK3 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK3); +#endif + +#if (CONF_CLK_PCK4_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 4, PMC_PCK_CSS(CONF_CLK_GEN_PCK4_SRC) | PMC_PCK_PRES(CONF_PCK4_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY4_bit(PMC)) { + /* Wait until PCK4 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK4); +#endif + +#if (CONF_CLK_PCK5_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 5, PMC_PCK_CSS(CONF_CLK_GEN_PCK5_SRC) | PMC_PCK_PRES(CONF_PCK5_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY5_bit(PMC)) { + /* Wait until PCK5 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK5); +#endif + +#if (CONF_CLK_PCK6_ENABLE == 1) + hri_pmc_write_PCK_reg(PMC, 6, PMC_PCK_CSS(CONF_CLK_GEN_PCK6_SRC) | PMC_PCK_PRES(CONF_PCK6_PRESC - 1)); + while (!hri_pmc_get_SR_PCKRDY6_bit(PMC)) { + /* Wait until PCK6 clock is ready */ + } + hri_pmc_write_SCER_reg(PMC, PMC_SCER_PCK6); +#endif +} + +/** + * \brief Initializes USB FS clock generators + * + * USB FS clock are running when this function returns. + */ +static void _pmc_init_fs_clock(void) +{ +#if (CONF_CLK_USB_48M_ENABLE == 1) + uint32_t data = 0; + + if (CONF_CLK_GEN_USB_48M_SRC == CLK_SRC_OPTION_UPLLCKDIV) { + data = PMC_USB_USBS; + } + data |= PMC_USB_USBDIV(CONF_USB_48M_DIV - 1); + hri_pmc_write_USB_reg(PMC, data); + hri_pmc_write_SCER_reg(PMC, PMC_SCER_USBCLK); +#endif +} + +/** + * \brief Initializes cortex M7 core clock + * + */ +void _pmc_init(void) +{ + _pmc_init_sources(); + _pmc_init_master_clock(); + _pmc_init_program_clock(); + _pmc_init_fs_clock(); +} diff --git a/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.h b/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.h new file mode 100644 index 0000000000..d9763504a8 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/pmc/hpl_pmc.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Power Management Controller register vG related functionality. + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_PMC_E70_H_INCLUDED +#define _HPL_PMC_E70_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#define PLL_COUNT 0x3fU + +#ifndef PMC_PCR_GCLKEN +#define PMC_PCR_GCLKEN (0x1u << 29) +#endif + +#ifndef PMC_PCR_GCLKDIV +#define PMC_PCR_GCLKDIV_Pos 20 +#define PMC_PCR_GCLKDIV_Msk (0xffu << PMC_PCR_GCLKDIV_Pos) +#define PMC_PCR_GCLKDIV(value) ((PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos))) +#endif + +#ifndef PMC_PCR_GCLKCSS +#define PMC_PCR_GCLKCSS_Pos 8 +#define PMC_PCR_GCLKCSS_Msk (0x07u << PMC_PCR_GCLKCSS_Pos) +#define PMC_PCR_GCLKCSS(value) ((PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos))) +#endif + +/** + * \brief Initializes cortex M7 core clock + * + */ +void _pmc_init(void); + +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must not be shifted (i.e., 1 << ID_xxx). + * + * \param periph_id Peripheral ID + * + */ +static inline void _pmc_enable_periph_clock(uint32_t periph_id) +{ + if (periph_id < 32) { + if (!hri_pmc_get_PCSR0_reg(PMC, (1 << periph_id))) { + hri_pmc_set_PCSR0_reg(PMC, (1 << periph_id)); + } + } else if (periph_id < 64) { + periph_id -= 32; + if (!hri_pmc_get_PCSR1_reg(PMC, (1 << periph_id))) { + hri_pmc_set_PCSR1_reg(PMC, (1 << periph_id)); + } + } else { + uint32_t tmp; + hri_pmc_write_PCR_reg(PMC, PMC_PCR_PID(periph_id)); + tmp = hri_pmc_read_PCR_reg(PMC); + tmp |= PMC_PCR_CMD | PMC_PCR_EN; + hri_pmc_write_PCR_reg(PMC, tmp); + } +} + +/** + * \brief Disable the specified peripheral clock. + * + * \note The ID must not be shifted (i.e., 1 << ID_xxx). + * + * \param periph_id Peripheral ID + * + */ +static inline void _pmc_disable_periph_clock(uint32_t periph_id) +{ + if (periph_id < 32) { + if (hri_pmc_get_PCSR0_reg(PMC, (1 << periph_id))) { + hri_pmc_clear_PCSR0_reg(PMC, (1 << periph_id)); + } + } else if (periph_id < 64) { + periph_id -= 32; + if (hri_pmc_get_PCSR1_reg(PMC, (1 << periph_id))) { + hri_pmc_clear_PCSR1_reg(PMC, (1 << periph_id)); + } + } else { + uint32_t tmp; + hri_pmc_write_PCR_reg(PMC, PMC_PCR_PID(periph_id)); + tmp = hri_pmc_read_PCR_reg(PMC); + tmp |= PMC_PCR_CMD; + tmp &= ~PMC_PCR_EN; + hri_pmc_write_PCR_reg(PMC, tmp); + } +} + +/** + * \brief Enable the gclk clock of I2SC. + * + * \note The ID must not be shifted (i.e., 1 << ID_xxx). + * + * \param periph_id Peripheral ID + * \param gclk_css Generic Clock Source Selection + * \param gclk_div Generic Clock Division Ratio. Generic clock is the selected + * clock period divided by GCLKDIV + 1. + * + */ +static inline void _pmc_enable_gclk_clock(uint32_t periph_id, uint8_t gclk_css, uint8_t gclk_div) +{ + hri_pmc_write_PCR_reg(PMC, PMC_PCR_PID(periph_id)); + if (!(hri_pmc_read_PCR_reg(PMC) & PMC_PCR_EN)) { + hri_pmc_write_PCR_reg(PMC, + (PMC_PCR_GCLKEN | PMC_PCR_EN | PMC_PCR_CMD | PMC_PCR_GCLKDIV(gclk_div - 1) + | PMC_PCR_GCLKCSS(gclk_css) | PMC_PCR_PID(periph_id))); + } +} + +/** + * \brief Disable the gclk clock of I2SC. + * + * \note The ID must not be shifted (i.e., 1 << ID_xxx). + * + * \param periph_id Peripheral ID + * + */ +static inline void _pmc_disable_gclk_clock(uint32_t periph_id) +{ + hri_pmc_write_PCR_reg(PMC, PMC_PCR_PID(periph_id)); + if ((hri_pmc_read_PCR_reg(PMC) & PMC_PCR_EN)) { + hri_pmc_write_PCR_reg(PMC, (PMC_PCR_CMD | PMC_PCR_PID(periph_id))); + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/microchip/same70/bsp/hpl/pmc/hpl_sleep.c b/bsp/microchip/same70/bsp/hpl/pmc/hpl_sleep.c new file mode 100644 index 0000000000..059a69c34d --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/pmc/hpl_sleep.c @@ -0,0 +1,252 @@ +/** + * \file + * + * \brief Power Management Controller register related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +/* Expected sleep mode for \ref _go_to_sleep() to enter */ +static uint8_t _sleep_mode = 0; + +/* Wait mode backup for MOR register */ +static uint32_t _mor; +/* Wait mode backup for MCKR register */ +static uint32_t _mckr; +/* Wait mode backup for FMR register */ +static uint32_t _fmr; +/* Wait mode backup for PLLAR register */ +static uint32_t _pllar; +/* Wait mode backup for UCKR register */ +static uint32_t _uckr; + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 0: /* Sleep Mode */ + break; + case 1: /* Wait Mode - USB suspend */ + case 2: /* Wait Mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + break; + case 3: /* Backup Mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + hri_supc_write_CR_reg(SUPC, SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG); + break; + default: + return ERR_INVALID_ARG; + } + _sleep_mode = mode; + return ERR_NONE; +} + +/** + * \brief Save clock settings and shutdown PLLs/OSCs + */ +static inline void _save_clocks(void) +{ + uint32_t mor = _mor = hri_pmc_read_CKGR_MOR_reg(PMC); + uint32_t mckr = _mckr = hri_pmc_read_MCKR_reg(PMC); + _fmr = hri_efc_read_EEFC_FMR_reg(EFC); + _pllar = hri_pmc_read_CKGR_PLLAR_reg(PMC); + _uckr = hri_pmc_read_CKGR_UCKR_reg(PMC); + + /* Enable FAST RC */ + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + + /* If MCK source is PLL, switch to MAINCK */ + if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { + /* MCK -> MAINCK */ + mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; + hri_pmc_write_MCKR_reg(PMC, mckr); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MCKRDY)) { + /* Wait MCK ready */ + } + } + + /* MCK PRES -> 1 */ + if (mckr & PMC_MCKR_PRES_Msk) { + mckr = (mckr & (~PMC_MCKR_PRES_Msk)); + hri_pmc_write_MCKR_reg(PMC, mckr); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MCKRDY)) { + /* Wait MCK ready */ + } + } + + /* Disable PLL(s) */ + hri_pmc_write_CKGR_PLLAR_reg(PMC, CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0)); + hri_pmc_write_CKGR_UCKR_reg(PMC, 0); + + /* Prepare for entering WAIT mode */ + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MOSCRCS)) { + /* Wait fast RC ready */ + } + + /* Switch MAINCK to FAST RC */ + mor &= ~CKGR_MOR_MOSCSEL; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MOSCSELS)) { + /* Wait switch to FAST RC */ + } + + /* Update FWS */ + hri_efc_write_EEFC_FMR_reg(EFC, _fmr & (~EEFC_FMR_FWS_Msk)); + + /* Disable XTALs */ + if (_sleep_mode == 2) { + mor &= ~CKGR_MOR_MOSCXTEN; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + } +} + +static inline void _restore_clocks(void) +{ + uint32_t mor; + uint32_t mckr; + uint32_t pll_sr = 0; + + /* Switch MAINCK to external XTAL */ + if (CKGR_MOR_MOSCXTBY == (_mor & CKGR_MOR_MOSCXTBY)) { + /* Bypass mode */ + /* Select bypass mode */ + mor = hri_pmc_read_CKGR_MOR_reg(PMC); + mor = (mor & (~CKGR_MOR_MOSCXTEN)) | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCSEL; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + /* Fully restore (Disable XTALs) */ + hri_pmc_write_CKGR_MOR_reg(PMC, _mor | CKGR_MOR_KEY_PASSWD); + } else if (CKGR_MOR_MOSCXTEN == (_mor & CKGR_MOR_MOSCXTEN)) { + /* Enable External XTAL */ + if (!hri_pmc_get_CKGR_MOR_reg(PMC, CKGR_MOR_MOSCXTEN)) { + mor = hri_pmc_read_CKGR_MOR_reg(PMC); + mor = (mor & (~CKGR_MOR_MOSCXTBY)) | CKGR_MOR_MOSCXTEN; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MOSCXTS)) { + /* Wait the XTAL to stabilize */ + } + } + /* Select External XTAL */ + if (!hri_pmc_get_CKGR_MOR_reg(PMC, CKGR_MOR_MOSCSEL)) { + mor = hri_pmc_read_CKGR_MOR_reg(PMC); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + hri_pmc_write_CKGR_MOR_reg(PMC, mor); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MOSCSELS)) { + /* Wait the XTAL switch */ + } + } + /* Fully restore (Disable Fast RC) */ + hri_pmc_write_CKGR_MOR_reg(PMC, _mor | CKGR_MOR_KEY_PASSWD); + } + + if (_pllar & CKGR_PLLAR_MULA_Msk) { + hri_pmc_write_CKGR_PLLAR_reg(PMC, _pllar | CKGR_PLLAR_ONE); + pll_sr |= PMC_SR_LOCKA; + } + if (_uckr & CKGR_UCKR_UPLLEN) { + hri_pmc_write_CKGR_UCKR_reg(PMC, _uckr); + pll_sr |= PMC_SR_LOCKU; + } + + /* Wait MCK source ready */ + switch (_mckr & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_PLLA_CLK: + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_LOCKA)) { + /* Wait PLLA lock */ + } + break; + case PMC_MCKR_CSS_UPLL_CLK: + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_LOCKU)) { + /* Wait UPLL lock */ + } + } + + /* Switch to faster clock */ + mckr = hri_pmc_read_MCKR_reg(PMC); + mckr = (mckr & (~PMC_MCKR_PRES_Msk)) | (_mckr & PMC_MCKR_PRES_Msk); + hri_pmc_write_MCKR_reg(PMC, mckr); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MCKRDY)) { + /* Wait MCK ready */ + } + + /* Restore FWS */ + hri_efc_write_EEFC_FMR_reg(EFC, _fmr); + + /* Fully restore MCKR (CSS and others) */ + hri_pmc_write_MCKR_reg(PMC, _mckr); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MCKRDY)) { + /* Wait MCK ready */ + } + + while (!hri_pmc_get_SR_reg(PMC, pll_sr)) { + /* Waiting all restored PLLs ready */ + } +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + bool irq_enabled = (__get_PRIMASK() == 0); + if (_sleep_mode == 1 || _sleep_mode == 2) { + __disable_irq(); + _save_clocks(); + __enable_irq(); + + /* Flash in wait mode: PMC_FSMR_FLPM_FLASH_STANDBY/_DEEP_POWERDOWN */ + hri_pmc_write_FSMR_FLPM_bf(PMC, _sleep_mode - 1); + /* Set the WAITMODE bit = 1 */ + __DSB(); + hri_pmc_set_CKGR_MOR_reg(PMC, CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE); + while (!hri_pmc_get_SR_reg(PMC, PMC_SR_MCKRDY)) { + /* Waiting for Master Clock Ready MCKRDY = 1 */ + } + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + while (!hri_pmc_get_CKGR_MOR_reg(PMC, CKGR_MOR_MOSCRCEN)) { + /* Waiting for MOSCRCEN */ + } + /* Flash in idle mode: PMC_FSMR_FLPM_FLASH_IDLE */ + hri_pmc_write_FSMR_FLPM_bf(PMC, 2); + + __disable_irq(); + _restore_clocks(); + if (irq_enabled) { + __enable_irq(); + } + } else { + __DSB(); + __WFI(); + } +} diff --git a/bsp/microchip/same70/bsp/hpl/systick/hpl_systick_ARMv7_base.c b/bsp/microchip/same70/bsp/hpl/systick/hpl_systick_ARMv7_base.c new file mode 100644 index 0000000000..bec816109b --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/systick/hpl_systick_ARMv7_base.c @@ -0,0 +1,106 @@ +/** + * \file + * + * \brief SysTick related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#ifdef _UNIT_TEST_ +#include +#endif + +/** + * \brief Initialize system time module + */ +void _system_time_init(void *const hw) +{ + (void)hw; + SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); + SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) + | (1 << SysTick_CTRL_CLKSOURCE_Pos); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + _system_time_init(hw); +} + +/** + * \brief De-initialize system time module + */ +void _system_time_deinit(void *const hw) +{ + (void)hw; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * \brief Get system time + */ +system_time_t _system_time_get(const void *const hw) +{ + (void)hw; + return (system_time_t)SysTick->VAL; +} + +/** + * \brief Get maximum possible system time + */ +system_time_t _system_time_get_max_time_value(const void *const hw) +{ + (void)hw; + return 0xFFFFFF; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ + (void)hw; + uint8_t n = cycles >> 24; + uint32_t buf = cycles; + + while (n--) { + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0xFFFFFF; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; + buf -= 0xFFFFFF; + } + + SysTick->LOAD = buf; + SysTick->VAL = buf; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; +} diff --git a/bsp/microchip/same70/bsp/hpl/usart/hpl_usart.c b/bsp/microchip/same70/bsp/hpl/usart/hpl_usart.c new file mode 100644 index 0000000000..e2c0d099a2 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/usart/hpl_usart.c @@ -0,0 +1,962 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef US_MR_SYNC_Pos +#define US_MR_SYNC_Pos 8 +#endif +#ifndef US_MR_MSBF_Pos +#define US_MR_MSBF_Pos 16 +#endif +#ifndef US_MR_MODE9_Pos +#define US_MR_MODE9_Pos 17 +#endif +#ifndef US_MR_CLKO_Pos +#define US_MR_CLKO_Pos 18 +#endif +#ifndef US_MR_OVER_Pos +#define US_MR_OVER_Pos 19 +#endif +#ifndef US_MR_INACK_Pos +#define US_MR_INACK_Pos 20 +#endif +#ifndef US_MR_DSNACK_Pos +#define US_MR_DSNACK_Pos 21 +#endif +#ifndef US_MR_VAR_SYNC_Pos +#define US_MR_VAR_SYNC_Pos 22 +#endif +#ifndef US_MR_INVDATA_Pos +#define US_MR_INVDATA_Pos 23 +#endif +#ifndef US_MR_FILTER_Pos +#define US_MR_FILTER_Pos 28 +#endif +#ifndef US_MR_MAN_Pos +#define US_MR_MAN_Pos 29 +#endif +#ifndef US_MR_MODSYNC_Pos +#define US_MR_MODSYNC_Pos 30 +#endif +#ifndef US_MR_ONEBIT_Pos +#define US_MR_ONEBIT_Pos 31 +#endif + +#ifndef CONF_USART_0_ENABLE +#define CONF_USART_0_ENABLE 0 +#endif +#ifndef CONF_USART_1_ENABLE +#define CONF_USART_1_ENABLE 0 +#endif +#ifndef CONF_USART_2_ENABLE +#define CONF_USART_2_ENABLE 0 +#endif + +/** Amount of USART. */ +#define USART_AMOUNT (CONF_USART_0_ENABLE + CONF_USART_1_ENABLE + CONF_USART_2_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ + +#define USART_CONFIGURATION(n) \ + { \ + n, \ + US_MR_USART_MODE(0x0) | US_MR_USCLKS(CONF_USART##n##_CK_SRC) | US_MR_CHRL(CONF_USART_##n##_CHSIZE) \ + | (CONF_USART_##n##_MODE << US_MR_USART_SYNC_Pos) | US_MR_USART_PAR(CONF_USART_##n##_PARITY) \ + | US_MR_USART_NBSTOP(CONF_USART_##n##_SBMODE) | US_MR_USART_CHMODE(CONF_USART_##n##_CHMODE) \ + | (CONF_USART_##n##_MSBF << US_MR_USART_MSBF_Pos) | (CONF_USART_##n##_MODE9 << US_MR_USART_MODE9_Pos) \ + | (CONF_USART_##n##_CLKO << US_MR_CLKO_Pos) | (CONF_USART_##n##_OVER << US_MR_USART_OVER_Pos) \ + | (CONF_USART_##n##_INACK << US_MR_USART_INACK_Pos) \ + | (CONF_USART_##n##_DSNACK << US_MR_USART_DSNACK_Pos) \ + | (CONF_USART_##n##_VAR_SYNC << US_MR_USART_VAR_SYNC_Pos) \ + | (CONF_USART_##n##_INVDATA << US_MR_USART_INVDATA_Pos) \ + | US_MR_USART_MAX_ITERATION(CONF_USART_##n##_MAX_ITERATION) \ + | (CONF_USART_##n##_FILTER << US_MR_USART_FILTER_Pos) | (CONF_USART_##n##_MAN << US_MR_USART_MAN_Pos) \ + | (CONF_USART_##n##_MODSYNC << US_MR_USART_MODSYNC_Pos) \ + | (CONF_USART_##n##_ONEBIT << US_MR_USART_ONEBIT_Pos), \ + US_BRGR_CD(CONF_USART_##n##_BAUD_CD) | US_BRGR_FP(CONF_USART_##n##_BAUD_FP) \ + } +/** + * \brief USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_usart_us_mr_reg_t us_mr; + hri_usart_us_brgr_reg_t us_brgr; +}; + +#if USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_USART_0_ENABLE == 1 + USART_CONFIGURATION(0), +#endif +#if CONF_USART_1_ENABLE == 1 + USART_CONFIGURATION(1), +#endif +#if CONF_USART_2_ENABLE == 1 + USART_CONFIGURATION(2), +#endif +}; +#endif + +static uint8_t _usart_get_irq_num(const void *const hw); +static uint8_t _get_usart_index(const void *const hw); +static uint8_t _usart_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_enable(void *const hw); +static inline void _usart_disable(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _usart_get_irq_num(const void *const hw) +{ + ASSERT(hw); + + return USART0_IRQn + _usart_get_hardware_index(hw); +} + +/** + * \brief Init irq param with the given usart hardware instance + */ +static void _usart_init_irq_param(const void *const hw, struct _usart_async_device *dev) +{ +} + +/** + * \brief Initialize synchronous USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + ASSERT(hw); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous USART + */ +int32_t _usart_usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + + _usart_init_irq_param(hw, device); + NVIC_DisableIRQ((IRQn_Type)_usart_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_usart_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_usart_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + ASSERT(device); + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize USART + */ +void _usart_usart_async_deinit(struct _usart_async_device *const device) +{ + ASSERT(device); + NVIC_DisableIRQ((IRQn_Type)_usart_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} +/** + * \brief Enable USART sync module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + ASSERT(device); + _usart_enable(device->hw); +} + +/** + * \brief Enable USART async module + */ +void _usart_usart_async_enable(struct _usart_async_device *const device) +{ + ASSERT(device); + _usart_enable(device->hw); +} + +/** + * \brief Disable USART sync module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + ASSERT(device); + _usart_disable(device->hw); +} + +/** + * \brief Disable USART async module + */ +void _usart_usart_async_disable(struct _usart_async_device *const device) +{ + ASSERT(device); + _usart_disable(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + ASSERT(device); + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + ASSERT(device); + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + ASSERT(device); + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + ASSERT(device); + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + ASSERT(device); + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + ASSERT(device); + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + ASSERT(device); + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + ASSERT(device); + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + ASSERT(device); + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + ASSERT(device); + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + ASSERT(device); + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_usart_async_set_character_size(struct _usart_async_device *const device, + const enum usart_character_size size) +{ + ASSERT(device); + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return (uint32_t)hri_usart_read_US_CSR_reg(device->hw); +} + +/** + * \brief Retrieve usart status + */ +uint32_t _usart_usart_async_get_status(const struct _usart_async_device *const device) +{ + ASSERT(device); + return (uint32_t)hri_usart_read_US_CSR_reg(device->hw); +} + +/** + * \brief Write a byte to the given USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + ASSERT(device); + hri_usart_write_US_THR_reg(device->hw, (hri_usart_us_thr_reg_t)data); +} + +/** + * \brief Write a byte to the given USART instance + */ +void _usart_usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + ASSERT(device); + hri_usart_write_US_THR_reg(device->hw, (hri_usart_us_thr_reg_t)data); +} + +/** + * \brief Read a byte from the given USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return (uint8_t)(hri_usart_read_US_RHR_reg(device->hw) & 0xff); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return hri_usart_get_US_CSR_TXRDY_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return hri_usart_get_US_CSR_TXEMPTY_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + ASSERT(device); + return hri_usart_get_US_CSR_TXRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return hri_usart_get_US_CSR_RXRDY_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + ASSERT(device); + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + ASSERT(device); + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + ASSERT(device); + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + ASSERT(device); + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + ASSERT(device); + hri_usart_set_US_IMR_TXRDY_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + ASSERT(device); + hri_usart_set_US_IMR_TXEMPTY_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given usart hardware instance + */ +static uint8_t _usart_get_hardware_index(const void *const hw) +{ + ASSERT(hw); + +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)USART0) / sizeof(Usart); +#endif + + return ((uint32_t)hw - (uint32_t)USART0) >> 14; +} + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + ASSERT(device); + return _usart_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + */ +uint8_t _usart_usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + ASSERT(device); + return _usart_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_usart_async_set_irq_state(struct _usart_async_device *const device, + const enum _usart_async_callback_type type, const bool state) +{ + ASSERT(device); + if (state) { + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_usart_set_US_IMR_TXRDY_bit(device->hw); + hri_usart_set_US_IMR_TXEMPTY_bit(device->hw); + } else if (USART_ASYNC_RX_DONE == type) { + hri_usart_set_US_IMR_RXRDY_bit(device->hw); + } else if (USART_ASYNC_ERROR == type) { + + hri_usart_set_US_IMR_reg( + device->hw, US_CSR_OVRE | US_CSR_USART_LIN_FRAME | US_CSR_USART_LIN_PARE | US_CSR_USART_MANERR); + } + } else { + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_usart_clear_US_IMR_TXRDY_bit(device->hw); + hri_usart_clear_US_IMR_TXEMPTY_bit(device->hw); + } else if (USART_ASYNC_RX_DONE == type) { + hri_usart_clear_US_IMR_RXRDY_bit(device->hw); + } else if (USART_ASYNC_ERROR == type) { + + hri_usart_clear_US_IMR_reg( + device->hw, US_CSR_OVRE | US_CSR_USART_LIN_FRAME | US_CSR_USART_LIN_PARE | US_CSR_USART_MANERR); + } + } +} + +/** + * \brief Retrieve usart sync helper functions + */ +void *_usart_get_usart_sync(void) +{ + return (void *)NULL; +} + +/** + * \brief Retrieve usart async helper functions + */ +void *_usart_get_usart_async(void) +{ + return (void *)NULL; +} + +/** + * \brief Retrieve usart dma helper functions + */ +void *_usart_get_usart_dma(void) +{ + return (void *)NULL; +} + +/** + * \internal Retrieve ordinal number of the given usart hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given usart hardware instance + */ +static uint8_t _get_usart_index(const void *const hw) +{ + ASSERT(hw); + uint8_t usart_offset = _usart_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == usart_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \internal Initialize USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + ASSERT(hw); + uint8_t i = _get_usart_index(hw); + /* Disable the Write Protect. */ + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + + /* Reset registers that could cause unpredictable behavior after reset. */ + hri_usart_write_US_MR_reg(hw, 0x0); + hri_usart_write_US_RTOR_reg(hw, 0x0); + hri_usart_write_US_TTGR_reg(hw, 0x0); + + /* Disable and reset TX and RX. */ + hri_usart_write_US_CR_reg(hw, US_CR_RSTRX | US_CR_RXDIS | US_CR_RSTTX | US_CR_TXDIS); + /* Reset status bits. */ + hri_usart_write_US_CR_reg(hw, US_CR_RSTSTA); + /* Turn off RTS and DTR if exist. */ + hri_usart_write_US_CR_reg(hw, US_CR_USART_RTSDIS); + + hri_usart_write_US_MR_reg(hw, _usarts[i].us_mr); + hri_usart_write_US_BRGR_reg(hw, _usarts[i].us_brgr); + + return ERR_NONE; +} + +/** + * \internal De-initialize USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + ASSERT(hw); + hri_usart_write_US_CR_reg(hw, US_CR_RSTRX | US_CR_RSTTX | US_CR_RSTSTA); +} + +/** + * \internal Enable USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_enable(void *const hw) +{ + ASSERT(hw); + hri_usart_write_US_CR_reg(hw, US_CR_RXEN | US_CR_TXEN); +} + +/** + * \internal Disable USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_disable(void *const hw) +{ + ASSERT(hw); + hri_usart_write_US_CR_reg(hw, US_CR_RXDIS | US_CR_TXDIS); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate USART clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return clock_rate / baud / samples; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + US_BRGR_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + ASSERT(hw); + uint32_t usart_freq, cd = 0, fp = 0, clock_select; + bool over; + uint8_t i = _usarts[_get_usart_index(hw)].number; + switch (i) { + case 0: + +#ifdef CONF_USART0_FREQUENCY + usart_freq = CONF_USART0_FREQUENCY; +#endif + break; + + case 1: +#ifdef CONF_USART1_FREQUENCY + usart_freq = CONF_USART1_FREQUENCY; +#endif + break; + + case 2: +#ifdef CONF_USART2_FREQUENCY + usart_freq = CONF_USART2_FREQUENCY; +#endif + break; + + default: + ASSERT(false); + } + + clock_select = hri_usart_read_US_MR_USCLKS_bf(hw); + if (hri_usart_get_US_MR_USART_SYNC_bit(hw)) { + switch (clock_select) { + case 0x0: + case 0x1: + case 0x2: + cd = usart_freq / baud_rate; + fp = usart_freq * 8 / baud_rate - 8 * cd; + break; + + case 0x3: + break; + + default: + ASSERT(false); + } + } else { + over = hri_usart_get_US_MR_USART_OVER_bit(hw); + switch (clock_select) { + case 0x0: + case 0x1: + case 0x2: + cd = usart_freq / baud_rate / 8 / (2 - over); + fp = usart_freq / baud_rate / (2 - over) - 8 * cd; + break; + + case 0x3: + break; + + default: + ASSERT(false); + } + } + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + hri_usart_write_US_BRGR_reg(hw, US_BRGR_CD(cd) | US_BRGR_FP(fp)); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + ASSERT(hw); + + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + if (order == USART_DATA_ORDER_MSB) { + hri_usart_set_US_MR_USART_MSBF_bit(hw); + } else { + hri_usart_clear_US_MR_USART_MSBF_bit(hw); + } +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + ASSERT(hw); + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + if (mode == USART_MODE_SYNCHRONOUS) { + hri_usart_set_US_MR_USART_SYNC_bit(hw); + } else { + hri_usart_clear_US_MR_USART_SYNC_bit(hw); + } +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + ASSERT(hw); + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + switch (parity) { + case USART_PARITY_EVEN: + hri_usart_write_US_MR_USART_PAR_bf(hw, (hri_usart_us_mr_reg_t)0x0u); + break; + + case USART_PARITY_ODD: + hri_usart_write_US_MR_USART_PAR_bf(hw, (hri_usart_us_mr_reg_t)0x1u); + break; + + case USART_PARITY_SPACE: + hri_usart_write_US_MR_USART_PAR_bf(hw, (hri_usart_us_mr_reg_t)0x2u); + break; + + case USART_PARITY_MARK: + hri_usart_write_US_MR_USART_PAR_bf(hw, (hri_usart_us_mr_reg_t)0x3u); + break; + + case USART_PARITY_NONE: + hri_usart_write_US_MR_USART_PAR_bf(hw, (hri_usart_us_mr_reg_t)0x4u); + break; + + default: + ASSERT(false); + } +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + ASSERT(hw); + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + switch (stop_bits) { + case USART_STOP_BITS_ONE: + hri_usart_write_US_MR_USART_NBSTOP_bf(hw, (hri_usart_us_mr_reg_t)0x0u); + break; + + case USART_STOP_BITS_TWO: + hri_usart_write_US_MR_USART_NBSTOP_bf(hw, (hri_usart_us_mr_reg_t)0x2u); + break; + + case USART_STOP_BITS_ONE_P_FIVE: + hri_usart_write_US_MR_USART_NBSTOP_bf(hw, (hri_usart_us_mr_reg_t)0x1u); + break; + + default: + ASSERT(false); + } +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + ASSERT(hw); + hri_usart_write_US_WPMR_reg(hw, US_WPMR_WPKEY_PASSWD); + if (size == USART_CHARACTER_SIZE_9BITS) { + hri_usart_set_US_MR_USART_MODE9_bit(hw); + } else { + hri_usart_clear_US_MR_USART_MODE9_bit(hw); + switch (size) { + case USART_CHARACTER_SIZE_5BITS: + hri_usart_write_US_MR_CHRL_bf(hw, (hri_usart_us_mr_reg_t)0x0u); + break; + + case USART_CHARACTER_SIZE_6BITS: + hri_usart_write_US_MR_CHRL_bf(hw, (hri_usart_us_mr_reg_t)0x1u); + break; + + case USART_CHARACTER_SIZE_7BITS: + hri_usart_write_US_MR_CHRL_bf(hw, (hri_usart_us_mr_reg_t)0x2u); + break; + + case USART_CHARACTER_SIZE_8BITS: + hri_usart_write_US_MR_CHRL_bf(hw, (hri_usart_us_mr_reg_t)0x3u); + break; + + default: + ASSERT(false); + } + } +} diff --git a/bsp/microchip/same70/bsp/hpl/usart/hpl_usart_base.h b/bsp/microchip/same70/bsp/hpl/usart/hpl_usart_base.h new file mode 100644 index 0000000000..b4b927c855 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/usart/hpl_usart_base.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_USART_H_INCLUDED +#define _HPL_USART_USART_H_INCLUDED + +#include +#include + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +void *_usart_get_usart_sync(void); +void *_usart_get_usart_async(void); +void *_usart_get_usart_dma(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_USART_H_INCLUDED */ diff --git a/bsp/microchip/same70/bsp/hpl/xdmac/hpl_xdmac.c b/bsp/microchip/same70/bsp/hpl/xdmac/hpl_xdmac.c new file mode 100644 index 0000000000..4723b696c1 --- /dev/null +++ b/bsp/microchip/same70/bsp/hpl/xdmac/hpl_xdmac.c @@ -0,0 +1,227 @@ + +/** + * \file + * + * \brief SAM DMA Controller (XDMAC) Interface + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#if CONF_DMA_ENABLE +#define DMAC_CH_NUM 24 + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {XDMAC_CC_MBSIZE(CONF_DMAC_BURSTSIZE_##n) | XDMAC_CC_CSIZE(CONF_DMAC_CHUNKSIZE_##n) \ + | XDMAC_CC_DWIDTH(CONF_DMAC_BEATSIZE_##n) | (CONF_DMAC_SRC_INTERFACE_##n << XDMAC_CC_SIF_Pos) \ + | (CONF_DMAC_DES_INTERFACE_##n << XDMAC_CC_DIF_Pos) \ + | XDMAC_CC_SAM((CONF_DMAC_SRC_STRIDE_##n == -1) ? 3 : CONF_DMAC_SRCINC_##n) \ + | XDMAC_CC_DAM((CONF_DMAC_DES_STRIDE_##n == -1) ? 3 : CONF_DMAC_DSTINC_##n) \ + | (CONF_DMAC_TYPE_##n << XDMAC_CC_TYPE_Pos) | (CONF_DMAC_DSYNC_##n << XDMAC_CC_DSYNC_Pos) \ + | (CONF_DMAC_SWREQ_##n << XDMAC_CC_SWREQ_Pos) \ + | ((!CONF_DMAC_SWREQ_##n) ? XDMAC_CC_PERID(CONF_DMAC_TRIGSRC_##n) : 0x0), \ + XDMAC_CDS_MSP_SDS_MSP(CONF_DMAC_SRC_STRIDE_##n) | XDMAC_CDS_MSP_DDS_MSP(CONF_DMAC_DES_STRIDE_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t config_reg; + uint32_t cds_msp; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +int32_t _dma_init(void) +{ + uint8_t i; + + /* Clear the pending Interrupt Status bit */ + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_xdmac_read_CIS_reg(XDMAC, i); + } + /* Configuration Registers */ + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_xdmac_write_CNDC_reg(XDMAC, i, 0x0); + hri_xdmac_write_CBC_reg(XDMAC, i, 0x0); + hri_xdmac_write_CSUS_reg(XDMAC, i, 0x0); + hri_xdmac_write_CDUS_reg(XDMAC, i, 0x0); + hri_xdmac_write_CC_reg(XDMAC, i, _cfgs[i].config_reg); + hri_xdmac_write_CDS_MSP_reg(XDMAC, i, _cfgs[i].cds_msp); + } + + NVIC_DisableIRQ(XDMAC_IRQn); + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_EnableIRQ(XDMAC_IRQn); + + return ERR_NONE; +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_xdmac_write_CDA_reg(XDMAC, channel, (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_xdmac_write_CSA_reg(XDMAC, channel, (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + if (!enable && (hri_xdmac_read_CC_DWIDTH_bf(XDMAC, channel) != XDMAC_CC_DWIDTH_WORD_Val)) { + /* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source + * address or fixed destination address mode, source and destination addresses + * are incremented by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing + * mode to use micro block and data striding with micro block stride set to 0 and + * data stride set to -1. + */ + hri_xdmac_write_CC_SAM_bf(XDMAC, channel, XDMAC_CC_SAM_UBS_DS_AM_Val); + hri_xdmac_write_CDS_MSP_SDS_MSP_bf(XDMAC, channel, (int16_t)(-1)); + } else { + hri_xdmac_write_CC_SAM_bf(XDMAC, channel, enable); + } + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + if (!enable && (hri_xdmac_read_CC_DWIDTH_bf(XDMAC, channel) != XDMAC_CC_DWIDTH_WORD_Val)) { + /* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source + * address or fixed destination address mode, source and destination addresses + * are incremented by 8-bit or 16-bit. + * Workaround: The user can fix the problem by setting the source addressing + * mode to use micro block and data striding with micro block stride set to 0 and + * data stride set to -1. + */ + hri_xdmac_write_CC_DAM_bf(XDMAC, channel, XDMAC_CC_DAM_UBS_DS_AM_Val); + hri_xdmac_write_CDS_MSP_SDS_MSP_bf(XDMAC, channel, (int16_t)(-1)); + } else { + hri_xdmac_write_CC_DAM_bf(XDMAC, channel, enable); + } + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint8_t width; + + width = hri_xdmac_get_CC_DWIDTH_bf(XDMAC, channel, 0x3); + hri_xdmac_write_CUBC_reg(XDMAC, channel, amount >> width); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_xdmac_set_GS_reg(XDMAC, 1 << channel); + + if (software_trigger) { + hri_xdmac_write_GSWR_reg(XDMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (state) { + if (type == DMA_TRANSFER_COMPLETE_CB) { + hri_xdmac_set_CIM_reg(XDMAC, channel, XDMAC_CIE_BIE); + } else if (type == DMA_TRANSFER_ERROR_CB) { + hri_xdmac_set_CIM_reg(XDMAC, channel, XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE); + } + hri_xdmac_set_GIM_reg(XDMAC, (1 << channel)); + } else { + if (type == DMA_TRANSFER_COMPLETE_CB) { + hri_xdmac_clear_CIM_reg(XDMAC, channel, XDMAC_CID_BID); + } else if (type == DMA_TRANSFER_ERROR_CB) { + hri_xdmac_clear_CIM_reg(XDMAC, channel, XDMAC_CID_RBEID | XDMAC_CID_WBEID | XDMAC_CID_ROID); + } + hri_xdmac_clear_GIM_reg(XDMAC, (1 << channel)); + } +} + +/** + * \internal XDMAC interrupt handler + */ +void XDMAC_Handler(void) +{ + uint32_t status; + struct _dma_resource *tmp_resource; + int8_t channel = -1; + uint32_t pend; + + pend = hri_xdmac_read_GIS_reg(XDMAC); + + /* Get the first pending channel ID */ + for (uint8_t i = 0; i < DMAC_CH_NUM; i++) { + if ((pend >> i) & 1) { + channel = i; + break; + } + } + + if (channel < 0) { + return; + } + + tmp_resource = &_resources[channel]; + status = hri_xdmac_read_CIS_reg(XDMAC, channel); + + if (status & (XDMAC_CIS_RBEIS | XDMAC_CIS_WBEIS | XDMAC_CIS_ROIS)) { + tmp_resource->dma_cb.error(tmp_resource); + } else if (status & XDMAC_CIS_BIS) { + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} + +#endif /* CONF_DMA_ENABLE */ diff --git a/bsp/microchip/same70/bsp/hri/hri_acc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_acc_e70b.h new file mode 100644 index 0000000000..cffbc5c7e5 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_acc_e70b.h @@ -0,0 +1,774 @@ +/** + * \file + * + * \brief SAM ACC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_ACC_COMPONENT_ +#ifndef _HRI_ACC_E70B_H_INCLUDED_ +#define _HRI_ACC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ACC_CRITICAL_SECTIONS) +#define ACC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ACC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ACC_CRITICAL_SECTION_ENTER() +#define ACC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_acc_acr_reg_t; +typedef uint32_t hri_acc_cr_reg_t; +typedef uint32_t hri_acc_imr_reg_t; +typedef uint32_t hri_acc_isr_reg_t; +typedef uint32_t hri_acc_mr_reg_t; +typedef uint32_t hri_acc_wpmr_reg_t; +typedef uint32_t hri_acc_wpsr_reg_t; + +static inline bool hri_acc_get_ISR_CE_bit(const void *const hw) +{ + return (((Acc *)hw)->ACC_ISR & ACC_ISR_CE) >> ACC_ISR_CE_Pos; +} + +static inline bool hri_acc_get_ISR_SCO_bit(const void *const hw) +{ + return (((Acc *)hw)->ACC_ISR & ACC_ISR_SCO) >> ACC_ISR_SCO_Pos; +} + +static inline bool hri_acc_get_ISR_MASK_bit(const void *const hw) +{ + return (((Acc *)hw)->ACC_ISR & ACC_ISR_MASK) >> ACC_ISR_MASK_Pos; +} + +static inline hri_acc_isr_reg_t hri_acc_get_ISR_reg(const void *const hw, hri_acc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_acc_isr_reg_t hri_acc_read_ISR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_ISR; +} + +static inline void hri_acc_set_IMR_CE_bit(const void *const hw) +{ + ((Acc *)hw)->ACC_IER = ACC_IMR_CE; +} + +static inline bool hri_acc_get_IMR_CE_bit(const void *const hw) +{ + return (((Acc *)hw)->ACC_IMR & ACC_IMR_CE) >> ACC_IMR_CE_Pos; +} + +static inline void hri_acc_write_IMR_CE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Acc *)hw)->ACC_IDR = ACC_IMR_CE; + } else { + ((Acc *)hw)->ACC_IER = ACC_IMR_CE; + } +} + +static inline void hri_acc_clear_IMR_CE_bit(const void *const hw) +{ + ((Acc *)hw)->ACC_IDR = ACC_IMR_CE; +} + +static inline void hri_acc_set_IMR_reg(const void *const hw, hri_acc_imr_reg_t mask) +{ + ((Acc *)hw)->ACC_IER = mask; +} + +static inline hri_acc_imr_reg_t hri_acc_get_IMR_reg(const void *const hw, hri_acc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_acc_imr_reg_t hri_acc_read_IMR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_IMR; +} + +static inline void hri_acc_write_IMR_reg(const void *const hw, hri_acc_imr_reg_t data) +{ + ((Acc *)hw)->ACC_IER = data; + ((Acc *)hw)->ACC_IDR = ~data; +} + +static inline void hri_acc_clear_IMR_reg(const void *const hw, hri_acc_imr_reg_t mask) +{ + ((Acc *)hw)->ACC_IDR = mask; +} + +static inline bool hri_acc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Acc *)hw)->ACC_WPSR & ACC_WPSR_WPVS) > 0; +} + +static inline hri_acc_wpsr_reg_t hri_acc_get_WPSR_reg(const void *const hw, hri_acc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_acc_wpsr_reg_t hri_acc_read_WPSR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_WPSR; +} + +static inline void hri_acc_set_MR_ACEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_ACEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_MR_ACEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_ACEN) >> ACC_MR_ACEN_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_MR_ACEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_ACEN; + tmp |= value << ACC_MR_ACEN_Pos; + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_ACEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_ACEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_ACEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_ACEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_MR_INV_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_INV; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_MR_INV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_INV) >> ACC_MR_INV_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_MR_INV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_INV; + tmp |= value << ACC_MR_INV_Pos; + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_INV_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_INV; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_INV_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_INV; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_MR_SELFS_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_SELFS; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_MR_SELFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_SELFS) >> ACC_MR_SELFS_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_MR_SELFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_SELFS; + tmp |= value << ACC_MR_SELFS_Pos; + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_SELFS_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_SELFS; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_SELFS_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_SELFS; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_MR_FE_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_FE; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_MR_FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_FE) >> ACC_MR_FE_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_MR_FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_FE; + tmp |= value << ACC_MR_FE_Pos; + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_FE_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_FE; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_FE_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_FE; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_MR_SELMINUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_SELMINUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_get_MR_SELMINUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_SELMINUS(mask)) >> ACC_MR_SELMINUS_Pos; + return tmp; +} + +static inline void hri_acc_write_MR_SELMINUS_bf(const void *const hw, hri_acc_mr_reg_t data) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_SELMINUS_Msk; + tmp |= ACC_MR_SELMINUS(data); + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_SELMINUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_SELMINUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_SELMINUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_SELMINUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_read_MR_SELMINUS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_SELMINUS_Msk) >> ACC_MR_SELMINUS_Pos; + return tmp; +} + +static inline void hri_acc_set_MR_SELPLUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_SELPLUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_get_MR_SELPLUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_SELPLUS(mask)) >> ACC_MR_SELPLUS_Pos; + return tmp; +} + +static inline void hri_acc_write_MR_SELPLUS_bf(const void *const hw, hri_acc_mr_reg_t data) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_SELPLUS_Msk; + tmp |= ACC_MR_SELPLUS(data); + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_SELPLUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_SELPLUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_SELPLUS_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_SELPLUS(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_read_MR_SELPLUS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_SELPLUS_Msk) >> ACC_MR_SELPLUS_Pos; + return tmp; +} + +static inline void hri_acc_set_MR_EDGETYP_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= ACC_MR_EDGETYP(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_get_MR_EDGETYP_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_EDGETYP(mask)) >> ACC_MR_EDGETYP_Pos; + return tmp; +} + +static inline void hri_acc_write_MR_EDGETYP_bf(const void *const hw, hri_acc_mr_reg_t data) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_MR; + tmp &= ~ACC_MR_EDGETYP_Msk; + tmp |= ACC_MR_EDGETYP(data); + ((Acc *)hw)->ACC_MR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_EDGETYP_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~ACC_MR_EDGETYP(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_EDGETYP_bf(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= ACC_MR_EDGETYP(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_read_MR_EDGETYP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp = (tmp & ACC_MR_EDGETYP_Msk) >> ACC_MR_EDGETYP_Pos; + return tmp; +} + +static inline void hri_acc_set_MR_reg(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR |= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_get_MR_reg(const void *const hw, hri_acc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_acc_write_MR_reg(const void *const hw, hri_acc_mr_reg_t data) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR = data; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_MR_reg(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR &= ~mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_MR_reg(const void *const hw, hri_acc_mr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_MR ^= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_mr_reg_t hri_acc_read_MR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_MR; +} + +static inline void hri_acc_set_ACR_ISEL_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR |= ACC_ACR_ISEL; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_ACR_ISEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_ACR; + tmp = (tmp & ACC_ACR_ISEL) >> ACC_ACR_ISEL_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_ACR_ISEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_ACR; + tmp &= ~ACC_ACR_ISEL; + tmp |= value << ACC_ACR_ISEL_Pos; + ((Acc *)hw)->ACC_ACR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_ACR_ISEL_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR &= ~ACC_ACR_ISEL; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_ACR_ISEL_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR ^= ACC_ACR_ISEL; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_ACR_HYST_bf(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR |= ACC_ACR_HYST(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_acr_reg_t hri_acc_get_ACR_HYST_bf(const void *const hw, hri_acc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_ACR; + tmp = (tmp & ACC_ACR_HYST(mask)) >> ACC_ACR_HYST_Pos; + return tmp; +} + +static inline void hri_acc_write_ACR_HYST_bf(const void *const hw, hri_acc_acr_reg_t data) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_ACR; + tmp &= ~ACC_ACR_HYST_Msk; + tmp |= ACC_ACR_HYST(data); + ((Acc *)hw)->ACC_ACR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_ACR_HYST_bf(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR &= ~ACC_ACR_HYST(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_ACR_HYST_bf(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR ^= ACC_ACR_HYST(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_acr_reg_t hri_acc_read_ACR_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_ACR; + tmp = (tmp & ACC_ACR_HYST_Msk) >> ACC_ACR_HYST_Pos; + return tmp; +} + +static inline void hri_acc_set_ACR_reg(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR |= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_acr_reg_t hri_acc_get_ACR_reg(const void *const hw, hri_acc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_ACR; + tmp &= mask; + return tmp; +} + +static inline void hri_acc_write_ACR_reg(const void *const hw, hri_acc_acr_reg_t data) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR = data; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_ACR_reg(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR &= ~mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_ACR_reg(const void *const hw, hri_acc_acr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_ACR ^= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_acr_reg_t hri_acc_read_ACR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_ACR; +} + +static inline void hri_acc_set_WPMR_WPEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR |= ACC_WPMR_WPEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_acc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_WPMR; + tmp = (tmp & ACC_WPMR_WPEN) >> ACC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_acc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_WPMR; + tmp &= ~ACC_WPMR_WPEN; + tmp |= value << ACC_WPMR_WPEN_Pos; + ((Acc *)hw)->ACC_WPMR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_WPMR_WPEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR &= ~ACC_WPMR_WPEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR ^= ACC_WPMR_WPEN; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_set_WPMR_WPKEY_bf(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR |= ACC_WPMR_WPKEY(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_wpmr_reg_t hri_acc_get_WPMR_WPKEY_bf(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_WPMR; + tmp = (tmp & ACC_WPMR_WPKEY(mask)) >> ACC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_acc_write_WPMR_WPKEY_bf(const void *const hw, hri_acc_wpmr_reg_t data) +{ + uint32_t tmp; + ACC_CRITICAL_SECTION_ENTER(); + tmp = ((Acc *)hw)->ACC_WPMR; + tmp &= ~ACC_WPMR_WPKEY_Msk; + tmp |= ACC_WPMR_WPKEY(data); + ((Acc *)hw)->ACC_WPMR = tmp; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_WPMR_WPKEY_bf(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR &= ~ACC_WPMR_WPKEY(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR ^= ACC_WPMR_WPKEY(mask); + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_wpmr_reg_t hri_acc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_WPMR; + tmp = (tmp & ACC_WPMR_WPKEY_Msk) >> ACC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_acc_set_WPMR_reg(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR |= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_wpmr_reg_t hri_acc_get_WPMR_reg(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Acc *)hw)->ACC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_acc_write_WPMR_reg(const void *const hw, hri_acc_wpmr_reg_t data) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR = data; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_clear_WPMR_reg(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR &= ~mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_acc_toggle_WPMR_reg(const void *const hw, hri_acc_wpmr_reg_t mask) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_WPMR ^= mask; + ACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_acc_wpmr_reg_t hri_acc_read_WPMR_reg(const void *const hw) +{ + return ((Acc *)hw)->ACC_WPMR; +} + +static inline void hri_acc_write_CR_reg(const void *const hw, hri_acc_cr_reg_t data) +{ + ACC_CRITICAL_SECTION_ENTER(); + ((Acc *)hw)->ACC_CR = data; + ACC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ACC_E70B_H_INCLUDED */ +#endif /* _SAME70_ACC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_aes_e70b.h b/bsp/microchip/same70/bsp/hri/hri_aes_e70b.h new file mode 100644 index 0000000000..0554b00752 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_aes_e70b.h @@ -0,0 +1,1147 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_AES_COMPONENT_ +#ifndef _HRI_AES_E70B_H_INCLUDED_ +#define _HRI_AES_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_aadlenr_reg_t; +typedef uint32_t hri_aes_clenr_reg_t; +typedef uint32_t hri_aes_cr_reg_t; +typedef uint32_t hri_aes_ctrr_reg_t; +typedef uint32_t hri_aes_gcmhr_reg_t; +typedef uint32_t hri_aes_ghashr_reg_t; +typedef uint32_t hri_aes_idatar_reg_t; +typedef uint32_t hri_aes_imr_reg_t; +typedef uint32_t hri_aes_isr_reg_t; +typedef uint32_t hri_aes_ivr_reg_t; +typedef uint32_t hri_aes_keywr_reg_t; +typedef uint32_t hri_aes_mr_reg_t; +typedef uint32_t hri_aes_odatar_reg_t; +typedef uint32_t hri_aes_tagr_reg_t; + +static inline bool hri_aes_get_ISR_DATRDY_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_ISR & AES_ISR_DATRDY) >> AES_ISR_DATRDY_Pos; +} + +static inline bool hri_aes_get_ISR_URAD_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_ISR & AES_ISR_URAD) >> AES_ISR_URAD_Pos; +} + +static inline bool hri_aes_get_ISR_TAGRDY_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_ISR & AES_ISR_TAGRDY) >> AES_ISR_TAGRDY_Pos; +} + +static inline hri_aes_isr_reg_t hri_aes_get_ISR_reg(const void *const hw, hri_aes_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_aes_isr_reg_t hri_aes_read_ISR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_ISR; +} + +static inline void hri_aes_set_IMR_DATRDY_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IER = AES_IMR_DATRDY; +} + +static inline bool hri_aes_get_IMR_DATRDY_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_IMR & AES_IMR_DATRDY) >> AES_IMR_DATRDY_Pos; +} + +static inline void hri_aes_write_IMR_DATRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->AES_IDR = AES_IMR_DATRDY; + } else { + ((Aes *)hw)->AES_IER = AES_IMR_DATRDY; + } +} + +static inline void hri_aes_clear_IMR_DATRDY_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IDR = AES_IMR_DATRDY; +} + +static inline void hri_aes_set_IMR_URAD_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IER = AES_IMR_URAD; +} + +static inline bool hri_aes_get_IMR_URAD_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_IMR & AES_IMR_URAD) >> AES_IMR_URAD_Pos; +} + +static inline void hri_aes_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->AES_IDR = AES_IMR_URAD; + } else { + ((Aes *)hw)->AES_IER = AES_IMR_URAD; + } +} + +static inline void hri_aes_clear_IMR_URAD_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IDR = AES_IMR_URAD; +} + +static inline void hri_aes_set_IMR_TAGRDY_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IER = AES_IMR_TAGRDY; +} + +static inline bool hri_aes_get_IMR_TAGRDY_bit(const void *const hw) +{ + return (((Aes *)hw)->AES_IMR & AES_IMR_TAGRDY) >> AES_IMR_TAGRDY_Pos; +} + +static inline void hri_aes_write_IMR_TAGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->AES_IDR = AES_IMR_TAGRDY; + } else { + ((Aes *)hw)->AES_IER = AES_IMR_TAGRDY; + } +} + +static inline void hri_aes_clear_IMR_TAGRDY_bit(const void *const hw) +{ + ((Aes *)hw)->AES_IDR = AES_IMR_TAGRDY; +} + +static inline void hri_aes_set_IMR_reg(const void *const hw, hri_aes_imr_reg_t mask) +{ + ((Aes *)hw)->AES_IER = mask; +} + +static inline hri_aes_imr_reg_t hri_aes_get_IMR_reg(const void *const hw, hri_aes_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_aes_imr_reg_t hri_aes_read_IMR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_IMR; +} + +static inline void hri_aes_write_IMR_reg(const void *const hw, hri_aes_imr_reg_t data) +{ + ((Aes *)hw)->AES_IER = data; + ((Aes *)hw)->AES_IDR = ~data; +} + +static inline void hri_aes_clear_IMR_reg(const void *const hw, hri_aes_imr_reg_t mask) +{ + ((Aes *)hw)->AES_IDR = mask; +} + +static inline hri_aes_odatar_reg_t hri_aes_get_ODATAR_ODATA_bf(const void *const hw, uint8_t index, + hri_aes_odatar_reg_t mask) +{ + return (((Aes *)hw)->AES_ODATAR[index] & AES_ODATAR_ODATA(mask)) >> AES_ODATAR_ODATA_Pos; +} + +static inline hri_aes_odatar_reg_t hri_aes_read_ODATAR_ODATA_bf(const void *const hw, uint8_t index) +{ + return (((Aes *)hw)->AES_ODATAR[index] & AES_ODATAR_ODATA_Msk) >> AES_ODATAR_ODATA_Pos; +} + +static inline hri_aes_odatar_reg_t hri_aes_get_ODATAR_reg(const void *const hw, uint8_t index, + hri_aes_odatar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_ODATAR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_aes_odatar_reg_t hri_aes_read_ODATAR_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->AES_ODATAR[index]; +} + +static inline hri_aes_tagr_reg_t hri_aes_get_TAGR_TAG_bf(const void *const hw, uint8_t index, hri_aes_tagr_reg_t mask) +{ + return (((Aes *)hw)->AES_TAGR[index] & AES_TAGR_TAG(mask)) >> AES_TAGR_TAG_Pos; +} + +static inline hri_aes_tagr_reg_t hri_aes_read_TAGR_TAG_bf(const void *const hw, uint8_t index) +{ + return (((Aes *)hw)->AES_TAGR[index] & AES_TAGR_TAG_Msk) >> AES_TAGR_TAG_Pos; +} + +static inline hri_aes_tagr_reg_t hri_aes_get_TAGR_reg(const void *const hw, uint8_t index, hri_aes_tagr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_TAGR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_aes_tagr_reg_t hri_aes_read_TAGR_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->AES_TAGR[index]; +} + +static inline hri_aes_ctrr_reg_t hri_aes_get_CTRR_CTR_bf(const void *const hw, hri_aes_ctrr_reg_t mask) +{ + return (((Aes *)hw)->AES_CTRR & AES_CTRR_CTR(mask)) >> AES_CTRR_CTR_Pos; +} + +static inline hri_aes_ctrr_reg_t hri_aes_read_CTRR_CTR_bf(const void *const hw) +{ + return (((Aes *)hw)->AES_CTRR & AES_CTRR_CTR_Msk) >> AES_CTRR_CTR_Pos; +} + +static inline hri_aes_ctrr_reg_t hri_aes_get_CTRR_reg(const void *const hw, hri_aes_ctrr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_CTRR; + tmp &= mask; + return tmp; +} + +static inline hri_aes_ctrr_reg_t hri_aes_read_CTRR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_CTRR; +} + +static inline void hri_aes_set_MR_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_MR_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_CIPHER) >> AES_MR_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_MR_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_CIPHER; + tmp |= value << AES_MR_CIPHER_Pos; + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_MR_GTAGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_GTAGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_MR_GTAGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_GTAGEN) >> AES_MR_GTAGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_MR_GTAGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_GTAGEN; + tmp |= value << AES_MR_GTAGEN_Pos; + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_GTAGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_GTAGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_GTAGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_GTAGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_MR_DUALBUFF_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_DUALBUFF; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_MR_DUALBUFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_DUALBUFF) >> AES_MR_DUALBUFF_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_MR_DUALBUFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_DUALBUFF; + tmp |= value << AES_MR_DUALBUFF_Pos; + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_DUALBUFF_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_DUALBUFF; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_DUALBUFF_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_DUALBUFF; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_MR_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_MR_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_LOD) >> AES_MR_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_MR_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_LOD; + tmp |= value << AES_MR_LOD_Pos; + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_MR_PROCDLY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_PROCDLY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_PROCDLY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_PROCDLY(mask)) >> AES_MR_PROCDLY_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_PROCDLY_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_PROCDLY_Msk; + tmp |= AES_MR_PROCDLY(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_PROCDLY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_PROCDLY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_PROCDLY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_PROCDLY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_PROCDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_PROCDLY_Msk) >> AES_MR_PROCDLY_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_SMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_SMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_SMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_SMOD(mask)) >> AES_MR_SMOD_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_SMOD_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_SMOD_Msk; + tmp |= AES_MR_SMOD(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_SMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_SMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_SMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_SMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_SMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_SMOD_Msk) >> AES_MR_SMOD_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_KEYSIZE_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_KEYSIZE_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_KEYSIZE(mask)) >> AES_MR_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_KEYSIZE_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_KEYSIZE_Msk; + tmp |= AES_MR_KEYSIZE(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_KEYSIZE_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_KEYSIZE_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_KEYSIZE_Msk) >> AES_MR_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_OPMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_OPMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_OPMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_OPMOD(mask)) >> AES_MR_OPMOD_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_OPMOD_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_OPMOD_Msk; + tmp |= AES_MR_OPMOD(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_OPMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_OPMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_OPMOD_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_OPMOD(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_OPMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_OPMOD_Msk) >> AES_MR_OPMOD_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_CFBS_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_CFBS_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_CFBS(mask)) >> AES_MR_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_CFBS_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_CFBS_Msk; + tmp |= AES_MR_CFBS(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_CFBS_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_CFBS_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_CFBS_Msk) >> AES_MR_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_CKEY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= AES_MR_CKEY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_CKEY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_CKEY(mask)) >> AES_MR_CKEY_Pos; + return tmp; +} + +static inline void hri_aes_write_MR_CKEY_bf(const void *const hw, hri_aes_mr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_MR; + tmp &= ~AES_MR_CKEY_Msk; + tmp |= AES_MR_CKEY(data); + ((Aes *)hw)->AES_MR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_CKEY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~AES_MR_CKEY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_CKEY_bf(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= AES_MR_CKEY(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_CKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp = (tmp & AES_MR_CKEY_Msk) >> AES_MR_CKEY_Pos; + return tmp; +} + +static inline void hri_aes_set_MR_reg(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_get_MR_reg(const void *const hw, hri_aes_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_MR_reg(const void *const hw, hri_aes_mr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_MR_reg(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_MR_reg(const void *const hw, hri_aes_mr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_MR ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_mr_reg_t hri_aes_read_MR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_MR; +} + +static inline void hri_aes_set_AADLENR_AADLEN_bf(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR |= AES_AADLENR_AADLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_aadlenr_reg_t hri_aes_get_AADLENR_AADLEN_bf(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_AADLENR; + tmp = (tmp & AES_AADLENR_AADLEN(mask)) >> AES_AADLENR_AADLEN_Pos; + return tmp; +} + +static inline void hri_aes_write_AADLENR_AADLEN_bf(const void *const hw, hri_aes_aadlenr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_AADLENR; + tmp &= ~AES_AADLENR_AADLEN_Msk; + tmp |= AES_AADLENR_AADLEN(data); + ((Aes *)hw)->AES_AADLENR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_AADLENR_AADLEN_bf(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR &= ~AES_AADLENR_AADLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_AADLENR_AADLEN_bf(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR ^= AES_AADLENR_AADLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_aadlenr_reg_t hri_aes_read_AADLENR_AADLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_AADLENR; + tmp = (tmp & AES_AADLENR_AADLEN_Msk) >> AES_AADLENR_AADLEN_Pos; + return tmp; +} + +static inline void hri_aes_set_AADLENR_reg(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_aadlenr_reg_t hri_aes_get_AADLENR_reg(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_AADLENR; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_AADLENR_reg(const void *const hw, hri_aes_aadlenr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_AADLENR_reg(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_AADLENR_reg(const void *const hw, hri_aes_aadlenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_AADLENR ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_aadlenr_reg_t hri_aes_read_AADLENR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_AADLENR; +} + +static inline void hri_aes_set_CLENR_CLEN_bf(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR |= AES_CLENR_CLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_clenr_reg_t hri_aes_get_CLENR_CLEN_bf(const void *const hw, hri_aes_clenr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_CLENR; + tmp = (tmp & AES_CLENR_CLEN(mask)) >> AES_CLENR_CLEN_Pos; + return tmp; +} + +static inline void hri_aes_write_CLENR_CLEN_bf(const void *const hw, hri_aes_clenr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_CLENR; + tmp &= ~AES_CLENR_CLEN_Msk; + tmp |= AES_CLENR_CLEN(data); + ((Aes *)hw)->AES_CLENR = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CLENR_CLEN_bf(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR &= ~AES_CLENR_CLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CLENR_CLEN_bf(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR ^= AES_CLENR_CLEN(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_clenr_reg_t hri_aes_read_CLENR_CLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_CLENR; + tmp = (tmp & AES_CLENR_CLEN_Msk) >> AES_CLENR_CLEN_Pos; + return tmp; +} + +static inline void hri_aes_set_CLENR_reg(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_clenr_reg_t hri_aes_get_CLENR_reg(const void *const hw, hri_aes_clenr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_CLENR; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CLENR_reg(const void *const hw, hri_aes_clenr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CLENR_reg(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CLENR_reg(const void *const hw, hri_aes_clenr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CLENR ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_clenr_reg_t hri_aes_read_CLENR_reg(const void *const hw) +{ + return ((Aes *)hw)->AES_CLENR; +} + +static inline void hri_aes_set_GHASHR_GHASH_bf(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] |= AES_GHASHR_GHASH(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghashr_reg_t hri_aes_get_GHASHR_GHASH_bf(const void *const hw, uint8_t index, + hri_aes_ghashr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GHASHR[index]; + tmp = (tmp & AES_GHASHR_GHASH(mask)) >> AES_GHASHR_GHASH_Pos; + return tmp; +} + +static inline void hri_aes_write_GHASHR_GHASH_bf(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_GHASHR[index]; + tmp &= ~AES_GHASHR_GHASH_Msk; + tmp |= AES_GHASHR_GHASH(data); + ((Aes *)hw)->AES_GHASHR[index] = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASHR_GHASH_bf(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] &= ~AES_GHASHR_GHASH(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASHR_GHASH_bf(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] ^= AES_GHASHR_GHASH(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghashr_reg_t hri_aes_read_GHASHR_GHASH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GHASHR[index]; + tmp = (tmp & AES_GHASHR_GHASH_Msk) >> AES_GHASHR_GHASH_Pos; + return tmp; +} + +static inline void hri_aes_set_GHASHR_reg(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghashr_reg_t hri_aes_get_GHASHR_reg(const void *const hw, uint8_t index, + hri_aes_ghashr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GHASHR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASHR_reg(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASHR_reg(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASHR_reg(const void *const hw, uint8_t index, hri_aes_ghashr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GHASHR[index] ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghashr_reg_t hri_aes_read_GHASHR_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->AES_GHASHR[index]; +} + +static inline void hri_aes_set_GCMHR_H_bf(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] |= AES_GCMHR_H(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_gcmhr_reg_t hri_aes_get_GCMHR_H_bf(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GCMHR[index]; + tmp = (tmp & AES_GCMHR_H(mask)) >> AES_GCMHR_H_Pos; + return tmp; +} + +static inline void hri_aes_write_GCMHR_H_bf(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->AES_GCMHR[index]; + tmp &= ~AES_GCMHR_H_Msk; + tmp |= AES_GCMHR_H(data); + ((Aes *)hw)->AES_GCMHR[index] = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GCMHR_H_bf(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] &= ~AES_GCMHR_H(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GCMHR_H_bf(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] ^= AES_GCMHR_H(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_gcmhr_reg_t hri_aes_read_GCMHR_H_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GCMHR[index]; + tmp = (tmp & AES_GCMHR_H_Msk) >> AES_GCMHR_H_Pos; + return tmp; +} + +static inline void hri_aes_set_GCMHR_reg(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_gcmhr_reg_t hri_aes_get_GCMHR_reg(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->AES_GCMHR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GCMHR_reg(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GCMHR_reg(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GCMHR_reg(const void *const hw, uint8_t index, hri_aes_gcmhr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_GCMHR[index] ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_gcmhr_reg_t hri_aes_read_GCMHR_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->AES_GCMHR[index]; +} + +static inline void hri_aes_write_CR_reg(const void *const hw, hri_aes_cr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_CR = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_KEYWR_reg(const void *const hw, uint8_t index, hri_aes_keywr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_KEYWR[index] = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_IDATAR_reg(const void *const hw, uint8_t index, hri_aes_idatar_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_IDATAR[index] = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_IVR_reg(const void *const hw, uint8_t index, hri_aes_ivr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->AES_IVR[index] = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_E70B_H_INCLUDED */ +#endif /* _SAME70_AES_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_afec_e70b.h b/bsp/microchip/same70/bsp/hri/hri_afec_e70b.h new file mode 100644 index 0000000000..81b972bffb --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_afec_e70b.h @@ -0,0 +1,5929 @@ +/** + * \file + * + * \brief SAM AFEC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_AFEC_COMPONENT_ +#ifndef _HRI_AFEC_E70B_H_INCLUDED_ +#define _HRI_AFEC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AFEC_CRITICAL_SECTIONS) +#define AFEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AFEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AFEC_CRITICAL_SECTION_ENTER() +#define AFEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_afec_acr_reg_t; +typedef uint32_t hri_afec_cdr_reg_t; +typedef uint32_t hri_afec_cecr_reg_t; +typedef uint32_t hri_afec_cgr_reg_t; +typedef uint32_t hri_afec_chsr_reg_t; +typedef uint32_t hri_afec_cocr_reg_t; +typedef uint32_t hri_afec_cosr_reg_t; +typedef uint32_t hri_afec_cr_reg_t; +typedef uint32_t hri_afec_cselr_reg_t; +typedef uint32_t hri_afec_cvr_reg_t; +typedef uint32_t hri_afec_cwr_reg_t; +typedef uint32_t hri_afec_diffr_reg_t; +typedef uint32_t hri_afec_emr_reg_t; +typedef uint32_t hri_afec_imr_reg_t; +typedef uint32_t hri_afec_isr_reg_t; +typedef uint32_t hri_afec_lcdr_reg_t; +typedef uint32_t hri_afec_mr_reg_t; +typedef uint32_t hri_afec_over_reg_t; +typedef uint32_t hri_afec_seq1r_reg_t; +typedef uint32_t hri_afec_seq2r_reg_t; +typedef uint32_t hri_afec_shmr_reg_t; +typedef uint32_t hri_afec_tempcwr_reg_t; +typedef uint32_t hri_afec_tempmr_reg_t; +typedef uint32_t hri_afec_wpmr_reg_t; +typedef uint32_t hri_afec_wpsr_reg_t; + +static inline bool hri_afec_get_ISR_EOC0_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC0) >> AFEC_ISR_EOC0_Pos; +} + +static inline bool hri_afec_get_ISR_EOC1_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC1) >> AFEC_ISR_EOC1_Pos; +} + +static inline bool hri_afec_get_ISR_EOC2_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC2) >> AFEC_ISR_EOC2_Pos; +} + +static inline bool hri_afec_get_ISR_EOC3_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC3) >> AFEC_ISR_EOC3_Pos; +} + +static inline bool hri_afec_get_ISR_EOC4_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC4) >> AFEC_ISR_EOC4_Pos; +} + +static inline bool hri_afec_get_ISR_EOC5_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC5) >> AFEC_ISR_EOC5_Pos; +} + +static inline bool hri_afec_get_ISR_EOC6_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC6) >> AFEC_ISR_EOC6_Pos; +} + +static inline bool hri_afec_get_ISR_EOC7_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC7) >> AFEC_ISR_EOC7_Pos; +} + +static inline bool hri_afec_get_ISR_EOC8_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC8) >> AFEC_ISR_EOC8_Pos; +} + +static inline bool hri_afec_get_ISR_EOC9_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC9) >> AFEC_ISR_EOC9_Pos; +} + +static inline bool hri_afec_get_ISR_EOC10_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC10) >> AFEC_ISR_EOC10_Pos; +} + +static inline bool hri_afec_get_ISR_EOC11_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_EOC11) >> AFEC_ISR_EOC11_Pos; +} + +static inline bool hri_afec_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_DRDY) >> AFEC_ISR_DRDY_Pos; +} + +static inline bool hri_afec_get_ISR_GOVRE_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_GOVRE) >> AFEC_ISR_GOVRE_Pos; +} + +static inline bool hri_afec_get_ISR_COMPE_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_COMPE) >> AFEC_ISR_COMPE_Pos; +} + +static inline bool hri_afec_get_ISR_TEMPCHG_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_ISR & AFEC_ISR_TEMPCHG) >> AFEC_ISR_TEMPCHG_Pos; +} + +static inline hri_afec_isr_reg_t hri_afec_get_ISR_reg(const void *const hw, hri_afec_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_isr_reg_t hri_afec_read_ISR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_ISR; +} + +static inline void hri_afec_set_CHSR_CH0_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH0; +} + +static inline bool hri_afec_get_CHSR_CH0_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH0) >> AFEC_CHSR_CH0_Pos; +} + +static inline void hri_afec_write_CHSR_CH0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH0; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH0; + } +} + +static inline void hri_afec_clear_CHSR_CH0_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH0; +} + +static inline void hri_afec_set_CHSR_CH1_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH1; +} + +static inline bool hri_afec_get_CHSR_CH1_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH1) >> AFEC_CHSR_CH1_Pos; +} + +static inline void hri_afec_write_CHSR_CH1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH1; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH1; + } +} + +static inline void hri_afec_clear_CHSR_CH1_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH1; +} + +static inline void hri_afec_set_CHSR_CH2_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH2; +} + +static inline bool hri_afec_get_CHSR_CH2_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH2) >> AFEC_CHSR_CH2_Pos; +} + +static inline void hri_afec_write_CHSR_CH2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH2; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH2; + } +} + +static inline void hri_afec_clear_CHSR_CH2_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH2; +} + +static inline void hri_afec_set_CHSR_CH3_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH3; +} + +static inline bool hri_afec_get_CHSR_CH3_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH3) >> AFEC_CHSR_CH3_Pos; +} + +static inline void hri_afec_write_CHSR_CH3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH3; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH3; + } +} + +static inline void hri_afec_clear_CHSR_CH3_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH3; +} + +static inline void hri_afec_set_CHSR_CH4_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH4; +} + +static inline bool hri_afec_get_CHSR_CH4_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH4) >> AFEC_CHSR_CH4_Pos; +} + +static inline void hri_afec_write_CHSR_CH4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH4; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH4; + } +} + +static inline void hri_afec_clear_CHSR_CH4_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH4; +} + +static inline void hri_afec_set_CHSR_CH5_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH5; +} + +static inline bool hri_afec_get_CHSR_CH5_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH5) >> AFEC_CHSR_CH5_Pos; +} + +static inline void hri_afec_write_CHSR_CH5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH5; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH5; + } +} + +static inline void hri_afec_clear_CHSR_CH5_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH5; +} + +static inline void hri_afec_set_CHSR_CH6_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH6; +} + +static inline bool hri_afec_get_CHSR_CH6_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH6) >> AFEC_CHSR_CH6_Pos; +} + +static inline void hri_afec_write_CHSR_CH6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH6; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH6; + } +} + +static inline void hri_afec_clear_CHSR_CH6_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH6; +} + +static inline void hri_afec_set_CHSR_CH7_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH7; +} + +static inline bool hri_afec_get_CHSR_CH7_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH7) >> AFEC_CHSR_CH7_Pos; +} + +static inline void hri_afec_write_CHSR_CH7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH7; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH7; + } +} + +static inline void hri_afec_clear_CHSR_CH7_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH7; +} + +static inline void hri_afec_set_CHSR_CH8_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH8; +} + +static inline bool hri_afec_get_CHSR_CH8_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH8) >> AFEC_CHSR_CH8_Pos; +} + +static inline void hri_afec_write_CHSR_CH8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH8; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH8; + } +} + +static inline void hri_afec_clear_CHSR_CH8_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH8; +} + +static inline void hri_afec_set_CHSR_CH9_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH9; +} + +static inline bool hri_afec_get_CHSR_CH9_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH9) >> AFEC_CHSR_CH9_Pos; +} + +static inline void hri_afec_write_CHSR_CH9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH9; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH9; + } +} + +static inline void hri_afec_clear_CHSR_CH9_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH9; +} + +static inline void hri_afec_set_CHSR_CH10_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH10; +} + +static inline bool hri_afec_get_CHSR_CH10_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH10) >> AFEC_CHSR_CH10_Pos; +} + +static inline void hri_afec_write_CHSR_CH10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH10; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH10; + } +} + +static inline void hri_afec_clear_CHSR_CH10_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH10; +} + +static inline void hri_afec_set_CHSR_CH11_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH11; +} + +static inline bool hri_afec_get_CHSR_CH11_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CHSR & AFEC_CHSR_CH11) >> AFEC_CHSR_CH11_Pos; +} + +static inline void hri_afec_write_CHSR_CH11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH11; + } else { + ((Afec *)hw)->AFEC_CHER = AFEC_CHSR_CH11; + } +} + +static inline void hri_afec_clear_CHSR_CH11_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_CHDR = AFEC_CHSR_CH11; +} + +static inline void hri_afec_set_CHSR_reg(const void *const hw, hri_afec_chsr_reg_t mask) +{ + ((Afec *)hw)->AFEC_CHER = mask; +} + +static inline hri_afec_chsr_reg_t hri_afec_get_CHSR_reg(const void *const hw, hri_afec_chsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CHSR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_chsr_reg_t hri_afec_read_CHSR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CHSR; +} + +static inline void hri_afec_write_CHSR_reg(const void *const hw, hri_afec_chsr_reg_t data) +{ + ((Afec *)hw)->AFEC_CHER = data; + ((Afec *)hw)->AFEC_CHDR = ~data; +} + +static inline void hri_afec_clear_CHSR_reg(const void *const hw, hri_afec_chsr_reg_t mask) +{ + ((Afec *)hw)->AFEC_CHDR = mask; +} + +static inline void hri_afec_set_IMR_EOC0_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC0; +} + +static inline bool hri_afec_get_IMR_EOC0_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC0) >> AFEC_IMR_EOC0_Pos; +} + +static inline void hri_afec_write_IMR_EOC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC0; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC0; + } +} + +static inline void hri_afec_clear_IMR_EOC0_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC0; +} + +static inline void hri_afec_set_IMR_EOC1_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC1; +} + +static inline bool hri_afec_get_IMR_EOC1_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC1) >> AFEC_IMR_EOC1_Pos; +} + +static inline void hri_afec_write_IMR_EOC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC1; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC1; + } +} + +static inline void hri_afec_clear_IMR_EOC1_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC1; +} + +static inline void hri_afec_set_IMR_EOC2_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC2; +} + +static inline bool hri_afec_get_IMR_EOC2_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC2) >> AFEC_IMR_EOC2_Pos; +} + +static inline void hri_afec_write_IMR_EOC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC2; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC2; + } +} + +static inline void hri_afec_clear_IMR_EOC2_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC2; +} + +static inline void hri_afec_set_IMR_EOC3_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC3; +} + +static inline bool hri_afec_get_IMR_EOC3_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC3) >> AFEC_IMR_EOC3_Pos; +} + +static inline void hri_afec_write_IMR_EOC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC3; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC3; + } +} + +static inline void hri_afec_clear_IMR_EOC3_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC3; +} + +static inline void hri_afec_set_IMR_EOC4_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC4; +} + +static inline bool hri_afec_get_IMR_EOC4_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC4) >> AFEC_IMR_EOC4_Pos; +} + +static inline void hri_afec_write_IMR_EOC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC4; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC4; + } +} + +static inline void hri_afec_clear_IMR_EOC4_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC4; +} + +static inline void hri_afec_set_IMR_EOC5_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC5; +} + +static inline bool hri_afec_get_IMR_EOC5_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC5) >> AFEC_IMR_EOC5_Pos; +} + +static inline void hri_afec_write_IMR_EOC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC5; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC5; + } +} + +static inline void hri_afec_clear_IMR_EOC5_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC5; +} + +static inline void hri_afec_set_IMR_EOC6_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC6; +} + +static inline bool hri_afec_get_IMR_EOC6_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC6) >> AFEC_IMR_EOC6_Pos; +} + +static inline void hri_afec_write_IMR_EOC6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC6; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC6; + } +} + +static inline void hri_afec_clear_IMR_EOC6_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC6; +} + +static inline void hri_afec_set_IMR_EOC7_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC7; +} + +static inline bool hri_afec_get_IMR_EOC7_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC7) >> AFEC_IMR_EOC7_Pos; +} + +static inline void hri_afec_write_IMR_EOC7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC7; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC7; + } +} + +static inline void hri_afec_clear_IMR_EOC7_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC7; +} + +static inline void hri_afec_set_IMR_EOC8_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC8; +} + +static inline bool hri_afec_get_IMR_EOC8_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC8) >> AFEC_IMR_EOC8_Pos; +} + +static inline void hri_afec_write_IMR_EOC8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC8; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC8; + } +} + +static inline void hri_afec_clear_IMR_EOC8_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC8; +} + +static inline void hri_afec_set_IMR_EOC9_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC9; +} + +static inline bool hri_afec_get_IMR_EOC9_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC9) >> AFEC_IMR_EOC9_Pos; +} + +static inline void hri_afec_write_IMR_EOC9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC9; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC9; + } +} + +static inline void hri_afec_clear_IMR_EOC9_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC9; +} + +static inline void hri_afec_set_IMR_EOC10_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC10; +} + +static inline bool hri_afec_get_IMR_EOC10_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC10) >> AFEC_IMR_EOC10_Pos; +} + +static inline void hri_afec_write_IMR_EOC10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC10; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC10; + } +} + +static inline void hri_afec_clear_IMR_EOC10_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC10; +} + +static inline void hri_afec_set_IMR_EOC11_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC11; +} + +static inline bool hri_afec_get_IMR_EOC11_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_EOC11) >> AFEC_IMR_EOC11_Pos; +} + +static inline void hri_afec_write_IMR_EOC11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC11; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_EOC11; + } +} + +static inline void hri_afec_clear_IMR_EOC11_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_EOC11; +} + +static inline void hri_afec_set_IMR_DRDY_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_DRDY; +} + +static inline bool hri_afec_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_DRDY) >> AFEC_IMR_DRDY_Pos; +} + +static inline void hri_afec_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_DRDY; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_DRDY; + } +} + +static inline void hri_afec_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_DRDY; +} + +static inline void hri_afec_set_IMR_GOVRE_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_GOVRE; +} + +static inline bool hri_afec_get_IMR_GOVRE_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_GOVRE) >> AFEC_IMR_GOVRE_Pos; +} + +static inline void hri_afec_write_IMR_GOVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_GOVRE; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_GOVRE; + } +} + +static inline void hri_afec_clear_IMR_GOVRE_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_GOVRE; +} + +static inline void hri_afec_set_IMR_COMPE_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_COMPE; +} + +static inline bool hri_afec_get_IMR_COMPE_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_COMPE) >> AFEC_IMR_COMPE_Pos; +} + +static inline void hri_afec_write_IMR_COMPE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_COMPE; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_COMPE; + } +} + +static inline void hri_afec_clear_IMR_COMPE_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_COMPE; +} + +static inline void hri_afec_set_IMR_TEMPCHG_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IER = AFEC_IMR_TEMPCHG; +} + +static inline bool hri_afec_get_IMR_TEMPCHG_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_IMR & AFEC_IMR_TEMPCHG) >> AFEC_IMR_TEMPCHG_Pos; +} + +static inline void hri_afec_write_IMR_TEMPCHG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_TEMPCHG; + } else { + ((Afec *)hw)->AFEC_IER = AFEC_IMR_TEMPCHG; + } +} + +static inline void hri_afec_clear_IMR_TEMPCHG_bit(const void *const hw) +{ + ((Afec *)hw)->AFEC_IDR = AFEC_IMR_TEMPCHG; +} + +static inline void hri_afec_set_IMR_reg(const void *const hw, hri_afec_imr_reg_t mask) +{ + ((Afec *)hw)->AFEC_IER = mask; +} + +static inline hri_afec_imr_reg_t hri_afec_get_IMR_reg(const void *const hw, hri_afec_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_imr_reg_t hri_afec_read_IMR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_IMR; +} + +static inline void hri_afec_write_IMR_reg(const void *const hw, hri_afec_imr_reg_t data) +{ + ((Afec *)hw)->AFEC_IER = data; + ((Afec *)hw)->AFEC_IDR = ~data; +} + +static inline void hri_afec_clear_IMR_reg(const void *const hw, hri_afec_imr_reg_t mask) +{ + ((Afec *)hw)->AFEC_IDR = mask; +} + +static inline hri_afec_lcdr_reg_t hri_afec_get_LCDR_LDATA_bf(const void *const hw, hri_afec_lcdr_reg_t mask) +{ + return (((Afec *)hw)->AFEC_LCDR & AFEC_LCDR_LDATA(mask)) >> AFEC_LCDR_LDATA_Pos; +} + +static inline hri_afec_lcdr_reg_t hri_afec_read_LCDR_LDATA_bf(const void *const hw) +{ + return (((Afec *)hw)->AFEC_LCDR & AFEC_LCDR_LDATA_Msk) >> AFEC_LCDR_LDATA_Pos; +} + +static inline hri_afec_lcdr_reg_t hri_afec_get_LCDR_CHNB_bf(const void *const hw, hri_afec_lcdr_reg_t mask) +{ + return (((Afec *)hw)->AFEC_LCDR & AFEC_LCDR_CHNB(mask)) >> AFEC_LCDR_CHNB_Pos; +} + +static inline hri_afec_lcdr_reg_t hri_afec_read_LCDR_CHNB_bf(const void *const hw) +{ + return (((Afec *)hw)->AFEC_LCDR & AFEC_LCDR_CHNB_Msk) >> AFEC_LCDR_CHNB_Pos; +} + +static inline hri_afec_lcdr_reg_t hri_afec_get_LCDR_reg(const void *const hw, hri_afec_lcdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_LCDR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_lcdr_reg_t hri_afec_read_LCDR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_LCDR; +} + +static inline bool hri_afec_get_OVER_OVRE0_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE0) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE1_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE1) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE2_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE2) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE3_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE3) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE4_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE4) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE5_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE5) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE6_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE6) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE7_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE7) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE8_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE8) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE9_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE9) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE10_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE10) > 0; +} + +static inline bool hri_afec_get_OVER_OVRE11_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_OVER & AFEC_OVER_OVRE11) > 0; +} + +static inline hri_afec_over_reg_t hri_afec_get_OVER_reg(const void *const hw, hri_afec_over_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_OVER; + tmp &= mask; + return tmp; +} + +static inline hri_afec_over_reg_t hri_afec_read_OVER_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_OVER; +} + +static inline hri_afec_cdr_reg_t hri_afec_get_CDR_DATA_bf(const void *const hw, hri_afec_cdr_reg_t mask) +{ + return (((Afec *)hw)->AFEC_CDR & AFEC_CDR_DATA(mask)) >> AFEC_CDR_DATA_Pos; +} + +static inline hri_afec_cdr_reg_t hri_afec_read_CDR_DATA_bf(const void *const hw) +{ + return (((Afec *)hw)->AFEC_CDR & AFEC_CDR_DATA_Msk) >> AFEC_CDR_DATA_Pos; +} + +static inline hri_afec_cdr_reg_t hri_afec_get_CDR_reg(const void *const hw, hri_afec_cdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CDR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_cdr_reg_t hri_afec_read_CDR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CDR; +} + +static inline bool hri_afec_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Afec *)hw)->AFEC_WPSR & AFEC_WPSR_WPVS) > 0; +} + +static inline hri_afec_wpsr_reg_t hri_afec_get_WPSR_WPVSRC_bf(const void *const hw, hri_afec_wpsr_reg_t mask) +{ + return (((Afec *)hw)->AFEC_WPSR & AFEC_WPSR_WPVSRC(mask)) >> AFEC_WPSR_WPVSRC_Pos; +} + +static inline hri_afec_wpsr_reg_t hri_afec_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Afec *)hw)->AFEC_WPSR & AFEC_WPSR_WPVSRC_Msk) >> AFEC_WPSR_WPVSRC_Pos; +} + +static inline hri_afec_wpsr_reg_t hri_afec_get_WPSR_reg(const void *const hw, hri_afec_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_afec_wpsr_reg_t hri_afec_read_WPSR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_WPSR; +} + +static inline void hri_afec_set_MR_TRGEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_TRGEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_TRGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRGEN) >> AFEC_MR_TRGEN_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_TRGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_TRGEN; + tmp |= value << AFEC_MR_TRGEN_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_TRGEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_TRGEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_TRGEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_TRGEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_SLEEP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_SLEEP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_SLEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_SLEEP) >> AFEC_MR_SLEEP_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_SLEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_SLEEP; + tmp |= value << AFEC_MR_SLEEP_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_SLEEP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_SLEEP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_SLEEP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_SLEEP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_FWUP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_FWUP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_FWUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_FWUP) >> AFEC_MR_FWUP_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_FWUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_FWUP; + tmp |= value << AFEC_MR_FWUP_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_FWUP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_FWUP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_FWUP_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_FWUP; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_FREERUN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_FREERUN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_FREERUN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_FREERUN) >> AFEC_MR_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_FREERUN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_FREERUN; + tmp |= value << AFEC_MR_FREERUN_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_FREERUN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_FREERUN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_FREERUN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_FREERUN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_ONE_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_ONE; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_ONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_ONE) >> AFEC_MR_ONE_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_ONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_ONE; + tmp |= value << AFEC_MR_ONE_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_ONE_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_ONE; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_ONE_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_ONE; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_USEQ_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_USEQ; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_MR_USEQ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_USEQ) >> AFEC_MR_USEQ_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_MR_USEQ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_USEQ; + tmp |= value << AFEC_MR_USEQ_Pos; + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_USEQ_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_USEQ; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_USEQ_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_USEQ; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_MR_TRGSEL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_TRGSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_TRGSEL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRGSEL(mask)) >> AFEC_MR_TRGSEL_Pos; + return tmp; +} + +static inline void hri_afec_write_MR_TRGSEL_bf(const void *const hw, hri_afec_mr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_TRGSEL_Msk; + tmp |= AFEC_MR_TRGSEL(data); + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_TRGSEL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_TRGSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_TRGSEL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_TRGSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_TRGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRGSEL_Msk) >> AFEC_MR_TRGSEL_Pos; + return tmp; +} + +static inline void hri_afec_set_MR_PRESCAL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_PRESCAL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_PRESCAL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_PRESCAL(mask)) >> AFEC_MR_PRESCAL_Pos; + return tmp; +} + +static inline void hri_afec_write_MR_PRESCAL_bf(const void *const hw, hri_afec_mr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_PRESCAL_Msk; + tmp |= AFEC_MR_PRESCAL(data); + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_PRESCAL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_PRESCAL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_PRESCAL_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_PRESCAL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_PRESCAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_PRESCAL_Msk) >> AFEC_MR_PRESCAL_Pos; + return tmp; +} + +static inline void hri_afec_set_MR_STARTUP_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_STARTUP(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_STARTUP_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_STARTUP(mask)) >> AFEC_MR_STARTUP_Pos; + return tmp; +} + +static inline void hri_afec_write_MR_STARTUP_bf(const void *const hw, hri_afec_mr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_STARTUP_Msk; + tmp |= AFEC_MR_STARTUP(data); + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_STARTUP_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_STARTUP(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_STARTUP_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_STARTUP(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_STARTUP_Msk) >> AFEC_MR_STARTUP_Pos; + return tmp; +} + +static inline void hri_afec_set_MR_TRACKTIM_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_TRACKTIM(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_TRACKTIM_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRACKTIM(mask)) >> AFEC_MR_TRACKTIM_Pos; + return tmp; +} + +static inline void hri_afec_write_MR_TRACKTIM_bf(const void *const hw, hri_afec_mr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_TRACKTIM_Msk; + tmp |= AFEC_MR_TRACKTIM(data); + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_TRACKTIM_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_TRACKTIM(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_TRACKTIM_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_TRACKTIM(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_TRACKTIM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRACKTIM_Msk) >> AFEC_MR_TRACKTIM_Pos; + return tmp; +} + +static inline void hri_afec_set_MR_TRANSFER_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= AFEC_MR_TRANSFER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_TRANSFER_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRANSFER(mask)) >> AFEC_MR_TRANSFER_Pos; + return tmp; +} + +static inline void hri_afec_write_MR_TRANSFER_bf(const void *const hw, hri_afec_mr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= ~AFEC_MR_TRANSFER_Msk; + tmp |= AFEC_MR_TRANSFER(data); + ((Afec *)hw)->AFEC_MR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_TRANSFER_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~AFEC_MR_TRANSFER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_TRANSFER_bf(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= AFEC_MR_TRANSFER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_TRANSFER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp = (tmp & AFEC_MR_TRANSFER_Msk) >> AFEC_MR_TRANSFER_Pos; + return tmp; +} + +static inline void hri_afec_set_MR_reg(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_get_MR_reg(const void *const hw, hri_afec_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_MR_reg(const void *const hw, hri_afec_mr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_MR_reg(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_MR_reg(const void *const hw, hri_afec_mr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_MR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_mr_reg_t hri_afec_read_MR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_MR; +} + +static inline void hri_afec_set_EMR_CMPALL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_CMPALL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_EMR_CMPALL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPALL) >> AFEC_EMR_CMPALL_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_EMR_CMPALL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_CMPALL; + tmp |= value << AFEC_EMR_CMPALL_Pos; + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_CMPALL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_CMPALL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_CMPALL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_CMPALL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_EMR_TAG_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_TAG; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_EMR_TAG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_TAG) >> AFEC_EMR_TAG_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_EMR_TAG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_TAG; + tmp |= value << AFEC_EMR_TAG_Pos; + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_TAG_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_TAG; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_TAG_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_TAG; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_EMR_STM_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_STM; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_EMR_STM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_STM) >> AFEC_EMR_STM_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_EMR_STM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_STM; + tmp |= value << AFEC_EMR_STM_Pos; + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_STM_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_STM; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_STM_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_STM; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_EMR_CMPMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_CMPMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_CMPMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPMODE(mask)) >> AFEC_EMR_CMPMODE_Pos; + return tmp; +} + +static inline void hri_afec_write_EMR_CMPMODE_bf(const void *const hw, hri_afec_emr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_CMPMODE_Msk; + tmp |= AFEC_EMR_CMPMODE(data); + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_CMPMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_CMPMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_CMPMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_CMPMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_CMPMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPMODE_Msk) >> AFEC_EMR_CMPMODE_Pos; + return tmp; +} + +static inline void hri_afec_set_EMR_CMPSEL_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_CMPSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_CMPSEL_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPSEL(mask)) >> AFEC_EMR_CMPSEL_Pos; + return tmp; +} + +static inline void hri_afec_write_EMR_CMPSEL_bf(const void *const hw, hri_afec_emr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_CMPSEL_Msk; + tmp |= AFEC_EMR_CMPSEL(data); + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_CMPSEL_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_CMPSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_CMPSEL_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_CMPSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_CMPSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPSEL_Msk) >> AFEC_EMR_CMPSEL_Pos; + return tmp; +} + +static inline void hri_afec_set_EMR_CMPFILTER_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_CMPFILTER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_CMPFILTER_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPFILTER(mask)) >> AFEC_EMR_CMPFILTER_Pos; + return tmp; +} + +static inline void hri_afec_write_EMR_CMPFILTER_bf(const void *const hw, hri_afec_emr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_CMPFILTER_Msk; + tmp |= AFEC_EMR_CMPFILTER(data); + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_CMPFILTER_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_CMPFILTER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_CMPFILTER_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_CMPFILTER(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_CMPFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_CMPFILTER_Msk) >> AFEC_EMR_CMPFILTER_Pos; + return tmp; +} + +static inline void hri_afec_set_EMR_RES_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_RES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_RES_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_RES(mask)) >> AFEC_EMR_RES_Pos; + return tmp; +} + +static inline void hri_afec_write_EMR_RES_bf(const void *const hw, hri_afec_emr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_RES_Msk; + tmp |= AFEC_EMR_RES(data); + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_RES_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_RES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_RES_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_RES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_RES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_RES_Msk) >> AFEC_EMR_RES_Pos; + return tmp; +} + +static inline void hri_afec_set_EMR_SIGNMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= AFEC_EMR_SIGNMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_SIGNMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_SIGNMODE(mask)) >> AFEC_EMR_SIGNMODE_Pos; + return tmp; +} + +static inline void hri_afec_write_EMR_SIGNMODE_bf(const void *const hw, hri_afec_emr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= ~AFEC_EMR_SIGNMODE_Msk; + tmp |= AFEC_EMR_SIGNMODE(data); + ((Afec *)hw)->AFEC_EMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_SIGNMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~AFEC_EMR_SIGNMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_SIGNMODE_bf(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= AFEC_EMR_SIGNMODE(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_SIGNMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp = (tmp & AFEC_EMR_SIGNMODE_Msk) >> AFEC_EMR_SIGNMODE_Pos; + return tmp; +} + +static inline void hri_afec_set_EMR_reg(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_get_EMR_reg(const void *const hw, hri_afec_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_EMR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_EMR_reg(const void *const hw, hri_afec_emr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_EMR_reg(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_EMR_reg(const void *const hw, hri_afec_emr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_EMR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_emr_reg_t hri_afec_read_EMR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_EMR; +} + +static inline void hri_afec_set_SEQ1R_USCH0_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH0_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH0(mask)) >> AFEC_SEQ1R_USCH0_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH0_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH0_Msk; + tmp |= AFEC_SEQ1R_USCH0(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH0_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH0_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH0_Msk) >> AFEC_SEQ1R_USCH0_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH1_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH1_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH1(mask)) >> AFEC_SEQ1R_USCH1_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH1_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH1_Msk; + tmp |= AFEC_SEQ1R_USCH1(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH1_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH1_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH1_Msk) >> AFEC_SEQ1R_USCH1_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH2_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH2_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH2(mask)) >> AFEC_SEQ1R_USCH2_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH2_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH2_Msk; + tmp |= AFEC_SEQ1R_USCH2(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH2_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH2_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH2_Msk) >> AFEC_SEQ1R_USCH2_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH3_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH3_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH3(mask)) >> AFEC_SEQ1R_USCH3_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH3_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH3_Msk; + tmp |= AFEC_SEQ1R_USCH3(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH3_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH3_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH3_Msk) >> AFEC_SEQ1R_USCH3_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH4_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH4_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH4(mask)) >> AFEC_SEQ1R_USCH4_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH4_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH4_Msk; + tmp |= AFEC_SEQ1R_USCH4(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH4_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH4_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH4_Msk) >> AFEC_SEQ1R_USCH4_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH5_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH5_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH5(mask)) >> AFEC_SEQ1R_USCH5_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH5_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH5_Msk; + tmp |= AFEC_SEQ1R_USCH5(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH5_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH5_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH5_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH5_Msk) >> AFEC_SEQ1R_USCH5_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH6_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH6_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH6(mask)) >> AFEC_SEQ1R_USCH6_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH6_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH6_Msk; + tmp |= AFEC_SEQ1R_USCH6(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH6_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH6_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH6_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH6_Msk) >> AFEC_SEQ1R_USCH6_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_USCH7_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= AFEC_SEQ1R_USCH7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_USCH7_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH7(mask)) >> AFEC_SEQ1R_USCH7_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_USCH7_bf(const void *const hw, hri_afec_seq1r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= ~AFEC_SEQ1R_USCH7_Msk; + tmp |= AFEC_SEQ1R_USCH7(data); + ((Afec *)hw)->AFEC_SEQ1R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_USCH7_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~AFEC_SEQ1R_USCH7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_USCH7_bf(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= AFEC_SEQ1R_USCH7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_USCH7_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp = (tmp & AFEC_SEQ1R_USCH7_Msk) >> AFEC_SEQ1R_USCH7_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ1R_reg(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_get_SEQ1R_reg(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ1R; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_SEQ1R_reg(const void *const hw, hri_afec_seq1r_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ1R_reg(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ1R_reg(const void *const hw, hri_afec_seq1r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ1R ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq1r_reg_t hri_afec_read_SEQ1R_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_SEQ1R; +} + +static inline void hri_afec_set_SEQ2R_USCH8_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R |= AFEC_SEQ2R_USCH8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_get_SEQ2R_USCH8_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH8(mask)) >> AFEC_SEQ2R_USCH8_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ2R_USCH8_bf(const void *const hw, hri_afec_seq2r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp &= ~AFEC_SEQ2R_USCH8_Msk; + tmp |= AFEC_SEQ2R_USCH8(data); + ((Afec *)hw)->AFEC_SEQ2R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ2R_USCH8_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R &= ~AFEC_SEQ2R_USCH8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ2R_USCH8_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R ^= AFEC_SEQ2R_USCH8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_read_SEQ2R_USCH8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH8_Msk) >> AFEC_SEQ2R_USCH8_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ2R_USCH9_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R |= AFEC_SEQ2R_USCH9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_get_SEQ2R_USCH9_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH9(mask)) >> AFEC_SEQ2R_USCH9_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ2R_USCH9_bf(const void *const hw, hri_afec_seq2r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp &= ~AFEC_SEQ2R_USCH9_Msk; + tmp |= AFEC_SEQ2R_USCH9(data); + ((Afec *)hw)->AFEC_SEQ2R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ2R_USCH9_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R &= ~AFEC_SEQ2R_USCH9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ2R_USCH9_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R ^= AFEC_SEQ2R_USCH9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_read_SEQ2R_USCH9_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH9_Msk) >> AFEC_SEQ2R_USCH9_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ2R_USCH10_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R |= AFEC_SEQ2R_USCH10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_get_SEQ2R_USCH10_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH10(mask)) >> AFEC_SEQ2R_USCH10_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ2R_USCH10_bf(const void *const hw, hri_afec_seq2r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp &= ~AFEC_SEQ2R_USCH10_Msk; + tmp |= AFEC_SEQ2R_USCH10(data); + ((Afec *)hw)->AFEC_SEQ2R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ2R_USCH10_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R &= ~AFEC_SEQ2R_USCH10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ2R_USCH10_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R ^= AFEC_SEQ2R_USCH10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_read_SEQ2R_USCH10_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH10_Msk) >> AFEC_SEQ2R_USCH10_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ2R_USCH11_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R |= AFEC_SEQ2R_USCH11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_get_SEQ2R_USCH11_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH11(mask)) >> AFEC_SEQ2R_USCH11_Pos; + return tmp; +} + +static inline void hri_afec_write_SEQ2R_USCH11_bf(const void *const hw, hri_afec_seq2r_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp &= ~AFEC_SEQ2R_USCH11_Msk; + tmp |= AFEC_SEQ2R_USCH11(data); + ((Afec *)hw)->AFEC_SEQ2R = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ2R_USCH11_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R &= ~AFEC_SEQ2R_USCH11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ2R_USCH11_bf(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R ^= AFEC_SEQ2R_USCH11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_read_SEQ2R_USCH11_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp = (tmp & AFEC_SEQ2R_USCH11_Msk) >> AFEC_SEQ2R_USCH11_Pos; + return tmp; +} + +static inline void hri_afec_set_SEQ2R_reg(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_get_SEQ2R_reg(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SEQ2R; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_SEQ2R_reg(const void *const hw, hri_afec_seq2r_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SEQ2R_reg(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SEQ2R_reg(const void *const hw, hri_afec_seq2r_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SEQ2R ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_seq2r_reg_t hri_afec_read_SEQ2R_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_SEQ2R; +} + +static inline void hri_afec_set_CWR_LOWTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR |= AFEC_CWR_LOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_get_CWR_LOWTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CWR; + tmp = (tmp & AFEC_CWR_LOWTHRES(mask)) >> AFEC_CWR_LOWTHRES_Pos; + return tmp; +} + +static inline void hri_afec_write_CWR_LOWTHRES_bf(const void *const hw, hri_afec_cwr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CWR; + tmp &= ~AFEC_CWR_LOWTHRES_Msk; + tmp |= AFEC_CWR_LOWTHRES(data); + ((Afec *)hw)->AFEC_CWR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CWR_LOWTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR &= ~AFEC_CWR_LOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CWR_LOWTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR ^= AFEC_CWR_LOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_read_CWR_LOWTHRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CWR; + tmp = (tmp & AFEC_CWR_LOWTHRES_Msk) >> AFEC_CWR_LOWTHRES_Pos; + return tmp; +} + +static inline void hri_afec_set_CWR_HIGHTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR |= AFEC_CWR_HIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_get_CWR_HIGHTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CWR; + tmp = (tmp & AFEC_CWR_HIGHTHRES(mask)) >> AFEC_CWR_HIGHTHRES_Pos; + return tmp; +} + +static inline void hri_afec_write_CWR_HIGHTHRES_bf(const void *const hw, hri_afec_cwr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CWR; + tmp &= ~AFEC_CWR_HIGHTHRES_Msk; + tmp |= AFEC_CWR_HIGHTHRES(data); + ((Afec *)hw)->AFEC_CWR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CWR_HIGHTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR &= ~AFEC_CWR_HIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CWR_HIGHTHRES_bf(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR ^= AFEC_CWR_HIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_read_CWR_HIGHTHRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CWR; + tmp = (tmp & AFEC_CWR_HIGHTHRES_Msk) >> AFEC_CWR_HIGHTHRES_Pos; + return tmp; +} + +static inline void hri_afec_set_CWR_reg(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_get_CWR_reg(const void *const hw, hri_afec_cwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CWR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_CWR_reg(const void *const hw, hri_afec_cwr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CWR_reg(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CWR_reg(const void *const hw, hri_afec_cwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CWR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cwr_reg_t hri_afec_read_CWR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CWR; +} + +static inline void hri_afec_set_CGR_GAIN0_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN0_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN0(mask)) >> AFEC_CGR_GAIN0_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN0_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN0_Msk; + tmp |= AFEC_CGR_GAIN0(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN0_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN0_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN0(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN0_Msk) >> AFEC_CGR_GAIN0_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN1_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN1_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN1(mask)) >> AFEC_CGR_GAIN1_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN1_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN1_Msk; + tmp |= AFEC_CGR_GAIN1(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN1_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN1_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN1(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN1_Msk) >> AFEC_CGR_GAIN1_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN2_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN2_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN2(mask)) >> AFEC_CGR_GAIN2_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN2_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN2_Msk; + tmp |= AFEC_CGR_GAIN2(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN2_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN2_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN2(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN2_Msk) >> AFEC_CGR_GAIN2_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN3_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN3_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN3(mask)) >> AFEC_CGR_GAIN3_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN3_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN3_Msk; + tmp |= AFEC_CGR_GAIN3(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN3_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN3_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN3(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN3_Msk) >> AFEC_CGR_GAIN3_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN4_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN4_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN4(mask)) >> AFEC_CGR_GAIN4_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN4_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN4_Msk; + tmp |= AFEC_CGR_GAIN4(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN4_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN4_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN4(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN4_Msk) >> AFEC_CGR_GAIN4_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN5_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN5_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN5(mask)) >> AFEC_CGR_GAIN5_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN5_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN5_Msk; + tmp |= AFEC_CGR_GAIN5(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN5_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN5_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN5(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN5_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN5_Msk) >> AFEC_CGR_GAIN5_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN6_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN6_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN6(mask)) >> AFEC_CGR_GAIN6_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN6_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN6_Msk; + tmp |= AFEC_CGR_GAIN6(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN6_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN6_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN6(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN6_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN6_Msk) >> AFEC_CGR_GAIN6_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN7_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN7_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN7(mask)) >> AFEC_CGR_GAIN7_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN7_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN7_Msk; + tmp |= AFEC_CGR_GAIN7(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN7_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN7_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN7(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN7_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN7_Msk) >> AFEC_CGR_GAIN7_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN8_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN8_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN8(mask)) >> AFEC_CGR_GAIN8_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN8_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN8_Msk; + tmp |= AFEC_CGR_GAIN8(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN8_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN8_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN8(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN8_Msk) >> AFEC_CGR_GAIN8_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN9_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN9_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN9(mask)) >> AFEC_CGR_GAIN9_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN9_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN9_Msk; + tmp |= AFEC_CGR_GAIN9(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN9_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN9_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN9(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN9_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN9_Msk) >> AFEC_CGR_GAIN9_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN10_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN10_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN10(mask)) >> AFEC_CGR_GAIN10_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN10_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN10_Msk; + tmp |= AFEC_CGR_GAIN10(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN10_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN10_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN10(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN10_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN10_Msk) >> AFEC_CGR_GAIN10_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_GAIN11_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= AFEC_CGR_GAIN11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_GAIN11_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN11(mask)) >> AFEC_CGR_GAIN11_Pos; + return tmp; +} + +static inline void hri_afec_write_CGR_GAIN11_bf(const void *const hw, hri_afec_cgr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= ~AFEC_CGR_GAIN11_Msk; + tmp |= AFEC_CGR_GAIN11(data); + ((Afec *)hw)->AFEC_CGR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_GAIN11_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~AFEC_CGR_GAIN11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_GAIN11_bf(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= AFEC_CGR_GAIN11(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_GAIN11_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp = (tmp & AFEC_CGR_GAIN11_Msk) >> AFEC_CGR_GAIN11_Pos; + return tmp; +} + +static inline void hri_afec_set_CGR_reg(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_get_CGR_reg(const void *const hw, hri_afec_cgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CGR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_CGR_reg(const void *const hw, hri_afec_cgr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CGR_reg(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CGR_reg(const void *const hw, hri_afec_cgr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CGR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cgr_reg_t hri_afec_read_CGR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CGR; +} + +static inline void hri_afec_set_DIFFR_DIFF0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF0) >> AFEC_DIFFR_DIFF0_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF0; + tmp |= value << AFEC_DIFFR_DIFF0_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF1) >> AFEC_DIFFR_DIFF1_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF1; + tmp |= value << AFEC_DIFFR_DIFF1_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF2) >> AFEC_DIFFR_DIFF2_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF2; + tmp |= value << AFEC_DIFFR_DIFF2_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF3) >> AFEC_DIFFR_DIFF3_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF3; + tmp |= value << AFEC_DIFFR_DIFF3_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF4) >> AFEC_DIFFR_DIFF4_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF4; + tmp |= value << AFEC_DIFFR_DIFF4_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF5) >> AFEC_DIFFR_DIFF5_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF5; + tmp |= value << AFEC_DIFFR_DIFF5_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF6) >> AFEC_DIFFR_DIFF6_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF6; + tmp |= value << AFEC_DIFFR_DIFF6_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF7) >> AFEC_DIFFR_DIFF7_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF7; + tmp |= value << AFEC_DIFFR_DIFF7_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF8) >> AFEC_DIFFR_DIFF8_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF8; + tmp |= value << AFEC_DIFFR_DIFF8_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF9) >> AFEC_DIFFR_DIFF9_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF9; + tmp |= value << AFEC_DIFFR_DIFF9_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF10) >> AFEC_DIFFR_DIFF10_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF10; + tmp |= value << AFEC_DIFFR_DIFF10_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_DIFF11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= AFEC_DIFFR_DIFF11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_DIFFR_DIFF11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp = (tmp & AFEC_DIFFR_DIFF11) >> AFEC_DIFFR_DIFF11_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_DIFFR_DIFF11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= ~AFEC_DIFFR_DIFF11; + tmp |= value << AFEC_DIFFR_DIFF11_Pos; + ((Afec *)hw)->AFEC_DIFFR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_DIFF11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~AFEC_DIFFR_DIFF11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_DIFF11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= AFEC_DIFFR_DIFF11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_DIFFR_reg(const void *const hw, hri_afec_diffr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_diffr_reg_t hri_afec_get_DIFFR_reg(const void *const hw, hri_afec_diffr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_DIFFR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_DIFFR_reg(const void *const hw, hri_afec_diffr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_DIFFR_reg(const void *const hw, hri_afec_diffr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_DIFFR_reg(const void *const hw, hri_afec_diffr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_DIFFR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_diffr_reg_t hri_afec_read_DIFFR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_DIFFR; +} + +static inline void hri_afec_set_CSELR_CSEL_bf(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR |= AFEC_CSELR_CSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cselr_reg_t hri_afec_get_CSELR_CSEL_bf(const void *const hw, hri_afec_cselr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CSELR; + tmp = (tmp & AFEC_CSELR_CSEL(mask)) >> AFEC_CSELR_CSEL_Pos; + return tmp; +} + +static inline void hri_afec_write_CSELR_CSEL_bf(const void *const hw, hri_afec_cselr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CSELR; + tmp &= ~AFEC_CSELR_CSEL_Msk; + tmp |= AFEC_CSELR_CSEL(data); + ((Afec *)hw)->AFEC_CSELR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CSELR_CSEL_bf(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR &= ~AFEC_CSELR_CSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CSELR_CSEL_bf(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR ^= AFEC_CSELR_CSEL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cselr_reg_t hri_afec_read_CSELR_CSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CSELR; + tmp = (tmp & AFEC_CSELR_CSEL_Msk) >> AFEC_CSELR_CSEL_Pos; + return tmp; +} + +static inline void hri_afec_set_CSELR_reg(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cselr_reg_t hri_afec_get_CSELR_reg(const void *const hw, hri_afec_cselr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CSELR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_CSELR_reg(const void *const hw, hri_afec_cselr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CSELR_reg(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CSELR_reg(const void *const hw, hri_afec_cselr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CSELR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cselr_reg_t hri_afec_read_CSELR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CSELR; +} + +static inline void hri_afec_set_COCR_AOFF_bf(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR |= AFEC_COCR_AOFF(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cocr_reg_t hri_afec_get_COCR_AOFF_bf(const void *const hw, hri_afec_cocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_COCR; + tmp = (tmp & AFEC_COCR_AOFF(mask)) >> AFEC_COCR_AOFF_Pos; + return tmp; +} + +static inline void hri_afec_write_COCR_AOFF_bf(const void *const hw, hri_afec_cocr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_COCR; + tmp &= ~AFEC_COCR_AOFF_Msk; + tmp |= AFEC_COCR_AOFF(data); + ((Afec *)hw)->AFEC_COCR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_COCR_AOFF_bf(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR &= ~AFEC_COCR_AOFF(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_COCR_AOFF_bf(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR ^= AFEC_COCR_AOFF(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cocr_reg_t hri_afec_read_COCR_AOFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_COCR; + tmp = (tmp & AFEC_COCR_AOFF_Msk) >> AFEC_COCR_AOFF_Pos; + return tmp; +} + +static inline void hri_afec_set_COCR_reg(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cocr_reg_t hri_afec_get_COCR_reg(const void *const hw, hri_afec_cocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_COCR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_COCR_reg(const void *const hw, hri_afec_cocr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_COCR_reg(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_COCR_reg(const void *const hw, hri_afec_cocr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COCR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cocr_reg_t hri_afec_read_COCR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_COCR; +} + +static inline void hri_afec_set_TEMPMR_RTCT_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR |= AFEC_TEMPMR_RTCT; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_TEMPMR_RTCT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp = (tmp & AFEC_TEMPMR_RTCT) >> AFEC_TEMPMR_RTCT_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_TEMPMR_RTCT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp &= ~AFEC_TEMPMR_RTCT; + tmp |= value << AFEC_TEMPMR_RTCT_Pos; + ((Afec *)hw)->AFEC_TEMPMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPMR_RTCT_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR &= ~AFEC_TEMPMR_RTCT; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPMR_RTCT_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR ^= AFEC_TEMPMR_RTCT; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_TEMPMR_TEMPCMPMOD_bf(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR |= AFEC_TEMPMR_TEMPCMPMOD(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempmr_reg_t hri_afec_get_TEMPMR_TEMPCMPMOD_bf(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp = (tmp & AFEC_TEMPMR_TEMPCMPMOD(mask)) >> AFEC_TEMPMR_TEMPCMPMOD_Pos; + return tmp; +} + +static inline void hri_afec_write_TEMPMR_TEMPCMPMOD_bf(const void *const hw, hri_afec_tempmr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp &= ~AFEC_TEMPMR_TEMPCMPMOD_Msk; + tmp |= AFEC_TEMPMR_TEMPCMPMOD(data); + ((Afec *)hw)->AFEC_TEMPMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPMR_TEMPCMPMOD_bf(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR &= ~AFEC_TEMPMR_TEMPCMPMOD(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPMR_TEMPCMPMOD_bf(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR ^= AFEC_TEMPMR_TEMPCMPMOD(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempmr_reg_t hri_afec_read_TEMPMR_TEMPCMPMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp = (tmp & AFEC_TEMPMR_TEMPCMPMOD_Msk) >> AFEC_TEMPMR_TEMPCMPMOD_Pos; + return tmp; +} + +static inline void hri_afec_set_TEMPMR_reg(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempmr_reg_t hri_afec_get_TEMPMR_reg(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_TEMPMR_reg(const void *const hw, hri_afec_tempmr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPMR_reg(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPMR_reg(const void *const hw, hri_afec_tempmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPMR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempmr_reg_t hri_afec_read_TEMPMR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_TEMPMR; +} + +static inline void hri_afec_set_TEMPCWR_TLOWTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR |= AFEC_TEMPCWR_TLOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_get_TEMPCWR_TLOWTHRES_bf(const void *const hw, + hri_afec_tempcwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp = (tmp & AFEC_TEMPCWR_TLOWTHRES(mask)) >> AFEC_TEMPCWR_TLOWTHRES_Pos; + return tmp; +} + +static inline void hri_afec_write_TEMPCWR_TLOWTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp &= ~AFEC_TEMPCWR_TLOWTHRES_Msk; + tmp |= AFEC_TEMPCWR_TLOWTHRES(data); + ((Afec *)hw)->AFEC_TEMPCWR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPCWR_TLOWTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR &= ~AFEC_TEMPCWR_TLOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPCWR_TLOWTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR ^= AFEC_TEMPCWR_TLOWTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_read_TEMPCWR_TLOWTHRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp = (tmp & AFEC_TEMPCWR_TLOWTHRES_Msk) >> AFEC_TEMPCWR_TLOWTHRES_Pos; + return tmp; +} + +static inline void hri_afec_set_TEMPCWR_THIGHTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR |= AFEC_TEMPCWR_THIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_get_TEMPCWR_THIGHTHRES_bf(const void *const hw, + hri_afec_tempcwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp = (tmp & AFEC_TEMPCWR_THIGHTHRES(mask)) >> AFEC_TEMPCWR_THIGHTHRES_Pos; + return tmp; +} + +static inline void hri_afec_write_TEMPCWR_THIGHTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp &= ~AFEC_TEMPCWR_THIGHTHRES_Msk; + tmp |= AFEC_TEMPCWR_THIGHTHRES(data); + ((Afec *)hw)->AFEC_TEMPCWR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPCWR_THIGHTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR &= ~AFEC_TEMPCWR_THIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPCWR_THIGHTHRES_bf(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR ^= AFEC_TEMPCWR_THIGHTHRES(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_read_TEMPCWR_THIGHTHRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp = (tmp & AFEC_TEMPCWR_THIGHTHRES_Msk) >> AFEC_TEMPCWR_THIGHTHRES_Pos; + return tmp; +} + +static inline void hri_afec_set_TEMPCWR_reg(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_get_TEMPCWR_reg(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_TEMPCWR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_TEMPCWR_reg(const void *const hw, hri_afec_tempcwr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_TEMPCWR_reg(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_TEMPCWR_reg(const void *const hw, hri_afec_tempcwr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_TEMPCWR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_tempcwr_reg_t hri_afec_read_TEMPCWR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_TEMPCWR; +} + +static inline void hri_afec_set_ACR_PGA0EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR |= AFEC_ACR_PGA0EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_ACR_PGA0EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ACR; + tmp = (tmp & AFEC_ACR_PGA0EN) >> AFEC_ACR_PGA0EN_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_ACR_PGA0EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_ACR; + tmp &= ~AFEC_ACR_PGA0EN; + tmp |= value << AFEC_ACR_PGA0EN_Pos; + ((Afec *)hw)->AFEC_ACR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_ACR_PGA0EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR &= ~AFEC_ACR_PGA0EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_ACR_PGA0EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR ^= AFEC_ACR_PGA0EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_ACR_PGA1EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR |= AFEC_ACR_PGA1EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_ACR_PGA1EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ACR; + tmp = (tmp & AFEC_ACR_PGA1EN) >> AFEC_ACR_PGA1EN_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_ACR_PGA1EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_ACR; + tmp &= ~AFEC_ACR_PGA1EN; + tmp |= value << AFEC_ACR_PGA1EN_Pos; + ((Afec *)hw)->AFEC_ACR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_ACR_PGA1EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR &= ~AFEC_ACR_PGA1EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_ACR_PGA1EN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR ^= AFEC_ACR_PGA1EN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_ACR_IBCTL_bf(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR |= AFEC_ACR_IBCTL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_acr_reg_t hri_afec_get_ACR_IBCTL_bf(const void *const hw, hri_afec_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ACR; + tmp = (tmp & AFEC_ACR_IBCTL(mask)) >> AFEC_ACR_IBCTL_Pos; + return tmp; +} + +static inline void hri_afec_write_ACR_IBCTL_bf(const void *const hw, hri_afec_acr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_ACR; + tmp &= ~AFEC_ACR_IBCTL_Msk; + tmp |= AFEC_ACR_IBCTL(data); + ((Afec *)hw)->AFEC_ACR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_ACR_IBCTL_bf(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR &= ~AFEC_ACR_IBCTL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_ACR_IBCTL_bf(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR ^= AFEC_ACR_IBCTL(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_acr_reg_t hri_afec_read_ACR_IBCTL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ACR; + tmp = (tmp & AFEC_ACR_IBCTL_Msk) >> AFEC_ACR_IBCTL_Pos; + return tmp; +} + +static inline void hri_afec_set_ACR_reg(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_acr_reg_t hri_afec_get_ACR_reg(const void *const hw, hri_afec_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_ACR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_ACR_reg(const void *const hw, hri_afec_acr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_ACR_reg(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_ACR_reg(const void *const hw, hri_afec_acr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_ACR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_acr_reg_t hri_afec_read_ACR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_ACR; +} + +static inline void hri_afec_set_SHMR_DUAL0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL0) >> AFEC_SHMR_DUAL0_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL0; + tmp |= value << AFEC_SHMR_DUAL0_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL1) >> AFEC_SHMR_DUAL1_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL1; + tmp |= value << AFEC_SHMR_DUAL1_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL2) >> AFEC_SHMR_DUAL2_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL2; + tmp |= value << AFEC_SHMR_DUAL2_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL3) >> AFEC_SHMR_DUAL3_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL3; + tmp |= value << AFEC_SHMR_DUAL3_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL4) >> AFEC_SHMR_DUAL4_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL4; + tmp |= value << AFEC_SHMR_DUAL4_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL5) >> AFEC_SHMR_DUAL5_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL5; + tmp |= value << AFEC_SHMR_DUAL5_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL6) >> AFEC_SHMR_DUAL6_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL6; + tmp |= value << AFEC_SHMR_DUAL6_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL7) >> AFEC_SHMR_DUAL7_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL7; + tmp |= value << AFEC_SHMR_DUAL7_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL8) >> AFEC_SHMR_DUAL8_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL8; + tmp |= value << AFEC_SHMR_DUAL8_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL9) >> AFEC_SHMR_DUAL9_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL9; + tmp |= value << AFEC_SHMR_DUAL9_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL10) >> AFEC_SHMR_DUAL10_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL10; + tmp |= value << AFEC_SHMR_DUAL10_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_DUAL11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= AFEC_SHMR_DUAL11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_SHMR_DUAL11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp = (tmp & AFEC_SHMR_DUAL11) >> AFEC_SHMR_DUAL11_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_SHMR_DUAL11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= ~AFEC_SHMR_DUAL11; + tmp |= value << AFEC_SHMR_DUAL11_Pos; + ((Afec *)hw)->AFEC_SHMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_DUAL11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~AFEC_SHMR_DUAL11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_DUAL11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= AFEC_SHMR_DUAL11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_SHMR_reg(const void *const hw, hri_afec_shmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_shmr_reg_t hri_afec_get_SHMR_reg(const void *const hw, hri_afec_shmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_SHMR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_SHMR_reg(const void *const hw, hri_afec_shmr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_SHMR_reg(const void *const hw, hri_afec_shmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_SHMR_reg(const void *const hw, hri_afec_shmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_SHMR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_shmr_reg_t hri_afec_read_SHMR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_SHMR; +} + +static inline void hri_afec_set_COSR_CSEL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR |= AFEC_COSR_CSEL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_COSR_CSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_COSR; + tmp = (tmp & AFEC_COSR_CSEL) >> AFEC_COSR_CSEL_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_COSR_CSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_COSR; + tmp &= ~AFEC_COSR_CSEL; + tmp |= value << AFEC_COSR_CSEL_Pos; + ((Afec *)hw)->AFEC_COSR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_COSR_CSEL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR &= ~AFEC_COSR_CSEL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_COSR_CSEL_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR ^= AFEC_COSR_CSEL; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_COSR_reg(const void *const hw, hri_afec_cosr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cosr_reg_t hri_afec_get_COSR_reg(const void *const hw, hri_afec_cosr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_COSR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_COSR_reg(const void *const hw, hri_afec_cosr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_COSR_reg(const void *const hw, hri_afec_cosr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_COSR_reg(const void *const hw, hri_afec_cosr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_COSR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cosr_reg_t hri_afec_read_COSR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_COSR; +} + +static inline void hri_afec_set_CVR_OFFSETCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR |= AFEC_CVR_OFFSETCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_get_CVR_OFFSETCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CVR; + tmp = (tmp & AFEC_CVR_OFFSETCORR(mask)) >> AFEC_CVR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_afec_write_CVR_OFFSETCORR_bf(const void *const hw, hri_afec_cvr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CVR; + tmp &= ~AFEC_CVR_OFFSETCORR_Msk; + tmp |= AFEC_CVR_OFFSETCORR(data); + ((Afec *)hw)->AFEC_CVR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CVR_OFFSETCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR &= ~AFEC_CVR_OFFSETCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CVR_OFFSETCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR ^= AFEC_CVR_OFFSETCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_read_CVR_OFFSETCORR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CVR; + tmp = (tmp & AFEC_CVR_OFFSETCORR_Msk) >> AFEC_CVR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_afec_set_CVR_GAINCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR |= AFEC_CVR_GAINCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_get_CVR_GAINCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CVR; + tmp = (tmp & AFEC_CVR_GAINCORR(mask)) >> AFEC_CVR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_afec_write_CVR_GAINCORR_bf(const void *const hw, hri_afec_cvr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CVR; + tmp &= ~AFEC_CVR_GAINCORR_Msk; + tmp |= AFEC_CVR_GAINCORR(data); + ((Afec *)hw)->AFEC_CVR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CVR_GAINCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR &= ~AFEC_CVR_GAINCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CVR_GAINCORR_bf(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR ^= AFEC_CVR_GAINCORR(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_read_CVR_GAINCORR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CVR; + tmp = (tmp & AFEC_CVR_GAINCORR_Msk) >> AFEC_CVR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_afec_set_CVR_reg(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_get_CVR_reg(const void *const hw, hri_afec_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CVR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_CVR_reg(const void *const hw, hri_afec_cvr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CVR_reg(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CVR_reg(const void *const hw, hri_afec_cvr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CVR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cvr_reg_t hri_afec_read_CVR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CVR; +} + +static inline void hri_afec_set_CECR_ECORR0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR0) >> AFEC_CECR_ECORR0_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR0; + tmp |= value << AFEC_CECR_ECORR0_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR0_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR0; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR1) >> AFEC_CECR_ECORR1_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR1; + tmp |= value << AFEC_CECR_ECORR1_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR1_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR1; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR2) >> AFEC_CECR_ECORR2_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR2; + tmp |= value << AFEC_CECR_ECORR2_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR2_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR2; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR3) >> AFEC_CECR_ECORR3_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR3; + tmp |= value << AFEC_CECR_ECORR3_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR3_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR3; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR4) >> AFEC_CECR_ECORR4_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR4; + tmp |= value << AFEC_CECR_ECORR4_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR4_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR4; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR5) >> AFEC_CECR_ECORR5_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR5; + tmp |= value << AFEC_CECR_ECORR5_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR5_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR5; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR6) >> AFEC_CECR_ECORR6_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR6; + tmp |= value << AFEC_CECR_ECORR6_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR6_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR6; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR7) >> AFEC_CECR_ECORR7_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR7; + tmp |= value << AFEC_CECR_ECORR7_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR7_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR7; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR8) >> AFEC_CECR_ECORR8_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR8; + tmp |= value << AFEC_CECR_ECORR8_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR8_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR8; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR9) >> AFEC_CECR_ECORR9_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR9; + tmp |= value << AFEC_CECR_ECORR9_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR9_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR9; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR10) >> AFEC_CECR_ECORR10_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR10; + tmp |= value << AFEC_CECR_ECORR10_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR10_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR10; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_ECORR11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= AFEC_CECR_ECORR11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_CECR_ECORR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp = (tmp & AFEC_CECR_ECORR11) >> AFEC_CECR_ECORR11_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_CECR_ECORR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= ~AFEC_CECR_ECORR11; + tmp |= value << AFEC_CECR_ECORR11_Pos; + ((Afec *)hw)->AFEC_CECR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_ECORR11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~AFEC_CECR_ECORR11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_ECORR11_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= AFEC_CECR_ECORR11; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_CECR_reg(const void *const hw, hri_afec_cecr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cecr_reg_t hri_afec_get_CECR_reg(const void *const hw, hri_afec_cecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_CECR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_CECR_reg(const void *const hw, hri_afec_cecr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_CECR_reg(const void *const hw, hri_afec_cecr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_CECR_reg(const void *const hw, hri_afec_cecr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CECR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_cecr_reg_t hri_afec_read_CECR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_CECR; +} + +static inline void hri_afec_set_WPMR_WPEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR |= AFEC_WPMR_WPEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_afec_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp = (tmp & AFEC_WPMR_WPEN) >> AFEC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_afec_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp &= ~AFEC_WPMR_WPEN; + tmp |= value << AFEC_WPMR_WPEN_Pos; + ((Afec *)hw)->AFEC_WPMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_WPMR_WPEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR &= ~AFEC_WPMR_WPEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_WPMR_WPEN_bit(const void *const hw) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR ^= AFEC_WPMR_WPEN; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_set_WPMR_WPKEY_bf(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR |= AFEC_WPMR_WPKEY(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_wpmr_reg_t hri_afec_get_WPMR_WPKEY_bf(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp = (tmp & AFEC_WPMR_WPKEY(mask)) >> AFEC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_afec_write_WPMR_WPKEY_bf(const void *const hw, hri_afec_wpmr_reg_t data) +{ + uint32_t tmp; + AFEC_CRITICAL_SECTION_ENTER(); + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp &= ~AFEC_WPMR_WPKEY_Msk; + tmp |= AFEC_WPMR_WPKEY(data); + ((Afec *)hw)->AFEC_WPMR = tmp; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_WPMR_WPKEY_bf(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR &= ~AFEC_WPMR_WPKEY(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_WPMR_WPKEY_bf(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR ^= AFEC_WPMR_WPKEY(mask); + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_wpmr_reg_t hri_afec_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp = (tmp & AFEC_WPMR_WPKEY_Msk) >> AFEC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_afec_set_WPMR_reg(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR |= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_wpmr_reg_t hri_afec_get_WPMR_reg(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Afec *)hw)->AFEC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_afec_write_WPMR_reg(const void *const hw, hri_afec_wpmr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_clear_WPMR_reg(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR &= ~mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_afec_toggle_WPMR_reg(const void *const hw, hri_afec_wpmr_reg_t mask) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_WPMR ^= mask; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_afec_wpmr_reg_t hri_afec_read_WPMR_reg(const void *const hw) +{ + return ((Afec *)hw)->AFEC_WPMR; +} + +static inline void hri_afec_write_CR_reg(const void *const hw, hri_afec_cr_reg_t data) +{ + AFEC_CRITICAL_SECTION_ENTER(); + ((Afec *)hw)->AFEC_CR = data; + AFEC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AFEC_E70B_H_INCLUDED */ +#endif /* _SAME70_AFEC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_chipid_e70b.h b/bsp/microchip/same70/bsp/hri/hri_chipid_e70b.h new file mode 100644 index 0000000000..e6e2daf126 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_chipid_e70b.h @@ -0,0 +1,171 @@ +/** + * \file + * + * \brief SAM CHIPID + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_CHIPID_COMPONENT_ +#ifndef _HRI_CHIPID_E70B_H_INCLUDED_ +#define _HRI_CHIPID_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CHIPID_CRITICAL_SECTIONS) +#define CHIPID_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CHIPID_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CHIPID_CRITICAL_SECTION_ENTER() +#define CHIPID_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_chipid_cidr_reg_t; +typedef uint32_t hri_chipid_exid_reg_t; + +static inline bool hri_chipid_get_CIDR_EXT_bit(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_EXT) > 0; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_VERSION_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_VERSION(mask)) >> CHIPID_CIDR_VERSION_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_VERSION_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_VERSION_Msk) >> CHIPID_CIDR_VERSION_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_EPROC_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_EPROC(mask)) >> CHIPID_CIDR_EPROC_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_EPROC_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_EPROC_Msk) >> CHIPID_CIDR_EPROC_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_NVPSIZ_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPSIZ(mask)) >> CHIPID_CIDR_NVPSIZ_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_NVPSIZ_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPSIZ_Msk) >> CHIPID_CIDR_NVPSIZ_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_NVPSIZ2_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPSIZ2(mask)) >> CHIPID_CIDR_NVPSIZ2_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_NVPSIZ2_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPSIZ2_Msk) >> CHIPID_CIDR_NVPSIZ2_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_SRAMSIZ_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_SRAMSIZ(mask)) >> CHIPID_CIDR_SRAMSIZ_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_SRAMSIZ_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_SRAMSIZ_Msk) >> CHIPID_CIDR_SRAMSIZ_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_ARCH_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_ARCH(mask)) >> CHIPID_CIDR_ARCH_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_ARCH_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_ARCH_Msk) >> CHIPID_CIDR_ARCH_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_NVPTYP_bf(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPTYP(mask)) >> CHIPID_CIDR_NVPTYP_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_NVPTYP_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_CIDR & CHIPID_CIDR_NVPTYP_Msk) >> CHIPID_CIDR_NVPTYP_Pos; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_get_CIDR_reg(const void *const hw, hri_chipid_cidr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Chipid *)hw)->CHIPID_CIDR; + tmp &= mask; + return tmp; +} + +static inline hri_chipid_cidr_reg_t hri_chipid_read_CIDR_reg(const void *const hw) +{ + return ((Chipid *)hw)->CHIPID_CIDR; +} + +static inline hri_chipid_exid_reg_t hri_chipid_get_EXID_EXID_bf(const void *const hw, hri_chipid_exid_reg_t mask) +{ + return (((Chipid *)hw)->CHIPID_EXID & CHIPID_EXID_EXID(mask)) >> CHIPID_EXID_EXID_Pos; +} + +static inline hri_chipid_exid_reg_t hri_chipid_read_EXID_EXID_bf(const void *const hw) +{ + return (((Chipid *)hw)->CHIPID_EXID & CHIPID_EXID_EXID_Msk) >> CHIPID_EXID_EXID_Pos; +} + +static inline hri_chipid_exid_reg_t hri_chipid_get_EXID_reg(const void *const hw, hri_chipid_exid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Chipid *)hw)->CHIPID_EXID; + tmp &= mask; + return tmp; +} + +static inline hri_chipid_exid_reg_t hri_chipid_read_EXID_reg(const void *const hw) +{ + return ((Chipid *)hw)->CHIPID_EXID; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CHIPID_E70B_H_INCLUDED */ +#endif /* _SAME70_CHIPID_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_dacc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_dacc_e70b.h new file mode 100644 index 0000000000..f64ce16617 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_dacc_e70b.h @@ -0,0 +1,1233 @@ +/** + * \file + * + * \brief SAM DACC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_DACC_COMPONENT_ +#ifndef _HRI_DACC_E70B_H_INCLUDED_ +#define _HRI_DACC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DACC_CRITICAL_SECTIONS) +#define DACC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DACC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DACC_CRITICAL_SECTION_ENTER() +#define DACC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dacc_acr_reg_t; +typedef uint32_t hri_dacc_cdr_reg_t; +typedef uint32_t hri_dacc_chsr_reg_t; +typedef uint32_t hri_dacc_cr_reg_t; +typedef uint32_t hri_dacc_imr_reg_t; +typedef uint32_t hri_dacc_isr_reg_t; +typedef uint32_t hri_dacc_mr_reg_t; +typedef uint32_t hri_dacc_trigr_reg_t; +typedef uint32_t hri_dacc_wpmr_reg_t; +typedef uint32_t hri_dacc_wpsr_reg_t; + +static inline bool hri_dacc_get_ISR_TXRDY0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_ISR & DACC_ISR_TXRDY0) >> DACC_ISR_TXRDY0_Pos; +} + +static inline bool hri_dacc_get_ISR_TXRDY1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_ISR & DACC_ISR_TXRDY1) >> DACC_ISR_TXRDY1_Pos; +} + +static inline bool hri_dacc_get_ISR_EOC0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_ISR & DACC_ISR_EOC0) >> DACC_ISR_EOC0_Pos; +} + +static inline bool hri_dacc_get_ISR_EOC1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_ISR & DACC_ISR_EOC1) >> DACC_ISR_EOC1_Pos; +} + +static inline hri_dacc_isr_reg_t hri_dacc_get_ISR_reg(const void *const hw, hri_dacc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_dacc_isr_reg_t hri_dacc_read_ISR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_ISR; +} + +static inline void hri_dacc_set_CHSR_CH0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_CHER = DACC_CHSR_CH0; +} + +static inline bool hri_dacc_get_CHSR_CH0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_CHSR & DACC_CHSR_CH0) >> DACC_CHSR_CH0_Pos; +} + +static inline void hri_dacc_write_CHSR_CH0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_CHDR = DACC_CHSR_CH0; + } else { + ((Dacc *)hw)->DACC_CHER = DACC_CHSR_CH0; + } +} + +static inline void hri_dacc_clear_CHSR_CH0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_CHDR = DACC_CHSR_CH0; +} + +static inline void hri_dacc_set_CHSR_CH1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_CHER = DACC_CHSR_CH1; +} + +static inline bool hri_dacc_get_CHSR_CH1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_CHSR & DACC_CHSR_CH1) >> DACC_CHSR_CH1_Pos; +} + +static inline void hri_dacc_write_CHSR_CH1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_CHDR = DACC_CHSR_CH1; + } else { + ((Dacc *)hw)->DACC_CHER = DACC_CHSR_CH1; + } +} + +static inline void hri_dacc_clear_CHSR_CH1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_CHDR = DACC_CHSR_CH1; +} + +static inline bool hri_dacc_get_CHSR_DACRDY0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_CHSR & DACC_CHSR_DACRDY0) >> DACC_CHSR_DACRDY0_Pos; +} + +static inline bool hri_dacc_get_CHSR_DACRDY1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_CHSR & DACC_CHSR_DACRDY1) >> DACC_CHSR_DACRDY1_Pos; +} + +static inline void hri_dacc_set_CHSR_reg(const void *const hw, hri_dacc_chsr_reg_t mask) +{ + ((Dacc *)hw)->DACC_CHER = mask; +} + +static inline hri_dacc_chsr_reg_t hri_dacc_get_CHSR_reg(const void *const hw, hri_dacc_chsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_CHSR; + tmp &= mask; + return tmp; +} + +static inline hri_dacc_chsr_reg_t hri_dacc_read_CHSR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_CHSR; +} + +static inline void hri_dacc_write_CHSR_reg(const void *const hw, hri_dacc_chsr_reg_t data) +{ + ((Dacc *)hw)->DACC_CHER = data; + ((Dacc *)hw)->DACC_CHDR = ~data; +} + +static inline void hri_dacc_clear_CHSR_reg(const void *const hw, hri_dacc_chsr_reg_t mask) +{ + ((Dacc *)hw)->DACC_CHDR = mask; +} + +static inline void hri_dacc_write_CHDR_reg(const void *const hw, hri_dacc_chsr_reg_t data) +{ + ((Dacc *)hw)->DACC_CHDR = data; +} + +static inline void hri_dacc_write_CHER_reg(const void *const hw, hri_dacc_chsr_reg_t data) +{ + ((Dacc *)hw)->DACC_CHER = data; +} + +static inline void hri_dacc_set_IMR_TXRDY0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IER = DACC_IMR_TXRDY0; +} + +static inline bool hri_dacc_get_IMR_TXRDY0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_IMR & DACC_IMR_TXRDY0) >> DACC_IMR_TXRDY0_Pos; +} + +static inline void hri_dacc_write_IMR_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_IDR = DACC_IMR_TXRDY0; + } else { + ((Dacc *)hw)->DACC_IER = DACC_IMR_TXRDY0; + } +} + +static inline void hri_dacc_clear_IMR_TXRDY0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IDR = DACC_IMR_TXRDY0; +} + +static inline void hri_dacc_set_IMR_TXRDY1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IER = DACC_IMR_TXRDY1; +} + +static inline bool hri_dacc_get_IMR_TXRDY1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_IMR & DACC_IMR_TXRDY1) >> DACC_IMR_TXRDY1_Pos; +} + +static inline void hri_dacc_write_IMR_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_IDR = DACC_IMR_TXRDY1; + } else { + ((Dacc *)hw)->DACC_IER = DACC_IMR_TXRDY1; + } +} + +static inline void hri_dacc_clear_IMR_TXRDY1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IDR = DACC_IMR_TXRDY1; +} + +static inline void hri_dacc_set_IMR_EOC0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IER = DACC_IMR_EOC0; +} + +static inline bool hri_dacc_get_IMR_EOC0_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_IMR & DACC_IMR_EOC0) >> DACC_IMR_EOC0_Pos; +} + +static inline void hri_dacc_write_IMR_EOC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_IDR = DACC_IMR_EOC0; + } else { + ((Dacc *)hw)->DACC_IER = DACC_IMR_EOC0; + } +} + +static inline void hri_dacc_clear_IMR_EOC0_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IDR = DACC_IMR_EOC0; +} + +static inline void hri_dacc_set_IMR_EOC1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IER = DACC_IMR_EOC1; +} + +static inline bool hri_dacc_get_IMR_EOC1_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_IMR & DACC_IMR_EOC1) >> DACC_IMR_EOC1_Pos; +} + +static inline void hri_dacc_write_IMR_EOC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dacc *)hw)->DACC_IDR = DACC_IMR_EOC1; + } else { + ((Dacc *)hw)->DACC_IER = DACC_IMR_EOC1; + } +} + +static inline void hri_dacc_clear_IMR_EOC1_bit(const void *const hw) +{ + ((Dacc *)hw)->DACC_IDR = DACC_IMR_EOC1; +} + +static inline void hri_dacc_set_IMR_reg(const void *const hw, hri_dacc_imr_reg_t mask) +{ + ((Dacc *)hw)->DACC_IER = mask; +} + +static inline hri_dacc_imr_reg_t hri_dacc_get_IMR_reg(const void *const hw, hri_dacc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_dacc_imr_reg_t hri_dacc_read_IMR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_IMR; +} + +static inline void hri_dacc_write_IMR_reg(const void *const hw, hri_dacc_imr_reg_t data) +{ + ((Dacc *)hw)->DACC_IER = data; + ((Dacc *)hw)->DACC_IDR = ~data; +} + +static inline void hri_dacc_clear_IMR_reg(const void *const hw, hri_dacc_imr_reg_t mask) +{ + ((Dacc *)hw)->DACC_IDR = mask; +} + +static inline bool hri_dacc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Dacc *)hw)->DACC_WPSR & DACC_WPSR_WPVS) > 0; +} + +static inline hri_dacc_wpsr_reg_t hri_dacc_get_WPSR_WPVSRC_bf(const void *const hw, hri_dacc_wpsr_reg_t mask) +{ + return (((Dacc *)hw)->DACC_WPSR & DACC_WPSR_WPVSRC(mask)) >> DACC_WPSR_WPVSRC_Pos; +} + +static inline hri_dacc_wpsr_reg_t hri_dacc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Dacc *)hw)->DACC_WPSR & DACC_WPSR_WPVSRC_Msk) >> DACC_WPSR_WPVSRC_Pos; +} + +static inline hri_dacc_wpsr_reg_t hri_dacc_get_WPSR_reg(const void *const hw, hri_dacc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_dacc_wpsr_reg_t hri_dacc_read_WPSR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_WPSR; +} + +static inline void hri_dacc_set_MR_MAXS0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_MAXS0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_MR_MAXS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_MAXS0) >> DACC_MR_MAXS0_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_MR_MAXS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_MAXS0; + tmp |= value << DACC_MR_MAXS0_Pos; + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_MAXS0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_MAXS0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_MAXS0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_MAXS0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_MR_MAXS1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_MAXS1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_MR_MAXS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_MAXS1) >> DACC_MR_MAXS1_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_MR_MAXS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_MAXS1; + tmp |= value << DACC_MR_MAXS1_Pos; + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_MAXS1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_MAXS1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_MAXS1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_MAXS1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_MR_WORD_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_WORD; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_MR_WORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_WORD) >> DACC_MR_WORD_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_MR_WORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_WORD; + tmp |= value << DACC_MR_WORD_Pos; + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_WORD_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_WORD; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_WORD_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_WORD; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_MR_ZERO_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_ZERO; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_MR_ZERO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_ZERO) >> DACC_MR_ZERO_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_MR_ZERO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_ZERO; + tmp |= value << DACC_MR_ZERO_Pos; + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_ZERO_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_ZERO; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_ZERO_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_ZERO; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_MR_DIFF_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_DIFF; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_MR_DIFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_DIFF) >> DACC_MR_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_MR_DIFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_DIFF; + tmp |= value << DACC_MR_DIFF_Pos; + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_DIFF_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_DIFF; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_DIFF_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_DIFF; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_MR_PRESCALER_bf(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= DACC_MR_PRESCALER(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_mr_reg_t hri_dacc_get_MR_PRESCALER_bf(const void *const hw, hri_dacc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_PRESCALER(mask)) >> DACC_MR_PRESCALER_Pos; + return tmp; +} + +static inline void hri_dacc_write_MR_PRESCALER_bf(const void *const hw, hri_dacc_mr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= ~DACC_MR_PRESCALER_Msk; + tmp |= DACC_MR_PRESCALER(data); + ((Dacc *)hw)->DACC_MR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_PRESCALER_bf(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~DACC_MR_PRESCALER(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_PRESCALER_bf(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= DACC_MR_PRESCALER(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_mr_reg_t hri_dacc_read_MR_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp = (tmp & DACC_MR_PRESCALER_Msk) >> DACC_MR_PRESCALER_Pos; + return tmp; +} + +static inline void hri_dacc_set_MR_reg(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR |= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_mr_reg_t hri_dacc_get_MR_reg(const void *const hw, hri_dacc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_dacc_write_MR_reg(const void *const hw, hri_dacc_mr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_MR_reg(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR &= ~mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_MR_reg(const void *const hw, hri_dacc_mr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_MR ^= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_mr_reg_t hri_dacc_read_MR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_MR; +} + +static inline void hri_dacc_set_TRIGR_TRGEN0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_TRGEN0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_TRIGR_TRGEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGEN0) >> DACC_TRIGR_TRGEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_TRIGR_TRGEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_TRGEN0; + tmp |= value << DACC_TRIGR_TRGEN0_Pos; + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_TRGEN0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_TRGEN0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_TRGEN0_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_TRGEN0; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_TRIGR_TRGEN1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_TRGEN1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_TRIGR_TRGEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGEN1) >> DACC_TRIGR_TRGEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_TRIGR_TRGEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_TRGEN1; + tmp |= value << DACC_TRIGR_TRGEN1_Pos; + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_TRGEN1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_TRGEN1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_TRGEN1_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_TRGEN1; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_TRIGR_TRGSEL0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_TRGSEL0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_get_TRIGR_TRGSEL0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGSEL0(mask)) >> DACC_TRIGR_TRGSEL0_Pos; + return tmp; +} + +static inline void hri_dacc_write_TRIGR_TRGSEL0_bf(const void *const hw, hri_dacc_trigr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_TRGSEL0_Msk; + tmp |= DACC_TRIGR_TRGSEL0(data); + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_TRGSEL0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_TRGSEL0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_TRGSEL0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_TRGSEL0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_read_TRIGR_TRGSEL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGSEL0_Msk) >> DACC_TRIGR_TRGSEL0_Pos; + return tmp; +} + +static inline void hri_dacc_set_TRIGR_TRGSEL1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_TRGSEL1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_get_TRIGR_TRGSEL1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGSEL1(mask)) >> DACC_TRIGR_TRGSEL1_Pos; + return tmp; +} + +static inline void hri_dacc_write_TRIGR_TRGSEL1_bf(const void *const hw, hri_dacc_trigr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_TRGSEL1_Msk; + tmp |= DACC_TRIGR_TRGSEL1(data); + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_TRGSEL1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_TRGSEL1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_TRGSEL1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_TRGSEL1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_read_TRIGR_TRGSEL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_TRGSEL1_Msk) >> DACC_TRIGR_TRGSEL1_Pos; + return tmp; +} + +static inline void hri_dacc_set_TRIGR_OSR0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_OSR0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_get_TRIGR_OSR0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_OSR0(mask)) >> DACC_TRIGR_OSR0_Pos; + return tmp; +} + +static inline void hri_dacc_write_TRIGR_OSR0_bf(const void *const hw, hri_dacc_trigr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_OSR0_Msk; + tmp |= DACC_TRIGR_OSR0(data); + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_OSR0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_OSR0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_OSR0_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_OSR0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_read_TRIGR_OSR0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_OSR0_Msk) >> DACC_TRIGR_OSR0_Pos; + return tmp; +} + +static inline void hri_dacc_set_TRIGR_OSR1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= DACC_TRIGR_OSR1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_get_TRIGR_OSR1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_OSR1(mask)) >> DACC_TRIGR_OSR1_Pos; + return tmp; +} + +static inline void hri_dacc_write_TRIGR_OSR1_bf(const void *const hw, hri_dacc_trigr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= ~DACC_TRIGR_OSR1_Msk; + tmp |= DACC_TRIGR_OSR1(data); + ((Dacc *)hw)->DACC_TRIGR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_OSR1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~DACC_TRIGR_OSR1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_OSR1_bf(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= DACC_TRIGR_OSR1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_read_TRIGR_OSR1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp = (tmp & DACC_TRIGR_OSR1_Msk) >> DACC_TRIGR_OSR1_Pos; + return tmp; +} + +static inline void hri_dacc_set_TRIGR_reg(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR |= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_get_TRIGR_reg(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_TRIGR; + tmp &= mask; + return tmp; +} + +static inline void hri_dacc_write_TRIGR_reg(const void *const hw, hri_dacc_trigr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_TRIGR_reg(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR &= ~mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_TRIGR_reg(const void *const hw, hri_dacc_trigr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_TRIGR ^= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_trigr_reg_t hri_dacc_read_TRIGR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_TRIGR; +} + +static inline void hri_dacc_set_ACR_IBCTLCH0_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR |= DACC_ACR_IBCTLCH0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_get_ACR_IBCTLCH0_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ACR; + tmp = (tmp & DACC_ACR_IBCTLCH0(mask)) >> DACC_ACR_IBCTLCH0_Pos; + return tmp; +} + +static inline void hri_dacc_write_ACR_IBCTLCH0_bf(const void *const hw, hri_dacc_acr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_ACR; + tmp &= ~DACC_ACR_IBCTLCH0_Msk; + tmp |= DACC_ACR_IBCTLCH0(data); + ((Dacc *)hw)->DACC_ACR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_ACR_IBCTLCH0_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR &= ~DACC_ACR_IBCTLCH0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_ACR_IBCTLCH0_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR ^= DACC_ACR_IBCTLCH0(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_read_ACR_IBCTLCH0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ACR; + tmp = (tmp & DACC_ACR_IBCTLCH0_Msk) >> DACC_ACR_IBCTLCH0_Pos; + return tmp; +} + +static inline void hri_dacc_set_ACR_IBCTLCH1_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR |= DACC_ACR_IBCTLCH1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_get_ACR_IBCTLCH1_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ACR; + tmp = (tmp & DACC_ACR_IBCTLCH1(mask)) >> DACC_ACR_IBCTLCH1_Pos; + return tmp; +} + +static inline void hri_dacc_write_ACR_IBCTLCH1_bf(const void *const hw, hri_dacc_acr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_ACR; + tmp &= ~DACC_ACR_IBCTLCH1_Msk; + tmp |= DACC_ACR_IBCTLCH1(data); + ((Dacc *)hw)->DACC_ACR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_ACR_IBCTLCH1_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR &= ~DACC_ACR_IBCTLCH1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_ACR_IBCTLCH1_bf(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR ^= DACC_ACR_IBCTLCH1(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_read_ACR_IBCTLCH1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ACR; + tmp = (tmp & DACC_ACR_IBCTLCH1_Msk) >> DACC_ACR_IBCTLCH1_Pos; + return tmp; +} + +static inline void hri_dacc_set_ACR_reg(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR |= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_get_ACR_reg(const void *const hw, hri_dacc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_ACR; + tmp &= mask; + return tmp; +} + +static inline void hri_dacc_write_ACR_reg(const void *const hw, hri_dacc_acr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_ACR_reg(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR &= ~mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_ACR_reg(const void *const hw, hri_dacc_acr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_ACR ^= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_acr_reg_t hri_dacc_read_ACR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_ACR; +} + +static inline void hri_dacc_set_WPMR_WPEN_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR |= DACC_WPMR_WPEN; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dacc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp = (tmp & DACC_WPMR_WPEN) >> DACC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_dacc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp &= ~DACC_WPMR_WPEN; + tmp |= value << DACC_WPMR_WPEN_Pos; + ((Dacc *)hw)->DACC_WPMR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_WPMR_WPEN_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR &= ~DACC_WPMR_WPEN; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR ^= DACC_WPMR_WPEN; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_set_WPMR_WPKEY_bf(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR |= DACC_WPMR_WPKEY(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_wpmr_reg_t hri_dacc_get_WPMR_WPKEY_bf(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp = (tmp & DACC_WPMR_WPKEY(mask)) >> DACC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_dacc_write_WPMR_WPKEY_bf(const void *const hw, hri_dacc_wpmr_reg_t data) +{ + uint32_t tmp; + DACC_CRITICAL_SECTION_ENTER(); + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp &= ~DACC_WPMR_WPKEY_Msk; + tmp |= DACC_WPMR_WPKEY(data); + ((Dacc *)hw)->DACC_WPMR = tmp; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_WPMR_WPKEY_bf(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR &= ~DACC_WPMR_WPKEY(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR ^= DACC_WPMR_WPKEY(mask); + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_wpmr_reg_t hri_dacc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp = (tmp & DACC_WPMR_WPKEY_Msk) >> DACC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_dacc_set_WPMR_reg(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR |= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_wpmr_reg_t hri_dacc_get_WPMR_reg(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dacc *)hw)->DACC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_dacc_write_WPMR_reg(const void *const hw, hri_dacc_wpmr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_clear_WPMR_reg(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR &= ~mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_toggle_WPMR_reg(const void *const hw, hri_dacc_wpmr_reg_t mask) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_WPMR ^= mask; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dacc_wpmr_reg_t hri_dacc_read_WPMR_reg(const void *const hw) +{ + return ((Dacc *)hw)->DACC_WPMR; +} + +static inline void hri_dacc_write_CR_reg(const void *const hw, hri_dacc_cr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_CR = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dacc_write_CDR_reg(const void *const hw, uint8_t index, hri_dacc_cdr_reg_t data) +{ + DACC_CRITICAL_SECTION_ENTER(); + ((Dacc *)hw)->DACC_CDR[index] = data; + DACC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DACC_E70B_H_INCLUDED */ +#endif /* _SAME70_DACC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_e70b.h b/bsp/microchip/same70/bsp/hri/hri_e70b.h new file mode 100644 index 0000000000..d75f84a8de --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_e70b.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief SAM E70 HRI top-level header file + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_E70B_H_INCLUDED_ +#define _HRI_E70B_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_E70B_H_INCLUDED_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_efc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_efc_e70b.h new file mode 100644 index 0000000000..4bd19d30e7 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_efc_e70b.h @@ -0,0 +1,484 @@ +/** + * \file + * + * \brief SAM EFC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_EFC_COMPONENT_ +#ifndef _HRI_EFC_E70B_H_INCLUDED_ +#define _HRI_EFC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EFC_CRITICAL_SECTIONS) +#define EFC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EFC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EFC_CRITICAL_SECTION_ENTER() +#define EFC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_efc_eefc_fcr_reg_t; +typedef uint32_t hri_efc_eefc_fmr_reg_t; +typedef uint32_t hri_efc_eefc_frr_reg_t; +typedef uint32_t hri_efc_eefc_fsr_reg_t; +typedef uint32_t hri_efc_eefc_wpmr_reg_t; + +static inline bool hri_efc_get_EEFC_FSR_FRDY_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_FRDY) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_FCMDE_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_FCMDE) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_FLOCKE_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_FLOCKE) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_FLERR_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_FLERR) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_UECCELSB_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_UECCELSB) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_MECCELSB_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_MECCELSB) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_UECCEMSB_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_UECCEMSB) > 0; +} + +static inline bool hri_efc_get_EEFC_FSR_MECCEMSB_bit(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FSR & EEFC_FSR_MECCEMSB) > 0; +} + +static inline hri_efc_eefc_fsr_reg_t hri_efc_get_EEFC_FSR_reg(const void *const hw, hri_efc_eefc_fsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FSR; + tmp &= mask; + return tmp; +} + +static inline hri_efc_eefc_fsr_reg_t hri_efc_read_EEFC_FSR_reg(const void *const hw) +{ + return ((Efc *)hw)->EEFC_FSR; +} + +static inline hri_efc_eefc_frr_reg_t hri_efc_get_EEFC_FRR_FVALUE_bf(const void *const hw, hri_efc_eefc_frr_reg_t mask) +{ + return (((Efc *)hw)->EEFC_FRR & EEFC_FRR_FVALUE(mask)) >> EEFC_FRR_FVALUE_Pos; +} + +static inline hri_efc_eefc_frr_reg_t hri_efc_read_EEFC_FRR_FVALUE_bf(const void *const hw) +{ + return (((Efc *)hw)->EEFC_FRR & EEFC_FRR_FVALUE_Msk) >> EEFC_FRR_FVALUE_Pos; +} + +static inline hri_efc_eefc_frr_reg_t hri_efc_get_EEFC_FRR_reg(const void *const hw, hri_efc_eefc_frr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FRR; + tmp &= mask; + return tmp; +} + +static inline hri_efc_eefc_frr_reg_t hri_efc_read_EEFC_FRR_reg(const void *const hw) +{ + return ((Efc *)hw)->EEFC_FRR; +} + +static inline void hri_efc_set_EEFC_FMR_FRDY_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR |= EEFC_FMR_FRDY; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_efc_get_EEFC_FMR_FRDY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp = (tmp & EEFC_FMR_FRDY) >> EEFC_FMR_FRDY_Pos; + return (bool)tmp; +} + +static inline void hri_efc_write_EEFC_FMR_FRDY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_FMR; + tmp &= ~EEFC_FMR_FRDY; + tmp |= value << EEFC_FMR_FRDY_Pos; + ((Efc *)hw)->EEFC_FMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_FMR_FRDY_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR &= ~EEFC_FMR_FRDY; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_FMR_FRDY_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR ^= EEFC_FMR_FRDY; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_set_EEFC_FMR_SCOD_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR |= EEFC_FMR_SCOD; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_efc_get_EEFC_FMR_SCOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp = (tmp & EEFC_FMR_SCOD) >> EEFC_FMR_SCOD_Pos; + return (bool)tmp; +} + +static inline void hri_efc_write_EEFC_FMR_SCOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_FMR; + tmp &= ~EEFC_FMR_SCOD; + tmp |= value << EEFC_FMR_SCOD_Pos; + ((Efc *)hw)->EEFC_FMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_FMR_SCOD_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR &= ~EEFC_FMR_SCOD; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_FMR_SCOD_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR ^= EEFC_FMR_SCOD; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_set_EEFC_FMR_CLOE_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR |= EEFC_FMR_CLOE; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_efc_get_EEFC_FMR_CLOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp = (tmp & EEFC_FMR_CLOE) >> EEFC_FMR_CLOE_Pos; + return (bool)tmp; +} + +static inline void hri_efc_write_EEFC_FMR_CLOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_FMR; + tmp &= ~EEFC_FMR_CLOE; + tmp |= value << EEFC_FMR_CLOE_Pos; + ((Efc *)hw)->EEFC_FMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_FMR_CLOE_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR &= ~EEFC_FMR_CLOE; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_FMR_CLOE_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR ^= EEFC_FMR_CLOE; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_set_EEFC_FMR_FWS_bf(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR |= EEFC_FMR_FWS(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_fmr_reg_t hri_efc_get_EEFC_FMR_FWS_bf(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp = (tmp & EEFC_FMR_FWS(mask)) >> EEFC_FMR_FWS_Pos; + return tmp; +} + +static inline void hri_efc_write_EEFC_FMR_FWS_bf(const void *const hw, hri_efc_eefc_fmr_reg_t data) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_FMR; + tmp &= ~EEFC_FMR_FWS_Msk; + tmp |= EEFC_FMR_FWS(data); + ((Efc *)hw)->EEFC_FMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_FMR_FWS_bf(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR &= ~EEFC_FMR_FWS(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_FMR_FWS_bf(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR ^= EEFC_FMR_FWS(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_fmr_reg_t hri_efc_read_EEFC_FMR_FWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp = (tmp & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos; + return tmp; +} + +static inline void hri_efc_set_EEFC_FMR_reg(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR |= mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_fmr_reg_t hri_efc_get_EEFC_FMR_reg(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_FMR; + tmp &= mask; + return tmp; +} + +static inline void hri_efc_write_EEFC_FMR_reg(const void *const hw, hri_efc_eefc_fmr_reg_t data) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR = data; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_FMR_reg(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR &= ~mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_FMR_reg(const void *const hw, hri_efc_eefc_fmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FMR ^= mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_fmr_reg_t hri_efc_read_EEFC_FMR_reg(const void *const hw) +{ + return ((Efc *)hw)->EEFC_FMR; +} + +static inline void hri_efc_set_EEFC_WPMR_WPEN_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR |= EEFC_WPMR_WPEN; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_efc_get_EEFC_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp = (tmp & EEFC_WPMR_WPEN) >> EEFC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_efc_write_EEFC_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp &= ~EEFC_WPMR_WPEN; + tmp |= value << EEFC_WPMR_WPEN_Pos; + ((Efc *)hw)->EEFC_WPMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_WPMR_WPEN_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR &= ~EEFC_WPMR_WPEN; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_WPMR_WPEN_bit(const void *const hw) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR ^= EEFC_WPMR_WPEN; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_set_EEFC_WPMR_WPKEY_bf(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR |= EEFC_WPMR_WPKEY(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_wpmr_reg_t hri_efc_get_EEFC_WPMR_WPKEY_bf(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp = (tmp & EEFC_WPMR_WPKEY(mask)) >> EEFC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_efc_write_EEFC_WPMR_WPKEY_bf(const void *const hw, hri_efc_eefc_wpmr_reg_t data) +{ + uint32_t tmp; + EFC_CRITICAL_SECTION_ENTER(); + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp &= ~EEFC_WPMR_WPKEY_Msk; + tmp |= EEFC_WPMR_WPKEY(data); + ((Efc *)hw)->EEFC_WPMR = tmp; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_WPMR_WPKEY_bf(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR &= ~EEFC_WPMR_WPKEY(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_WPMR_WPKEY_bf(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR ^= EEFC_WPMR_WPKEY(mask); + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_wpmr_reg_t hri_efc_read_EEFC_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp = (tmp & EEFC_WPMR_WPKEY_Msk) >> EEFC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_efc_set_EEFC_WPMR_reg(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR |= mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_wpmr_reg_t hri_efc_get_EEFC_WPMR_reg(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Efc *)hw)->EEFC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_efc_write_EEFC_WPMR_reg(const void *const hw, hri_efc_eefc_wpmr_reg_t data) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR = data; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_clear_EEFC_WPMR_reg(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR &= ~mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_efc_toggle_EEFC_WPMR_reg(const void *const hw, hri_efc_eefc_wpmr_reg_t mask) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_WPMR ^= mask; + EFC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_efc_eefc_wpmr_reg_t hri_efc_read_EEFC_WPMR_reg(const void *const hw) +{ + return ((Efc *)hw)->EEFC_WPMR; +} + +static inline void hri_efc_write_EEFC_FCR_reg(const void *const hw, hri_efc_eefc_fcr_reg_t data) +{ + EFC_CRITICAL_SECTION_ENTER(); + ((Efc *)hw)->EEFC_FCR = data; + EFC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EFC_E70B_H_INCLUDED */ +#endif /* _SAME70_EFC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_gmac_e70b.h b/bsp/microchip/same70/bsp/hri/hri_gmac_e70b.h new file mode 100644 index 0000000000..c622f031d9 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_gmac_e70b.h @@ -0,0 +1,11034 @@ +/** + * \file + * + * \brief SAM GMAC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_GMAC_COMPONENT_ +#ifndef _HRI_GMAC_E70B_H_INCLUDED_ +#define _HRI_GMAC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) +#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GMAC_CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gmac_ae_reg_t; +typedef uint32_t hri_gmac_bcfr_reg_t; +typedef uint32_t hri_gmac_bcft_reg_t; +typedef uint32_t hri_gmac_bfr64_reg_t; +typedef uint32_t hri_gmac_bft64_reg_t; +typedef uint32_t hri_gmac_cbscr_reg_t; +typedef uint32_t hri_gmac_cbsisqa_reg_t; +typedef uint32_t hri_gmac_cbsisqb_reg_t; +typedef uint32_t hri_gmac_cse_reg_t; +typedef uint32_t hri_gmac_dcfgr_reg_t; +typedef uint32_t hri_gmac_dtf_reg_t; +typedef uint32_t hri_gmac_ec_reg_t; +typedef uint32_t hri_gmac_efrn_reg_t; +typedef uint32_t hri_gmac_efrsh_reg_t; +typedef uint32_t hri_gmac_efrsl_reg_t; +typedef uint32_t hri_gmac_eftn_reg_t; +typedef uint32_t hri_gmac_eftsh_reg_t; +typedef uint32_t hri_gmac_eftsl_reg_t; +typedef uint32_t hri_gmac_fcse_reg_t; +typedef uint32_t hri_gmac_fr_reg_t; +typedef uint32_t hri_gmac_ft_reg_t; +typedef uint32_t hri_gmac_gtbft1518_reg_t; +typedef uint32_t hri_gmac_hrb_reg_t; +typedef uint32_t hri_gmac_hrt_reg_t; +typedef uint32_t hri_gmac_ihce_reg_t; +typedef uint32_t hri_gmac_imr_reg_t; +typedef uint32_t hri_gmac_imrpq_reg_t; +typedef uint32_t hri_gmac_ipgs_reg_t; +typedef uint32_t hri_gmac_isr_reg_t; +typedef uint32_t hri_gmac_isrpq_reg_t; +typedef uint32_t hri_gmac_jr_reg_t; +typedef uint32_t hri_gmac_lc_reg_t; +typedef uint32_t hri_gmac_lffe_reg_t; +typedef uint32_t hri_gmac_man_reg_t; +typedef uint32_t hri_gmac_mcf_reg_t; +typedef uint32_t hri_gmac_mfr_reg_t; +typedef uint32_t hri_gmac_mft_reg_t; +typedef uint32_t hri_gmac_ncfgr_reg_t; +typedef uint32_t hri_gmac_ncr_reg_t; +typedef uint32_t hri_gmac_nsc_reg_t; +typedef uint32_t hri_gmac_nsr_reg_t; +typedef uint32_t hri_gmac_ofr_reg_t; +typedef uint32_t hri_gmac_orhi_reg_t; +typedef uint32_t hri_gmac_orlo_reg_t; +typedef uint32_t hri_gmac_othi_reg_t; +typedef uint32_t hri_gmac_otlo_reg_t; +typedef uint32_t hri_gmac_pefrn_reg_t; +typedef uint32_t hri_gmac_pefrsh_reg_t; +typedef uint32_t hri_gmac_pefrsl_reg_t; +typedef uint32_t hri_gmac_peftn_reg_t; +typedef uint32_t hri_gmac_peftsh_reg_t; +typedef uint32_t hri_gmac_peftsl_reg_t; +typedef uint32_t hri_gmac_pfr_reg_t; +typedef uint32_t hri_gmac_pft_reg_t; +typedef uint32_t hri_gmac_rbqb_reg_t; +typedef uint32_t hri_gmac_rbqbapq_reg_t; +typedef uint32_t hri_gmac_rbsrpq_reg_t; +typedef uint32_t hri_gmac_rjfml_reg_t; +typedef uint32_t hri_gmac_roe_reg_t; +typedef uint32_t hri_gmac_rpq_reg_t; +typedef uint32_t hri_gmac_rpsf_reg_t; +typedef uint32_t hri_gmac_rre_reg_t; +typedef uint32_t hri_gmac_rse_reg_t; +typedef uint32_t hri_gmac_rsr_reg_t; +typedef uint32_t hri_gmac_rxlpi_reg_t; +typedef uint32_t hri_gmac_rxlpitime_reg_t; +typedef uint32_t hri_gmac_sab_reg_t; +typedef uint32_t hri_gmac_samb1_reg_t; +typedef uint32_t hri_gmac_samt1_reg_t; +typedef uint32_t hri_gmac_sat_reg_t; +typedef uint32_t hri_gmac_scf_reg_t; +typedef uint32_t hri_gmac_sch_reg_t; +typedef uint32_t hri_gmac_scl_reg_t; +typedef uint32_t hri_gmac_st1rpq_reg_t; +typedef uint32_t hri_gmac_st2cw0_reg_t; +typedef uint32_t hri_gmac_st2cw1_reg_t; +typedef uint32_t hri_gmac_st2er_reg_t; +typedef uint32_t hri_gmac_st2rpq_reg_t; +typedef uint32_t hri_gmac_svlan_reg_t; +typedef uint32_t hri_gmac_ta_reg_t; +typedef uint32_t hri_gmac_tbfr1023_reg_t; +typedef uint32_t hri_gmac_tbfr127_reg_t; +typedef uint32_t hri_gmac_tbfr1518_reg_t; +typedef uint32_t hri_gmac_tbfr255_reg_t; +typedef uint32_t hri_gmac_tbfr511_reg_t; +typedef uint32_t hri_gmac_tbft1023_reg_t; +typedef uint32_t hri_gmac_tbft127_reg_t; +typedef uint32_t hri_gmac_tbft1518_reg_t; +typedef uint32_t hri_gmac_tbft255_reg_t; +typedef uint32_t hri_gmac_tbft511_reg_t; +typedef uint32_t hri_gmac_tbqb_reg_t; +typedef uint32_t hri_gmac_tbqbapq_reg_t; +typedef uint32_t hri_gmac_tce_reg_t; +typedef uint32_t hri_gmac_ti_reg_t; +typedef uint32_t hri_gmac_tidm1_reg_t; +typedef uint32_t hri_gmac_tidm2_reg_t; +typedef uint32_t hri_gmac_tidm3_reg_t; +typedef uint32_t hri_gmac_tidm4_reg_t; +typedef uint32_t hri_gmac_tisubn_reg_t; +typedef uint32_t hri_gmac_tmxbfr_reg_t; +typedef uint32_t hri_gmac_tn_reg_t; +typedef uint32_t hri_gmac_tpfcp_reg_t; +typedef uint32_t hri_gmac_tpq_reg_t; +typedef uint32_t hri_gmac_tpsf_reg_t; +typedef uint32_t hri_gmac_tsh_reg_t; +typedef uint32_t hri_gmac_tsl_reg_t; +typedef uint32_t hri_gmac_tsr_reg_t; +typedef uint32_t hri_gmac_tur_reg_t; +typedef uint32_t hri_gmac_txlpi_reg_t; +typedef uint32_t hri_gmac_txlpitime_reg_t; +typedef uint32_t hri_gmac_uce_reg_t; +typedef uint32_t hri_gmac_ufr_reg_t; +typedef uint32_t hri_gmac_ur_reg_t; +typedef uint32_t hri_gmac_wol_reg_t; +typedef uint32_t hri_gmacsa_sab_reg_t; +typedef uint32_t hri_gmacsa_sat_reg_t; +typedef uint32_t hri_gmacst2cw_st2cw0_reg_t; +typedef uint32_t hri_gmacst2cw_st2cw1_reg_t; + +static inline bool hri_gmac_get_ISR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_MFS) >> GMAC_ISR_MFS_Pos; +} + +static inline bool hri_gmac_get_ISR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_RCOMP) >> GMAC_ISR_RCOMP_Pos; +} + +static inline bool hri_gmac_get_ISR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_RXUBR) >> GMAC_ISR_RXUBR_Pos; +} + +static inline bool hri_gmac_get_ISR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_TXUBR) >> GMAC_ISR_TXUBR_Pos; +} + +static inline bool hri_gmac_get_ISR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_TUR) >> GMAC_ISR_TUR_Pos; +} + +static inline bool hri_gmac_get_ISR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_RLEX) >> GMAC_ISR_RLEX_Pos; +} + +static inline bool hri_gmac_get_ISR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_TFC) >> GMAC_ISR_TFC_Pos; +} + +static inline bool hri_gmac_get_ISR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_TCOMP) >> GMAC_ISR_TCOMP_Pos; +} + +static inline bool hri_gmac_get_ISR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_ROVR) >> GMAC_ISR_ROVR_Pos; +} + +static inline bool hri_gmac_get_ISR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_HRESP) >> GMAC_ISR_HRESP_Pos; +} + +static inline bool hri_gmac_get_ISR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PFNZ) >> GMAC_ISR_PFNZ_Pos; +} + +static inline bool hri_gmac_get_ISR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PTZ) >> GMAC_ISR_PTZ_Pos; +} + +static inline bool hri_gmac_get_ISR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PFTR) >> GMAC_ISR_PFTR_Pos; +} + +static inline bool hri_gmac_get_ISR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_DRQFR) >> GMAC_ISR_DRQFR_Pos; +} + +static inline bool hri_gmac_get_ISR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_SFR) >> GMAC_ISR_SFR_Pos; +} + +static inline bool hri_gmac_get_ISR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_DRQFT) >> GMAC_ISR_DRQFT_Pos; +} + +static inline bool hri_gmac_get_ISR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_SFT) >> GMAC_ISR_SFT_Pos; +} + +static inline bool hri_gmac_get_ISR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PDRQFR) >> GMAC_ISR_PDRQFR_Pos; +} + +static inline bool hri_gmac_get_ISR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PDRSFR) >> GMAC_ISR_PDRSFR_Pos; +} + +static inline bool hri_gmac_get_ISR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PDRQFT) >> GMAC_ISR_PDRQFT_Pos; +} + +static inline bool hri_gmac_get_ISR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_PDRSFT) >> GMAC_ISR_PDRSFT_Pos; +} + +static inline bool hri_gmac_get_ISR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_SRI) >> GMAC_ISR_SRI_Pos; +} + +static inline bool hri_gmac_get_ISR_RXLPISBC_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_RXLPISBC) >> GMAC_ISR_RXLPISBC_Pos; +} + +static inline bool hri_gmac_get_ISR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_WOL) >> GMAC_ISR_WOL_Pos; +} + +static inline bool hri_gmac_get_ISR_TSUTIMCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ISR & GMAC_ISR_TSUTIMCOMP) >> GMAC_ISR_TSUTIMCOMP_Pos; +} + +static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_ISR; +} + +static inline bool hri_gmac_get_ISRPQ_RCOMP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_RCOMP) >> GMAC_ISRPQ_RCOMP_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_RXUBR_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_RXUBR) >> GMAC_ISRPQ_RXUBR_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_RLEX_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_RLEX) >> GMAC_ISRPQ_RLEX_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_TFC_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_TFC) >> GMAC_ISRPQ_TFC_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_TCOMP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_TCOMP) >> GMAC_ISRPQ_TCOMP_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_ROVR_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_ROVR) >> GMAC_ISRPQ_ROVR_Pos; +} + +static inline bool hri_gmac_get_ISRPQ_HRESP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_ISRPQ[index] & GMAC_ISRPQ_HRESP) >> GMAC_ISRPQ_HRESP_Pos; +} + +static inline hri_gmac_isrpq_reg_t hri_gmac_get_ISRPQ_reg(const void *const hw, uint8_t index, + hri_gmac_isrpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ISRPQ[index]; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_isrpq_reg_t hri_gmac_read_ISRPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_ISRPQ[index]; +} + +static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_MFS; +} + +static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; +} + +static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_MFS; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_MFS; + } +} + +static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_MFS; +} + +static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RCOMP; +} + +static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RCOMP; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RCOMP; + } +} + +static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RCOMP; +} + +static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RXUBR; +} + +static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RXUBR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RXUBR; + } +} + +static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RXUBR; +} + +static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TXUBR; +} + +static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TXUBR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TXUBR; + } +} + +static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TXUBR; +} + +static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TUR; +} + +static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; +} + +static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TUR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TUR; + } +} + +static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TUR; +} + +static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RLEX; +} + +static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; +} + +static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RLEX; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RLEX; + } +} + +static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RLEX; +} + +static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TFC; +} + +static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; +} + +static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TFC; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TFC; + } +} + +static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TFC; +} + +static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TCOMP; +} + +static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TCOMP; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TCOMP; +} + +static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_ROVR; +} + +static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; +} + +static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_ROVR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_ROVR; + } +} + +static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_ROVR; +} + +static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_HRESP; +} + +static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; +} + +static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_HRESP; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_HRESP; + } +} + +static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_HRESP; +} + +static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PFNZ; +} + +static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; +} + +static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PFNZ; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PFNZ; + } +} + +static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PFNZ; +} + +static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PTZ; +} + +static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; +} + +static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PTZ; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PTZ; + } +} + +static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PTZ; +} + +static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PFTR; +} + +static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; +} + +static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PFTR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PFTR; + } +} + +static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PFTR; +} + +static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_EXINT; +} + +static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; +} + +static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_EXINT; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_EXINT; + } +} + +static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_EXINT; +} + +static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_DRQFR; +} + +static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_DRQFR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_DRQFR; + } +} + +static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_DRQFR; +} + +static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SFR; +} + +static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; +} + +static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SFR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SFR; + } +} + +static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SFR; +} + +static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_DRQFT; +} + +static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_DRQFT; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_DRQFT; + } +} + +static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_DRQFT; +} + +static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SFT; +} + +static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; +} + +static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SFT; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SFT; + } +} + +static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SFT; +} + +static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRQFR; +} + +static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRQFR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRQFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRQFR; +} + +static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRSFR; +} + +static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRSFR; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRSFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRSFR; +} + +static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRQFT; +} + +static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRQFT; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRQFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRQFT; +} + +static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRSFT; +} + +static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRSFT; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_PDRSFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_PDRSFT; +} + +static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SRI; +} + +static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; +} + +static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SRI; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_SRI; + } +} + +static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_SRI; +} + +static inline void hri_gmac_set_IMR_RXLPISBC_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RXLPISBC; +} + +static inline bool hri_gmac_get_IMR_RXLPISBC_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_RXLPISBC) >> GMAC_IMR_RXLPISBC_Pos; +} + +static inline void hri_gmac_write_IMR_RXLPISBC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RXLPISBC; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_RXLPISBC; + } +} + +static inline void hri_gmac_clear_IMR_RXLPISBC_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_RXLPISBC; +} + +static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_WOL; +} + +static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; +} + +static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_WOL; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_WOL; + } +} + +static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_WOL; +} + +static inline void hri_gmac_set_IMR_TSUTIMCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TSUTIMCOMP; +} + +static inline bool hri_gmac_get_IMR_TSUTIMCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IMR & GMAC_IMR_TSUTIMCOMP) >> GMAC_IMR_TSUTIMCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TSUTIMCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TSUTIMCOMP; + } else { + ((Gmac *)hw)->GMAC_IER = GMAC_IMR_TSUTIMCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TSUTIMCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->GMAC_IDR = GMAC_IMR_TSUTIMCOMP; +} + +static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->GMAC_IER = mask; +} + +static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_IMR; +} + +static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) +{ + ((Gmac *)hw)->GMAC_IER = data; + ((Gmac *)hw)->GMAC_IDR = ~data; +} + +static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->GMAC_IDR = mask; +} + +static inline void hri_gmac_set_IMRPQ_RCOMP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RCOMP; +} + +static inline bool hri_gmac_get_IMRPQ_RCOMP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_RCOMP) >> GMAC_IMRPQ_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMRPQ_RCOMP_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RCOMP; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RCOMP; + } +} + +static inline void hri_gmac_clear_IMRPQ_RCOMP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RCOMP; +} + +static inline void hri_gmac_set_IMRPQ_RXUBR_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RXUBR; +} + +static inline bool hri_gmac_get_IMRPQ_RXUBR_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_RXUBR) >> GMAC_IMRPQ_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMRPQ_RXUBR_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RXUBR; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RXUBR; + } +} + +static inline void hri_gmac_clear_IMRPQ_RXUBR_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RXUBR; +} + +static inline void hri_gmac_set_IMRPQ_RLEX_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RLEX; +} + +static inline bool hri_gmac_get_IMRPQ_RLEX_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_RLEX) >> GMAC_IMRPQ_RLEX_Pos; +} + +static inline void hri_gmac_write_IMRPQ_RLEX_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RLEX; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_RLEX; + } +} + +static inline void hri_gmac_clear_IMRPQ_RLEX_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_RLEX; +} + +static inline void hri_gmac_set_IMRPQ_AHB_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_AHB; +} + +static inline bool hri_gmac_get_IMRPQ_AHB_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_AHB) >> GMAC_IMRPQ_AHB_Pos; +} + +static inline void hri_gmac_write_IMRPQ_AHB_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_AHB; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_AHB; + } +} + +static inline void hri_gmac_clear_IMRPQ_AHB_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_AHB; +} + +static inline void hri_gmac_set_IMRPQ_TCOMP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_TCOMP; +} + +static inline bool hri_gmac_get_IMRPQ_TCOMP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_TCOMP) >> GMAC_IMRPQ_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMRPQ_TCOMP_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_TCOMP; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_TCOMP; + } +} + +static inline void hri_gmac_clear_IMRPQ_TCOMP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_TCOMP; +} + +static inline void hri_gmac_set_IMRPQ_ROVR_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_ROVR; +} + +static inline bool hri_gmac_get_IMRPQ_ROVR_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_ROVR) >> GMAC_IMRPQ_ROVR_Pos; +} + +static inline void hri_gmac_write_IMRPQ_ROVR_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_ROVR; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_ROVR; + } +} + +static inline void hri_gmac_clear_IMRPQ_ROVR_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_ROVR; +} + +static inline void hri_gmac_set_IMRPQ_HRESP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_HRESP; +} + +static inline bool hri_gmac_get_IMRPQ_HRESP_bit(const void *const hw, uint8_t index) +{ + return (((Gmac *)hw)->GMAC_IMRPQ[index] & GMAC_IMRPQ_HRESP) >> GMAC_IMRPQ_HRESP_Pos; +} + +static inline void hri_gmac_write_IMRPQ_HRESP_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_HRESP; + } else { + ((Gmac *)hw)->GMAC_IERPQ[index] = GMAC_IMRPQ_HRESP; + } +} + +static inline void hri_gmac_clear_IMRPQ_HRESP_bit(const void *const hw, uint8_t index) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = GMAC_IMRPQ_HRESP; +} + +static inline void hri_gmac_set_IMRPQ_reg(const void *const hw, uint8_t index, hri_gmac_imrpq_reg_t mask) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = mask; +} + +static inline hri_gmac_imrpq_reg_t hri_gmac_get_IMRPQ_reg(const void *const hw, uint8_t index, + hri_gmac_imrpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IMRPQ[index]; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imrpq_reg_t hri_gmac_read_IMRPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_IMRPQ[index]; +} + +static inline void hri_gmac_write_IMRPQ_reg(const void *const hw, uint8_t index, hri_gmac_imrpq_reg_t data) +{ + ((Gmac *)hw)->GMAC_IERPQ[index] = data; + ((Gmac *)hw)->GMAC_IDRPQ[index] = ~data; +} + +static inline void hri_gmac_clear_IMRPQ_reg(const void *const hw, uint8_t index, hri_gmac_imrpq_reg_t mask) +{ + ((Gmac *)hw)->GMAC_IDRPQ[index] = mask; +} + +static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_NSR & GMAC_NSR_MDIO) > 0; +} + +static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_NSR & GMAC_NSR_IDLE) > 0; +} + +static inline bool hri_gmac_get_NSR_RXLPIS_bit(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_NSR & GMAC_NSR_RXLPIS) > 0; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NSR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_NSR; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_RPQ & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_RPQ & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RPQ; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RPQ; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFTSH & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFTSH & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFTSH; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFTSH; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFRSH & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFRSH & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFRSH; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFRSH; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFTSH & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFTSH & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFTSH; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFTSH; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFRSH & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFRSH & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFRSH; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFRSH; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_OTLO & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_OTLO & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_OTLO; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_OTLO; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_OTHI & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_OTHI & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_OTHI; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_OTHI; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_FT & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_FT & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_FT; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_FT; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_BCFT & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_BCFT & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_BCFT; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_BCFT; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_MFT & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_MFT & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MFT; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_MFT; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PFT & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PFT & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PFT; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PFT; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_BFT64 & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_BFT64 & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_BFT64; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_BFT64; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFT127 & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFT127 & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFT127; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFT127; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFT255 & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFT255 & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFT255; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFT255; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFT511 & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFT511 & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFT511; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFT511; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFT1023 & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFT1023 & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFT1023; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFT1023; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFT1518 & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFT1518 & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFT1518; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFT1518; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, + hri_gmac_gtbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_GTBFT1518 & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_GTBFT1518 & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_GTBFT1518; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_GTBFT1518; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TUR & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TUR & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TUR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TUR; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_SCF & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_SCF & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCF; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SCF; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_MCF & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_MCF & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MCF; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_MCF; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EC & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EC & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EC; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EC; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_LC & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_LC & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_LC; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_LC; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_DTF & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_DTF & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DTF; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_DTF; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_CSE & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_CSE & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CSE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_CSE; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_ORLO & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ORLO & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ORLO; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_ORLO; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_ORHI & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ORHI & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ORHI; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_ORHI; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_FR & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_FR & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_FR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_FR; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_BCFR & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_BCFR & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_BCFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_BCFR; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_MFR & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_MFR & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_MFR; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PFR & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PFR & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PFR; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_BFR64 & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_BFR64 & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_BFR64; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_BFR64; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFR127 & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFR127 & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFR127; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFR127; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFR255 & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFR255 & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFR255; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFR255; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFR511 & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFR511 & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFR511; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFR511; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFR1023 & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFR1023 & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFR1023; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFR1023; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TBFR1518 & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TBFR1518 & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBFR1518; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBFR1518; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TMXBFR & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TMXBFR & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TMXBFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TMXBFR; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_UFR & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_UFR & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_UFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_UFR; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_OFR & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_OFR & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_OFR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_OFR; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_JR & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_JR & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_JR; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_JR; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_FCSE & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_FCSE & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_FCSE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_FCSE; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_LFFE & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_LFFE & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_LFFE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_LFFE; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_RSE & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_RSE & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RSE; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_AE & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_AE & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_AE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_AE; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_RRE & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_RRE & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RRE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RRE; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_ROE & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_ROE & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ROE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_ROE; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_IHCE & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_IHCE & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IHCE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_IHCE; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TCE & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TCE & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TCE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TCE; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_UCE & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_UCE & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_UCE; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_UCE; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFTSL & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFTSL & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFTSL; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFTSL; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFTN & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFTN & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFTN; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFTN; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFRSL & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFRSL & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFRSL; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFRSL; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_EFRN & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_EFRN & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_EFRN; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_EFRN; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFTSL & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFTSL & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFTSL; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFTSL; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFTN & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFTN & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFTN; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFTN; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFRSL & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFRSL & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFRSL; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFRSL; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_PEFRN & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_PEFRN & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_PEFRN; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_PEFRN; +} + +static inline hri_gmac_rxlpi_reg_t hri_gmac_get_RXLPI_COUNT_bf(const void *const hw, hri_gmac_rxlpi_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_RXLPI & GMAC_RXLPI_COUNT(mask)) >> GMAC_RXLPI_COUNT_Pos; +} + +static inline hri_gmac_rxlpi_reg_t hri_gmac_read_RXLPI_COUNT_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_RXLPI & GMAC_RXLPI_COUNT_Msk) >> GMAC_RXLPI_COUNT_Pos; +} + +static inline hri_gmac_rxlpi_reg_t hri_gmac_get_RXLPI_reg(const void *const hw, hri_gmac_rxlpi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RXLPI; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rxlpi_reg_t hri_gmac_read_RXLPI_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RXLPI; +} + +static inline hri_gmac_rxlpitime_reg_t hri_gmac_get_RXLPITIME_LPITIME_bf(const void *const hw, + hri_gmac_rxlpitime_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_RXLPITIME & GMAC_RXLPITIME_LPITIME(mask)) >> GMAC_RXLPITIME_LPITIME_Pos; +} + +static inline hri_gmac_rxlpitime_reg_t hri_gmac_read_RXLPITIME_LPITIME_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_RXLPITIME & GMAC_RXLPITIME_LPITIME_Msk) >> GMAC_RXLPITIME_LPITIME_Pos; +} + +static inline hri_gmac_rxlpitime_reg_t hri_gmac_get_RXLPITIME_reg(const void *const hw, hri_gmac_rxlpitime_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RXLPITIME; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rxlpitime_reg_t hri_gmac_read_RXLPITIME_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RXLPITIME; +} + +static inline hri_gmac_txlpi_reg_t hri_gmac_get_TXLPI_COUNT_bf(const void *const hw, hri_gmac_txlpi_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TXLPI & GMAC_TXLPI_COUNT(mask)) >> GMAC_TXLPI_COUNT_Pos; +} + +static inline hri_gmac_txlpi_reg_t hri_gmac_read_TXLPI_COUNT_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TXLPI & GMAC_TXLPI_COUNT_Msk) >> GMAC_TXLPI_COUNT_Pos; +} + +static inline hri_gmac_txlpi_reg_t hri_gmac_get_TXLPI_reg(const void *const hw, hri_gmac_txlpi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TXLPI; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_txlpi_reg_t hri_gmac_read_TXLPI_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TXLPI; +} + +static inline hri_gmac_txlpitime_reg_t hri_gmac_get_TXLPITIME_LPITIME_bf(const void *const hw, + hri_gmac_txlpitime_reg_t mask) +{ + return (((Gmac *)hw)->GMAC_TXLPITIME & GMAC_TXLPITIME_LPITIME(mask)) >> GMAC_TXLPITIME_LPITIME_Pos; +} + +static inline hri_gmac_txlpitime_reg_t hri_gmac_read_TXLPITIME_LPITIME_bf(const void *const hw) +{ + return (((Gmac *)hw)->GMAC_TXLPITIME & GMAC_TXLPITIME_LPITIME_Msk) >> GMAC_TXLPITIME_LPITIME_Pos; +} + +static inline hri_gmac_txlpitime_reg_t hri_gmac_get_TXLPITIME_reg(const void *const hw, hri_gmac_txlpitime_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TXLPITIME; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_txlpitime_reg_t hri_gmac_read_TXLPITIME_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TXLPITIME; +} + +static inline void hri_gmac_set_NCR_LBL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_LBL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_LBL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_LBL) >> GMAC_NCR_LBL_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_LBL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_LBL; + tmp |= value << GMAC_NCR_LBL_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_LBL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_LBL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_LBL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_LBL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_RXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_RXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_RXEN) >> GMAC_NCR_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_RXEN; + tmp |= value << GMAC_NCR_RXEN_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_RXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_RXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_RXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_RXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TXEN) >> GMAC_NCR_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TXEN; + tmp |= value << GMAC_NCR_TXEN_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TXEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TXEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_MPE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_MPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_MPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_MPE) >> GMAC_NCR_MPE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_MPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_MPE; + tmp |= value << GMAC_NCR_MPE_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_MPE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_MPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_MPE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_MPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_CLRSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_CLRSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_CLRSTAT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_CLRSTAT) >> GMAC_NCR_CLRSTAT_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_CLRSTAT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_CLRSTAT; + tmp |= value << GMAC_NCR_CLRSTAT_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_CLRSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_CLRSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_CLRSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_CLRSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_INCSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_INCSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_INCSTAT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_INCSTAT) >> GMAC_NCR_INCSTAT_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_INCSTAT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_INCSTAT; + tmp |= value << GMAC_NCR_INCSTAT_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_INCSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_INCSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_INCSTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_INCSTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_WESTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_WESTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_WESTAT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_WESTAT) >> GMAC_NCR_WESTAT_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_WESTAT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_WESTAT; + tmp |= value << GMAC_NCR_WESTAT_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_WESTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_WESTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_WESTAT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_WESTAT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_BP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_BP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_BP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_BP) >> GMAC_NCR_BP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_BP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_BP; + tmp |= value << GMAC_NCR_BP_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_BP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_BP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_BP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_BP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TSTART_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TSTART; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TSTART) >> GMAC_NCR_TSTART_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TSTART; + tmp |= value << GMAC_NCR_TSTART_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TSTART_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TSTART; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TSTART_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TSTART; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_THALT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_THALT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_THALT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_THALT) >> GMAC_NCR_THALT_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_THALT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_THALT; + tmp |= value << GMAC_NCR_THALT_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_THALT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_THALT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_THALT_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_THALT; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TXPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TXPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TXPF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TXPF) >> GMAC_NCR_TXPF_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TXPF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TXPF; + tmp |= value << GMAC_NCR_TXPF_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TXPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TXPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TXPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TXPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TXZQPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TXZQPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TXZQPF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TXZQPF) >> GMAC_NCR_TXZQPF_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TXZQPF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TXZQPF; + tmp |= value << GMAC_NCR_TXZQPF_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TXZQPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TXZQPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TXZQPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TXZQPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_SRTSM_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_SRTSM; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_SRTSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_SRTSM) >> GMAC_NCR_SRTSM_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_SRTSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_SRTSM; + tmp |= value << GMAC_NCR_SRTSM_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_SRTSM_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_SRTSM; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_SRTSM_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_SRTSM; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_ENPBPR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_ENPBPR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_ENPBPR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_ENPBPR) >> GMAC_NCR_ENPBPR_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_ENPBPR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_ENPBPR; + tmp |= value << GMAC_NCR_ENPBPR_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_ENPBPR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_ENPBPR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_ENPBPR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_ENPBPR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TXPBPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TXPBPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TXPBPF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TXPBPF) >> GMAC_NCR_TXPBPF_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TXPBPF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TXPBPF; + tmp |= value << GMAC_NCR_TXPBPF_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TXPBPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TXPBPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TXPBPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TXPBPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_FNP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_FNP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_FNP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_FNP) >> GMAC_NCR_FNP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_FNP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_FNP; + tmp |= value << GMAC_NCR_FNP_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_FNP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_FNP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_FNP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_FNP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_TXLPIEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= GMAC_NCR_TXLPIEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCR_TXLPIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp = (tmp & GMAC_NCR_TXLPIEN) >> GMAC_NCR_TXLPIEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCR_TXLPIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= ~GMAC_NCR_TXLPIEN; + tmp |= value << GMAC_NCR_TXLPIEN_Pos; + ((Gmac *)hw)->GMAC_NCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_TXLPIEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~GMAC_NCR_TXLPIEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_TXLPIEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= GMAC_NCR_TXLPIEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_NCR; +} + +static inline void hri_gmac_set_NCFGR_SPD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_SPD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_SPD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_SPD) >> GMAC_NCFGR_SPD_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_SPD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_SPD; + tmp |= value << GMAC_NCFGR_SPD_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_SPD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_SPD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_SPD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_FD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_FD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_FD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_FD) >> GMAC_NCFGR_FD_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_FD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_FD; + tmp |= value << GMAC_NCFGR_FD_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_FD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_FD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_FD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_FD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_DNVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_DNVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_DNVLAN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_DNVLAN) >> GMAC_NCFGR_DNVLAN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_DNVLAN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_DNVLAN; + tmp |= value << GMAC_NCFGR_DNVLAN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_DNVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_DNVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_DNVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_DNVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_JFRAME_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_JFRAME; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_JFRAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_JFRAME) >> GMAC_NCFGR_JFRAME_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_JFRAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_JFRAME; + tmp |= value << GMAC_NCFGR_JFRAME_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_JFRAME_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_JFRAME; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_JFRAME_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_JFRAME; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_CAF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_CAF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_CAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_CAF) >> GMAC_NCFGR_CAF_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_CAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_CAF; + tmp |= value << GMAC_NCFGR_CAF_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_CAF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_CAF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_CAF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_CAF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_NBC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_NBC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_NBC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_NBC) >> GMAC_NCFGR_NBC_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_NBC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_NBC; + tmp |= value << GMAC_NCFGR_NBC_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_NBC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_NBC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_NBC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_NBC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_MTIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_MTIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_MTIHEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_MTIHEN) >> GMAC_NCFGR_MTIHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_MTIHEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_MTIHEN; + tmp |= value << GMAC_NCFGR_MTIHEN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_MTIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_MTIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_MTIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_MTIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_UNIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_UNIHEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_UNIHEN) >> GMAC_NCFGR_UNIHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_UNIHEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_UNIHEN; + tmp |= value << GMAC_NCFGR_UNIHEN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_UNIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_UNIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_UNIHEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_UNIHEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_MAXFS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_MAXFS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_MAXFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_MAXFS) >> GMAC_NCFGR_MAXFS_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_MAXFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_MAXFS; + tmp |= value << GMAC_NCFGR_MAXFS_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_MAXFS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_MAXFS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_MAXFS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_MAXFS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_RTY_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_RTY; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_RTY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RTY) >> GMAC_NCFGR_RTY_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_RTY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_RTY; + tmp |= value << GMAC_NCFGR_RTY_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_RTY_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_RTY; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_RTY_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_RTY; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_PEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_PEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_PEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_PEN) >> GMAC_NCFGR_PEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_PEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_PEN; + tmp |= value << GMAC_NCFGR_PEN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_PEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_PEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_PEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_PEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_LFERD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_LFERD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_LFERD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_LFERD) >> GMAC_NCFGR_LFERD_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_LFERD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_LFERD; + tmp |= value << GMAC_NCFGR_LFERD_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_LFERD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_LFERD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_LFERD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_LFERD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_RFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_RFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_RFCS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RFCS) >> GMAC_NCFGR_RFCS_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_RFCS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_RFCS; + tmp |= value << GMAC_NCFGR_RFCS_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_RFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_RFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_RFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_RFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_DCPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_DCPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_DCPF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_DCPF) >> GMAC_NCFGR_DCPF_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_DCPF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_DCPF; + tmp |= value << GMAC_NCFGR_DCPF_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_DCPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_DCPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_DCPF_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_DCPF; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_RXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_RXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_RXCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RXCOEN) >> GMAC_NCFGR_RXCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_RXCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_RXCOEN; + tmp |= value << GMAC_NCFGR_RXCOEN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_RXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_RXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_RXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_RXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_EFRHD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_EFRHD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_EFRHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_EFRHD) >> GMAC_NCFGR_EFRHD_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_EFRHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_EFRHD; + tmp |= value << GMAC_NCFGR_EFRHD_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_EFRHD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_EFRHD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_EFRHD_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_EFRHD; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_IRXFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_IRXFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_IRXFCS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_IRXFCS) >> GMAC_NCFGR_IRXFCS_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_IRXFCS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_IRXFCS; + tmp |= value << GMAC_NCFGR_IRXFCS_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_IRXFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_IRXFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_IRXFCS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_IRXFCS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_IPGSEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_IPGSEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_IPGSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_IPGSEN) >> GMAC_NCFGR_IPGSEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_IPGSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_IPGSEN; + tmp |= value << GMAC_NCFGR_IPGSEN_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_IPGSEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_IPGSEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_IPGSEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_IPGSEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_RXBP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_RXBP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_RXBP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RXBP) >> GMAC_NCFGR_RXBP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_RXBP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_RXBP; + tmp |= value << GMAC_NCFGR_RXBP_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_RXBP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_RXBP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_RXBP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_RXBP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_IRXER_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_IRXER; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_NCFGR_IRXER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_IRXER) >> GMAC_NCFGR_IRXER_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_NCFGR_IRXER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_IRXER; + tmp |= value << GMAC_NCFGR_IRXER_Pos; + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_IRXER_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_IRXER; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_IRXER_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_IRXER; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_NCFGR_RXBUFO_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_RXBUFO_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RXBUFO(mask)) >> GMAC_NCFGR_RXBUFO_Pos; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_RXBUFO_bf(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_RXBUFO_Msk; + tmp |= GMAC_NCFGR_RXBUFO(data); + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_RXBUFO_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_RXBUFO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_RXBUFO_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_RXBUFO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_RXBUFO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_RXBUFO_Msk) >> GMAC_NCFGR_RXBUFO_Pos; + return tmp; +} + +static inline void hri_gmac_set_NCFGR_CLK_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_CLK(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_CLK_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_CLK(mask)) >> GMAC_NCFGR_CLK_Pos; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_CLK_bf(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_CLK_Msk; + tmp |= GMAC_NCFGR_CLK(data); + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_CLK_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_CLK(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_CLK_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_CLK(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_CLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_CLK_Msk) >> GMAC_NCFGR_CLK_Pos; + return tmp; +} + +static inline void hri_gmac_set_NCFGR_DBW_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= GMAC_NCFGR_DBW(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_DBW_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_DBW(mask)) >> GMAC_NCFGR_DBW_Pos; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_DBW_bf(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= ~GMAC_NCFGR_DBW_Msk; + tmp |= GMAC_NCFGR_DBW(data); + ((Gmac *)hw)->GMAC_NCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_DBW_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~GMAC_NCFGR_DBW(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_DBW_bf(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= GMAC_NCFGR_DBW(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_DBW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp = (tmp & GMAC_NCFGR_DBW_Msk) >> GMAC_NCFGR_DBW_Pos; + return tmp; +} + +static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NCFGR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NCFGR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_NCFGR; +} + +static inline void hri_gmac_set_UR_RMII_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR |= GMAC_UR_RMII; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_UR_RMII_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_UR; + tmp = (tmp & GMAC_UR_RMII) >> GMAC_UR_RMII_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_UR_RMII_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_UR; + tmp &= ~GMAC_UR_RMII; + tmp |= value << GMAC_UR_RMII_Pos; + ((Gmac *)hw)->GMAC_UR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_RMII_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR &= ~GMAC_UR_RMII; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_RMII_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR ^= GMAC_UR_RMII; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_UR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_UR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_UR; +} + +static inline void hri_gmac_set_DCFGR_ESMA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_ESMA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_DCFGR_ESMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_ESMA) >> GMAC_DCFGR_ESMA_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_DCFGR_ESMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_ESMA; + tmp |= value << GMAC_DCFGR_ESMA_Pos; + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_ESMA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_ESMA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_ESMA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_ESMA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_DCFGR_ESPA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_ESPA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_DCFGR_ESPA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_ESPA) >> GMAC_DCFGR_ESPA_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_DCFGR_ESPA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_ESPA; + tmp |= value << GMAC_DCFGR_ESPA_Pos; + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_ESPA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_ESPA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_ESPA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_ESPA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_DCFGR_TXPBMS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_TXPBMS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_DCFGR_TXPBMS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_TXPBMS) >> GMAC_DCFGR_TXPBMS_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_DCFGR_TXPBMS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_TXPBMS; + tmp |= value << GMAC_DCFGR_TXPBMS_Pos; + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_TXPBMS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_TXPBMS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_TXPBMS_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_TXPBMS; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_DCFGR_TXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_TXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_DCFGR_TXCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_TXCOEN) >> GMAC_DCFGR_TXCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_DCFGR_TXCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_TXCOEN; + tmp |= value << GMAC_DCFGR_TXCOEN_Pos; + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_TXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_TXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_TXCOEN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_TXCOEN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_DCFGR_DDRP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_DDRP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_DCFGR_DDRP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_DDRP) >> GMAC_DCFGR_DDRP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_DCFGR_DDRP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_DDRP; + tmp |= value << GMAC_DCFGR_DDRP_Pos; + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_DDRP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_DDRP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_DDRP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_DDRP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_DCFGR_FBLDO_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_FBLDO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_FBLDO_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_FBLDO(mask)) >> GMAC_DCFGR_FBLDO_Pos; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_FBLDO_bf(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_FBLDO_Msk; + tmp |= GMAC_DCFGR_FBLDO(data); + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_FBLDO_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_FBLDO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_FBLDO_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_FBLDO(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_FBLDO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_FBLDO_Msk) >> GMAC_DCFGR_FBLDO_Pos; + return tmp; +} + +static inline void hri_gmac_set_DCFGR_RXBMS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_RXBMS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_RXBMS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_RXBMS(mask)) >> GMAC_DCFGR_RXBMS_Pos; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_RXBMS_bf(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_RXBMS_Msk; + tmp |= GMAC_DCFGR_RXBMS(data); + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_RXBMS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_RXBMS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_RXBMS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_RXBMS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_RXBMS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_RXBMS_Msk) >> GMAC_DCFGR_RXBMS_Pos; + return tmp; +} + +static inline void hri_gmac_set_DCFGR_DRBS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= GMAC_DCFGR_DRBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_DRBS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_DRBS(mask)) >> GMAC_DCFGR_DRBS_Pos; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_DRBS_bf(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= ~GMAC_DCFGR_DRBS_Msk; + tmp |= GMAC_DCFGR_DRBS(data); + ((Gmac *)hw)->GMAC_DCFGR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_DRBS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~GMAC_DCFGR_DRBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_DRBS_bf(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= GMAC_DCFGR_DRBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_DRBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp = (tmp & GMAC_DCFGR_DRBS_Msk) >> GMAC_DCFGR_DRBS_Pos; + return tmp; +} + +static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_DCFGR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_DCFGR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_DCFGR; +} + +static inline void hri_gmac_set_TSR_UBR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_UBR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_UBR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_UBR) >> GMAC_TSR_UBR_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_UBR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_UBR; + tmp |= value << GMAC_TSR_UBR_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_UBR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_UBR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_UBR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_UBR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_COL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_COL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_COL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_COL) >> GMAC_TSR_COL_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_COL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_COL; + tmp |= value << GMAC_TSR_COL_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_COL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_COL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_COL_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_COL; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_RLE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_RLE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_RLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_RLE) >> GMAC_TSR_RLE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_RLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_RLE; + tmp |= value << GMAC_TSR_RLE_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_RLE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_RLE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_RLE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_RLE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_TXGO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_TXGO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_TXGO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_TXGO) >> GMAC_TSR_TXGO_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_TXGO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_TXGO; + tmp |= value << GMAC_TSR_TXGO_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_TXGO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_TXGO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_TXGO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_TXGO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_TFC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_TFC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_TFC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_TFC) >> GMAC_TSR_TFC_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_TFC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_TFC; + tmp |= value << GMAC_TSR_TFC_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_TFC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_TFC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_TFC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_TFC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_TXCOMP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_TXCOMP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_TXCOMP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_TXCOMP) >> GMAC_TSR_TXCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_TXCOMP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_TXCOMP; + tmp |= value << GMAC_TSR_TXCOMP_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_TXCOMP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_TXCOMP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_TXCOMP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_TXCOMP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_HRESP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= GMAC_TSR_HRESP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TSR_HRESP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp = (tmp & GMAC_TSR_HRESP) >> GMAC_TSR_HRESP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TSR_HRESP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= ~GMAC_TSR_HRESP; + tmp |= value << GMAC_TSR_HRESP_Pos; + ((Gmac *)hw)->GMAC_TSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_HRESP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~GMAC_TSR_HRESP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_HRESP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= GMAC_TSR_HRESP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TSR; +} + +static inline void hri_gmac_set_RBQB_ADDR_bf(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB |= GMAC_RBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_ADDR_bf(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQB; + tmp = (tmp & GMAC_RBQB_ADDR(mask)) >> GMAC_RBQB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_RBQB_ADDR_bf(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RBQB; + tmp &= ~GMAC_RBQB_ADDR_Msk; + tmp |= GMAC_RBQB_ADDR(data); + ((Gmac *)hw)->GMAC_RBQB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_ADDR_bf(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB &= ~GMAC_RBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_ADDR_bf(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB ^= GMAC_RBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQB; + tmp = (tmp & GMAC_RBQB_ADDR_Msk) >> GMAC_RBQB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RBQB; +} + +static inline void hri_gmac_set_TBQB_ADDR_bf(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB |= GMAC_TBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_ADDR_bf(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQB; + tmp = (tmp & GMAC_TBQB_ADDR(mask)) >> GMAC_TBQB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_TBQB_ADDR_bf(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TBQB; + tmp &= ~GMAC_TBQB_ADDR_Msk; + tmp |= GMAC_TBQB_ADDR(data); + ((Gmac *)hw)->GMAC_TBQB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_ADDR_bf(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB &= ~GMAC_TBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_ADDR_bf(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB ^= GMAC_TBQB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQB; + tmp = (tmp & GMAC_TBQB_ADDR_Msk) >> GMAC_TBQB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TBQB; +} + +static inline void hri_gmac_set_RSR_BNA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR |= GMAC_RSR_BNA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_RSR_BNA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp = (tmp & GMAC_RSR_BNA) >> GMAC_RSR_BNA_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_RSR_BNA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp &= ~GMAC_RSR_BNA; + tmp |= value << GMAC_RSR_BNA_Pos; + ((Gmac *)hw)->GMAC_RSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_BNA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR &= ~GMAC_RSR_BNA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_BNA_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR ^= GMAC_RSR_BNA; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_RSR_REC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR |= GMAC_RSR_REC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_RSR_REC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp = (tmp & GMAC_RSR_REC) >> GMAC_RSR_REC_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_RSR_REC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp &= ~GMAC_RSR_REC; + tmp |= value << GMAC_RSR_REC_Pos; + ((Gmac *)hw)->GMAC_RSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_REC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR &= ~GMAC_RSR_REC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_REC_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR ^= GMAC_RSR_REC; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_RSR_RXOVR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR |= GMAC_RSR_RXOVR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_RSR_RXOVR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp = (tmp & GMAC_RSR_RXOVR) >> GMAC_RSR_RXOVR_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_RSR_RXOVR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp &= ~GMAC_RSR_RXOVR; + tmp |= value << GMAC_RSR_RXOVR_Pos; + ((Gmac *)hw)->GMAC_RSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_RXOVR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR &= ~GMAC_RSR_RXOVR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_RXOVR_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR ^= GMAC_RSR_RXOVR; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_RSR_HNO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR |= GMAC_RSR_HNO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_RSR_HNO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp = (tmp & GMAC_RSR_HNO) >> GMAC_RSR_HNO_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_RSR_HNO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp &= ~GMAC_RSR_HNO; + tmp |= value << GMAC_RSR_HNO_Pos; + ((Gmac *)hw)->GMAC_RSR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_HNO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR &= ~GMAC_RSR_HNO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_HNO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR ^= GMAC_RSR_HNO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RSR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RSR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RSR; +} + +static inline void hri_gmac_set_MAN_CLTTO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_CLTTO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_MAN_CLTTO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_CLTTO) >> GMAC_MAN_CLTTO_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_MAN_CLTTO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_CLTTO; + tmp |= value << GMAC_MAN_CLTTO_Pos; + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_CLTTO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_CLTTO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_CLTTO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_CLTTO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_MAN_WZO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_WZO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_MAN_WZO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_WZO) >> GMAC_MAN_WZO_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_MAN_WZO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_WZO; + tmp |= value << GMAC_MAN_WZO_Pos; + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_WZO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_WZO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_WZO_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_WZO; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_MAN_DATA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_DATA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_DATA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_DATA(mask)) >> GMAC_MAN_DATA_Pos; + return tmp; +} + +static inline void hri_gmac_write_MAN_DATA_bf(const void *const hw, hri_gmac_man_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_DATA_Msk; + tmp |= GMAC_MAN_DATA(data); + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_DATA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_DATA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_DATA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_DATA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_DATA_Msk) >> GMAC_MAN_DATA_Pos; + return tmp; +} + +static inline void hri_gmac_set_MAN_WTN_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_WTN(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_WTN_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_WTN(mask)) >> GMAC_MAN_WTN_Pos; + return tmp; +} + +static inline void hri_gmac_write_MAN_WTN_bf(const void *const hw, hri_gmac_man_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_WTN_Msk; + tmp |= GMAC_MAN_WTN(data); + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_WTN_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_WTN(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_WTN_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_WTN(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_WTN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_WTN_Msk) >> GMAC_MAN_WTN_Pos; + return tmp; +} + +static inline void hri_gmac_set_MAN_REGA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_REGA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_REGA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_REGA(mask)) >> GMAC_MAN_REGA_Pos; + return tmp; +} + +static inline void hri_gmac_write_MAN_REGA_bf(const void *const hw, hri_gmac_man_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_REGA_Msk; + tmp |= GMAC_MAN_REGA(data); + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_REGA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_REGA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_REGA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_REGA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_REGA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_REGA_Msk) >> GMAC_MAN_REGA_Pos; + return tmp; +} + +static inline void hri_gmac_set_MAN_PHYA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_PHYA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_PHYA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_PHYA(mask)) >> GMAC_MAN_PHYA_Pos; + return tmp; +} + +static inline void hri_gmac_write_MAN_PHYA_bf(const void *const hw, hri_gmac_man_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_PHYA_Msk; + tmp |= GMAC_MAN_PHYA(data); + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_PHYA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_PHYA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_PHYA_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_PHYA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_PHYA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_PHYA_Msk) >> GMAC_MAN_PHYA_Pos; + return tmp; +} + +static inline void hri_gmac_set_MAN_OP_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= GMAC_MAN_OP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_OP_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_OP(mask)) >> GMAC_MAN_OP_Pos; + return tmp; +} + +static inline void hri_gmac_write_MAN_OP_bf(const void *const hw, hri_gmac_man_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= ~GMAC_MAN_OP_Msk; + tmp |= GMAC_MAN_OP(data); + ((Gmac *)hw)->GMAC_MAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_OP_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~GMAC_MAN_OP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_OP_bf(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= GMAC_MAN_OP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_OP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp = (tmp & GMAC_MAN_OP_Msk) >> GMAC_MAN_OP_Pos; + return tmp; +} + +static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_MAN; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_MAN ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_MAN; +} + +static inline void hri_gmac_set_TPQ_TPQ_bf(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ |= GMAC_TPQ_TPQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_TPQ_bf(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPQ; + tmp = (tmp & GMAC_TPQ_TPQ(mask)) >> GMAC_TPQ_TPQ_Pos; + return tmp; +} + +static inline void hri_gmac_write_TPQ_TPQ_bf(const void *const hw, hri_gmac_tpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TPQ; + tmp &= ~GMAC_TPQ_TPQ_Msk; + tmp |= GMAC_TPQ_TPQ(data); + ((Gmac *)hw)->GMAC_TPQ = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_TPQ_bf(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ &= ~GMAC_TPQ_TPQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_TPQ_bf(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ ^= GMAC_TPQ_TPQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_TPQ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPQ; + tmp = (tmp & GMAC_TPQ_TPQ_Msk) >> GMAC_TPQ_TPQ_Pos; + return tmp; +} + +static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPQ; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPQ ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TPQ; +} + +static inline void hri_gmac_set_TPSF_ENTXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF |= GMAC_TPSF_ENTXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TPSF_ENTXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp = (tmp & GMAC_TPSF_ENTXP) >> GMAC_TPSF_ENTXP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TPSF_ENTXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp &= ~GMAC_TPSF_ENTXP; + tmp |= value << GMAC_TPSF_ENTXP_Pos; + ((Gmac *)hw)->GMAC_TPSF = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_ENTXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF &= ~GMAC_TPSF_ENTXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_ENTXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF ^= GMAC_TPSF_ENTXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TPSF_TPB1ADR_bf(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF |= GMAC_TPSF_TPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_TPB1ADR_bf(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp = (tmp & GMAC_TPSF_TPB1ADR(mask)) >> GMAC_TPSF_TPB1ADR_Pos; + return tmp; +} + +static inline void hri_gmac_write_TPSF_TPB1ADR_bf(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp &= ~GMAC_TPSF_TPB1ADR_Msk; + tmp |= GMAC_TPSF_TPB1ADR(data); + ((Gmac *)hw)->GMAC_TPSF = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_TPB1ADR_bf(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF &= ~GMAC_TPSF_TPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_TPB1ADR_bf(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF ^= GMAC_TPSF_TPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_TPB1ADR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp = (tmp & GMAC_TPSF_TPB1ADR_Msk) >> GMAC_TPSF_TPB1ADR_Pos; + return tmp; +} + +static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPSF; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPSF ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TPSF; +} + +static inline void hri_gmac_set_RPSF_ENRXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF |= GMAC_RPSF_ENRXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_RPSF_ENRXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp = (tmp & GMAC_RPSF_ENRXP) >> GMAC_RPSF_ENRXP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_RPSF_ENRXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp &= ~GMAC_RPSF_ENRXP; + tmp |= value << GMAC_RPSF_ENRXP_Pos; + ((Gmac *)hw)->GMAC_RPSF = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_ENRXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF &= ~GMAC_RPSF_ENRXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_ENRXP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF ^= GMAC_RPSF_ENRXP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_RPSF_RPB1ADR_bf(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF |= GMAC_RPSF_RPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_RPB1ADR_bf(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp = (tmp & GMAC_RPSF_RPB1ADR(mask)) >> GMAC_RPSF_RPB1ADR_Pos; + return tmp; +} + +static inline void hri_gmac_write_RPSF_RPB1ADR_bf(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp &= ~GMAC_RPSF_RPB1ADR_Msk; + tmp |= GMAC_RPSF_RPB1ADR(data); + ((Gmac *)hw)->GMAC_RPSF = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_RPB1ADR_bf(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF &= ~GMAC_RPSF_RPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_RPB1ADR_bf(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF ^= GMAC_RPSF_RPB1ADR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_RPB1ADR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp = (tmp & GMAC_RPSF_RPB1ADR_Msk) >> GMAC_RPSF_RPB1ADR_Pos; + return tmp; +} + +static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RPSF; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RPSF ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RPSF; +} + +static inline void hri_gmac_set_RJFML_FML_bf(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML |= GMAC_RJFML_FML(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_FML_bf(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RJFML; + tmp = (tmp & GMAC_RJFML_FML(mask)) >> GMAC_RJFML_FML_Pos; + return tmp; +} + +static inline void hri_gmac_write_RJFML_FML_bf(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RJFML; + tmp &= ~GMAC_RJFML_FML_Msk; + tmp |= GMAC_RJFML_FML(data); + ((Gmac *)hw)->GMAC_RJFML = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_FML_bf(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML &= ~GMAC_RJFML_FML(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_FML_bf(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML ^= GMAC_RJFML_FML(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_FML_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RJFML; + tmp = (tmp & GMAC_RJFML_FML_Msk) >> GMAC_RJFML_FML_Pos; + return tmp; +} + +static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RJFML; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RJFML ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_RJFML; +} + +static inline void hri_gmac_set_HRB_ADDR_bf(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB |= GMAC_HRB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_ADDR_bf(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRB; + tmp = (tmp & GMAC_HRB_ADDR(mask)) >> GMAC_HRB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_HRB_ADDR_bf(const void *const hw, hri_gmac_hrb_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_HRB; + tmp &= ~GMAC_HRB_ADDR_Msk; + tmp |= GMAC_HRB_ADDR(data); + ((Gmac *)hw)->GMAC_HRB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_ADDR_bf(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB &= ~GMAC_HRB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_ADDR_bf(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB ^= GMAC_HRB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRB; + tmp = (tmp & GMAC_HRB_ADDR_Msk) >> GMAC_HRB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_HRB; +} + +static inline void hri_gmac_set_HRT_ADDR_bf(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT |= GMAC_HRT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_ADDR_bf(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRT; + tmp = (tmp & GMAC_HRT_ADDR(mask)) >> GMAC_HRT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_HRT_ADDR_bf(const void *const hw, hri_gmac_hrt_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_HRT; + tmp &= ~GMAC_HRT_ADDR_Msk; + tmp |= GMAC_HRT_ADDR(data); + ((Gmac *)hw)->GMAC_HRT = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_ADDR_bf(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT &= ~GMAC_HRT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_ADDR_bf(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT ^= GMAC_HRT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRT; + tmp = (tmp & GMAC_HRT_ADDR_Msk) >> GMAC_HRT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_HRT; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_HRT ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_HRT; +} + +static inline void hri_gmac_set_TIDM1_ENID1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 |= GMAC_TIDM1_ENID1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TIDM1_ENID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp = (tmp & GMAC_TIDM1_ENID1) >> GMAC_TIDM1_ENID1_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TIDM1_ENID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp &= ~GMAC_TIDM1_ENID1; + tmp |= value << GMAC_TIDM1_ENID1_Pos; + ((Gmac *)hw)->GMAC_TIDM1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM1_ENID1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 &= ~GMAC_TIDM1_ENID1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM1_ENID1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 ^= GMAC_TIDM1_ENID1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TIDM1_TID_bf(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 |= GMAC_TIDM1_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm1_reg_t hri_gmac_get_TIDM1_TID_bf(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp = (tmp & GMAC_TIDM1_TID(mask)) >> GMAC_TIDM1_TID_Pos; + return tmp; +} + +static inline void hri_gmac_write_TIDM1_TID_bf(const void *const hw, hri_gmac_tidm1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp &= ~GMAC_TIDM1_TID_Msk; + tmp |= GMAC_TIDM1_TID(data); + ((Gmac *)hw)->GMAC_TIDM1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM1_TID_bf(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 &= ~GMAC_TIDM1_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM1_TID_bf(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 ^= GMAC_TIDM1_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm1_reg_t hri_gmac_read_TIDM1_TID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp = (tmp & GMAC_TIDM1_TID_Msk) >> GMAC_TIDM1_TID_Pos; + return tmp; +} + +static inline void hri_gmac_set_TIDM1_reg(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm1_reg_t hri_gmac_get_TIDM1_reg(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM1; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM1_reg(const void *const hw, hri_gmac_tidm1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM1_reg(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM1_reg(const void *const hw, hri_gmac_tidm1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM1 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm1_reg_t hri_gmac_read_TIDM1_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TIDM1; +} + +static inline void hri_gmac_set_TIDM2_ENID2_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 |= GMAC_TIDM2_ENID2; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TIDM2_ENID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp = (tmp & GMAC_TIDM2_ENID2) >> GMAC_TIDM2_ENID2_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TIDM2_ENID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp &= ~GMAC_TIDM2_ENID2; + tmp |= value << GMAC_TIDM2_ENID2_Pos; + ((Gmac *)hw)->GMAC_TIDM2 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM2_ENID2_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 &= ~GMAC_TIDM2_ENID2; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM2_ENID2_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 ^= GMAC_TIDM2_ENID2; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TIDM2_TID_bf(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 |= GMAC_TIDM2_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm2_reg_t hri_gmac_get_TIDM2_TID_bf(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp = (tmp & GMAC_TIDM2_TID(mask)) >> GMAC_TIDM2_TID_Pos; + return tmp; +} + +static inline void hri_gmac_write_TIDM2_TID_bf(const void *const hw, hri_gmac_tidm2_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp &= ~GMAC_TIDM2_TID_Msk; + tmp |= GMAC_TIDM2_TID(data); + ((Gmac *)hw)->GMAC_TIDM2 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM2_TID_bf(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 &= ~GMAC_TIDM2_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM2_TID_bf(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 ^= GMAC_TIDM2_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm2_reg_t hri_gmac_read_TIDM2_TID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp = (tmp & GMAC_TIDM2_TID_Msk) >> GMAC_TIDM2_TID_Pos; + return tmp; +} + +static inline void hri_gmac_set_TIDM2_reg(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm2_reg_t hri_gmac_get_TIDM2_reg(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM2; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM2_reg(const void *const hw, hri_gmac_tidm2_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM2_reg(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM2_reg(const void *const hw, hri_gmac_tidm2_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM2 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm2_reg_t hri_gmac_read_TIDM2_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TIDM2; +} + +static inline void hri_gmac_set_TIDM3_ENID3_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 |= GMAC_TIDM3_ENID3; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TIDM3_ENID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp = (tmp & GMAC_TIDM3_ENID3) >> GMAC_TIDM3_ENID3_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TIDM3_ENID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp &= ~GMAC_TIDM3_ENID3; + tmp |= value << GMAC_TIDM3_ENID3_Pos; + ((Gmac *)hw)->GMAC_TIDM3 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM3_ENID3_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 &= ~GMAC_TIDM3_ENID3; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM3_ENID3_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 ^= GMAC_TIDM3_ENID3; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TIDM3_TID_bf(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 |= GMAC_TIDM3_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm3_reg_t hri_gmac_get_TIDM3_TID_bf(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp = (tmp & GMAC_TIDM3_TID(mask)) >> GMAC_TIDM3_TID_Pos; + return tmp; +} + +static inline void hri_gmac_write_TIDM3_TID_bf(const void *const hw, hri_gmac_tidm3_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp &= ~GMAC_TIDM3_TID_Msk; + tmp |= GMAC_TIDM3_TID(data); + ((Gmac *)hw)->GMAC_TIDM3 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM3_TID_bf(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 &= ~GMAC_TIDM3_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM3_TID_bf(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 ^= GMAC_TIDM3_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm3_reg_t hri_gmac_read_TIDM3_TID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp = (tmp & GMAC_TIDM3_TID_Msk) >> GMAC_TIDM3_TID_Pos; + return tmp; +} + +static inline void hri_gmac_set_TIDM3_reg(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm3_reg_t hri_gmac_get_TIDM3_reg(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM3; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM3_reg(const void *const hw, hri_gmac_tidm3_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM3_reg(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM3_reg(const void *const hw, hri_gmac_tidm3_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM3 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm3_reg_t hri_gmac_read_TIDM3_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TIDM3; +} + +static inline void hri_gmac_set_TIDM4_ENID4_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 |= GMAC_TIDM4_ENID4; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_TIDM4_ENID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp = (tmp & GMAC_TIDM4_ENID4) >> GMAC_TIDM4_ENID4_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_TIDM4_ENID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp &= ~GMAC_TIDM4_ENID4; + tmp |= value << GMAC_TIDM4_ENID4_Pos; + ((Gmac *)hw)->GMAC_TIDM4 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM4_ENID4_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 &= ~GMAC_TIDM4_ENID4; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM4_ENID4_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 ^= GMAC_TIDM4_ENID4; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_TIDM4_TID_bf(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 |= GMAC_TIDM4_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm4_reg_t hri_gmac_get_TIDM4_TID_bf(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp = (tmp & GMAC_TIDM4_TID(mask)) >> GMAC_TIDM4_TID_Pos; + return tmp; +} + +static inline void hri_gmac_write_TIDM4_TID_bf(const void *const hw, hri_gmac_tidm4_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp &= ~GMAC_TIDM4_TID_Msk; + tmp |= GMAC_TIDM4_TID(data); + ((Gmac *)hw)->GMAC_TIDM4 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM4_TID_bf(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 &= ~GMAC_TIDM4_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM4_TID_bf(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 ^= GMAC_TIDM4_TID(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm4_reg_t hri_gmac_read_TIDM4_TID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp = (tmp & GMAC_TIDM4_TID_Msk) >> GMAC_TIDM4_TID_Pos; + return tmp; +} + +static inline void hri_gmac_set_TIDM4_reg(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm4_reg_t hri_gmac_get_TIDM4_reg(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TIDM4; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM4_reg(const void *const hw, hri_gmac_tidm4_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM4_reg(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM4_reg(const void *const hw, hri_gmac_tidm4_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TIDM4 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm4_reg_t hri_gmac_read_TIDM4_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TIDM4; +} + +static inline void hri_gmac_set_WOL_MAG_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= GMAC_WOL_MAG; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_WOL_MAG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_MAG) >> GMAC_WOL_MAG_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_WOL_MAG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= ~GMAC_WOL_MAG; + tmp |= value << GMAC_WOL_MAG_Pos; + ((Gmac *)hw)->GMAC_WOL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_MAG_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~GMAC_WOL_MAG; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_MAG_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= GMAC_WOL_MAG; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_WOL_ARP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= GMAC_WOL_ARP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_WOL_ARP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_ARP) >> GMAC_WOL_ARP_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_WOL_ARP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= ~GMAC_WOL_ARP; + tmp |= value << GMAC_WOL_ARP_Pos; + ((Gmac *)hw)->GMAC_WOL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_ARP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~GMAC_WOL_ARP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_ARP_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= GMAC_WOL_ARP; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_WOL_SA1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= GMAC_WOL_SA1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_WOL_SA1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_SA1) >> GMAC_WOL_SA1_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_WOL_SA1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= ~GMAC_WOL_SA1; + tmp |= value << GMAC_WOL_SA1_Pos; + ((Gmac *)hw)->GMAC_WOL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_SA1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~GMAC_WOL_SA1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_SA1_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= GMAC_WOL_SA1; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_WOL_MTI_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= GMAC_WOL_MTI; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_WOL_MTI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_MTI) >> GMAC_WOL_MTI_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_WOL_MTI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= ~GMAC_WOL_MTI; + tmp |= value << GMAC_WOL_MTI_Pos; + ((Gmac *)hw)->GMAC_WOL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_MTI_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~GMAC_WOL_MTI; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_MTI_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= GMAC_WOL_MTI; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_WOL_IP_bf(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= GMAC_WOL_IP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_IP_bf(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_IP(mask)) >> GMAC_WOL_IP_Pos; + return tmp; +} + +static inline void hri_gmac_write_WOL_IP_bf(const void *const hw, hri_gmac_wol_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= ~GMAC_WOL_IP_Msk; + tmp |= GMAC_WOL_IP(data); + ((Gmac *)hw)->GMAC_WOL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_IP_bf(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~GMAC_WOL_IP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_IP_bf(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= GMAC_WOL_IP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_IP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp = (tmp & GMAC_WOL_IP_Msk) >> GMAC_WOL_IP_Pos; + return tmp; +} + +static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_WOL; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_WOL ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_WOL; +} + +static inline void hri_gmac_set_IPGS_FL_bf(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS |= GMAC_IPGS_FL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_FL_bf(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IPGS; + tmp = (tmp & GMAC_IPGS_FL(mask)) >> GMAC_IPGS_FL_Pos; + return tmp; +} + +static inline void hri_gmac_write_IPGS_FL_bf(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_IPGS; + tmp &= ~GMAC_IPGS_FL_Msk; + tmp |= GMAC_IPGS_FL(data); + ((Gmac *)hw)->GMAC_IPGS = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_FL_bf(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS &= ~GMAC_IPGS_FL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_FL_bf(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS ^= GMAC_IPGS_FL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_FL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IPGS; + tmp = (tmp & GMAC_IPGS_FL_Msk) >> GMAC_IPGS_FL_Pos; + return tmp; +} + +static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_IPGS; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_IPGS ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_IPGS; +} + +static inline void hri_gmac_set_SVLAN_ESVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN |= GMAC_SVLAN_ESVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_SVLAN_ESVLAN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp = (tmp & GMAC_SVLAN_ESVLAN) >> GMAC_SVLAN_ESVLAN_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_SVLAN_ESVLAN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp &= ~GMAC_SVLAN_ESVLAN; + tmp |= value << GMAC_SVLAN_ESVLAN_Pos; + ((Gmac *)hw)->GMAC_SVLAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_ESVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN &= ~GMAC_SVLAN_ESVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_ESVLAN_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN ^= GMAC_SVLAN_ESVLAN; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_SVLAN_VLAN_TYPE_bf(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN |= GMAC_SVLAN_VLAN_TYPE(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_VLAN_TYPE_bf(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp = (tmp & GMAC_SVLAN_VLAN_TYPE(mask)) >> GMAC_SVLAN_VLAN_TYPE_Pos; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_VLAN_TYPE_bf(const void *const hw, hri_gmac_svlan_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp &= ~GMAC_SVLAN_VLAN_TYPE_Msk; + tmp |= GMAC_SVLAN_VLAN_TYPE(data); + ((Gmac *)hw)->GMAC_SVLAN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_VLAN_TYPE_bf(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN &= ~GMAC_SVLAN_VLAN_TYPE(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_VLAN_TYPE_bf(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN ^= GMAC_SVLAN_VLAN_TYPE(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_VLAN_TYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp = (tmp & GMAC_SVLAN_VLAN_TYPE_Msk) >> GMAC_SVLAN_VLAN_TYPE_Pos; + return tmp; +} + +static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SVLAN; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SVLAN ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SVLAN; +} + +static inline void hri_gmac_set_TPFCP_PEV_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP |= GMAC_TPFCP_PEV(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_PEV_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp = (tmp & GMAC_TPFCP_PEV(mask)) >> GMAC_TPFCP_PEV_Pos; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_PEV_bf(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp &= ~GMAC_TPFCP_PEV_Msk; + tmp |= GMAC_TPFCP_PEV(data); + ((Gmac *)hw)->GMAC_TPFCP = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_PEV_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP &= ~GMAC_TPFCP_PEV(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_PEV_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP ^= GMAC_TPFCP_PEV(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_PEV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp = (tmp & GMAC_TPFCP_PEV_Msk) >> GMAC_TPFCP_PEV_Pos; + return tmp; +} + +static inline void hri_gmac_set_TPFCP_PQ_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP |= GMAC_TPFCP_PQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_PQ_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp = (tmp & GMAC_TPFCP_PQ(mask)) >> GMAC_TPFCP_PQ_Pos; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_PQ_bf(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp &= ~GMAC_TPFCP_PQ_Msk; + tmp |= GMAC_TPFCP_PQ(data); + ((Gmac *)hw)->GMAC_TPFCP = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_PQ_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP &= ~GMAC_TPFCP_PQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_PQ_bf(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP ^= GMAC_TPFCP_PQ(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_PQ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp = (tmp & GMAC_TPFCP_PQ_Msk) >> GMAC_TPFCP_PQ_Pos; + return tmp; +} + +static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TPFCP; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TPFCP ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TPFCP; +} + +static inline void hri_gmac_set_SAMB1_ADDR_bf(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 |= GMAC_SAMB1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_ADDR_bf(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMB1; + tmp = (tmp & GMAC_SAMB1_ADDR(mask)) >> GMAC_SAMB1_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_ADDR_bf(const void *const hw, hri_gmac_samb1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SAMB1; + tmp &= ~GMAC_SAMB1_ADDR_Msk; + tmp |= GMAC_SAMB1_ADDR(data); + ((Gmac *)hw)->GMAC_SAMB1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_ADDR_bf(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 &= ~GMAC_SAMB1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_ADDR_bf(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 ^= GMAC_SAMB1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMB1; + tmp = (tmp & GMAC_SAMB1_ADDR_Msk) >> GMAC_SAMB1_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMB1; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMB1 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SAMB1; +} + +static inline void hri_gmac_set_SAMT1_ADDR_bf(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 |= GMAC_SAMT1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_ADDR_bf(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMT1; + tmp = (tmp & GMAC_SAMT1_ADDR(mask)) >> GMAC_SAMT1_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_ADDR_bf(const void *const hw, hri_gmac_samt1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SAMT1; + tmp &= ~GMAC_SAMT1_ADDR_Msk; + tmp |= GMAC_SAMT1_ADDR(data); + ((Gmac *)hw)->GMAC_SAMT1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_ADDR_bf(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 &= ~GMAC_SAMT1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_ADDR_bf(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 ^= GMAC_SAMT1_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMT1; + tmp = (tmp & GMAC_SAMT1_ADDR_Msk) >> GMAC_SAMT1_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SAMT1; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SAMT1 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SAMT1; +} + +static inline void hri_gmac_set_NSC_NANOSEC_bf(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC |= GMAC_NSC_NANOSEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_NANOSEC_bf(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NSC; + tmp = (tmp & GMAC_NSC_NANOSEC(mask)) >> GMAC_NSC_NANOSEC_Pos; + return tmp; +} + +static inline void hri_gmac_write_NSC_NANOSEC_bf(const void *const hw, hri_gmac_nsc_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_NSC; + tmp &= ~GMAC_NSC_NANOSEC_Msk; + tmp |= GMAC_NSC_NANOSEC(data); + ((Gmac *)hw)->GMAC_NSC = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_NANOSEC_bf(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC &= ~GMAC_NSC_NANOSEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_NANOSEC_bf(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC ^= GMAC_NSC_NANOSEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_NANOSEC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NSC; + tmp = (tmp & GMAC_NSC_NANOSEC_Msk) >> GMAC_NSC_NANOSEC_Pos; + return tmp; +} + +static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_NSC; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_NSC ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_NSC; +} + +static inline void hri_gmac_set_SCL_SEC_bf(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL |= GMAC_SCL_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_SEC_bf(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCL; + tmp = (tmp & GMAC_SCL_SEC(mask)) >> GMAC_SCL_SEC_Pos; + return tmp; +} + +static inline void hri_gmac_write_SCL_SEC_bf(const void *const hw, hri_gmac_scl_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SCL; + tmp &= ~GMAC_SCL_SEC_Msk; + tmp |= GMAC_SCL_SEC(data); + ((Gmac *)hw)->GMAC_SCL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_SEC_bf(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL &= ~GMAC_SCL_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_SEC_bf(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL ^= GMAC_SCL_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_SEC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCL; + tmp = (tmp & GMAC_SCL_SEC_Msk) >> GMAC_SCL_SEC_Pos; + return tmp; +} + +static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCL; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCL ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SCL; +} + +static inline void hri_gmac_set_SCH_SEC_bf(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH |= GMAC_SCH_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_SEC_bf(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCH; + tmp = (tmp & GMAC_SCH_SEC(mask)) >> GMAC_SCH_SEC_Pos; + return tmp; +} + +static inline void hri_gmac_write_SCH_SEC_bf(const void *const hw, hri_gmac_sch_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_SCH; + tmp &= ~GMAC_SCH_SEC_Msk; + tmp |= GMAC_SCH_SEC(data); + ((Gmac *)hw)->GMAC_SCH = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_SEC_bf(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH &= ~GMAC_SCH_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_SEC_bf(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH ^= GMAC_SCH_SEC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_SEC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCH; + tmp = (tmp & GMAC_SCH_SEC_Msk) >> GMAC_SCH_SEC_Pos; + return tmp; +} + +static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_SCH; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_SCH ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_SCH; +} + +static inline void hri_gmac_set_TISUBN_LSBTIR_bf(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN |= GMAC_TISUBN_LSBTIR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_LSBTIR_bf(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TISUBN; + tmp = (tmp & GMAC_TISUBN_LSBTIR(mask)) >> GMAC_TISUBN_LSBTIR_Pos; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_LSBTIR_bf(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TISUBN; + tmp &= ~GMAC_TISUBN_LSBTIR_Msk; + tmp |= GMAC_TISUBN_LSBTIR(data); + ((Gmac *)hw)->GMAC_TISUBN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_LSBTIR_bf(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN &= ~GMAC_TISUBN_LSBTIR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_LSBTIR_bf(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN ^= GMAC_TISUBN_LSBTIR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_LSBTIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TISUBN; + tmp = (tmp & GMAC_TISUBN_LSBTIR_Msk) >> GMAC_TISUBN_LSBTIR_Pos; + return tmp; +} + +static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TISUBN; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TISUBN ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TISUBN; +} + +static inline void hri_gmac_set_TSH_TCS_bf(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH |= GMAC_TSH_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_TCS_bf(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSH; + tmp = (tmp & GMAC_TSH_TCS(mask)) >> GMAC_TSH_TCS_Pos; + return tmp; +} + +static inline void hri_gmac_write_TSH_TCS_bf(const void *const hw, hri_gmac_tsh_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSH; + tmp &= ~GMAC_TSH_TCS_Msk; + tmp |= GMAC_TSH_TCS(data); + ((Gmac *)hw)->GMAC_TSH = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_TCS_bf(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH &= ~GMAC_TSH_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_TCS_bf(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH ^= GMAC_TSH_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_TCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSH; + tmp = (tmp & GMAC_TSH_TCS_Msk) >> GMAC_TSH_TCS_Pos; + return tmp; +} + +static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSH; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSH ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TSH; +} + +static inline void hri_gmac_set_TSL_TCS_bf(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL |= GMAC_TSL_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_TCS_bf(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSL; + tmp = (tmp & GMAC_TSL_TCS(mask)) >> GMAC_TSL_TCS_Pos; + return tmp; +} + +static inline void hri_gmac_write_TSL_TCS_bf(const void *const hw, hri_gmac_tsl_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TSL; + tmp &= ~GMAC_TSL_TCS_Msk; + tmp |= GMAC_TSL_TCS(data); + ((Gmac *)hw)->GMAC_TSL = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_TCS_bf(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL &= ~GMAC_TSL_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_TCS_bf(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL ^= GMAC_TSL_TCS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_TCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSL; + tmp = (tmp & GMAC_TSL_TCS_Msk) >> GMAC_TSL_TCS_Pos; + return tmp; +} + +static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TSL; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TSL ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TSL; +} + +static inline void hri_gmac_set_TN_TNS_bf(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN |= GMAC_TN_TNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_TNS_bf(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TN; + tmp = (tmp & GMAC_TN_TNS(mask)) >> GMAC_TN_TNS_Pos; + return tmp; +} + +static inline void hri_gmac_write_TN_TNS_bf(const void *const hw, hri_gmac_tn_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TN; + tmp &= ~GMAC_TN_TNS_Msk; + tmp |= GMAC_TN_TNS(data); + ((Gmac *)hw)->GMAC_TN = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_TNS_bf(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN &= ~GMAC_TN_TNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_TNS_bf(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN ^= GMAC_TN_TNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_TNS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TN; + tmp = (tmp & GMAC_TN_TNS_Msk) >> GMAC_TN_TNS_Pos; + return tmp; +} + +static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TN; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TN ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TN; +} + +static inline void hri_gmac_set_TI_CNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI |= GMAC_TI_CNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_CNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_CNS(mask)) >> GMAC_TI_CNS_Pos; + return tmp; +} + +static inline void hri_gmac_write_TI_CNS_bf(const void *const hw, hri_gmac_ti_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TI; + tmp &= ~GMAC_TI_CNS_Msk; + tmp |= GMAC_TI_CNS(data); + ((Gmac *)hw)->GMAC_TI = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_CNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI &= ~GMAC_TI_CNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_CNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI ^= GMAC_TI_CNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_CNS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_CNS_Msk) >> GMAC_TI_CNS_Pos; + return tmp; +} + +static inline void hri_gmac_set_TI_ACNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI |= GMAC_TI_ACNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_ACNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_ACNS(mask)) >> GMAC_TI_ACNS_Pos; + return tmp; +} + +static inline void hri_gmac_write_TI_ACNS_bf(const void *const hw, hri_gmac_ti_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TI; + tmp &= ~GMAC_TI_ACNS_Msk; + tmp |= GMAC_TI_ACNS(data); + ((Gmac *)hw)->GMAC_TI = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_ACNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI &= ~GMAC_TI_ACNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_ACNS_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI ^= GMAC_TI_ACNS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_ACNS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_ACNS_Msk) >> GMAC_TI_ACNS_Pos; + return tmp; +} + +static inline void hri_gmac_set_TI_NIT_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI |= GMAC_TI_NIT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_NIT_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_NIT(mask)) >> GMAC_TI_NIT_Pos; + return tmp; +} + +static inline void hri_gmac_write_TI_NIT_bf(const void *const hw, hri_gmac_ti_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TI; + tmp &= ~GMAC_TI_NIT_Msk; + tmp |= GMAC_TI_NIT(data); + ((Gmac *)hw)->GMAC_TI = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_NIT_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI &= ~GMAC_TI_NIT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_NIT_bf(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI ^= GMAC_TI_NIT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_NIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp = (tmp & GMAC_TI_NIT_Msk) >> GMAC_TI_NIT_Pos; + return tmp; +} + +static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TI; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TI ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_TI; +} + +static inline void hri_gmac_set_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] |= GMAC_TBQBAPQ_TXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqbapq_reg_t hri_gmac_get_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index, + hri_gmac_tbqbapq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQBAPQ[index]; + tmp = (tmp & GMAC_TBQBAPQ_TXBQBA(mask)) >> GMAC_TBQBAPQ_TXBQBA_Pos; + return tmp; +} + +static inline void hri_gmac_write_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_TBQBAPQ[index]; + tmp &= ~GMAC_TBQBAPQ_TXBQBA_Msk; + tmp |= GMAC_TBQBAPQ_TXBQBA(data); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] &= ~GMAC_TBQBAPQ_TXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] ^= GMAC_TBQBAPQ_TXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqbapq_reg_t hri_gmac_read_TBQBAPQ_TXBQBA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQBAPQ[index]; + tmp = (tmp & GMAC_TBQBAPQ_TXBQBA_Msk) >> GMAC_TBQBAPQ_TXBQBA_Pos; + return tmp; +} + +static inline void hri_gmac_set_TBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqbapq_reg_t hri_gmac_get_TBQBAPQ_reg(const void *const hw, uint8_t index, + hri_gmac_tbqbapq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_TBQBAPQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_tbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TBQBAPQ[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqbapq_reg_t hri_gmac_read_TBQBAPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_TBQBAPQ[index]; +} + +static inline void hri_gmac_set_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] |= GMAC_RBQBAPQ_RXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqbapq_reg_t hri_gmac_get_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index, + hri_gmac_rbqbapq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQBAPQ[index]; + tmp = (tmp & GMAC_RBQBAPQ_RXBQBA(mask)) >> GMAC_RBQBAPQ_RXBQBA_Pos; + return tmp; +} + +static inline void hri_gmac_write_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RBQBAPQ[index]; + tmp &= ~GMAC_RBQBAPQ_RXBQBA_Msk; + tmp |= GMAC_RBQBAPQ_RXBQBA(data); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] &= ~GMAC_RBQBAPQ_RXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] ^= GMAC_RBQBAPQ_RXBQBA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqbapq_reg_t hri_gmac_read_RBQBAPQ_RXBQBA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQBAPQ[index]; + tmp = (tmp & GMAC_RBQBAPQ_RXBQBA_Msk) >> GMAC_RBQBAPQ_RXBQBA_Pos; + return tmp; +} + +static inline void hri_gmac_set_RBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqbapq_reg_t hri_gmac_get_RBQBAPQ_reg(const void *const hw, uint8_t index, + hri_gmac_rbqbapq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBQBAPQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQBAPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbqbapq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBQBAPQ[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqbapq_reg_t hri_gmac_read_RBQBAPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_RBQBAPQ[index]; +} + +static inline void hri_gmac_set_RBSRPQ_RBS_bf(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] |= GMAC_RBSRPQ_RBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbsrpq_reg_t hri_gmac_get_RBSRPQ_RBS_bf(const void *const hw, uint8_t index, + hri_gmac_rbsrpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBSRPQ[index]; + tmp = (tmp & GMAC_RBSRPQ_RBS(mask)) >> GMAC_RBSRPQ_RBS_Pos; + return tmp; +} + +static inline void hri_gmac_write_RBSRPQ_RBS_bf(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_RBSRPQ[index]; + tmp &= ~GMAC_RBSRPQ_RBS_Msk; + tmp |= GMAC_RBSRPQ_RBS(data); + ((Gmac *)hw)->GMAC_RBSRPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBSRPQ_RBS_bf(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] &= ~GMAC_RBSRPQ_RBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBSRPQ_RBS_bf(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] ^= GMAC_RBSRPQ_RBS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbsrpq_reg_t hri_gmac_read_RBSRPQ_RBS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBSRPQ[index]; + tmp = (tmp & GMAC_RBSRPQ_RBS_Msk) >> GMAC_RBSRPQ_RBS_Pos; + return tmp; +} + +static inline void hri_gmac_set_RBSRPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbsrpq_reg_t hri_gmac_get_RBSRPQ_reg(const void *const hw, uint8_t index, + hri_gmac_rbsrpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_RBSRPQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBSRPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBSRPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBSRPQ_reg(const void *const hw, uint8_t index, hri_gmac_rbsrpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_RBSRPQ[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbsrpq_reg_t hri_gmac_read_RBSRPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_RBSRPQ[index]; +} + +static inline void hri_gmac_set_CBSCR_QBE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR |= GMAC_CBSCR_QBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_CBSCR_QBE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSCR; + tmp = (tmp & GMAC_CBSCR_QBE) >> GMAC_CBSCR_QBE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_CBSCR_QBE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_CBSCR; + tmp &= ~GMAC_CBSCR_QBE; + tmp |= value << GMAC_CBSCR_QBE_Pos; + ((Gmac *)hw)->GMAC_CBSCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSCR_QBE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR &= ~GMAC_CBSCR_QBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSCR_QBE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR ^= GMAC_CBSCR_QBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_CBSCR_QAE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR |= GMAC_CBSCR_QAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_CBSCR_QAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSCR; + tmp = (tmp & GMAC_CBSCR_QAE) >> GMAC_CBSCR_QAE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_CBSCR_QAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_CBSCR; + tmp &= ~GMAC_CBSCR_QAE; + tmp |= value << GMAC_CBSCR_QAE_Pos; + ((Gmac *)hw)->GMAC_CBSCR = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSCR_QAE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR &= ~GMAC_CBSCR_QAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSCR_QAE_bit(const void *const hw) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR ^= GMAC_CBSCR_QAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_CBSCR_reg(const void *const hw, hri_gmac_cbscr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbscr_reg_t hri_gmac_get_CBSCR_reg(const void *const hw, hri_gmac_cbscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSCR; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_CBSCR_reg(const void *const hw, hri_gmac_cbscr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSCR_reg(const void *const hw, hri_gmac_cbscr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSCR_reg(const void *const hw, hri_gmac_cbscr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSCR ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbscr_reg_t hri_gmac_read_CBSCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_CBSCR; +} + +static inline void hri_gmac_set_CBSISQA_IS_bf(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA |= GMAC_CBSISQA_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqa_reg_t hri_gmac_get_CBSISQA_IS_bf(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQA; + tmp = (tmp & GMAC_CBSISQA_IS(mask)) >> GMAC_CBSISQA_IS_Pos; + return tmp; +} + +static inline void hri_gmac_write_CBSISQA_IS_bf(const void *const hw, hri_gmac_cbsisqa_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_CBSISQA; + tmp &= ~GMAC_CBSISQA_IS_Msk; + tmp |= GMAC_CBSISQA_IS(data); + ((Gmac *)hw)->GMAC_CBSISQA = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSISQA_IS_bf(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA &= ~GMAC_CBSISQA_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSISQA_IS_bf(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA ^= GMAC_CBSISQA_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqa_reg_t hri_gmac_read_CBSISQA_IS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQA; + tmp = (tmp & GMAC_CBSISQA_IS_Msk) >> GMAC_CBSISQA_IS_Pos; + return tmp; +} + +static inline void hri_gmac_set_CBSISQA_reg(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqa_reg_t hri_gmac_get_CBSISQA_reg(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQA; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_CBSISQA_reg(const void *const hw, hri_gmac_cbsisqa_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSISQA_reg(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSISQA_reg(const void *const hw, hri_gmac_cbsisqa_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQA ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqa_reg_t hri_gmac_read_CBSISQA_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_CBSISQA; +} + +static inline void hri_gmac_set_CBSISQB_IS_bf(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB |= GMAC_CBSISQB_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqb_reg_t hri_gmac_get_CBSISQB_IS_bf(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQB; + tmp = (tmp & GMAC_CBSISQB_IS(mask)) >> GMAC_CBSISQB_IS_Pos; + return tmp; +} + +static inline void hri_gmac_write_CBSISQB_IS_bf(const void *const hw, hri_gmac_cbsisqb_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_CBSISQB; + tmp &= ~GMAC_CBSISQB_IS_Msk; + tmp |= GMAC_CBSISQB_IS(data); + ((Gmac *)hw)->GMAC_CBSISQB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSISQB_IS_bf(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB &= ~GMAC_CBSISQB_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSISQB_IS_bf(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB ^= GMAC_CBSISQB_IS(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqb_reg_t hri_gmac_read_CBSISQB_IS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQB; + tmp = (tmp & GMAC_CBSISQB_IS_Msk) >> GMAC_CBSISQB_IS_Pos; + return tmp; +} + +static inline void hri_gmac_set_CBSISQB_reg(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqb_reg_t hri_gmac_get_CBSISQB_reg(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_CBSISQB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_CBSISQB_reg(const void *const hw, hri_gmac_cbsisqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_CBSISQB_reg(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_CBSISQB_reg(const void *const hw, hri_gmac_cbsisqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_CBSISQB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_cbsisqb_reg_t hri_gmac_read_CBSISQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->GMAC_CBSISQB; +} + +static inline void hri_gmac_set_ST1RPQ_DSTCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= GMAC_ST1RPQ_DSTCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST1RPQ_DSTCE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_DSTCE) >> GMAC_ST1RPQ_DSTCE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST1RPQ_DSTCE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= ~GMAC_ST1RPQ_DSTCE; + tmp |= value << GMAC_ST1RPQ_DSTCE_Pos; + ((Gmac *)hw)->GMAC_ST1RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_DSTCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~GMAC_ST1RPQ_DSTCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_DSTCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= GMAC_ST1RPQ_DSTCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST1RPQ_UDPE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= GMAC_ST1RPQ_UDPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST1RPQ_UDPE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_UDPE) >> GMAC_ST1RPQ_UDPE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST1RPQ_UDPE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= ~GMAC_ST1RPQ_UDPE; + tmp |= value << GMAC_ST1RPQ_UDPE_Pos; + ((Gmac *)hw)->GMAC_ST1RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_UDPE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~GMAC_ST1RPQ_UDPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_UDPE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= GMAC_ST1RPQ_UDPE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST1RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= GMAC_ST1RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_get_ST1RPQ_QNB_bf(const void *const hw, uint8_t index, + hri_gmac_st1rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_QNB(mask)) >> GMAC_ST1RPQ_QNB_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST1RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= ~GMAC_ST1RPQ_QNB_Msk; + tmp |= GMAC_ST1RPQ_QNB(data); + ((Gmac *)hw)->GMAC_ST1RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~GMAC_ST1RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= GMAC_ST1RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_read_ST1RPQ_QNB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_QNB_Msk) >> GMAC_ST1RPQ_QNB_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= GMAC_ST1RPQ_DSTCM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_get_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index, + hri_gmac_st1rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_DSTCM(mask)) >> GMAC_ST1RPQ_DSTCM_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= ~GMAC_ST1RPQ_DSTCM_Msk; + tmp |= GMAC_ST1RPQ_DSTCM(data); + ((Gmac *)hw)->GMAC_ST1RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~GMAC_ST1RPQ_DSTCM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= GMAC_ST1RPQ_DSTCM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_read_ST1RPQ_DSTCM_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_DSTCM_Msk) >> GMAC_ST1RPQ_DSTCM_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= GMAC_ST1RPQ_UDPM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_get_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index, + hri_gmac_st1rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_UDPM(mask)) >> GMAC_ST1RPQ_UDPM_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= ~GMAC_ST1RPQ_UDPM_Msk; + tmp |= GMAC_ST1RPQ_UDPM(data); + ((Gmac *)hw)->GMAC_ST1RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~GMAC_ST1RPQ_UDPM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= GMAC_ST1RPQ_UDPM(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_read_ST1RPQ_UDPM_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp = (tmp & GMAC_ST1RPQ_UDPM_Msk) >> GMAC_ST1RPQ_UDPM_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST1RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_get_ST1RPQ_reg(const void *const hw, uint8_t index, + hri_gmac_st1rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST1RPQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ST1RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST1RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST1RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st1rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST1RPQ[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st1rpq_reg_t hri_gmac_read_ST1RPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_ST1RPQ[index]; +} + +static inline void hri_gmac_set_ST2RPQ_VLANE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_VLANE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST2RPQ_VLANE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_VLANE) >> GMAC_ST2RPQ_VLANE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST2RPQ_VLANE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_VLANE; + tmp |= value << GMAC_ST2RPQ_VLANE_Pos; + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_VLANE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_VLANE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_VLANE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_VLANE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST2RPQ_ETHE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_ETHE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST2RPQ_ETHE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_ETHE) >> GMAC_ST2RPQ_ETHE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST2RPQ_ETHE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_ETHE; + tmp |= value << GMAC_ST2RPQ_ETHE_Pos; + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_ETHE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_ETHE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_ETHE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_ETHE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST2RPQ_COMPAE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST2RPQ_COMPAE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPAE) >> GMAC_ST2RPQ_COMPAE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPAE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPAE; + tmp |= value << GMAC_ST2RPQ_COMPAE_Pos; + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPAE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPAE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPAE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST2RPQ_COMPBE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST2RPQ_COMPBE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPBE) >> GMAC_ST2RPQ_COMPBE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPBE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPBE; + tmp |= value << GMAC_ST2RPQ_COMPBE_Pos; + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPBE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPBE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPBE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST2RPQ_COMPCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gmac_get_ST2RPQ_COMPCE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPCE) >> GMAC_ST2RPQ_COMPCE_Pos; + return (bool)tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPCE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPCE; + tmp |= value << GMAC_ST2RPQ_COMPCE_Pos; + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPCE_bit(const void *const hw, uint8_t index) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPCE; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_set_ST2RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_QNB_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_QNB(mask)) >> GMAC_ST2RPQ_QNB_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_QNB_Msk; + tmp |= GMAC_ST2RPQ_QNB(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_QNB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_QNB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_QNB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_QNB_Msk) >> GMAC_ST2RPQ_QNB_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_VLANP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_VLANP(mask)) >> GMAC_ST2RPQ_VLANP_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_VLANP_Msk; + tmp |= GMAC_ST2RPQ_VLANP(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_VLANP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_VLANP(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_VLANP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_VLANP_Msk) >> GMAC_ST2RPQ_VLANP_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_I2ETH(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_I2ETH(mask)) >> GMAC_ST2RPQ_I2ETH_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_I2ETH_Msk; + tmp |= GMAC_ST2RPQ_I2ETH(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_I2ETH(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_I2ETH(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_I2ETH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_I2ETH_Msk) >> GMAC_ST2RPQ_I2ETH_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPA(mask)) >> GMAC_ST2RPQ_COMPA_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPA_Msk; + tmp |= GMAC_ST2RPQ_COMPA(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPA(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_COMPA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPA_Msk) >> GMAC_ST2RPQ_COMPA_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPB(mask)) >> GMAC_ST2RPQ_COMPB_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPB_Msk; + tmp |= GMAC_ST2RPQ_COMPB(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPB(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_COMPB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPB_Msk) >> GMAC_ST2RPQ_COMPB_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= GMAC_ST2RPQ_COMPC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPC(mask)) >> GMAC_ST2RPQ_COMPC_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= ~GMAC_ST2RPQ_COMPC_Msk; + tmp |= GMAC_ST2RPQ_COMPC(data); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~GMAC_ST2RPQ_COMPC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= GMAC_ST2RPQ_COMPC(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_COMPC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp = (tmp & GMAC_ST2RPQ_COMPC_Msk) >> GMAC_ST2RPQ_COMPC_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_get_ST2RPQ_reg(const void *const hw, uint8_t index, + hri_gmac_st2rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2RPQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ST2RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2RPQ_reg(const void *const hw, uint8_t index, hri_gmac_st2rpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2RPQ[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2rpq_reg_t hri_gmac_read_ST2RPQ_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_ST2RPQ[index]; +} + +static inline void hri_gmac_set_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] |= GMAC_ST2ER_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2er_reg_t hri_gmac_get_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index, + hri_gmac_st2er_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2ER[index]; + tmp = (tmp & GMAC_ST2ER_COMPVAL(mask)) >> GMAC_ST2ER_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GMAC_ST2ER[index]; + tmp &= ~GMAC_ST2ER_COMPVAL_Msk; + tmp |= GMAC_ST2ER_COMPVAL(data); + ((Gmac *)hw)->GMAC_ST2ER[index] = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] &= ~GMAC_ST2ER_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] ^= GMAC_ST2ER_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2er_reg_t hri_gmac_read_ST2ER_COMPVAL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2ER[index]; + tmp = (tmp & GMAC_ST2ER_COMPVAL_Msk) >> GMAC_ST2ER_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2ER_reg(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2er_reg_t hri_gmac_get_ST2ER_reg(const void *const hw, uint8_t index, + hri_gmac_st2er_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GMAC_ST2ER[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ST2ER_reg(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2ER_reg(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2ER_reg(const void *const hw, uint8_t index, hri_gmac_st2er_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_ST2ER[index] ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2er_reg_t hri_gmac_read_ST2ER_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->GMAC_ST2ER[index]; +} + +static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GMAC_TA = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_set_ST2CW0_MASKVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 |= GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_get_ST2CW0_MASKVAL_bf(const void *const hw, + hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_MASKVAL(mask)) >> GMAC_ST2CW0_MASKVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW0_MASKVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp &= ~GMAC_ST2CW0_MASKVAL_Msk; + tmp |= GMAC_ST2CW0_MASKVAL(data); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW0_MASKVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 &= ~GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW0_MASKVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 ^= GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_read_ST2CW0_MASKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_MASKVAL_Msk) >> GMAC_ST2CW0_MASKVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_set_ST2CW0_COMPVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 |= GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_get_ST2CW0_COMPVAL_bf(const void *const hw, + hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_COMPVAL(mask)) >> GMAC_ST2CW0_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW0_COMPVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp &= ~GMAC_ST2CW0_COMPVAL_Msk; + tmp |= GMAC_ST2CW0_COMPVAL(data); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW0_COMPVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 &= ~GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW0_COMPVAL_bf(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 ^= GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_read_ST2CW0_COMPVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_COMPVAL_Msk) >> GMAC_ST2CW0_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_set_ST2CW0_reg(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_get_ST2CW0_reg(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW0; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW0_reg(const void *const hw, hri_gmac_st2cw0_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW0_reg(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW0_reg(const void *const hw, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW0 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmacst2cw_read_ST2CW0_reg(const void *const hw) +{ + return ((GmacSt2cw *)hw)->GMAC_ST2CW0; +} + +static inline void hri_gmacst2cw_set_ST2CW1_OFFSVAL_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 |= GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_get_ST2CW1_OFFSVAL_bf(const void *const hw, + hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSVAL(mask)) >> GMAC_ST2CW1_OFFSVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW1_OFFSVAL_bf(const void *const hw, hri_gmac_st2cw1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp &= ~GMAC_ST2CW1_OFFSVAL_Msk; + tmp |= GMAC_ST2CW1_OFFSVAL(data); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW1_OFFSVAL_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 &= ~GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW1_OFFSVAL_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 ^= GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_read_ST2CW1_OFFSVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSVAL_Msk) >> GMAC_ST2CW1_OFFSVAL_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_set_ST2CW1_OFFSSTRT_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 |= GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_get_ST2CW1_OFFSSTRT_bf(const void *const hw, + hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSSTRT(mask)) >> GMAC_ST2CW1_OFFSSTRT_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW1_OFFSSTRT_bf(const void *const hw, hri_gmac_st2cw1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp &= ~GMAC_ST2CW1_OFFSSTRT_Msk; + tmp |= GMAC_ST2CW1_OFFSSTRT(data); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW1_OFFSSTRT_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 &= ~GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW1_OFFSSTRT_bf(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 ^= GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_read_ST2CW1_OFFSSTRT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSSTRT_Msk) >> GMAC_ST2CW1_OFFSSTRT_Pos; + return tmp; +} + +static inline void hri_gmacst2cw_set_ST2CW1_reg(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_get_ST2CW1_reg(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSt2cw *)hw)->GMAC_ST2CW1; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacst2cw_write_ST2CW1_reg(const void *const hw, hri_gmac_st2cw1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_clear_ST2CW1_reg(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacst2cw_toggle_ST2CW1_reg(const void *const hw, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSt2cw *)hw)->GMAC_ST2CW1 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmacst2cw_read_ST2CW1_reg(const void *const hw) +{ + return ((GmacSt2cw *)hw)->GMAC_ST2CW1; +} + +static inline void hri_gmac_set_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 |= GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_get_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_MASKVAL(mask)) >> GMAC_ST2CW0_MASKVAL_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp &= ~GMAC_ST2CW0_MASKVAL_Msk; + tmp |= GMAC_ST2CW0_MASKVAL(data); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 &= ~GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 ^= GMAC_ST2CW0_MASKVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_read_ST2CW0_MASKVAL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_MASKVAL_Msk) >> GMAC_ST2CW0_MASKVAL_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 |= GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_get_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_COMPVAL(mask)) >> GMAC_ST2CW0_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp &= ~GMAC_ST2CW0_COMPVAL_Msk; + tmp |= GMAC_ST2CW0_COMPVAL(data); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 &= ~GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 ^= GMAC_ST2CW0_COMPVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_read_ST2CW0_COMPVAL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp = (tmp & GMAC_ST2CW0_COMPVAL_Msk) >> GMAC_ST2CW0_COMPVAL_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2CW0_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_get_ST2CW0_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ST2CW0_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw0_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW0_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW0_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw0_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw0_reg_t hri_gmac_read_ST2CW0_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW0; +} + +static inline void hri_gmac_set_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 |= GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_get_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSVAL(mask)) >> GMAC_ST2CW1_OFFSVAL_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp &= ~GMAC_ST2CW1_OFFSVAL_Msk; + tmp |= GMAC_ST2CW1_OFFSVAL(data); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 &= ~GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 ^= GMAC_ST2CW1_OFFSVAL(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_read_ST2CW1_OFFSVAL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSVAL_Msk) >> GMAC_ST2CW1_OFFSVAL_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 |= GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_get_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSSTRT(mask)) >> GMAC_ST2CW1_OFFSSTRT_Pos; + return tmp; +} + +static inline void hri_gmac_write_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp &= ~GMAC_ST2CW1_OFFSSTRT_Msk; + tmp |= GMAC_ST2CW1_OFFSSTRT(data); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 &= ~GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 ^= GMAC_ST2CW1_OFFSSTRT(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_read_ST2CW1_OFFSSTRT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp = (tmp & GMAC_ST2CW1_OFFSSTRT_Msk) >> GMAC_ST2CW1_OFFSSTRT_Pos; + return tmp; +} + +static inline void hri_gmac_set_ST2CW1_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_get_ST2CW1_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_st2cw1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ST2CW1_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ST2CW1_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ST2CW1_reg(const void *const hw, uint8_t submodule_index, hri_gmac_st2cw1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1 ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_st2cw1_reg_t hri_gmac_read_ST2CW1_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->GmacSt2cw[submodule_index].GMAC_ST2CW1; +} + +static inline void hri_gmacsa_set_SAB_ADDR_bf(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB |= GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_ADDR_bf(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAB; + tmp = (tmp & GMAC_SAB_ADDR(mask)) >> GMAC_SAB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_ADDR_bf(const void *const hw, hri_gmac_sab_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSa *)hw)->GMAC_SAB; + tmp &= ~GMAC_SAB_ADDR_Msk; + tmp |= GMAC_SAB_ADDR(data); + ((GmacSa *)hw)->GMAC_SAB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_ADDR_bf(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB &= ~GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_ADDR_bf(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB ^= GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAB; + tmp = (tmp & GMAC_SAB_ADDR_Msk) >> GMAC_SAB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) +{ + return ((GmacSa *)hw)->GMAC_SAB; +} + +static inline void hri_gmacsa_set_SAT_ADDR_bf(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT |= GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_ADDR_bf(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAT; + tmp = (tmp & GMAC_SAT_ADDR(mask)) >> GMAC_SAT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_ADDR_bf(const void *const hw, hri_gmac_sat_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((GmacSa *)hw)->GMAC_SAT; + tmp &= ~GMAC_SAT_ADDR_Msk; + tmp |= GMAC_SAT_ADDR(data); + ((GmacSa *)hw)->GMAC_SAT = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_ADDR_bf(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT &= ~GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_ADDR_bf(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT ^= GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAT; + tmp = (tmp & GMAC_SAT_ADDR_Msk) >> GMAC_SAT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->GMAC_SAT; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->GMAC_SAT ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) +{ + return ((GmacSa *)hw)->GMAC_SAT; +} + +static inline void hri_gmac_set_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB |= GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB; + tmp = (tmp & GMAC_SAB_ADDR(mask)) >> GMAC_SAB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB; + tmp &= ~GMAC_SAB_ADDR_Msk; + tmp |= GMAC_SAB_ADDR(data); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB &= ~GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB ^= GMAC_SAB_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_ADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB; + tmp = (tmp & GMAC_SAB_ADDR_Msk) >> GMAC_SAB_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAB; +} + +static inline void hri_gmac_set_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT |= GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT; + tmp = (tmp & GMAC_SAT_ADDR(mask)) >> GMAC_SAT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_write_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + uint32_t tmp; + GMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT; + tmp &= ~GMAC_SAT_ADDR_Msk; + tmp |= GMAC_SAT_ADDR(data); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT = tmp; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT &= ~GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT ^= GMAC_SAT_ADDR(mask); + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_ADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT; + tmp = (tmp & GMAC_SAT_ADDR_Msk) >> GMAC_SAT_ADDR_Pos; + return tmp; +} + +static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->GmacSa[submodule_index].GMAC_SAT; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GMAC_E70B_H_INCLUDED */ +#endif /* _SAME70_GMAC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_gpbr_e70b.h b/bsp/microchip/same70/bsp/hri/hri_gpbr_e70b.h new file mode 100644 index 0000000000..4e4c83ae6e --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_gpbr_e70b.h @@ -0,0 +1,154 @@ +/** + * \file + * + * \brief SAM GPBR + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_GPBR_COMPONENT_ +#ifndef _HRI_GPBR_E70B_H_INCLUDED_ +#define _HRI_GPBR_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GPBR_CRITICAL_SECTIONS) +#define GPBR_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GPBR_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GPBR_CRITICAL_SECTION_ENTER() +#define GPBR_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gpbr_sys_gpbr_reg_t; + +static inline void hri_gpbr_set_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] |= GPBR_SYS_GPBR_GPBR_VALUE(mask); + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gpbr_sys_gpbr_reg_t hri_gpbr_get_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gpbr *)hw)->SYS_GPBR[index]; + tmp = (tmp & GPBR_SYS_GPBR_GPBR_VALUE(mask)) >> GPBR_SYS_GPBR_GPBR_VALUE_Pos; + return tmp; +} + +static inline void hri_gpbr_write_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t data) +{ + uint32_t tmp; + GPBR_CRITICAL_SECTION_ENTER(); + tmp = ((Gpbr *)hw)->SYS_GPBR[index]; + tmp &= ~GPBR_SYS_GPBR_GPBR_VALUE_Msk; + tmp |= GPBR_SYS_GPBR_GPBR_VALUE(data); + ((Gpbr *)hw)->SYS_GPBR[index] = tmp; + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gpbr_clear_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] &= ~GPBR_SYS_GPBR_GPBR_VALUE(mask); + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gpbr_toggle_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] ^= GPBR_SYS_GPBR_GPBR_VALUE(mask); + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gpbr_sys_gpbr_reg_t hri_gpbr_read_SYS_GPBR_GPBR_VALUE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gpbr *)hw)->SYS_GPBR[index]; + tmp = (tmp & GPBR_SYS_GPBR_GPBR_VALUE_Msk) >> GPBR_SYS_GPBR_GPBR_VALUE_Pos; + return tmp; +} + +static inline void hri_gpbr_set_SYS_GPBR_reg(const void *const hw, uint8_t index, hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] |= mask; + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gpbr_sys_gpbr_reg_t hri_gpbr_get_SYS_GPBR_reg(const void *const hw, uint8_t index, + hri_gpbr_sys_gpbr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gpbr *)hw)->SYS_GPBR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_gpbr_write_SYS_GPBR_reg(const void *const hw, uint8_t index, hri_gpbr_sys_gpbr_reg_t data) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] = data; + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gpbr_clear_SYS_GPBR_reg(const void *const hw, uint8_t index, hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] &= ~mask; + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gpbr_toggle_SYS_GPBR_reg(const void *const hw, uint8_t index, hri_gpbr_sys_gpbr_reg_t mask) +{ + GPBR_CRITICAL_SECTION_ENTER(); + ((Gpbr *)hw)->SYS_GPBR[index] ^= mask; + GPBR_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gpbr_sys_gpbr_reg_t hri_gpbr_read_SYS_GPBR_reg(const void *const hw, uint8_t index) +{ + return ((Gpbr *)hw)->SYS_GPBR[index]; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GPBR_E70B_H_INCLUDED */ +#endif /* _SAME70_GPBR_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_hsmci_e70b.h b/bsp/microchip/same70/bsp/hri/hri_hsmci_e70b.h new file mode 100644 index 0000000000..ff51c5396c --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_hsmci_e70b.h @@ -0,0 +1,2435 @@ +/** + * \file + * + * \brief SAM HSMCI + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_HSMCI_COMPONENT_ +#ifndef _HRI_HSMCI_E70B_H_INCLUDED_ +#define _HRI_HSMCI_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HSMCI_CRITICAL_SECTIONS) +#define HSMCI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HSMCI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HSMCI_CRITICAL_SECTION_ENTER() +#define HSMCI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hsmci_argr_reg_t; +typedef uint32_t hri_hsmci_blkr_reg_t; +typedef uint32_t hri_hsmci_cfg_reg_t; +typedef uint32_t hri_hsmci_cmdr_reg_t; +typedef uint32_t hri_hsmci_cr_reg_t; +typedef uint32_t hri_hsmci_cstor_reg_t; +typedef uint32_t hri_hsmci_dma_reg_t; +typedef uint32_t hri_hsmci_dtor_reg_t; +typedef uint32_t hri_hsmci_fifo_reg_t; +typedef uint32_t hri_hsmci_imr_reg_t; +typedef uint32_t hri_hsmci_mr_reg_t; +typedef uint32_t hri_hsmci_rdr_reg_t; +typedef uint32_t hri_hsmci_rspr_reg_t; +typedef uint32_t hri_hsmci_sdcr_reg_t; +typedef uint32_t hri_hsmci_sr_reg_t; +typedef uint32_t hri_hsmci_tdr_reg_t; +typedef uint32_t hri_hsmci_wpmr_reg_t; +typedef uint32_t hri_hsmci_wpsr_reg_t; + +static inline void hri_hsmci_set_IMR_CMDRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CMDRDY; +} + +static inline bool hri_hsmci_get_IMR_CMDRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_CMDRDY) >> HSMCI_IMR_CMDRDY_Pos; +} + +static inline void hri_hsmci_write_IMR_CMDRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CMDRDY; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CMDRDY; + } +} + +static inline void hri_hsmci_clear_IMR_CMDRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CMDRDY; +} + +static inline void hri_hsmci_set_IMR_RXRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RXRDY; +} + +static inline bool hri_hsmci_get_IMR_RXRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RXRDY) >> HSMCI_IMR_RXRDY_Pos; +} + +static inline void hri_hsmci_write_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RXRDY; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RXRDY; + } +} + +static inline void hri_hsmci_clear_IMR_RXRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RXRDY; +} + +static inline void hri_hsmci_set_IMR_TXRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_TXRDY; +} + +static inline bool hri_hsmci_get_IMR_TXRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_TXRDY) >> HSMCI_IMR_TXRDY_Pos; +} + +static inline void hri_hsmci_write_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_TXRDY; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_TXRDY; + } +} + +static inline void hri_hsmci_clear_IMR_TXRDY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_TXRDY; +} + +static inline void hri_hsmci_set_IMR_BLKE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_BLKE; +} + +static inline bool hri_hsmci_get_IMR_BLKE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_BLKE) >> HSMCI_IMR_BLKE_Pos; +} + +static inline void hri_hsmci_write_IMR_BLKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_BLKE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_BLKE; + } +} + +static inline void hri_hsmci_clear_IMR_BLKE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_BLKE; +} + +static inline void hri_hsmci_set_IMR_DTIP_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DTIP; +} + +static inline bool hri_hsmci_get_IMR_DTIP_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_DTIP) >> HSMCI_IMR_DTIP_Pos; +} + +static inline void hri_hsmci_write_IMR_DTIP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DTIP; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DTIP; + } +} + +static inline void hri_hsmci_clear_IMR_DTIP_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DTIP; +} + +static inline void hri_hsmci_set_IMR_NOTBUSY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_NOTBUSY; +} + +static inline bool hri_hsmci_get_IMR_NOTBUSY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_NOTBUSY) >> HSMCI_IMR_NOTBUSY_Pos; +} + +static inline void hri_hsmci_write_IMR_NOTBUSY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_NOTBUSY; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_NOTBUSY; + } +} + +static inline void hri_hsmci_clear_IMR_NOTBUSY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_NOTBUSY; +} + +static inline void hri_hsmci_set_IMR_SDIOIRQA_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_SDIOIRQA; +} + +static inline bool hri_hsmci_get_IMR_SDIOIRQA_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_SDIOIRQA) >> HSMCI_IMR_SDIOIRQA_Pos; +} + +static inline void hri_hsmci_write_IMR_SDIOIRQA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_SDIOIRQA; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_SDIOIRQA; + } +} + +static inline void hri_hsmci_clear_IMR_SDIOIRQA_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_SDIOIRQA; +} + +static inline void hri_hsmci_set_IMR_SDIOWAIT_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_SDIOWAIT; +} + +static inline bool hri_hsmci_get_IMR_SDIOWAIT_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_SDIOWAIT) >> HSMCI_IMR_SDIOWAIT_Pos; +} + +static inline void hri_hsmci_write_IMR_SDIOWAIT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_SDIOWAIT; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_SDIOWAIT; + } +} + +static inline void hri_hsmci_clear_IMR_SDIOWAIT_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_SDIOWAIT; +} + +static inline void hri_hsmci_set_IMR_CSRCV_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CSRCV; +} + +static inline bool hri_hsmci_get_IMR_CSRCV_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_CSRCV) >> HSMCI_IMR_CSRCV_Pos; +} + +static inline void hri_hsmci_write_IMR_CSRCV_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CSRCV; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CSRCV; + } +} + +static inline void hri_hsmci_clear_IMR_CSRCV_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CSRCV; +} + +static inline void hri_hsmci_set_IMR_RINDE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RINDE; +} + +static inline bool hri_hsmci_get_IMR_RINDE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RINDE) >> HSMCI_IMR_RINDE_Pos; +} + +static inline void hri_hsmci_write_IMR_RINDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RINDE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RINDE; + } +} + +static inline void hri_hsmci_clear_IMR_RINDE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RINDE; +} + +static inline void hri_hsmci_set_IMR_RDIRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RDIRE; +} + +static inline bool hri_hsmci_get_IMR_RDIRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RDIRE) >> HSMCI_IMR_RDIRE_Pos; +} + +static inline void hri_hsmci_write_IMR_RDIRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RDIRE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RDIRE; + } +} + +static inline void hri_hsmci_clear_IMR_RDIRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RDIRE; +} + +static inline void hri_hsmci_set_IMR_RCRCE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RCRCE; +} + +static inline bool hri_hsmci_get_IMR_RCRCE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RCRCE) >> HSMCI_IMR_RCRCE_Pos; +} + +static inline void hri_hsmci_write_IMR_RCRCE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RCRCE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RCRCE; + } +} + +static inline void hri_hsmci_clear_IMR_RCRCE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RCRCE; +} + +static inline void hri_hsmci_set_IMR_RENDE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RENDE; +} + +static inline bool hri_hsmci_get_IMR_RENDE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RENDE) >> HSMCI_IMR_RENDE_Pos; +} + +static inline void hri_hsmci_write_IMR_RENDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RENDE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RENDE; + } +} + +static inline void hri_hsmci_clear_IMR_RENDE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RENDE; +} + +static inline void hri_hsmci_set_IMR_RTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RTOE; +} + +static inline bool hri_hsmci_get_IMR_RTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_RTOE) >> HSMCI_IMR_RTOE_Pos; +} + +static inline void hri_hsmci_write_IMR_RTOE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RTOE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_RTOE; + } +} + +static inline void hri_hsmci_clear_IMR_RTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_RTOE; +} + +static inline void hri_hsmci_set_IMR_DCRCE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DCRCE; +} + +static inline bool hri_hsmci_get_IMR_DCRCE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_DCRCE) >> HSMCI_IMR_DCRCE_Pos; +} + +static inline void hri_hsmci_write_IMR_DCRCE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DCRCE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DCRCE; + } +} + +static inline void hri_hsmci_clear_IMR_DCRCE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DCRCE; +} + +static inline void hri_hsmci_set_IMR_DTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DTOE; +} + +static inline bool hri_hsmci_get_IMR_DTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_DTOE) >> HSMCI_IMR_DTOE_Pos; +} + +static inline void hri_hsmci_write_IMR_DTOE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DTOE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_DTOE; + } +} + +static inline void hri_hsmci_clear_IMR_DTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_DTOE; +} + +static inline void hri_hsmci_set_IMR_CSTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CSTOE; +} + +static inline bool hri_hsmci_get_IMR_CSTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_CSTOE) >> HSMCI_IMR_CSTOE_Pos; +} + +static inline void hri_hsmci_write_IMR_CSTOE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CSTOE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_CSTOE; + } +} + +static inline void hri_hsmci_clear_IMR_CSTOE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_CSTOE; +} + +static inline void hri_hsmci_set_IMR_BLKOVRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_BLKOVRE; +} + +static inline bool hri_hsmci_get_IMR_BLKOVRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_BLKOVRE) >> HSMCI_IMR_BLKOVRE_Pos; +} + +static inline void hri_hsmci_write_IMR_BLKOVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_BLKOVRE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_BLKOVRE; + } +} + +static inline void hri_hsmci_clear_IMR_BLKOVRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_BLKOVRE; +} + +static inline void hri_hsmci_set_IMR_FIFOEMPTY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_FIFOEMPTY; +} + +static inline bool hri_hsmci_get_IMR_FIFOEMPTY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_FIFOEMPTY) >> HSMCI_IMR_FIFOEMPTY_Pos; +} + +static inline void hri_hsmci_write_IMR_FIFOEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_FIFOEMPTY; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_FIFOEMPTY; + } +} + +static inline void hri_hsmci_clear_IMR_FIFOEMPTY_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_FIFOEMPTY; +} + +static inline void hri_hsmci_set_IMR_XFRDONE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_XFRDONE; +} + +static inline bool hri_hsmci_get_IMR_XFRDONE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_XFRDONE) >> HSMCI_IMR_XFRDONE_Pos; +} + +static inline void hri_hsmci_write_IMR_XFRDONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_XFRDONE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_XFRDONE; + } +} + +static inline void hri_hsmci_clear_IMR_XFRDONE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_XFRDONE; +} + +static inline void hri_hsmci_set_IMR_ACKRCV_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_ACKRCV; +} + +static inline bool hri_hsmci_get_IMR_ACKRCV_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_ACKRCV) >> HSMCI_IMR_ACKRCV_Pos; +} + +static inline void hri_hsmci_write_IMR_ACKRCV_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_ACKRCV; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_ACKRCV; + } +} + +static inline void hri_hsmci_clear_IMR_ACKRCV_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_ACKRCV; +} + +static inline void hri_hsmci_set_IMR_ACKRCVE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_ACKRCVE; +} + +static inline bool hri_hsmci_get_IMR_ACKRCVE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_ACKRCVE) >> HSMCI_IMR_ACKRCVE_Pos; +} + +static inline void hri_hsmci_write_IMR_ACKRCVE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_ACKRCVE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_ACKRCVE; + } +} + +static inline void hri_hsmci_clear_IMR_ACKRCVE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_ACKRCVE; +} + +static inline void hri_hsmci_set_IMR_OVRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_OVRE; +} + +static inline bool hri_hsmci_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_OVRE) >> HSMCI_IMR_OVRE_Pos; +} + +static inline void hri_hsmci_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_OVRE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_OVRE; + } +} + +static inline void hri_hsmci_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_OVRE; +} + +static inline void hri_hsmci_set_IMR_UNRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_UNRE; +} + +static inline bool hri_hsmci_get_IMR_UNRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_IMR & HSMCI_IMR_UNRE) >> HSMCI_IMR_UNRE_Pos; +} + +static inline void hri_hsmci_write_IMR_UNRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_UNRE; + } else { + ((Hsmci *)hw)->HSMCI_IER = HSMCI_IMR_UNRE; + } +} + +static inline void hri_hsmci_clear_IMR_UNRE_bit(const void *const hw) +{ + ((Hsmci *)hw)->HSMCI_IDR = HSMCI_IMR_UNRE; +} + +static inline void hri_hsmci_set_IMR_reg(const void *const hw, hri_hsmci_imr_reg_t mask) +{ + ((Hsmci *)hw)->HSMCI_IER = mask; +} + +static inline hri_hsmci_imr_reg_t hri_hsmci_get_IMR_reg(const void *const hw, hri_hsmci_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_hsmci_imr_reg_t hri_hsmci_read_IMR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_IMR; +} + +static inline void hri_hsmci_write_IMR_reg(const void *const hw, hri_hsmci_imr_reg_t data) +{ + ((Hsmci *)hw)->HSMCI_IER = data; + ((Hsmci *)hw)->HSMCI_IDR = ~data; +} + +static inline void hri_hsmci_clear_IMR_reg(const void *const hw, hri_hsmci_imr_reg_t mask) +{ + ((Hsmci *)hw)->HSMCI_IDR = mask; +} + +static inline hri_hsmci_rspr_reg_t hri_hsmci_get_RSPR_RSP_bf(const void *const hw, uint8_t index, + hri_hsmci_rspr_reg_t mask) +{ + return (((Hsmci *)hw)->HSMCI_RSPR[index] & HSMCI_RSPR_RSP(mask)) >> HSMCI_RSPR_RSP_Pos; +} + +static inline hri_hsmci_rspr_reg_t hri_hsmci_read_RSPR_RSP_bf(const void *const hw, uint8_t index) +{ + return (((Hsmci *)hw)->HSMCI_RSPR[index] & HSMCI_RSPR_RSP_Msk) >> HSMCI_RSPR_RSP_Pos; +} + +static inline hri_hsmci_rspr_reg_t hri_hsmci_get_RSPR_reg(const void *const hw, uint8_t index, + hri_hsmci_rspr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_RSPR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_hsmci_rspr_reg_t hri_hsmci_read_RSPR_reg(const void *const hw, uint8_t index) +{ + return ((Hsmci *)hw)->HSMCI_RSPR[index]; +} + +static inline hri_hsmci_rdr_reg_t hri_hsmci_get_RDR_DATA_bf(const void *const hw, hri_hsmci_rdr_reg_t mask) +{ + return (((Hsmci *)hw)->HSMCI_RDR & HSMCI_RDR_DATA(mask)) >> HSMCI_RDR_DATA_Pos; +} + +static inline hri_hsmci_rdr_reg_t hri_hsmci_read_RDR_DATA_bf(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_RDR & HSMCI_RDR_DATA_Msk) >> HSMCI_RDR_DATA_Pos; +} + +static inline hri_hsmci_rdr_reg_t hri_hsmci_get_RDR_reg(const void *const hw, hri_hsmci_rdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_RDR; + tmp &= mask; + return tmp; +} + +static inline hri_hsmci_rdr_reg_t hri_hsmci_read_RDR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_RDR; +} + +static inline bool hri_hsmci_get_SR_CMDRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_CMDRDY) > 0; +} + +static inline bool hri_hsmci_get_SR_RXRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RXRDY) > 0; +} + +static inline bool hri_hsmci_get_SR_TXRDY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_TXRDY) > 0; +} + +static inline bool hri_hsmci_get_SR_BLKE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_BLKE) > 0; +} + +static inline bool hri_hsmci_get_SR_DTIP_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_DTIP) > 0; +} + +static inline bool hri_hsmci_get_SR_NOTBUSY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_NOTBUSY) > 0; +} + +static inline bool hri_hsmci_get_SR_SDIOIRQA_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_SDIOIRQA) > 0; +} + +static inline bool hri_hsmci_get_SR_SDIOWAIT_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_SDIOWAIT) > 0; +} + +static inline bool hri_hsmci_get_SR_CSRCV_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_CSRCV) > 0; +} + +static inline bool hri_hsmci_get_SR_RINDE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RINDE) > 0; +} + +static inline bool hri_hsmci_get_SR_RDIRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RDIRE) > 0; +} + +static inline bool hri_hsmci_get_SR_RCRCE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RCRCE) > 0; +} + +static inline bool hri_hsmci_get_SR_RENDE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RENDE) > 0; +} + +static inline bool hri_hsmci_get_SR_RTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_RTOE) > 0; +} + +static inline bool hri_hsmci_get_SR_DCRCE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_DCRCE) > 0; +} + +static inline bool hri_hsmci_get_SR_DTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_DTOE) > 0; +} + +static inline bool hri_hsmci_get_SR_CSTOE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_CSTOE) > 0; +} + +static inline bool hri_hsmci_get_SR_BLKOVRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_BLKOVRE) > 0; +} + +static inline bool hri_hsmci_get_SR_FIFOEMPTY_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_FIFOEMPTY) > 0; +} + +static inline bool hri_hsmci_get_SR_XFRDONE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_XFRDONE) > 0; +} + +static inline bool hri_hsmci_get_SR_ACKRCV_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_ACKRCV) > 0; +} + +static inline bool hri_hsmci_get_SR_ACKRCVE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_ACKRCVE) > 0; +} + +static inline bool hri_hsmci_get_SR_OVRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_OVRE) > 0; +} + +static inline bool hri_hsmci_get_SR_UNRE_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_SR & HSMCI_SR_UNRE) > 0; +} + +static inline hri_hsmci_sr_reg_t hri_hsmci_get_SR_reg(const void *const hw, hri_hsmci_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SR; + tmp &= mask; + return tmp; +} + +static inline hri_hsmci_sr_reg_t hri_hsmci_read_SR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_SR; +} + +static inline bool hri_hsmci_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_WPSR & HSMCI_WPSR_WPVS) > 0; +} + +static inline hri_hsmci_wpsr_reg_t hri_hsmci_get_WPSR_WPVSRC_bf(const void *const hw, hri_hsmci_wpsr_reg_t mask) +{ + return (((Hsmci *)hw)->HSMCI_WPSR & HSMCI_WPSR_WPVSRC(mask)) >> HSMCI_WPSR_WPVSRC_Pos; +} + +static inline hri_hsmci_wpsr_reg_t hri_hsmci_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Hsmci *)hw)->HSMCI_WPSR & HSMCI_WPSR_WPVSRC_Msk) >> HSMCI_WPSR_WPVSRC_Pos; +} + +static inline hri_hsmci_wpsr_reg_t hri_hsmci_get_WPSR_reg(const void *const hw, hri_hsmci_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_hsmci_wpsr_reg_t hri_hsmci_read_WPSR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_WPSR; +} + +static inline void hri_hsmci_set_MR_RDPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_RDPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_MR_RDPROOF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_RDPROOF) >> HSMCI_MR_RDPROOF_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_MR_RDPROOF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_RDPROOF; + tmp |= value << HSMCI_MR_RDPROOF_Pos; + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_RDPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_RDPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_RDPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_RDPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_MR_WRPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_WRPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_MR_WRPROOF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_WRPROOF) >> HSMCI_MR_WRPROOF_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_MR_WRPROOF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_WRPROOF; + tmp |= value << HSMCI_MR_WRPROOF_Pos; + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_WRPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_WRPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_WRPROOF_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_WRPROOF; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_MR_FBYTE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_FBYTE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_MR_FBYTE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_FBYTE) >> HSMCI_MR_FBYTE_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_MR_FBYTE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_FBYTE; + tmp |= value << HSMCI_MR_FBYTE_Pos; + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_FBYTE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_FBYTE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_FBYTE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_FBYTE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_MR_PADV_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_PADV; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_MR_PADV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_PADV) >> HSMCI_MR_PADV_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_MR_PADV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_PADV; + tmp |= value << HSMCI_MR_PADV_Pos; + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_PADV_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_PADV; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_PADV_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_PADV; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_MR_CLKODD_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_CLKODD; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_MR_CLKODD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_CLKODD) >> HSMCI_MR_CLKODD_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_MR_CLKODD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_CLKODD; + tmp |= value << HSMCI_MR_CLKODD_Pos; + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_CLKODD_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_CLKODD; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_CLKODD_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_CLKODD; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_MR_CLKDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_CLKDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_get_MR_CLKDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_CLKDIV(mask)) >> HSMCI_MR_CLKDIV_Pos; + return tmp; +} + +static inline void hri_hsmci_write_MR_CLKDIV_bf(const void *const hw, hri_hsmci_mr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_CLKDIV_Msk; + tmp |= HSMCI_MR_CLKDIV(data); + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_CLKDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_CLKDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_CLKDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_CLKDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_read_MR_CLKDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_CLKDIV_Msk) >> HSMCI_MR_CLKDIV_Pos; + return tmp; +} + +static inline void hri_hsmci_set_MR_PWSDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= HSMCI_MR_PWSDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_get_MR_PWSDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_PWSDIV(mask)) >> HSMCI_MR_PWSDIV_Pos; + return tmp; +} + +static inline void hri_hsmci_write_MR_PWSDIV_bf(const void *const hw, hri_hsmci_mr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= ~HSMCI_MR_PWSDIV_Msk; + tmp |= HSMCI_MR_PWSDIV(data); + ((Hsmci *)hw)->HSMCI_MR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_PWSDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~HSMCI_MR_PWSDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_PWSDIV_bf(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= HSMCI_MR_PWSDIV(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_read_MR_PWSDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp = (tmp & HSMCI_MR_PWSDIV_Msk) >> HSMCI_MR_PWSDIV_Pos; + return tmp; +} + +static inline void hri_hsmci_set_MR_reg(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_get_MR_reg(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_MR_reg(const void *const hw, hri_hsmci_mr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_MR_reg(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_MR_reg(const void *const hw, hri_hsmci_mr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_MR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_mr_reg_t hri_hsmci_read_MR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_MR; +} + +static inline void hri_hsmci_set_DTOR_DTOCYC_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR |= HSMCI_DTOR_DTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_get_DTOR_DTOCYC_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp = (tmp & HSMCI_DTOR_DTOCYC(mask)) >> HSMCI_DTOR_DTOCYC_Pos; + return tmp; +} + +static inline void hri_hsmci_write_DTOR_DTOCYC_bf(const void *const hw, hri_hsmci_dtor_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp &= ~HSMCI_DTOR_DTOCYC_Msk; + tmp |= HSMCI_DTOR_DTOCYC(data); + ((Hsmci *)hw)->HSMCI_DTOR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DTOR_DTOCYC_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR &= ~HSMCI_DTOR_DTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DTOR_DTOCYC_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR ^= HSMCI_DTOR_DTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_read_DTOR_DTOCYC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp = (tmp & HSMCI_DTOR_DTOCYC_Msk) >> HSMCI_DTOR_DTOCYC_Pos; + return tmp; +} + +static inline void hri_hsmci_set_DTOR_DTOMUL_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR |= HSMCI_DTOR_DTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_get_DTOR_DTOMUL_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp = (tmp & HSMCI_DTOR_DTOMUL(mask)) >> HSMCI_DTOR_DTOMUL_Pos; + return tmp; +} + +static inline void hri_hsmci_write_DTOR_DTOMUL_bf(const void *const hw, hri_hsmci_dtor_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp &= ~HSMCI_DTOR_DTOMUL_Msk; + tmp |= HSMCI_DTOR_DTOMUL(data); + ((Hsmci *)hw)->HSMCI_DTOR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DTOR_DTOMUL_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR &= ~HSMCI_DTOR_DTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DTOR_DTOMUL_bf(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR ^= HSMCI_DTOR_DTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_read_DTOR_DTOMUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp = (tmp & HSMCI_DTOR_DTOMUL_Msk) >> HSMCI_DTOR_DTOMUL_Pos; + return tmp; +} + +static inline void hri_hsmci_set_DTOR_reg(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_get_DTOR_reg(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DTOR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_DTOR_reg(const void *const hw, hri_hsmci_dtor_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DTOR_reg(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DTOR_reg(const void *const hw, hri_hsmci_dtor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DTOR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dtor_reg_t hri_hsmci_read_DTOR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_DTOR; +} + +static inline void hri_hsmci_set_SDCR_SDCSEL_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR |= HSMCI_SDCR_SDCSEL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_get_SDCR_SDCSEL_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp = (tmp & HSMCI_SDCR_SDCSEL(mask)) >> HSMCI_SDCR_SDCSEL_Pos; + return tmp; +} + +static inline void hri_hsmci_write_SDCR_SDCSEL_bf(const void *const hw, hri_hsmci_sdcr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp &= ~HSMCI_SDCR_SDCSEL_Msk; + tmp |= HSMCI_SDCR_SDCSEL(data); + ((Hsmci *)hw)->HSMCI_SDCR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_SDCR_SDCSEL_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR &= ~HSMCI_SDCR_SDCSEL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_SDCR_SDCSEL_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR ^= HSMCI_SDCR_SDCSEL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_read_SDCR_SDCSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp = (tmp & HSMCI_SDCR_SDCSEL_Msk) >> HSMCI_SDCR_SDCSEL_Pos; + return tmp; +} + +static inline void hri_hsmci_set_SDCR_SDCBUS_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR |= HSMCI_SDCR_SDCBUS(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_get_SDCR_SDCBUS_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp = (tmp & HSMCI_SDCR_SDCBUS(mask)) >> HSMCI_SDCR_SDCBUS_Pos; + return tmp; +} + +static inline void hri_hsmci_write_SDCR_SDCBUS_bf(const void *const hw, hri_hsmci_sdcr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp &= ~HSMCI_SDCR_SDCBUS_Msk; + tmp |= HSMCI_SDCR_SDCBUS(data); + ((Hsmci *)hw)->HSMCI_SDCR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_SDCR_SDCBUS_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR &= ~HSMCI_SDCR_SDCBUS(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_SDCR_SDCBUS_bf(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR ^= HSMCI_SDCR_SDCBUS(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_read_SDCR_SDCBUS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp = (tmp & HSMCI_SDCR_SDCBUS_Msk) >> HSMCI_SDCR_SDCBUS_Pos; + return tmp; +} + +static inline void hri_hsmci_set_SDCR_reg(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_get_SDCR_reg(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_SDCR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_SDCR_reg(const void *const hw, hri_hsmci_sdcr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_SDCR_reg(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_SDCR_reg(const void *const hw, hri_hsmci_sdcr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_SDCR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_sdcr_reg_t hri_hsmci_read_SDCR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_SDCR; +} + +static inline void hri_hsmci_set_ARGR_ARG_bf(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR |= HSMCI_ARGR_ARG(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_argr_reg_t hri_hsmci_get_ARGR_ARG_bf(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_ARGR; + tmp = (tmp & HSMCI_ARGR_ARG(mask)) >> HSMCI_ARGR_ARG_Pos; + return tmp; +} + +static inline void hri_hsmci_write_ARGR_ARG_bf(const void *const hw, hri_hsmci_argr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_ARGR; + tmp &= ~HSMCI_ARGR_ARG_Msk; + tmp |= HSMCI_ARGR_ARG(data); + ((Hsmci *)hw)->HSMCI_ARGR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_ARGR_ARG_bf(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR &= ~HSMCI_ARGR_ARG(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_ARGR_ARG_bf(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR ^= HSMCI_ARGR_ARG(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_argr_reg_t hri_hsmci_read_ARGR_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_ARGR; + tmp = (tmp & HSMCI_ARGR_ARG_Msk) >> HSMCI_ARGR_ARG_Pos; + return tmp; +} + +static inline void hri_hsmci_set_ARGR_reg(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_argr_reg_t hri_hsmci_get_ARGR_reg(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_ARGR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_ARGR_reg(const void *const hw, hri_hsmci_argr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_ARGR_reg(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_ARGR_reg(const void *const hw, hri_hsmci_argr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_ARGR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_argr_reg_t hri_hsmci_read_ARGR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_ARGR; +} + +static inline void hri_hsmci_set_BLKR_BCNT_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR |= HSMCI_BLKR_BCNT(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_get_BLKR_BCNT_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp = (tmp & HSMCI_BLKR_BCNT(mask)) >> HSMCI_BLKR_BCNT_Pos; + return tmp; +} + +static inline void hri_hsmci_write_BLKR_BCNT_bf(const void *const hw, hri_hsmci_blkr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp &= ~HSMCI_BLKR_BCNT_Msk; + tmp |= HSMCI_BLKR_BCNT(data); + ((Hsmci *)hw)->HSMCI_BLKR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_BLKR_BCNT_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR &= ~HSMCI_BLKR_BCNT(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_BLKR_BCNT_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR ^= HSMCI_BLKR_BCNT(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_read_BLKR_BCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp = (tmp & HSMCI_BLKR_BCNT_Msk) >> HSMCI_BLKR_BCNT_Pos; + return tmp; +} + +static inline void hri_hsmci_set_BLKR_BLKLEN_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR |= HSMCI_BLKR_BLKLEN(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_get_BLKR_BLKLEN_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp = (tmp & HSMCI_BLKR_BLKLEN(mask)) >> HSMCI_BLKR_BLKLEN_Pos; + return tmp; +} + +static inline void hri_hsmci_write_BLKR_BLKLEN_bf(const void *const hw, hri_hsmci_blkr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp &= ~HSMCI_BLKR_BLKLEN_Msk; + tmp |= HSMCI_BLKR_BLKLEN(data); + ((Hsmci *)hw)->HSMCI_BLKR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_BLKR_BLKLEN_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR &= ~HSMCI_BLKR_BLKLEN(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_BLKR_BLKLEN_bf(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR ^= HSMCI_BLKR_BLKLEN(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_read_BLKR_BLKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp = (tmp & HSMCI_BLKR_BLKLEN_Msk) >> HSMCI_BLKR_BLKLEN_Pos; + return tmp; +} + +static inline void hri_hsmci_set_BLKR_reg(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_get_BLKR_reg(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_BLKR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_BLKR_reg(const void *const hw, hri_hsmci_blkr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_BLKR_reg(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_BLKR_reg(const void *const hw, hri_hsmci_blkr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_BLKR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_blkr_reg_t hri_hsmci_read_BLKR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_BLKR; +} + +static inline void hri_hsmci_set_CSTOR_CSTOCYC_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR |= HSMCI_CSTOR_CSTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_get_CSTOR_CSTOCYC_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp = (tmp & HSMCI_CSTOR_CSTOCYC(mask)) >> HSMCI_CSTOR_CSTOCYC_Pos; + return tmp; +} + +static inline void hri_hsmci_write_CSTOR_CSTOCYC_bf(const void *const hw, hri_hsmci_cstor_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp &= ~HSMCI_CSTOR_CSTOCYC_Msk; + tmp |= HSMCI_CSTOR_CSTOCYC(data); + ((Hsmci *)hw)->HSMCI_CSTOR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CSTOR_CSTOCYC_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR &= ~HSMCI_CSTOR_CSTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CSTOR_CSTOCYC_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR ^= HSMCI_CSTOR_CSTOCYC(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_read_CSTOR_CSTOCYC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp = (tmp & HSMCI_CSTOR_CSTOCYC_Msk) >> HSMCI_CSTOR_CSTOCYC_Pos; + return tmp; +} + +static inline void hri_hsmci_set_CSTOR_CSTOMUL_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR |= HSMCI_CSTOR_CSTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_get_CSTOR_CSTOMUL_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp = (tmp & HSMCI_CSTOR_CSTOMUL(mask)) >> HSMCI_CSTOR_CSTOMUL_Pos; + return tmp; +} + +static inline void hri_hsmci_write_CSTOR_CSTOMUL_bf(const void *const hw, hri_hsmci_cstor_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp &= ~HSMCI_CSTOR_CSTOMUL_Msk; + tmp |= HSMCI_CSTOR_CSTOMUL(data); + ((Hsmci *)hw)->HSMCI_CSTOR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CSTOR_CSTOMUL_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR &= ~HSMCI_CSTOR_CSTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CSTOR_CSTOMUL_bf(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR ^= HSMCI_CSTOR_CSTOMUL(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_read_CSTOR_CSTOMUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp = (tmp & HSMCI_CSTOR_CSTOMUL_Msk) >> HSMCI_CSTOR_CSTOMUL_Pos; + return tmp; +} + +static inline void hri_hsmci_set_CSTOR_reg(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_get_CSTOR_reg(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CSTOR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_CSTOR_reg(const void *const hw, hri_hsmci_cstor_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CSTOR_reg(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CSTOR_reg(const void *const hw, hri_hsmci_cstor_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CSTOR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cstor_reg_t hri_hsmci_read_CSTOR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_CSTOR; +} + +static inline void hri_hsmci_set_DMA_DMAEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA |= HSMCI_DMA_DMAEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_DMA_DMAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp = (tmp & HSMCI_DMA_DMAEN) >> HSMCI_DMA_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_DMA_DMAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp &= ~HSMCI_DMA_DMAEN; + tmp |= value << HSMCI_DMA_DMAEN_Pos; + ((Hsmci *)hw)->HSMCI_DMA = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DMA_DMAEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA &= ~HSMCI_DMA_DMAEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DMA_DMAEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA ^= HSMCI_DMA_DMAEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_DMA_CHKSIZE_bf(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA |= HSMCI_DMA_CHKSIZE(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dma_reg_t hri_hsmci_get_DMA_CHKSIZE_bf(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp = (tmp & HSMCI_DMA_CHKSIZE(mask)) >> HSMCI_DMA_CHKSIZE_Pos; + return tmp; +} + +static inline void hri_hsmci_write_DMA_CHKSIZE_bf(const void *const hw, hri_hsmci_dma_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp &= ~HSMCI_DMA_CHKSIZE_Msk; + tmp |= HSMCI_DMA_CHKSIZE(data); + ((Hsmci *)hw)->HSMCI_DMA = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DMA_CHKSIZE_bf(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA &= ~HSMCI_DMA_CHKSIZE(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DMA_CHKSIZE_bf(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA ^= HSMCI_DMA_CHKSIZE(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dma_reg_t hri_hsmci_read_DMA_CHKSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp = (tmp & HSMCI_DMA_CHKSIZE_Msk) >> HSMCI_DMA_CHKSIZE_Pos; + return tmp; +} + +static inline void hri_hsmci_set_DMA_reg(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dma_reg_t hri_hsmci_get_DMA_reg(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_DMA; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_DMA_reg(const void *const hw, hri_hsmci_dma_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_DMA_reg(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_DMA_reg(const void *const hw, hri_hsmci_dma_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_DMA ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_dma_reg_t hri_hsmci_read_DMA_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_DMA; +} + +static inline void hri_hsmci_set_CFG_FIFOMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG |= HSMCI_CFG_FIFOMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_CFG_FIFOMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp = (tmp & HSMCI_CFG_FIFOMODE) >> HSMCI_CFG_FIFOMODE_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_CFG_FIFOMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp &= ~HSMCI_CFG_FIFOMODE; + tmp |= value << HSMCI_CFG_FIFOMODE_Pos; + ((Hsmci *)hw)->HSMCI_CFG = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CFG_FIFOMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG &= ~HSMCI_CFG_FIFOMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CFG_FIFOMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG ^= HSMCI_CFG_FIFOMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_CFG_FERRCTRL_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG |= HSMCI_CFG_FERRCTRL; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_CFG_FERRCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp = (tmp & HSMCI_CFG_FERRCTRL) >> HSMCI_CFG_FERRCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_CFG_FERRCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp &= ~HSMCI_CFG_FERRCTRL; + tmp |= value << HSMCI_CFG_FERRCTRL_Pos; + ((Hsmci *)hw)->HSMCI_CFG = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CFG_FERRCTRL_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG &= ~HSMCI_CFG_FERRCTRL; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CFG_FERRCTRL_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG ^= HSMCI_CFG_FERRCTRL; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_CFG_HSMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG |= HSMCI_CFG_HSMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_CFG_HSMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp = (tmp & HSMCI_CFG_HSMODE) >> HSMCI_CFG_HSMODE_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_CFG_HSMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp &= ~HSMCI_CFG_HSMODE; + tmp |= value << HSMCI_CFG_HSMODE_Pos; + ((Hsmci *)hw)->HSMCI_CFG = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CFG_HSMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CFG_HSMODE_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG ^= HSMCI_CFG_HSMODE; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_CFG_LSYNC_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG |= HSMCI_CFG_LSYNC; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_CFG_LSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp = (tmp & HSMCI_CFG_LSYNC) >> HSMCI_CFG_LSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_CFG_LSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp &= ~HSMCI_CFG_LSYNC; + tmp |= value << HSMCI_CFG_LSYNC_Pos; + ((Hsmci *)hw)->HSMCI_CFG = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CFG_LSYNC_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG &= ~HSMCI_CFG_LSYNC; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CFG_LSYNC_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG ^= HSMCI_CFG_LSYNC; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_CFG_reg(const void *const hw, hri_hsmci_cfg_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cfg_reg_t hri_hsmci_get_CFG_reg(const void *const hw, hri_hsmci_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_CFG; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_CFG_reg(const void *const hw, hri_hsmci_cfg_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_CFG_reg(const void *const hw, hri_hsmci_cfg_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_CFG_reg(const void *const hw, hri_hsmci_cfg_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CFG ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_cfg_reg_t hri_hsmci_read_CFG_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_CFG; +} + +static inline void hri_hsmci_set_WPMR_WPEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR |= HSMCI_WPMR_WPEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_hsmci_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp = (tmp & HSMCI_WPMR_WPEN) >> HSMCI_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_hsmci_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp &= ~HSMCI_WPMR_WPEN; + tmp |= value << HSMCI_WPMR_WPEN_Pos; + ((Hsmci *)hw)->HSMCI_WPMR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_WPMR_WPEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR &= ~HSMCI_WPMR_WPEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_WPMR_WPEN_bit(const void *const hw) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR ^= HSMCI_WPMR_WPEN; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_set_WPMR_WPKEY_bf(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR |= HSMCI_WPMR_WPKEY(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_wpmr_reg_t hri_hsmci_get_WPMR_WPKEY_bf(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp = (tmp & HSMCI_WPMR_WPKEY(mask)) >> HSMCI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_hsmci_write_WPMR_WPKEY_bf(const void *const hw, hri_hsmci_wpmr_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp &= ~HSMCI_WPMR_WPKEY_Msk; + tmp |= HSMCI_WPMR_WPKEY(data); + ((Hsmci *)hw)->HSMCI_WPMR = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_WPMR_WPKEY_bf(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR &= ~HSMCI_WPMR_WPKEY(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_WPMR_WPKEY_bf(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR ^= HSMCI_WPMR_WPKEY(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_wpmr_reg_t hri_hsmci_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp = (tmp & HSMCI_WPMR_WPKEY_Msk) >> HSMCI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_hsmci_set_WPMR_reg(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_wpmr_reg_t hri_hsmci_get_WPMR_reg(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_WPMR_reg(const void *const hw, hri_hsmci_wpmr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_WPMR_reg(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_WPMR_reg(const void *const hw, hri_hsmci_wpmr_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_WPMR ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_wpmr_reg_t hri_hsmci_read_WPMR_reg(const void *const hw) +{ + return ((Hsmci *)hw)->HSMCI_WPMR; +} + +static inline void hri_hsmci_set_FIFO_DATA_bf(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] |= HSMCI_FIFO_DATA(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_fifo_reg_t hri_hsmci_get_FIFO_DATA_bf(const void *const hw, uint8_t index, + hri_hsmci_fifo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_FIFO[index]; + tmp = (tmp & HSMCI_FIFO_DATA(mask)) >> HSMCI_FIFO_DATA_Pos; + return tmp; +} + +static inline void hri_hsmci_write_FIFO_DATA_bf(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t data) +{ + uint32_t tmp; + HSMCI_CRITICAL_SECTION_ENTER(); + tmp = ((Hsmci *)hw)->HSMCI_FIFO[index]; + tmp &= ~HSMCI_FIFO_DATA_Msk; + tmp |= HSMCI_FIFO_DATA(data); + ((Hsmci *)hw)->HSMCI_FIFO[index] = tmp; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_FIFO_DATA_bf(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] &= ~HSMCI_FIFO_DATA(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_FIFO_DATA_bf(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] ^= HSMCI_FIFO_DATA(mask); + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_fifo_reg_t hri_hsmci_read_FIFO_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_FIFO[index]; + tmp = (tmp & HSMCI_FIFO_DATA_Msk) >> HSMCI_FIFO_DATA_Pos; + return tmp; +} + +static inline void hri_hsmci_set_FIFO_reg(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] |= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_fifo_reg_t hri_hsmci_get_FIFO_reg(const void *const hw, uint8_t index, + hri_hsmci_fifo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hsmci *)hw)->HSMCI_FIFO[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_hsmci_write_FIFO_reg(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_clear_FIFO_reg(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] &= ~mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_toggle_FIFO_reg(const void *const hw, uint8_t index, hri_hsmci_fifo_reg_t mask) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_FIFO[index] ^= mask; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hsmci_fifo_reg_t hri_hsmci_read_FIFO_reg(const void *const hw, uint8_t index) +{ + return ((Hsmci *)hw)->HSMCI_FIFO[index]; +} + +static inline void hri_hsmci_write_CR_reg(const void *const hw, hri_hsmci_cr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_write_CMDR_reg(const void *const hw, hri_hsmci_cmdr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_CMDR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hsmci_write_TDR_reg(const void *const hw, hri_hsmci_tdr_reg_t data) +{ + HSMCI_CRITICAL_SECTION_ENTER(); + ((Hsmci *)hw)->HSMCI_TDR = data; + HSMCI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HSMCI_E70B_H_INCLUDED */ +#endif /* _SAME70_HSMCI_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_i2sc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_i2sc_e70b.h new file mode 100644 index 0000000000..e7641ccb01 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_i2sc_e70b.h @@ -0,0 +1,851 @@ +/** + * \file + * + * \brief SAM I2SC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_I2SC_COMPONENT_ +#ifndef _HRI_I2SC_E70B_H_INCLUDED_ +#define _HRI_I2SC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2SC_CRITICAL_SECTIONS) +#define I2SC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2SC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2SC_CRITICAL_SECTION_ENTER() +#define I2SC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_i2sc_cr_reg_t; +typedef uint32_t hri_i2sc_imr_reg_t; +typedef uint32_t hri_i2sc_mr_reg_t; +typedef uint32_t hri_i2sc_rhr_reg_t; +typedef uint32_t hri_i2sc_scr_reg_t; +typedef uint32_t hri_i2sc_sr_reg_t; +typedef uint32_t hri_i2sc_ssr_reg_t; +typedef uint32_t hri_i2sc_thr_reg_t; + +static inline void hri_i2sc_set_IMR_RXRDY_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_RXRDY; +} + +static inline bool hri_i2sc_get_IMR_RXRDY_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_IMR & I2SC_IMR_RXRDY) >> I2SC_IMR_RXRDY_Pos; +} + +static inline void hri_i2sc_write_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_RXRDY; + } else { + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_RXRDY; + } +} + +static inline void hri_i2sc_clear_IMR_RXRDY_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_RXRDY; +} + +static inline void hri_i2sc_set_IMR_RXOR_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_RXOR; +} + +static inline bool hri_i2sc_get_IMR_RXOR_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_IMR & I2SC_IMR_RXOR) >> I2SC_IMR_RXOR_Pos; +} + +static inline void hri_i2sc_write_IMR_RXOR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_RXOR; + } else { + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_RXOR; + } +} + +static inline void hri_i2sc_clear_IMR_RXOR_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_RXOR; +} + +static inline void hri_i2sc_set_IMR_TXRDY_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_TXRDY; +} + +static inline bool hri_i2sc_get_IMR_TXRDY_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_IMR & I2SC_IMR_TXRDY) >> I2SC_IMR_TXRDY_Pos; +} + +static inline void hri_i2sc_write_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_TXRDY; + } else { + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_TXRDY; + } +} + +static inline void hri_i2sc_clear_IMR_TXRDY_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_TXRDY; +} + +static inline void hri_i2sc_set_IMR_TXUR_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_TXUR; +} + +static inline bool hri_i2sc_get_IMR_TXUR_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_IMR & I2SC_IMR_TXUR) >> I2SC_IMR_TXUR_Pos; +} + +static inline void hri_i2sc_write_IMR_TXUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_TXUR; + } else { + ((I2sc *)hw)->I2SC_IER = I2SC_IMR_TXUR; + } +} + +static inline void hri_i2sc_clear_IMR_TXUR_bit(const void *const hw) +{ + ((I2sc *)hw)->I2SC_IDR = I2SC_IMR_TXUR; +} + +static inline void hri_i2sc_set_IMR_reg(const void *const hw, hri_i2sc_imr_reg_t mask) +{ + ((I2sc *)hw)->I2SC_IER = mask; +} + +static inline hri_i2sc_imr_reg_t hri_i2sc_get_IMR_reg(const void *const hw, hri_i2sc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_i2sc_imr_reg_t hri_i2sc_read_IMR_reg(const void *const hw) +{ + return ((I2sc *)hw)->I2SC_IMR; +} + +static inline void hri_i2sc_write_IMR_reg(const void *const hw, hri_i2sc_imr_reg_t data) +{ + ((I2sc *)hw)->I2SC_IER = data; + ((I2sc *)hw)->I2SC_IDR = ~data; +} + +static inline void hri_i2sc_clear_IMR_reg(const void *const hw, hri_i2sc_imr_reg_t mask) +{ + ((I2sc *)hw)->I2SC_IDR = mask; +} + +static inline bool hri_i2sc_get_SR_RXEN_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_RXEN) > 0; +} + +static inline bool hri_i2sc_get_SR_RXRDY_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_RXRDY) > 0; +} + +static inline bool hri_i2sc_get_SR_RXOR_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_RXOR) > 0; +} + +static inline bool hri_i2sc_get_SR_TXEN_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_TXEN) > 0; +} + +static inline bool hri_i2sc_get_SR_TXRDY_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_TXRDY) > 0; +} + +static inline bool hri_i2sc_get_SR_TXUR_bit(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_TXUR) > 0; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_get_SR_RXORCH_bf(const void *const hw, hri_i2sc_sr_reg_t mask) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_RXORCH(mask)) >> I2SC_SR_RXORCH_Pos; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_read_SR_RXORCH_bf(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_RXORCH_Msk) >> I2SC_SR_RXORCH_Pos; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_get_SR_TXURCH_bf(const void *const hw, hri_i2sc_sr_reg_t mask) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_TXURCH(mask)) >> I2SC_SR_TXURCH_Pos; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_read_SR_TXURCH_bf(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_SR & I2SC_SR_TXURCH_Msk) >> I2SC_SR_TXURCH_Pos; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_get_SR_reg(const void *const hw, hri_i2sc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_i2sc_sr_reg_t hri_i2sc_read_SR_reg(const void *const hw) +{ + return ((I2sc *)hw)->I2SC_SR; +} + +static inline hri_i2sc_rhr_reg_t hri_i2sc_get_RHR_RHR_bf(const void *const hw, hri_i2sc_rhr_reg_t mask) +{ + return (((I2sc *)hw)->I2SC_RHR & I2SC_RHR_RHR(mask)) >> I2SC_RHR_RHR_Pos; +} + +static inline hri_i2sc_rhr_reg_t hri_i2sc_read_RHR_RHR_bf(const void *const hw) +{ + return (((I2sc *)hw)->I2SC_RHR & I2SC_RHR_RHR_Msk) >> I2SC_RHR_RHR_Pos; +} + +static inline hri_i2sc_rhr_reg_t hri_i2sc_get_RHR_reg(const void *const hw, hri_i2sc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_RHR; + tmp &= mask; + return tmp; +} + +static inline hri_i2sc_rhr_reg_t hri_i2sc_read_RHR_reg(const void *const hw) +{ + return ((I2sc *)hw)->I2SC_RHR; +} + +static inline void hri_i2sc_set_MR_MODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_MODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_MODE) >> I2SC_MR_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_MODE; + tmp |= value << I2SC_MR_MODE_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_MODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_MODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_MODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_MODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_RXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_RXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_RXMONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_RXMONO) >> I2SC_MR_RXMONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_RXMONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_RXMONO; + tmp |= value << I2SC_MR_RXMONO_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_RXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_RXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_RXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_RXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_RXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_RXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_RXDMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_RXDMA) >> I2SC_MR_RXDMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_RXDMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_RXDMA; + tmp |= value << I2SC_MR_RXDMA_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_RXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_RXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_RXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_RXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_RXLOOP_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_RXLOOP; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_RXLOOP) >> I2SC_MR_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_RXLOOP; + tmp |= value << I2SC_MR_RXLOOP_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_RXLOOP_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_RXLOOP; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_RXLOOP_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_RXLOOP; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_TXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_TXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_TXMONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_TXMONO) >> I2SC_MR_TXMONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_TXMONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_TXMONO; + tmp |= value << I2SC_MR_TXMONO_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_TXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_TXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_TXMONO_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_TXMONO; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_TXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_TXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_TXDMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_TXDMA) >> I2SC_MR_TXDMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_TXDMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_TXDMA; + tmp |= value << I2SC_MR_TXDMA_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_TXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_TXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_TXDMA_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_TXDMA; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_TXSAME_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_TXSAME; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_TXSAME) >> I2SC_MR_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_TXSAME; + tmp |= value << I2SC_MR_TXSAME_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_TXSAME_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_TXSAME; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_TXSAME_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_TXSAME; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_IMCKMODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_IMCKMODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_IMCKMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IMCKMODE) >> I2SC_MR_IMCKMODE_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_IMCKMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_IMCKMODE; + tmp |= value << I2SC_MR_IMCKMODE_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_IMCKMODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_IMCKMODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_IMCKMODE_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_IMCKMODE; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_IWS_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_IWS; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2sc_get_MR_IWS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IWS) >> I2SC_MR_IWS_Pos; + return (bool)tmp; +} + +static inline void hri_i2sc_write_MR_IWS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_IWS; + tmp |= value << I2SC_MR_IWS_Pos; + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_IWS_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_IWS; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_IWS_bit(const void *const hw) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_IWS; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_set_MR_DATALENGTH_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_DATALENGTH(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_get_MR_DATALENGTH_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_DATALENGTH(mask)) >> I2SC_MR_DATALENGTH_Pos; + return tmp; +} + +static inline void hri_i2sc_write_MR_DATALENGTH_bf(const void *const hw, hri_i2sc_mr_reg_t data) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_DATALENGTH_Msk; + tmp |= I2SC_MR_DATALENGTH(data); + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_DATALENGTH_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_DATALENGTH(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_DATALENGTH_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_DATALENGTH(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_read_MR_DATALENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_DATALENGTH_Msk) >> I2SC_MR_DATALENGTH_Pos; + return tmp; +} + +static inline void hri_i2sc_set_MR_IMCKDIV_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_IMCKDIV(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_get_MR_IMCKDIV_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IMCKDIV(mask)) >> I2SC_MR_IMCKDIV_Pos; + return tmp; +} + +static inline void hri_i2sc_write_MR_IMCKDIV_bf(const void *const hw, hri_i2sc_mr_reg_t data) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_IMCKDIV_Msk; + tmp |= I2SC_MR_IMCKDIV(data); + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_IMCKDIV_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_IMCKDIV(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_IMCKDIV_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_IMCKDIV(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_read_MR_IMCKDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IMCKDIV_Msk) >> I2SC_MR_IMCKDIV_Pos; + return tmp; +} + +static inline void hri_i2sc_set_MR_IMCKFS_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= I2SC_MR_IMCKFS(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_get_MR_IMCKFS_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IMCKFS(mask)) >> I2SC_MR_IMCKFS_Pos; + return tmp; +} + +static inline void hri_i2sc_write_MR_IMCKFS_bf(const void *const hw, hri_i2sc_mr_reg_t data) +{ + uint32_t tmp; + I2SC_CRITICAL_SECTION_ENTER(); + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= ~I2SC_MR_IMCKFS_Msk; + tmp |= I2SC_MR_IMCKFS(data); + ((I2sc *)hw)->I2SC_MR = tmp; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_IMCKFS_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~I2SC_MR_IMCKFS(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_IMCKFS_bf(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= I2SC_MR_IMCKFS(mask); + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_read_MR_IMCKFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp = (tmp & I2SC_MR_IMCKFS_Msk) >> I2SC_MR_IMCKFS_Pos; + return tmp; +} + +static inline void hri_i2sc_set_MR_reg(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR |= mask; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_get_MR_reg(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2sc *)hw)->I2SC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_i2sc_write_MR_reg(const void *const hw, hri_i2sc_mr_reg_t data) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR = data; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_clear_MR_reg(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR &= ~mask; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_toggle_MR_reg(const void *const hw, hri_i2sc_mr_reg_t mask) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_MR ^= mask; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2sc_mr_reg_t hri_i2sc_read_MR_reg(const void *const hw) +{ + return ((I2sc *)hw)->I2SC_MR; +} + +static inline void hri_i2sc_write_CR_reg(const void *const hw, hri_i2sc_cr_reg_t data) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_CR = data; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_write_SCR_reg(const void *const hw, hri_i2sc_scr_reg_t data) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_SCR = data; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_write_SSR_reg(const void *const hw, hri_i2sc_ssr_reg_t data) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_SSR = data; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2sc_write_THR_reg(const void *const hw, hri_i2sc_thr_reg_t data) +{ + I2SC_CRITICAL_SECTION_ENTER(); + ((I2sc *)hw)->I2SC_THR = data; + I2SC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2SC_E70B_H_INCLUDED */ +#endif /* _SAME70_I2SC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_icm_e70b.h b/bsp/microchip/same70/bsp/hri/hri_icm_e70b.h new file mode 100644 index 0000000000..1c08f2e35c --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_icm_e70b.h @@ -0,0 +1,960 @@ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_ICM_COMPONENT_ +#ifndef _HRI_ICM_E70B_H_INCLUDED_ +#define _HRI_ICM_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ICM_ISR & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_ISR; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ICM_IMR & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->ICM_IDR = ICM_IMR_URAD; + } else { + ((Icm *)hw)->ICM_IER = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RHC(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RDM(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RBE(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RWC(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_REC(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = ICM_IMR_RSU(data); + ((Icm *)hw)->ICM_IDR = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IER = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_IMR; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->ICM_IER = data; + ((Icm *)hw)->ICM_IDR = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->ICM_IDR = mask; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->ICM_SR & ICM_SR_ENABLE) > 0; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->ICM_SR & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->ICM_SR & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->ICM_SR & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->ICM_SR & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_SR; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_SR; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->ICM_UASR & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->ICM_UASR & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_UASR; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_UASR; +} + +static inline void hri_icm_set_CFG_WBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_WBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_WBDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_WBDIS) >> ICM_CFG_WBDIS_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_WBDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_WBDIS; + tmp |= value << ICM_CFG_WBDIS_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_WBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_WBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_WBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_WBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_EOMDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_EOMDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_EOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_EOMDIS) >> ICM_CFG_EOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_EOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_EOMDIS; + tmp |= value << ICM_CFG_EOMDIS_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_EOMDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_EOMDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_EOMDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_EOMDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_SLBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_SLBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_SLBDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_SLBDIS) >> ICM_CFG_SLBDIS_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_SLBDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_SLBDIS; + tmp |= value << ICM_CFG_SLBDIS_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_SLBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_SLBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_SLBDIS_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_SLBDIS; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_ASCD_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_ASCD; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_ASCD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_ASCD) >> ICM_CFG_ASCD_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_ASCD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_ASCD; + tmp |= value << ICM_CFG_ASCD_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_ASCD_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_ASCD; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_ASCD_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_ASCD; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_DUALBUFF_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_DUALBUFF; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_DUALBUFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_DUALBUFF) >> ICM_CFG_DUALBUFF_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_DUALBUFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_DUALBUFF; + tmp |= value << ICM_CFG_DUALBUFF_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_DUALBUFF_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_DUALBUFF; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_DUALBUFF_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_DUALBUFF; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_UIHASH_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_UIHASH; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_icm_get_CFG_UIHASH_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_UIHASH) >> ICM_CFG_UIHASH_Pos; + return (bool)tmp; +} + +static inline void hri_icm_write_CFG_UIHASH_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_UIHASH; + tmp |= value << ICM_CFG_UIHASH_Pos; + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_UIHASH_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_UIHASH; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_UIHASH_bit(const void *const hw) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_UIHASH; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_BBC_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_BBC(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_BBC_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_BBC(mask)) >> ICM_CFG_BBC_Pos; + return tmp; +} + +static inline void hri_icm_write_CFG_BBC_bf(const void *const hw, hri_icm_cfg_reg_t data) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_BBC_Msk; + tmp |= ICM_CFG_BBC(data); + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_BBC_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_BBC(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_BBC_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_BBC(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_BBC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_BBC_Msk) >> ICM_CFG_BBC_Pos; + return tmp; +} + +static inline void hri_icm_set_CFG_UALGO_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= ICM_CFG_UALGO(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_UALGO_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_UALGO(mask)) >> ICM_CFG_UALGO_Pos; + return tmp; +} + +static inline void hri_icm_write_CFG_UALGO_bf(const void *const hw, hri_icm_cfg_reg_t data) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= ~ICM_CFG_UALGO_Msk; + tmp |= ICM_CFG_UALGO(data); + ((Icm *)hw)->ICM_CFG = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_UALGO_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~ICM_CFG_UALGO(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_UALGO_bf(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= ICM_CFG_UALGO(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_UALGO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp = (tmp & ICM_CFG_UALGO_Msk) >> ICM_CFG_UALGO_Pos; + return tmp; +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_CFG; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CFG ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_CFG; +} + +static inline void hri_icm_set_DSCR_DASA_bf(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR |= ICM_DSCR_DASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_DASA_bf(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_DSCR; + tmp = (tmp & ICM_DSCR_DASA(mask)) >> ICM_DSCR_DASA_Pos; + return tmp; +} + +static inline void hri_icm_write_DSCR_DASA_bf(const void *const hw, hri_icm_dscr_reg_t data) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_DSCR; + tmp &= ~ICM_DSCR_DASA_Msk; + tmp |= ICM_DSCR_DASA(data); + ((Icm *)hw)->ICM_DSCR = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_DASA_bf(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR &= ~ICM_DSCR_DASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_DASA_bf(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR ^= ICM_DSCR_DASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_DASA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_DSCR; + tmp = (tmp & ICM_DSCR_DASA_Msk) >> ICM_DSCR_DASA_Pos; + return tmp; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_DSCR; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_DSCR ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_DSCR; +} + +static inline void hri_icm_set_HASH_HASA_bf(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH |= ICM_HASH_HASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_HASA_bf(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_HASH; + tmp = (tmp & ICM_HASH_HASA(mask)) >> ICM_HASH_HASA_Pos; + return tmp; +} + +static inline void hri_icm_write_HASH_HASA_bf(const void *const hw, hri_icm_hash_reg_t data) +{ + uint32_t tmp; + ICM_CRITICAL_SECTION_ENTER(); + tmp = ((Icm *)hw)->ICM_HASH; + tmp &= ~ICM_HASH_HASA_Msk; + tmp |= ICM_HASH_HASA(data); + ((Icm *)hw)->ICM_HASH = tmp; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_HASA_bf(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH &= ~ICM_HASH_HASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_HASA_bf(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH ^= ICM_HASH_HASA(mask); + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_HASA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_HASH; + tmp = (tmp & ICM_HASH_HASA_Msk) >> ICM_HASH_HASA_Pos; + return tmp; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ICM_HASH; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_HASH ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->ICM_HASH; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_CTRL = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->ICM_UIHVAL[index] = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_E70B_H_INCLUDED */ +#endif /* _SAME70_ICM_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_isi_e70b.h b/bsp/microchip/same70/bsp/hri/hri_isi_e70b.h new file mode 100644 index 0000000000..e9bc03f572 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_isi_e70b.h @@ -0,0 +1,3729 @@ +/** + * \file + * + * \brief SAM ISI + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_ISI_COMPONENT_ +#ifndef _HRI_ISI_E70B_H_INCLUDED_ +#define _HRI_ISI_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ISI_CRITICAL_SECTIONS) +#define ISI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ISI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ISI_CRITICAL_SECTION_ENTER() +#define ISI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_isi_cfg1_reg_t; +typedef uint32_t hri_isi_cfg2_reg_t; +typedef uint32_t hri_isi_cr_reg_t; +typedef uint32_t hri_isi_dma_c_addr_reg_t; +typedef uint32_t hri_isi_dma_c_ctrl_reg_t; +typedef uint32_t hri_isi_dma_c_dscr_reg_t; +typedef uint32_t hri_isi_dma_chsr_reg_t; +typedef uint32_t hri_isi_dma_p_addr_reg_t; +typedef uint32_t hri_isi_dma_p_ctrl_reg_t; +typedef uint32_t hri_isi_dma_p_dscr_reg_t; +typedef uint32_t hri_isi_imr_reg_t; +typedef uint32_t hri_isi_pdecf_reg_t; +typedef uint32_t hri_isi_psize_reg_t; +typedef uint32_t hri_isi_r2y_set0_reg_t; +typedef uint32_t hri_isi_r2y_set1_reg_t; +typedef uint32_t hri_isi_r2y_set2_reg_t; +typedef uint32_t hri_isi_sr_reg_t; +typedef uint32_t hri_isi_wpmr_reg_t; +typedef uint32_t hri_isi_wpsr_reg_t; +typedef uint32_t hri_isi_y2r_set0_reg_t; +typedef uint32_t hri_isi_y2r_set1_reg_t; + +static inline void hri_isi_set_IMR_DIS_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_DIS_DONE; +} + +static inline bool hri_isi_get_IMR_DIS_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_DIS_DONE) >> ISI_IMR_DIS_DONE_Pos; +} + +static inline void hri_isi_write_IMR_DIS_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_DIS_DONE; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_DIS_DONE; + } +} + +static inline void hri_isi_clear_IMR_DIS_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_DIS_DONE; +} + +static inline void hri_isi_set_IMR_SRST_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_SRST; +} + +static inline bool hri_isi_get_IMR_SRST_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_SRST) >> ISI_IMR_SRST_Pos; +} + +static inline void hri_isi_write_IMR_SRST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_SRST; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_SRST; + } +} + +static inline void hri_isi_clear_IMR_SRST_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_SRST; +} + +static inline void hri_isi_set_IMR_VSYNC_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_VSYNC; +} + +static inline bool hri_isi_get_IMR_VSYNC_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_VSYNC) >> ISI_IMR_VSYNC_Pos; +} + +static inline void hri_isi_write_IMR_VSYNC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_VSYNC; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_VSYNC; + } +} + +static inline void hri_isi_clear_IMR_VSYNC_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_VSYNC; +} + +static inline void hri_isi_set_IMR_PXFR_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_PXFR_DONE; +} + +static inline bool hri_isi_get_IMR_PXFR_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_PXFR_DONE) >> ISI_IMR_PXFR_DONE_Pos; +} + +static inline void hri_isi_write_IMR_PXFR_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_PXFR_DONE; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_PXFR_DONE; + } +} + +static inline void hri_isi_clear_IMR_PXFR_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_PXFR_DONE; +} + +static inline void hri_isi_set_IMR_CXFR_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_CXFR_DONE; +} + +static inline bool hri_isi_get_IMR_CXFR_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_CXFR_DONE) >> ISI_IMR_CXFR_DONE_Pos; +} + +static inline void hri_isi_write_IMR_CXFR_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_CXFR_DONE; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_CXFR_DONE; + } +} + +static inline void hri_isi_clear_IMR_CXFR_DONE_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_CXFR_DONE; +} + +static inline void hri_isi_set_IMR_P_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_P_OVR; +} + +static inline bool hri_isi_get_IMR_P_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_P_OVR) >> ISI_IMR_P_OVR_Pos; +} + +static inline void hri_isi_write_IMR_P_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_P_OVR; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_P_OVR; + } +} + +static inline void hri_isi_clear_IMR_P_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_P_OVR; +} + +static inline void hri_isi_set_IMR_C_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_C_OVR; +} + +static inline bool hri_isi_get_IMR_C_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_C_OVR) >> ISI_IMR_C_OVR_Pos; +} + +static inline void hri_isi_write_IMR_C_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_C_OVR; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_C_OVR; + } +} + +static inline void hri_isi_clear_IMR_C_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_C_OVR; +} + +static inline void hri_isi_set_IMR_CRC_ERR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_CRC_ERR; +} + +static inline bool hri_isi_get_IMR_CRC_ERR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_CRC_ERR) >> ISI_IMR_CRC_ERR_Pos; +} + +static inline void hri_isi_write_IMR_CRC_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_CRC_ERR; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_CRC_ERR; + } +} + +static inline void hri_isi_clear_IMR_CRC_ERR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_CRC_ERR; +} + +static inline void hri_isi_set_IMR_FR_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IER = ISI_IMR_FR_OVR; +} + +static inline bool hri_isi_get_IMR_FR_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_IMR & ISI_IMR_FR_OVR) >> ISI_IMR_FR_OVR_Pos; +} + +static inline void hri_isi_write_IMR_FR_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_IDR = ISI_IMR_FR_OVR; + } else { + ((Isi *)hw)->ISI_IER = ISI_IMR_FR_OVR; + } +} + +static inline void hri_isi_clear_IMR_FR_OVR_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_IDR = ISI_IMR_FR_OVR; +} + +static inline void hri_isi_set_IMR_reg(const void *const hw, hri_isi_imr_reg_t mask) +{ + ((Isi *)hw)->ISI_IER = mask; +} + +static inline hri_isi_imr_reg_t hri_isi_get_IMR_reg(const void *const hw, hri_isi_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_isi_imr_reg_t hri_isi_read_IMR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_IMR; +} + +static inline void hri_isi_write_IMR_reg(const void *const hw, hri_isi_imr_reg_t data) +{ + ((Isi *)hw)->ISI_IER = data; + ((Isi *)hw)->ISI_IDR = ~data; +} + +static inline void hri_isi_clear_IMR_reg(const void *const hw, hri_isi_imr_reg_t mask) +{ + ((Isi *)hw)->ISI_IDR = mask; +} + +static inline void hri_isi_set_DMA_CHSR_P_CH_S_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_DMA_CHER = ISI_DMA_CHSR_P_CH_S; +} + +static inline bool hri_isi_get_DMA_CHSR_P_CH_S_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_DMA_CHSR & ISI_DMA_CHSR_P_CH_S) >> ISI_DMA_CHSR_P_CH_S_Pos; +} + +static inline void hri_isi_write_DMA_CHSR_P_CH_S_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_DMA_CHDR = ISI_DMA_CHSR_P_CH_S; + } else { + ((Isi *)hw)->ISI_DMA_CHER = ISI_DMA_CHSR_P_CH_S; + } +} + +static inline void hri_isi_clear_DMA_CHSR_P_CH_S_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_DMA_CHDR = ISI_DMA_CHSR_P_CH_S; +} + +static inline void hri_isi_set_DMA_CHSR_C_CH_S_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_DMA_CHER = ISI_DMA_CHSR_C_CH_S; +} + +static inline bool hri_isi_get_DMA_CHSR_C_CH_S_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_DMA_CHSR & ISI_DMA_CHSR_C_CH_S) >> ISI_DMA_CHSR_C_CH_S_Pos; +} + +static inline void hri_isi_write_DMA_CHSR_C_CH_S_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Isi *)hw)->ISI_DMA_CHDR = ISI_DMA_CHSR_C_CH_S; + } else { + ((Isi *)hw)->ISI_DMA_CHER = ISI_DMA_CHSR_C_CH_S; + } +} + +static inline void hri_isi_clear_DMA_CHSR_C_CH_S_bit(const void *const hw) +{ + ((Isi *)hw)->ISI_DMA_CHDR = ISI_DMA_CHSR_C_CH_S; +} + +static inline void hri_isi_set_DMA_CHSR_reg(const void *const hw, hri_isi_dma_chsr_reg_t mask) +{ + ((Isi *)hw)->ISI_DMA_CHER = mask; +} + +static inline hri_isi_dma_chsr_reg_t hri_isi_get_DMA_CHSR_reg(const void *const hw, hri_isi_dma_chsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_CHSR; + tmp &= mask; + return tmp; +} + +static inline hri_isi_dma_chsr_reg_t hri_isi_read_DMA_CHSR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_CHSR; +} + +static inline void hri_isi_write_DMA_CHSR_reg(const void *const hw, hri_isi_dma_chsr_reg_t data) +{ + ((Isi *)hw)->ISI_DMA_CHER = data; + ((Isi *)hw)->ISI_DMA_CHDR = ~data; +} + +static inline void hri_isi_clear_DMA_CHSR_reg(const void *const hw, hri_isi_dma_chsr_reg_t mask) +{ + ((Isi *)hw)->ISI_DMA_CHDR = mask; +} + +static inline bool hri_isi_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_ENABLE) > 0; +} + +static inline bool hri_isi_get_SR_DIS_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_DIS_DONE) > 0; +} + +static inline bool hri_isi_get_SR_SRST_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_SRST) > 0; +} + +static inline bool hri_isi_get_SR_CDC_PND_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_CDC_PND) > 0; +} + +static inline bool hri_isi_get_SR_VSYNC_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_VSYNC) > 0; +} + +static inline bool hri_isi_get_SR_PXFR_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_PXFR_DONE) > 0; +} + +static inline bool hri_isi_get_SR_CXFR_DONE_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_CXFR_DONE) > 0; +} + +static inline bool hri_isi_get_SR_SIP_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_SIP) > 0; +} + +static inline bool hri_isi_get_SR_P_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_P_OVR) > 0; +} + +static inline bool hri_isi_get_SR_C_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_C_OVR) > 0; +} + +static inline bool hri_isi_get_SR_CRC_ERR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_CRC_ERR) > 0; +} + +static inline bool hri_isi_get_SR_FR_OVR_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_SR & ISI_SR_FR_OVR) > 0; +} + +static inline hri_isi_sr_reg_t hri_isi_get_SR_reg(const void *const hw, hri_isi_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_SR; + tmp &= mask; + return tmp; +} + +static inline hri_isi_sr_reg_t hri_isi_read_SR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_SR; +} + +static inline bool hri_isi_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Isi *)hw)->ISI_WPSR & ISI_WPSR_WPVS) > 0; +} + +static inline hri_isi_wpsr_reg_t hri_isi_get_WPSR_WPVSRC_bf(const void *const hw, hri_isi_wpsr_reg_t mask) +{ + return (((Isi *)hw)->ISI_WPSR & ISI_WPSR_WPVSRC(mask)) >> ISI_WPSR_WPVSRC_Pos; +} + +static inline hri_isi_wpsr_reg_t hri_isi_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Isi *)hw)->ISI_WPSR & ISI_WPSR_WPVSRC_Msk) >> ISI_WPSR_WPVSRC_Pos; +} + +static inline hri_isi_wpsr_reg_t hri_isi_get_WPSR_reg(const void *const hw, hri_isi_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_isi_wpsr_reg_t hri_isi_read_WPSR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_WPSR; +} + +static inline void hri_isi_set_CFG1_HSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_HSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_HSYNC_POL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_HSYNC_POL) >> ISI_CFG1_HSYNC_POL_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_HSYNC_POL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_HSYNC_POL; + tmp |= value << ISI_CFG1_HSYNC_POL_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_HSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_HSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_HSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_HSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_VSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_VSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_VSYNC_POL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_VSYNC_POL) >> ISI_CFG1_VSYNC_POL_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_VSYNC_POL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_VSYNC_POL; + tmp |= value << ISI_CFG1_VSYNC_POL_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_VSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_VSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_VSYNC_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_VSYNC_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_PIXCLK_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_PIXCLK_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_PIXCLK_POL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_PIXCLK_POL) >> ISI_CFG1_PIXCLK_POL_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_PIXCLK_POL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_PIXCLK_POL; + tmp |= value << ISI_CFG1_PIXCLK_POL_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_PIXCLK_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_PIXCLK_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_PIXCLK_POL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_PIXCLK_POL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_GRAYLE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_GRAYLE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_GRAYLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_GRAYLE) >> ISI_CFG1_GRAYLE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_GRAYLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_GRAYLE; + tmp |= value << ISI_CFG1_GRAYLE_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_GRAYLE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_GRAYLE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_GRAYLE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_GRAYLE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_EMB_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_EMB_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_EMB_SYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_EMB_SYNC) >> ISI_CFG1_EMB_SYNC_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_EMB_SYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_EMB_SYNC; + tmp |= value << ISI_CFG1_EMB_SYNC_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_EMB_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_EMB_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_EMB_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_EMB_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_CRC_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_CRC_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_CRC_SYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_CRC_SYNC) >> ISI_CFG1_CRC_SYNC_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_CRC_SYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_CRC_SYNC; + tmp |= value << ISI_CFG1_CRC_SYNC_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_CRC_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_CRC_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_CRC_SYNC_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_CRC_SYNC; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_DISCR_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_DISCR; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_DISCR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_DISCR) >> ISI_CFG1_DISCR_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_DISCR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_DISCR; + tmp |= value << ISI_CFG1_DISCR_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_DISCR_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_DISCR; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_DISCR_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_DISCR; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_FULL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_FULL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG1_FULL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_FULL) >> ISI_CFG1_FULL_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG1_FULL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_FULL; + tmp |= value << ISI_CFG1_FULL_Pos; + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_FULL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_FULL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_FULL_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_FULL; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG1_FRATE_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_FRATE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_get_CFG1_FRATE_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_FRATE(mask)) >> ISI_CFG1_FRATE_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG1_FRATE_bf(const void *const hw, hri_isi_cfg1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_FRATE_Msk; + tmp |= ISI_CFG1_FRATE(data); + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_FRATE_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_FRATE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_FRATE_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_FRATE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_read_CFG1_FRATE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_FRATE_Msk) >> ISI_CFG1_FRATE_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG1_THMASK_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_THMASK(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_get_CFG1_THMASK_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_THMASK(mask)) >> ISI_CFG1_THMASK_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG1_THMASK_bf(const void *const hw, hri_isi_cfg1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_THMASK_Msk; + tmp |= ISI_CFG1_THMASK(data); + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_THMASK_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_THMASK(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_THMASK_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_THMASK(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_read_CFG1_THMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_THMASK_Msk) >> ISI_CFG1_THMASK_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG1_SLD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_SLD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_get_CFG1_SLD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_SLD(mask)) >> ISI_CFG1_SLD_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG1_SLD_bf(const void *const hw, hri_isi_cfg1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_SLD_Msk; + tmp |= ISI_CFG1_SLD(data); + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_SLD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_SLD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_SLD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_SLD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_read_CFG1_SLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_SLD_Msk) >> ISI_CFG1_SLD_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG1_SFD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= ISI_CFG1_SFD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_get_CFG1_SFD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_SFD(mask)) >> ISI_CFG1_SFD_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG1_SFD_bf(const void *const hw, hri_isi_cfg1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= ~ISI_CFG1_SFD_Msk; + tmp |= ISI_CFG1_SFD(data); + ((Isi *)hw)->ISI_CFG1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_SFD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~ISI_CFG1_SFD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_SFD_bf(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= ISI_CFG1_SFD(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_read_CFG1_SFD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp = (tmp & ISI_CFG1_SFD_Msk) >> ISI_CFG1_SFD_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG1_reg(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_get_CFG1_reg(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG1; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_CFG1_reg(const void *const hw, hri_isi_cfg1_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG1_reg(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG1_reg(const void *const hw, hri_isi_cfg1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG1 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg1_reg_t hri_isi_read_CFG1_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_CFG1; +} + +static inline void hri_isi_set_CFG2_GS_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_GS_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG2_GS_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_GS_MODE) >> ISI_CFG2_GS_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG2_GS_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_GS_MODE; + tmp |= value << ISI_CFG2_GS_MODE_Pos; + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_GS_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_GS_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_GS_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_GS_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG2_RGB_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_RGB_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG2_RGB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_RGB_MODE) >> ISI_CFG2_RGB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG2_RGB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_RGB_MODE; + tmp |= value << ISI_CFG2_RGB_MODE_Pos; + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_RGB_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_RGB_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_RGB_MODE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_RGB_MODE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG2_GRAYSCALE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_GRAYSCALE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG2_GRAYSCALE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_GRAYSCALE) >> ISI_CFG2_GRAYSCALE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG2_GRAYSCALE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_GRAYSCALE; + tmp |= value << ISI_CFG2_GRAYSCALE_Pos; + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_GRAYSCALE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_GRAYSCALE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_GRAYSCALE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_GRAYSCALE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG2_RGB_SWAP_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_RGB_SWAP; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG2_RGB_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_RGB_SWAP) >> ISI_CFG2_RGB_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG2_RGB_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_RGB_SWAP; + tmp |= value << ISI_CFG2_RGB_SWAP_Pos; + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_RGB_SWAP_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_RGB_SWAP; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_RGB_SWAP_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_RGB_SWAP; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG2_COL_SPACE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_COL_SPACE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_CFG2_COL_SPACE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_COL_SPACE) >> ISI_CFG2_COL_SPACE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_CFG2_COL_SPACE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_COL_SPACE; + tmp |= value << ISI_CFG2_COL_SPACE_Pos; + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_COL_SPACE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_COL_SPACE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_COL_SPACE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_COL_SPACE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_CFG2_IM_VSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_IM_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_get_CFG2_IM_VSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_IM_VSIZE(mask)) >> ISI_CFG2_IM_VSIZE_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG2_IM_VSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_IM_VSIZE_Msk; + tmp |= ISI_CFG2_IM_VSIZE(data); + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_IM_VSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_IM_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_IM_VSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_IM_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_read_CFG2_IM_VSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_IM_VSIZE_Msk) >> ISI_CFG2_IM_VSIZE_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG2_IM_HSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_IM_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_get_CFG2_IM_HSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_IM_HSIZE(mask)) >> ISI_CFG2_IM_HSIZE_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG2_IM_HSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_IM_HSIZE_Msk; + tmp |= ISI_CFG2_IM_HSIZE(data); + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_IM_HSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_IM_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_IM_HSIZE_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_IM_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_read_CFG2_IM_HSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_IM_HSIZE_Msk) >> ISI_CFG2_IM_HSIZE_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG2_YCC_SWAP_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_YCC_SWAP(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_get_CFG2_YCC_SWAP_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_YCC_SWAP(mask)) >> ISI_CFG2_YCC_SWAP_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG2_YCC_SWAP_bf(const void *const hw, hri_isi_cfg2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_YCC_SWAP_Msk; + tmp |= ISI_CFG2_YCC_SWAP(data); + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_YCC_SWAP_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_YCC_SWAP(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_YCC_SWAP_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_YCC_SWAP(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_read_CFG2_YCC_SWAP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_YCC_SWAP_Msk) >> ISI_CFG2_YCC_SWAP_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG2_RGB_CFG_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= ISI_CFG2_RGB_CFG(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_get_CFG2_RGB_CFG_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_RGB_CFG(mask)) >> ISI_CFG2_RGB_CFG_Pos; + return tmp; +} + +static inline void hri_isi_write_CFG2_RGB_CFG_bf(const void *const hw, hri_isi_cfg2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= ~ISI_CFG2_RGB_CFG_Msk; + tmp |= ISI_CFG2_RGB_CFG(data); + ((Isi *)hw)->ISI_CFG2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_RGB_CFG_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~ISI_CFG2_RGB_CFG(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_RGB_CFG_bf(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= ISI_CFG2_RGB_CFG(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_read_CFG2_RGB_CFG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp = (tmp & ISI_CFG2_RGB_CFG_Msk) >> ISI_CFG2_RGB_CFG_Pos; + return tmp; +} + +static inline void hri_isi_set_CFG2_reg(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_get_CFG2_reg(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_CFG2; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_CFG2_reg(const void *const hw, hri_isi_cfg2_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_CFG2_reg(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_CFG2_reg(const void *const hw, hri_isi_cfg2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CFG2 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_cfg2_reg_t hri_isi_read_CFG2_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_CFG2; +} + +static inline void hri_isi_set_PSIZE_PREV_VSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE |= ISI_PSIZE_PREV_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_get_PSIZE_PREV_VSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp = (tmp & ISI_PSIZE_PREV_VSIZE(mask)) >> ISI_PSIZE_PREV_VSIZE_Pos; + return tmp; +} + +static inline void hri_isi_write_PSIZE_PREV_VSIZE_bf(const void *const hw, hri_isi_psize_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp &= ~ISI_PSIZE_PREV_VSIZE_Msk; + tmp |= ISI_PSIZE_PREV_VSIZE(data); + ((Isi *)hw)->ISI_PSIZE = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_PSIZE_PREV_VSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE &= ~ISI_PSIZE_PREV_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_PSIZE_PREV_VSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE ^= ISI_PSIZE_PREV_VSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_read_PSIZE_PREV_VSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp = (tmp & ISI_PSIZE_PREV_VSIZE_Msk) >> ISI_PSIZE_PREV_VSIZE_Pos; + return tmp; +} + +static inline void hri_isi_set_PSIZE_PREV_HSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE |= ISI_PSIZE_PREV_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_get_PSIZE_PREV_HSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp = (tmp & ISI_PSIZE_PREV_HSIZE(mask)) >> ISI_PSIZE_PREV_HSIZE_Pos; + return tmp; +} + +static inline void hri_isi_write_PSIZE_PREV_HSIZE_bf(const void *const hw, hri_isi_psize_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp &= ~ISI_PSIZE_PREV_HSIZE_Msk; + tmp |= ISI_PSIZE_PREV_HSIZE(data); + ((Isi *)hw)->ISI_PSIZE = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_PSIZE_PREV_HSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE &= ~ISI_PSIZE_PREV_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_PSIZE_PREV_HSIZE_bf(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE ^= ISI_PSIZE_PREV_HSIZE(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_read_PSIZE_PREV_HSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp = (tmp & ISI_PSIZE_PREV_HSIZE_Msk) >> ISI_PSIZE_PREV_HSIZE_Pos; + return tmp; +} + +static inline void hri_isi_set_PSIZE_reg(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_get_PSIZE_reg(const void *const hw, hri_isi_psize_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PSIZE; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_PSIZE_reg(const void *const hw, hri_isi_psize_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_PSIZE_reg(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_PSIZE_reg(const void *const hw, hri_isi_psize_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PSIZE ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_psize_reg_t hri_isi_read_PSIZE_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_PSIZE; +} + +static inline void hri_isi_set_PDECF_DEC_FACTOR_bf(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF |= ISI_PDECF_DEC_FACTOR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_pdecf_reg_t hri_isi_get_PDECF_DEC_FACTOR_bf(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PDECF; + tmp = (tmp & ISI_PDECF_DEC_FACTOR(mask)) >> ISI_PDECF_DEC_FACTOR_Pos; + return tmp; +} + +static inline void hri_isi_write_PDECF_DEC_FACTOR_bf(const void *const hw, hri_isi_pdecf_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_PDECF; + tmp &= ~ISI_PDECF_DEC_FACTOR_Msk; + tmp |= ISI_PDECF_DEC_FACTOR(data); + ((Isi *)hw)->ISI_PDECF = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_PDECF_DEC_FACTOR_bf(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF &= ~ISI_PDECF_DEC_FACTOR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_PDECF_DEC_FACTOR_bf(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF ^= ISI_PDECF_DEC_FACTOR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_pdecf_reg_t hri_isi_read_PDECF_DEC_FACTOR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PDECF; + tmp = (tmp & ISI_PDECF_DEC_FACTOR_Msk) >> ISI_PDECF_DEC_FACTOR_Pos; + return tmp; +} + +static inline void hri_isi_set_PDECF_reg(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_pdecf_reg_t hri_isi_get_PDECF_reg(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_PDECF; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_PDECF_reg(const void *const hw, hri_isi_pdecf_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_PDECF_reg(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_PDECF_reg(const void *const hw, hri_isi_pdecf_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_PDECF ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_pdecf_reg_t hri_isi_read_PDECF_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_PDECF; +} + +static inline void hri_isi_set_Y2R_SET0_C0_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 |= ISI_Y2R_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_get_Y2R_SET0_C0_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C0(mask)) >> ISI_Y2R_SET0_C0_Pos; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET0_C0_bf(const void *const hw, hri_isi_y2r_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp &= ~ISI_Y2R_SET0_C0_Msk; + tmp |= ISI_Y2R_SET0_C0(data); + ((Isi *)hw)->ISI_Y2R_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET0_C0_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 &= ~ISI_Y2R_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET0_C0_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 ^= ISI_Y2R_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_read_Y2R_SET0_C0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C0_Msk) >> ISI_Y2R_SET0_C0_Pos; + return tmp; +} + +static inline void hri_isi_set_Y2R_SET0_C1_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 |= ISI_Y2R_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_get_Y2R_SET0_C1_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C1(mask)) >> ISI_Y2R_SET0_C1_Pos; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET0_C1_bf(const void *const hw, hri_isi_y2r_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp &= ~ISI_Y2R_SET0_C1_Msk; + tmp |= ISI_Y2R_SET0_C1(data); + ((Isi *)hw)->ISI_Y2R_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET0_C1_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 &= ~ISI_Y2R_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET0_C1_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 ^= ISI_Y2R_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_read_Y2R_SET0_C1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C1_Msk) >> ISI_Y2R_SET0_C1_Pos; + return tmp; +} + +static inline void hri_isi_set_Y2R_SET0_C2_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 |= ISI_Y2R_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_get_Y2R_SET0_C2_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C2(mask)) >> ISI_Y2R_SET0_C2_Pos; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET0_C2_bf(const void *const hw, hri_isi_y2r_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp &= ~ISI_Y2R_SET0_C2_Msk; + tmp |= ISI_Y2R_SET0_C2(data); + ((Isi *)hw)->ISI_Y2R_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET0_C2_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 &= ~ISI_Y2R_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET0_C2_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 ^= ISI_Y2R_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_read_Y2R_SET0_C2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C2_Msk) >> ISI_Y2R_SET0_C2_Pos; + return tmp; +} + +static inline void hri_isi_set_Y2R_SET0_C3_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 |= ISI_Y2R_SET0_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_get_Y2R_SET0_C3_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C3(mask)) >> ISI_Y2R_SET0_C3_Pos; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET0_C3_bf(const void *const hw, hri_isi_y2r_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp &= ~ISI_Y2R_SET0_C3_Msk; + tmp |= ISI_Y2R_SET0_C3(data); + ((Isi *)hw)->ISI_Y2R_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET0_C3_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 &= ~ISI_Y2R_SET0_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET0_C3_bf(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 ^= ISI_Y2R_SET0_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_read_Y2R_SET0_C3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp = (tmp & ISI_Y2R_SET0_C3_Msk) >> ISI_Y2R_SET0_C3_Pos; + return tmp; +} + +static inline void hri_isi_set_Y2R_SET0_reg(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_get_Y2R_SET0_reg(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET0; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET0_reg(const void *const hw, hri_isi_y2r_set0_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET0_reg(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET0_reg(const void *const hw, hri_isi_y2r_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET0 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set0_reg_t hri_isi_read_Y2R_SET0_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_Y2R_SET0; +} + +static inline void hri_isi_set_Y2R_SET1_Yoff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 |= ISI_Y2R_SET1_Yoff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_Y2R_SET1_Yoff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp = (tmp & ISI_Y2R_SET1_Yoff) >> ISI_Y2R_SET1_Yoff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_Y2R_SET1_Yoff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp &= ~ISI_Y2R_SET1_Yoff; + tmp |= value << ISI_Y2R_SET1_Yoff_Pos; + ((Isi *)hw)->ISI_Y2R_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET1_Yoff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 &= ~ISI_Y2R_SET1_Yoff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET1_Yoff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 ^= ISI_Y2R_SET1_Yoff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_Y2R_SET1_Croff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 |= ISI_Y2R_SET1_Croff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_Y2R_SET1_Croff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp = (tmp & ISI_Y2R_SET1_Croff) >> ISI_Y2R_SET1_Croff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_Y2R_SET1_Croff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp &= ~ISI_Y2R_SET1_Croff; + tmp |= value << ISI_Y2R_SET1_Croff_Pos; + ((Isi *)hw)->ISI_Y2R_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET1_Croff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 &= ~ISI_Y2R_SET1_Croff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET1_Croff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 ^= ISI_Y2R_SET1_Croff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_Y2R_SET1_Cboff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 |= ISI_Y2R_SET1_Cboff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_Y2R_SET1_Cboff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp = (tmp & ISI_Y2R_SET1_Cboff) >> ISI_Y2R_SET1_Cboff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_Y2R_SET1_Cboff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp &= ~ISI_Y2R_SET1_Cboff; + tmp |= value << ISI_Y2R_SET1_Cboff_Pos; + ((Isi *)hw)->ISI_Y2R_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET1_Cboff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 &= ~ISI_Y2R_SET1_Cboff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET1_Cboff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 ^= ISI_Y2R_SET1_Cboff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_Y2R_SET1_C4_bf(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 |= ISI_Y2R_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set1_reg_t hri_isi_get_Y2R_SET1_C4_bf(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp = (tmp & ISI_Y2R_SET1_C4(mask)) >> ISI_Y2R_SET1_C4_Pos; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET1_C4_bf(const void *const hw, hri_isi_y2r_set1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp &= ~ISI_Y2R_SET1_C4_Msk; + tmp |= ISI_Y2R_SET1_C4(data); + ((Isi *)hw)->ISI_Y2R_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET1_C4_bf(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 &= ~ISI_Y2R_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET1_C4_bf(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 ^= ISI_Y2R_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set1_reg_t hri_isi_read_Y2R_SET1_C4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp = (tmp & ISI_Y2R_SET1_C4_Msk) >> ISI_Y2R_SET1_C4_Pos; + return tmp; +} + +static inline void hri_isi_set_Y2R_SET1_reg(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set1_reg_t hri_isi_get_Y2R_SET1_reg(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_Y2R_SET1; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_Y2R_SET1_reg(const void *const hw, hri_isi_y2r_set1_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_Y2R_SET1_reg(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_Y2R_SET1_reg(const void *const hw, hri_isi_y2r_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_Y2R_SET1 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_y2r_set1_reg_t hri_isi_read_Y2R_SET1_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_Y2R_SET1; +} + +static inline void hri_isi_set_R2Y_SET0_Roff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 |= ISI_R2Y_SET0_Roff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_R2Y_SET0_Roff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_Roff) >> ISI_R2Y_SET0_Roff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_R2Y_SET0_Roff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp &= ~ISI_R2Y_SET0_Roff; + tmp |= value << ISI_R2Y_SET0_Roff_Pos; + ((Isi *)hw)->ISI_R2Y_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET0_Roff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 &= ~ISI_R2Y_SET0_Roff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET0_Roff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 ^= ISI_R2Y_SET0_Roff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_R2Y_SET0_C0_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 |= ISI_R2Y_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_get_R2Y_SET0_C0_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C0(mask)) >> ISI_R2Y_SET0_C0_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET0_C0_bf(const void *const hw, hri_isi_r2y_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp &= ~ISI_R2Y_SET0_C0_Msk; + tmp |= ISI_R2Y_SET0_C0(data); + ((Isi *)hw)->ISI_R2Y_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET0_C0_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 &= ~ISI_R2Y_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET0_C0_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 ^= ISI_R2Y_SET0_C0(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_read_R2Y_SET0_C0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C0_Msk) >> ISI_R2Y_SET0_C0_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET0_C1_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 |= ISI_R2Y_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_get_R2Y_SET0_C1_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C1(mask)) >> ISI_R2Y_SET0_C1_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET0_C1_bf(const void *const hw, hri_isi_r2y_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp &= ~ISI_R2Y_SET0_C1_Msk; + tmp |= ISI_R2Y_SET0_C1(data); + ((Isi *)hw)->ISI_R2Y_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET0_C1_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 &= ~ISI_R2Y_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET0_C1_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 ^= ISI_R2Y_SET0_C1(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_read_R2Y_SET0_C1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C1_Msk) >> ISI_R2Y_SET0_C1_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET0_C2_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 |= ISI_R2Y_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_get_R2Y_SET0_C2_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C2(mask)) >> ISI_R2Y_SET0_C2_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET0_C2_bf(const void *const hw, hri_isi_r2y_set0_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp &= ~ISI_R2Y_SET0_C2_Msk; + tmp |= ISI_R2Y_SET0_C2(data); + ((Isi *)hw)->ISI_R2Y_SET0 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET0_C2_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 &= ~ISI_R2Y_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET0_C2_bf(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 ^= ISI_R2Y_SET0_C2(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_read_R2Y_SET0_C2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp = (tmp & ISI_R2Y_SET0_C2_Msk) >> ISI_R2Y_SET0_C2_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET0_reg(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_get_R2Y_SET0_reg(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET0; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET0_reg(const void *const hw, hri_isi_r2y_set0_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET0_reg(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET0_reg(const void *const hw, hri_isi_r2y_set0_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET0 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set0_reg_t hri_isi_read_R2Y_SET0_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_R2Y_SET0; +} + +static inline void hri_isi_set_R2Y_SET1_Goff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 |= ISI_R2Y_SET1_Goff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_R2Y_SET1_Goff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_Goff) >> ISI_R2Y_SET1_Goff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_R2Y_SET1_Goff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp &= ~ISI_R2Y_SET1_Goff; + tmp |= value << ISI_R2Y_SET1_Goff_Pos; + ((Isi *)hw)->ISI_R2Y_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET1_Goff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 &= ~ISI_R2Y_SET1_Goff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET1_Goff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 ^= ISI_R2Y_SET1_Goff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_R2Y_SET1_C3_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 |= ISI_R2Y_SET1_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_get_R2Y_SET1_C3_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C3(mask)) >> ISI_R2Y_SET1_C3_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET1_C3_bf(const void *const hw, hri_isi_r2y_set1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp &= ~ISI_R2Y_SET1_C3_Msk; + tmp |= ISI_R2Y_SET1_C3(data); + ((Isi *)hw)->ISI_R2Y_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET1_C3_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 &= ~ISI_R2Y_SET1_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET1_C3_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 ^= ISI_R2Y_SET1_C3(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_read_R2Y_SET1_C3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C3_Msk) >> ISI_R2Y_SET1_C3_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET1_C4_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 |= ISI_R2Y_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_get_R2Y_SET1_C4_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C4(mask)) >> ISI_R2Y_SET1_C4_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET1_C4_bf(const void *const hw, hri_isi_r2y_set1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp &= ~ISI_R2Y_SET1_C4_Msk; + tmp |= ISI_R2Y_SET1_C4(data); + ((Isi *)hw)->ISI_R2Y_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET1_C4_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 &= ~ISI_R2Y_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET1_C4_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 ^= ISI_R2Y_SET1_C4(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_read_R2Y_SET1_C4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C4_Msk) >> ISI_R2Y_SET1_C4_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET1_C5_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 |= ISI_R2Y_SET1_C5(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_get_R2Y_SET1_C5_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C5(mask)) >> ISI_R2Y_SET1_C5_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET1_C5_bf(const void *const hw, hri_isi_r2y_set1_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp &= ~ISI_R2Y_SET1_C5_Msk; + tmp |= ISI_R2Y_SET1_C5(data); + ((Isi *)hw)->ISI_R2Y_SET1 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET1_C5_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 &= ~ISI_R2Y_SET1_C5(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET1_C5_bf(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 ^= ISI_R2Y_SET1_C5(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_read_R2Y_SET1_C5_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp = (tmp & ISI_R2Y_SET1_C5_Msk) >> ISI_R2Y_SET1_C5_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET1_reg(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_get_R2Y_SET1_reg(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET1; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET1_reg(const void *const hw, hri_isi_r2y_set1_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET1_reg(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET1_reg(const void *const hw, hri_isi_r2y_set1_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET1 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set1_reg_t hri_isi_read_R2Y_SET1_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_R2Y_SET1; +} + +static inline void hri_isi_set_R2Y_SET2_Boff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 |= ISI_R2Y_SET2_Boff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_R2Y_SET2_Boff_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_Boff) >> ISI_R2Y_SET2_Boff_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_R2Y_SET2_Boff_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp &= ~ISI_R2Y_SET2_Boff; + tmp |= value << ISI_R2Y_SET2_Boff_Pos; + ((Isi *)hw)->ISI_R2Y_SET2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET2_Boff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 &= ~ISI_R2Y_SET2_Boff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET2_Boff_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 ^= ISI_R2Y_SET2_Boff; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_R2Y_SET2_C6_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 |= ISI_R2Y_SET2_C6(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_get_R2Y_SET2_C6_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C6(mask)) >> ISI_R2Y_SET2_C6_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET2_C6_bf(const void *const hw, hri_isi_r2y_set2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp &= ~ISI_R2Y_SET2_C6_Msk; + tmp |= ISI_R2Y_SET2_C6(data); + ((Isi *)hw)->ISI_R2Y_SET2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET2_C6_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 &= ~ISI_R2Y_SET2_C6(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET2_C6_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 ^= ISI_R2Y_SET2_C6(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_read_R2Y_SET2_C6_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C6_Msk) >> ISI_R2Y_SET2_C6_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET2_C7_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 |= ISI_R2Y_SET2_C7(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_get_R2Y_SET2_C7_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C7(mask)) >> ISI_R2Y_SET2_C7_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET2_C7_bf(const void *const hw, hri_isi_r2y_set2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp &= ~ISI_R2Y_SET2_C7_Msk; + tmp |= ISI_R2Y_SET2_C7(data); + ((Isi *)hw)->ISI_R2Y_SET2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET2_C7_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 &= ~ISI_R2Y_SET2_C7(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET2_C7_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 ^= ISI_R2Y_SET2_C7(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_read_R2Y_SET2_C7_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C7_Msk) >> ISI_R2Y_SET2_C7_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET2_C8_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 |= ISI_R2Y_SET2_C8(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_get_R2Y_SET2_C8_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C8(mask)) >> ISI_R2Y_SET2_C8_Pos; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET2_C8_bf(const void *const hw, hri_isi_r2y_set2_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp &= ~ISI_R2Y_SET2_C8_Msk; + tmp |= ISI_R2Y_SET2_C8(data); + ((Isi *)hw)->ISI_R2Y_SET2 = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET2_C8_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 &= ~ISI_R2Y_SET2_C8(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET2_C8_bf(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 ^= ISI_R2Y_SET2_C8(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_read_R2Y_SET2_C8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp = (tmp & ISI_R2Y_SET2_C8_Msk) >> ISI_R2Y_SET2_C8_Pos; + return tmp; +} + +static inline void hri_isi_set_R2Y_SET2_reg(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_get_R2Y_SET2_reg(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_R2Y_SET2; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_R2Y_SET2_reg(const void *const hw, hri_isi_r2y_set2_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_R2Y_SET2_reg(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_R2Y_SET2_reg(const void *const hw, hri_isi_r2y_set2_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_R2Y_SET2 ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_r2y_set2_reg_t hri_isi_read_R2Y_SET2_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_R2Y_SET2; +} + +static inline void hri_isi_set_DMA_P_ADDR_P_ADDR_bf(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR |= ISI_DMA_P_ADDR_P_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_addr_reg_t hri_isi_get_DMA_P_ADDR_P_ADDR_bf(const void *const hw, + hri_isi_dma_p_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_ADDR; + tmp = (tmp & ISI_DMA_P_ADDR_P_ADDR(mask)) >> ISI_DMA_P_ADDR_P_ADDR_Pos; + return tmp; +} + +static inline void hri_isi_write_DMA_P_ADDR_P_ADDR_bf(const void *const hw, hri_isi_dma_p_addr_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_ADDR; + tmp &= ~ISI_DMA_P_ADDR_P_ADDR_Msk; + tmp |= ISI_DMA_P_ADDR_P_ADDR(data); + ((Isi *)hw)->ISI_DMA_P_ADDR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_ADDR_P_ADDR_bf(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR &= ~ISI_DMA_P_ADDR_P_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_ADDR_P_ADDR_bf(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR ^= ISI_DMA_P_ADDR_P_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_addr_reg_t hri_isi_read_DMA_P_ADDR_P_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_ADDR; + tmp = (tmp & ISI_DMA_P_ADDR_P_ADDR_Msk) >> ISI_DMA_P_ADDR_P_ADDR_Pos; + return tmp; +} + +static inline void hri_isi_set_DMA_P_ADDR_reg(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_addr_reg_t hri_isi_get_DMA_P_ADDR_reg(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_ADDR; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_P_ADDR_reg(const void *const hw, hri_isi_dma_p_addr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_ADDR_reg(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_ADDR_reg(const void *const hw, hri_isi_dma_p_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_ADDR ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_addr_reg_t hri_isi_read_DMA_P_ADDR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_P_ADDR; +} + +static inline void hri_isi_set_DMA_P_CTRL_P_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL |= ISI_DMA_P_CTRL_P_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_P_CTRL_P_FETCH_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp = (tmp & ISI_DMA_P_CTRL_P_FETCH) >> ISI_DMA_P_CTRL_P_FETCH_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_P_CTRL_P_FETCH_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp &= ~ISI_DMA_P_CTRL_P_FETCH; + tmp |= value << ISI_DMA_P_CTRL_P_FETCH_Pos; + ((Isi *)hw)->ISI_DMA_P_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_CTRL_P_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL &= ~ISI_DMA_P_CTRL_P_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_CTRL_P_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL ^= ISI_DMA_P_CTRL_P_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_P_CTRL_P_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL |= ISI_DMA_P_CTRL_P_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_P_CTRL_P_WB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp = (tmp & ISI_DMA_P_CTRL_P_WB) >> ISI_DMA_P_CTRL_P_WB_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_P_CTRL_P_WB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp &= ~ISI_DMA_P_CTRL_P_WB; + tmp |= value << ISI_DMA_P_CTRL_P_WB_Pos; + ((Isi *)hw)->ISI_DMA_P_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_CTRL_P_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL &= ~ISI_DMA_P_CTRL_P_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_CTRL_P_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL ^= ISI_DMA_P_CTRL_P_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_P_CTRL_P_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL |= ISI_DMA_P_CTRL_P_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_P_CTRL_P_IEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp = (tmp & ISI_DMA_P_CTRL_P_IEN) >> ISI_DMA_P_CTRL_P_IEN_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_P_CTRL_P_IEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp &= ~ISI_DMA_P_CTRL_P_IEN; + tmp |= value << ISI_DMA_P_CTRL_P_IEN_Pos; + ((Isi *)hw)->ISI_DMA_P_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_CTRL_P_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL &= ~ISI_DMA_P_CTRL_P_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_CTRL_P_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL ^= ISI_DMA_P_CTRL_P_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_P_CTRL_P_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL |= ISI_DMA_P_CTRL_P_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_P_CTRL_P_DONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp = (tmp & ISI_DMA_P_CTRL_P_DONE) >> ISI_DMA_P_CTRL_P_DONE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_P_CTRL_P_DONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp &= ~ISI_DMA_P_CTRL_P_DONE; + tmp |= value << ISI_DMA_P_CTRL_P_DONE_Pos; + ((Isi *)hw)->ISI_DMA_P_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_CTRL_P_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL &= ~ISI_DMA_P_CTRL_P_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_CTRL_P_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL ^= ISI_DMA_P_CTRL_P_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_P_CTRL_reg(const void *const hw, hri_isi_dma_p_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_ctrl_reg_t hri_isi_get_DMA_P_CTRL_reg(const void *const hw, hri_isi_dma_p_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_CTRL; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_P_CTRL_reg(const void *const hw, hri_isi_dma_p_ctrl_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_CTRL_reg(const void *const hw, hri_isi_dma_p_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_CTRL_reg(const void *const hw, hri_isi_dma_p_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_CTRL ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_ctrl_reg_t hri_isi_read_DMA_P_CTRL_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_P_CTRL; +} + +static inline void hri_isi_set_DMA_P_DSCR_P_DSCR_bf(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR |= ISI_DMA_P_DSCR_P_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_dscr_reg_t hri_isi_get_DMA_P_DSCR_P_DSCR_bf(const void *const hw, + hri_isi_dma_p_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_DSCR; + tmp = (tmp & ISI_DMA_P_DSCR_P_DSCR(mask)) >> ISI_DMA_P_DSCR_P_DSCR_Pos; + return tmp; +} + +static inline void hri_isi_write_DMA_P_DSCR_P_DSCR_bf(const void *const hw, hri_isi_dma_p_dscr_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_P_DSCR; + tmp &= ~ISI_DMA_P_DSCR_P_DSCR_Msk; + tmp |= ISI_DMA_P_DSCR_P_DSCR(data); + ((Isi *)hw)->ISI_DMA_P_DSCR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_DSCR_P_DSCR_bf(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR &= ~ISI_DMA_P_DSCR_P_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_DSCR_P_DSCR_bf(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR ^= ISI_DMA_P_DSCR_P_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_dscr_reg_t hri_isi_read_DMA_P_DSCR_P_DSCR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_DSCR; + tmp = (tmp & ISI_DMA_P_DSCR_P_DSCR_Msk) >> ISI_DMA_P_DSCR_P_DSCR_Pos; + return tmp; +} + +static inline void hri_isi_set_DMA_P_DSCR_reg(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_dscr_reg_t hri_isi_get_DMA_P_DSCR_reg(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_P_DSCR; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_P_DSCR_reg(const void *const hw, hri_isi_dma_p_dscr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_P_DSCR_reg(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_P_DSCR_reg(const void *const hw, hri_isi_dma_p_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_P_DSCR ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_p_dscr_reg_t hri_isi_read_DMA_P_DSCR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_P_DSCR; +} + +static inline void hri_isi_set_DMA_C_ADDR_C_ADDR_bf(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR |= ISI_DMA_C_ADDR_C_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_addr_reg_t hri_isi_get_DMA_C_ADDR_C_ADDR_bf(const void *const hw, + hri_isi_dma_c_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_ADDR; + tmp = (tmp & ISI_DMA_C_ADDR_C_ADDR(mask)) >> ISI_DMA_C_ADDR_C_ADDR_Pos; + return tmp; +} + +static inline void hri_isi_write_DMA_C_ADDR_C_ADDR_bf(const void *const hw, hri_isi_dma_c_addr_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_ADDR; + tmp &= ~ISI_DMA_C_ADDR_C_ADDR_Msk; + tmp |= ISI_DMA_C_ADDR_C_ADDR(data); + ((Isi *)hw)->ISI_DMA_C_ADDR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_ADDR_C_ADDR_bf(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR &= ~ISI_DMA_C_ADDR_C_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_ADDR_C_ADDR_bf(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR ^= ISI_DMA_C_ADDR_C_ADDR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_addr_reg_t hri_isi_read_DMA_C_ADDR_C_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_ADDR; + tmp = (tmp & ISI_DMA_C_ADDR_C_ADDR_Msk) >> ISI_DMA_C_ADDR_C_ADDR_Pos; + return tmp; +} + +static inline void hri_isi_set_DMA_C_ADDR_reg(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_addr_reg_t hri_isi_get_DMA_C_ADDR_reg(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_ADDR; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_C_ADDR_reg(const void *const hw, hri_isi_dma_c_addr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_ADDR_reg(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_ADDR_reg(const void *const hw, hri_isi_dma_c_addr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_ADDR ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_addr_reg_t hri_isi_read_DMA_C_ADDR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_C_ADDR; +} + +static inline void hri_isi_set_DMA_C_CTRL_C_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL |= ISI_DMA_C_CTRL_C_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_C_CTRL_C_FETCH_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp = (tmp & ISI_DMA_C_CTRL_C_FETCH) >> ISI_DMA_C_CTRL_C_FETCH_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_C_CTRL_C_FETCH_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp &= ~ISI_DMA_C_CTRL_C_FETCH; + tmp |= value << ISI_DMA_C_CTRL_C_FETCH_Pos; + ((Isi *)hw)->ISI_DMA_C_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_CTRL_C_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL &= ~ISI_DMA_C_CTRL_C_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_CTRL_C_FETCH_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL ^= ISI_DMA_C_CTRL_C_FETCH; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_C_CTRL_C_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL |= ISI_DMA_C_CTRL_C_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_C_CTRL_C_WB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp = (tmp & ISI_DMA_C_CTRL_C_WB) >> ISI_DMA_C_CTRL_C_WB_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_C_CTRL_C_WB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp &= ~ISI_DMA_C_CTRL_C_WB; + tmp |= value << ISI_DMA_C_CTRL_C_WB_Pos; + ((Isi *)hw)->ISI_DMA_C_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_CTRL_C_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL &= ~ISI_DMA_C_CTRL_C_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_CTRL_C_WB_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL ^= ISI_DMA_C_CTRL_C_WB; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_C_CTRL_C_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL |= ISI_DMA_C_CTRL_C_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_C_CTRL_C_IEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp = (tmp & ISI_DMA_C_CTRL_C_IEN) >> ISI_DMA_C_CTRL_C_IEN_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_C_CTRL_C_IEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp &= ~ISI_DMA_C_CTRL_C_IEN; + tmp |= value << ISI_DMA_C_CTRL_C_IEN_Pos; + ((Isi *)hw)->ISI_DMA_C_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_CTRL_C_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL &= ~ISI_DMA_C_CTRL_C_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_CTRL_C_IEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL ^= ISI_DMA_C_CTRL_C_IEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_C_CTRL_C_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL |= ISI_DMA_C_CTRL_C_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_DMA_C_CTRL_C_DONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp = (tmp & ISI_DMA_C_CTRL_C_DONE) >> ISI_DMA_C_CTRL_C_DONE_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_DMA_C_CTRL_C_DONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp &= ~ISI_DMA_C_CTRL_C_DONE; + tmp |= value << ISI_DMA_C_CTRL_C_DONE_Pos; + ((Isi *)hw)->ISI_DMA_C_CTRL = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_CTRL_C_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL &= ~ISI_DMA_C_CTRL_C_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_CTRL_C_DONE_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL ^= ISI_DMA_C_CTRL_C_DONE; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_DMA_C_CTRL_reg(const void *const hw, hri_isi_dma_c_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_ctrl_reg_t hri_isi_get_DMA_C_CTRL_reg(const void *const hw, hri_isi_dma_c_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_CTRL; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_C_CTRL_reg(const void *const hw, hri_isi_dma_c_ctrl_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_CTRL_reg(const void *const hw, hri_isi_dma_c_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_CTRL_reg(const void *const hw, hri_isi_dma_c_ctrl_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_CTRL ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_ctrl_reg_t hri_isi_read_DMA_C_CTRL_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_C_CTRL; +} + +static inline void hri_isi_set_DMA_C_DSCR_C_DSCR_bf(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR |= ISI_DMA_C_DSCR_C_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_dscr_reg_t hri_isi_get_DMA_C_DSCR_C_DSCR_bf(const void *const hw, + hri_isi_dma_c_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_DSCR; + tmp = (tmp & ISI_DMA_C_DSCR_C_DSCR(mask)) >> ISI_DMA_C_DSCR_C_DSCR_Pos; + return tmp; +} + +static inline void hri_isi_write_DMA_C_DSCR_C_DSCR_bf(const void *const hw, hri_isi_dma_c_dscr_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_DMA_C_DSCR; + tmp &= ~ISI_DMA_C_DSCR_C_DSCR_Msk; + tmp |= ISI_DMA_C_DSCR_C_DSCR(data); + ((Isi *)hw)->ISI_DMA_C_DSCR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_DSCR_C_DSCR_bf(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR &= ~ISI_DMA_C_DSCR_C_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_DSCR_C_DSCR_bf(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR ^= ISI_DMA_C_DSCR_C_DSCR(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_dscr_reg_t hri_isi_read_DMA_C_DSCR_C_DSCR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_DSCR; + tmp = (tmp & ISI_DMA_C_DSCR_C_DSCR_Msk) >> ISI_DMA_C_DSCR_C_DSCR_Pos; + return tmp; +} + +static inline void hri_isi_set_DMA_C_DSCR_reg(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_dscr_reg_t hri_isi_get_DMA_C_DSCR_reg(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_DMA_C_DSCR; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_DMA_C_DSCR_reg(const void *const hw, hri_isi_dma_c_dscr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_DMA_C_DSCR_reg(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_DMA_C_DSCR_reg(const void *const hw, hri_isi_dma_c_dscr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_DMA_C_DSCR ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_dma_c_dscr_reg_t hri_isi_read_DMA_C_DSCR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_DMA_C_DSCR; +} + +static inline void hri_isi_set_WPMR_WPEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR |= ISI_WPMR_WPEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_isi_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_WPMR; + tmp = (tmp & ISI_WPMR_WPEN) >> ISI_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_isi_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_WPMR; + tmp &= ~ISI_WPMR_WPEN; + tmp |= value << ISI_WPMR_WPEN_Pos; + ((Isi *)hw)->ISI_WPMR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_WPMR_WPEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR &= ~ISI_WPMR_WPEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_WPMR_WPEN_bit(const void *const hw) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR ^= ISI_WPMR_WPEN; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_set_WPMR_WPKEY_bf(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR |= ISI_WPMR_WPKEY(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_wpmr_reg_t hri_isi_get_WPMR_WPKEY_bf(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_WPMR; + tmp = (tmp & ISI_WPMR_WPKEY(mask)) >> ISI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_isi_write_WPMR_WPKEY_bf(const void *const hw, hri_isi_wpmr_reg_t data) +{ + uint32_t tmp; + ISI_CRITICAL_SECTION_ENTER(); + tmp = ((Isi *)hw)->ISI_WPMR; + tmp &= ~ISI_WPMR_WPKEY_Msk; + tmp |= ISI_WPMR_WPKEY(data); + ((Isi *)hw)->ISI_WPMR = tmp; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_WPMR_WPKEY_bf(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR &= ~ISI_WPMR_WPKEY(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_WPMR_WPKEY_bf(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR ^= ISI_WPMR_WPKEY(mask); + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_wpmr_reg_t hri_isi_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_WPMR; + tmp = (tmp & ISI_WPMR_WPKEY_Msk) >> ISI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_isi_set_WPMR_reg(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR |= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_wpmr_reg_t hri_isi_get_WPMR_reg(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Isi *)hw)->ISI_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_isi_write_WPMR_reg(const void *const hw, hri_isi_wpmr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_clear_WPMR_reg(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR &= ~mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_isi_toggle_WPMR_reg(const void *const hw, hri_isi_wpmr_reg_t mask) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_WPMR ^= mask; + ISI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_isi_wpmr_reg_t hri_isi_read_WPMR_reg(const void *const hw) +{ + return ((Isi *)hw)->ISI_WPMR; +} + +static inline void hri_isi_write_CR_reg(const void *const hw, hri_isi_cr_reg_t data) +{ + ISI_CRITICAL_SECTION_ENTER(); + ((Isi *)hw)->ISI_CR = data; + ISI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ISI_E70B_H_INCLUDED */ +#endif /* _SAME70_ISI_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_lockbit_e70b.h b/bsp/microchip/same70/bsp/hri/hri_lockbit_e70b.h new file mode 100644 index 0000000000..60357651b2 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_lockbit_e70b.h @@ -0,0 +1,5346 @@ +/** + * \file + * + * \brief SAM LOCKBIT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_LOCKBIT_COMPONENT_ +#ifndef _HRI_LOCKBIT_E70B_H_INCLUDED_ +#define _HRI_LOCKBIT_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_LOCKBIT_CRITICAL_SECTIONS) +#define LOCKBIT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define LOCKBIT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define LOCKBIT_CRITICAL_SECTION_ENTER() +#define LOCKBIT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_lockbit_word0_reg_t; +typedef uint32_t hri_lockbit_word1_reg_t; +typedef uint32_t hri_lockbit_word2_reg_t; +typedef uint32_t hri_lockbit_word3_reg_t; + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_0_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_0; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_0) >> 0; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_0; + tmp |= value << 0; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_0_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_0; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_0_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_0; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_1_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_1; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_1) >> 1; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_1; + tmp |= value << 1; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_1_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_1; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_1_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_1; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_2_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_2; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_2) >> 2; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_2; + tmp |= value << 2; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_2_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_2; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_2_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_2; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_3_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_3; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_3) >> 3; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_3; + tmp |= value << 3; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_3_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_3; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_3_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_3; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_4_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_4; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_4) >> 4; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_4; + tmp |= value << 4; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_4_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_4; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_4_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_4; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_5_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_5; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_5) >> 5; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_5; + tmp |= value << 5; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_5_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_5; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_5_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_5; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_6_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_6; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_6) >> 6; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_6; + tmp |= value << 6; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_6_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_6; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_6_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_6; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_7_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_7; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_7) >> 7; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_7; + tmp |= value << 7; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_7_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_7; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_7_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_7; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_8_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_8; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_8) >> 8; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_8; + tmp |= value << 8; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_8_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_8; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_8_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_8; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_9_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_9; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_9) >> 9; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_9; + tmp |= value << 9; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_9_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_9; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_9_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_9; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_10_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_10; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_10) >> 10; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_10; + tmp |= value << 10; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_10_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_10; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_10_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_10; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_11_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_11; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_11) >> 11; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_11; + tmp |= value << 11; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_11_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_11; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_11_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_11; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_12_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_12; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_12) >> 12; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_12; + tmp |= value << 12; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_12_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_12; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_12_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_12; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_13_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_13; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_13) >> 13; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_13; + tmp |= value << 13; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_13_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_13; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_13_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_13; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_14_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_14; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_14) >> 14; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_14; + tmp |= value << 14; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_14_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_14; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_14_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_14; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_15_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_15; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_15) >> 15; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_15; + tmp |= value << 15; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_15_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_15; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_15_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_15; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_16_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_16; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_16) >> 16; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_16; + tmp |= value << 16; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_16_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_16; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_16_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_16; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_17_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_17; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_17) >> 17; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_17; + tmp |= value << 17; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_17_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_17; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_17_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_17; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_18_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_18; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_18) >> 18; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_18; + tmp |= value << 18; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_18_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_18; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_18_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_18; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_19_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_19; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_19) >> 19; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_19; + tmp |= value << 19; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_19_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_19; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_19_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_19; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_20_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_20; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_20) >> 20; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_20; + tmp |= value << 20; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_20_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_20; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_20_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_20; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_21_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_21; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_21) >> 21; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_21; + tmp |= value << 21; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_21_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_21; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_21_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_21; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_22_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_22; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_22) >> 22; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_22; + tmp |= value << 22; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_22_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_22; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_22_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_22; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_23_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_23; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_23) >> 23; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_23; + tmp |= value << 23; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_23_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_23; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_23_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_23; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_24_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_24; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_24) >> 24; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_24; + tmp |= value << 24; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_24_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_24; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_24_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_24; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_25_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_25; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_25) >> 25; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_25; + tmp |= value << 25; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_25_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_25; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_25_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_25; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_26_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_26; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_26) >> 26; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_26; + tmp |= value << 26; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_26_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_26; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_26_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_26; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_27_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_27; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_27) >> 27; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_27; + tmp |= value << 27; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_27_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_27; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_27_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_27; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_28_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_28; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_28) >> 28; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_28; + tmp |= value << 28; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_28_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_28; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_28_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_28; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_29_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_29; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_29) >> 29; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_29; + tmp |= value << 29; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_29_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_29; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_29_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_29; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_30_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_30; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_30) >> 30; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_30; + tmp |= value << 30; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_30_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_30; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_30_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_30; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_LOCK_REGION_31_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= LOCKBIT_WORD0_LOCK_REGION_31; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD0_LOCK_REGION_31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp = (tmp & LOCKBIT_WORD0_LOCK_REGION_31) >> 31; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD0_LOCK_REGION_31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD0; + tmp &= ~LOCKBIT_WORD0_LOCK_REGION_31; + tmp |= value << 31; + ((Lockbit *)hw)->WORD0 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_LOCK_REGION_31_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~LOCKBIT_WORD0_LOCK_REGION_31; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_LOCK_REGION_31_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= LOCKBIT_WORD0_LOCK_REGION_31; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD0_reg(const void *const hw, hri_lockbit_word0_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 |= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word0_reg_t hri_lockbit_get_WORD0_reg(const void *const hw, hri_lockbit_word0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD0; + tmp &= mask; + return tmp; +} + +static inline void hri_lockbit_write_WORD0_reg(const void *const hw, hri_lockbit_word0_reg_t data) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 = data; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD0_reg(const void *const hw, hri_lockbit_word0_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 &= ~mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD0_reg(const void *const hw, hri_lockbit_word0_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD0 ^= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word0_reg_t hri_lockbit_read_WORD0_reg(const void *const hw) +{ + return ((Lockbit *)hw)->WORD0; +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_32_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_32; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_32) >> 0; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_32; + tmp |= value << 0; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_32_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_32; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_32_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_32; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_33_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_33; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_33) >> 1; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_33; + tmp |= value << 1; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_33_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_33; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_33_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_33; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_34_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_34; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_34) >> 2; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_34; + tmp |= value << 2; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_34_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_34; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_34_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_34; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_35_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_35; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_35) >> 3; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_35; + tmp |= value << 3; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_35_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_35; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_35_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_35; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_36_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_36; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_36) >> 4; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_36; + tmp |= value << 4; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_36_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_36; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_36_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_36; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_37_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_37; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_37) >> 5; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_37; + tmp |= value << 5; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_37_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_37; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_37_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_37; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_38_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_38; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_38) >> 6; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_38; + tmp |= value << 6; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_38_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_38; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_38_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_38; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_39_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_39; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_39) >> 7; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_39; + tmp |= value << 7; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_39_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_39; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_39_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_39; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_40_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_40; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_40) >> 8; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_40; + tmp |= value << 8; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_40_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_40; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_40_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_40; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_41_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_41; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_41) >> 9; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_41; + tmp |= value << 9; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_41_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_41; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_41_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_41; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_42_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_42; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_42) >> 10; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_42; + tmp |= value << 10; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_42_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_42; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_42_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_42; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_43_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_43; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_43) >> 11; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_43; + tmp |= value << 11; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_43_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_43; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_43_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_43; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_44_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_44; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_44) >> 12; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_44; + tmp |= value << 12; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_44_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_44; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_44_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_44; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_45_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_45; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_45) >> 13; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_45; + tmp |= value << 13; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_45_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_45; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_45_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_45; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_46_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_46; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_46) >> 14; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_46; + tmp |= value << 14; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_46_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_46; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_46_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_46; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_47_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_47; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_47) >> 15; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_47; + tmp |= value << 15; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_47_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_47; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_47_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_47; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_48_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_48; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_48) >> 16; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_48; + tmp |= value << 16; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_48_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_48; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_48_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_48; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_49_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_49; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_49) >> 17; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_49; + tmp |= value << 17; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_49_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_49; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_49_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_49; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_50_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_50; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_50) >> 18; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_50; + tmp |= value << 18; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_50_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_50; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_50_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_50; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_51_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_51; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_51) >> 19; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_51; + tmp |= value << 19; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_51_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_51; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_51_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_51; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_52_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_52; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_52) >> 20; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_52; + tmp |= value << 20; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_52_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_52; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_52_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_52; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_53_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_53; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_53) >> 21; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_53; + tmp |= value << 21; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_53_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_53; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_53_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_53; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_54_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_54; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_54) >> 22; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_54; + tmp |= value << 22; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_54_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_54; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_54_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_54; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_55_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_55; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_55) >> 23; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_55; + tmp |= value << 23; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_55_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_55; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_55_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_55; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_56_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_56; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_56) >> 24; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_56; + tmp |= value << 24; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_56_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_56; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_56_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_56; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_57_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_57; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_57) >> 25; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_57; + tmp |= value << 25; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_57_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_57; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_57_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_57; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_58_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_58; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_58) >> 26; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_58; + tmp |= value << 26; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_58_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_58; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_58_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_58; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_59_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_59; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_59) >> 27; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_59; + tmp |= value << 27; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_59_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_59; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_59_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_59; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_60_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_60; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_60) >> 28; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_60; + tmp |= value << 28; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_60_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_60; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_60_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_60; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_61_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_61; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_61) >> 29; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_61; + tmp |= value << 29; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_61_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_61; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_61_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_61; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_62_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_62; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_62) >> 30; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_62; + tmp |= value << 30; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_62_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_62; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_62_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_62; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_LOCK_REGION_63_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= LOCKBIT_WORD1_LOCK_REGION_63; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD1_LOCK_REGION_63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp = (tmp & LOCKBIT_WORD1_LOCK_REGION_63) >> 31; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD1_LOCK_REGION_63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD1; + tmp &= ~LOCKBIT_WORD1_LOCK_REGION_63; + tmp |= value << 31; + ((Lockbit *)hw)->WORD1 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_LOCK_REGION_63_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~LOCKBIT_WORD1_LOCK_REGION_63; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_LOCK_REGION_63_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= LOCKBIT_WORD1_LOCK_REGION_63; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD1_reg(const void *const hw, hri_lockbit_word1_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 |= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word1_reg_t hri_lockbit_get_WORD1_reg(const void *const hw, hri_lockbit_word1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD1; + tmp &= mask; + return tmp; +} + +static inline void hri_lockbit_write_WORD1_reg(const void *const hw, hri_lockbit_word1_reg_t data) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 = data; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD1_reg(const void *const hw, hri_lockbit_word1_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 &= ~mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD1_reg(const void *const hw, hri_lockbit_word1_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD1 ^= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word1_reg_t hri_lockbit_read_WORD1_reg(const void *const hw) +{ + return ((Lockbit *)hw)->WORD1; +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_64_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_64; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_64_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_64) >> 0; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_64_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_64; + tmp |= value << 0; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_64_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_64; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_64_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_64; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_65_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_65; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_65_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_65) >> 1; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_65_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_65; + tmp |= value << 1; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_65_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_65; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_65_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_65; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_66_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_66; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_66_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_66) >> 2; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_66_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_66; + tmp |= value << 2; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_66_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_66; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_66_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_66; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_67_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_67; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_67_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_67) >> 3; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_67_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_67; + tmp |= value << 3; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_67_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_67; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_67_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_67; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_68_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_68; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_68_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_68) >> 4; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_68_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_68; + tmp |= value << 4; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_68_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_68; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_68_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_68; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_69_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_69; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_69_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_69) >> 5; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_69_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_69; + tmp |= value << 5; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_69_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_69; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_69_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_69; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_70_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_70; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_70_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_70) >> 6; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_70_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_70; + tmp |= value << 6; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_70_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_70; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_70_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_70; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_71_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_71; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_71_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_71) >> 7; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_71_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_71; + tmp |= value << 7; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_71_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_71; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_71_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_71; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_72_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_72; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_72_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_72) >> 8; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_72_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_72; + tmp |= value << 8; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_72_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_72; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_72_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_72; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_73_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_73; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_73_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_73) >> 9; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_73_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_73; + tmp |= value << 9; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_73_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_73; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_73_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_73; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_74_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_74; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_74_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_74) >> 10; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_74_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_74; + tmp |= value << 10; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_74_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_74; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_74_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_74; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_75_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_75; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_75_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_75) >> 11; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_75_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_75; + tmp |= value << 11; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_75_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_75; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_75_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_75; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_76_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_76; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_76_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_76) >> 12; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_76_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_76; + tmp |= value << 12; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_76_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_76; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_76_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_76; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_77_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_77; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_77_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_77) >> 13; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_77_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_77; + tmp |= value << 13; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_77_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_77; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_77_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_77; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_78_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_78; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_78_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_78) >> 14; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_78_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_78; + tmp |= value << 14; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_78_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_78; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_78_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_78; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_79_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_79; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_79_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_79) >> 15; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_79_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_79; + tmp |= value << 15; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_79_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_79; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_79_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_79; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_80_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_80; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_80_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_80) >> 16; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_80_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_80; + tmp |= value << 16; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_80_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_80; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_80_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_80; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_81_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_81; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_81_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_81) >> 17; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_81_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_81; + tmp |= value << 17; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_81_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_81; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_81_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_81; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_82_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_82; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_82_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_82) >> 18; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_82_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_82; + tmp |= value << 18; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_82_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_82; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_82_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_82; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_83_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_83; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_83_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_83) >> 19; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_83_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_83; + tmp |= value << 19; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_83_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_83; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_83_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_83; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_84_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_84; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_84_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_84) >> 20; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_84_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_84; + tmp |= value << 20; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_84_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_84; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_84_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_84; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_85_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_85; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_85_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_85) >> 21; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_85_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_85; + tmp |= value << 21; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_85_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_85; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_85_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_85; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_86_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_86; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_86_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_86) >> 22; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_86_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_86; + tmp |= value << 22; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_86_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_86; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_86_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_86; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_87_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_87; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_87_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_87) >> 23; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_87_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_87; + tmp |= value << 23; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_87_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_87; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_87_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_87; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_88_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_88; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_88_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_88) >> 24; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_88_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_88; + tmp |= value << 24; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_88_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_88; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_88_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_88; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_89_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_89; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_89_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_89) >> 25; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_89_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_89; + tmp |= value << 25; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_89_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_89; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_89_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_89; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_90_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_90; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_90_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_90) >> 26; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_90_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_90; + tmp |= value << 26; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_90_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_90; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_90_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_90; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_91_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_91; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_91_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_91) >> 27; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_91_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_91; + tmp |= value << 27; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_91_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_91; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_91_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_91; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_92_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_92; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_92_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_92) >> 28; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_92_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_92; + tmp |= value << 28; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_92_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_92; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_92_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_92; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_93_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_93; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_93_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_93) >> 29; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_93_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_93; + tmp |= value << 29; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_93_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_93; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_93_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_93; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_94_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_94; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_94_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_94) >> 30; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_94_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_94; + tmp |= value << 30; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_94_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_94; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_94_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_94; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_LOCK_REGION_95_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= LOCKBIT_WORD2_LOCK_REGION_95; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD2_LOCK_REGION_95_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp = (tmp & LOCKBIT_WORD2_LOCK_REGION_95) >> 31; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD2_LOCK_REGION_95_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD2; + tmp &= ~LOCKBIT_WORD2_LOCK_REGION_95; + tmp |= value << 31; + ((Lockbit *)hw)->WORD2 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_LOCK_REGION_95_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~LOCKBIT_WORD2_LOCK_REGION_95; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_LOCK_REGION_95_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= LOCKBIT_WORD2_LOCK_REGION_95; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD2_reg(const void *const hw, hri_lockbit_word2_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 |= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word2_reg_t hri_lockbit_get_WORD2_reg(const void *const hw, hri_lockbit_word2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD2; + tmp &= mask; + return tmp; +} + +static inline void hri_lockbit_write_WORD2_reg(const void *const hw, hri_lockbit_word2_reg_t data) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 = data; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD2_reg(const void *const hw, hri_lockbit_word2_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 &= ~mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD2_reg(const void *const hw, hri_lockbit_word2_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD2 ^= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word2_reg_t hri_lockbit_read_WORD2_reg(const void *const hw) +{ + return ((Lockbit *)hw)->WORD2; +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_96_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_96; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_96_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_96) >> 0; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_96_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_96; + tmp |= value << 0; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_96_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_96; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_96_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_96; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_97_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_97; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_97_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_97) >> 1; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_97_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_97; + tmp |= value << 1; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_97_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_97; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_97_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_97; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_98_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_98; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_98_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_98) >> 2; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_98_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_98; + tmp |= value << 2; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_98_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_98; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_98_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_98; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_99_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_99; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_99_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_99) >> 3; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_99_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_99; + tmp |= value << 3; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_99_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_99; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_99_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_99; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_100_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_100; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_100_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_100) >> 4; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_100_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_100; + tmp |= value << 4; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_100_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_100; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_100_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_100; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_101_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_101; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_101_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_101) >> 5; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_101_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_101; + tmp |= value << 5; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_101_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_101; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_101_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_101; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_102_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_102; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_102_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_102) >> 6; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_102_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_102; + tmp |= value << 6; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_102_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_102; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_102_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_102; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_103_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_103; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_103_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_103) >> 7; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_103_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_103; + tmp |= value << 7; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_103_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_103; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_103_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_103; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_104_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_104; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_104_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_104) >> 8; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_104_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_104; + tmp |= value << 8; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_104_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_104; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_104_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_104; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_105_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_105; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_105_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_105) >> 9; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_105_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_105; + tmp |= value << 9; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_105_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_105; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_105_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_105; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_106_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_106; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_106_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_106) >> 10; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_106_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_106; + tmp |= value << 10; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_106_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_106; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_106_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_106; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_107_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_107; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_107_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_107) >> 11; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_107_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_107; + tmp |= value << 11; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_107_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_107; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_107_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_107; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_108_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_108; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_108_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_108) >> 12; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_108_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_108; + tmp |= value << 12; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_108_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_108; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_108_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_108; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_109_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_109; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_109_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_109) >> 13; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_109_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_109; + tmp |= value << 13; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_109_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_109; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_109_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_109; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_110_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_110; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_110_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_110) >> 14; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_110_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_110; + tmp |= value << 14; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_110_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_110; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_110_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_110; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_111_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_111; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_111_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_111) >> 15; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_111_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_111; + tmp |= value << 15; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_111_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_111; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_111_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_111; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_112_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_112; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_112_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_112) >> 16; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_112_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_112; + tmp |= value << 16; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_112_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_112; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_112_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_112; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_113_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_113; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_113_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_113) >> 17; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_113_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_113; + tmp |= value << 17; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_113_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_113; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_113_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_113; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_114_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_114; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_114_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_114) >> 18; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_114_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_114; + tmp |= value << 18; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_114_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_114; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_114_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_114; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_115_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_115; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_115_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_115) >> 19; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_115_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_115; + tmp |= value << 19; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_115_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_115; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_115_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_115; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_116_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_116; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_116_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_116) >> 20; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_116_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_116; + tmp |= value << 20; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_116_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_116; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_116_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_116; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_117_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_117; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_117_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_117) >> 21; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_117_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_117; + tmp |= value << 21; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_117_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_117; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_117_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_117; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_118_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_118; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_118_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_118) >> 22; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_118_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_118; + tmp |= value << 22; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_118_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_118; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_118_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_118; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_119_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_119; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_119_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_119) >> 23; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_119_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_119; + tmp |= value << 23; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_119_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_119; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_119_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_119; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_120_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_120; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_120_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_120) >> 24; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_120_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_120; + tmp |= value << 24; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_120_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_120; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_120_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_120; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_121_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_121; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_121_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_121) >> 25; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_121_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_121; + tmp |= value << 25; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_121_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_121; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_121_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_121; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_122_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_122; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_122_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_122) >> 26; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_122_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_122; + tmp |= value << 26; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_122_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_122; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_122_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_122; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_123_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_123; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_123_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_123) >> 27; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_123_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_123; + tmp |= value << 27; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_123_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_123; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_123_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_123; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_124_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_124; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_124_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_124) >> 28; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_124_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_124; + tmp |= value << 28; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_124_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_124; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_124_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_124; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_125_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_125; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_125_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_125) >> 29; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_125_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_125; + tmp |= value << 29; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_125_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_125; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_125_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_125; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_126_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_126; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_126_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_126) >> 30; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_126_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_126; + tmp |= value << 30; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_126_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_126; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_126_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_126; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_LOCK_REGION_127_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= LOCKBIT_WORD3_LOCK_REGION_127; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_lockbit_get_WORD3_LOCK_REGION_127_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp = (tmp & LOCKBIT_WORD3_LOCK_REGION_127) >> 31; + return (bool)tmp; +} + +static inline void hri_lockbit_write_WORD3_LOCK_REGION_127_bit(const void *const hw, bool value) +{ + uint32_t tmp; + LOCKBIT_CRITICAL_SECTION_ENTER(); + tmp = ((Lockbit *)hw)->WORD3; + tmp &= ~LOCKBIT_WORD3_LOCK_REGION_127; + tmp |= value << 31; + ((Lockbit *)hw)->WORD3 = tmp; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_LOCK_REGION_127_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~LOCKBIT_WORD3_LOCK_REGION_127; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_LOCK_REGION_127_bit(const void *const hw) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= LOCKBIT_WORD3_LOCK_REGION_127; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_set_WORD3_reg(const void *const hw, hri_lockbit_word3_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 |= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word3_reg_t hri_lockbit_get_WORD3_reg(const void *const hw, hri_lockbit_word3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Lockbit *)hw)->WORD3; + tmp &= mask; + return tmp; +} + +static inline void hri_lockbit_write_WORD3_reg(const void *const hw, hri_lockbit_word3_reg_t data) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 = data; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_clear_WORD3_reg(const void *const hw, hri_lockbit_word3_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 &= ~mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_lockbit_toggle_WORD3_reg(const void *const hw, hri_lockbit_word3_reg_t mask) +{ + LOCKBIT_CRITICAL_SECTION_ENTER(); + ((Lockbit *)hw)->WORD3 ^= mask; + LOCKBIT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_lockbit_word3_reg_t hri_lockbit_read_WORD3_reg(const void *const hw) +{ + return ((Lockbit *)hw)->WORD3; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_LOCKBIT_E70B_H_INCLUDED */ +#endif /* _SAME70_LOCKBIT_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_matrix_e70b.h b/bsp/microchip/same70/bsp/hri/hri_matrix_e70b.h new file mode 100644 index 0000000000..7119c05a5e --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_matrix_e70b.h @@ -0,0 +1,3363 @@ +/** + * \file + * + * \brief SAM MATRIX + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_MATRIX_COMPONENT_ +#ifndef _HRI_MATRIX_E70B_H_INCLUDED_ +#define _HRI_MATRIX_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MATRIX_CRITICAL_SECTIONS) +#define MATRIX_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MATRIX_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MATRIX_CRITICAL_SECTION_ENTER() +#define MATRIX_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_matrix_ccfg_can0_reg_t; +typedef uint32_t hri_matrix_ccfg_dynckg_reg_t; +typedef uint32_t hri_matrix_ccfg_pccr_reg_t; +typedef uint32_t hri_matrix_ccfg_smcnfcs_reg_t; +typedef uint32_t hri_matrix_ccfg_sysio_reg_t; +typedef uint32_t hri_matrix_mcfg_reg_t; +typedef uint32_t hri_matrix_mrcr_reg_t; +typedef uint32_t hri_matrix_pras_reg_t; +typedef uint32_t hri_matrix_prbs_reg_t; +typedef uint32_t hri_matrix_scfg_reg_t; +typedef uint32_t hri_matrix_wpmr_reg_t; +typedef uint32_t hri_matrix_wpsr_reg_t; +typedef uint32_t hri_matrixpr_pras_reg_t; +typedef uint32_t hri_matrixpr_prbs_reg_t; + +static inline void hri_matrixpr_set_PRAS_M0PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M0PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M0PR(mask)) >> MATRIX_PRAS_M0PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M0PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M0PR_Msk; + tmp |= MATRIX_PRAS_M0PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M0PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M0PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M0PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M0PR_Msk) >> MATRIX_PRAS_M0PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M1PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M1PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M1PR(mask)) >> MATRIX_PRAS_M1PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M1PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M1PR_Msk; + tmp |= MATRIX_PRAS_M1PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M1PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M1PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M1PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M1PR_Msk) >> MATRIX_PRAS_M1PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M2PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M2PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M2PR(mask)) >> MATRIX_PRAS_M2PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M2PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M2PR_Msk; + tmp |= MATRIX_PRAS_M2PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M2PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M2PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M2PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M2PR_Msk) >> MATRIX_PRAS_M2PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M3PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M3PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M3PR(mask)) >> MATRIX_PRAS_M3PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M3PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M3PR_Msk; + tmp |= MATRIX_PRAS_M3PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M3PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M3PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M3PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M3PR_Msk) >> MATRIX_PRAS_M3PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M4PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M4PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M4PR(mask)) >> MATRIX_PRAS_M4PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M4PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M4PR_Msk; + tmp |= MATRIX_PRAS_M4PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M4PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M4PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M4PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M4PR_Msk) >> MATRIX_PRAS_M4PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M5PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M5PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M5PR(mask)) >> MATRIX_PRAS_M5PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M5PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M5PR_Msk; + tmp |= MATRIX_PRAS_M5PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M5PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M5PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M5PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M5PR_Msk) >> MATRIX_PRAS_M5PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_M6PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_M6PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M6PR(mask)) >> MATRIX_PRAS_M6PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_M6PR_bf(const void *const hw, hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M6PR_Msk; + tmp |= MATRIX_PRAS_M6PR(data); + ((MatrixPr *)hw)->MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_M6PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_M6PR_bf(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_M6PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M6PR_Msk) >> MATRIX_PRAS_M6PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRAS_reg(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_get_PRAS_reg(const void *const hw, hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRAS; + tmp &= mask; + return tmp; +} + +static inline void hri_matrixpr_write_PRAS_reg(const void *const hw, hri_matrix_pras_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRAS_reg(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRAS_reg(const void *const hw, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRAS ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrixpr_read_PRAS_reg(const void *const hw) +{ + return ((MatrixPr *)hw)->MATRIX_PRAS; +} + +static inline void hri_matrixpr_set_PRBS_M8PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_M8PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M8PR(mask)) >> MATRIX_PRBS_M8PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_M8PR_bf(const void *const hw, hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M8PR_Msk; + tmp |= MATRIX_PRBS_M8PR(data); + ((MatrixPr *)hw)->MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_M8PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_M8PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_M8PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M8PR_Msk) >> MATRIX_PRBS_M8PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRBS_M9PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_M9PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M9PR(mask)) >> MATRIX_PRBS_M9PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_M9PR_bf(const void *const hw, hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M9PR_Msk; + tmp |= MATRIX_PRBS_M9PR(data); + ((MatrixPr *)hw)->MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_M9PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_M9PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_M9PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M9PR_Msk) >> MATRIX_PRBS_M9PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRBS_M10PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_M10PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M10PR(mask)) >> MATRIX_PRBS_M10PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_M10PR_bf(const void *const hw, hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M10PR_Msk; + tmp |= MATRIX_PRBS_M10PR(data); + ((MatrixPr *)hw)->MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_M10PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_M10PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_M10PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M10PR_Msk) >> MATRIX_PRBS_M10PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRBS_M11PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_M11PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M11PR(mask)) >> MATRIX_PRBS_M11PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_M11PR_bf(const void *const hw, hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M11PR_Msk; + tmp |= MATRIX_PRBS_M11PR(data); + ((MatrixPr *)hw)->MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_M11PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_M11PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_M11PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M11PR_Msk) >> MATRIX_PRBS_M11PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRBS_M12PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_M12PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M12PR(mask)) >> MATRIX_PRBS_M12PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_M12PR_bf(const void *const hw, hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M12PR_Msk; + tmp |= MATRIX_PRBS_M12PR(data); + ((MatrixPr *)hw)->MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_M12PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_M12PR_bf(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_M12PR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M12PR_Msk) >> MATRIX_PRBS_M12PR_Pos; + return tmp; +} + +static inline void hri_matrixpr_set_PRBS_reg(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_get_PRBS_reg(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((MatrixPr *)hw)->MATRIX_PRBS; + tmp &= mask; + return tmp; +} + +static inline void hri_matrixpr_write_PRBS_reg(const void *const hw, hri_matrix_prbs_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_clear_PRBS_reg(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrixpr_toggle_PRBS_reg(const void *const hw, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((MatrixPr *)hw)->MATRIX_PRBS ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrixpr_read_PRBS_reg(const void *const hw) +{ + return ((MatrixPr *)hw)->MATRIX_PRBS; +} + +static inline void hri_matrix_set_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M0PR(mask)) >> MATRIX_PRAS_M0PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M0PR_Msk; + tmp |= MATRIX_PRAS_M0PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M0PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M0PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M0PR_Msk) >> MATRIX_PRAS_M0PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M1PR(mask)) >> MATRIX_PRAS_M1PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M1PR_Msk; + tmp |= MATRIX_PRAS_M1PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M1PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M1PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M1PR_Msk) >> MATRIX_PRAS_M1PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M2PR(mask)) >> MATRIX_PRAS_M2PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M2PR_Msk; + tmp |= MATRIX_PRAS_M2PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M2PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M2PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M2PR_Msk) >> MATRIX_PRAS_M2PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M3PR(mask)) >> MATRIX_PRAS_M3PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M3PR_Msk; + tmp |= MATRIX_PRAS_M3PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M3PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M3PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M3PR_Msk) >> MATRIX_PRAS_M3PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M4PR(mask)) >> MATRIX_PRAS_M4PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M4PR_Msk; + tmp |= MATRIX_PRAS_M4PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M4PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M4PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M4PR_Msk) >> MATRIX_PRAS_M4PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M5PR(mask)) >> MATRIX_PRAS_M5PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M5PR_Msk; + tmp |= MATRIX_PRAS_M5PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M5PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M5PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M5PR_Msk) >> MATRIX_PRAS_M5PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M6PR(mask)) >> MATRIX_PRAS_M6PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= ~MATRIX_PRAS_M6PR_Msk; + tmp |= MATRIX_PRAS_M6PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= MATRIX_PRAS_M6PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_M6PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp = (tmp & MATRIX_PRAS_M6PR_Msk) >> MATRIX_PRAS_M6PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRAS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_matrix_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_PRAS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_pras_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_pras_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_pras_reg_t hri_matrix_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRAS; +} + +static inline void hri_matrix_set_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M8PR(mask)) >> MATRIX_PRBS_M8PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M8PR_Msk; + tmp |= MATRIX_PRBS_M8PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= MATRIX_PRBS_M8PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_M8PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M8PR_Msk) >> MATRIX_PRBS_M8PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M9PR(mask)) >> MATRIX_PRBS_M9PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M9PR_Msk; + tmp |= MATRIX_PRBS_M9PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= MATRIX_PRBS_M9PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_M9PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M9PR_Msk) >> MATRIX_PRBS_M9PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M10PR(mask)) >> MATRIX_PRBS_M10PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M10PR_Msk; + tmp |= MATRIX_PRBS_M10PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= MATRIX_PRBS_M10PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_M10PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M10PR_Msk) >> MATRIX_PRBS_M10PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M11PR(mask)) >> MATRIX_PRBS_M11PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M11PR_Msk; + tmp |= MATRIX_PRBS_M11PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= MATRIX_PRBS_M11PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_M11PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M11PR_Msk) >> MATRIX_PRBS_M11PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M12PR(mask)) >> MATRIX_PRBS_M12PR_Pos; + return tmp; +} + +static inline void hri_matrix_write_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= ~MATRIX_PRBS_M12PR_Msk; + tmp |= MATRIX_PRBS_M12PR(data); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= MATRIX_PRBS_M12PR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_M12PR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp = (tmp & MATRIX_PRBS_M12PR_Msk) >> MATRIX_PRBS_M12PR_Pos; + return tmp; +} + +static inline void hri_matrix_set_PRBS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_matrix_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_PRBS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_prbs_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, hri_matrix_prbs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_prbs_reg_t hri_matrix_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Matrix *)hw)->MatrixPr[submodule_index].MATRIX_PRBS; +} + +static inline bool hri_matrix_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Matrix *)hw)->MATRIX_WPSR & MATRIX_WPSR_WPVS) > 0; +} + +static inline hri_matrix_wpsr_reg_t hri_matrix_get_WPSR_WPVSRC_bf(const void *const hw, hri_matrix_wpsr_reg_t mask) +{ + return (((Matrix *)hw)->MATRIX_WPSR & MATRIX_WPSR_WPVSRC(mask)) >> MATRIX_WPSR_WPVSRC_Pos; +} + +static inline hri_matrix_wpsr_reg_t hri_matrix_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Matrix *)hw)->MATRIX_WPSR & MATRIX_WPSR_WPVSRC_Msk) >> MATRIX_WPSR_WPVSRC_Pos; +} + +static inline hri_matrix_wpsr_reg_t hri_matrix_get_WPSR_reg(const void *const hw, hri_matrix_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_matrix_wpsr_reg_t hri_matrix_read_WPSR_reg(const void *const hw) +{ + return ((Matrix *)hw)->MATRIX_WPSR; +} + +static inline void hri_matrix_set_MCFG_ULBT_bf(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] |= MATRIX_MCFG_ULBT(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mcfg_reg_t hri_matrix_get_MCFG_ULBT_bf(const void *const hw, uint8_t index, + hri_matrix_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MCFG[index]; + tmp = (tmp & MATRIX_MCFG_ULBT(mask)) >> MATRIX_MCFG_ULBT_Pos; + return tmp; +} + +static inline void hri_matrix_write_MCFG_ULBT_bf(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MCFG[index]; + tmp &= ~MATRIX_MCFG_ULBT_Msk; + tmp |= MATRIX_MCFG_ULBT(data); + ((Matrix *)hw)->MATRIX_MCFG[index] = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MCFG_ULBT_bf(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] &= ~MATRIX_MCFG_ULBT(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MCFG_ULBT_bf(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] ^= MATRIX_MCFG_ULBT(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mcfg_reg_t hri_matrix_read_MCFG_ULBT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MCFG[index]; + tmp = (tmp & MATRIX_MCFG_ULBT_Msk) >> MATRIX_MCFG_ULBT_Pos; + return tmp; +} + +static inline void hri_matrix_set_MCFG_reg(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mcfg_reg_t hri_matrix_get_MCFG_reg(const void *const hw, uint8_t index, + hri_matrix_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MCFG[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_MCFG_reg(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MCFG_reg(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MCFG_reg(const void *const hw, uint8_t index, hri_matrix_mcfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MCFG[index] ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mcfg_reg_t hri_matrix_read_MCFG_reg(const void *const hw, uint8_t index) +{ + return ((Matrix *)hw)->MATRIX_MCFG[index]; +} + +static inline void hri_matrix_set_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] |= MATRIX_SCFG_SLOT_CYCLE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_get_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_SLOT_CYCLE(mask)) >> MATRIX_SCFG_SLOT_CYCLE_Pos; + return tmp; +} + +static inline void hri_matrix_write_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp &= ~MATRIX_SCFG_SLOT_CYCLE_Msk; + tmp |= MATRIX_SCFG_SLOT_CYCLE(data); + ((Matrix *)hw)->MATRIX_SCFG[index] = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] &= ~MATRIX_SCFG_SLOT_CYCLE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] ^= MATRIX_SCFG_SLOT_CYCLE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_read_SCFG_SLOT_CYCLE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_SLOT_CYCLE_Msk) >> MATRIX_SCFG_SLOT_CYCLE_Pos; + return tmp; +} + +static inline void hri_matrix_set_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] |= MATRIX_SCFG_DEFMSTR_TYPE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_get_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_DEFMSTR_TYPE(mask)) >> MATRIX_SCFG_DEFMSTR_TYPE_Pos; + return tmp; +} + +static inline void hri_matrix_write_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp &= ~MATRIX_SCFG_DEFMSTR_TYPE_Msk; + tmp |= MATRIX_SCFG_DEFMSTR_TYPE(data); + ((Matrix *)hw)->MATRIX_SCFG[index] = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] &= ~MATRIX_SCFG_DEFMSTR_TYPE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] ^= MATRIX_SCFG_DEFMSTR_TYPE(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_read_SCFG_DEFMSTR_TYPE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_DEFMSTR_TYPE_Msk) >> MATRIX_SCFG_DEFMSTR_TYPE_Pos; + return tmp; +} + +static inline void hri_matrix_set_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] |= MATRIX_SCFG_FIXED_DEFMSTR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_get_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_FIXED_DEFMSTR(mask)) >> MATRIX_SCFG_FIXED_DEFMSTR_Pos; + return tmp; +} + +static inline void hri_matrix_write_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp &= ~MATRIX_SCFG_FIXED_DEFMSTR_Msk; + tmp |= MATRIX_SCFG_FIXED_DEFMSTR(data); + ((Matrix *)hw)->MATRIX_SCFG[index] = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] &= ~MATRIX_SCFG_FIXED_DEFMSTR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] ^= MATRIX_SCFG_FIXED_DEFMSTR(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_read_SCFG_FIXED_DEFMSTR_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp = (tmp & MATRIX_SCFG_FIXED_DEFMSTR_Msk) >> MATRIX_SCFG_FIXED_DEFMSTR_Pos; + return tmp; +} + +static inline void hri_matrix_set_SCFG_reg(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_get_SCFG_reg(const void *const hw, uint8_t index, + hri_matrix_scfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_SCFG[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_SCFG_reg(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_SCFG_reg(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_SCFG_reg(const void *const hw, uint8_t index, hri_matrix_scfg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_SCFG[index] ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_scfg_reg_t hri_matrix_read_SCFG_reg(const void *const hw, uint8_t index) +{ + return ((Matrix *)hw)->MATRIX_SCFG[index]; +} + +static inline void hri_matrix_set_MRCR_RCB0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB0) >> MATRIX_MRCR_RCB0_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB0; + tmp |= value << MATRIX_MRCR_RCB0_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB1) >> MATRIX_MRCR_RCB1_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB1; + tmp |= value << MATRIX_MRCR_RCB1_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB2) >> MATRIX_MRCR_RCB2_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB2; + tmp |= value << MATRIX_MRCR_RCB2_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB3) >> MATRIX_MRCR_RCB3_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB3; + tmp |= value << MATRIX_MRCR_RCB3_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB4) >> MATRIX_MRCR_RCB4_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB4; + tmp |= value << MATRIX_MRCR_RCB4_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB5) >> MATRIX_MRCR_RCB5_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB5; + tmp |= value << MATRIX_MRCR_RCB5_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB6) >> MATRIX_MRCR_RCB6_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB6; + tmp |= value << MATRIX_MRCR_RCB6_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB8_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB8; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB8) >> MATRIX_MRCR_RCB8_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB8; + tmp |= value << MATRIX_MRCR_RCB8_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB8_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB8; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB8_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB8; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB9_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB9; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB9) >> MATRIX_MRCR_RCB9_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB9; + tmp |= value << MATRIX_MRCR_RCB9_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB9_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB9; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB9_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB9; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB10_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB10; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB10) >> MATRIX_MRCR_RCB10_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB10; + tmp |= value << MATRIX_MRCR_RCB10_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB10_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB10; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB10_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB10; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB11_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB11; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB11) >> MATRIX_MRCR_RCB11_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB11; + tmp |= value << MATRIX_MRCR_RCB11_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB11_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB11; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB11_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB11; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_RCB12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= MATRIX_MRCR_RCB12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_MRCR_RCB12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp = (tmp & MATRIX_MRCR_RCB12) >> MATRIX_MRCR_RCB12_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_MRCR_RCB12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= ~MATRIX_MRCR_RCB12; + tmp |= value << MATRIX_MRCR_RCB12_Pos; + ((Matrix *)hw)->MATRIX_MRCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_RCB12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~MATRIX_MRCR_RCB12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_RCB12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= MATRIX_MRCR_RCB12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_MRCR_reg(const void *const hw, hri_matrix_mrcr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mrcr_reg_t hri_matrix_get_MRCR_reg(const void *const hw, hri_matrix_mrcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_MRCR; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_MRCR_reg(const void *const hw, hri_matrix_mrcr_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_MRCR_reg(const void *const hw, hri_matrix_mrcr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_MRCR_reg(const void *const hw, hri_matrix_mrcr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_MRCR ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_mrcr_reg_t hri_matrix_read_MRCR_reg(const void *const hw) +{ + return ((Matrix *)hw)->MATRIX_MRCR; +} + +static inline void hri_matrix_set_CCFG_CAN0_CAN0DMABA_bf(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 |= CCFG_CAN0_CAN0DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_can0_reg_t hri_matrix_get_CCFG_CAN0_CAN0DMABA_bf(const void *const hw, + hri_matrix_ccfg_can0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_CAN0; + tmp = (tmp & CCFG_CAN0_CAN0DMABA(mask)) >> CCFG_CAN0_CAN0DMABA_Pos; + return tmp; +} + +static inline void hri_matrix_write_CCFG_CAN0_CAN0DMABA_bf(const void *const hw, hri_matrix_ccfg_can0_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_CAN0; + tmp &= ~CCFG_CAN0_CAN0DMABA_Msk; + tmp |= CCFG_CAN0_CAN0DMABA(data); + ((Matrix *)hw)->CCFG_CAN0 = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_CAN0_CAN0DMABA_bf(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 &= ~CCFG_CAN0_CAN0DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_CAN0_CAN0DMABA_bf(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 ^= CCFG_CAN0_CAN0DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_can0_reg_t hri_matrix_read_CCFG_CAN0_CAN0DMABA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_CAN0; + tmp = (tmp & CCFG_CAN0_CAN0DMABA_Msk) >> CCFG_CAN0_CAN0DMABA_Pos; + return tmp; +} + +static inline void hri_matrix_set_CCFG_CAN0_reg(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_can0_reg_t hri_matrix_get_CCFG_CAN0_reg(const void *const hw, + hri_matrix_ccfg_can0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_CAN0; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_CCFG_CAN0_reg(const void *const hw, hri_matrix_ccfg_can0_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_CAN0_reg(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_CAN0_reg(const void *const hw, hri_matrix_ccfg_can0_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_CAN0 ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_can0_reg_t hri_matrix_read_CCFG_CAN0_reg(const void *const hw) +{ + return ((Matrix *)hw)->CCFG_CAN0; +} + +static inline void hri_matrix_set_CCFG_SYSIO_SYSIO4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SYSIO_SYSIO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_SYSIO4) >> CCFG_SYSIO_SYSIO4_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_SYSIO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_SYSIO4; + tmp |= value << CCFG_SYSIO_SYSIO4_Pos; + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_SYSIO4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_SYSIO4_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_SYSIO4; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SYSIO_SYSIO5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SYSIO_SYSIO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_SYSIO5) >> CCFG_SYSIO_SYSIO5_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_SYSIO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_SYSIO5; + tmp |= value << CCFG_SYSIO_SYSIO5_Pos; + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_SYSIO5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_SYSIO5_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_SYSIO5; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SYSIO_SYSIO6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_SYSIO6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SYSIO_SYSIO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_SYSIO6) >> CCFG_SYSIO_SYSIO6_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_SYSIO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_SYSIO6; + tmp |= value << CCFG_SYSIO_SYSIO6_Pos; + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_SYSIO6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_SYSIO6_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_SYSIO6; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SYSIO_SYSIO7_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_SYSIO7; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SYSIO_SYSIO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_SYSIO7) >> CCFG_SYSIO_SYSIO7_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_SYSIO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_SYSIO7; + tmp |= value << CCFG_SYSIO_SYSIO7_Pos; + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_SYSIO7_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO7; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_SYSIO7_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_SYSIO7; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SYSIO_SYSIO12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SYSIO_SYSIO12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_SYSIO12) >> CCFG_SYSIO_SYSIO12_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_SYSIO12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_SYSIO12; + tmp |= value << CCFG_SYSIO_SYSIO12_Pos; + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_SYSIO12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_SYSIO12_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_SYSIO12; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= CCFG_SYSIO_CAN1DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_sysio_reg_t hri_matrix_get_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw, + hri_matrix_ccfg_sysio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_CAN1DMABA(mask)) >> CCFG_SYSIO_CAN1DMABA_Pos; + return tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw, hri_matrix_ccfg_sysio_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= ~CCFG_SYSIO_CAN1DMABA_Msk; + tmp |= CCFG_SYSIO_CAN1DMABA(data); + ((Matrix *)hw)->CCFG_SYSIO = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~CCFG_SYSIO_CAN1DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= CCFG_SYSIO_CAN1DMABA(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_sysio_reg_t hri_matrix_read_CCFG_SYSIO_CAN1DMABA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp = (tmp & CCFG_SYSIO_CAN1DMABA_Msk) >> CCFG_SYSIO_CAN1DMABA_Pos; + return tmp; +} + +static inline void hri_matrix_set_CCFG_SYSIO_reg(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_sysio_reg_t hri_matrix_get_CCFG_SYSIO_reg(const void *const hw, + hri_matrix_ccfg_sysio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SYSIO; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_CCFG_SYSIO_reg(const void *const hw, hri_matrix_ccfg_sysio_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SYSIO_reg(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SYSIO_reg(const void *const hw, hri_matrix_ccfg_sysio_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SYSIO ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_sysio_reg_t hri_matrix_read_CCFG_SYSIO_reg(const void *const hw) +{ + return ((Matrix *)hw)->CCFG_SYSIO; +} + +static inline void hri_matrix_set_CCFG_PCCR_TC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR |= CCFG_PCCR_TC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_PCCR_TC0CC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp = (tmp & CCFG_PCCR_TC0CC) >> CCFG_PCCR_TC0CC_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_PCCR_TC0CC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp &= ~CCFG_PCCR_TC0CC; + tmp |= value << CCFG_PCCR_TC0CC_Pos; + ((Matrix *)hw)->CCFG_PCCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_PCCR_TC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR &= ~CCFG_PCCR_TC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_PCCR_TC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR ^= CCFG_PCCR_TC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_PCCR_I2SC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR |= CCFG_PCCR_I2SC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_PCCR_I2SC0CC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp = (tmp & CCFG_PCCR_I2SC0CC) >> CCFG_PCCR_I2SC0CC_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_PCCR_I2SC0CC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp &= ~CCFG_PCCR_I2SC0CC; + tmp |= value << CCFG_PCCR_I2SC0CC_Pos; + ((Matrix *)hw)->CCFG_PCCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_PCCR_I2SC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR &= ~CCFG_PCCR_I2SC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_PCCR_I2SC0CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR ^= CCFG_PCCR_I2SC0CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_PCCR_I2SC1CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR |= CCFG_PCCR_I2SC1CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_PCCR_I2SC1CC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp = (tmp & CCFG_PCCR_I2SC1CC) >> CCFG_PCCR_I2SC1CC_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_PCCR_I2SC1CC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp &= ~CCFG_PCCR_I2SC1CC; + tmp |= value << CCFG_PCCR_I2SC1CC_Pos; + ((Matrix *)hw)->CCFG_PCCR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_PCCR_I2SC1CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR &= ~CCFG_PCCR_I2SC1CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_PCCR_I2SC1CC_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR ^= CCFG_PCCR_I2SC1CC; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_PCCR_reg(const void *const hw, hri_matrix_ccfg_pccr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_pccr_reg_t hri_matrix_get_CCFG_PCCR_reg(const void *const hw, + hri_matrix_ccfg_pccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_PCCR; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_CCFG_PCCR_reg(const void *const hw, hri_matrix_ccfg_pccr_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_PCCR_reg(const void *const hw, hri_matrix_ccfg_pccr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_PCCR_reg(const void *const hw, hri_matrix_ccfg_pccr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_PCCR ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_pccr_reg_t hri_matrix_read_CCFG_PCCR_reg(const void *const hw) +{ + return ((Matrix *)hw)->CCFG_PCCR; +} + +static inline void hri_matrix_set_CCFG_DYNCKG_MATCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG |= CCFG_DYNCKG_MATCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_DYNCKG_MATCKG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp = (tmp & CCFG_DYNCKG_MATCKG) >> CCFG_DYNCKG_MATCKG_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_DYNCKG_MATCKG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp &= ~CCFG_DYNCKG_MATCKG; + tmp |= value << CCFG_DYNCKG_MATCKG_Pos; + ((Matrix *)hw)->CCFG_DYNCKG = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_DYNCKG_MATCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG &= ~CCFG_DYNCKG_MATCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_DYNCKG_MATCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG ^= CCFG_DYNCKG_MATCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_DYNCKG_BRIDCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG |= CCFG_DYNCKG_BRIDCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_DYNCKG_BRIDCKG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp = (tmp & CCFG_DYNCKG_BRIDCKG) >> CCFG_DYNCKG_BRIDCKG_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_DYNCKG_BRIDCKG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp &= ~CCFG_DYNCKG_BRIDCKG; + tmp |= value << CCFG_DYNCKG_BRIDCKG_Pos; + ((Matrix *)hw)->CCFG_DYNCKG = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_DYNCKG_BRIDCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG &= ~CCFG_DYNCKG_BRIDCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_DYNCKG_BRIDCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG ^= CCFG_DYNCKG_BRIDCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_DYNCKG_EFCCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG |= CCFG_DYNCKG_EFCCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_DYNCKG_EFCCKG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp = (tmp & CCFG_DYNCKG_EFCCKG) >> CCFG_DYNCKG_EFCCKG_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_DYNCKG_EFCCKG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp &= ~CCFG_DYNCKG_EFCCKG; + tmp |= value << CCFG_DYNCKG_EFCCKG_Pos; + ((Matrix *)hw)->CCFG_DYNCKG = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_DYNCKG_EFCCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG &= ~CCFG_DYNCKG_EFCCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_DYNCKG_EFCCKG_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG ^= CCFG_DYNCKG_EFCCKG; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_DYNCKG_reg(const void *const hw, hri_matrix_ccfg_dynckg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_dynckg_reg_t hri_matrix_get_CCFG_DYNCKG_reg(const void *const hw, + hri_matrix_ccfg_dynckg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_DYNCKG; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_CCFG_DYNCKG_reg(const void *const hw, hri_matrix_ccfg_dynckg_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_DYNCKG_reg(const void *const hw, hri_matrix_ccfg_dynckg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_DYNCKG_reg(const void *const hw, hri_matrix_ccfg_dynckg_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_DYNCKG ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_dynckg_reg_t hri_matrix_read_CCFG_DYNCKG_reg(const void *const hw) +{ + return ((Matrix *)hw)->CCFG_DYNCKG; +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_SMC_NFCS0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= CCFG_SMCNFCS_SMC_NFCS0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SMCNFCS_SMC_NFCS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp = (tmp & CCFG_SMCNFCS_SMC_NFCS0) >> CCFG_SMCNFCS_SMC_NFCS0_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_SMC_NFCS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= ~CCFG_SMCNFCS_SMC_NFCS0; + tmp |= value << CCFG_SMCNFCS_SMC_NFCS0_Pos; + ((Matrix *)hw)->CCFG_SMCNFCS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_SMC_NFCS0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~CCFG_SMCNFCS_SMC_NFCS0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_SMC_NFCS0_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= CCFG_SMCNFCS_SMC_NFCS0; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_SMC_NFCS1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= CCFG_SMCNFCS_SMC_NFCS1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SMCNFCS_SMC_NFCS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp = (tmp & CCFG_SMCNFCS_SMC_NFCS1) >> CCFG_SMCNFCS_SMC_NFCS1_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_SMC_NFCS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= ~CCFG_SMCNFCS_SMC_NFCS1; + tmp |= value << CCFG_SMCNFCS_SMC_NFCS1_Pos; + ((Matrix *)hw)->CCFG_SMCNFCS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_SMC_NFCS1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~CCFG_SMCNFCS_SMC_NFCS1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_SMC_NFCS1_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= CCFG_SMCNFCS_SMC_NFCS1; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_SMC_NFCS2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= CCFG_SMCNFCS_SMC_NFCS2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SMCNFCS_SMC_NFCS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp = (tmp & CCFG_SMCNFCS_SMC_NFCS2) >> CCFG_SMCNFCS_SMC_NFCS2_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_SMC_NFCS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= ~CCFG_SMCNFCS_SMC_NFCS2; + tmp |= value << CCFG_SMCNFCS_SMC_NFCS2_Pos; + ((Matrix *)hw)->CCFG_SMCNFCS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_SMC_NFCS2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~CCFG_SMCNFCS_SMC_NFCS2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_SMC_NFCS2_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= CCFG_SMCNFCS_SMC_NFCS2; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_SMC_NFCS3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= CCFG_SMCNFCS_SMC_NFCS3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SMCNFCS_SMC_NFCS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp = (tmp & CCFG_SMCNFCS_SMC_NFCS3) >> CCFG_SMCNFCS_SMC_NFCS3_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_SMC_NFCS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= ~CCFG_SMCNFCS_SMC_NFCS3; + tmp |= value << CCFG_SMCNFCS_SMC_NFCS3_Pos; + ((Matrix *)hw)->CCFG_SMCNFCS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_SMC_NFCS3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~CCFG_SMCNFCS_SMC_NFCS3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_SMC_NFCS3_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= CCFG_SMCNFCS_SMC_NFCS3; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_SDRAMEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= CCFG_SMCNFCS_SDRAMEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_CCFG_SMCNFCS_SDRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp = (tmp & CCFG_SMCNFCS_SDRAMEN) >> CCFG_SMCNFCS_SDRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_SDRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= ~CCFG_SMCNFCS_SDRAMEN; + tmp |= value << CCFG_SMCNFCS_SDRAMEN_Pos; + ((Matrix *)hw)->CCFG_SMCNFCS = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_SDRAMEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~CCFG_SMCNFCS_SDRAMEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_SDRAMEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= CCFG_SMCNFCS_SDRAMEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_CCFG_SMCNFCS_reg(const void *const hw, hri_matrix_ccfg_smcnfcs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_smcnfcs_reg_t hri_matrix_get_CCFG_SMCNFCS_reg(const void *const hw, + hri_matrix_ccfg_smcnfcs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->CCFG_SMCNFCS; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_CCFG_SMCNFCS_reg(const void *const hw, hri_matrix_ccfg_smcnfcs_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_CCFG_SMCNFCS_reg(const void *const hw, hri_matrix_ccfg_smcnfcs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_CCFG_SMCNFCS_reg(const void *const hw, hri_matrix_ccfg_smcnfcs_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->CCFG_SMCNFCS ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_ccfg_smcnfcs_reg_t hri_matrix_read_CCFG_SMCNFCS_reg(const void *const hw) +{ + return ((Matrix *)hw)->CCFG_SMCNFCS; +} + +static inline void hri_matrix_set_WPMR_WPEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR |= MATRIX_WPMR_WPEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_matrix_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp = (tmp & MATRIX_WPMR_WPEN) >> MATRIX_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_matrix_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp &= ~MATRIX_WPMR_WPEN; + tmp |= value << MATRIX_WPMR_WPEN_Pos; + ((Matrix *)hw)->MATRIX_WPMR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_WPMR_WPEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR &= ~MATRIX_WPMR_WPEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_WPMR_WPEN_bit(const void *const hw) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR ^= MATRIX_WPMR_WPEN; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_set_WPMR_WPKEY_bf(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR |= MATRIX_WPMR_WPKEY(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_wpmr_reg_t hri_matrix_get_WPMR_WPKEY_bf(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp = (tmp & MATRIX_WPMR_WPKEY(mask)) >> MATRIX_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_matrix_write_WPMR_WPKEY_bf(const void *const hw, hri_matrix_wpmr_reg_t data) +{ + uint32_t tmp; + MATRIX_CRITICAL_SECTION_ENTER(); + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp &= ~MATRIX_WPMR_WPKEY_Msk; + tmp |= MATRIX_WPMR_WPKEY(data); + ((Matrix *)hw)->MATRIX_WPMR = tmp; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_WPMR_WPKEY_bf(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR &= ~MATRIX_WPMR_WPKEY(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_WPMR_WPKEY_bf(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR ^= MATRIX_WPMR_WPKEY(mask); + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_wpmr_reg_t hri_matrix_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp = (tmp & MATRIX_WPMR_WPKEY_Msk) >> MATRIX_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_matrix_set_WPMR_reg(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR |= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_wpmr_reg_t hri_matrix_get_WPMR_reg(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Matrix *)hw)->MATRIX_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_matrix_write_WPMR_reg(const void *const hw, hri_matrix_wpmr_reg_t data) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR = data; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_clear_WPMR_reg(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR &= ~mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_matrix_toggle_WPMR_reg(const void *const hw, hri_matrix_wpmr_reg_t mask) +{ + MATRIX_CRITICAL_SECTION_ENTER(); + ((Matrix *)hw)->MATRIX_WPMR ^= mask; + MATRIX_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_matrix_wpmr_reg_t hri_matrix_read_WPMR_reg(const void *const hw) +{ + return ((Matrix *)hw)->MATRIX_WPMR; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MATRIX_E70B_H_INCLUDED */ +#endif /* _SAME70_MATRIX_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_mcan_e70b.h b/bsp/microchip/same70/bsp/hri/hri_mcan_e70b.h new file mode 100644 index 0000000000..a470862e2a --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_mcan_e70b.h @@ -0,0 +1,16853 @@ +/** + * \file + * + * \brief SAM MCAN + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_MCAN_COMPONENT_ +#ifndef _HRI_MCAN_E70B_H_INCLUDED_ +#define _HRI_MCAN_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCAN_CRITICAL_SECTIONS) +#define MCAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCAN_CRITICAL_SECTION_ENTER() +#define MCAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mcan_cccr_reg_t; +typedef uint32_t hri_mcan_crel_reg_t; +typedef uint32_t hri_mcan_cust_reg_t; +typedef uint32_t hri_mcan_dbtp_reg_t; +typedef uint32_t hri_mcan_ecr_reg_t; +typedef uint32_t hri_mcan_endn_reg_t; +typedef uint32_t hri_mcan_gfc_reg_t; +typedef uint32_t hri_mcan_hpms_reg_t; +typedef uint32_t hri_mcan_ie_reg_t; +typedef uint32_t hri_mcan_ile_reg_t; +typedef uint32_t hri_mcan_ils_reg_t; +typedef uint32_t hri_mcan_ir_reg_t; +typedef uint32_t hri_mcan_nbtp_reg_t; +typedef uint32_t hri_mcan_ndat1_reg_t; +typedef uint32_t hri_mcan_ndat2_reg_t; +typedef uint32_t hri_mcan_psr_reg_t; +typedef uint32_t hri_mcan_rwd_reg_t; +typedef uint32_t hri_mcan_rxbc_reg_t; +typedef uint32_t hri_mcan_rxesc_reg_t; +typedef uint32_t hri_mcan_rxf0a_reg_t; +typedef uint32_t hri_mcan_rxf0c_reg_t; +typedef uint32_t hri_mcan_rxf0s_reg_t; +typedef uint32_t hri_mcan_rxf1a_reg_t; +typedef uint32_t hri_mcan_rxf1c_reg_t; +typedef uint32_t hri_mcan_rxf1s_reg_t; +typedef uint32_t hri_mcan_sidfc_reg_t; +typedef uint32_t hri_mcan_tdcr_reg_t; +typedef uint32_t hri_mcan_test_reg_t; +typedef uint32_t hri_mcan_tocc_reg_t; +typedef uint32_t hri_mcan_tocv_reg_t; +typedef uint32_t hri_mcan_tscc_reg_t; +typedef uint32_t hri_mcan_tscv_reg_t; +typedef uint32_t hri_mcan_txbar_reg_t; +typedef uint32_t hri_mcan_txbc_reg_t; +typedef uint32_t hri_mcan_txbcf_reg_t; +typedef uint32_t hri_mcan_txbcie_reg_t; +typedef uint32_t hri_mcan_txbcr_reg_t; +typedef uint32_t hri_mcan_txbrp_reg_t; +typedef uint32_t hri_mcan_txbtie_reg_t; +typedef uint32_t hri_mcan_txbto_reg_t; +typedef uint32_t hri_mcan_txefa_reg_t; +typedef uint32_t hri_mcan_txefc_reg_t; +typedef uint32_t hri_mcan_txefs_reg_t; +typedef uint32_t hri_mcan_txesc_reg_t; +typedef uint32_t hri_mcan_txfqs_reg_t; +typedef uint32_t hri_mcan_xidam_reg_t; +typedef uint32_t hri_mcan_xidfc_reg_t; + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_DAY_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_DAY(mask)) >> MCAN_CREL_DAY_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_DAY_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_DAY_Msk) >> MCAN_CREL_DAY_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_MON_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_MON(mask)) >> MCAN_CREL_MON_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_MON_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_MON_Msk) >> MCAN_CREL_MON_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_YEAR_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_YEAR(mask)) >> MCAN_CREL_YEAR_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_YEAR_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_YEAR_Msk) >> MCAN_CREL_YEAR_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_SUBSTEP_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_SUBSTEP(mask)) >> MCAN_CREL_SUBSTEP_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_SUBSTEP_Msk) >> MCAN_CREL_SUBSTEP_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_STEP_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_STEP(mask)) >> MCAN_CREL_STEP_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_STEP_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_STEP_Msk) >> MCAN_CREL_STEP_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_REL_bf(const void *const hw, hri_mcan_crel_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_REL(mask)) >> MCAN_CREL_REL_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_REL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_CREL & MCAN_CREL_REL_Msk) >> MCAN_CREL_REL_Pos; +} + +static inline hri_mcan_crel_reg_t hri_mcan_get_CREL_reg(const void *const hw, hri_mcan_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CREL; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_crel_reg_t hri_mcan_read_CREL_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_CREL; +} + +static inline hri_mcan_endn_reg_t hri_mcan_get_ENDN_ETV_bf(const void *const hw, hri_mcan_endn_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_ENDN & MCAN_ENDN_ETV(mask)) >> MCAN_ENDN_ETV_Pos; +} + +static inline hri_mcan_endn_reg_t hri_mcan_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_ENDN & MCAN_ENDN_ETV_Msk) >> MCAN_ENDN_ETV_Pos; +} + +static inline hri_mcan_endn_reg_t hri_mcan_get_ENDN_reg(const void *const hw, hri_mcan_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ENDN; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_endn_reg_t hri_mcan_read_ENDN_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_ENDN; +} + +static inline bool hri_mcan_get_ECR_RP_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_RP) > 0; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_get_ECR_TEC_bf(const void *const hw, hri_mcan_ecr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_TEC(mask)) >> MCAN_ECR_TEC_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_read_ECR_TEC_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_TEC_Msk) >> MCAN_ECR_TEC_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_get_ECR_REC_bf(const void *const hw, hri_mcan_ecr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_REC(mask)) >> MCAN_ECR_REC_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_read_ECR_REC_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_REC_Msk) >> MCAN_ECR_REC_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_get_ECR_CEL_bf(const void *const hw, hri_mcan_ecr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_CEL(mask)) >> MCAN_ECR_CEL_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_read_ECR_CEL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_ECR & MCAN_ECR_CEL_Msk) >> MCAN_ECR_CEL_Pos; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_get_ECR_reg(const void *const hw, hri_mcan_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ECR; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_ecr_reg_t hri_mcan_read_ECR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_ECR; +} + +static inline bool hri_mcan_get_PSR_EP_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_EP) > 0; +} + +static inline bool hri_mcan_get_PSR_EW_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_EW) > 0; +} + +static inline bool hri_mcan_get_PSR_BO_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_BO) > 0; +} + +static inline bool hri_mcan_get_PSR_RESI_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_RESI) > 0; +} + +static inline bool hri_mcan_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_RBRS) > 0; +} + +static inline bool hri_mcan_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_RFDF) > 0; +} + +static inline bool hri_mcan_get_PSR_PXE_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_PXE) > 0; +} + +static inline hri_mcan_psr_reg_t hri_mcan_get_PSR_LEC_bf(const void *const hw, hri_mcan_psr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_LEC(mask)) >> MCAN_PSR_LEC_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_read_PSR_LEC_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_LEC_Msk) >> MCAN_PSR_LEC_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_get_PSR_ACT_bf(const void *const hw, hri_mcan_psr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_ACT(mask)) >> MCAN_PSR_ACT_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_read_PSR_ACT_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_ACT_Msk) >> MCAN_PSR_ACT_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_get_PSR_DLEC_bf(const void *const hw, hri_mcan_psr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_DLEC(mask)) >> MCAN_PSR_DLEC_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_DLEC_Msk) >> MCAN_PSR_DLEC_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_get_PSR_TDCV_bf(const void *const hw, hri_mcan_psr_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_TDCV(mask)) >> MCAN_PSR_TDCV_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_PSR & MCAN_PSR_TDCV_Msk) >> MCAN_PSR_TDCV_Pos; +} + +static inline hri_mcan_psr_reg_t hri_mcan_get_PSR_reg(const void *const hw, hri_mcan_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_PSR; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_psr_reg_t hri_mcan_read_PSR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_PSR; +} + +static inline bool hri_mcan_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_FLST) > 0; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_get_HPMS_BIDX_bf(const void *const hw, hri_mcan_hpms_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_BIDX(mask)) >> MCAN_HPMS_BIDX_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_BIDX_Msk) >> MCAN_HPMS_BIDX_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_get_HPMS_MSI_bf(const void *const hw, hri_mcan_hpms_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_MSI(mask)) >> MCAN_HPMS_MSI_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_MSI_Msk) >> MCAN_HPMS_MSI_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_get_HPMS_FIDX_bf(const void *const hw, hri_mcan_hpms_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_FIDX(mask)) >> MCAN_HPMS_FIDX_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_HPMS & MCAN_HPMS_FIDX_Msk) >> MCAN_HPMS_FIDX_Pos; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_get_HPMS_reg(const void *const hw, hri_mcan_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_HPMS; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_hpms_reg_t hri_mcan_read_HPMS_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_HPMS; +} + +static inline bool hri_mcan_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0F) > 0; +} + +static inline bool hri_mcan_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_RF0L) > 0; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_get_RXF0S_F0FL_bf(const void *const hw, hri_mcan_rxf0s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0FL(mask)) >> MCAN_RXF0S_F0FL_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0FL_Msk) >> MCAN_RXF0S_F0FL_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_get_RXF0S_F0GI_bf(const void *const hw, hri_mcan_rxf0s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0GI(mask)) >> MCAN_RXF0S_F0GI_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0GI_Msk) >> MCAN_RXF0S_F0GI_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_get_RXF0S_F0PI_bf(const void *const hw, hri_mcan_rxf0s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0PI(mask)) >> MCAN_RXF0S_F0PI_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF0S & MCAN_RXF0S_F0PI_Msk) >> MCAN_RXF0S_F0PI_Pos; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_get_RXF0S_reg(const void *const hw, hri_mcan_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0S; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_rxf0s_reg_t hri_mcan_read_RXF0S_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF0S; +} + +static inline bool hri_mcan_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1F) > 0; +} + +static inline bool hri_mcan_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_RF1L) > 0; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_get_RXF1S_F1FL_bf(const void *const hw, hri_mcan_rxf1s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1FL(mask)) >> MCAN_RXF1S_F1FL_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1FL_Msk) >> MCAN_RXF1S_F1FL_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_get_RXF1S_F1GI_bf(const void *const hw, hri_mcan_rxf1s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1GI(mask)) >> MCAN_RXF1S_F1GI_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1GI_Msk) >> MCAN_RXF1S_F1GI_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_get_RXF1S_F1PI_bf(const void *const hw, hri_mcan_rxf1s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1PI(mask)) >> MCAN_RXF1S_F1PI_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_F1PI_Msk) >> MCAN_RXF1S_F1PI_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_get_RXF1S_DMS_bf(const void *const hw, hri_mcan_rxf1s_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_DMS(mask)) >> MCAN_RXF1S_DMS_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_RXF1S & MCAN_RXF1S_DMS_Msk) >> MCAN_RXF1S_DMS_Pos; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_get_RXF1S_reg(const void *const hw, hri_mcan_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1S; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_rxf1s_reg_t hri_mcan_read_RXF1S_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF1S; +} + +static inline bool hri_mcan_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFQF) > 0; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_get_TXFQS_TFFL_bf(const void *const hw, hri_mcan_txfqs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFFL(mask)) >> MCAN_TXFQS_TFFL_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFFL_Msk) >> MCAN_TXFQS_TFFL_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_get_TXFQS_TFGI_bf(const void *const hw, hri_mcan_txfqs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFGI(mask)) >> MCAN_TXFQS_TFGI_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFGI_Msk) >> MCAN_TXFQS_TFGI_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_get_TXFQS_TFQPI_bf(const void *const hw, hri_mcan_txfqs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFQPI(mask)) >> MCAN_TXFQS_TFQPI_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXFQS & MCAN_TXFQS_TFQPI_Msk) >> MCAN_TXFQS_TFQPI_Pos; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_get_TXFQS_reg(const void *const hw, hri_mcan_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXFQS; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_txfqs_reg_t hri_mcan_read_TXFQS_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXFQS; +} + +static inline bool hri_mcan_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP0) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP1) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP2) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP3) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP4) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP5) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP6) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP7) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP8) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP9) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP10) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP11) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP12) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP13) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP14) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP15) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP16) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP17) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP18) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP19) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP20) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP21) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP22) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP23) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP24) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP25) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP26) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP27) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP28) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP29) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP30) > 0; +} + +static inline bool hri_mcan_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBRP & MCAN_TXBRP_TRP31) > 0; +} + +static inline hri_mcan_txbrp_reg_t hri_mcan_get_TXBRP_reg(const void *const hw, hri_mcan_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBRP; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_txbrp_reg_t hri_mcan_read_TXBRP_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBRP; +} + +static inline bool hri_mcan_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO0) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO1) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO2) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO3) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO4) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO5) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO6) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO7) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO8) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO9) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO10) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO11) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO12) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO13) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO14) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO15) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO16) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO17) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO18) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO19) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO20) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO21) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO22) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO23) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO24) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO25) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO26) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO27) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO28) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO29) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO30) > 0; +} + +static inline bool hri_mcan_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBTO & MCAN_TXBTO_TO31) > 0; +} + +static inline hri_mcan_txbto_reg_t hri_mcan_get_TXBTO_reg(const void *const hw, hri_mcan_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTO; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_txbto_reg_t hri_mcan_read_TXBTO_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBTO; +} + +static inline bool hri_mcan_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF0) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF1) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF2) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF3) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF4) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF5) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF6) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF7) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF8) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF9) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF10) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF11) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF12) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF13) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF14) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF15) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF16) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF17) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF18) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF19) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF20) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF21) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF22) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF23) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF24) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF25) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF26) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF27) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF28) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF29) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF30) > 0; +} + +static inline bool hri_mcan_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXBCF & MCAN_TXBCF_CF31) > 0; +} + +static inline hri_mcan_txbcf_reg_t hri_mcan_get_TXBCF_reg(const void *const hw, hri_mcan_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCF; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_txbcf_reg_t hri_mcan_read_TXBCF_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBCF; +} + +static inline bool hri_mcan_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFF) > 0; +} + +static inline bool hri_mcan_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_TEFL) > 0; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_get_TXEFS_EFFL_bf(const void *const hw, hri_mcan_txefs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFFL(mask)) >> MCAN_TXEFS_EFFL_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFFL_Msk) >> MCAN_TXEFS_EFFL_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_get_TXEFS_EFGI_bf(const void *const hw, hri_mcan_txefs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFGI(mask)) >> MCAN_TXEFS_EFGI_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFGI_Msk) >> MCAN_TXEFS_EFGI_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_get_TXEFS_EFPI_bf(const void *const hw, hri_mcan_txefs_reg_t mask) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFPI(mask)) >> MCAN_TXEFS_EFPI_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Mcan *)hw)->MCAN_TXEFS & MCAN_TXEFS_EFPI_Msk) >> MCAN_TXEFS_EFPI_Pos; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_get_TXEFS_reg(const void *const hw, hri_mcan_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFS; + tmp &= mask; + return tmp; +} + +static inline hri_mcan_txefs_reg_t hri_mcan_read_TXEFS_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXEFS; +} + +static inline void hri_mcan_set_CUST_CSV_bf(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST |= MCAN_CUST_CSV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cust_reg_t hri_mcan_get_CUST_CSV_bf(const void *const hw, hri_mcan_cust_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CUST; + tmp = (tmp & MCAN_CUST_CSV(mask)) >> MCAN_CUST_CSV_Pos; + return tmp; +} + +static inline void hri_mcan_write_CUST_CSV_bf(const void *const hw, hri_mcan_cust_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CUST; + tmp &= ~MCAN_CUST_CSV_Msk; + tmp |= MCAN_CUST_CSV(data); + ((Mcan *)hw)->MCAN_CUST = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CUST_CSV_bf(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST &= ~MCAN_CUST_CSV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CUST_CSV_bf(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST ^= MCAN_CUST_CSV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cust_reg_t hri_mcan_read_CUST_CSV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CUST; + tmp = (tmp & MCAN_CUST_CSV_Msk) >> MCAN_CUST_CSV_Pos; + return tmp; +} + +static inline void hri_mcan_set_CUST_reg(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cust_reg_t hri_mcan_get_CUST_reg(const void *const hw, hri_mcan_cust_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CUST; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_CUST_reg(const void *const hw, hri_mcan_cust_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CUST_reg(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CUST_reg(const void *const hw, hri_mcan_cust_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CUST ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cust_reg_t hri_mcan_read_CUST_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_CUST; +} + +static inline void hri_mcan_set_DBTP_TDC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= MCAN_DBTP_TDC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_TDC) >> MCAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= ~MCAN_DBTP_TDC; + tmp |= value << MCAN_DBTP_TDC_Pos; + ((Mcan *)hw)->MCAN_DBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_TDC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~MCAN_DBTP_TDC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_TDC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= MCAN_DBTP_TDC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_DBTP_DSJW_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= MCAN_DBTP_DSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_get_DBTP_DSJW_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DSJW(mask)) >> MCAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_mcan_write_DBTP_DSJW_bf(const void *const hw, hri_mcan_dbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= ~MCAN_DBTP_DSJW_Msk; + tmp |= MCAN_DBTP_DSJW(data); + ((Mcan *)hw)->MCAN_DBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_DSJW_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~MCAN_DBTP_DSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_DSJW_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= MCAN_DBTP_DSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DSJW_Msk) >> MCAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_mcan_set_DBTP_DTSEG2_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= MCAN_DBTP_DTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_get_DBTP_DTSEG2_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DTSEG2(mask)) >> MCAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_mcan_write_DBTP_DTSEG2_bf(const void *const hw, hri_mcan_dbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= ~MCAN_DBTP_DTSEG2_Msk; + tmp |= MCAN_DBTP_DTSEG2(data); + ((Mcan *)hw)->MCAN_DBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_DTSEG2_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~MCAN_DBTP_DTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= MCAN_DBTP_DTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DTSEG2_Msk) >> MCAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_mcan_set_DBTP_DTSEG1_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= MCAN_DBTP_DTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_get_DBTP_DTSEG1_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DTSEG1(mask)) >> MCAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_mcan_write_DBTP_DTSEG1_bf(const void *const hw, hri_mcan_dbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= ~MCAN_DBTP_DTSEG1_Msk; + tmp |= MCAN_DBTP_DTSEG1(data); + ((Mcan *)hw)->MCAN_DBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_DTSEG1_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~MCAN_DBTP_DTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= MCAN_DBTP_DTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DTSEG1_Msk) >> MCAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_mcan_set_DBTP_DBRP_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= MCAN_DBTP_DBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_get_DBTP_DBRP_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DBRP(mask)) >> MCAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_mcan_write_DBTP_DBRP_bf(const void *const hw, hri_mcan_dbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= ~MCAN_DBTP_DBRP_Msk; + tmp |= MCAN_DBTP_DBRP(data); + ((Mcan *)hw)->MCAN_DBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_DBRP_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~MCAN_DBTP_DBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_DBRP_bf(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= MCAN_DBTP_DBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp = (tmp & MCAN_DBTP_DBRP_Msk) >> MCAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_mcan_set_DBTP_reg(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_get_DBTP_reg(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_DBTP; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_DBTP_reg(const void *const hw, hri_mcan_dbtp_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_DBTP_reg(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_DBTP_reg(const void *const hw, hri_mcan_dbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_DBTP ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_dbtp_reg_t hri_mcan_read_DBTP_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_DBTP; +} + +static inline void hri_mcan_set_TEST_LBCK_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST |= MCAN_TEST_LBCK; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp = (tmp & MCAN_TEST_LBCK) >> MCAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp &= ~MCAN_TEST_LBCK; + tmp |= value << MCAN_TEST_LBCK_Pos; + ((Mcan *)hw)->MCAN_TEST = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TEST_LBCK_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST &= ~MCAN_TEST_LBCK; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TEST_LBCK_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST ^= MCAN_TEST_LBCK; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TEST_RX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST |= MCAN_TEST_RX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp = (tmp & MCAN_TEST_RX) >> MCAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp &= ~MCAN_TEST_RX; + tmp |= value << MCAN_TEST_RX_Pos; + ((Mcan *)hw)->MCAN_TEST = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TEST_RX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST &= ~MCAN_TEST_RX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TEST_RX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST ^= MCAN_TEST_RX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TEST_TX_bf(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST |= MCAN_TEST_TX(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_test_reg_t hri_mcan_get_TEST_TX_bf(const void *const hw, hri_mcan_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp = (tmp & MCAN_TEST_TX(mask)) >> MCAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_mcan_write_TEST_TX_bf(const void *const hw, hri_mcan_test_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp &= ~MCAN_TEST_TX_Msk; + tmp |= MCAN_TEST_TX(data); + ((Mcan *)hw)->MCAN_TEST = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TEST_TX_bf(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST &= ~MCAN_TEST_TX(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TEST_TX_bf(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST ^= MCAN_TEST_TX(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_test_reg_t hri_mcan_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp = (tmp & MCAN_TEST_TX_Msk) >> MCAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_mcan_set_TEST_reg(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_test_reg_t hri_mcan_get_TEST_reg(const void *const hw, hri_mcan_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TEST; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TEST_reg(const void *const hw, hri_mcan_test_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TEST_reg(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TEST_reg(const void *const hw, hri_mcan_test_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TEST ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_test_reg_t hri_mcan_read_TEST_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TEST; +} + +static inline void hri_mcan_set_RWD_WDC_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD |= MCAN_RWD_WDC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_get_RWD_WDC_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp = (tmp & MCAN_RWD_WDC(mask)) >> MCAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_mcan_write_RWD_WDC_bf(const void *const hw, hri_mcan_rwd_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp &= ~MCAN_RWD_WDC_Msk; + tmp |= MCAN_RWD_WDC(data); + ((Mcan *)hw)->MCAN_RWD = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RWD_WDC_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD &= ~MCAN_RWD_WDC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RWD_WDC_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD ^= MCAN_RWD_WDC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp = (tmp & MCAN_RWD_WDC_Msk) >> MCAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_mcan_set_RWD_WDV_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD |= MCAN_RWD_WDV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_get_RWD_WDV_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp = (tmp & MCAN_RWD_WDV(mask)) >> MCAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_mcan_write_RWD_WDV_bf(const void *const hw, hri_mcan_rwd_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp &= ~MCAN_RWD_WDV_Msk; + tmp |= MCAN_RWD_WDV(data); + ((Mcan *)hw)->MCAN_RWD = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RWD_WDV_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD &= ~MCAN_RWD_WDV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RWD_WDV_bf(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD ^= MCAN_RWD_WDV(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp = (tmp & MCAN_RWD_WDV_Msk) >> MCAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_mcan_set_RWD_reg(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_get_RWD_reg(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RWD; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RWD_reg(const void *const hw, hri_mcan_rwd_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RWD_reg(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RWD_reg(const void *const hw, hri_mcan_rwd_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RWD ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rwd_reg_t hri_mcan_read_RWD_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RWD; +} + +static inline void hri_mcan_set_CCCR_INIT_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_INIT; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_INIT) >> MCAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_INIT; + tmp |= value << MCAN_CCCR_INIT_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_INIT_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_INIT; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_INIT_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_INIT; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_CCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_CCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_CCE) >> MCAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_CCE; + tmp |= value << MCAN_CCCR_CCE_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_CCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_CCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_CCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_CCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_ASM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_ASM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_ASM) >> MCAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_ASM; + tmp |= value << MCAN_CCCR_ASM_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_ASM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_ASM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_ASM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_ASM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_CSA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_CSA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_CSA) >> MCAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_CSA; + tmp |= value << MCAN_CCCR_CSA_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_CSA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_CSA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_CSA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_CSA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_CSR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_CSR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_CSR) >> MCAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_CSR; + tmp |= value << MCAN_CCCR_CSR_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_CSR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_CSR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_CSR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_CSR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_MON_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_MON; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_MON) >> MCAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_MON; + tmp |= value << MCAN_CCCR_MON_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_MON_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_MON; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_MON_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_MON; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_DAR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_DAR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_DAR) >> MCAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_DAR; + tmp |= value << MCAN_CCCR_DAR_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_DAR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_DAR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_DAR_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_DAR; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_TEST_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_TEST; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_TEST) >> MCAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_TEST; + tmp |= value << MCAN_CCCR_TEST_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_TEST_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_TEST; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_TEST_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_TEST; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_FDOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_FDOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_FDOE) >> MCAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_FDOE; + tmp |= value << MCAN_CCCR_FDOE_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_FDOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_FDOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_FDOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_FDOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_BRSE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_BRSE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_BRSE) >> MCAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_BRSE; + tmp |= value << MCAN_CCCR_BRSE_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_BRSE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_BRSE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_BRSE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_BRSE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_PXHD_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_PXHD; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_PXHD) >> MCAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_PXHD; + tmp |= value << MCAN_CCCR_PXHD_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_PXHD_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_PXHD; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_PXHD_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_PXHD; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_EFBI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_EFBI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_EFBI) >> MCAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_EFBI; + tmp |= value << MCAN_CCCR_EFBI_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_EFBI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_EFBI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_EFBI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_EFBI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_TXP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_TXP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_TXP) >> MCAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_TXP; + tmp |= value << MCAN_CCCR_TXP_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_TXP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_TXP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_TXP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_TXP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_NISO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= MCAN_CCCR_NISO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp = (tmp & MCAN_CCCR_NISO) >> MCAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= ~MCAN_CCCR_NISO; + tmp |= value << MCAN_CCCR_NISO_Pos; + ((Mcan *)hw)->MCAN_CCCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_NISO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~MCAN_CCCR_NISO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_NISO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= MCAN_CCCR_NISO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_CCCR_reg(const void *const hw, hri_mcan_cccr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cccr_reg_t hri_mcan_get_CCCR_reg(const void *const hw, hri_mcan_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_CCCR; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_CCCR_reg(const void *const hw, hri_mcan_cccr_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_CCCR_reg(const void *const hw, hri_mcan_cccr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_CCCR_reg(const void *const hw, hri_mcan_cccr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_CCCR ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_cccr_reg_t hri_mcan_read_CCCR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_CCCR; +} + +static inline void hri_mcan_set_NBTP_NTSEG2_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP |= MCAN_NBTP_NTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_get_NBTP_NTSEG2_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NTSEG2(mask)) >> MCAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_mcan_write_NBTP_NTSEG2_bf(const void *const hw, hri_mcan_nbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp &= ~MCAN_NBTP_NTSEG2_Msk; + tmp |= MCAN_NBTP_NTSEG2(data); + ((Mcan *)hw)->MCAN_NBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NBTP_NTSEG2_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP &= ~MCAN_NBTP_NTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP ^= MCAN_NBTP_NTSEG2(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NTSEG2_Msk) >> MCAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_mcan_set_NBTP_NTSEG1_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP |= MCAN_NBTP_NTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_get_NBTP_NTSEG1_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NTSEG1(mask)) >> MCAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_mcan_write_NBTP_NTSEG1_bf(const void *const hw, hri_mcan_nbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp &= ~MCAN_NBTP_NTSEG1_Msk; + tmp |= MCAN_NBTP_NTSEG1(data); + ((Mcan *)hw)->MCAN_NBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NBTP_NTSEG1_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP &= ~MCAN_NBTP_NTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP ^= MCAN_NBTP_NTSEG1(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NTSEG1_Msk) >> MCAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_mcan_set_NBTP_NBRP_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP |= MCAN_NBTP_NBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_get_NBTP_NBRP_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NBRP(mask)) >> MCAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_mcan_write_NBTP_NBRP_bf(const void *const hw, hri_mcan_nbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp &= ~MCAN_NBTP_NBRP_Msk; + tmp |= MCAN_NBTP_NBRP(data); + ((Mcan *)hw)->MCAN_NBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NBTP_NBRP_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP &= ~MCAN_NBTP_NBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NBTP_NBRP_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP ^= MCAN_NBTP_NBRP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NBRP_Msk) >> MCAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_mcan_set_NBTP_NSJW_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP |= MCAN_NBTP_NSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_get_NBTP_NSJW_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NSJW(mask)) >> MCAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_mcan_write_NBTP_NSJW_bf(const void *const hw, hri_mcan_nbtp_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp &= ~MCAN_NBTP_NSJW_Msk; + tmp |= MCAN_NBTP_NSJW(data); + ((Mcan *)hw)->MCAN_NBTP = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NBTP_NSJW_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP &= ~MCAN_NBTP_NSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NBTP_NSJW_bf(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP ^= MCAN_NBTP_NSJW(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp = (tmp & MCAN_NBTP_NSJW_Msk) >> MCAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_mcan_set_NBTP_reg(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_get_NBTP_reg(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NBTP; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_NBTP_reg(const void *const hw, hri_mcan_nbtp_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NBTP_reg(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NBTP_reg(const void *const hw, hri_mcan_nbtp_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NBTP ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_nbtp_reg_t hri_mcan_read_NBTP_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_NBTP; +} + +static inline void hri_mcan_set_TSCC_TSS_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC |= MCAN_TSCC_TSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_get_TSCC_TSS_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp = (tmp & MCAN_TSCC_TSS(mask)) >> MCAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_mcan_write_TSCC_TSS_bf(const void *const hw, hri_mcan_tscc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp &= ~MCAN_TSCC_TSS_Msk; + tmp |= MCAN_TSCC_TSS(data); + ((Mcan *)hw)->MCAN_TSCC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TSCC_TSS_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC &= ~MCAN_TSCC_TSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TSCC_TSS_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC ^= MCAN_TSCC_TSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp = (tmp & MCAN_TSCC_TSS_Msk) >> MCAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_mcan_set_TSCC_TCP_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC |= MCAN_TSCC_TCP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_get_TSCC_TCP_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp = (tmp & MCAN_TSCC_TCP(mask)) >> MCAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_mcan_write_TSCC_TCP_bf(const void *const hw, hri_mcan_tscc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp &= ~MCAN_TSCC_TCP_Msk; + tmp |= MCAN_TSCC_TCP(data); + ((Mcan *)hw)->MCAN_TSCC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TSCC_TCP_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC &= ~MCAN_TSCC_TCP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TSCC_TCP_bf(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC ^= MCAN_TSCC_TCP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp = (tmp & MCAN_TSCC_TCP_Msk) >> MCAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_mcan_set_TSCC_reg(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_get_TSCC_reg(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TSCC_reg(const void *const hw, hri_mcan_tscc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TSCC_reg(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TSCC_reg(const void *const hw, hri_mcan_tscc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscc_reg_t hri_mcan_read_TSCC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TSCC; +} + +static inline void hri_mcan_set_TSCV_TSC_bf(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV |= MCAN_TSCV_TSC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscv_reg_t hri_mcan_get_TSCV_TSC_bf(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCV; + tmp = (tmp & MCAN_TSCV_TSC(mask)) >> MCAN_TSCV_TSC_Pos; + return tmp; +} + +static inline void hri_mcan_write_TSCV_TSC_bf(const void *const hw, hri_mcan_tscv_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TSCV; + tmp &= ~MCAN_TSCV_TSC_Msk; + tmp |= MCAN_TSCV_TSC(data); + ((Mcan *)hw)->MCAN_TSCV = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TSCV_TSC_bf(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV &= ~MCAN_TSCV_TSC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TSCV_TSC_bf(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV ^= MCAN_TSCV_TSC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscv_reg_t hri_mcan_read_TSCV_TSC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCV; + tmp = (tmp & MCAN_TSCV_TSC_Msk) >> MCAN_TSCV_TSC_Pos; + return tmp; +} + +static inline void hri_mcan_set_TSCV_reg(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscv_reg_t hri_mcan_get_TSCV_reg(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TSCV; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TSCV_reg(const void *const hw, hri_mcan_tscv_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TSCV_reg(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TSCV_reg(const void *const hw, hri_mcan_tscv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TSCV ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tscv_reg_t hri_mcan_read_TSCV_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TSCV; +} + +static inline void hri_mcan_set_TOCC_ETOC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC |= MCAN_TOCC_ETOC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp = (tmp & MCAN_TOCC_ETOC) >> MCAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp &= ~MCAN_TOCC_ETOC; + tmp |= value << MCAN_TOCC_ETOC_Pos; + ((Mcan *)hw)->MCAN_TOCC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCC_ETOC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC &= ~MCAN_TOCC_ETOC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCC_ETOC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC ^= MCAN_TOCC_ETOC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TOCC_TOS_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC |= MCAN_TOCC_TOS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_get_TOCC_TOS_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp = (tmp & MCAN_TOCC_TOS(mask)) >> MCAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_mcan_write_TOCC_TOS_bf(const void *const hw, hri_mcan_tocc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp &= ~MCAN_TOCC_TOS_Msk; + tmp |= MCAN_TOCC_TOS(data); + ((Mcan *)hw)->MCAN_TOCC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCC_TOS_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC &= ~MCAN_TOCC_TOS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCC_TOS_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC ^= MCAN_TOCC_TOS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp = (tmp & MCAN_TOCC_TOS_Msk) >> MCAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_mcan_set_TOCC_TOP_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC |= MCAN_TOCC_TOP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_get_TOCC_TOP_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp = (tmp & MCAN_TOCC_TOP(mask)) >> MCAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_mcan_write_TOCC_TOP_bf(const void *const hw, hri_mcan_tocc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp &= ~MCAN_TOCC_TOP_Msk; + tmp |= MCAN_TOCC_TOP(data); + ((Mcan *)hw)->MCAN_TOCC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCC_TOP_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC &= ~MCAN_TOCC_TOP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCC_TOP_bf(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC ^= MCAN_TOCC_TOP(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp = (tmp & MCAN_TOCC_TOP_Msk) >> MCAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_mcan_set_TOCC_reg(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_get_TOCC_reg(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TOCC_reg(const void *const hw, hri_mcan_tocc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCC_reg(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCC_reg(const void *const hw, hri_mcan_tocc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocc_reg_t hri_mcan_read_TOCC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TOCC; +} + +static inline void hri_mcan_set_TOCV_TOC_bf(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV |= MCAN_TOCV_TOC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocv_reg_t hri_mcan_get_TOCV_TOC_bf(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCV; + tmp = (tmp & MCAN_TOCV_TOC(mask)) >> MCAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_mcan_write_TOCV_TOC_bf(const void *const hw, hri_mcan_tocv_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TOCV; + tmp &= ~MCAN_TOCV_TOC_Msk; + tmp |= MCAN_TOCV_TOC(data); + ((Mcan *)hw)->MCAN_TOCV = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCV_TOC_bf(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV &= ~MCAN_TOCV_TOC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCV_TOC_bf(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV ^= MCAN_TOCV_TOC(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocv_reg_t hri_mcan_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCV; + tmp = (tmp & MCAN_TOCV_TOC_Msk) >> MCAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_mcan_set_TOCV_reg(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocv_reg_t hri_mcan_get_TOCV_reg(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TOCV; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TOCV_reg(const void *const hw, hri_mcan_tocv_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TOCV_reg(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TOCV_reg(const void *const hw, hri_mcan_tocv_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TOCV ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tocv_reg_t hri_mcan_read_TOCV_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TOCV; +} + +static inline void hri_mcan_set_TDCR_TDCF_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR |= MCAN_TDCR_TDCF(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_get_TDCR_TDCF_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp = (tmp & MCAN_TDCR_TDCF(mask)) >> MCAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_mcan_write_TDCR_TDCF_bf(const void *const hw, hri_mcan_tdcr_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp &= ~MCAN_TDCR_TDCF_Msk; + tmp |= MCAN_TDCR_TDCF(data); + ((Mcan *)hw)->MCAN_TDCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TDCR_TDCF_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR &= ~MCAN_TDCR_TDCF(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TDCR_TDCF_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR ^= MCAN_TDCR_TDCF(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp = (tmp & MCAN_TDCR_TDCF_Msk) >> MCAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_mcan_set_TDCR_TDCO_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR |= MCAN_TDCR_TDCO(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_get_TDCR_TDCO_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp = (tmp & MCAN_TDCR_TDCO(mask)) >> MCAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_mcan_write_TDCR_TDCO_bf(const void *const hw, hri_mcan_tdcr_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp &= ~MCAN_TDCR_TDCO_Msk; + tmp |= MCAN_TDCR_TDCO(data); + ((Mcan *)hw)->MCAN_TDCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TDCR_TDCO_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR &= ~MCAN_TDCR_TDCO(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TDCR_TDCO_bf(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR ^= MCAN_TDCR_TDCO(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp = (tmp & MCAN_TDCR_TDCO_Msk) >> MCAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_mcan_set_TDCR_reg(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_get_TDCR_reg(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TDCR; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TDCR_reg(const void *const hw, hri_mcan_tdcr_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TDCR_reg(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TDCR_reg(const void *const hw, hri_mcan_tdcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TDCR ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_tdcr_reg_t hri_mcan_read_TDCR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TDCR; +} + +static inline void hri_mcan_set_IR_RF0N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF0N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF0N) >> MCAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF0N; + tmp |= value << MCAN_IR_RF0N_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF0N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF0N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF0N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF0N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF0W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF0W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF0W) >> MCAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF0W; + tmp |= value << MCAN_IR_RF0W_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF0W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF0W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF0W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF0W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF0F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF0F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF0F) >> MCAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF0F; + tmp |= value << MCAN_IR_RF0F_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF0F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF0F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF0F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF0F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF0L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF0L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF0L) >> MCAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF0L; + tmp |= value << MCAN_IR_RF0L_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF0L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF0L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF0L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF0L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF1N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF1N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF1N) >> MCAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF1N; + tmp |= value << MCAN_IR_RF1N_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF1N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF1N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF1N_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF1N; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF1W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF1W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF1W) >> MCAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF1W; + tmp |= value << MCAN_IR_RF1W_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF1W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF1W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF1W_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF1W; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF1F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF1F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF1F) >> MCAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF1F; + tmp |= value << MCAN_IR_RF1F_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF1F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF1F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF1F_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF1F; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_RF1L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_RF1L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_RF1L) >> MCAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_RF1L; + tmp |= value << MCAN_IR_RF1L_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_RF1L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_RF1L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_RF1L_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_RF1L; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_HPM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_HPM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_HPM) >> MCAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_HPM; + tmp |= value << MCAN_IR_HPM_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_HPM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_HPM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_HPM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_HPM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TC) >> MCAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TC; + tmp |= value << MCAN_IR_TC_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TC_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TC; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TCF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TCF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TCF) >> MCAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TCF; + tmp |= value << MCAN_IR_TCF_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TCF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TCF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TCF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TCF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TFE) >> MCAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TFE; + tmp |= value << MCAN_IR_TFE_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TEFN_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TEFN; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TEFN) >> MCAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TEFN; + tmp |= value << MCAN_IR_TEFN_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TEFN_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TEFN; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TEFN_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TEFN; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TEFW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TEFW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TEFW) >> MCAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TEFW; + tmp |= value << MCAN_IR_TEFW_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TEFW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TEFW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TEFW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TEFW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TEFF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TEFF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TEFF) >> MCAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TEFF; + tmp |= value << MCAN_IR_TEFF_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TEFF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TEFF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TEFF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TEFF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TEFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TEFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TEFL) >> MCAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TEFL; + tmp |= value << MCAN_IR_TEFL_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TEFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TEFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TEFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TEFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TSW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TSW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TSW) >> MCAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TSW; + tmp |= value << MCAN_IR_TSW_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TSW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TSW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TSW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TSW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_MRAF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_MRAF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_MRAF) >> MCAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_MRAF; + tmp |= value << MCAN_IR_MRAF_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_MRAF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_MRAF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_MRAF_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_MRAF; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_TOO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_TOO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_TOO) >> MCAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_TOO; + tmp |= value << MCAN_IR_TOO_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_TOO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_TOO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_TOO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_TOO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_DRX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_DRX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_DRX) >> MCAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_DRX; + tmp |= value << MCAN_IR_DRX_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_DRX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_DRX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_DRX_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_DRX; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_ELO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_ELO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_ELO) >> MCAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_ELO; + tmp |= value << MCAN_IR_ELO_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_ELO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_ELO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_ELO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_ELO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_EP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_EP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_EP) >> MCAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_EP; + tmp |= value << MCAN_IR_EP_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_EP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_EP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_EP_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_EP; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_EW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_EW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_EW) >> MCAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_EW; + tmp |= value << MCAN_IR_EW_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_EW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_EW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_EW_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_EW; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_BO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_BO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_BO) >> MCAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_BO; + tmp |= value << MCAN_IR_BO_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_BO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_BO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_BO_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_BO; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_WDI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_WDI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_WDI) >> MCAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_WDI; + tmp |= value << MCAN_IR_WDI_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_WDI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_WDI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_WDI_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_WDI; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_PEA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_PEA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_PEA) >> MCAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_PEA; + tmp |= value << MCAN_IR_PEA_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_PEA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_PEA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_PEA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_PEA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_PED_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_PED; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_PED) >> MCAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_PED; + tmp |= value << MCAN_IR_PED_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_PED_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_PED; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_PED_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_PED; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_ARA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= MCAN_IR_ARA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp = (tmp & MCAN_IR_ARA) >> MCAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= ~MCAN_IR_ARA; + tmp |= value << MCAN_IR_ARA_Pos; + ((Mcan *)hw)->MCAN_IR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_ARA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~MCAN_IR_ARA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_ARA_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= MCAN_IR_ARA; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IR_reg(const void *const hw, hri_mcan_ir_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ir_reg_t hri_mcan_get_IR_reg(const void *const hw, hri_mcan_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IR; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_IR_reg(const void *const hw, hri_mcan_ir_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IR_reg(const void *const hw, hri_mcan_ir_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IR_reg(const void *const hw, hri_mcan_ir_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IR ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ir_reg_t hri_mcan_read_IR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_IR; +} + +static inline void hri_mcan_set_IE_RF0NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF0NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF0NE) >> MCAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF0NE; + tmp |= value << MCAN_IE_RF0NE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF0NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF0NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF0NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF0NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF0WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF0WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF0WE) >> MCAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF0WE; + tmp |= value << MCAN_IE_RF0WE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF0WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF0WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF0WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF0WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF0FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF0FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF0FE) >> MCAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF0FE; + tmp |= value << MCAN_IE_RF0FE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF0FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF0FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF0FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF0FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF0LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF0LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF0LE) >> MCAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF0LE; + tmp |= value << MCAN_IE_RF0LE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF0LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF0LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF0LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF0LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF1NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF1NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF1NE) >> MCAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF1NE; + tmp |= value << MCAN_IE_RF1NE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF1NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF1NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF1NE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF1NE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF1WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF1WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF1WE) >> MCAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF1WE; + tmp |= value << MCAN_IE_RF1WE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF1WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF1WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF1WE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF1WE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF1FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF1FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF1FE) >> MCAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF1FE; + tmp |= value << MCAN_IE_RF1FE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF1FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF1FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF1FE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF1FE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_RF1LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_RF1LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_RF1LE) >> MCAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_RF1LE; + tmp |= value << MCAN_IE_RF1LE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_RF1LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_RF1LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_RF1LE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_RF1LE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_HPME_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_HPME; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_HPME) >> MCAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_HPME; + tmp |= value << MCAN_IE_HPME_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_HPME_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_HPME; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_HPME_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_HPME; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TCE) >> MCAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TCE; + tmp |= value << MCAN_IE_TCE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TCE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TCE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TCFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TCFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TCFE) >> MCAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TCFE; + tmp |= value << MCAN_IE_TCFE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TCFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TCFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TCFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TCFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TFEE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TFEE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TFEE) >> MCAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TFEE; + tmp |= value << MCAN_IE_TFEE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TFEE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TFEE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TFEE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TFEE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TEFNE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TEFNE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TEFNE) >> MCAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TEFNE; + tmp |= value << MCAN_IE_TEFNE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TEFNE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TEFNE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TEFNE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TEFNE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TEFWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TEFWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TEFWE) >> MCAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TEFWE; + tmp |= value << MCAN_IE_TEFWE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TEFWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TEFWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TEFWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TEFWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TEFFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TEFFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TEFFE) >> MCAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TEFFE; + tmp |= value << MCAN_IE_TEFFE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TEFFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TEFFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TEFFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TEFFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TEFLE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TEFLE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TEFLE) >> MCAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TEFLE; + tmp |= value << MCAN_IE_TEFLE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TEFLE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TEFLE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TEFLE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TEFLE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TSWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TSWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TSWE) >> MCAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TSWE; + tmp |= value << MCAN_IE_TSWE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TSWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TSWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TSWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TSWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_MRAFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_MRAFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_MRAFE) >> MCAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_MRAFE; + tmp |= value << MCAN_IE_MRAFE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_MRAFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_MRAFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_MRAFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_MRAFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_TOOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_TOOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_TOOE) >> MCAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_TOOE; + tmp |= value << MCAN_IE_TOOE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_TOOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_TOOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_TOOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_TOOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_DRXE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_DRXE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_DRXE) >> MCAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_DRXE; + tmp |= value << MCAN_IE_DRXE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_DRXE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_DRXE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_DRXE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_DRXE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_ELOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_ELOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_ELOE) >> MCAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_ELOE; + tmp |= value << MCAN_IE_ELOE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_ELOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_ELOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_ELOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_ELOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_EPE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_EPE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_EPE) >> MCAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_EPE; + tmp |= value << MCAN_IE_EPE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_EPE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_EPE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_EPE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_EPE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_EWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_EWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_EWE) >> MCAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_EWE; + tmp |= value << MCAN_IE_EWE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_EWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_EWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_EWE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_EWE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_BOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_BOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_BOE) >> MCAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_BOE; + tmp |= value << MCAN_IE_BOE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_BOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_BOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_BOE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_BOE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_WDIE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_WDIE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_WDIE) >> MCAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_WDIE; + tmp |= value << MCAN_IE_WDIE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_WDIE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_WDIE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_WDIE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_WDIE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_PEAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_PEAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_PEAE) >> MCAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_PEAE; + tmp |= value << MCAN_IE_PEAE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_PEAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_PEAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_PEAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_PEAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_PEDE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_PEDE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_PEDE) >> MCAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_PEDE; + tmp |= value << MCAN_IE_PEDE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_PEDE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_PEDE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_PEDE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_PEDE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_ARAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= MCAN_IE_ARAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp = (tmp & MCAN_IE_ARAE) >> MCAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= ~MCAN_IE_ARAE; + tmp |= value << MCAN_IE_ARAE_Pos; + ((Mcan *)hw)->MCAN_IE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_ARAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~MCAN_IE_ARAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_ARAE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= MCAN_IE_ARAE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_IE_reg(const void *const hw, hri_mcan_ie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ie_reg_t hri_mcan_get_IE_reg(const void *const hw, hri_mcan_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_IE; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_IE_reg(const void *const hw, hri_mcan_ie_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_IE_reg(const void *const hw, hri_mcan_ie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_IE_reg(const void *const hw, hri_mcan_ie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_IE ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ie_reg_t hri_mcan_read_IE_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_IE; +} + +static inline void hri_mcan_set_ILS_RF0NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF0NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF0NL) >> MCAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF0NL; + tmp |= value << MCAN_ILS_RF0NL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF0NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF0NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF0NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF0NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF0WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF0WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF0WL) >> MCAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF0WL; + tmp |= value << MCAN_ILS_RF0WL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF0WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF0WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF0WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF0WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF0FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF0FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF0FL) >> MCAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF0FL; + tmp |= value << MCAN_ILS_RF0FL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF0FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF0FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF0FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF0FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF0LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF0LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF0LL) >> MCAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF0LL; + tmp |= value << MCAN_ILS_RF0LL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF0LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF0LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF0LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF0LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF1NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF1NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF1NL) >> MCAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF1NL; + tmp |= value << MCAN_ILS_RF1NL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF1NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF1NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF1NL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF1NL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF1WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF1WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF1WL) >> MCAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF1WL; + tmp |= value << MCAN_ILS_RF1WL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF1WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF1WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF1WL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF1WL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF1FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF1FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF1FL) >> MCAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF1FL; + tmp |= value << MCAN_ILS_RF1FL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF1FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF1FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF1FL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF1FL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_RF1LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_RF1LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_RF1LL) >> MCAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_RF1LL; + tmp |= value << MCAN_ILS_RF1LL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_RF1LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_RF1LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_RF1LL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_RF1LL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_HPML_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_HPML; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_HPML) >> MCAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_HPML; + tmp |= value << MCAN_ILS_HPML_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_HPML_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_HPML; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_HPML_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_HPML; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TCL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TCL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TCL) >> MCAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TCL; + tmp |= value << MCAN_ILS_TCL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TCL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TCL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TCL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TCL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TCFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TCFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TCFL) >> MCAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TCFL; + tmp |= value << MCAN_ILS_TCFL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TCFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TCFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TCFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TCFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TFEL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TFEL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TFEL) >> MCAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TFEL; + tmp |= value << MCAN_ILS_TFEL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TFEL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TFEL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TFEL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TFEL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TEFNL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TEFNL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TEFNL) >> MCAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TEFNL; + tmp |= value << MCAN_ILS_TEFNL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TEFNL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TEFNL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TEFNL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TEFNL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TEFWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TEFWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TEFWL) >> MCAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TEFWL; + tmp |= value << MCAN_ILS_TEFWL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TEFWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TEFWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TEFWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TEFWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TEFFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TEFFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TEFFL) >> MCAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TEFFL; + tmp |= value << MCAN_ILS_TEFFL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TEFFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TEFFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TEFFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TEFFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TEFLL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TEFLL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TEFLL) >> MCAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TEFLL; + tmp |= value << MCAN_ILS_TEFLL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TEFLL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TEFLL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TEFLL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TEFLL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TSWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TSWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TSWL) >> MCAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TSWL; + tmp |= value << MCAN_ILS_TSWL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TSWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TSWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TSWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TSWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_MRAFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_MRAFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_MRAFL) >> MCAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_MRAFL; + tmp |= value << MCAN_ILS_MRAFL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_MRAFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_MRAFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_MRAFL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_MRAFL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_TOOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_TOOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_TOOL) >> MCAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_TOOL; + tmp |= value << MCAN_ILS_TOOL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_TOOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_TOOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_TOOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_TOOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_DRXL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_DRXL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_DRXL) >> MCAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_DRXL; + tmp |= value << MCAN_ILS_DRXL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_DRXL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_DRXL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_DRXL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_DRXL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_ELOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_ELOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_ELOL) >> MCAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_ELOL; + tmp |= value << MCAN_ILS_ELOL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_ELOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_ELOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_ELOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_ELOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_EPL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_EPL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_EPL) >> MCAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_EPL; + tmp |= value << MCAN_ILS_EPL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_EPL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_EPL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_EPL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_EPL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_EWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_EWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_EWL) >> MCAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_EWL; + tmp |= value << MCAN_ILS_EWL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_EWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_EWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_EWL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_EWL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_BOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_BOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_BOL) >> MCAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_BOL; + tmp |= value << MCAN_ILS_BOL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_BOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_BOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_BOL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_BOL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_WDIL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_WDIL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_WDIL) >> MCAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_WDIL; + tmp |= value << MCAN_ILS_WDIL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_WDIL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_WDIL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_WDIL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_WDIL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_PEAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_PEAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_PEAL) >> MCAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_PEAL; + tmp |= value << MCAN_ILS_PEAL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_PEAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_PEAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_PEAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_PEAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_PEDL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_PEDL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_PEDL) >> MCAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_PEDL; + tmp |= value << MCAN_ILS_PEDL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_PEDL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_PEDL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_PEDL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_PEDL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_ARAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= MCAN_ILS_ARAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp = (tmp & MCAN_ILS_ARAL) >> MCAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= ~MCAN_ILS_ARAL; + tmp |= value << MCAN_ILS_ARAL_Pos; + ((Mcan *)hw)->MCAN_ILS = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_ARAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~MCAN_ILS_ARAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_ARAL_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= MCAN_ILS_ARAL; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILS_reg(const void *const hw, hri_mcan_ils_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ils_reg_t hri_mcan_get_ILS_reg(const void *const hw, hri_mcan_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILS; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_ILS_reg(const void *const hw, hri_mcan_ils_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILS_reg(const void *const hw, hri_mcan_ils_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILS_reg(const void *const hw, hri_mcan_ils_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILS ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ils_reg_t hri_mcan_read_ILS_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_ILS; +} + +static inline void hri_mcan_set_ILE_EINT0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE |= MCAN_ILE_EINT0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILE; + tmp = (tmp & MCAN_ILE_EINT0) >> MCAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILE; + tmp &= ~MCAN_ILE_EINT0; + tmp |= value << MCAN_ILE_EINT0_Pos; + ((Mcan *)hw)->MCAN_ILE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILE_EINT0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE &= ~MCAN_ILE_EINT0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILE_EINT0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE ^= MCAN_ILE_EINT0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILE_EINT1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE |= MCAN_ILE_EINT1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILE; + tmp = (tmp & MCAN_ILE_EINT1) >> MCAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_ILE; + tmp &= ~MCAN_ILE_EINT1; + tmp |= value << MCAN_ILE_EINT1_Pos; + ((Mcan *)hw)->MCAN_ILE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILE_EINT1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE &= ~MCAN_ILE_EINT1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILE_EINT1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE ^= MCAN_ILE_EINT1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_ILE_reg(const void *const hw, hri_mcan_ile_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ile_reg_t hri_mcan_get_ILE_reg(const void *const hw, hri_mcan_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_ILE; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_ILE_reg(const void *const hw, hri_mcan_ile_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_ILE_reg(const void *const hw, hri_mcan_ile_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_ILE_reg(const void *const hw, hri_mcan_ile_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_ILE ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ile_reg_t hri_mcan_read_ILE_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_ILE; +} + +static inline void hri_mcan_set_GFC_RRFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC |= MCAN_GFC_RRFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_RRFE) >> MCAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp &= ~MCAN_GFC_RRFE; + tmp |= value << MCAN_GFC_RRFE_Pos; + ((Mcan *)hw)->MCAN_GFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_GFC_RRFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC &= ~MCAN_GFC_RRFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_GFC_RRFE_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC ^= MCAN_GFC_RRFE; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_GFC_RRFS_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC |= MCAN_GFC_RRFS; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_RRFS) >> MCAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp &= ~MCAN_GFC_RRFS; + tmp |= value << MCAN_GFC_RRFS_Pos; + ((Mcan *)hw)->MCAN_GFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_GFC_RRFS_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC &= ~MCAN_GFC_RRFS; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_GFC_RRFS_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC ^= MCAN_GFC_RRFS; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_GFC_ANFE_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC |= MCAN_GFC_ANFE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_get_GFC_ANFE_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_ANFE(mask)) >> MCAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_mcan_write_GFC_ANFE_bf(const void *const hw, hri_mcan_gfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp &= ~MCAN_GFC_ANFE_Msk; + tmp |= MCAN_GFC_ANFE(data); + ((Mcan *)hw)->MCAN_GFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_GFC_ANFE_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC &= ~MCAN_GFC_ANFE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_GFC_ANFE_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC ^= MCAN_GFC_ANFE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_ANFE_Msk) >> MCAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_mcan_set_GFC_ANFS_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC |= MCAN_GFC_ANFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_get_GFC_ANFS_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_ANFS(mask)) >> MCAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_mcan_write_GFC_ANFS_bf(const void *const hw, hri_mcan_gfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp &= ~MCAN_GFC_ANFS_Msk; + tmp |= MCAN_GFC_ANFS(data); + ((Mcan *)hw)->MCAN_GFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_GFC_ANFS_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC &= ~MCAN_GFC_ANFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_GFC_ANFS_bf(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC ^= MCAN_GFC_ANFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp = (tmp & MCAN_GFC_ANFS_Msk) >> MCAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_mcan_set_GFC_reg(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_get_GFC_reg(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_GFC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_GFC_reg(const void *const hw, hri_mcan_gfc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_GFC_reg(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_GFC_reg(const void *const hw, hri_mcan_gfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_GFC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_gfc_reg_t hri_mcan_read_GFC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_GFC; +} + +static inline void hri_mcan_set_SIDFC_FLSSA_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC |= MCAN_SIDFC_FLSSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_get_SIDFC_FLSSA_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp = (tmp & MCAN_SIDFC_FLSSA(mask)) >> MCAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_mcan_write_SIDFC_FLSSA_bf(const void *const hw, hri_mcan_sidfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp &= ~MCAN_SIDFC_FLSSA_Msk; + tmp |= MCAN_SIDFC_FLSSA(data); + ((Mcan *)hw)->MCAN_SIDFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_SIDFC_FLSSA_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC &= ~MCAN_SIDFC_FLSSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC ^= MCAN_SIDFC_FLSSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp = (tmp & MCAN_SIDFC_FLSSA_Msk) >> MCAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_mcan_set_SIDFC_LSS_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC |= MCAN_SIDFC_LSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_get_SIDFC_LSS_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp = (tmp & MCAN_SIDFC_LSS(mask)) >> MCAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_mcan_write_SIDFC_LSS_bf(const void *const hw, hri_mcan_sidfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp &= ~MCAN_SIDFC_LSS_Msk; + tmp |= MCAN_SIDFC_LSS(data); + ((Mcan *)hw)->MCAN_SIDFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_SIDFC_LSS_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC &= ~MCAN_SIDFC_LSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_SIDFC_LSS_bf(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC ^= MCAN_SIDFC_LSS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp = (tmp & MCAN_SIDFC_LSS_Msk) >> MCAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_mcan_set_SIDFC_reg(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_get_SIDFC_reg(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_SIDFC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_SIDFC_reg(const void *const hw, hri_mcan_sidfc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_SIDFC_reg(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_SIDFC_reg(const void *const hw, hri_mcan_sidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_SIDFC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_sidfc_reg_t hri_mcan_read_SIDFC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_SIDFC; +} + +static inline void hri_mcan_set_XIDFC_FLESA_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC |= MCAN_XIDFC_FLESA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_get_XIDFC_FLESA_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp = (tmp & MCAN_XIDFC_FLESA(mask)) >> MCAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_mcan_write_XIDFC_FLESA_bf(const void *const hw, hri_mcan_xidfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp &= ~MCAN_XIDFC_FLESA_Msk; + tmp |= MCAN_XIDFC_FLESA(data); + ((Mcan *)hw)->MCAN_XIDFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_XIDFC_FLESA_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC &= ~MCAN_XIDFC_FLESA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_XIDFC_FLESA_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC ^= MCAN_XIDFC_FLESA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp = (tmp & MCAN_XIDFC_FLESA_Msk) >> MCAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_mcan_set_XIDFC_LSE_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC |= MCAN_XIDFC_LSE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_get_XIDFC_LSE_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp = (tmp & MCAN_XIDFC_LSE(mask)) >> MCAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_mcan_write_XIDFC_LSE_bf(const void *const hw, hri_mcan_xidfc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp &= ~MCAN_XIDFC_LSE_Msk; + tmp |= MCAN_XIDFC_LSE(data); + ((Mcan *)hw)->MCAN_XIDFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_XIDFC_LSE_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC &= ~MCAN_XIDFC_LSE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_XIDFC_LSE_bf(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC ^= MCAN_XIDFC_LSE(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp = (tmp & MCAN_XIDFC_LSE_Msk) >> MCAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_mcan_set_XIDFC_reg(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_get_XIDFC_reg(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDFC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_XIDFC_reg(const void *const hw, hri_mcan_xidfc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_XIDFC_reg(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_XIDFC_reg(const void *const hw, hri_mcan_xidfc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDFC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidfc_reg_t hri_mcan_read_XIDFC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_XIDFC; +} + +static inline void hri_mcan_set_XIDAM_EIDM_bf(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM |= MCAN_XIDAM_EIDM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidam_reg_t hri_mcan_get_XIDAM_EIDM_bf(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDAM; + tmp = (tmp & MCAN_XIDAM_EIDM(mask)) >> MCAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_mcan_write_XIDAM_EIDM_bf(const void *const hw, hri_mcan_xidam_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_XIDAM; + tmp &= ~MCAN_XIDAM_EIDM_Msk; + tmp |= MCAN_XIDAM_EIDM(data); + ((Mcan *)hw)->MCAN_XIDAM = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_XIDAM_EIDM_bf(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM &= ~MCAN_XIDAM_EIDM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_XIDAM_EIDM_bf(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM ^= MCAN_XIDAM_EIDM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidam_reg_t hri_mcan_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDAM; + tmp = (tmp & MCAN_XIDAM_EIDM_Msk) >> MCAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_mcan_set_XIDAM_reg(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidam_reg_t hri_mcan_get_XIDAM_reg(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_XIDAM; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_XIDAM_reg(const void *const hw, hri_mcan_xidam_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_XIDAM_reg(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_XIDAM_reg(const void *const hw, hri_mcan_xidam_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_XIDAM ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_xidam_reg_t hri_mcan_read_XIDAM_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_XIDAM; +} + +static inline void hri_mcan_set_NDAT1_ND0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND0) >> MCAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND0; + tmp |= value << MCAN_NDAT1_ND0_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND1) >> MCAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND1; + tmp |= value << MCAN_NDAT1_ND1_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND2) >> MCAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND2; + tmp |= value << MCAN_NDAT1_ND2_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND3) >> MCAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND3; + tmp |= value << MCAN_NDAT1_ND3_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND4) >> MCAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND4; + tmp |= value << MCAN_NDAT1_ND4_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND5) >> MCAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND5; + tmp |= value << MCAN_NDAT1_ND5_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND6) >> MCAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND6; + tmp |= value << MCAN_NDAT1_ND6_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND7) >> MCAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND7; + tmp |= value << MCAN_NDAT1_ND7_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND8) >> MCAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND8; + tmp |= value << MCAN_NDAT1_ND8_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND9) >> MCAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND9; + tmp |= value << MCAN_NDAT1_ND9_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND10) >> MCAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND10; + tmp |= value << MCAN_NDAT1_ND10_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND11) >> MCAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND11; + tmp |= value << MCAN_NDAT1_ND11_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND12) >> MCAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND12; + tmp |= value << MCAN_NDAT1_ND12_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND13) >> MCAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND13; + tmp |= value << MCAN_NDAT1_ND13_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND14) >> MCAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND14; + tmp |= value << MCAN_NDAT1_ND14_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND15) >> MCAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND15; + tmp |= value << MCAN_NDAT1_ND15_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND16) >> MCAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND16; + tmp |= value << MCAN_NDAT1_ND16_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND17) >> MCAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND17; + tmp |= value << MCAN_NDAT1_ND17_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND18) >> MCAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND18; + tmp |= value << MCAN_NDAT1_ND18_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND19) >> MCAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND19; + tmp |= value << MCAN_NDAT1_ND19_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND20) >> MCAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND20; + tmp |= value << MCAN_NDAT1_ND20_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND21) >> MCAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND21; + tmp |= value << MCAN_NDAT1_ND21_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND22) >> MCAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND22; + tmp |= value << MCAN_NDAT1_ND22_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND23) >> MCAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND23; + tmp |= value << MCAN_NDAT1_ND23_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND24) >> MCAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND24; + tmp |= value << MCAN_NDAT1_ND24_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND25) >> MCAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND25; + tmp |= value << MCAN_NDAT1_ND25_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND26) >> MCAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND26; + tmp |= value << MCAN_NDAT1_ND26_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND27) >> MCAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND27; + tmp |= value << MCAN_NDAT1_ND27_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND28) >> MCAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND28; + tmp |= value << MCAN_NDAT1_ND28_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND29) >> MCAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND29; + tmp |= value << MCAN_NDAT1_ND29_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND30) >> MCAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND30; + tmp |= value << MCAN_NDAT1_ND30_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_ND31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= MCAN_NDAT1_ND31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp = (tmp & MCAN_NDAT1_ND31) >> MCAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= ~MCAN_NDAT1_ND31; + tmp |= value << MCAN_NDAT1_ND31_Pos; + ((Mcan *)hw)->MCAN_NDAT1 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_ND31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~MCAN_NDAT1_ND31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_ND31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= MCAN_NDAT1_ND31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT1_reg(const void *const hw, hri_mcan_ndat1_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ndat1_reg_t hri_mcan_get_NDAT1_reg(const void *const hw, hri_mcan_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT1; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_NDAT1_reg(const void *const hw, hri_mcan_ndat1_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT1_reg(const void *const hw, hri_mcan_ndat1_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT1_reg(const void *const hw, hri_mcan_ndat1_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT1 ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ndat1_reg_t hri_mcan_read_NDAT1_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_NDAT1; +} + +static inline void hri_mcan_set_NDAT2_ND32_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND32; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND32) >> MCAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND32; + tmp |= value << MCAN_NDAT2_ND32_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND32_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND32; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND32_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND32; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND33_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND33; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND33) >> MCAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND33; + tmp |= value << MCAN_NDAT2_ND33_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND33_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND33; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND33_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND33; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND34_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND34; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND34) >> MCAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND34; + tmp |= value << MCAN_NDAT2_ND34_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND34_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND34; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND34_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND34; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND35_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND35; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND35) >> MCAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND35; + tmp |= value << MCAN_NDAT2_ND35_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND35_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND35; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND35_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND35; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND36_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND36; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND36) >> MCAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND36; + tmp |= value << MCAN_NDAT2_ND36_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND36_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND36; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND36_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND36; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND37_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND37; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND37) >> MCAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND37; + tmp |= value << MCAN_NDAT2_ND37_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND37_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND37; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND37_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND37; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND38_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND38; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND38) >> MCAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND38; + tmp |= value << MCAN_NDAT2_ND38_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND38_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND38; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND38_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND38; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND39_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND39; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND39) >> MCAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND39; + tmp |= value << MCAN_NDAT2_ND39_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND39_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND39; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND39_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND39; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND40_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND40; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND40) >> MCAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND40; + tmp |= value << MCAN_NDAT2_ND40_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND40_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND40; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND40_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND40; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND41_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND41; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND41) >> MCAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND41; + tmp |= value << MCAN_NDAT2_ND41_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND41_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND41; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND41_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND41; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND42_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND42; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND42) >> MCAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND42; + tmp |= value << MCAN_NDAT2_ND42_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND42_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND42; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND42_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND42; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND43_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND43; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND43) >> MCAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND43; + tmp |= value << MCAN_NDAT2_ND43_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND43_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND43; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND43_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND43; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND44_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND44; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND44) >> MCAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND44; + tmp |= value << MCAN_NDAT2_ND44_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND44_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND44; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND44_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND44; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND45_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND45; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND45) >> MCAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND45; + tmp |= value << MCAN_NDAT2_ND45_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND45_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND45; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND45_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND45; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND46_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND46; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND46) >> MCAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND46; + tmp |= value << MCAN_NDAT2_ND46_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND46_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND46; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND46_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND46; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND47_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND47; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND47) >> MCAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND47; + tmp |= value << MCAN_NDAT2_ND47_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND47_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND47; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND47_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND47; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND48_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND48; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND48) >> MCAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND48; + tmp |= value << MCAN_NDAT2_ND48_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND48_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND48; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND48_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND48; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND49_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND49; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND49) >> MCAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND49; + tmp |= value << MCAN_NDAT2_ND49_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND49_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND49; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND49_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND49; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND50_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND50; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND50) >> MCAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND50; + tmp |= value << MCAN_NDAT2_ND50_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND50_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND50; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND50_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND50; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND51_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND51; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND51) >> MCAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND51; + tmp |= value << MCAN_NDAT2_ND51_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND51_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND51; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND51_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND51; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND52_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND52; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND52) >> MCAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND52; + tmp |= value << MCAN_NDAT2_ND52_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND52_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND52; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND52_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND52; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND53_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND53; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND53) >> MCAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND53; + tmp |= value << MCAN_NDAT2_ND53_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND53_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND53; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND53_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND53; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND54_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND54; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND54) >> MCAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND54; + tmp |= value << MCAN_NDAT2_ND54_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND54_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND54; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND54_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND54; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND55_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND55; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND55) >> MCAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND55; + tmp |= value << MCAN_NDAT2_ND55_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND55_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND55; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND55_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND55; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND56_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND56; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND56) >> MCAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND56; + tmp |= value << MCAN_NDAT2_ND56_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND56_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND56; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND56_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND56; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND57_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND57; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND57) >> MCAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND57; + tmp |= value << MCAN_NDAT2_ND57_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND57_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND57; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND57_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND57; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND58_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND58; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND58) >> MCAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND58; + tmp |= value << MCAN_NDAT2_ND58_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND58_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND58; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND58_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND58; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND59_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND59; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND59) >> MCAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND59; + tmp |= value << MCAN_NDAT2_ND59_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND59_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND59; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND59_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND59; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND60_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND60; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND60) >> MCAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND60; + tmp |= value << MCAN_NDAT2_ND60_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND60_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND60; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND60_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND60; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND61_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND61; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND61) >> MCAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND61; + tmp |= value << MCAN_NDAT2_ND61_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND61_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND61; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND61_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND61; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND62_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND62; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND62) >> MCAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND62; + tmp |= value << MCAN_NDAT2_ND62_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND62_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND62; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND62_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND62; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_ND63_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= MCAN_NDAT2_ND63; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp = (tmp & MCAN_NDAT2_ND63) >> MCAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= ~MCAN_NDAT2_ND63; + tmp |= value << MCAN_NDAT2_ND63_Pos; + ((Mcan *)hw)->MCAN_NDAT2 = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_ND63_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~MCAN_NDAT2_ND63; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_ND63_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= MCAN_NDAT2_ND63; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_NDAT2_reg(const void *const hw, hri_mcan_ndat2_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ndat2_reg_t hri_mcan_get_NDAT2_reg(const void *const hw, hri_mcan_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_NDAT2; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_NDAT2_reg(const void *const hw, hri_mcan_ndat2_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_NDAT2_reg(const void *const hw, hri_mcan_ndat2_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_NDAT2_reg(const void *const hw, hri_mcan_ndat2_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_NDAT2 ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_ndat2_reg_t hri_mcan_read_NDAT2_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_NDAT2; +} + +static inline void hri_mcan_set_RXF0C_F0OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C |= MCAN_RXF0C_F0OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0OM) >> MCAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp &= ~MCAN_RXF0C_F0OM; + tmp |= value << MCAN_RXF0C_F0OM_Pos; + ((Mcan *)hw)->MCAN_RXF0C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0C_F0OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C &= ~MCAN_RXF0C_F0OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C ^= MCAN_RXF0C_F0OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_RXF0C_F0SA_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C |= MCAN_RXF0C_F0SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_get_RXF0C_F0SA_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0SA(mask)) >> MCAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF0C_F0SA_bf(const void *const hw, hri_mcan_rxf0c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp &= ~MCAN_RXF0C_F0SA_Msk; + tmp |= MCAN_RXF0C_F0SA(data); + ((Mcan *)hw)->MCAN_RXF0C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0C_F0SA_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C &= ~MCAN_RXF0C_F0SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0C_F0SA_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C ^= MCAN_RXF0C_F0SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0SA_Msk) >> MCAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF0C_F0S_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C |= MCAN_RXF0C_F0S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_get_RXF0C_F0S_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0S(mask)) >> MCAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF0C_F0S_bf(const void *const hw, hri_mcan_rxf0c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp &= ~MCAN_RXF0C_F0S_Msk; + tmp |= MCAN_RXF0C_F0S(data); + ((Mcan *)hw)->MCAN_RXF0C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0C_F0S_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C &= ~MCAN_RXF0C_F0S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0C_F0S_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C ^= MCAN_RXF0C_F0S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0S_Msk) >> MCAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF0C_F0WM_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C |= MCAN_RXF0C_F0WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_get_RXF0C_F0WM_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0WM(mask)) >> MCAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF0C_F0WM_bf(const void *const hw, hri_mcan_rxf0c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp &= ~MCAN_RXF0C_F0WM_Msk; + tmp |= MCAN_RXF0C_F0WM(data); + ((Mcan *)hw)->MCAN_RXF0C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0C_F0WM_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C &= ~MCAN_RXF0C_F0WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0C_F0WM_bf(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C ^= MCAN_RXF0C_F0WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp = (tmp & MCAN_RXF0C_F0WM_Msk) >> MCAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF0C_reg(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_get_RXF0C_reg(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0C; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXF0C_reg(const void *const hw, hri_mcan_rxf0c_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0C_reg(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0C_reg(const void *const hw, hri_mcan_rxf0c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0C ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0c_reg_t hri_mcan_read_RXF0C_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF0C; +} + +static inline void hri_mcan_set_RXF0A_F0AI_bf(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A |= MCAN_RXF0A_F0AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0a_reg_t hri_mcan_get_RXF0A_F0AI_bf(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0A; + tmp = (tmp & MCAN_RXF0A_F0AI(mask)) >> MCAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF0A_F0AI_bf(const void *const hw, hri_mcan_rxf0a_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF0A; + tmp &= ~MCAN_RXF0A_F0AI_Msk; + tmp |= MCAN_RXF0A_F0AI(data); + ((Mcan *)hw)->MCAN_RXF0A = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0A_F0AI_bf(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A &= ~MCAN_RXF0A_F0AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0A_F0AI_bf(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A ^= MCAN_RXF0A_F0AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0a_reg_t hri_mcan_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0A; + tmp = (tmp & MCAN_RXF0A_F0AI_Msk) >> MCAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF0A_reg(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0a_reg_t hri_mcan_get_RXF0A_reg(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF0A; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXF0A_reg(const void *const hw, hri_mcan_rxf0a_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF0A_reg(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF0A_reg(const void *const hw, hri_mcan_rxf0a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF0A ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf0a_reg_t hri_mcan_read_RXF0A_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF0A; +} + +static inline void hri_mcan_set_RXBC_RBSA_bf(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC |= MCAN_RXBC_RBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxbc_reg_t hri_mcan_get_RXBC_RBSA_bf(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXBC; + tmp = (tmp & MCAN_RXBC_RBSA(mask)) >> MCAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXBC_RBSA_bf(const void *const hw, hri_mcan_rxbc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXBC; + tmp &= ~MCAN_RXBC_RBSA_Msk; + tmp |= MCAN_RXBC_RBSA(data); + ((Mcan *)hw)->MCAN_RXBC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXBC_RBSA_bf(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC &= ~MCAN_RXBC_RBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXBC_RBSA_bf(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC ^= MCAN_RXBC_RBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxbc_reg_t hri_mcan_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXBC; + tmp = (tmp & MCAN_RXBC_RBSA_Msk) >> MCAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXBC_reg(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxbc_reg_t hri_mcan_get_RXBC_reg(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXBC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXBC_reg(const void *const hw, hri_mcan_rxbc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXBC_reg(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXBC_reg(const void *const hw, hri_mcan_rxbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXBC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxbc_reg_t hri_mcan_read_RXBC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXBC; +} + +static inline void hri_mcan_set_RXF1C_F1OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C |= MCAN_RXF1C_F1OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1OM) >> MCAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp &= ~MCAN_RXF1C_F1OM; + tmp |= value << MCAN_RXF1C_F1OM_Pos; + ((Mcan *)hw)->MCAN_RXF1C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1C_F1OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C &= ~MCAN_RXF1C_F1OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C ^= MCAN_RXF1C_F1OM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_RXF1C_F1SA_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C |= MCAN_RXF1C_F1SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_get_RXF1C_F1SA_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1SA(mask)) >> MCAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF1C_F1SA_bf(const void *const hw, hri_mcan_rxf1c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp &= ~MCAN_RXF1C_F1SA_Msk; + tmp |= MCAN_RXF1C_F1SA(data); + ((Mcan *)hw)->MCAN_RXF1C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1C_F1SA_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C &= ~MCAN_RXF1C_F1SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1C_F1SA_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C ^= MCAN_RXF1C_F1SA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1SA_Msk) >> MCAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF1C_F1S_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C |= MCAN_RXF1C_F1S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_get_RXF1C_F1S_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1S(mask)) >> MCAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF1C_F1S_bf(const void *const hw, hri_mcan_rxf1c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp &= ~MCAN_RXF1C_F1S_Msk; + tmp |= MCAN_RXF1C_F1S(data); + ((Mcan *)hw)->MCAN_RXF1C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1C_F1S_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C &= ~MCAN_RXF1C_F1S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1C_F1S_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C ^= MCAN_RXF1C_F1S(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1S_Msk) >> MCAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF1C_F1WM_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C |= MCAN_RXF1C_F1WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_get_RXF1C_F1WM_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1WM(mask)) >> MCAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF1C_F1WM_bf(const void *const hw, hri_mcan_rxf1c_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp &= ~MCAN_RXF1C_F1WM_Msk; + tmp |= MCAN_RXF1C_F1WM(data); + ((Mcan *)hw)->MCAN_RXF1C = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1C_F1WM_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C &= ~MCAN_RXF1C_F1WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1C_F1WM_bf(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C ^= MCAN_RXF1C_F1WM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp = (tmp & MCAN_RXF1C_F1WM_Msk) >> MCAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF1C_reg(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_get_RXF1C_reg(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1C; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXF1C_reg(const void *const hw, hri_mcan_rxf1c_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1C_reg(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1C_reg(const void *const hw, hri_mcan_rxf1c_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1C ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1c_reg_t hri_mcan_read_RXF1C_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF1C; +} + +static inline void hri_mcan_set_RXF1A_F1AI_bf(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A |= MCAN_RXF1A_F1AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1a_reg_t hri_mcan_get_RXF1A_F1AI_bf(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1A; + tmp = (tmp & MCAN_RXF1A_F1AI(mask)) >> MCAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXF1A_F1AI_bf(const void *const hw, hri_mcan_rxf1a_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXF1A; + tmp &= ~MCAN_RXF1A_F1AI_Msk; + tmp |= MCAN_RXF1A_F1AI(data); + ((Mcan *)hw)->MCAN_RXF1A = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1A_F1AI_bf(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A &= ~MCAN_RXF1A_F1AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1A_F1AI_bf(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A ^= MCAN_RXF1A_F1AI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1a_reg_t hri_mcan_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1A; + tmp = (tmp & MCAN_RXF1A_F1AI_Msk) >> MCAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXF1A_reg(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1a_reg_t hri_mcan_get_RXF1A_reg(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXF1A; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXF1A_reg(const void *const hw, hri_mcan_rxf1a_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXF1A_reg(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXF1A_reg(const void *const hw, hri_mcan_rxf1a_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXF1A ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxf1a_reg_t hri_mcan_read_RXF1A_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXF1A; +} + +static inline void hri_mcan_set_RXESC_F0DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC |= MCAN_RXESC_F0DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_get_RXESC_F0DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_F0DS(mask)) >> MCAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXESC_F0DS_bf(const void *const hw, hri_mcan_rxesc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp &= ~MCAN_RXESC_F0DS_Msk; + tmp |= MCAN_RXESC_F0DS(data); + ((Mcan *)hw)->MCAN_RXESC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXESC_F0DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC &= ~MCAN_RXESC_F0DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXESC_F0DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC ^= MCAN_RXESC_F0DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_F0DS_Msk) >> MCAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXESC_F1DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC |= MCAN_RXESC_F1DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_get_RXESC_F1DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_F1DS(mask)) >> MCAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXESC_F1DS_bf(const void *const hw, hri_mcan_rxesc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp &= ~MCAN_RXESC_F1DS_Msk; + tmp |= MCAN_RXESC_F1DS(data); + ((Mcan *)hw)->MCAN_RXESC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXESC_F1DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC &= ~MCAN_RXESC_F1DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXESC_F1DS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC ^= MCAN_RXESC_F1DS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_F1DS_Msk) >> MCAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXESC_RBDS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC |= MCAN_RXESC_RBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_get_RXESC_RBDS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_RBDS(mask)) >> MCAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_mcan_write_RXESC_RBDS_bf(const void *const hw, hri_mcan_rxesc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp &= ~MCAN_RXESC_RBDS_Msk; + tmp |= MCAN_RXESC_RBDS(data); + ((Mcan *)hw)->MCAN_RXESC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXESC_RBDS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC &= ~MCAN_RXESC_RBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXESC_RBDS_bf(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC ^= MCAN_RXESC_RBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp = (tmp & MCAN_RXESC_RBDS_Msk) >> MCAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_mcan_set_RXESC_reg(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_get_RXESC_reg(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_RXESC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_RXESC_reg(const void *const hw, hri_mcan_rxesc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_RXESC_reg(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_RXESC_reg(const void *const hw, hri_mcan_rxesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_RXESC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_rxesc_reg_t hri_mcan_read_RXESC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_RXESC; +} + +static inline void hri_mcan_set_TXBC_TFQM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC |= MCAN_TXBC_TFQM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_TFQM) >> MCAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp &= ~MCAN_TXBC_TFQM; + tmp |= value << MCAN_TXBC_TFQM_Pos; + ((Mcan *)hw)->MCAN_TXBC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBC_TFQM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC &= ~MCAN_TXBC_TFQM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBC_TFQM_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC ^= MCAN_TXBC_TFQM; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBC_TBSA_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC |= MCAN_TXBC_TBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_get_TXBC_TBSA_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_TBSA(mask)) >> MCAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXBC_TBSA_bf(const void *const hw, hri_mcan_txbc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp &= ~MCAN_TXBC_TBSA_Msk; + tmp |= MCAN_TXBC_TBSA(data); + ((Mcan *)hw)->MCAN_TXBC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBC_TBSA_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC &= ~MCAN_TXBC_TBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBC_TBSA_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC ^= MCAN_TXBC_TBSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_TBSA_Msk) >> MCAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXBC_NDTB_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC |= MCAN_TXBC_NDTB(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_get_TXBC_NDTB_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_NDTB(mask)) >> MCAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXBC_NDTB_bf(const void *const hw, hri_mcan_txbc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp &= ~MCAN_TXBC_NDTB_Msk; + tmp |= MCAN_TXBC_NDTB(data); + ((Mcan *)hw)->MCAN_TXBC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBC_NDTB_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC &= ~MCAN_TXBC_NDTB(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBC_NDTB_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC ^= MCAN_TXBC_NDTB(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_NDTB_Msk) >> MCAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXBC_TFQS_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC |= MCAN_TXBC_TFQS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_get_TXBC_TFQS_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_TFQS(mask)) >> MCAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXBC_TFQS_bf(const void *const hw, hri_mcan_txbc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp &= ~MCAN_TXBC_TFQS_Msk; + tmp |= MCAN_TXBC_TFQS(data); + ((Mcan *)hw)->MCAN_TXBC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBC_TFQS_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC &= ~MCAN_TXBC_TFQS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBC_TFQS_bf(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC ^= MCAN_TXBC_TFQS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp = (tmp & MCAN_TXBC_TFQS_Msk) >> MCAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXBC_reg(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_get_TXBC_reg(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXBC_reg(const void *const hw, hri_mcan_txbc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBC_reg(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBC_reg(const void *const hw, hri_mcan_txbc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbc_reg_t hri_mcan_read_TXBC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBC; +} + +static inline void hri_mcan_set_TXESC_TBDS_bf(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC |= MCAN_TXESC_TBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txesc_reg_t hri_mcan_get_TXESC_TBDS_bf(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXESC; + tmp = (tmp & MCAN_TXESC_TBDS(mask)) >> MCAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXESC_TBDS_bf(const void *const hw, hri_mcan_txesc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXESC; + tmp &= ~MCAN_TXESC_TBDS_Msk; + tmp |= MCAN_TXESC_TBDS(data); + ((Mcan *)hw)->MCAN_TXESC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXESC_TBDS_bf(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC &= ~MCAN_TXESC_TBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXESC_TBDS_bf(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC ^= MCAN_TXESC_TBDS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txesc_reg_t hri_mcan_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXESC; + tmp = (tmp & MCAN_TXESC_TBDS_Msk) >> MCAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXESC_reg(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txesc_reg_t hri_mcan_get_TXESC_reg(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXESC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXESC_reg(const void *const hw, hri_mcan_txesc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXESC_reg(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXESC_reg(const void *const hw, hri_mcan_txesc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXESC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txesc_reg_t hri_mcan_read_TXESC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXESC; +} + +static inline void hri_mcan_set_TXBAR_AR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR0) >> MCAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR0; + tmp |= value << MCAN_TXBAR_AR0_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR1) >> MCAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR1; + tmp |= value << MCAN_TXBAR_AR1_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR2) >> MCAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR2; + tmp |= value << MCAN_TXBAR_AR2_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR3) >> MCAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR3; + tmp |= value << MCAN_TXBAR_AR3_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR4) >> MCAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR4; + tmp |= value << MCAN_TXBAR_AR4_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR5) >> MCAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR5; + tmp |= value << MCAN_TXBAR_AR5_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR6) >> MCAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR6; + tmp |= value << MCAN_TXBAR_AR6_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR7) >> MCAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR7; + tmp |= value << MCAN_TXBAR_AR7_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR8) >> MCAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR8; + tmp |= value << MCAN_TXBAR_AR8_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR9) >> MCAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR9; + tmp |= value << MCAN_TXBAR_AR9_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR10) >> MCAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR10; + tmp |= value << MCAN_TXBAR_AR10_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR11) >> MCAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR11; + tmp |= value << MCAN_TXBAR_AR11_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR12) >> MCAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR12; + tmp |= value << MCAN_TXBAR_AR12_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR13) >> MCAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR13; + tmp |= value << MCAN_TXBAR_AR13_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR14) >> MCAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR14; + tmp |= value << MCAN_TXBAR_AR14_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR15) >> MCAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR15; + tmp |= value << MCAN_TXBAR_AR15_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR16) >> MCAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR16; + tmp |= value << MCAN_TXBAR_AR16_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR17) >> MCAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR17; + tmp |= value << MCAN_TXBAR_AR17_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR18) >> MCAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR18; + tmp |= value << MCAN_TXBAR_AR18_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR19) >> MCAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR19; + tmp |= value << MCAN_TXBAR_AR19_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR20) >> MCAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR20; + tmp |= value << MCAN_TXBAR_AR20_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR21) >> MCAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR21; + tmp |= value << MCAN_TXBAR_AR21_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR22) >> MCAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR22; + tmp |= value << MCAN_TXBAR_AR22_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR23) >> MCAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR23; + tmp |= value << MCAN_TXBAR_AR23_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR24) >> MCAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR24; + tmp |= value << MCAN_TXBAR_AR24_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR25) >> MCAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR25; + tmp |= value << MCAN_TXBAR_AR25_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR26) >> MCAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR26; + tmp |= value << MCAN_TXBAR_AR26_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR27) >> MCAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR27; + tmp |= value << MCAN_TXBAR_AR27_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR28) >> MCAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR28; + tmp |= value << MCAN_TXBAR_AR28_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR29) >> MCAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR29; + tmp |= value << MCAN_TXBAR_AR29_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR30) >> MCAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR30; + tmp |= value << MCAN_TXBAR_AR30_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_AR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= MCAN_TXBAR_AR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp = (tmp & MCAN_TXBAR_AR31) >> MCAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= ~MCAN_TXBAR_AR31; + tmp |= value << MCAN_TXBAR_AR31_Pos; + ((Mcan *)hw)->MCAN_TXBAR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_AR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~MCAN_TXBAR_AR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_AR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= MCAN_TXBAR_AR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBAR_reg(const void *const hw, hri_mcan_txbar_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbar_reg_t hri_mcan_get_TXBAR_reg(const void *const hw, hri_mcan_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBAR; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXBAR_reg(const void *const hw, hri_mcan_txbar_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBAR_reg(const void *const hw, hri_mcan_txbar_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBAR_reg(const void *const hw, hri_mcan_txbar_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBAR ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbar_reg_t hri_mcan_read_TXBAR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBAR; +} + +static inline void hri_mcan_set_TXBCR_CR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR0) >> MCAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR0; + tmp |= value << MCAN_TXBCR_CR0_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR1) >> MCAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR1; + tmp |= value << MCAN_TXBCR_CR1_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR2) >> MCAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR2; + tmp |= value << MCAN_TXBCR_CR2_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR3) >> MCAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR3; + tmp |= value << MCAN_TXBCR_CR3_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR4) >> MCAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR4; + tmp |= value << MCAN_TXBCR_CR4_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR5) >> MCAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR5; + tmp |= value << MCAN_TXBCR_CR5_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR6) >> MCAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR6; + tmp |= value << MCAN_TXBCR_CR6_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR7) >> MCAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR7; + tmp |= value << MCAN_TXBCR_CR7_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR8) >> MCAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR8; + tmp |= value << MCAN_TXBCR_CR8_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR9) >> MCAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR9; + tmp |= value << MCAN_TXBCR_CR9_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR10) >> MCAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR10; + tmp |= value << MCAN_TXBCR_CR10_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR11) >> MCAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR11; + tmp |= value << MCAN_TXBCR_CR11_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR12) >> MCAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR12; + tmp |= value << MCAN_TXBCR_CR12_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR13) >> MCAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR13; + tmp |= value << MCAN_TXBCR_CR13_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR14) >> MCAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR14; + tmp |= value << MCAN_TXBCR_CR14_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR15) >> MCAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR15; + tmp |= value << MCAN_TXBCR_CR15_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR16) >> MCAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR16; + tmp |= value << MCAN_TXBCR_CR16_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR17) >> MCAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR17; + tmp |= value << MCAN_TXBCR_CR17_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR18) >> MCAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR18; + tmp |= value << MCAN_TXBCR_CR18_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR19) >> MCAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR19; + tmp |= value << MCAN_TXBCR_CR19_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR20) >> MCAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR20; + tmp |= value << MCAN_TXBCR_CR20_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR21) >> MCAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR21; + tmp |= value << MCAN_TXBCR_CR21_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR22) >> MCAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR22; + tmp |= value << MCAN_TXBCR_CR22_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR23) >> MCAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR23; + tmp |= value << MCAN_TXBCR_CR23_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR24) >> MCAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR24; + tmp |= value << MCAN_TXBCR_CR24_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR25) >> MCAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR25; + tmp |= value << MCAN_TXBCR_CR25_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR26) >> MCAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR26; + tmp |= value << MCAN_TXBCR_CR26_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR27) >> MCAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR27; + tmp |= value << MCAN_TXBCR_CR27_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR28) >> MCAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR28; + tmp |= value << MCAN_TXBCR_CR28_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR29) >> MCAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR29; + tmp |= value << MCAN_TXBCR_CR29_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR30) >> MCAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR30; + tmp |= value << MCAN_TXBCR_CR30_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_CR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= MCAN_TXBCR_CR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp = (tmp & MCAN_TXBCR_CR31) >> MCAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= ~MCAN_TXBCR_CR31; + tmp |= value << MCAN_TXBCR_CR31_Pos; + ((Mcan *)hw)->MCAN_TXBCR = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_CR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~MCAN_TXBCR_CR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_CR31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= MCAN_TXBCR_CR31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCR_reg(const void *const hw, hri_mcan_txbcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbcr_reg_t hri_mcan_get_TXBCR_reg(const void *const hw, hri_mcan_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCR; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXBCR_reg(const void *const hw, hri_mcan_txbcr_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCR_reg(const void *const hw, hri_mcan_txbcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCR_reg(const void *const hw, hri_mcan_txbcr_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCR ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbcr_reg_t hri_mcan_read_TXBCR_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBCR; +} + +static inline void hri_mcan_set_TXBTIE_TIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE0) >> MCAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE0; + tmp |= value << MCAN_TXBTIE_TIE0_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE1) >> MCAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE1; + tmp |= value << MCAN_TXBTIE_TIE1_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE2) >> MCAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE2; + tmp |= value << MCAN_TXBTIE_TIE2_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE3) >> MCAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE3; + tmp |= value << MCAN_TXBTIE_TIE3_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE4) >> MCAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE4; + tmp |= value << MCAN_TXBTIE_TIE4_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE5) >> MCAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE5; + tmp |= value << MCAN_TXBTIE_TIE5_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE6) >> MCAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE6; + tmp |= value << MCAN_TXBTIE_TIE6_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE7) >> MCAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE7; + tmp |= value << MCAN_TXBTIE_TIE7_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE8) >> MCAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE8; + tmp |= value << MCAN_TXBTIE_TIE8_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE9) >> MCAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE9; + tmp |= value << MCAN_TXBTIE_TIE9_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE10) >> MCAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE10; + tmp |= value << MCAN_TXBTIE_TIE10_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE11) >> MCAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE11; + tmp |= value << MCAN_TXBTIE_TIE11_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE12) >> MCAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE12; + tmp |= value << MCAN_TXBTIE_TIE12_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE13) >> MCAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE13; + tmp |= value << MCAN_TXBTIE_TIE13_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE14) >> MCAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE14; + tmp |= value << MCAN_TXBTIE_TIE14_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE15) >> MCAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE15; + tmp |= value << MCAN_TXBTIE_TIE15_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE16) >> MCAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE16; + tmp |= value << MCAN_TXBTIE_TIE16_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE17) >> MCAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE17; + tmp |= value << MCAN_TXBTIE_TIE17_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE18) >> MCAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE18; + tmp |= value << MCAN_TXBTIE_TIE18_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE19) >> MCAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE19; + tmp |= value << MCAN_TXBTIE_TIE19_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE20) >> MCAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE20; + tmp |= value << MCAN_TXBTIE_TIE20_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE21) >> MCAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE21; + tmp |= value << MCAN_TXBTIE_TIE21_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE22) >> MCAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE22; + tmp |= value << MCAN_TXBTIE_TIE22_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE23) >> MCAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE23; + tmp |= value << MCAN_TXBTIE_TIE23_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE24) >> MCAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE24; + tmp |= value << MCAN_TXBTIE_TIE24_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE25) >> MCAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE25; + tmp |= value << MCAN_TXBTIE_TIE25_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE26) >> MCAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE26; + tmp |= value << MCAN_TXBTIE_TIE26_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE27) >> MCAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE27; + tmp |= value << MCAN_TXBTIE_TIE27_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE28) >> MCAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE28; + tmp |= value << MCAN_TXBTIE_TIE28_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE29) >> MCAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE29; + tmp |= value << MCAN_TXBTIE_TIE29_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE30) >> MCAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE30; + tmp |= value << MCAN_TXBTIE_TIE30_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_TIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= MCAN_TXBTIE_TIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp = (tmp & MCAN_TXBTIE_TIE31) >> MCAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= ~MCAN_TXBTIE_TIE31; + tmp |= value << MCAN_TXBTIE_TIE31_Pos; + ((Mcan *)hw)->MCAN_TXBTIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~MCAN_TXBTIE_TIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= MCAN_TXBTIE_TIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBTIE_reg(const void *const hw, hri_mcan_txbtie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbtie_reg_t hri_mcan_get_TXBTIE_reg(const void *const hw, hri_mcan_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBTIE; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXBTIE_reg(const void *const hw, hri_mcan_txbtie_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBTIE_reg(const void *const hw, hri_mcan_txbtie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBTIE_reg(const void *const hw, hri_mcan_txbtie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBTIE ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbtie_reg_t hri_mcan_read_TXBTIE_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBTIE; +} + +static inline void hri_mcan_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE0) >> MCAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE0; + tmp |= value << MCAN_TXBCIE_CFIE0_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE0; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE1) >> MCAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE1; + tmp |= value << MCAN_TXBCIE_CFIE1_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE1; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE2) >> MCAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE2; + tmp |= value << MCAN_TXBCIE_CFIE2_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE2; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE3) >> MCAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE3; + tmp |= value << MCAN_TXBCIE_CFIE3_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE3; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE4) >> MCAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE4; + tmp |= value << MCAN_TXBCIE_CFIE4_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE4; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE5) >> MCAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE5; + tmp |= value << MCAN_TXBCIE_CFIE5_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE5; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE6) >> MCAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE6; + tmp |= value << MCAN_TXBCIE_CFIE6_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE6; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE7) >> MCAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE7; + tmp |= value << MCAN_TXBCIE_CFIE7_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE7; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE8) >> MCAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE8; + tmp |= value << MCAN_TXBCIE_CFIE8_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE8; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE9) >> MCAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE9; + tmp |= value << MCAN_TXBCIE_CFIE9_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE9; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE10) >> MCAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE10; + tmp |= value << MCAN_TXBCIE_CFIE10_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE10; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE11) >> MCAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE11; + tmp |= value << MCAN_TXBCIE_CFIE11_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE11; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE12) >> MCAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE12; + tmp |= value << MCAN_TXBCIE_CFIE12_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE12; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE13) >> MCAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE13; + tmp |= value << MCAN_TXBCIE_CFIE13_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE13; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE14) >> MCAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE14; + tmp |= value << MCAN_TXBCIE_CFIE14_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE14; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE15) >> MCAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE15; + tmp |= value << MCAN_TXBCIE_CFIE15_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE15; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE16) >> MCAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE16; + tmp |= value << MCAN_TXBCIE_CFIE16_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE16; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE17) >> MCAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE17; + tmp |= value << MCAN_TXBCIE_CFIE17_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE17; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE18) >> MCAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE18; + tmp |= value << MCAN_TXBCIE_CFIE18_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE18; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE19) >> MCAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE19; + tmp |= value << MCAN_TXBCIE_CFIE19_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE19; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE20) >> MCAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE20; + tmp |= value << MCAN_TXBCIE_CFIE20_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE20; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE21) >> MCAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE21; + tmp |= value << MCAN_TXBCIE_CFIE21_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE21; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE22) >> MCAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE22; + tmp |= value << MCAN_TXBCIE_CFIE22_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE22; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE23) >> MCAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE23; + tmp |= value << MCAN_TXBCIE_CFIE23_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE23; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE24) >> MCAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE24; + tmp |= value << MCAN_TXBCIE_CFIE24_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE24; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE25) >> MCAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE25; + tmp |= value << MCAN_TXBCIE_CFIE25_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE25; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE26) >> MCAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE26; + tmp |= value << MCAN_TXBCIE_CFIE26_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE26; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE27) >> MCAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE27; + tmp |= value << MCAN_TXBCIE_CFIE27_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE27; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE28) >> MCAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE28; + tmp |= value << MCAN_TXBCIE_CFIE28_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE28; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE29) >> MCAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE29; + tmp |= value << MCAN_TXBCIE_CFIE29_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE29; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE30) >> MCAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE30; + tmp |= value << MCAN_TXBCIE_CFIE30_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE30; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= MCAN_TXBCIE_CFIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mcan_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp = (tmp & MCAN_TXBCIE_CFIE31) >> MCAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_mcan_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= ~MCAN_TXBCIE_CFIE31; + tmp |= value << MCAN_TXBCIE_CFIE31_Pos; + ((Mcan *)hw)->MCAN_TXBCIE = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~MCAN_TXBCIE_CFIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= MCAN_TXBCIE_CFIE31; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_set_TXBCIE_reg(const void *const hw, hri_mcan_txbcie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbcie_reg_t hri_mcan_get_TXBCIE_reg(const void *const hw, hri_mcan_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXBCIE; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXBCIE_reg(const void *const hw, hri_mcan_txbcie_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXBCIE_reg(const void *const hw, hri_mcan_txbcie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXBCIE_reg(const void *const hw, hri_mcan_txbcie_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXBCIE ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txbcie_reg_t hri_mcan_read_TXBCIE_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXBCIE; +} + +static inline void hri_mcan_set_TXEFC_EFSA_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC |= MCAN_TXEFC_EFSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_get_TXEFC_EFSA_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFSA(mask)) >> MCAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXEFC_EFSA_bf(const void *const hw, hri_mcan_txefc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp &= ~MCAN_TXEFC_EFSA_Msk; + tmp |= MCAN_TXEFC_EFSA(data); + ((Mcan *)hw)->MCAN_TXEFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFC_EFSA_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC &= ~MCAN_TXEFC_EFSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFC_EFSA_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC ^= MCAN_TXEFC_EFSA(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFSA_Msk) >> MCAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXEFC_EFS_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC |= MCAN_TXEFC_EFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_get_TXEFC_EFS_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFS(mask)) >> MCAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXEFC_EFS_bf(const void *const hw, hri_mcan_txefc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp &= ~MCAN_TXEFC_EFS_Msk; + tmp |= MCAN_TXEFC_EFS(data); + ((Mcan *)hw)->MCAN_TXEFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFC_EFS_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC &= ~MCAN_TXEFC_EFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFC_EFS_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC ^= MCAN_TXEFC_EFS(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFS_Msk) >> MCAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXEFC_EFWM_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC |= MCAN_TXEFC_EFWM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_get_TXEFC_EFWM_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFWM(mask)) >> MCAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXEFC_EFWM_bf(const void *const hw, hri_mcan_txefc_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp &= ~MCAN_TXEFC_EFWM_Msk; + tmp |= MCAN_TXEFC_EFWM(data); + ((Mcan *)hw)->MCAN_TXEFC = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFC_EFWM_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC &= ~MCAN_TXEFC_EFWM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFC_EFWM_bf(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC ^= MCAN_TXEFC_EFWM(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp = (tmp & MCAN_TXEFC_EFWM_Msk) >> MCAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXEFC_reg(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_get_TXEFC_reg(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFC; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXEFC_reg(const void *const hw, hri_mcan_txefc_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFC_reg(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFC_reg(const void *const hw, hri_mcan_txefc_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFC ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefc_reg_t hri_mcan_read_TXEFC_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXEFC; +} + +static inline void hri_mcan_set_TXEFA_EFAI_bf(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA |= MCAN_TXEFA_EFAI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefa_reg_t hri_mcan_get_TXEFA_EFAI_bf(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFA; + tmp = (tmp & MCAN_TXEFA_EFAI(mask)) >> MCAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_mcan_write_TXEFA_EFAI_bf(const void *const hw, hri_mcan_txefa_reg_t data) +{ + uint32_t tmp; + MCAN_CRITICAL_SECTION_ENTER(); + tmp = ((Mcan *)hw)->MCAN_TXEFA; + tmp &= ~MCAN_TXEFA_EFAI_Msk; + tmp |= MCAN_TXEFA_EFAI(data); + ((Mcan *)hw)->MCAN_TXEFA = tmp; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFA_EFAI_bf(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA &= ~MCAN_TXEFA_EFAI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFA_EFAI_bf(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA ^= MCAN_TXEFA_EFAI(mask); + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefa_reg_t hri_mcan_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFA; + tmp = (tmp & MCAN_TXEFA_EFAI_Msk) >> MCAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_mcan_set_TXEFA_reg(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA |= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefa_reg_t hri_mcan_get_TXEFA_reg(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mcan *)hw)->MCAN_TXEFA; + tmp &= mask; + return tmp; +} + +static inline void hri_mcan_write_TXEFA_reg(const void *const hw, hri_mcan_txefa_reg_t data) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA = data; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_clear_TXEFA_reg(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA &= ~mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mcan_toggle_TXEFA_reg(const void *const hw, hri_mcan_txefa_reg_t mask) +{ + MCAN_CRITICAL_SECTION_ENTER(); + ((Mcan *)hw)->MCAN_TXEFA ^= mask; + MCAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mcan_txefa_reg_t hri_mcan_read_TXEFA_reg(const void *const hw) +{ + return ((Mcan *)hw)->MCAN_TXEFA; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCAN_E70B_H_INCLUDED */ +#endif /* _SAME70_MCAN_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_pio_e70b.h b/bsp/microchip/same70/bsp/hri/hri_pio_e70b.h new file mode 100644 index 0000000000..e40b8fb60a --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_pio_e70b.h @@ -0,0 +1,15518 @@ +/** + * \file + * + * \brief SAM PIO + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_PIO_COMPONENT_ +#ifndef _HRI_PIO_E70B_H_INCLUDED_ +#define _HRI_PIO_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PIO_CRITICAL_SECTIONS) +#define PIO_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PIO_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PIO_CRITICAL_SECTION_ENTER() +#define PIO_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pio_abcdsr_reg_t; +typedef uint32_t hri_pio_aimmr_reg_t; +typedef uint32_t hri_pio_driver_reg_t; +typedef uint32_t hri_pio_elsr_reg_t; +typedef uint32_t hri_pio_frlhsr_reg_t; +typedef uint32_t hri_pio_ifscsr_reg_t; +typedef uint32_t hri_pio_ifsr_reg_t; +typedef uint32_t hri_pio_imr_reg_t; +typedef uint32_t hri_pio_isr_reg_t; +typedef uint32_t hri_pio_locksr_reg_t; +typedef uint32_t hri_pio_mdsr_reg_t; +typedef uint32_t hri_pio_odsr_reg_t; +typedef uint32_t hri_pio_osr_reg_t; +typedef uint32_t hri_pio_owsr_reg_t; +typedef uint32_t hri_pio_pcidr_reg_t; +typedef uint32_t hri_pio_pcier_reg_t; +typedef uint32_t hri_pio_pcimr_reg_t; +typedef uint32_t hri_pio_pcisr_reg_t; +typedef uint32_t hri_pio_pcmr_reg_t; +typedef uint32_t hri_pio_pcrhr_reg_t; +typedef uint32_t hri_pio_pdsr_reg_t; +typedef uint32_t hri_pio_ppdsr_reg_t; +typedef uint32_t hri_pio_psr_reg_t; +typedef uint32_t hri_pio_pusr_reg_t; +typedef uint32_t hri_pio_scdr_reg_t; +typedef uint32_t hri_pio_schmitt_reg_t; +typedef uint32_t hri_pio_wpmr_reg_t; +typedef uint32_t hri_pio_wpsr_reg_t; + +static inline bool hri_pio_get_ISR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P0) >> PIO_ISR_P0_Pos; +} + +static inline bool hri_pio_get_ISR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P1) >> PIO_ISR_P1_Pos; +} + +static inline bool hri_pio_get_ISR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P2) >> PIO_ISR_P2_Pos; +} + +static inline bool hri_pio_get_ISR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P3) >> PIO_ISR_P3_Pos; +} + +static inline bool hri_pio_get_ISR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P4) >> PIO_ISR_P4_Pos; +} + +static inline bool hri_pio_get_ISR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P5) >> PIO_ISR_P5_Pos; +} + +static inline bool hri_pio_get_ISR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P6) >> PIO_ISR_P6_Pos; +} + +static inline bool hri_pio_get_ISR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P7) >> PIO_ISR_P7_Pos; +} + +static inline bool hri_pio_get_ISR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P8) >> PIO_ISR_P8_Pos; +} + +static inline bool hri_pio_get_ISR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P9) >> PIO_ISR_P9_Pos; +} + +static inline bool hri_pio_get_ISR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P10) >> PIO_ISR_P10_Pos; +} + +static inline bool hri_pio_get_ISR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P11) >> PIO_ISR_P11_Pos; +} + +static inline bool hri_pio_get_ISR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P12) >> PIO_ISR_P12_Pos; +} + +static inline bool hri_pio_get_ISR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P13) >> PIO_ISR_P13_Pos; +} + +static inline bool hri_pio_get_ISR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P14) >> PIO_ISR_P14_Pos; +} + +static inline bool hri_pio_get_ISR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P15) >> PIO_ISR_P15_Pos; +} + +static inline bool hri_pio_get_ISR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P16) >> PIO_ISR_P16_Pos; +} + +static inline bool hri_pio_get_ISR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P17) >> PIO_ISR_P17_Pos; +} + +static inline bool hri_pio_get_ISR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P18) >> PIO_ISR_P18_Pos; +} + +static inline bool hri_pio_get_ISR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P19) >> PIO_ISR_P19_Pos; +} + +static inline bool hri_pio_get_ISR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P20) >> PIO_ISR_P20_Pos; +} + +static inline bool hri_pio_get_ISR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P21) >> PIO_ISR_P21_Pos; +} + +static inline bool hri_pio_get_ISR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P22) >> PIO_ISR_P22_Pos; +} + +static inline bool hri_pio_get_ISR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P23) >> PIO_ISR_P23_Pos; +} + +static inline bool hri_pio_get_ISR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P24) >> PIO_ISR_P24_Pos; +} + +static inline bool hri_pio_get_ISR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P25) >> PIO_ISR_P25_Pos; +} + +static inline bool hri_pio_get_ISR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P26) >> PIO_ISR_P26_Pos; +} + +static inline bool hri_pio_get_ISR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P27) >> PIO_ISR_P27_Pos; +} + +static inline bool hri_pio_get_ISR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P28) >> PIO_ISR_P28_Pos; +} + +static inline bool hri_pio_get_ISR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P29) >> PIO_ISR_P29_Pos; +} + +static inline bool hri_pio_get_ISR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P30) >> PIO_ISR_P30_Pos; +} + +static inline bool hri_pio_get_ISR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ISR & PIO_ISR_P31) >> PIO_ISR_P31_Pos; +} + +static inline hri_pio_isr_reg_t hri_pio_get_ISR_reg(const void *const hw, hri_pio_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_isr_reg_t hri_pio_read_ISR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_ISR; +} + +static inline void hri_pio_set_PSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P0; +} + +static inline bool hri_pio_get_PSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P0) >> PIO_PSR_P0_Pos; +} + +static inline void hri_pio_write_PSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P0; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P0; + } +} + +static inline void hri_pio_clear_PSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P0; +} + +static inline void hri_pio_set_PSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P1; +} + +static inline bool hri_pio_get_PSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P1) >> PIO_PSR_P1_Pos; +} + +static inline void hri_pio_write_PSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P1; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P1; + } +} + +static inline void hri_pio_clear_PSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P1; +} + +static inline void hri_pio_set_PSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P2; +} + +static inline bool hri_pio_get_PSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P2) >> PIO_PSR_P2_Pos; +} + +static inline void hri_pio_write_PSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P2; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P2; + } +} + +static inline void hri_pio_clear_PSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P2; +} + +static inline void hri_pio_set_PSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P3; +} + +static inline bool hri_pio_get_PSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P3) >> PIO_PSR_P3_Pos; +} + +static inline void hri_pio_write_PSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P3; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P3; + } +} + +static inline void hri_pio_clear_PSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P3; +} + +static inline void hri_pio_set_PSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P4; +} + +static inline bool hri_pio_get_PSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P4) >> PIO_PSR_P4_Pos; +} + +static inline void hri_pio_write_PSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P4; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P4; + } +} + +static inline void hri_pio_clear_PSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P4; +} + +static inline void hri_pio_set_PSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P5; +} + +static inline bool hri_pio_get_PSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P5) >> PIO_PSR_P5_Pos; +} + +static inline void hri_pio_write_PSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P5; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P5; + } +} + +static inline void hri_pio_clear_PSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P5; +} + +static inline void hri_pio_set_PSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P6; +} + +static inline bool hri_pio_get_PSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P6) >> PIO_PSR_P6_Pos; +} + +static inline void hri_pio_write_PSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P6; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P6; + } +} + +static inline void hri_pio_clear_PSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P6; +} + +static inline void hri_pio_set_PSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P7; +} + +static inline bool hri_pio_get_PSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P7) >> PIO_PSR_P7_Pos; +} + +static inline void hri_pio_write_PSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P7; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P7; + } +} + +static inline void hri_pio_clear_PSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P7; +} + +static inline void hri_pio_set_PSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P8; +} + +static inline bool hri_pio_get_PSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P8) >> PIO_PSR_P8_Pos; +} + +static inline void hri_pio_write_PSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P8; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P8; + } +} + +static inline void hri_pio_clear_PSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P8; +} + +static inline void hri_pio_set_PSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P9; +} + +static inline bool hri_pio_get_PSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P9) >> PIO_PSR_P9_Pos; +} + +static inline void hri_pio_write_PSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P9; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P9; + } +} + +static inline void hri_pio_clear_PSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P9; +} + +static inline void hri_pio_set_PSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P10; +} + +static inline bool hri_pio_get_PSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P10) >> PIO_PSR_P10_Pos; +} + +static inline void hri_pio_write_PSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P10; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P10; + } +} + +static inline void hri_pio_clear_PSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P10; +} + +static inline void hri_pio_set_PSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P11; +} + +static inline bool hri_pio_get_PSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P11) >> PIO_PSR_P11_Pos; +} + +static inline void hri_pio_write_PSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P11; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P11; + } +} + +static inline void hri_pio_clear_PSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P11; +} + +static inline void hri_pio_set_PSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P12; +} + +static inline bool hri_pio_get_PSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P12) >> PIO_PSR_P12_Pos; +} + +static inline void hri_pio_write_PSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P12; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P12; + } +} + +static inline void hri_pio_clear_PSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P12; +} + +static inline void hri_pio_set_PSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P13; +} + +static inline bool hri_pio_get_PSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P13) >> PIO_PSR_P13_Pos; +} + +static inline void hri_pio_write_PSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P13; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P13; + } +} + +static inline void hri_pio_clear_PSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P13; +} + +static inline void hri_pio_set_PSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P14; +} + +static inline bool hri_pio_get_PSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P14) >> PIO_PSR_P14_Pos; +} + +static inline void hri_pio_write_PSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P14; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P14; + } +} + +static inline void hri_pio_clear_PSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P14; +} + +static inline void hri_pio_set_PSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P15; +} + +static inline bool hri_pio_get_PSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P15) >> PIO_PSR_P15_Pos; +} + +static inline void hri_pio_write_PSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P15; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P15; + } +} + +static inline void hri_pio_clear_PSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P15; +} + +static inline void hri_pio_set_PSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P16; +} + +static inline bool hri_pio_get_PSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P16) >> PIO_PSR_P16_Pos; +} + +static inline void hri_pio_write_PSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P16; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P16; + } +} + +static inline void hri_pio_clear_PSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P16; +} + +static inline void hri_pio_set_PSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P17; +} + +static inline bool hri_pio_get_PSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P17) >> PIO_PSR_P17_Pos; +} + +static inline void hri_pio_write_PSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P17; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P17; + } +} + +static inline void hri_pio_clear_PSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P17; +} + +static inline void hri_pio_set_PSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P18; +} + +static inline bool hri_pio_get_PSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P18) >> PIO_PSR_P18_Pos; +} + +static inline void hri_pio_write_PSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P18; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P18; + } +} + +static inline void hri_pio_clear_PSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P18; +} + +static inline void hri_pio_set_PSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P19; +} + +static inline bool hri_pio_get_PSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P19) >> PIO_PSR_P19_Pos; +} + +static inline void hri_pio_write_PSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P19; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P19; + } +} + +static inline void hri_pio_clear_PSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P19; +} + +static inline void hri_pio_set_PSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P20; +} + +static inline bool hri_pio_get_PSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P20) >> PIO_PSR_P20_Pos; +} + +static inline void hri_pio_write_PSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P20; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P20; + } +} + +static inline void hri_pio_clear_PSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P20; +} + +static inline void hri_pio_set_PSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P21; +} + +static inline bool hri_pio_get_PSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P21) >> PIO_PSR_P21_Pos; +} + +static inline void hri_pio_write_PSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P21; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P21; + } +} + +static inline void hri_pio_clear_PSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P21; +} + +static inline void hri_pio_set_PSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P22; +} + +static inline bool hri_pio_get_PSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P22) >> PIO_PSR_P22_Pos; +} + +static inline void hri_pio_write_PSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P22; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P22; + } +} + +static inline void hri_pio_clear_PSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P22; +} + +static inline void hri_pio_set_PSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P23; +} + +static inline bool hri_pio_get_PSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P23) >> PIO_PSR_P23_Pos; +} + +static inline void hri_pio_write_PSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P23; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P23; + } +} + +static inline void hri_pio_clear_PSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P23; +} + +static inline void hri_pio_set_PSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P24; +} + +static inline bool hri_pio_get_PSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P24) >> PIO_PSR_P24_Pos; +} + +static inline void hri_pio_write_PSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P24; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P24; + } +} + +static inline void hri_pio_clear_PSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P24; +} + +static inline void hri_pio_set_PSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P25; +} + +static inline bool hri_pio_get_PSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P25) >> PIO_PSR_P25_Pos; +} + +static inline void hri_pio_write_PSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P25; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P25; + } +} + +static inline void hri_pio_clear_PSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P25; +} + +static inline void hri_pio_set_PSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P26; +} + +static inline bool hri_pio_get_PSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P26) >> PIO_PSR_P26_Pos; +} + +static inline void hri_pio_write_PSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P26; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P26; + } +} + +static inline void hri_pio_clear_PSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P26; +} + +static inline void hri_pio_set_PSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P27; +} + +static inline bool hri_pio_get_PSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P27) >> PIO_PSR_P27_Pos; +} + +static inline void hri_pio_write_PSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P27; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P27; + } +} + +static inline void hri_pio_clear_PSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P27; +} + +static inline void hri_pio_set_PSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P28; +} + +static inline bool hri_pio_get_PSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P28) >> PIO_PSR_P28_Pos; +} + +static inline void hri_pio_write_PSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P28; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P28; + } +} + +static inline void hri_pio_clear_PSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P28; +} + +static inline void hri_pio_set_PSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P29; +} + +static inline bool hri_pio_get_PSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P29) >> PIO_PSR_P29_Pos; +} + +static inline void hri_pio_write_PSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P29; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P29; + } +} + +static inline void hri_pio_clear_PSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P29; +} + +static inline void hri_pio_set_PSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P30; +} + +static inline bool hri_pio_get_PSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P30) >> PIO_PSR_P30_Pos; +} + +static inline void hri_pio_write_PSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P30; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P30; + } +} + +static inline void hri_pio_clear_PSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P30; +} + +static inline void hri_pio_set_PSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PER = PIO_PSR_P31; +} + +static inline bool hri_pio_get_PSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PSR & PIO_PSR_P31) >> PIO_PSR_P31_Pos; +} + +static inline void hri_pio_write_PSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PDR = PIO_PSR_P31; + } else { + ((Pio *)hw)->PIO_PER = PIO_PSR_P31; + } +} + +static inline void hri_pio_clear_PSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PDR = PIO_PSR_P31; +} + +static inline void hri_pio_set_PSR_reg(const void *const hw, hri_pio_psr_reg_t mask) +{ + ((Pio *)hw)->PIO_PER = mask; +} + +static inline hri_pio_psr_reg_t hri_pio_get_PSR_reg(const void *const hw, hri_pio_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_psr_reg_t hri_pio_read_PSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PSR; +} + +static inline void hri_pio_write_PSR_reg(const void *const hw, hri_pio_psr_reg_t data) +{ + ((Pio *)hw)->PIO_PER = data; + ((Pio *)hw)->PIO_PDR = ~data; +} + +static inline void hri_pio_clear_PSR_reg(const void *const hw, hri_pio_psr_reg_t mask) +{ + ((Pio *)hw)->PIO_PDR = mask; +} + +static inline void hri_pio_set_OSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P0; +} + +static inline bool hri_pio_get_OSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P0) >> PIO_OSR_P0_Pos; +} + +static inline void hri_pio_write_OSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P0; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P0; + } +} + +static inline void hri_pio_clear_OSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P0; +} + +static inline void hri_pio_set_OSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P1; +} + +static inline bool hri_pio_get_OSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P1) >> PIO_OSR_P1_Pos; +} + +static inline void hri_pio_write_OSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P1; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P1; + } +} + +static inline void hri_pio_clear_OSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P1; +} + +static inline void hri_pio_set_OSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P2; +} + +static inline bool hri_pio_get_OSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P2) >> PIO_OSR_P2_Pos; +} + +static inline void hri_pio_write_OSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P2; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P2; + } +} + +static inline void hri_pio_clear_OSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P2; +} + +static inline void hri_pio_set_OSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P3; +} + +static inline bool hri_pio_get_OSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P3) >> PIO_OSR_P3_Pos; +} + +static inline void hri_pio_write_OSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P3; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P3; + } +} + +static inline void hri_pio_clear_OSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P3; +} + +static inline void hri_pio_set_OSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P4; +} + +static inline bool hri_pio_get_OSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P4) >> PIO_OSR_P4_Pos; +} + +static inline void hri_pio_write_OSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P4; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P4; + } +} + +static inline void hri_pio_clear_OSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P4; +} + +static inline void hri_pio_set_OSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P5; +} + +static inline bool hri_pio_get_OSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P5) >> PIO_OSR_P5_Pos; +} + +static inline void hri_pio_write_OSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P5; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P5; + } +} + +static inline void hri_pio_clear_OSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P5; +} + +static inline void hri_pio_set_OSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P6; +} + +static inline bool hri_pio_get_OSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P6) >> PIO_OSR_P6_Pos; +} + +static inline void hri_pio_write_OSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P6; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P6; + } +} + +static inline void hri_pio_clear_OSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P6; +} + +static inline void hri_pio_set_OSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P7; +} + +static inline bool hri_pio_get_OSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P7) >> PIO_OSR_P7_Pos; +} + +static inline void hri_pio_write_OSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P7; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P7; + } +} + +static inline void hri_pio_clear_OSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P7; +} + +static inline void hri_pio_set_OSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P8; +} + +static inline bool hri_pio_get_OSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P8) >> PIO_OSR_P8_Pos; +} + +static inline void hri_pio_write_OSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P8; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P8; + } +} + +static inline void hri_pio_clear_OSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P8; +} + +static inline void hri_pio_set_OSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P9; +} + +static inline bool hri_pio_get_OSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P9) >> PIO_OSR_P9_Pos; +} + +static inline void hri_pio_write_OSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P9; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P9; + } +} + +static inline void hri_pio_clear_OSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P9; +} + +static inline void hri_pio_set_OSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P10; +} + +static inline bool hri_pio_get_OSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P10) >> PIO_OSR_P10_Pos; +} + +static inline void hri_pio_write_OSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P10; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P10; + } +} + +static inline void hri_pio_clear_OSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P10; +} + +static inline void hri_pio_set_OSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P11; +} + +static inline bool hri_pio_get_OSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P11) >> PIO_OSR_P11_Pos; +} + +static inline void hri_pio_write_OSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P11; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P11; + } +} + +static inline void hri_pio_clear_OSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P11; +} + +static inline void hri_pio_set_OSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P12; +} + +static inline bool hri_pio_get_OSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P12) >> PIO_OSR_P12_Pos; +} + +static inline void hri_pio_write_OSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P12; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P12; + } +} + +static inline void hri_pio_clear_OSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P12; +} + +static inline void hri_pio_set_OSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P13; +} + +static inline bool hri_pio_get_OSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P13) >> PIO_OSR_P13_Pos; +} + +static inline void hri_pio_write_OSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P13; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P13; + } +} + +static inline void hri_pio_clear_OSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P13; +} + +static inline void hri_pio_set_OSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P14; +} + +static inline bool hri_pio_get_OSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P14) >> PIO_OSR_P14_Pos; +} + +static inline void hri_pio_write_OSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P14; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P14; + } +} + +static inline void hri_pio_clear_OSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P14; +} + +static inline void hri_pio_set_OSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P15; +} + +static inline bool hri_pio_get_OSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P15) >> PIO_OSR_P15_Pos; +} + +static inline void hri_pio_write_OSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P15; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P15; + } +} + +static inline void hri_pio_clear_OSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P15; +} + +static inline void hri_pio_set_OSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P16; +} + +static inline bool hri_pio_get_OSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P16) >> PIO_OSR_P16_Pos; +} + +static inline void hri_pio_write_OSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P16; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P16; + } +} + +static inline void hri_pio_clear_OSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P16; +} + +static inline void hri_pio_set_OSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P17; +} + +static inline bool hri_pio_get_OSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P17) >> PIO_OSR_P17_Pos; +} + +static inline void hri_pio_write_OSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P17; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P17; + } +} + +static inline void hri_pio_clear_OSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P17; +} + +static inline void hri_pio_set_OSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P18; +} + +static inline bool hri_pio_get_OSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P18) >> PIO_OSR_P18_Pos; +} + +static inline void hri_pio_write_OSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P18; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P18; + } +} + +static inline void hri_pio_clear_OSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P18; +} + +static inline void hri_pio_set_OSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P19; +} + +static inline bool hri_pio_get_OSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P19) >> PIO_OSR_P19_Pos; +} + +static inline void hri_pio_write_OSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P19; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P19; + } +} + +static inline void hri_pio_clear_OSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P19; +} + +static inline void hri_pio_set_OSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P20; +} + +static inline bool hri_pio_get_OSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P20) >> PIO_OSR_P20_Pos; +} + +static inline void hri_pio_write_OSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P20; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P20; + } +} + +static inline void hri_pio_clear_OSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P20; +} + +static inline void hri_pio_set_OSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P21; +} + +static inline bool hri_pio_get_OSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P21) >> PIO_OSR_P21_Pos; +} + +static inline void hri_pio_write_OSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P21; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P21; + } +} + +static inline void hri_pio_clear_OSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P21; +} + +static inline void hri_pio_set_OSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P22; +} + +static inline bool hri_pio_get_OSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P22) >> PIO_OSR_P22_Pos; +} + +static inline void hri_pio_write_OSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P22; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P22; + } +} + +static inline void hri_pio_clear_OSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P22; +} + +static inline void hri_pio_set_OSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P23; +} + +static inline bool hri_pio_get_OSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P23) >> PIO_OSR_P23_Pos; +} + +static inline void hri_pio_write_OSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P23; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P23; + } +} + +static inline void hri_pio_clear_OSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P23; +} + +static inline void hri_pio_set_OSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P24; +} + +static inline bool hri_pio_get_OSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P24) >> PIO_OSR_P24_Pos; +} + +static inline void hri_pio_write_OSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P24; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P24; + } +} + +static inline void hri_pio_clear_OSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P24; +} + +static inline void hri_pio_set_OSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P25; +} + +static inline bool hri_pio_get_OSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P25) >> PIO_OSR_P25_Pos; +} + +static inline void hri_pio_write_OSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P25; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P25; + } +} + +static inline void hri_pio_clear_OSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P25; +} + +static inline void hri_pio_set_OSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P26; +} + +static inline bool hri_pio_get_OSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P26) >> PIO_OSR_P26_Pos; +} + +static inline void hri_pio_write_OSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P26; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P26; + } +} + +static inline void hri_pio_clear_OSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P26; +} + +static inline void hri_pio_set_OSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P27; +} + +static inline bool hri_pio_get_OSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P27) >> PIO_OSR_P27_Pos; +} + +static inline void hri_pio_write_OSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P27; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P27; + } +} + +static inline void hri_pio_clear_OSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P27; +} + +static inline void hri_pio_set_OSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P28; +} + +static inline bool hri_pio_get_OSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P28) >> PIO_OSR_P28_Pos; +} + +static inline void hri_pio_write_OSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P28; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P28; + } +} + +static inline void hri_pio_clear_OSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P28; +} + +static inline void hri_pio_set_OSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P29; +} + +static inline bool hri_pio_get_OSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P29) >> PIO_OSR_P29_Pos; +} + +static inline void hri_pio_write_OSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P29; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P29; + } +} + +static inline void hri_pio_clear_OSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P29; +} + +static inline void hri_pio_set_OSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P30; +} + +static inline bool hri_pio_get_OSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P30) >> PIO_OSR_P30_Pos; +} + +static inline void hri_pio_write_OSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P30; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P30; + } +} + +static inline void hri_pio_clear_OSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P30; +} + +static inline void hri_pio_set_OSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OER = PIO_OSR_P31; +} + +static inline bool hri_pio_get_OSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OSR & PIO_OSR_P31) >> PIO_OSR_P31_Pos; +} + +static inline void hri_pio_write_OSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ODR = PIO_OSR_P31; + } else { + ((Pio *)hw)->PIO_OER = PIO_OSR_P31; + } +} + +static inline void hri_pio_clear_OSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ODR = PIO_OSR_P31; +} + +static inline void hri_pio_set_OSR_reg(const void *const hw, hri_pio_osr_reg_t mask) +{ + ((Pio *)hw)->PIO_OER = mask; +} + +static inline hri_pio_osr_reg_t hri_pio_get_OSR_reg(const void *const hw, hri_pio_osr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_OSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_osr_reg_t hri_pio_read_OSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_OSR; +} + +static inline void hri_pio_write_OSR_reg(const void *const hw, hri_pio_osr_reg_t data) +{ + ((Pio *)hw)->PIO_OER = data; + ((Pio *)hw)->PIO_ODR = ~data; +} + +static inline void hri_pio_clear_OSR_reg(const void *const hw, hri_pio_osr_reg_t mask) +{ + ((Pio *)hw)->PIO_ODR = mask; +} + +static inline void hri_pio_set_IFSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P0; +} + +static inline bool hri_pio_get_IFSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P0) >> PIO_IFSR_P0_Pos; +} + +static inline void hri_pio_write_IFSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P0; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P0; + } +} + +static inline void hri_pio_clear_IFSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P0; +} + +static inline void hri_pio_set_IFSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P1; +} + +static inline bool hri_pio_get_IFSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P1) >> PIO_IFSR_P1_Pos; +} + +static inline void hri_pio_write_IFSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P1; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P1; + } +} + +static inline void hri_pio_clear_IFSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P1; +} + +static inline void hri_pio_set_IFSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P2; +} + +static inline bool hri_pio_get_IFSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P2) >> PIO_IFSR_P2_Pos; +} + +static inline void hri_pio_write_IFSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P2; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P2; + } +} + +static inline void hri_pio_clear_IFSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P2; +} + +static inline void hri_pio_set_IFSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P3; +} + +static inline bool hri_pio_get_IFSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P3) >> PIO_IFSR_P3_Pos; +} + +static inline void hri_pio_write_IFSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P3; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P3; + } +} + +static inline void hri_pio_clear_IFSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P3; +} + +static inline void hri_pio_set_IFSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P4; +} + +static inline bool hri_pio_get_IFSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P4) >> PIO_IFSR_P4_Pos; +} + +static inline void hri_pio_write_IFSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P4; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P4; + } +} + +static inline void hri_pio_clear_IFSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P4; +} + +static inline void hri_pio_set_IFSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P5; +} + +static inline bool hri_pio_get_IFSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P5) >> PIO_IFSR_P5_Pos; +} + +static inline void hri_pio_write_IFSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P5; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P5; + } +} + +static inline void hri_pio_clear_IFSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P5; +} + +static inline void hri_pio_set_IFSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P6; +} + +static inline bool hri_pio_get_IFSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P6) >> PIO_IFSR_P6_Pos; +} + +static inline void hri_pio_write_IFSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P6; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P6; + } +} + +static inline void hri_pio_clear_IFSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P6; +} + +static inline void hri_pio_set_IFSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P7; +} + +static inline bool hri_pio_get_IFSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P7) >> PIO_IFSR_P7_Pos; +} + +static inline void hri_pio_write_IFSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P7; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P7; + } +} + +static inline void hri_pio_clear_IFSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P7; +} + +static inline void hri_pio_set_IFSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P8; +} + +static inline bool hri_pio_get_IFSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P8) >> PIO_IFSR_P8_Pos; +} + +static inline void hri_pio_write_IFSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P8; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P8; + } +} + +static inline void hri_pio_clear_IFSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P8; +} + +static inline void hri_pio_set_IFSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P9; +} + +static inline bool hri_pio_get_IFSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P9) >> PIO_IFSR_P9_Pos; +} + +static inline void hri_pio_write_IFSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P9; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P9; + } +} + +static inline void hri_pio_clear_IFSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P9; +} + +static inline void hri_pio_set_IFSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P10; +} + +static inline bool hri_pio_get_IFSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P10) >> PIO_IFSR_P10_Pos; +} + +static inline void hri_pio_write_IFSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P10; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P10; + } +} + +static inline void hri_pio_clear_IFSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P10; +} + +static inline void hri_pio_set_IFSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P11; +} + +static inline bool hri_pio_get_IFSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P11) >> PIO_IFSR_P11_Pos; +} + +static inline void hri_pio_write_IFSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P11; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P11; + } +} + +static inline void hri_pio_clear_IFSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P11; +} + +static inline void hri_pio_set_IFSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P12; +} + +static inline bool hri_pio_get_IFSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P12) >> PIO_IFSR_P12_Pos; +} + +static inline void hri_pio_write_IFSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P12; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P12; + } +} + +static inline void hri_pio_clear_IFSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P12; +} + +static inline void hri_pio_set_IFSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P13; +} + +static inline bool hri_pio_get_IFSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P13) >> PIO_IFSR_P13_Pos; +} + +static inline void hri_pio_write_IFSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P13; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P13; + } +} + +static inline void hri_pio_clear_IFSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P13; +} + +static inline void hri_pio_set_IFSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P14; +} + +static inline bool hri_pio_get_IFSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P14) >> PIO_IFSR_P14_Pos; +} + +static inline void hri_pio_write_IFSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P14; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P14; + } +} + +static inline void hri_pio_clear_IFSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P14; +} + +static inline void hri_pio_set_IFSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P15; +} + +static inline bool hri_pio_get_IFSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P15) >> PIO_IFSR_P15_Pos; +} + +static inline void hri_pio_write_IFSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P15; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P15; + } +} + +static inline void hri_pio_clear_IFSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P15; +} + +static inline void hri_pio_set_IFSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P16; +} + +static inline bool hri_pio_get_IFSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P16) >> PIO_IFSR_P16_Pos; +} + +static inline void hri_pio_write_IFSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P16; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P16; + } +} + +static inline void hri_pio_clear_IFSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P16; +} + +static inline void hri_pio_set_IFSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P17; +} + +static inline bool hri_pio_get_IFSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P17) >> PIO_IFSR_P17_Pos; +} + +static inline void hri_pio_write_IFSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P17; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P17; + } +} + +static inline void hri_pio_clear_IFSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P17; +} + +static inline void hri_pio_set_IFSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P18; +} + +static inline bool hri_pio_get_IFSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P18) >> PIO_IFSR_P18_Pos; +} + +static inline void hri_pio_write_IFSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P18; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P18; + } +} + +static inline void hri_pio_clear_IFSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P18; +} + +static inline void hri_pio_set_IFSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P19; +} + +static inline bool hri_pio_get_IFSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P19) >> PIO_IFSR_P19_Pos; +} + +static inline void hri_pio_write_IFSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P19; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P19; + } +} + +static inline void hri_pio_clear_IFSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P19; +} + +static inline void hri_pio_set_IFSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P20; +} + +static inline bool hri_pio_get_IFSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P20) >> PIO_IFSR_P20_Pos; +} + +static inline void hri_pio_write_IFSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P20; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P20; + } +} + +static inline void hri_pio_clear_IFSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P20; +} + +static inline void hri_pio_set_IFSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P21; +} + +static inline bool hri_pio_get_IFSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P21) >> PIO_IFSR_P21_Pos; +} + +static inline void hri_pio_write_IFSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P21; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P21; + } +} + +static inline void hri_pio_clear_IFSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P21; +} + +static inline void hri_pio_set_IFSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P22; +} + +static inline bool hri_pio_get_IFSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P22) >> PIO_IFSR_P22_Pos; +} + +static inline void hri_pio_write_IFSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P22; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P22; + } +} + +static inline void hri_pio_clear_IFSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P22; +} + +static inline void hri_pio_set_IFSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P23; +} + +static inline bool hri_pio_get_IFSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P23) >> PIO_IFSR_P23_Pos; +} + +static inline void hri_pio_write_IFSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P23; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P23; + } +} + +static inline void hri_pio_clear_IFSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P23; +} + +static inline void hri_pio_set_IFSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P24; +} + +static inline bool hri_pio_get_IFSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P24) >> PIO_IFSR_P24_Pos; +} + +static inline void hri_pio_write_IFSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P24; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P24; + } +} + +static inline void hri_pio_clear_IFSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P24; +} + +static inline void hri_pio_set_IFSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P25; +} + +static inline bool hri_pio_get_IFSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P25) >> PIO_IFSR_P25_Pos; +} + +static inline void hri_pio_write_IFSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P25; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P25; + } +} + +static inline void hri_pio_clear_IFSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P25; +} + +static inline void hri_pio_set_IFSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P26; +} + +static inline bool hri_pio_get_IFSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P26) >> PIO_IFSR_P26_Pos; +} + +static inline void hri_pio_write_IFSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P26; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P26; + } +} + +static inline void hri_pio_clear_IFSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P26; +} + +static inline void hri_pio_set_IFSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P27; +} + +static inline bool hri_pio_get_IFSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P27) >> PIO_IFSR_P27_Pos; +} + +static inline void hri_pio_write_IFSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P27; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P27; + } +} + +static inline void hri_pio_clear_IFSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P27; +} + +static inline void hri_pio_set_IFSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P28; +} + +static inline bool hri_pio_get_IFSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P28) >> PIO_IFSR_P28_Pos; +} + +static inline void hri_pio_write_IFSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P28; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P28; + } +} + +static inline void hri_pio_clear_IFSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P28; +} + +static inline void hri_pio_set_IFSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P29; +} + +static inline bool hri_pio_get_IFSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P29) >> PIO_IFSR_P29_Pos; +} + +static inline void hri_pio_write_IFSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P29; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P29; + } +} + +static inline void hri_pio_clear_IFSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P29; +} + +static inline void hri_pio_set_IFSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P30; +} + +static inline bool hri_pio_get_IFSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P30) >> PIO_IFSR_P30_Pos; +} + +static inline void hri_pio_write_IFSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P30; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P30; + } +} + +static inline void hri_pio_clear_IFSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P30; +} + +static inline void hri_pio_set_IFSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P31; +} + +static inline bool hri_pio_get_IFSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSR & PIO_IFSR_P31) >> PIO_IFSR_P31_Pos; +} + +static inline void hri_pio_write_IFSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P31; + } else { + ((Pio *)hw)->PIO_IFER = PIO_IFSR_P31; + } +} + +static inline void hri_pio_clear_IFSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFDR = PIO_IFSR_P31; +} + +static inline void hri_pio_set_IFSR_reg(const void *const hw, hri_pio_ifsr_reg_t mask) +{ + ((Pio *)hw)->PIO_IFER = mask; +} + +static inline hri_pio_ifsr_reg_t hri_pio_get_IFSR_reg(const void *const hw, hri_pio_ifsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_IFSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_ifsr_reg_t hri_pio_read_IFSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_IFSR; +} + +static inline void hri_pio_write_IFSR_reg(const void *const hw, hri_pio_ifsr_reg_t data) +{ + ((Pio *)hw)->PIO_IFER = data; + ((Pio *)hw)->PIO_IFDR = ~data; +} + +static inline void hri_pio_clear_IFSR_reg(const void *const hw, hri_pio_ifsr_reg_t mask) +{ + ((Pio *)hw)->PIO_IFDR = mask; +} + +static inline void hri_pio_set_ODSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P0; +} + +static inline bool hri_pio_get_ODSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P0) >> PIO_ODSR_P0_Pos; +} + +static inline void hri_pio_write_ODSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P0; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P0; + } +} + +static inline void hri_pio_clear_ODSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P0; +} + +static inline void hri_pio_set_ODSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P1; +} + +static inline bool hri_pio_get_ODSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P1) >> PIO_ODSR_P1_Pos; +} + +static inline void hri_pio_write_ODSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P1; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P1; + } +} + +static inline void hri_pio_clear_ODSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P1; +} + +static inline void hri_pio_set_ODSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P2; +} + +static inline bool hri_pio_get_ODSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P2) >> PIO_ODSR_P2_Pos; +} + +static inline void hri_pio_write_ODSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P2; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P2; + } +} + +static inline void hri_pio_clear_ODSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P2; +} + +static inline void hri_pio_set_ODSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P3; +} + +static inline bool hri_pio_get_ODSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P3) >> PIO_ODSR_P3_Pos; +} + +static inline void hri_pio_write_ODSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P3; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P3; + } +} + +static inline void hri_pio_clear_ODSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P3; +} + +static inline void hri_pio_set_ODSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P4; +} + +static inline bool hri_pio_get_ODSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P4) >> PIO_ODSR_P4_Pos; +} + +static inline void hri_pio_write_ODSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P4; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P4; + } +} + +static inline void hri_pio_clear_ODSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P4; +} + +static inline void hri_pio_set_ODSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P5; +} + +static inline bool hri_pio_get_ODSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P5) >> PIO_ODSR_P5_Pos; +} + +static inline void hri_pio_write_ODSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P5; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P5; + } +} + +static inline void hri_pio_clear_ODSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P5; +} + +static inline void hri_pio_set_ODSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P6; +} + +static inline bool hri_pio_get_ODSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P6) >> PIO_ODSR_P6_Pos; +} + +static inline void hri_pio_write_ODSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P6; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P6; + } +} + +static inline void hri_pio_clear_ODSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P6; +} + +static inline void hri_pio_set_ODSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P7; +} + +static inline bool hri_pio_get_ODSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P7) >> PIO_ODSR_P7_Pos; +} + +static inline void hri_pio_write_ODSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P7; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P7; + } +} + +static inline void hri_pio_clear_ODSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P7; +} + +static inline void hri_pio_set_ODSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P8; +} + +static inline bool hri_pio_get_ODSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P8) >> PIO_ODSR_P8_Pos; +} + +static inline void hri_pio_write_ODSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P8; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P8; + } +} + +static inline void hri_pio_clear_ODSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P8; +} + +static inline void hri_pio_set_ODSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P9; +} + +static inline bool hri_pio_get_ODSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P9) >> PIO_ODSR_P9_Pos; +} + +static inline void hri_pio_write_ODSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P9; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P9; + } +} + +static inline void hri_pio_clear_ODSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P9; +} + +static inline void hri_pio_set_ODSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P10; +} + +static inline bool hri_pio_get_ODSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P10) >> PIO_ODSR_P10_Pos; +} + +static inline void hri_pio_write_ODSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P10; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P10; + } +} + +static inline void hri_pio_clear_ODSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P10; +} + +static inline void hri_pio_set_ODSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P11; +} + +static inline bool hri_pio_get_ODSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P11) >> PIO_ODSR_P11_Pos; +} + +static inline void hri_pio_write_ODSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P11; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P11; + } +} + +static inline void hri_pio_clear_ODSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P11; +} + +static inline void hri_pio_set_ODSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P12; +} + +static inline bool hri_pio_get_ODSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P12) >> PIO_ODSR_P12_Pos; +} + +static inline void hri_pio_write_ODSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P12; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P12; + } +} + +static inline void hri_pio_clear_ODSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P12; +} + +static inline void hri_pio_set_ODSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P13; +} + +static inline bool hri_pio_get_ODSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P13) >> PIO_ODSR_P13_Pos; +} + +static inline void hri_pio_write_ODSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P13; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P13; + } +} + +static inline void hri_pio_clear_ODSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P13; +} + +static inline void hri_pio_set_ODSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P14; +} + +static inline bool hri_pio_get_ODSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P14) >> PIO_ODSR_P14_Pos; +} + +static inline void hri_pio_write_ODSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P14; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P14; + } +} + +static inline void hri_pio_clear_ODSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P14; +} + +static inline void hri_pio_set_ODSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P15; +} + +static inline bool hri_pio_get_ODSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P15) >> PIO_ODSR_P15_Pos; +} + +static inline void hri_pio_write_ODSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P15; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P15; + } +} + +static inline void hri_pio_clear_ODSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P15; +} + +static inline void hri_pio_set_ODSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P16; +} + +static inline bool hri_pio_get_ODSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P16) >> PIO_ODSR_P16_Pos; +} + +static inline void hri_pio_write_ODSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P16; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P16; + } +} + +static inline void hri_pio_clear_ODSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P16; +} + +static inline void hri_pio_set_ODSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P17; +} + +static inline bool hri_pio_get_ODSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P17) >> PIO_ODSR_P17_Pos; +} + +static inline void hri_pio_write_ODSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P17; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P17; + } +} + +static inline void hri_pio_clear_ODSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P17; +} + +static inline void hri_pio_set_ODSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P18; +} + +static inline bool hri_pio_get_ODSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P18) >> PIO_ODSR_P18_Pos; +} + +static inline void hri_pio_write_ODSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P18; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P18; + } +} + +static inline void hri_pio_clear_ODSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P18; +} + +static inline void hri_pio_set_ODSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P19; +} + +static inline bool hri_pio_get_ODSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P19) >> PIO_ODSR_P19_Pos; +} + +static inline void hri_pio_write_ODSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P19; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P19; + } +} + +static inline void hri_pio_clear_ODSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P19; +} + +static inline void hri_pio_set_ODSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P20; +} + +static inline bool hri_pio_get_ODSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P20) >> PIO_ODSR_P20_Pos; +} + +static inline void hri_pio_write_ODSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P20; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P20; + } +} + +static inline void hri_pio_clear_ODSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P20; +} + +static inline void hri_pio_set_ODSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P21; +} + +static inline bool hri_pio_get_ODSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P21) >> PIO_ODSR_P21_Pos; +} + +static inline void hri_pio_write_ODSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P21; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P21; + } +} + +static inline void hri_pio_clear_ODSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P21; +} + +static inline void hri_pio_set_ODSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P22; +} + +static inline bool hri_pio_get_ODSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P22) >> PIO_ODSR_P22_Pos; +} + +static inline void hri_pio_write_ODSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P22; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P22; + } +} + +static inline void hri_pio_clear_ODSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P22; +} + +static inline void hri_pio_set_ODSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P23; +} + +static inline bool hri_pio_get_ODSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P23) >> PIO_ODSR_P23_Pos; +} + +static inline void hri_pio_write_ODSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P23; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P23; + } +} + +static inline void hri_pio_clear_ODSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P23; +} + +static inline void hri_pio_set_ODSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P24; +} + +static inline bool hri_pio_get_ODSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P24) >> PIO_ODSR_P24_Pos; +} + +static inline void hri_pio_write_ODSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P24; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P24; + } +} + +static inline void hri_pio_clear_ODSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P24; +} + +static inline void hri_pio_set_ODSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P25; +} + +static inline bool hri_pio_get_ODSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P25) >> PIO_ODSR_P25_Pos; +} + +static inline void hri_pio_write_ODSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P25; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P25; + } +} + +static inline void hri_pio_clear_ODSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P25; +} + +static inline void hri_pio_set_ODSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P26; +} + +static inline bool hri_pio_get_ODSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P26) >> PIO_ODSR_P26_Pos; +} + +static inline void hri_pio_write_ODSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P26; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P26; + } +} + +static inline void hri_pio_clear_ODSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P26; +} + +static inline void hri_pio_set_ODSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P27; +} + +static inline bool hri_pio_get_ODSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P27) >> PIO_ODSR_P27_Pos; +} + +static inline void hri_pio_write_ODSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P27; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P27; + } +} + +static inline void hri_pio_clear_ODSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P27; +} + +static inline void hri_pio_set_ODSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P28; +} + +static inline bool hri_pio_get_ODSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P28) >> PIO_ODSR_P28_Pos; +} + +static inline void hri_pio_write_ODSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P28; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P28; + } +} + +static inline void hri_pio_clear_ODSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P28; +} + +static inline void hri_pio_set_ODSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P29; +} + +static inline bool hri_pio_get_ODSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P29) >> PIO_ODSR_P29_Pos; +} + +static inline void hri_pio_write_ODSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P29; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P29; + } +} + +static inline void hri_pio_clear_ODSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P29; +} + +static inline void hri_pio_set_ODSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P30; +} + +static inline bool hri_pio_get_ODSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P30) >> PIO_ODSR_P30_Pos; +} + +static inline void hri_pio_write_ODSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P30; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P30; + } +} + +static inline void hri_pio_clear_ODSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P30; +} + +static inline void hri_pio_set_ODSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P31; +} + +static inline bool hri_pio_get_ODSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ODSR & PIO_ODSR_P31) >> PIO_ODSR_P31_Pos; +} + +static inline void hri_pio_write_ODSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P31; + } else { + ((Pio *)hw)->PIO_SODR = PIO_ODSR_P31; + } +} + +static inline void hri_pio_clear_ODSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_CODR = PIO_ODSR_P31; +} + +static inline void hri_pio_set_ODSR_reg(const void *const hw, hri_pio_odsr_reg_t mask) +{ + ((Pio *)hw)->PIO_SODR = mask; +} + +static inline hri_pio_odsr_reg_t hri_pio_get_ODSR_reg(const void *const hw, hri_pio_odsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ODSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_odsr_reg_t hri_pio_read_ODSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_ODSR; +} + +static inline void hri_pio_write_ODSR_reg(const void *const hw, hri_pio_odsr_reg_t data) +{ + ((Pio *)hw)->PIO_SODR = data; + ((Pio *)hw)->PIO_CODR = ~data; +} + +static inline void hri_pio_clear_ODSR_reg(const void *const hw, hri_pio_odsr_reg_t mask) +{ + ((Pio *)hw)->PIO_CODR = mask; +} + +static inline void hri_pio_set_IMR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P0; +} + +static inline bool hri_pio_get_IMR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P0) >> PIO_IMR_P0_Pos; +} + +static inline void hri_pio_write_IMR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P0; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P0; + } +} + +static inline void hri_pio_clear_IMR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P0; +} + +static inline void hri_pio_set_IMR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P1; +} + +static inline bool hri_pio_get_IMR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P1) >> PIO_IMR_P1_Pos; +} + +static inline void hri_pio_write_IMR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P1; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P1; + } +} + +static inline void hri_pio_clear_IMR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P1; +} + +static inline void hri_pio_set_IMR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P2; +} + +static inline bool hri_pio_get_IMR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P2) >> PIO_IMR_P2_Pos; +} + +static inline void hri_pio_write_IMR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P2; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P2; + } +} + +static inline void hri_pio_clear_IMR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P2; +} + +static inline void hri_pio_set_IMR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P3; +} + +static inline bool hri_pio_get_IMR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P3) >> PIO_IMR_P3_Pos; +} + +static inline void hri_pio_write_IMR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P3; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P3; + } +} + +static inline void hri_pio_clear_IMR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P3; +} + +static inline void hri_pio_set_IMR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P4; +} + +static inline bool hri_pio_get_IMR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P4) >> PIO_IMR_P4_Pos; +} + +static inline void hri_pio_write_IMR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P4; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P4; + } +} + +static inline void hri_pio_clear_IMR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P4; +} + +static inline void hri_pio_set_IMR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P5; +} + +static inline bool hri_pio_get_IMR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P5) >> PIO_IMR_P5_Pos; +} + +static inline void hri_pio_write_IMR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P5; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P5; + } +} + +static inline void hri_pio_clear_IMR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P5; +} + +static inline void hri_pio_set_IMR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P6; +} + +static inline bool hri_pio_get_IMR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P6) >> PIO_IMR_P6_Pos; +} + +static inline void hri_pio_write_IMR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P6; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P6; + } +} + +static inline void hri_pio_clear_IMR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P6; +} + +static inline void hri_pio_set_IMR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P7; +} + +static inline bool hri_pio_get_IMR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P7) >> PIO_IMR_P7_Pos; +} + +static inline void hri_pio_write_IMR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P7; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P7; + } +} + +static inline void hri_pio_clear_IMR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P7; +} + +static inline void hri_pio_set_IMR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P8; +} + +static inline bool hri_pio_get_IMR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P8) >> PIO_IMR_P8_Pos; +} + +static inline void hri_pio_write_IMR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P8; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P8; + } +} + +static inline void hri_pio_clear_IMR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P8; +} + +static inline void hri_pio_set_IMR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P9; +} + +static inline bool hri_pio_get_IMR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P9) >> PIO_IMR_P9_Pos; +} + +static inline void hri_pio_write_IMR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P9; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P9; + } +} + +static inline void hri_pio_clear_IMR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P9; +} + +static inline void hri_pio_set_IMR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P10; +} + +static inline bool hri_pio_get_IMR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P10) >> PIO_IMR_P10_Pos; +} + +static inline void hri_pio_write_IMR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P10; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P10; + } +} + +static inline void hri_pio_clear_IMR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P10; +} + +static inline void hri_pio_set_IMR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P11; +} + +static inline bool hri_pio_get_IMR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P11) >> PIO_IMR_P11_Pos; +} + +static inline void hri_pio_write_IMR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P11; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P11; + } +} + +static inline void hri_pio_clear_IMR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P11; +} + +static inline void hri_pio_set_IMR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P12; +} + +static inline bool hri_pio_get_IMR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P12) >> PIO_IMR_P12_Pos; +} + +static inline void hri_pio_write_IMR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P12; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P12; + } +} + +static inline void hri_pio_clear_IMR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P12; +} + +static inline void hri_pio_set_IMR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P13; +} + +static inline bool hri_pio_get_IMR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P13) >> PIO_IMR_P13_Pos; +} + +static inline void hri_pio_write_IMR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P13; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P13; + } +} + +static inline void hri_pio_clear_IMR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P13; +} + +static inline void hri_pio_set_IMR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P14; +} + +static inline bool hri_pio_get_IMR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P14) >> PIO_IMR_P14_Pos; +} + +static inline void hri_pio_write_IMR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P14; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P14; + } +} + +static inline void hri_pio_clear_IMR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P14; +} + +static inline void hri_pio_set_IMR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P15; +} + +static inline bool hri_pio_get_IMR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P15) >> PIO_IMR_P15_Pos; +} + +static inline void hri_pio_write_IMR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P15; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P15; + } +} + +static inline void hri_pio_clear_IMR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P15; +} + +static inline void hri_pio_set_IMR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P16; +} + +static inline bool hri_pio_get_IMR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P16) >> PIO_IMR_P16_Pos; +} + +static inline void hri_pio_write_IMR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P16; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P16; + } +} + +static inline void hri_pio_clear_IMR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P16; +} + +static inline void hri_pio_set_IMR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P17; +} + +static inline bool hri_pio_get_IMR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P17) >> PIO_IMR_P17_Pos; +} + +static inline void hri_pio_write_IMR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P17; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P17; + } +} + +static inline void hri_pio_clear_IMR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P17; +} + +static inline void hri_pio_set_IMR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P18; +} + +static inline bool hri_pio_get_IMR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P18) >> PIO_IMR_P18_Pos; +} + +static inline void hri_pio_write_IMR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P18; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P18; + } +} + +static inline void hri_pio_clear_IMR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P18; +} + +static inline void hri_pio_set_IMR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P19; +} + +static inline bool hri_pio_get_IMR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P19) >> PIO_IMR_P19_Pos; +} + +static inline void hri_pio_write_IMR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P19; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P19; + } +} + +static inline void hri_pio_clear_IMR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P19; +} + +static inline void hri_pio_set_IMR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P20; +} + +static inline bool hri_pio_get_IMR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P20) >> PIO_IMR_P20_Pos; +} + +static inline void hri_pio_write_IMR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P20; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P20; + } +} + +static inline void hri_pio_clear_IMR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P20; +} + +static inline void hri_pio_set_IMR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P21; +} + +static inline bool hri_pio_get_IMR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P21) >> PIO_IMR_P21_Pos; +} + +static inline void hri_pio_write_IMR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P21; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P21; + } +} + +static inline void hri_pio_clear_IMR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P21; +} + +static inline void hri_pio_set_IMR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P22; +} + +static inline bool hri_pio_get_IMR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P22) >> PIO_IMR_P22_Pos; +} + +static inline void hri_pio_write_IMR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P22; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P22; + } +} + +static inline void hri_pio_clear_IMR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P22; +} + +static inline void hri_pio_set_IMR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P23; +} + +static inline bool hri_pio_get_IMR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P23) >> PIO_IMR_P23_Pos; +} + +static inline void hri_pio_write_IMR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P23; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P23; + } +} + +static inline void hri_pio_clear_IMR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P23; +} + +static inline void hri_pio_set_IMR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P24; +} + +static inline bool hri_pio_get_IMR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P24) >> PIO_IMR_P24_Pos; +} + +static inline void hri_pio_write_IMR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P24; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P24; + } +} + +static inline void hri_pio_clear_IMR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P24; +} + +static inline void hri_pio_set_IMR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P25; +} + +static inline bool hri_pio_get_IMR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P25) >> PIO_IMR_P25_Pos; +} + +static inline void hri_pio_write_IMR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P25; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P25; + } +} + +static inline void hri_pio_clear_IMR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P25; +} + +static inline void hri_pio_set_IMR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P26; +} + +static inline bool hri_pio_get_IMR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P26) >> PIO_IMR_P26_Pos; +} + +static inline void hri_pio_write_IMR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P26; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P26; + } +} + +static inline void hri_pio_clear_IMR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P26; +} + +static inline void hri_pio_set_IMR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P27; +} + +static inline bool hri_pio_get_IMR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P27) >> PIO_IMR_P27_Pos; +} + +static inline void hri_pio_write_IMR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P27; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P27; + } +} + +static inline void hri_pio_clear_IMR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P27; +} + +static inline void hri_pio_set_IMR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P28; +} + +static inline bool hri_pio_get_IMR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P28) >> PIO_IMR_P28_Pos; +} + +static inline void hri_pio_write_IMR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P28; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P28; + } +} + +static inline void hri_pio_clear_IMR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P28; +} + +static inline void hri_pio_set_IMR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P29; +} + +static inline bool hri_pio_get_IMR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P29) >> PIO_IMR_P29_Pos; +} + +static inline void hri_pio_write_IMR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P29; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P29; + } +} + +static inline void hri_pio_clear_IMR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P29; +} + +static inline void hri_pio_set_IMR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P30; +} + +static inline bool hri_pio_get_IMR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P30) >> PIO_IMR_P30_Pos; +} + +static inline void hri_pio_write_IMR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P30; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P30; + } +} + +static inline void hri_pio_clear_IMR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P30; +} + +static inline void hri_pio_set_IMR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IER = PIO_IMR_P31; +} + +static inline bool hri_pio_get_IMR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IMR & PIO_IMR_P31) >> PIO_IMR_P31_Pos; +} + +static inline void hri_pio_write_IMR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IDR = PIO_IMR_P31; + } else { + ((Pio *)hw)->PIO_IER = PIO_IMR_P31; + } +} + +static inline void hri_pio_clear_IMR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IDR = PIO_IMR_P31; +} + +static inline void hri_pio_set_IMR_reg(const void *const hw, hri_pio_imr_reg_t mask) +{ + ((Pio *)hw)->PIO_IER = mask; +} + +static inline hri_pio_imr_reg_t hri_pio_get_IMR_reg(const void *const hw, hri_pio_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_imr_reg_t hri_pio_read_IMR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_IMR; +} + +static inline void hri_pio_write_IMR_reg(const void *const hw, hri_pio_imr_reg_t data) +{ + ((Pio *)hw)->PIO_IER = data; + ((Pio *)hw)->PIO_IDR = ~data; +} + +static inline void hri_pio_clear_IMR_reg(const void *const hw, hri_pio_imr_reg_t mask) +{ + ((Pio *)hw)->PIO_IDR = mask; +} + +static inline void hri_pio_set_MDSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P0; +} + +static inline bool hri_pio_get_MDSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P0) >> PIO_MDSR_P0_Pos; +} + +static inline void hri_pio_write_MDSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P0; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P0; + } +} + +static inline void hri_pio_clear_MDSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P0; +} + +static inline void hri_pio_set_MDSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P1; +} + +static inline bool hri_pio_get_MDSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P1) >> PIO_MDSR_P1_Pos; +} + +static inline void hri_pio_write_MDSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P1; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P1; + } +} + +static inline void hri_pio_clear_MDSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P1; +} + +static inline void hri_pio_set_MDSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P2; +} + +static inline bool hri_pio_get_MDSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P2) >> PIO_MDSR_P2_Pos; +} + +static inline void hri_pio_write_MDSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P2; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P2; + } +} + +static inline void hri_pio_clear_MDSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P2; +} + +static inline void hri_pio_set_MDSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P3; +} + +static inline bool hri_pio_get_MDSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P3) >> PIO_MDSR_P3_Pos; +} + +static inline void hri_pio_write_MDSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P3; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P3; + } +} + +static inline void hri_pio_clear_MDSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P3; +} + +static inline void hri_pio_set_MDSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P4; +} + +static inline bool hri_pio_get_MDSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P4) >> PIO_MDSR_P4_Pos; +} + +static inline void hri_pio_write_MDSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P4; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P4; + } +} + +static inline void hri_pio_clear_MDSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P4; +} + +static inline void hri_pio_set_MDSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P5; +} + +static inline bool hri_pio_get_MDSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P5) >> PIO_MDSR_P5_Pos; +} + +static inline void hri_pio_write_MDSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P5; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P5; + } +} + +static inline void hri_pio_clear_MDSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P5; +} + +static inline void hri_pio_set_MDSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P6; +} + +static inline bool hri_pio_get_MDSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P6) >> PIO_MDSR_P6_Pos; +} + +static inline void hri_pio_write_MDSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P6; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P6; + } +} + +static inline void hri_pio_clear_MDSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P6; +} + +static inline void hri_pio_set_MDSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P7; +} + +static inline bool hri_pio_get_MDSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P7) >> PIO_MDSR_P7_Pos; +} + +static inline void hri_pio_write_MDSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P7; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P7; + } +} + +static inline void hri_pio_clear_MDSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P7; +} + +static inline void hri_pio_set_MDSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P8; +} + +static inline bool hri_pio_get_MDSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P8) >> PIO_MDSR_P8_Pos; +} + +static inline void hri_pio_write_MDSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P8; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P8; + } +} + +static inline void hri_pio_clear_MDSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P8; +} + +static inline void hri_pio_set_MDSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P9; +} + +static inline bool hri_pio_get_MDSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P9) >> PIO_MDSR_P9_Pos; +} + +static inline void hri_pio_write_MDSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P9; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P9; + } +} + +static inline void hri_pio_clear_MDSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P9; +} + +static inline void hri_pio_set_MDSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P10; +} + +static inline bool hri_pio_get_MDSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P10) >> PIO_MDSR_P10_Pos; +} + +static inline void hri_pio_write_MDSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P10; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P10; + } +} + +static inline void hri_pio_clear_MDSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P10; +} + +static inline void hri_pio_set_MDSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P11; +} + +static inline bool hri_pio_get_MDSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P11) >> PIO_MDSR_P11_Pos; +} + +static inline void hri_pio_write_MDSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P11; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P11; + } +} + +static inline void hri_pio_clear_MDSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P11; +} + +static inline void hri_pio_set_MDSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P12; +} + +static inline bool hri_pio_get_MDSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P12) >> PIO_MDSR_P12_Pos; +} + +static inline void hri_pio_write_MDSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P12; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P12; + } +} + +static inline void hri_pio_clear_MDSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P12; +} + +static inline void hri_pio_set_MDSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P13; +} + +static inline bool hri_pio_get_MDSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P13) >> PIO_MDSR_P13_Pos; +} + +static inline void hri_pio_write_MDSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P13; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P13; + } +} + +static inline void hri_pio_clear_MDSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P13; +} + +static inline void hri_pio_set_MDSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P14; +} + +static inline bool hri_pio_get_MDSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P14) >> PIO_MDSR_P14_Pos; +} + +static inline void hri_pio_write_MDSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P14; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P14; + } +} + +static inline void hri_pio_clear_MDSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P14; +} + +static inline void hri_pio_set_MDSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P15; +} + +static inline bool hri_pio_get_MDSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P15) >> PIO_MDSR_P15_Pos; +} + +static inline void hri_pio_write_MDSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P15; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P15; + } +} + +static inline void hri_pio_clear_MDSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P15; +} + +static inline void hri_pio_set_MDSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P16; +} + +static inline bool hri_pio_get_MDSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P16) >> PIO_MDSR_P16_Pos; +} + +static inline void hri_pio_write_MDSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P16; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P16; + } +} + +static inline void hri_pio_clear_MDSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P16; +} + +static inline void hri_pio_set_MDSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P17; +} + +static inline bool hri_pio_get_MDSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P17) >> PIO_MDSR_P17_Pos; +} + +static inline void hri_pio_write_MDSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P17; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P17; + } +} + +static inline void hri_pio_clear_MDSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P17; +} + +static inline void hri_pio_set_MDSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P18; +} + +static inline bool hri_pio_get_MDSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P18) >> PIO_MDSR_P18_Pos; +} + +static inline void hri_pio_write_MDSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P18; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P18; + } +} + +static inline void hri_pio_clear_MDSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P18; +} + +static inline void hri_pio_set_MDSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P19; +} + +static inline bool hri_pio_get_MDSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P19) >> PIO_MDSR_P19_Pos; +} + +static inline void hri_pio_write_MDSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P19; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P19; + } +} + +static inline void hri_pio_clear_MDSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P19; +} + +static inline void hri_pio_set_MDSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P20; +} + +static inline bool hri_pio_get_MDSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P20) >> PIO_MDSR_P20_Pos; +} + +static inline void hri_pio_write_MDSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P20; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P20; + } +} + +static inline void hri_pio_clear_MDSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P20; +} + +static inline void hri_pio_set_MDSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P21; +} + +static inline bool hri_pio_get_MDSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P21) >> PIO_MDSR_P21_Pos; +} + +static inline void hri_pio_write_MDSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P21; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P21; + } +} + +static inline void hri_pio_clear_MDSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P21; +} + +static inline void hri_pio_set_MDSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P22; +} + +static inline bool hri_pio_get_MDSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P22) >> PIO_MDSR_P22_Pos; +} + +static inline void hri_pio_write_MDSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P22; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P22; + } +} + +static inline void hri_pio_clear_MDSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P22; +} + +static inline void hri_pio_set_MDSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P23; +} + +static inline bool hri_pio_get_MDSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P23) >> PIO_MDSR_P23_Pos; +} + +static inline void hri_pio_write_MDSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P23; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P23; + } +} + +static inline void hri_pio_clear_MDSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P23; +} + +static inline void hri_pio_set_MDSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P24; +} + +static inline bool hri_pio_get_MDSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P24) >> PIO_MDSR_P24_Pos; +} + +static inline void hri_pio_write_MDSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P24; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P24; + } +} + +static inline void hri_pio_clear_MDSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P24; +} + +static inline void hri_pio_set_MDSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P25; +} + +static inline bool hri_pio_get_MDSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P25) >> PIO_MDSR_P25_Pos; +} + +static inline void hri_pio_write_MDSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P25; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P25; + } +} + +static inline void hri_pio_clear_MDSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P25; +} + +static inline void hri_pio_set_MDSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P26; +} + +static inline bool hri_pio_get_MDSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P26) >> PIO_MDSR_P26_Pos; +} + +static inline void hri_pio_write_MDSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P26; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P26; + } +} + +static inline void hri_pio_clear_MDSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P26; +} + +static inline void hri_pio_set_MDSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P27; +} + +static inline bool hri_pio_get_MDSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P27) >> PIO_MDSR_P27_Pos; +} + +static inline void hri_pio_write_MDSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P27; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P27; + } +} + +static inline void hri_pio_clear_MDSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P27; +} + +static inline void hri_pio_set_MDSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P28; +} + +static inline bool hri_pio_get_MDSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P28) >> PIO_MDSR_P28_Pos; +} + +static inline void hri_pio_write_MDSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P28; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P28; + } +} + +static inline void hri_pio_clear_MDSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P28; +} + +static inline void hri_pio_set_MDSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P29; +} + +static inline bool hri_pio_get_MDSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P29) >> PIO_MDSR_P29_Pos; +} + +static inline void hri_pio_write_MDSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P29; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P29; + } +} + +static inline void hri_pio_clear_MDSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P29; +} + +static inline void hri_pio_set_MDSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P30; +} + +static inline bool hri_pio_get_MDSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P30) >> PIO_MDSR_P30_Pos; +} + +static inline void hri_pio_write_MDSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P30; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P30; + } +} + +static inline void hri_pio_clear_MDSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P30; +} + +static inline void hri_pio_set_MDSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P31; +} + +static inline bool hri_pio_get_MDSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_MDSR & PIO_MDSR_P31) >> PIO_MDSR_P31_Pos; +} + +static inline void hri_pio_write_MDSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P31; + } else { + ((Pio *)hw)->PIO_MDER = PIO_MDSR_P31; + } +} + +static inline void hri_pio_clear_MDSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_MDDR = PIO_MDSR_P31; +} + +static inline void hri_pio_set_MDSR_reg(const void *const hw, hri_pio_mdsr_reg_t mask) +{ + ((Pio *)hw)->PIO_MDER = mask; +} + +static inline hri_pio_mdsr_reg_t hri_pio_get_MDSR_reg(const void *const hw, hri_pio_mdsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_MDSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_mdsr_reg_t hri_pio_read_MDSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_MDSR; +} + +static inline void hri_pio_write_MDSR_reg(const void *const hw, hri_pio_mdsr_reg_t data) +{ + ((Pio *)hw)->PIO_MDER = data; + ((Pio *)hw)->PIO_MDDR = ~data; +} + +static inline void hri_pio_clear_MDSR_reg(const void *const hw, hri_pio_mdsr_reg_t mask) +{ + ((Pio *)hw)->PIO_MDDR = mask; +} + +static inline void hri_pio_set_PUSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P0; +} + +static inline bool hri_pio_get_PUSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P0) >> PIO_PUSR_P0_Pos; +} + +static inline void hri_pio_write_PUSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P0; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P0; + } +} + +static inline void hri_pio_clear_PUSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P0; +} + +static inline void hri_pio_set_PUSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P1; +} + +static inline bool hri_pio_get_PUSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P1) >> PIO_PUSR_P1_Pos; +} + +static inline void hri_pio_write_PUSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P1; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P1; + } +} + +static inline void hri_pio_clear_PUSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P1; +} + +static inline void hri_pio_set_PUSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P2; +} + +static inline bool hri_pio_get_PUSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P2) >> PIO_PUSR_P2_Pos; +} + +static inline void hri_pio_write_PUSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P2; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P2; + } +} + +static inline void hri_pio_clear_PUSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P2; +} + +static inline void hri_pio_set_PUSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P3; +} + +static inline bool hri_pio_get_PUSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P3) >> PIO_PUSR_P3_Pos; +} + +static inline void hri_pio_write_PUSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P3; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P3; + } +} + +static inline void hri_pio_clear_PUSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P3; +} + +static inline void hri_pio_set_PUSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P4; +} + +static inline bool hri_pio_get_PUSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P4) >> PIO_PUSR_P4_Pos; +} + +static inline void hri_pio_write_PUSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P4; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P4; + } +} + +static inline void hri_pio_clear_PUSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P4; +} + +static inline void hri_pio_set_PUSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P5; +} + +static inline bool hri_pio_get_PUSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P5) >> PIO_PUSR_P5_Pos; +} + +static inline void hri_pio_write_PUSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P5; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P5; + } +} + +static inline void hri_pio_clear_PUSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P5; +} + +static inline void hri_pio_set_PUSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P6; +} + +static inline bool hri_pio_get_PUSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P6) >> PIO_PUSR_P6_Pos; +} + +static inline void hri_pio_write_PUSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P6; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P6; + } +} + +static inline void hri_pio_clear_PUSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P6; +} + +static inline void hri_pio_set_PUSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P7; +} + +static inline bool hri_pio_get_PUSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P7) >> PIO_PUSR_P7_Pos; +} + +static inline void hri_pio_write_PUSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P7; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P7; + } +} + +static inline void hri_pio_clear_PUSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P7; +} + +static inline void hri_pio_set_PUSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P8; +} + +static inline bool hri_pio_get_PUSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P8) >> PIO_PUSR_P8_Pos; +} + +static inline void hri_pio_write_PUSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P8; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P8; + } +} + +static inline void hri_pio_clear_PUSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P8; +} + +static inline void hri_pio_set_PUSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P9; +} + +static inline bool hri_pio_get_PUSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P9) >> PIO_PUSR_P9_Pos; +} + +static inline void hri_pio_write_PUSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P9; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P9; + } +} + +static inline void hri_pio_clear_PUSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P9; +} + +static inline void hri_pio_set_PUSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P10; +} + +static inline bool hri_pio_get_PUSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P10) >> PIO_PUSR_P10_Pos; +} + +static inline void hri_pio_write_PUSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P10; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P10; + } +} + +static inline void hri_pio_clear_PUSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P10; +} + +static inline void hri_pio_set_PUSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P11; +} + +static inline bool hri_pio_get_PUSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P11) >> PIO_PUSR_P11_Pos; +} + +static inline void hri_pio_write_PUSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P11; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P11; + } +} + +static inline void hri_pio_clear_PUSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P11; +} + +static inline void hri_pio_set_PUSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P12; +} + +static inline bool hri_pio_get_PUSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P12) >> PIO_PUSR_P12_Pos; +} + +static inline void hri_pio_write_PUSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P12; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P12; + } +} + +static inline void hri_pio_clear_PUSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P12; +} + +static inline void hri_pio_set_PUSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P13; +} + +static inline bool hri_pio_get_PUSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P13) >> PIO_PUSR_P13_Pos; +} + +static inline void hri_pio_write_PUSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P13; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P13; + } +} + +static inline void hri_pio_clear_PUSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P13; +} + +static inline void hri_pio_set_PUSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P14; +} + +static inline bool hri_pio_get_PUSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P14) >> PIO_PUSR_P14_Pos; +} + +static inline void hri_pio_write_PUSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P14; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P14; + } +} + +static inline void hri_pio_clear_PUSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P14; +} + +static inline void hri_pio_set_PUSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P15; +} + +static inline bool hri_pio_get_PUSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P15) >> PIO_PUSR_P15_Pos; +} + +static inline void hri_pio_write_PUSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P15; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P15; + } +} + +static inline void hri_pio_clear_PUSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P15; +} + +static inline void hri_pio_set_PUSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P16; +} + +static inline bool hri_pio_get_PUSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P16) >> PIO_PUSR_P16_Pos; +} + +static inline void hri_pio_write_PUSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P16; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P16; + } +} + +static inline void hri_pio_clear_PUSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P16; +} + +static inline void hri_pio_set_PUSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P17; +} + +static inline bool hri_pio_get_PUSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P17) >> PIO_PUSR_P17_Pos; +} + +static inline void hri_pio_write_PUSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P17; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P17; + } +} + +static inline void hri_pio_clear_PUSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P17; +} + +static inline void hri_pio_set_PUSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P18; +} + +static inline bool hri_pio_get_PUSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P18) >> PIO_PUSR_P18_Pos; +} + +static inline void hri_pio_write_PUSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P18; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P18; + } +} + +static inline void hri_pio_clear_PUSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P18; +} + +static inline void hri_pio_set_PUSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P19; +} + +static inline bool hri_pio_get_PUSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P19) >> PIO_PUSR_P19_Pos; +} + +static inline void hri_pio_write_PUSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P19; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P19; + } +} + +static inline void hri_pio_clear_PUSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P19; +} + +static inline void hri_pio_set_PUSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P20; +} + +static inline bool hri_pio_get_PUSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P20) >> PIO_PUSR_P20_Pos; +} + +static inline void hri_pio_write_PUSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P20; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P20; + } +} + +static inline void hri_pio_clear_PUSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P20; +} + +static inline void hri_pio_set_PUSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P21; +} + +static inline bool hri_pio_get_PUSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P21) >> PIO_PUSR_P21_Pos; +} + +static inline void hri_pio_write_PUSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P21; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P21; + } +} + +static inline void hri_pio_clear_PUSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P21; +} + +static inline void hri_pio_set_PUSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P22; +} + +static inline bool hri_pio_get_PUSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P22) >> PIO_PUSR_P22_Pos; +} + +static inline void hri_pio_write_PUSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P22; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P22; + } +} + +static inline void hri_pio_clear_PUSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P22; +} + +static inline void hri_pio_set_PUSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P23; +} + +static inline bool hri_pio_get_PUSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P23) >> PIO_PUSR_P23_Pos; +} + +static inline void hri_pio_write_PUSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P23; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P23; + } +} + +static inline void hri_pio_clear_PUSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P23; +} + +static inline void hri_pio_set_PUSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P24; +} + +static inline bool hri_pio_get_PUSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P24) >> PIO_PUSR_P24_Pos; +} + +static inline void hri_pio_write_PUSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P24; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P24; + } +} + +static inline void hri_pio_clear_PUSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P24; +} + +static inline void hri_pio_set_PUSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P25; +} + +static inline bool hri_pio_get_PUSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P25) >> PIO_PUSR_P25_Pos; +} + +static inline void hri_pio_write_PUSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P25; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P25; + } +} + +static inline void hri_pio_clear_PUSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P25; +} + +static inline void hri_pio_set_PUSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P26; +} + +static inline bool hri_pio_get_PUSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P26) >> PIO_PUSR_P26_Pos; +} + +static inline void hri_pio_write_PUSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P26; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P26; + } +} + +static inline void hri_pio_clear_PUSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P26; +} + +static inline void hri_pio_set_PUSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P27; +} + +static inline bool hri_pio_get_PUSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P27) >> PIO_PUSR_P27_Pos; +} + +static inline void hri_pio_write_PUSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P27; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P27; + } +} + +static inline void hri_pio_clear_PUSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P27; +} + +static inline void hri_pio_set_PUSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P28; +} + +static inline bool hri_pio_get_PUSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P28) >> PIO_PUSR_P28_Pos; +} + +static inline void hri_pio_write_PUSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P28; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P28; + } +} + +static inline void hri_pio_clear_PUSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P28; +} + +static inline void hri_pio_set_PUSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P29; +} + +static inline bool hri_pio_get_PUSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P29) >> PIO_PUSR_P29_Pos; +} + +static inline void hri_pio_write_PUSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P29; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P29; + } +} + +static inline void hri_pio_clear_PUSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P29; +} + +static inline void hri_pio_set_PUSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P30; +} + +static inline bool hri_pio_get_PUSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P30) >> PIO_PUSR_P30_Pos; +} + +static inline void hri_pio_write_PUSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P30; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P30; + } +} + +static inline void hri_pio_clear_PUSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P30; +} + +static inline void hri_pio_set_PUSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P31; +} + +static inline bool hri_pio_get_PUSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PUSR & PIO_PUSR_P31) >> PIO_PUSR_P31_Pos; +} + +static inline void hri_pio_write_PUSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P31; + } else { + ((Pio *)hw)->PIO_PUER = PIO_PUSR_P31; + } +} + +static inline void hri_pio_clear_PUSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PUDR = PIO_PUSR_P31; +} + +static inline void hri_pio_set_PUSR_reg(const void *const hw, hri_pio_pusr_reg_t mask) +{ + ((Pio *)hw)->PIO_PUER = mask; +} + +static inline hri_pio_pusr_reg_t hri_pio_get_PUSR_reg(const void *const hw, hri_pio_pusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PUSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_pusr_reg_t hri_pio_read_PUSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PUSR; +} + +static inline void hri_pio_write_PUSR_reg(const void *const hw, hri_pio_pusr_reg_t data) +{ + ((Pio *)hw)->PIO_PUER = data; + ((Pio *)hw)->PIO_PUDR = ~data; +} + +static inline void hri_pio_clear_PUSR_reg(const void *const hw, hri_pio_pusr_reg_t mask) +{ + ((Pio *)hw)->PIO_PUDR = mask; +} + +static inline void hri_pio_set_IFSCSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P0; +} + +static inline bool hri_pio_get_IFSCSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P0) >> PIO_IFSCSR_P0_Pos; +} + +static inline void hri_pio_write_IFSCSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P0; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P0; + } +} + +static inline void hri_pio_clear_IFSCSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P0; +} + +static inline void hri_pio_set_IFSCSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P1; +} + +static inline bool hri_pio_get_IFSCSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P1) >> PIO_IFSCSR_P1_Pos; +} + +static inline void hri_pio_write_IFSCSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P1; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P1; + } +} + +static inline void hri_pio_clear_IFSCSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P1; +} + +static inline void hri_pio_set_IFSCSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P2; +} + +static inline bool hri_pio_get_IFSCSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P2) >> PIO_IFSCSR_P2_Pos; +} + +static inline void hri_pio_write_IFSCSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P2; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P2; + } +} + +static inline void hri_pio_clear_IFSCSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P2; +} + +static inline void hri_pio_set_IFSCSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P3; +} + +static inline bool hri_pio_get_IFSCSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P3) >> PIO_IFSCSR_P3_Pos; +} + +static inline void hri_pio_write_IFSCSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P3; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P3; + } +} + +static inline void hri_pio_clear_IFSCSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P3; +} + +static inline void hri_pio_set_IFSCSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P4; +} + +static inline bool hri_pio_get_IFSCSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P4) >> PIO_IFSCSR_P4_Pos; +} + +static inline void hri_pio_write_IFSCSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P4; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P4; + } +} + +static inline void hri_pio_clear_IFSCSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P4; +} + +static inline void hri_pio_set_IFSCSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P5; +} + +static inline bool hri_pio_get_IFSCSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P5) >> PIO_IFSCSR_P5_Pos; +} + +static inline void hri_pio_write_IFSCSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P5; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P5; + } +} + +static inline void hri_pio_clear_IFSCSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P5; +} + +static inline void hri_pio_set_IFSCSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P6; +} + +static inline bool hri_pio_get_IFSCSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P6) >> PIO_IFSCSR_P6_Pos; +} + +static inline void hri_pio_write_IFSCSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P6; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P6; + } +} + +static inline void hri_pio_clear_IFSCSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P6; +} + +static inline void hri_pio_set_IFSCSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P7; +} + +static inline bool hri_pio_get_IFSCSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P7) >> PIO_IFSCSR_P7_Pos; +} + +static inline void hri_pio_write_IFSCSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P7; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P7; + } +} + +static inline void hri_pio_clear_IFSCSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P7; +} + +static inline void hri_pio_set_IFSCSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P8; +} + +static inline bool hri_pio_get_IFSCSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P8) >> PIO_IFSCSR_P8_Pos; +} + +static inline void hri_pio_write_IFSCSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P8; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P8; + } +} + +static inline void hri_pio_clear_IFSCSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P8; +} + +static inline void hri_pio_set_IFSCSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P9; +} + +static inline bool hri_pio_get_IFSCSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P9) >> PIO_IFSCSR_P9_Pos; +} + +static inline void hri_pio_write_IFSCSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P9; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P9; + } +} + +static inline void hri_pio_clear_IFSCSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P9; +} + +static inline void hri_pio_set_IFSCSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P10; +} + +static inline bool hri_pio_get_IFSCSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P10) >> PIO_IFSCSR_P10_Pos; +} + +static inline void hri_pio_write_IFSCSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P10; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P10; + } +} + +static inline void hri_pio_clear_IFSCSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P10; +} + +static inline void hri_pio_set_IFSCSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P11; +} + +static inline bool hri_pio_get_IFSCSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P11) >> PIO_IFSCSR_P11_Pos; +} + +static inline void hri_pio_write_IFSCSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P11; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P11; + } +} + +static inline void hri_pio_clear_IFSCSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P11; +} + +static inline void hri_pio_set_IFSCSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P12; +} + +static inline bool hri_pio_get_IFSCSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P12) >> PIO_IFSCSR_P12_Pos; +} + +static inline void hri_pio_write_IFSCSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P12; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P12; + } +} + +static inline void hri_pio_clear_IFSCSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P12; +} + +static inline void hri_pio_set_IFSCSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P13; +} + +static inline bool hri_pio_get_IFSCSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P13) >> PIO_IFSCSR_P13_Pos; +} + +static inline void hri_pio_write_IFSCSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P13; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P13; + } +} + +static inline void hri_pio_clear_IFSCSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P13; +} + +static inline void hri_pio_set_IFSCSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P14; +} + +static inline bool hri_pio_get_IFSCSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P14) >> PIO_IFSCSR_P14_Pos; +} + +static inline void hri_pio_write_IFSCSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P14; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P14; + } +} + +static inline void hri_pio_clear_IFSCSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P14; +} + +static inline void hri_pio_set_IFSCSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P15; +} + +static inline bool hri_pio_get_IFSCSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P15) >> PIO_IFSCSR_P15_Pos; +} + +static inline void hri_pio_write_IFSCSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P15; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P15; + } +} + +static inline void hri_pio_clear_IFSCSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P15; +} + +static inline void hri_pio_set_IFSCSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P16; +} + +static inline bool hri_pio_get_IFSCSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P16) >> PIO_IFSCSR_P16_Pos; +} + +static inline void hri_pio_write_IFSCSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P16; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P16; + } +} + +static inline void hri_pio_clear_IFSCSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P16; +} + +static inline void hri_pio_set_IFSCSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P17; +} + +static inline bool hri_pio_get_IFSCSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P17) >> PIO_IFSCSR_P17_Pos; +} + +static inline void hri_pio_write_IFSCSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P17; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P17; + } +} + +static inline void hri_pio_clear_IFSCSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P17; +} + +static inline void hri_pio_set_IFSCSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P18; +} + +static inline bool hri_pio_get_IFSCSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P18) >> PIO_IFSCSR_P18_Pos; +} + +static inline void hri_pio_write_IFSCSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P18; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P18; + } +} + +static inline void hri_pio_clear_IFSCSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P18; +} + +static inline void hri_pio_set_IFSCSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P19; +} + +static inline bool hri_pio_get_IFSCSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P19) >> PIO_IFSCSR_P19_Pos; +} + +static inline void hri_pio_write_IFSCSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P19; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P19; + } +} + +static inline void hri_pio_clear_IFSCSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P19; +} + +static inline void hri_pio_set_IFSCSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P20; +} + +static inline bool hri_pio_get_IFSCSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P20) >> PIO_IFSCSR_P20_Pos; +} + +static inline void hri_pio_write_IFSCSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P20; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P20; + } +} + +static inline void hri_pio_clear_IFSCSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P20; +} + +static inline void hri_pio_set_IFSCSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P21; +} + +static inline bool hri_pio_get_IFSCSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P21) >> PIO_IFSCSR_P21_Pos; +} + +static inline void hri_pio_write_IFSCSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P21; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P21; + } +} + +static inline void hri_pio_clear_IFSCSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P21; +} + +static inline void hri_pio_set_IFSCSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P22; +} + +static inline bool hri_pio_get_IFSCSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P22) >> PIO_IFSCSR_P22_Pos; +} + +static inline void hri_pio_write_IFSCSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P22; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P22; + } +} + +static inline void hri_pio_clear_IFSCSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P22; +} + +static inline void hri_pio_set_IFSCSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P23; +} + +static inline bool hri_pio_get_IFSCSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P23) >> PIO_IFSCSR_P23_Pos; +} + +static inline void hri_pio_write_IFSCSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P23; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P23; + } +} + +static inline void hri_pio_clear_IFSCSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P23; +} + +static inline void hri_pio_set_IFSCSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P24; +} + +static inline bool hri_pio_get_IFSCSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P24) >> PIO_IFSCSR_P24_Pos; +} + +static inline void hri_pio_write_IFSCSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P24; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P24; + } +} + +static inline void hri_pio_clear_IFSCSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P24; +} + +static inline void hri_pio_set_IFSCSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P25; +} + +static inline bool hri_pio_get_IFSCSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P25) >> PIO_IFSCSR_P25_Pos; +} + +static inline void hri_pio_write_IFSCSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P25; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P25; + } +} + +static inline void hri_pio_clear_IFSCSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P25; +} + +static inline void hri_pio_set_IFSCSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P26; +} + +static inline bool hri_pio_get_IFSCSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P26) >> PIO_IFSCSR_P26_Pos; +} + +static inline void hri_pio_write_IFSCSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P26; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P26; + } +} + +static inline void hri_pio_clear_IFSCSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P26; +} + +static inline void hri_pio_set_IFSCSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P27; +} + +static inline bool hri_pio_get_IFSCSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P27) >> PIO_IFSCSR_P27_Pos; +} + +static inline void hri_pio_write_IFSCSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P27; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P27; + } +} + +static inline void hri_pio_clear_IFSCSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P27; +} + +static inline void hri_pio_set_IFSCSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P28; +} + +static inline bool hri_pio_get_IFSCSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P28) >> PIO_IFSCSR_P28_Pos; +} + +static inline void hri_pio_write_IFSCSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P28; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P28; + } +} + +static inline void hri_pio_clear_IFSCSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P28; +} + +static inline void hri_pio_set_IFSCSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P29; +} + +static inline bool hri_pio_get_IFSCSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P29) >> PIO_IFSCSR_P29_Pos; +} + +static inline void hri_pio_write_IFSCSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P29; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P29; + } +} + +static inline void hri_pio_clear_IFSCSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P29; +} + +static inline void hri_pio_set_IFSCSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P30; +} + +static inline bool hri_pio_get_IFSCSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P30) >> PIO_IFSCSR_P30_Pos; +} + +static inline void hri_pio_write_IFSCSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P30; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P30; + } +} + +static inline void hri_pio_clear_IFSCSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P30; +} + +static inline void hri_pio_set_IFSCSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P31; +} + +static inline bool hri_pio_get_IFSCSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_IFSCSR & PIO_IFSCSR_P31) >> PIO_IFSCSR_P31_Pos; +} + +static inline void hri_pio_write_IFSCSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P31; + } else { + ((Pio *)hw)->PIO_IFSCER = PIO_IFSCSR_P31; + } +} + +static inline void hri_pio_clear_IFSCSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_IFSCDR = PIO_IFSCSR_P31; +} + +static inline void hri_pio_set_IFSCSR_reg(const void *const hw, hri_pio_ifscsr_reg_t mask) +{ + ((Pio *)hw)->PIO_IFSCER = mask; +} + +static inline hri_pio_ifscsr_reg_t hri_pio_get_IFSCSR_reg(const void *const hw, hri_pio_ifscsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_IFSCSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_ifscsr_reg_t hri_pio_read_IFSCSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_IFSCSR; +} + +static inline void hri_pio_write_IFSCSR_reg(const void *const hw, hri_pio_ifscsr_reg_t data) +{ + ((Pio *)hw)->PIO_IFSCER = data; + ((Pio *)hw)->PIO_IFSCDR = ~data; +} + +static inline void hri_pio_clear_IFSCSR_reg(const void *const hw, hri_pio_ifscsr_reg_t mask) +{ + ((Pio *)hw)->PIO_IFSCDR = mask; +} + +static inline void hri_pio_set_PPDSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P0; +} + +static inline bool hri_pio_get_PPDSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P0) >> PIO_PPDSR_P0_Pos; +} + +static inline void hri_pio_write_PPDSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P0; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P0; + } +} + +static inline void hri_pio_clear_PPDSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P0; +} + +static inline void hri_pio_set_PPDSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P1; +} + +static inline bool hri_pio_get_PPDSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P1) >> PIO_PPDSR_P1_Pos; +} + +static inline void hri_pio_write_PPDSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P1; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P1; + } +} + +static inline void hri_pio_clear_PPDSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P1; +} + +static inline void hri_pio_set_PPDSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P2; +} + +static inline bool hri_pio_get_PPDSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P2) >> PIO_PPDSR_P2_Pos; +} + +static inline void hri_pio_write_PPDSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P2; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P2; + } +} + +static inline void hri_pio_clear_PPDSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P2; +} + +static inline void hri_pio_set_PPDSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P3; +} + +static inline bool hri_pio_get_PPDSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P3) >> PIO_PPDSR_P3_Pos; +} + +static inline void hri_pio_write_PPDSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P3; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P3; + } +} + +static inline void hri_pio_clear_PPDSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P3; +} + +static inline void hri_pio_set_PPDSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P4; +} + +static inline bool hri_pio_get_PPDSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P4) >> PIO_PPDSR_P4_Pos; +} + +static inline void hri_pio_write_PPDSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P4; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P4; + } +} + +static inline void hri_pio_clear_PPDSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P4; +} + +static inline void hri_pio_set_PPDSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P5; +} + +static inline bool hri_pio_get_PPDSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P5) >> PIO_PPDSR_P5_Pos; +} + +static inline void hri_pio_write_PPDSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P5; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P5; + } +} + +static inline void hri_pio_clear_PPDSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P5; +} + +static inline void hri_pio_set_PPDSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P6; +} + +static inline bool hri_pio_get_PPDSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P6) >> PIO_PPDSR_P6_Pos; +} + +static inline void hri_pio_write_PPDSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P6; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P6; + } +} + +static inline void hri_pio_clear_PPDSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P6; +} + +static inline void hri_pio_set_PPDSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P7; +} + +static inline bool hri_pio_get_PPDSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P7) >> PIO_PPDSR_P7_Pos; +} + +static inline void hri_pio_write_PPDSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P7; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P7; + } +} + +static inline void hri_pio_clear_PPDSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P7; +} + +static inline void hri_pio_set_PPDSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P8; +} + +static inline bool hri_pio_get_PPDSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P8) >> PIO_PPDSR_P8_Pos; +} + +static inline void hri_pio_write_PPDSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P8; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P8; + } +} + +static inline void hri_pio_clear_PPDSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P8; +} + +static inline void hri_pio_set_PPDSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P9; +} + +static inline bool hri_pio_get_PPDSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P9) >> PIO_PPDSR_P9_Pos; +} + +static inline void hri_pio_write_PPDSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P9; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P9; + } +} + +static inline void hri_pio_clear_PPDSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P9; +} + +static inline void hri_pio_set_PPDSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P10; +} + +static inline bool hri_pio_get_PPDSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P10) >> PIO_PPDSR_P10_Pos; +} + +static inline void hri_pio_write_PPDSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P10; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P10; + } +} + +static inline void hri_pio_clear_PPDSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P10; +} + +static inline void hri_pio_set_PPDSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P11; +} + +static inline bool hri_pio_get_PPDSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P11) >> PIO_PPDSR_P11_Pos; +} + +static inline void hri_pio_write_PPDSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P11; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P11; + } +} + +static inline void hri_pio_clear_PPDSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P11; +} + +static inline void hri_pio_set_PPDSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P12; +} + +static inline bool hri_pio_get_PPDSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P12) >> PIO_PPDSR_P12_Pos; +} + +static inline void hri_pio_write_PPDSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P12; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P12; + } +} + +static inline void hri_pio_clear_PPDSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P12; +} + +static inline void hri_pio_set_PPDSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P13; +} + +static inline bool hri_pio_get_PPDSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P13) >> PIO_PPDSR_P13_Pos; +} + +static inline void hri_pio_write_PPDSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P13; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P13; + } +} + +static inline void hri_pio_clear_PPDSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P13; +} + +static inline void hri_pio_set_PPDSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P14; +} + +static inline bool hri_pio_get_PPDSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P14) >> PIO_PPDSR_P14_Pos; +} + +static inline void hri_pio_write_PPDSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P14; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P14; + } +} + +static inline void hri_pio_clear_PPDSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P14; +} + +static inline void hri_pio_set_PPDSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P15; +} + +static inline bool hri_pio_get_PPDSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P15) >> PIO_PPDSR_P15_Pos; +} + +static inline void hri_pio_write_PPDSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P15; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P15; + } +} + +static inline void hri_pio_clear_PPDSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P15; +} + +static inline void hri_pio_set_PPDSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P16; +} + +static inline bool hri_pio_get_PPDSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P16) >> PIO_PPDSR_P16_Pos; +} + +static inline void hri_pio_write_PPDSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P16; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P16; + } +} + +static inline void hri_pio_clear_PPDSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P16; +} + +static inline void hri_pio_set_PPDSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P17; +} + +static inline bool hri_pio_get_PPDSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P17) >> PIO_PPDSR_P17_Pos; +} + +static inline void hri_pio_write_PPDSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P17; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P17; + } +} + +static inline void hri_pio_clear_PPDSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P17; +} + +static inline void hri_pio_set_PPDSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P18; +} + +static inline bool hri_pio_get_PPDSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P18) >> PIO_PPDSR_P18_Pos; +} + +static inline void hri_pio_write_PPDSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P18; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P18; + } +} + +static inline void hri_pio_clear_PPDSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P18; +} + +static inline void hri_pio_set_PPDSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P19; +} + +static inline bool hri_pio_get_PPDSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P19) >> PIO_PPDSR_P19_Pos; +} + +static inline void hri_pio_write_PPDSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P19; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P19; + } +} + +static inline void hri_pio_clear_PPDSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P19; +} + +static inline void hri_pio_set_PPDSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P20; +} + +static inline bool hri_pio_get_PPDSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P20) >> PIO_PPDSR_P20_Pos; +} + +static inline void hri_pio_write_PPDSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P20; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P20; + } +} + +static inline void hri_pio_clear_PPDSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P20; +} + +static inline void hri_pio_set_PPDSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P21; +} + +static inline bool hri_pio_get_PPDSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P21) >> PIO_PPDSR_P21_Pos; +} + +static inline void hri_pio_write_PPDSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P21; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P21; + } +} + +static inline void hri_pio_clear_PPDSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P21; +} + +static inline void hri_pio_set_PPDSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P22; +} + +static inline bool hri_pio_get_PPDSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P22) >> PIO_PPDSR_P22_Pos; +} + +static inline void hri_pio_write_PPDSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P22; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P22; + } +} + +static inline void hri_pio_clear_PPDSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P22; +} + +static inline void hri_pio_set_PPDSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P23; +} + +static inline bool hri_pio_get_PPDSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P23) >> PIO_PPDSR_P23_Pos; +} + +static inline void hri_pio_write_PPDSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P23; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P23; + } +} + +static inline void hri_pio_clear_PPDSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P23; +} + +static inline void hri_pio_set_PPDSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P24; +} + +static inline bool hri_pio_get_PPDSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P24) >> PIO_PPDSR_P24_Pos; +} + +static inline void hri_pio_write_PPDSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P24; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P24; + } +} + +static inline void hri_pio_clear_PPDSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P24; +} + +static inline void hri_pio_set_PPDSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P25; +} + +static inline bool hri_pio_get_PPDSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P25) >> PIO_PPDSR_P25_Pos; +} + +static inline void hri_pio_write_PPDSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P25; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P25; + } +} + +static inline void hri_pio_clear_PPDSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P25; +} + +static inline void hri_pio_set_PPDSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P26; +} + +static inline bool hri_pio_get_PPDSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P26) >> PIO_PPDSR_P26_Pos; +} + +static inline void hri_pio_write_PPDSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P26; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P26; + } +} + +static inline void hri_pio_clear_PPDSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P26; +} + +static inline void hri_pio_set_PPDSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P27; +} + +static inline bool hri_pio_get_PPDSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P27) >> PIO_PPDSR_P27_Pos; +} + +static inline void hri_pio_write_PPDSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P27; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P27; + } +} + +static inline void hri_pio_clear_PPDSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P27; +} + +static inline void hri_pio_set_PPDSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P28; +} + +static inline bool hri_pio_get_PPDSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P28) >> PIO_PPDSR_P28_Pos; +} + +static inline void hri_pio_write_PPDSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P28; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P28; + } +} + +static inline void hri_pio_clear_PPDSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P28; +} + +static inline void hri_pio_set_PPDSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P29; +} + +static inline bool hri_pio_get_PPDSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P29) >> PIO_PPDSR_P29_Pos; +} + +static inline void hri_pio_write_PPDSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P29; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P29; + } +} + +static inline void hri_pio_clear_PPDSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P29; +} + +static inline void hri_pio_set_PPDSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P30; +} + +static inline bool hri_pio_get_PPDSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P30) >> PIO_PPDSR_P30_Pos; +} + +static inline void hri_pio_write_PPDSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P30; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P30; + } +} + +static inline void hri_pio_clear_PPDSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P30; +} + +static inline void hri_pio_set_PPDSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P31; +} + +static inline bool hri_pio_get_PPDSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PPDSR & PIO_PPDSR_P31) >> PIO_PPDSR_P31_Pos; +} + +static inline void hri_pio_write_PPDSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P31; + } else { + ((Pio *)hw)->PIO_PPDER = PIO_PPDSR_P31; + } +} + +static inline void hri_pio_clear_PPDSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_PPDDR = PIO_PPDSR_P31; +} + +static inline void hri_pio_set_PPDSR_reg(const void *const hw, hri_pio_ppdsr_reg_t mask) +{ + ((Pio *)hw)->PIO_PPDER = mask; +} + +static inline hri_pio_ppdsr_reg_t hri_pio_get_PPDSR_reg(const void *const hw, hri_pio_ppdsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PPDSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_ppdsr_reg_t hri_pio_read_PPDSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PPDSR; +} + +static inline void hri_pio_write_PPDSR_reg(const void *const hw, hri_pio_ppdsr_reg_t data) +{ + ((Pio *)hw)->PIO_PPDER = data; + ((Pio *)hw)->PIO_PPDDR = ~data; +} + +static inline void hri_pio_clear_PPDSR_reg(const void *const hw, hri_pio_ppdsr_reg_t mask) +{ + ((Pio *)hw)->PIO_PPDDR = mask; +} + +static inline void hri_pio_set_OWSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P0; +} + +static inline bool hri_pio_get_OWSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P0) >> PIO_OWSR_P0_Pos; +} + +static inline void hri_pio_write_OWSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P0; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P0; + } +} + +static inline void hri_pio_clear_OWSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P0; +} + +static inline void hri_pio_set_OWSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P1; +} + +static inline bool hri_pio_get_OWSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P1) >> PIO_OWSR_P1_Pos; +} + +static inline void hri_pio_write_OWSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P1; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P1; + } +} + +static inline void hri_pio_clear_OWSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P1; +} + +static inline void hri_pio_set_OWSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P2; +} + +static inline bool hri_pio_get_OWSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P2) >> PIO_OWSR_P2_Pos; +} + +static inline void hri_pio_write_OWSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P2; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P2; + } +} + +static inline void hri_pio_clear_OWSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P2; +} + +static inline void hri_pio_set_OWSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P3; +} + +static inline bool hri_pio_get_OWSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P3) >> PIO_OWSR_P3_Pos; +} + +static inline void hri_pio_write_OWSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P3; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P3; + } +} + +static inline void hri_pio_clear_OWSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P3; +} + +static inline void hri_pio_set_OWSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P4; +} + +static inline bool hri_pio_get_OWSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P4) >> PIO_OWSR_P4_Pos; +} + +static inline void hri_pio_write_OWSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P4; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P4; + } +} + +static inline void hri_pio_clear_OWSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P4; +} + +static inline void hri_pio_set_OWSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P5; +} + +static inline bool hri_pio_get_OWSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P5) >> PIO_OWSR_P5_Pos; +} + +static inline void hri_pio_write_OWSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P5; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P5; + } +} + +static inline void hri_pio_clear_OWSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P5; +} + +static inline void hri_pio_set_OWSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P6; +} + +static inline bool hri_pio_get_OWSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P6) >> PIO_OWSR_P6_Pos; +} + +static inline void hri_pio_write_OWSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P6; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P6; + } +} + +static inline void hri_pio_clear_OWSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P6; +} + +static inline void hri_pio_set_OWSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P7; +} + +static inline bool hri_pio_get_OWSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P7) >> PIO_OWSR_P7_Pos; +} + +static inline void hri_pio_write_OWSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P7; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P7; + } +} + +static inline void hri_pio_clear_OWSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P7; +} + +static inline void hri_pio_set_OWSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P8; +} + +static inline bool hri_pio_get_OWSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P8) >> PIO_OWSR_P8_Pos; +} + +static inline void hri_pio_write_OWSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P8; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P8; + } +} + +static inline void hri_pio_clear_OWSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P8; +} + +static inline void hri_pio_set_OWSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P9; +} + +static inline bool hri_pio_get_OWSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P9) >> PIO_OWSR_P9_Pos; +} + +static inline void hri_pio_write_OWSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P9; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P9; + } +} + +static inline void hri_pio_clear_OWSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P9; +} + +static inline void hri_pio_set_OWSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P10; +} + +static inline bool hri_pio_get_OWSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P10) >> PIO_OWSR_P10_Pos; +} + +static inline void hri_pio_write_OWSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P10; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P10; + } +} + +static inline void hri_pio_clear_OWSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P10; +} + +static inline void hri_pio_set_OWSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P11; +} + +static inline bool hri_pio_get_OWSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P11) >> PIO_OWSR_P11_Pos; +} + +static inline void hri_pio_write_OWSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P11; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P11; + } +} + +static inline void hri_pio_clear_OWSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P11; +} + +static inline void hri_pio_set_OWSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P12; +} + +static inline bool hri_pio_get_OWSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P12) >> PIO_OWSR_P12_Pos; +} + +static inline void hri_pio_write_OWSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P12; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P12; + } +} + +static inline void hri_pio_clear_OWSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P12; +} + +static inline void hri_pio_set_OWSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P13; +} + +static inline bool hri_pio_get_OWSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P13) >> PIO_OWSR_P13_Pos; +} + +static inline void hri_pio_write_OWSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P13; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P13; + } +} + +static inline void hri_pio_clear_OWSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P13; +} + +static inline void hri_pio_set_OWSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P14; +} + +static inline bool hri_pio_get_OWSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P14) >> PIO_OWSR_P14_Pos; +} + +static inline void hri_pio_write_OWSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P14; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P14; + } +} + +static inline void hri_pio_clear_OWSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P14; +} + +static inline void hri_pio_set_OWSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P15; +} + +static inline bool hri_pio_get_OWSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P15) >> PIO_OWSR_P15_Pos; +} + +static inline void hri_pio_write_OWSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P15; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P15; + } +} + +static inline void hri_pio_clear_OWSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P15; +} + +static inline void hri_pio_set_OWSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P16; +} + +static inline bool hri_pio_get_OWSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P16) >> PIO_OWSR_P16_Pos; +} + +static inline void hri_pio_write_OWSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P16; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P16; + } +} + +static inline void hri_pio_clear_OWSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P16; +} + +static inline void hri_pio_set_OWSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P17; +} + +static inline bool hri_pio_get_OWSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P17) >> PIO_OWSR_P17_Pos; +} + +static inline void hri_pio_write_OWSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P17; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P17; + } +} + +static inline void hri_pio_clear_OWSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P17; +} + +static inline void hri_pio_set_OWSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P18; +} + +static inline bool hri_pio_get_OWSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P18) >> PIO_OWSR_P18_Pos; +} + +static inline void hri_pio_write_OWSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P18; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P18; + } +} + +static inline void hri_pio_clear_OWSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P18; +} + +static inline void hri_pio_set_OWSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P19; +} + +static inline bool hri_pio_get_OWSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P19) >> PIO_OWSR_P19_Pos; +} + +static inline void hri_pio_write_OWSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P19; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P19; + } +} + +static inline void hri_pio_clear_OWSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P19; +} + +static inline void hri_pio_set_OWSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P20; +} + +static inline bool hri_pio_get_OWSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P20) >> PIO_OWSR_P20_Pos; +} + +static inline void hri_pio_write_OWSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P20; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P20; + } +} + +static inline void hri_pio_clear_OWSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P20; +} + +static inline void hri_pio_set_OWSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P21; +} + +static inline bool hri_pio_get_OWSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P21) >> PIO_OWSR_P21_Pos; +} + +static inline void hri_pio_write_OWSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P21; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P21; + } +} + +static inline void hri_pio_clear_OWSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P21; +} + +static inline void hri_pio_set_OWSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P22; +} + +static inline bool hri_pio_get_OWSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P22) >> PIO_OWSR_P22_Pos; +} + +static inline void hri_pio_write_OWSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P22; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P22; + } +} + +static inline void hri_pio_clear_OWSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P22; +} + +static inline void hri_pio_set_OWSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P23; +} + +static inline bool hri_pio_get_OWSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P23) >> PIO_OWSR_P23_Pos; +} + +static inline void hri_pio_write_OWSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P23; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P23; + } +} + +static inline void hri_pio_clear_OWSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P23; +} + +static inline void hri_pio_set_OWSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P24; +} + +static inline bool hri_pio_get_OWSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P24) >> PIO_OWSR_P24_Pos; +} + +static inline void hri_pio_write_OWSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P24; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P24; + } +} + +static inline void hri_pio_clear_OWSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P24; +} + +static inline void hri_pio_set_OWSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P25; +} + +static inline bool hri_pio_get_OWSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P25) >> PIO_OWSR_P25_Pos; +} + +static inline void hri_pio_write_OWSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P25; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P25; + } +} + +static inline void hri_pio_clear_OWSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P25; +} + +static inline void hri_pio_set_OWSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P26; +} + +static inline bool hri_pio_get_OWSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P26) >> PIO_OWSR_P26_Pos; +} + +static inline void hri_pio_write_OWSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P26; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P26; + } +} + +static inline void hri_pio_clear_OWSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P26; +} + +static inline void hri_pio_set_OWSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P27; +} + +static inline bool hri_pio_get_OWSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P27) >> PIO_OWSR_P27_Pos; +} + +static inline void hri_pio_write_OWSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P27; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P27; + } +} + +static inline void hri_pio_clear_OWSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P27; +} + +static inline void hri_pio_set_OWSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P28; +} + +static inline bool hri_pio_get_OWSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P28) >> PIO_OWSR_P28_Pos; +} + +static inline void hri_pio_write_OWSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P28; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P28; + } +} + +static inline void hri_pio_clear_OWSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P28; +} + +static inline void hri_pio_set_OWSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P29; +} + +static inline bool hri_pio_get_OWSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P29) >> PIO_OWSR_P29_Pos; +} + +static inline void hri_pio_write_OWSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P29; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P29; + } +} + +static inline void hri_pio_clear_OWSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P29; +} + +static inline void hri_pio_set_OWSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P30; +} + +static inline bool hri_pio_get_OWSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P30) >> PIO_OWSR_P30_Pos; +} + +static inline void hri_pio_write_OWSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P30; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P30; + } +} + +static inline void hri_pio_clear_OWSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P30; +} + +static inline void hri_pio_set_OWSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P31; +} + +static inline bool hri_pio_get_OWSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_OWSR & PIO_OWSR_P31) >> PIO_OWSR_P31_Pos; +} + +static inline void hri_pio_write_OWSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P31; + } else { + ((Pio *)hw)->PIO_OWER = PIO_OWSR_P31; + } +} + +static inline void hri_pio_clear_OWSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_OWDR = PIO_OWSR_P31; +} + +static inline void hri_pio_set_OWSR_reg(const void *const hw, hri_pio_owsr_reg_t mask) +{ + ((Pio *)hw)->PIO_OWER = mask; +} + +static inline hri_pio_owsr_reg_t hri_pio_get_OWSR_reg(const void *const hw, hri_pio_owsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_OWSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_owsr_reg_t hri_pio_read_OWSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_OWSR; +} + +static inline void hri_pio_write_OWSR_reg(const void *const hw, hri_pio_owsr_reg_t data) +{ + ((Pio *)hw)->PIO_OWER = data; + ((Pio *)hw)->PIO_OWDR = ~data; +} + +static inline void hri_pio_clear_OWSR_reg(const void *const hw, hri_pio_owsr_reg_t mask) +{ + ((Pio *)hw)->PIO_OWDR = mask; +} + +static inline void hri_pio_set_AIMMR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P0; +} + +static inline bool hri_pio_get_AIMMR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P0) >> PIO_AIMMR_P0_Pos; +} + +static inline void hri_pio_write_AIMMR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P0; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P0; + } +} + +static inline void hri_pio_clear_AIMMR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P0; +} + +static inline void hri_pio_set_AIMMR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P1; +} + +static inline bool hri_pio_get_AIMMR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P1) >> PIO_AIMMR_P1_Pos; +} + +static inline void hri_pio_write_AIMMR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P1; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P1; + } +} + +static inline void hri_pio_clear_AIMMR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P1; +} + +static inline void hri_pio_set_AIMMR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P2; +} + +static inline bool hri_pio_get_AIMMR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P2) >> PIO_AIMMR_P2_Pos; +} + +static inline void hri_pio_write_AIMMR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P2; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P2; + } +} + +static inline void hri_pio_clear_AIMMR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P2; +} + +static inline void hri_pio_set_AIMMR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P3; +} + +static inline bool hri_pio_get_AIMMR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P3) >> PIO_AIMMR_P3_Pos; +} + +static inline void hri_pio_write_AIMMR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P3; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P3; + } +} + +static inline void hri_pio_clear_AIMMR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P3; +} + +static inline void hri_pio_set_AIMMR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P4; +} + +static inline bool hri_pio_get_AIMMR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P4) >> PIO_AIMMR_P4_Pos; +} + +static inline void hri_pio_write_AIMMR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P4; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P4; + } +} + +static inline void hri_pio_clear_AIMMR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P4; +} + +static inline void hri_pio_set_AIMMR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P5; +} + +static inline bool hri_pio_get_AIMMR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P5) >> PIO_AIMMR_P5_Pos; +} + +static inline void hri_pio_write_AIMMR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P5; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P5; + } +} + +static inline void hri_pio_clear_AIMMR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P5; +} + +static inline void hri_pio_set_AIMMR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P6; +} + +static inline bool hri_pio_get_AIMMR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P6) >> PIO_AIMMR_P6_Pos; +} + +static inline void hri_pio_write_AIMMR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P6; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P6; + } +} + +static inline void hri_pio_clear_AIMMR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P6; +} + +static inline void hri_pio_set_AIMMR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P7; +} + +static inline bool hri_pio_get_AIMMR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P7) >> PIO_AIMMR_P7_Pos; +} + +static inline void hri_pio_write_AIMMR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P7; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P7; + } +} + +static inline void hri_pio_clear_AIMMR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P7; +} + +static inline void hri_pio_set_AIMMR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P8; +} + +static inline bool hri_pio_get_AIMMR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P8) >> PIO_AIMMR_P8_Pos; +} + +static inline void hri_pio_write_AIMMR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P8; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P8; + } +} + +static inline void hri_pio_clear_AIMMR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P8; +} + +static inline void hri_pio_set_AIMMR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P9; +} + +static inline bool hri_pio_get_AIMMR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P9) >> PIO_AIMMR_P9_Pos; +} + +static inline void hri_pio_write_AIMMR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P9; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P9; + } +} + +static inline void hri_pio_clear_AIMMR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P9; +} + +static inline void hri_pio_set_AIMMR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P10; +} + +static inline bool hri_pio_get_AIMMR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P10) >> PIO_AIMMR_P10_Pos; +} + +static inline void hri_pio_write_AIMMR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P10; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P10; + } +} + +static inline void hri_pio_clear_AIMMR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P10; +} + +static inline void hri_pio_set_AIMMR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P11; +} + +static inline bool hri_pio_get_AIMMR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P11) >> PIO_AIMMR_P11_Pos; +} + +static inline void hri_pio_write_AIMMR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P11; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P11; + } +} + +static inline void hri_pio_clear_AIMMR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P11; +} + +static inline void hri_pio_set_AIMMR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P12; +} + +static inline bool hri_pio_get_AIMMR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P12) >> PIO_AIMMR_P12_Pos; +} + +static inline void hri_pio_write_AIMMR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P12; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P12; + } +} + +static inline void hri_pio_clear_AIMMR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P12; +} + +static inline void hri_pio_set_AIMMR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P13; +} + +static inline bool hri_pio_get_AIMMR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P13) >> PIO_AIMMR_P13_Pos; +} + +static inline void hri_pio_write_AIMMR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P13; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P13; + } +} + +static inline void hri_pio_clear_AIMMR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P13; +} + +static inline void hri_pio_set_AIMMR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P14; +} + +static inline bool hri_pio_get_AIMMR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P14) >> PIO_AIMMR_P14_Pos; +} + +static inline void hri_pio_write_AIMMR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P14; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P14; + } +} + +static inline void hri_pio_clear_AIMMR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P14; +} + +static inline void hri_pio_set_AIMMR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P15; +} + +static inline bool hri_pio_get_AIMMR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P15) >> PIO_AIMMR_P15_Pos; +} + +static inline void hri_pio_write_AIMMR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P15; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P15; + } +} + +static inline void hri_pio_clear_AIMMR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P15; +} + +static inline void hri_pio_set_AIMMR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P16; +} + +static inline bool hri_pio_get_AIMMR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P16) >> PIO_AIMMR_P16_Pos; +} + +static inline void hri_pio_write_AIMMR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P16; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P16; + } +} + +static inline void hri_pio_clear_AIMMR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P16; +} + +static inline void hri_pio_set_AIMMR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P17; +} + +static inline bool hri_pio_get_AIMMR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P17) >> PIO_AIMMR_P17_Pos; +} + +static inline void hri_pio_write_AIMMR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P17; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P17; + } +} + +static inline void hri_pio_clear_AIMMR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P17; +} + +static inline void hri_pio_set_AIMMR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P18; +} + +static inline bool hri_pio_get_AIMMR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P18) >> PIO_AIMMR_P18_Pos; +} + +static inline void hri_pio_write_AIMMR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P18; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P18; + } +} + +static inline void hri_pio_clear_AIMMR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P18; +} + +static inline void hri_pio_set_AIMMR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P19; +} + +static inline bool hri_pio_get_AIMMR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P19) >> PIO_AIMMR_P19_Pos; +} + +static inline void hri_pio_write_AIMMR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P19; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P19; + } +} + +static inline void hri_pio_clear_AIMMR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P19; +} + +static inline void hri_pio_set_AIMMR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P20; +} + +static inline bool hri_pio_get_AIMMR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P20) >> PIO_AIMMR_P20_Pos; +} + +static inline void hri_pio_write_AIMMR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P20; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P20; + } +} + +static inline void hri_pio_clear_AIMMR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P20; +} + +static inline void hri_pio_set_AIMMR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P21; +} + +static inline bool hri_pio_get_AIMMR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P21) >> PIO_AIMMR_P21_Pos; +} + +static inline void hri_pio_write_AIMMR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P21; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P21; + } +} + +static inline void hri_pio_clear_AIMMR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P21; +} + +static inline void hri_pio_set_AIMMR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P22; +} + +static inline bool hri_pio_get_AIMMR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P22) >> PIO_AIMMR_P22_Pos; +} + +static inline void hri_pio_write_AIMMR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P22; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P22; + } +} + +static inline void hri_pio_clear_AIMMR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P22; +} + +static inline void hri_pio_set_AIMMR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P23; +} + +static inline bool hri_pio_get_AIMMR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P23) >> PIO_AIMMR_P23_Pos; +} + +static inline void hri_pio_write_AIMMR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P23; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P23; + } +} + +static inline void hri_pio_clear_AIMMR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P23; +} + +static inline void hri_pio_set_AIMMR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P24; +} + +static inline bool hri_pio_get_AIMMR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P24) >> PIO_AIMMR_P24_Pos; +} + +static inline void hri_pio_write_AIMMR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P24; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P24; + } +} + +static inline void hri_pio_clear_AIMMR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P24; +} + +static inline void hri_pio_set_AIMMR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P25; +} + +static inline bool hri_pio_get_AIMMR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P25) >> PIO_AIMMR_P25_Pos; +} + +static inline void hri_pio_write_AIMMR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P25; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P25; + } +} + +static inline void hri_pio_clear_AIMMR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P25; +} + +static inline void hri_pio_set_AIMMR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P26; +} + +static inline bool hri_pio_get_AIMMR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P26) >> PIO_AIMMR_P26_Pos; +} + +static inline void hri_pio_write_AIMMR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P26; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P26; + } +} + +static inline void hri_pio_clear_AIMMR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P26; +} + +static inline void hri_pio_set_AIMMR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P27; +} + +static inline bool hri_pio_get_AIMMR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P27) >> PIO_AIMMR_P27_Pos; +} + +static inline void hri_pio_write_AIMMR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P27; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P27; + } +} + +static inline void hri_pio_clear_AIMMR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P27; +} + +static inline void hri_pio_set_AIMMR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P28; +} + +static inline bool hri_pio_get_AIMMR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P28) >> PIO_AIMMR_P28_Pos; +} + +static inline void hri_pio_write_AIMMR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P28; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P28; + } +} + +static inline void hri_pio_clear_AIMMR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P28; +} + +static inline void hri_pio_set_AIMMR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P29; +} + +static inline bool hri_pio_get_AIMMR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P29) >> PIO_AIMMR_P29_Pos; +} + +static inline void hri_pio_write_AIMMR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P29; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P29; + } +} + +static inline void hri_pio_clear_AIMMR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P29; +} + +static inline void hri_pio_set_AIMMR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P30; +} + +static inline bool hri_pio_get_AIMMR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P30) >> PIO_AIMMR_P30_Pos; +} + +static inline void hri_pio_write_AIMMR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P30; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P30; + } +} + +static inline void hri_pio_clear_AIMMR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P30; +} + +static inline void hri_pio_set_AIMMR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P31; +} + +static inline bool hri_pio_get_AIMMR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_AIMMR & PIO_AIMMR_P31) >> PIO_AIMMR_P31_Pos; +} + +static inline void hri_pio_write_AIMMR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P31; + } else { + ((Pio *)hw)->PIO_AIMER = PIO_AIMMR_P31; + } +} + +static inline void hri_pio_clear_AIMMR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_AIMDR = PIO_AIMMR_P31; +} + +static inline void hri_pio_set_AIMMR_reg(const void *const hw, hri_pio_aimmr_reg_t mask) +{ + ((Pio *)hw)->PIO_AIMER = mask; +} + +static inline hri_pio_aimmr_reg_t hri_pio_get_AIMMR_reg(const void *const hw, hri_pio_aimmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_AIMMR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_aimmr_reg_t hri_pio_read_AIMMR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_AIMMR; +} + +static inline void hri_pio_write_AIMMR_reg(const void *const hw, hri_pio_aimmr_reg_t data) +{ + ((Pio *)hw)->PIO_AIMER = data; + ((Pio *)hw)->PIO_AIMDR = ~data; +} + +static inline void hri_pio_clear_AIMMR_reg(const void *const hw, hri_pio_aimmr_reg_t mask) +{ + ((Pio *)hw)->PIO_AIMDR = mask; +} + +static inline void hri_pio_set_ELSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P0; +} + +static inline bool hri_pio_get_ELSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P0) >> PIO_ELSR_P0_Pos; +} + +static inline void hri_pio_write_ELSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P0; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P0; + } +} + +static inline void hri_pio_clear_ELSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P0; +} + +static inline void hri_pio_set_ELSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P1; +} + +static inline bool hri_pio_get_ELSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P1) >> PIO_ELSR_P1_Pos; +} + +static inline void hri_pio_write_ELSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P1; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P1; + } +} + +static inline void hri_pio_clear_ELSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P1; +} + +static inline void hri_pio_set_ELSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P2; +} + +static inline bool hri_pio_get_ELSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P2) >> PIO_ELSR_P2_Pos; +} + +static inline void hri_pio_write_ELSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P2; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P2; + } +} + +static inline void hri_pio_clear_ELSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P2; +} + +static inline void hri_pio_set_ELSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P3; +} + +static inline bool hri_pio_get_ELSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P3) >> PIO_ELSR_P3_Pos; +} + +static inline void hri_pio_write_ELSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P3; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P3; + } +} + +static inline void hri_pio_clear_ELSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P3; +} + +static inline void hri_pio_set_ELSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P4; +} + +static inline bool hri_pio_get_ELSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P4) >> PIO_ELSR_P4_Pos; +} + +static inline void hri_pio_write_ELSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P4; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P4; + } +} + +static inline void hri_pio_clear_ELSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P4; +} + +static inline void hri_pio_set_ELSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P5; +} + +static inline bool hri_pio_get_ELSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P5) >> PIO_ELSR_P5_Pos; +} + +static inline void hri_pio_write_ELSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P5; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P5; + } +} + +static inline void hri_pio_clear_ELSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P5; +} + +static inline void hri_pio_set_ELSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P6; +} + +static inline bool hri_pio_get_ELSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P6) >> PIO_ELSR_P6_Pos; +} + +static inline void hri_pio_write_ELSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P6; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P6; + } +} + +static inline void hri_pio_clear_ELSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P6; +} + +static inline void hri_pio_set_ELSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P7; +} + +static inline bool hri_pio_get_ELSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P7) >> PIO_ELSR_P7_Pos; +} + +static inline void hri_pio_write_ELSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P7; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P7; + } +} + +static inline void hri_pio_clear_ELSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P7; +} + +static inline void hri_pio_set_ELSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P8; +} + +static inline bool hri_pio_get_ELSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P8) >> PIO_ELSR_P8_Pos; +} + +static inline void hri_pio_write_ELSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P8; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P8; + } +} + +static inline void hri_pio_clear_ELSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P8; +} + +static inline void hri_pio_set_ELSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P9; +} + +static inline bool hri_pio_get_ELSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P9) >> PIO_ELSR_P9_Pos; +} + +static inline void hri_pio_write_ELSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P9; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P9; + } +} + +static inline void hri_pio_clear_ELSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P9; +} + +static inline void hri_pio_set_ELSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P10; +} + +static inline bool hri_pio_get_ELSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P10) >> PIO_ELSR_P10_Pos; +} + +static inline void hri_pio_write_ELSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P10; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P10; + } +} + +static inline void hri_pio_clear_ELSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P10; +} + +static inline void hri_pio_set_ELSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P11; +} + +static inline bool hri_pio_get_ELSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P11) >> PIO_ELSR_P11_Pos; +} + +static inline void hri_pio_write_ELSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P11; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P11; + } +} + +static inline void hri_pio_clear_ELSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P11; +} + +static inline void hri_pio_set_ELSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P12; +} + +static inline bool hri_pio_get_ELSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P12) >> PIO_ELSR_P12_Pos; +} + +static inline void hri_pio_write_ELSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P12; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P12; + } +} + +static inline void hri_pio_clear_ELSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P12; +} + +static inline void hri_pio_set_ELSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P13; +} + +static inline bool hri_pio_get_ELSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P13) >> PIO_ELSR_P13_Pos; +} + +static inline void hri_pio_write_ELSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P13; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P13; + } +} + +static inline void hri_pio_clear_ELSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P13; +} + +static inline void hri_pio_set_ELSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P14; +} + +static inline bool hri_pio_get_ELSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P14) >> PIO_ELSR_P14_Pos; +} + +static inline void hri_pio_write_ELSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P14; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P14; + } +} + +static inline void hri_pio_clear_ELSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P14; +} + +static inline void hri_pio_set_ELSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P15; +} + +static inline bool hri_pio_get_ELSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P15) >> PIO_ELSR_P15_Pos; +} + +static inline void hri_pio_write_ELSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P15; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P15; + } +} + +static inline void hri_pio_clear_ELSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P15; +} + +static inline void hri_pio_set_ELSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P16; +} + +static inline bool hri_pio_get_ELSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P16) >> PIO_ELSR_P16_Pos; +} + +static inline void hri_pio_write_ELSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P16; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P16; + } +} + +static inline void hri_pio_clear_ELSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P16; +} + +static inline void hri_pio_set_ELSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P17; +} + +static inline bool hri_pio_get_ELSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P17) >> PIO_ELSR_P17_Pos; +} + +static inline void hri_pio_write_ELSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P17; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P17; + } +} + +static inline void hri_pio_clear_ELSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P17; +} + +static inline void hri_pio_set_ELSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P18; +} + +static inline bool hri_pio_get_ELSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P18) >> PIO_ELSR_P18_Pos; +} + +static inline void hri_pio_write_ELSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P18; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P18; + } +} + +static inline void hri_pio_clear_ELSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P18; +} + +static inline void hri_pio_set_ELSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P19; +} + +static inline bool hri_pio_get_ELSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P19) >> PIO_ELSR_P19_Pos; +} + +static inline void hri_pio_write_ELSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P19; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P19; + } +} + +static inline void hri_pio_clear_ELSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P19; +} + +static inline void hri_pio_set_ELSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P20; +} + +static inline bool hri_pio_get_ELSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P20) >> PIO_ELSR_P20_Pos; +} + +static inline void hri_pio_write_ELSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P20; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P20; + } +} + +static inline void hri_pio_clear_ELSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P20; +} + +static inline void hri_pio_set_ELSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P21; +} + +static inline bool hri_pio_get_ELSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P21) >> PIO_ELSR_P21_Pos; +} + +static inline void hri_pio_write_ELSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P21; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P21; + } +} + +static inline void hri_pio_clear_ELSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P21; +} + +static inline void hri_pio_set_ELSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P22; +} + +static inline bool hri_pio_get_ELSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P22) >> PIO_ELSR_P22_Pos; +} + +static inline void hri_pio_write_ELSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P22; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P22; + } +} + +static inline void hri_pio_clear_ELSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P22; +} + +static inline void hri_pio_set_ELSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P23; +} + +static inline bool hri_pio_get_ELSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P23) >> PIO_ELSR_P23_Pos; +} + +static inline void hri_pio_write_ELSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P23; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P23; + } +} + +static inline void hri_pio_clear_ELSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P23; +} + +static inline void hri_pio_set_ELSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P24; +} + +static inline bool hri_pio_get_ELSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P24) >> PIO_ELSR_P24_Pos; +} + +static inline void hri_pio_write_ELSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P24; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P24; + } +} + +static inline void hri_pio_clear_ELSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P24; +} + +static inline void hri_pio_set_ELSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P25; +} + +static inline bool hri_pio_get_ELSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P25) >> PIO_ELSR_P25_Pos; +} + +static inline void hri_pio_write_ELSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P25; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P25; + } +} + +static inline void hri_pio_clear_ELSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P25; +} + +static inline void hri_pio_set_ELSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P26; +} + +static inline bool hri_pio_get_ELSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P26) >> PIO_ELSR_P26_Pos; +} + +static inline void hri_pio_write_ELSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P26; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P26; + } +} + +static inline void hri_pio_clear_ELSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P26; +} + +static inline void hri_pio_set_ELSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P27; +} + +static inline bool hri_pio_get_ELSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P27) >> PIO_ELSR_P27_Pos; +} + +static inline void hri_pio_write_ELSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P27; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P27; + } +} + +static inline void hri_pio_clear_ELSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P27; +} + +static inline void hri_pio_set_ELSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P28; +} + +static inline bool hri_pio_get_ELSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P28) >> PIO_ELSR_P28_Pos; +} + +static inline void hri_pio_write_ELSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P28; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P28; + } +} + +static inline void hri_pio_clear_ELSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P28; +} + +static inline void hri_pio_set_ELSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P29; +} + +static inline bool hri_pio_get_ELSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P29) >> PIO_ELSR_P29_Pos; +} + +static inline void hri_pio_write_ELSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P29; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P29; + } +} + +static inline void hri_pio_clear_ELSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P29; +} + +static inline void hri_pio_set_ELSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P30; +} + +static inline bool hri_pio_get_ELSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P30) >> PIO_ELSR_P30_Pos; +} + +static inline void hri_pio_write_ELSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P30; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P30; + } +} + +static inline void hri_pio_clear_ELSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P30; +} + +static inline void hri_pio_set_ELSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P31; +} + +static inline bool hri_pio_get_ELSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_ELSR & PIO_ELSR_P31) >> PIO_ELSR_P31_Pos; +} + +static inline void hri_pio_write_ELSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P31; + } else { + ((Pio *)hw)->PIO_LSR = PIO_ELSR_P31; + } +} + +static inline void hri_pio_clear_ELSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_ESR = PIO_ELSR_P31; +} + +static inline void hri_pio_set_ELSR_reg(const void *const hw, hri_pio_elsr_reg_t mask) +{ + ((Pio *)hw)->PIO_LSR = mask; +} + +static inline hri_pio_elsr_reg_t hri_pio_get_ELSR_reg(const void *const hw, hri_pio_elsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ELSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_elsr_reg_t hri_pio_read_ELSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_ELSR; +} + +static inline void hri_pio_write_ELSR_reg(const void *const hw, hri_pio_elsr_reg_t data) +{ + ((Pio *)hw)->PIO_LSR = data; + ((Pio *)hw)->PIO_ESR = ~data; +} + +static inline void hri_pio_clear_ELSR_reg(const void *const hw, hri_pio_elsr_reg_t mask) +{ + ((Pio *)hw)->PIO_ESR = mask; +} + +static inline void hri_pio_set_FRLHSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P0; +} + +static inline bool hri_pio_get_FRLHSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P0) >> PIO_FRLHSR_P0_Pos; +} + +static inline void hri_pio_write_FRLHSR_P0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P0; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P0; + } +} + +static inline void hri_pio_clear_FRLHSR_P0_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P0; +} + +static inline void hri_pio_set_FRLHSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P1; +} + +static inline bool hri_pio_get_FRLHSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P1) >> PIO_FRLHSR_P1_Pos; +} + +static inline void hri_pio_write_FRLHSR_P1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P1; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P1; + } +} + +static inline void hri_pio_clear_FRLHSR_P1_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P1; +} + +static inline void hri_pio_set_FRLHSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P2; +} + +static inline bool hri_pio_get_FRLHSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P2) >> PIO_FRLHSR_P2_Pos; +} + +static inline void hri_pio_write_FRLHSR_P2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P2; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P2; + } +} + +static inline void hri_pio_clear_FRLHSR_P2_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P2; +} + +static inline void hri_pio_set_FRLHSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P3; +} + +static inline bool hri_pio_get_FRLHSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P3) >> PIO_FRLHSR_P3_Pos; +} + +static inline void hri_pio_write_FRLHSR_P3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P3; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P3; + } +} + +static inline void hri_pio_clear_FRLHSR_P3_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P3; +} + +static inline void hri_pio_set_FRLHSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P4; +} + +static inline bool hri_pio_get_FRLHSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P4) >> PIO_FRLHSR_P4_Pos; +} + +static inline void hri_pio_write_FRLHSR_P4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P4; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P4; + } +} + +static inline void hri_pio_clear_FRLHSR_P4_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P4; +} + +static inline void hri_pio_set_FRLHSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P5; +} + +static inline bool hri_pio_get_FRLHSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P5) >> PIO_FRLHSR_P5_Pos; +} + +static inline void hri_pio_write_FRLHSR_P5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P5; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P5; + } +} + +static inline void hri_pio_clear_FRLHSR_P5_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P5; +} + +static inline void hri_pio_set_FRLHSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P6; +} + +static inline bool hri_pio_get_FRLHSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P6) >> PIO_FRLHSR_P6_Pos; +} + +static inline void hri_pio_write_FRLHSR_P6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P6; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P6; + } +} + +static inline void hri_pio_clear_FRLHSR_P6_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P6; +} + +static inline void hri_pio_set_FRLHSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P7; +} + +static inline bool hri_pio_get_FRLHSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P7) >> PIO_FRLHSR_P7_Pos; +} + +static inline void hri_pio_write_FRLHSR_P7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P7; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P7; + } +} + +static inline void hri_pio_clear_FRLHSR_P7_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P7; +} + +static inline void hri_pio_set_FRLHSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P8; +} + +static inline bool hri_pio_get_FRLHSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P8) >> PIO_FRLHSR_P8_Pos; +} + +static inline void hri_pio_write_FRLHSR_P8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P8; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P8; + } +} + +static inline void hri_pio_clear_FRLHSR_P8_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P8; +} + +static inline void hri_pio_set_FRLHSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P9; +} + +static inline bool hri_pio_get_FRLHSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P9) >> PIO_FRLHSR_P9_Pos; +} + +static inline void hri_pio_write_FRLHSR_P9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P9; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P9; + } +} + +static inline void hri_pio_clear_FRLHSR_P9_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P9; +} + +static inline void hri_pio_set_FRLHSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P10; +} + +static inline bool hri_pio_get_FRLHSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P10) >> PIO_FRLHSR_P10_Pos; +} + +static inline void hri_pio_write_FRLHSR_P10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P10; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P10; + } +} + +static inline void hri_pio_clear_FRLHSR_P10_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P10; +} + +static inline void hri_pio_set_FRLHSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P11; +} + +static inline bool hri_pio_get_FRLHSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P11) >> PIO_FRLHSR_P11_Pos; +} + +static inline void hri_pio_write_FRLHSR_P11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P11; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P11; + } +} + +static inline void hri_pio_clear_FRLHSR_P11_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P11; +} + +static inline void hri_pio_set_FRLHSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P12; +} + +static inline bool hri_pio_get_FRLHSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P12) >> PIO_FRLHSR_P12_Pos; +} + +static inline void hri_pio_write_FRLHSR_P12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P12; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P12; + } +} + +static inline void hri_pio_clear_FRLHSR_P12_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P12; +} + +static inline void hri_pio_set_FRLHSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P13; +} + +static inline bool hri_pio_get_FRLHSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P13) >> PIO_FRLHSR_P13_Pos; +} + +static inline void hri_pio_write_FRLHSR_P13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P13; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P13; + } +} + +static inline void hri_pio_clear_FRLHSR_P13_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P13; +} + +static inline void hri_pio_set_FRLHSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P14; +} + +static inline bool hri_pio_get_FRLHSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P14) >> PIO_FRLHSR_P14_Pos; +} + +static inline void hri_pio_write_FRLHSR_P14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P14; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P14; + } +} + +static inline void hri_pio_clear_FRLHSR_P14_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P14; +} + +static inline void hri_pio_set_FRLHSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P15; +} + +static inline bool hri_pio_get_FRLHSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P15) >> PIO_FRLHSR_P15_Pos; +} + +static inline void hri_pio_write_FRLHSR_P15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P15; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P15; + } +} + +static inline void hri_pio_clear_FRLHSR_P15_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P15; +} + +static inline void hri_pio_set_FRLHSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P16; +} + +static inline bool hri_pio_get_FRLHSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P16) >> PIO_FRLHSR_P16_Pos; +} + +static inline void hri_pio_write_FRLHSR_P16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P16; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P16; + } +} + +static inline void hri_pio_clear_FRLHSR_P16_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P16; +} + +static inline void hri_pio_set_FRLHSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P17; +} + +static inline bool hri_pio_get_FRLHSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P17) >> PIO_FRLHSR_P17_Pos; +} + +static inline void hri_pio_write_FRLHSR_P17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P17; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P17; + } +} + +static inline void hri_pio_clear_FRLHSR_P17_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P17; +} + +static inline void hri_pio_set_FRLHSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P18; +} + +static inline bool hri_pio_get_FRLHSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P18) >> PIO_FRLHSR_P18_Pos; +} + +static inline void hri_pio_write_FRLHSR_P18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P18; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P18; + } +} + +static inline void hri_pio_clear_FRLHSR_P18_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P18; +} + +static inline void hri_pio_set_FRLHSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P19; +} + +static inline bool hri_pio_get_FRLHSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P19) >> PIO_FRLHSR_P19_Pos; +} + +static inline void hri_pio_write_FRLHSR_P19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P19; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P19; + } +} + +static inline void hri_pio_clear_FRLHSR_P19_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P19; +} + +static inline void hri_pio_set_FRLHSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P20; +} + +static inline bool hri_pio_get_FRLHSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P20) >> PIO_FRLHSR_P20_Pos; +} + +static inline void hri_pio_write_FRLHSR_P20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P20; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P20; + } +} + +static inline void hri_pio_clear_FRLHSR_P20_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P20; +} + +static inline void hri_pio_set_FRLHSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P21; +} + +static inline bool hri_pio_get_FRLHSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P21) >> PIO_FRLHSR_P21_Pos; +} + +static inline void hri_pio_write_FRLHSR_P21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P21; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P21; + } +} + +static inline void hri_pio_clear_FRLHSR_P21_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P21; +} + +static inline void hri_pio_set_FRLHSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P22; +} + +static inline bool hri_pio_get_FRLHSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P22) >> PIO_FRLHSR_P22_Pos; +} + +static inline void hri_pio_write_FRLHSR_P22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P22; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P22; + } +} + +static inline void hri_pio_clear_FRLHSR_P22_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P22; +} + +static inline void hri_pio_set_FRLHSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P23; +} + +static inline bool hri_pio_get_FRLHSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P23) >> PIO_FRLHSR_P23_Pos; +} + +static inline void hri_pio_write_FRLHSR_P23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P23; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P23; + } +} + +static inline void hri_pio_clear_FRLHSR_P23_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P23; +} + +static inline void hri_pio_set_FRLHSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P24; +} + +static inline bool hri_pio_get_FRLHSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P24) >> PIO_FRLHSR_P24_Pos; +} + +static inline void hri_pio_write_FRLHSR_P24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P24; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P24; + } +} + +static inline void hri_pio_clear_FRLHSR_P24_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P24; +} + +static inline void hri_pio_set_FRLHSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P25; +} + +static inline bool hri_pio_get_FRLHSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P25) >> PIO_FRLHSR_P25_Pos; +} + +static inline void hri_pio_write_FRLHSR_P25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P25; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P25; + } +} + +static inline void hri_pio_clear_FRLHSR_P25_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P25; +} + +static inline void hri_pio_set_FRLHSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P26; +} + +static inline bool hri_pio_get_FRLHSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P26) >> PIO_FRLHSR_P26_Pos; +} + +static inline void hri_pio_write_FRLHSR_P26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P26; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P26; + } +} + +static inline void hri_pio_clear_FRLHSR_P26_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P26; +} + +static inline void hri_pio_set_FRLHSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P27; +} + +static inline bool hri_pio_get_FRLHSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P27) >> PIO_FRLHSR_P27_Pos; +} + +static inline void hri_pio_write_FRLHSR_P27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P27; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P27; + } +} + +static inline void hri_pio_clear_FRLHSR_P27_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P27; +} + +static inline void hri_pio_set_FRLHSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P28; +} + +static inline bool hri_pio_get_FRLHSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P28) >> PIO_FRLHSR_P28_Pos; +} + +static inline void hri_pio_write_FRLHSR_P28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P28; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P28; + } +} + +static inline void hri_pio_clear_FRLHSR_P28_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P28; +} + +static inline void hri_pio_set_FRLHSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P29; +} + +static inline bool hri_pio_get_FRLHSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P29) >> PIO_FRLHSR_P29_Pos; +} + +static inline void hri_pio_write_FRLHSR_P29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P29; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P29; + } +} + +static inline void hri_pio_clear_FRLHSR_P29_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P29; +} + +static inline void hri_pio_set_FRLHSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P30; +} + +static inline bool hri_pio_get_FRLHSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P30) >> PIO_FRLHSR_P30_Pos; +} + +static inline void hri_pio_write_FRLHSR_P30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P30; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P30; + } +} + +static inline void hri_pio_clear_FRLHSR_P30_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P30; +} + +static inline void hri_pio_set_FRLHSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P31; +} + +static inline bool hri_pio_get_FRLHSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_FRLHSR & PIO_FRLHSR_P31) >> PIO_FRLHSR_P31_Pos; +} + +static inline void hri_pio_write_FRLHSR_P31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P31; + } else { + ((Pio *)hw)->PIO_REHLSR = PIO_FRLHSR_P31; + } +} + +static inline void hri_pio_clear_FRLHSR_P31_bit(const void *const hw) +{ + ((Pio *)hw)->PIO_FELLSR = PIO_FRLHSR_P31; +} + +static inline void hri_pio_set_FRLHSR_reg(const void *const hw, hri_pio_frlhsr_reg_t mask) +{ + ((Pio *)hw)->PIO_REHLSR = mask; +} + +static inline hri_pio_frlhsr_reg_t hri_pio_get_FRLHSR_reg(const void *const hw, hri_pio_frlhsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_FRLHSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_frlhsr_reg_t hri_pio_read_FRLHSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_FRLHSR; +} + +static inline void hri_pio_write_FRLHSR_reg(const void *const hw, hri_pio_frlhsr_reg_t data) +{ + ((Pio *)hw)->PIO_REHLSR = data; + ((Pio *)hw)->PIO_FELLSR = ~data; +} + +static inline void hri_pio_clear_FRLHSR_reg(const void *const hw, hri_pio_frlhsr_reg_t mask) +{ + ((Pio *)hw)->PIO_FELLSR = mask; +} + +static inline bool hri_pio_get_PDSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P0) > 0; +} + +static inline bool hri_pio_get_PDSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P1) > 0; +} + +static inline bool hri_pio_get_PDSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P2) > 0; +} + +static inline bool hri_pio_get_PDSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P3) > 0; +} + +static inline bool hri_pio_get_PDSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P4) > 0; +} + +static inline bool hri_pio_get_PDSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P5) > 0; +} + +static inline bool hri_pio_get_PDSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P6) > 0; +} + +static inline bool hri_pio_get_PDSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P7) > 0; +} + +static inline bool hri_pio_get_PDSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P8) > 0; +} + +static inline bool hri_pio_get_PDSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P9) > 0; +} + +static inline bool hri_pio_get_PDSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P10) > 0; +} + +static inline bool hri_pio_get_PDSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P11) > 0; +} + +static inline bool hri_pio_get_PDSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P12) > 0; +} + +static inline bool hri_pio_get_PDSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P13) > 0; +} + +static inline bool hri_pio_get_PDSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P14) > 0; +} + +static inline bool hri_pio_get_PDSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P15) > 0; +} + +static inline bool hri_pio_get_PDSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P16) > 0; +} + +static inline bool hri_pio_get_PDSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P17) > 0; +} + +static inline bool hri_pio_get_PDSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P18) > 0; +} + +static inline bool hri_pio_get_PDSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P19) > 0; +} + +static inline bool hri_pio_get_PDSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P20) > 0; +} + +static inline bool hri_pio_get_PDSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P21) > 0; +} + +static inline bool hri_pio_get_PDSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P22) > 0; +} + +static inline bool hri_pio_get_PDSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P23) > 0; +} + +static inline bool hri_pio_get_PDSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P24) > 0; +} + +static inline bool hri_pio_get_PDSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P25) > 0; +} + +static inline bool hri_pio_get_PDSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P26) > 0; +} + +static inline bool hri_pio_get_PDSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P27) > 0; +} + +static inline bool hri_pio_get_PDSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P28) > 0; +} + +static inline bool hri_pio_get_PDSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P29) > 0; +} + +static inline bool hri_pio_get_PDSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P30) > 0; +} + +static inline bool hri_pio_get_PDSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PDSR & PIO_PDSR_P31) > 0; +} + +static inline hri_pio_pdsr_reg_t hri_pio_get_PDSR_reg(const void *const hw, hri_pio_pdsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PDSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_pdsr_reg_t hri_pio_read_PDSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PDSR; +} + +static inline bool hri_pio_get_LOCKSR_P0_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P0) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P1_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P1) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P2_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P2) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P3_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P3) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P4_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P4) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P5_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P5) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P6_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P6) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P7_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P7) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P8_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P8) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P9_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P9) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P10_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P10) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P11_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P11) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P12_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P12) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P13_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P13) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P14_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P14) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P15_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P15) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P16_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P16) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P17_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P17) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P18_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P18) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P19_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P19) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P20_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P20) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P21_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P21) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P22_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P22) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P23_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P23) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P24_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P24) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P25_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P25) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P26_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P26) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P27_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P27) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P28_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P28) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P29_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P29) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P30_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P30) > 0; +} + +static inline bool hri_pio_get_LOCKSR_P31_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_LOCKSR & PIO_LOCKSR_P31) > 0; +} + +static inline hri_pio_locksr_reg_t hri_pio_get_LOCKSR_reg(const void *const hw, hri_pio_locksr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_LOCKSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_locksr_reg_t hri_pio_read_LOCKSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_LOCKSR; +} + +static inline bool hri_pio_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_WPSR & PIO_WPSR_WPVS) > 0; +} + +static inline hri_pio_wpsr_reg_t hri_pio_get_WPSR_WPVSRC_bf(const void *const hw, hri_pio_wpsr_reg_t mask) +{ + return (((Pio *)hw)->PIO_WPSR & PIO_WPSR_WPVSRC(mask)) >> PIO_WPSR_WPVSRC_Pos; +} + +static inline hri_pio_wpsr_reg_t hri_pio_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pio *)hw)->PIO_WPSR & PIO_WPSR_WPVSRC_Msk) >> PIO_WPSR_WPVSRC_Pos; +} + +static inline hri_pio_wpsr_reg_t hri_pio_get_WPSR_reg(const void *const hw, hri_pio_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_wpsr_reg_t hri_pio_read_WPSR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_WPSR; +} + +static inline bool hri_pio_get_PCIMR_DRDY_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCIMR & PIO_PCIMR_DRDY) > 0; +} + +static inline bool hri_pio_get_PCIMR_OVRE_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCIMR & PIO_PCIMR_OVRE) > 0; +} + +static inline bool hri_pio_get_PCIMR_ENDRX_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCIMR & PIO_PCIMR_ENDRX) > 0; +} + +static inline bool hri_pio_get_PCIMR_RXBUFF_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCIMR & PIO_PCIMR_RXBUFF) > 0; +} + +static inline hri_pio_pcimr_reg_t hri_pio_get_PCIMR_reg(const void *const hw, hri_pio_pcimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCIMR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_pcimr_reg_t hri_pio_read_PCIMR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PCIMR; +} + +static inline bool hri_pio_get_PCISR_DRDY_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCISR & PIO_PCISR_DRDY) > 0; +} + +static inline bool hri_pio_get_PCISR_OVRE_bit(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCISR & PIO_PCISR_OVRE) > 0; +} + +static inline hri_pio_pcisr_reg_t hri_pio_get_PCISR_reg(const void *const hw, hri_pio_pcisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCISR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_pcisr_reg_t hri_pio_read_PCISR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PCISR; +} + +static inline hri_pio_pcrhr_reg_t hri_pio_get_PCRHR_RDATA_bf(const void *const hw, hri_pio_pcrhr_reg_t mask) +{ + return (((Pio *)hw)->PIO_PCRHR & PIO_PCRHR_RDATA(mask)) >> PIO_PCRHR_RDATA_Pos; +} + +static inline hri_pio_pcrhr_reg_t hri_pio_read_PCRHR_RDATA_bf(const void *const hw) +{ + return (((Pio *)hw)->PIO_PCRHR & PIO_PCRHR_RDATA_Msk) >> PIO_PCRHR_RDATA_Pos; +} + +static inline hri_pio_pcrhr_reg_t hri_pio_get_PCRHR_reg(const void *const hw, hri_pio_pcrhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCRHR; + tmp &= mask; + return tmp; +} + +static inline hri_pio_pcrhr_reg_t hri_pio_read_PCRHR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PCRHR; +} + +static inline void hri_pio_set_ABCDSR_P0_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P0) >> PIO_ABCDSR_P0_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P0; + tmp |= value << PIO_ABCDSR_P0_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P0_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P0_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P1_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P1) >> PIO_ABCDSR_P1_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P1; + tmp |= value << PIO_ABCDSR_P1_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P1_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P1_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P2_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P2) >> PIO_ABCDSR_P2_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P2; + tmp |= value << PIO_ABCDSR_P2_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P2_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P2_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P3_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P3) >> PIO_ABCDSR_P3_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P3; + tmp |= value << PIO_ABCDSR_P3_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P3_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P3_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P4_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P4) >> PIO_ABCDSR_P4_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P4; + tmp |= value << PIO_ABCDSR_P4_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P4_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P4_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P5_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P5) >> PIO_ABCDSR_P5_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P5; + tmp |= value << PIO_ABCDSR_P5_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P5_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P5_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P6_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P6) >> PIO_ABCDSR_P6_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P6; + tmp |= value << PIO_ABCDSR_P6_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P6_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P6_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P7_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P7) >> PIO_ABCDSR_P7_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P7; + tmp |= value << PIO_ABCDSR_P7_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P7_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P7_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P8_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P8_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P8) >> PIO_ABCDSR_P8_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P8_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P8; + tmp |= value << PIO_ABCDSR_P8_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P8_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P8_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P9_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P9_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P9) >> PIO_ABCDSR_P9_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P9_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P9; + tmp |= value << PIO_ABCDSR_P9_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P9_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P9_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P10_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P10_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P10) >> PIO_ABCDSR_P10_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P10_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P10; + tmp |= value << PIO_ABCDSR_P10_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P10_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P10_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P11_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P11_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P11) >> PIO_ABCDSR_P11_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P11_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P11; + tmp |= value << PIO_ABCDSR_P11_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P11_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P11_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P12_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P12_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P12) >> PIO_ABCDSR_P12_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P12_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P12; + tmp |= value << PIO_ABCDSR_P12_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P12_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P12_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P13_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P13_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P13) >> PIO_ABCDSR_P13_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P13_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P13; + tmp |= value << PIO_ABCDSR_P13_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P13_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P13_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P14_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P14_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P14) >> PIO_ABCDSR_P14_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P14_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P14; + tmp |= value << PIO_ABCDSR_P14_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P14_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P14_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P15_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P15_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P15) >> PIO_ABCDSR_P15_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P15_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P15; + tmp |= value << PIO_ABCDSR_P15_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P15_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P15_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P16_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P16_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P16) >> PIO_ABCDSR_P16_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P16_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P16; + tmp |= value << PIO_ABCDSR_P16_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P16_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P16_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P17_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P17_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P17) >> PIO_ABCDSR_P17_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P17_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P17; + tmp |= value << PIO_ABCDSR_P17_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P17_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P17_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P18_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P18_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P18) >> PIO_ABCDSR_P18_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P18_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P18; + tmp |= value << PIO_ABCDSR_P18_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P18_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P18_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P19_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P19_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P19) >> PIO_ABCDSR_P19_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P19_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P19; + tmp |= value << PIO_ABCDSR_P19_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P19_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P19_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P20_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P20_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P20) >> PIO_ABCDSR_P20_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P20_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P20; + tmp |= value << PIO_ABCDSR_P20_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P20_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P20_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P21_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P21_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P21) >> PIO_ABCDSR_P21_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P21_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P21; + tmp |= value << PIO_ABCDSR_P21_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P21_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P21_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P22_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P22_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P22) >> PIO_ABCDSR_P22_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P22_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P22; + tmp |= value << PIO_ABCDSR_P22_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P22_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P22_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P23_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P23_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P23) >> PIO_ABCDSR_P23_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P23_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P23; + tmp |= value << PIO_ABCDSR_P23_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P23_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P23_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P24_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P24_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P24) >> PIO_ABCDSR_P24_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P24_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P24; + tmp |= value << PIO_ABCDSR_P24_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P24_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P24_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P25_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P25_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P25) >> PIO_ABCDSR_P25_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P25_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P25; + tmp |= value << PIO_ABCDSR_P25_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P25_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P25_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P26_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P26_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P26) >> PIO_ABCDSR_P26_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P26_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P26; + tmp |= value << PIO_ABCDSR_P26_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P26_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P26_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P27_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P27_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P27) >> PIO_ABCDSR_P27_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P27_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P27; + tmp |= value << PIO_ABCDSR_P27_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P27_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P27_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P28_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P28_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P28) >> PIO_ABCDSR_P28_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P28_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P28; + tmp |= value << PIO_ABCDSR_P28_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P28_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P28_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P29_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P29_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P29) >> PIO_ABCDSR_P29_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P29_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P29; + tmp |= value << PIO_ABCDSR_P29_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P29_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P29_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P30_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P30_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P30) >> PIO_ABCDSR_P30_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P30_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P30; + tmp |= value << PIO_ABCDSR_P30_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P30_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P30_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_P31_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= PIO_ABCDSR_P31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_ABCDSR_P31_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp = (tmp & PIO_ABCDSR_P31) >> PIO_ABCDSR_P31_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_ABCDSR_P31_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= ~PIO_ABCDSR_P31; + tmp |= value << PIO_ABCDSR_P31_Pos; + ((Pio *)hw)->PIO_ABCDSR[index] = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_P31_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~PIO_ABCDSR_P31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_P31_bit(const void *const hw, uint8_t index) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= PIO_ABCDSR_P31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_ABCDSR_reg(const void *const hw, uint8_t index, hri_pio_abcdsr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_abcdsr_reg_t hri_pio_get_ABCDSR_reg(const void *const hw, uint8_t index, + hri_pio_abcdsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_ABCDSR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_ABCDSR_reg(const void *const hw, uint8_t index, hri_pio_abcdsr_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_ABCDSR_reg(const void *const hw, uint8_t index, hri_pio_abcdsr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_ABCDSR_reg(const void *const hw, uint8_t index, hri_pio_abcdsr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_ABCDSR[index] ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_abcdsr_reg_t hri_pio_read_ABCDSR_reg(const void *const hw, uint8_t index) +{ + return ((Pio *)hw)->PIO_ABCDSR[index]; +} + +static inline void hri_pio_set_SCDR_DIV_bf(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR |= PIO_SCDR_DIV(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_scdr_reg_t hri_pio_get_SCDR_DIV_bf(const void *const hw, hri_pio_scdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCDR; + tmp = (tmp & PIO_SCDR_DIV(mask)) >> PIO_SCDR_DIV_Pos; + return tmp; +} + +static inline void hri_pio_write_SCDR_DIV_bf(const void *const hw, hri_pio_scdr_reg_t data) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCDR; + tmp &= ~PIO_SCDR_DIV_Msk; + tmp |= PIO_SCDR_DIV(data); + ((Pio *)hw)->PIO_SCDR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCDR_DIV_bf(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR &= ~PIO_SCDR_DIV(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCDR_DIV_bf(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR ^= PIO_SCDR_DIV(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_scdr_reg_t hri_pio_read_SCDR_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCDR; + tmp = (tmp & PIO_SCDR_DIV_Msk) >> PIO_SCDR_DIV_Pos; + return tmp; +} + +static inline void hri_pio_set_SCDR_reg(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_scdr_reg_t hri_pio_get_SCDR_reg(const void *const hw, hri_pio_scdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCDR; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_SCDR_reg(const void *const hw, hri_pio_scdr_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCDR_reg(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCDR_reg(const void *const hw, hri_pio_scdr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCDR ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_scdr_reg_t hri_pio_read_SCDR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_SCDR; +} + +static inline void hri_pio_set_WPMR_WPEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR |= PIO_WPMR_WPEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_WPMR; + tmp = (tmp & PIO_WPMR_WPEN) >> PIO_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_WPMR; + tmp &= ~PIO_WPMR_WPEN; + tmp |= value << PIO_WPMR_WPEN_Pos; + ((Pio *)hw)->PIO_WPMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_WPMR_WPEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR &= ~PIO_WPMR_WPEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_WPMR_WPEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR ^= PIO_WPMR_WPEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_WPMR_WPKEY_bf(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR |= PIO_WPMR_WPKEY(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_wpmr_reg_t hri_pio_get_WPMR_WPKEY_bf(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_WPMR; + tmp = (tmp & PIO_WPMR_WPKEY(mask)) >> PIO_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_pio_write_WPMR_WPKEY_bf(const void *const hw, hri_pio_wpmr_reg_t data) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_WPMR; + tmp &= ~PIO_WPMR_WPKEY_Msk; + tmp |= PIO_WPMR_WPKEY(data); + ((Pio *)hw)->PIO_WPMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_WPMR_WPKEY_bf(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR &= ~PIO_WPMR_WPKEY(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_WPMR_WPKEY_bf(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR ^= PIO_WPMR_WPKEY(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_wpmr_reg_t hri_pio_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_WPMR; + tmp = (tmp & PIO_WPMR_WPKEY_Msk) >> PIO_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_pio_set_WPMR_reg(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_wpmr_reg_t hri_pio_get_WPMR_reg(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_WPMR_reg(const void *const hw, hri_pio_wpmr_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_WPMR_reg(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_WPMR_reg(const void *const hw, hri_pio_wpmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_WPMR ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_wpmr_reg_t hri_pio_read_WPMR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_WPMR; +} + +static inline void hri_pio_set_SCHMITT_SCHMITT0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT0) >> PIO_SCHMITT_SCHMITT0_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT0; + tmp |= value << PIO_SCHMITT_SCHMITT0_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT1) >> PIO_SCHMITT_SCHMITT1_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT1; + tmp |= value << PIO_SCHMITT_SCHMITT1_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT2) >> PIO_SCHMITT_SCHMITT2_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT2; + tmp |= value << PIO_SCHMITT_SCHMITT2_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT3) >> PIO_SCHMITT_SCHMITT3_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT3; + tmp |= value << PIO_SCHMITT_SCHMITT3_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT4) >> PIO_SCHMITT_SCHMITT4_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT4; + tmp |= value << PIO_SCHMITT_SCHMITT4_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT5) >> PIO_SCHMITT_SCHMITT5_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT5; + tmp |= value << PIO_SCHMITT_SCHMITT5_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT6) >> PIO_SCHMITT_SCHMITT6_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT6; + tmp |= value << PIO_SCHMITT_SCHMITT6_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT7) >> PIO_SCHMITT_SCHMITT7_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT7; + tmp |= value << PIO_SCHMITT_SCHMITT7_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT8) >> PIO_SCHMITT_SCHMITT8_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT8; + tmp |= value << PIO_SCHMITT_SCHMITT8_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT9) >> PIO_SCHMITT_SCHMITT9_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT9; + tmp |= value << PIO_SCHMITT_SCHMITT9_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT10) >> PIO_SCHMITT_SCHMITT10_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT10; + tmp |= value << PIO_SCHMITT_SCHMITT10_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT11) >> PIO_SCHMITT_SCHMITT11_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT11; + tmp |= value << PIO_SCHMITT_SCHMITT11_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT12) >> PIO_SCHMITT_SCHMITT12_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT12; + tmp |= value << PIO_SCHMITT_SCHMITT12_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT13) >> PIO_SCHMITT_SCHMITT13_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT13; + tmp |= value << PIO_SCHMITT_SCHMITT13_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT14) >> PIO_SCHMITT_SCHMITT14_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT14; + tmp |= value << PIO_SCHMITT_SCHMITT14_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT15) >> PIO_SCHMITT_SCHMITT15_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT15; + tmp |= value << PIO_SCHMITT_SCHMITT15_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT16) >> PIO_SCHMITT_SCHMITT16_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT16; + tmp |= value << PIO_SCHMITT_SCHMITT16_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT17) >> PIO_SCHMITT_SCHMITT17_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT17; + tmp |= value << PIO_SCHMITT_SCHMITT17_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT18) >> PIO_SCHMITT_SCHMITT18_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT18; + tmp |= value << PIO_SCHMITT_SCHMITT18_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT19) >> PIO_SCHMITT_SCHMITT19_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT19; + tmp |= value << PIO_SCHMITT_SCHMITT19_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT20) >> PIO_SCHMITT_SCHMITT20_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT20; + tmp |= value << PIO_SCHMITT_SCHMITT20_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT21) >> PIO_SCHMITT_SCHMITT21_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT21; + tmp |= value << PIO_SCHMITT_SCHMITT21_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT22) >> PIO_SCHMITT_SCHMITT22_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT22; + tmp |= value << PIO_SCHMITT_SCHMITT22_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT23) >> PIO_SCHMITT_SCHMITT23_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT23; + tmp |= value << PIO_SCHMITT_SCHMITT23_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT24) >> PIO_SCHMITT_SCHMITT24_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT24; + tmp |= value << PIO_SCHMITT_SCHMITT24_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT25) >> PIO_SCHMITT_SCHMITT25_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT25; + tmp |= value << PIO_SCHMITT_SCHMITT25_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT26) >> PIO_SCHMITT_SCHMITT26_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT26; + tmp |= value << PIO_SCHMITT_SCHMITT26_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT27) >> PIO_SCHMITT_SCHMITT27_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT27; + tmp |= value << PIO_SCHMITT_SCHMITT27_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT28) >> PIO_SCHMITT_SCHMITT28_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT28; + tmp |= value << PIO_SCHMITT_SCHMITT28_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT29) >> PIO_SCHMITT_SCHMITT29_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT29; + tmp |= value << PIO_SCHMITT_SCHMITT29_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT30) >> PIO_SCHMITT_SCHMITT30_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT30; + tmp |= value << PIO_SCHMITT_SCHMITT30_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_SCHMITT31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= PIO_SCHMITT_SCHMITT31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_SCHMITT_SCHMITT31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp = (tmp & PIO_SCHMITT_SCHMITT31) >> PIO_SCHMITT_SCHMITT31_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_SCHMITT_SCHMITT31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= ~PIO_SCHMITT_SCHMITT31; + tmp |= value << PIO_SCHMITT_SCHMITT31_Pos; + ((Pio *)hw)->PIO_SCHMITT = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_SCHMITT31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~PIO_SCHMITT_SCHMITT31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_SCHMITT31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= PIO_SCHMITT_SCHMITT31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_SCHMITT_reg(const void *const hw, hri_pio_schmitt_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_schmitt_reg_t hri_pio_get_SCHMITT_reg(const void *const hw, hri_pio_schmitt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_SCHMITT; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_SCHMITT_reg(const void *const hw, hri_pio_schmitt_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_SCHMITT_reg(const void *const hw, hri_pio_schmitt_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_SCHMITT_reg(const void *const hw, hri_pio_schmitt_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_SCHMITT ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_schmitt_reg_t hri_pio_read_SCHMITT_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_SCHMITT; +} + +static inline void hri_pio_set_DRIVER_LINE0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE0) >> PIO_DRIVER_LINE0_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE0; + tmp |= value << PIO_DRIVER_LINE0_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE0_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE0; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE1) >> PIO_DRIVER_LINE1_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE1; + tmp |= value << PIO_DRIVER_LINE1_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE1_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE1; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE2) >> PIO_DRIVER_LINE2_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE2; + tmp |= value << PIO_DRIVER_LINE2_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE2_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE2; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE3) >> PIO_DRIVER_LINE3_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE3; + tmp |= value << PIO_DRIVER_LINE3_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE3_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE3; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE4) >> PIO_DRIVER_LINE4_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE4; + tmp |= value << PIO_DRIVER_LINE4_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE4_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE4; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE5) >> PIO_DRIVER_LINE5_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE5; + tmp |= value << PIO_DRIVER_LINE5_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE5_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE5; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE6) >> PIO_DRIVER_LINE6_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE6; + tmp |= value << PIO_DRIVER_LINE6_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE6_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE6; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE7) >> PIO_DRIVER_LINE7_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE7; + tmp |= value << PIO_DRIVER_LINE7_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE7_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE7; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE8) >> PIO_DRIVER_LINE8_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE8; + tmp |= value << PIO_DRIVER_LINE8_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE8_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE8; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE9) >> PIO_DRIVER_LINE9_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE9; + tmp |= value << PIO_DRIVER_LINE9_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE9_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE9; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE10) >> PIO_DRIVER_LINE10_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE10; + tmp |= value << PIO_DRIVER_LINE10_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE10_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE10; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE11) >> PIO_DRIVER_LINE11_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE11; + tmp |= value << PIO_DRIVER_LINE11_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE11_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE11; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE12) >> PIO_DRIVER_LINE12_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE12; + tmp |= value << PIO_DRIVER_LINE12_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE12_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE12; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE13) >> PIO_DRIVER_LINE13_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE13; + tmp |= value << PIO_DRIVER_LINE13_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE13_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE13; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE14) >> PIO_DRIVER_LINE14_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE14; + tmp |= value << PIO_DRIVER_LINE14_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE14_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE14; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE15) >> PIO_DRIVER_LINE15_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE15; + tmp |= value << PIO_DRIVER_LINE15_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE15_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE15; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE16) >> PIO_DRIVER_LINE16_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE16; + tmp |= value << PIO_DRIVER_LINE16_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE16_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE16; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE17) >> PIO_DRIVER_LINE17_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE17; + tmp |= value << PIO_DRIVER_LINE17_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE17_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE17; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE18) >> PIO_DRIVER_LINE18_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE18; + tmp |= value << PIO_DRIVER_LINE18_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE18_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE18; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE19) >> PIO_DRIVER_LINE19_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE19; + tmp |= value << PIO_DRIVER_LINE19_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE19_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE19; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE20) >> PIO_DRIVER_LINE20_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE20; + tmp |= value << PIO_DRIVER_LINE20_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE20_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE20; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE21) >> PIO_DRIVER_LINE21_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE21; + tmp |= value << PIO_DRIVER_LINE21_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE21_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE21; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE22) >> PIO_DRIVER_LINE22_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE22; + tmp |= value << PIO_DRIVER_LINE22_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE22_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE22; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE23) >> PIO_DRIVER_LINE23_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE23; + tmp |= value << PIO_DRIVER_LINE23_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE23_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE23; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE24) >> PIO_DRIVER_LINE24_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE24; + tmp |= value << PIO_DRIVER_LINE24_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE24_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE24; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE25) >> PIO_DRIVER_LINE25_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE25; + tmp |= value << PIO_DRIVER_LINE25_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE25_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE25; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE26) >> PIO_DRIVER_LINE26_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE26; + tmp |= value << PIO_DRIVER_LINE26_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE26_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE26; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE27) >> PIO_DRIVER_LINE27_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE27; + tmp |= value << PIO_DRIVER_LINE27_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE27_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE27; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE28) >> PIO_DRIVER_LINE28_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE28; + tmp |= value << PIO_DRIVER_LINE28_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE28_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE28; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE29) >> PIO_DRIVER_LINE29_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE29; + tmp |= value << PIO_DRIVER_LINE29_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE29_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE29; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE30) >> PIO_DRIVER_LINE30_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE30; + tmp |= value << PIO_DRIVER_LINE30_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE30_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE30; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_LINE31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= PIO_DRIVER_LINE31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_DRIVER_LINE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp = (tmp & PIO_DRIVER_LINE31) >> PIO_DRIVER_LINE31_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_DRIVER_LINE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= ~PIO_DRIVER_LINE31; + tmp |= value << PIO_DRIVER_LINE31_Pos; + ((Pio *)hw)->PIO_DRIVER = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_LINE31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~PIO_DRIVER_LINE31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_LINE31_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= PIO_DRIVER_LINE31; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_DRIVER_reg(const void *const hw, hri_pio_driver_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_driver_reg_t hri_pio_get_DRIVER_reg(const void *const hw, hri_pio_driver_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_DRIVER; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_DRIVER_reg(const void *const hw, hri_pio_driver_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_DRIVER_reg(const void *const hw, hri_pio_driver_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_DRIVER_reg(const void *const hw, hri_pio_driver_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_DRIVER ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_driver_reg_t hri_pio_read_DRIVER_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_DRIVER; +} + +static inline void hri_pio_set_PCMR_PCEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= PIO_PCMR_PCEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_PCMR_PCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_PCEN) >> PIO_PCMR_PCEN_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_PCMR_PCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= ~PIO_PCMR_PCEN; + tmp |= value << PIO_PCMR_PCEN_Pos; + ((Pio *)hw)->PIO_PCMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_PCEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~PIO_PCMR_PCEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_PCEN_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= PIO_PCMR_PCEN; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_PCMR_ALWYS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= PIO_PCMR_ALWYS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_PCMR_ALWYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_ALWYS) >> PIO_PCMR_ALWYS_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_PCMR_ALWYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= ~PIO_PCMR_ALWYS; + tmp |= value << PIO_PCMR_ALWYS_Pos; + ((Pio *)hw)->PIO_PCMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_ALWYS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~PIO_PCMR_ALWYS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_ALWYS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= PIO_PCMR_ALWYS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_PCMR_HALFS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= PIO_PCMR_HALFS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_PCMR_HALFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_HALFS) >> PIO_PCMR_HALFS_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_PCMR_HALFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= ~PIO_PCMR_HALFS; + tmp |= value << PIO_PCMR_HALFS_Pos; + ((Pio *)hw)->PIO_PCMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_HALFS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~PIO_PCMR_HALFS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_HALFS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= PIO_PCMR_HALFS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_PCMR_FRSTS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= PIO_PCMR_FRSTS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pio_get_PCMR_FRSTS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_FRSTS) >> PIO_PCMR_FRSTS_Pos; + return (bool)tmp; +} + +static inline void hri_pio_write_PCMR_FRSTS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= ~PIO_PCMR_FRSTS; + tmp |= value << PIO_PCMR_FRSTS_Pos; + ((Pio *)hw)->PIO_PCMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_FRSTS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~PIO_PCMR_FRSTS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_FRSTS_bit(const void *const hw) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= PIO_PCMR_FRSTS; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_set_PCMR_DSIZE_bf(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= PIO_PCMR_DSIZE(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_pcmr_reg_t hri_pio_get_PCMR_DSIZE_bf(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_DSIZE(mask)) >> PIO_PCMR_DSIZE_Pos; + return tmp; +} + +static inline void hri_pio_write_PCMR_DSIZE_bf(const void *const hw, hri_pio_pcmr_reg_t data) +{ + uint32_t tmp; + PIO_CRITICAL_SECTION_ENTER(); + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= ~PIO_PCMR_DSIZE_Msk; + tmp |= PIO_PCMR_DSIZE(data); + ((Pio *)hw)->PIO_PCMR = tmp; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_DSIZE_bf(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~PIO_PCMR_DSIZE(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_DSIZE_bf(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= PIO_PCMR_DSIZE(mask); + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_pcmr_reg_t hri_pio_read_PCMR_DSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp = (tmp & PIO_PCMR_DSIZE_Msk) >> PIO_PCMR_DSIZE_Pos; + return tmp; +} + +static inline void hri_pio_set_PCMR_reg(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR |= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_pcmr_reg_t hri_pio_get_PCMR_reg(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pio *)hw)->PIO_PCMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pio_write_PCMR_reg(const void *const hw, hri_pio_pcmr_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_clear_PCMR_reg(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR &= ~mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_toggle_PCMR_reg(const void *const hw, hri_pio_pcmr_reg_t mask) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCMR ^= mask; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pio_pcmr_reg_t hri_pio_read_PCMR_reg(const void *const hw) +{ + return ((Pio *)hw)->PIO_PCMR; +} + +static inline void hri_pio_write_PCIER_reg(const void *const hw, hri_pio_pcier_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCIER = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pio_write_PCIDR_reg(const void *const hw, hri_pio_pcidr_reg_t data) +{ + PIO_CRITICAL_SECTION_ENTER(); + ((Pio *)hw)->PIO_PCIDR = data; + PIO_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PIO_E70B_H_INCLUDED */ +#endif /* _SAME70_PIO_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_pmc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_pmc_e70b.h new file mode 100644 index 0000000000..b0f1597dc8 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_pmc_e70b.h @@ -0,0 +1,7618 @@ +/** + * \file + * + * \brief SAM PMC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_PMC_COMPONENT_ +#ifndef _HRI_PMC_E70B_H_INCLUDED_ +#define _HRI_PMC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PMC_CRITICAL_SECTIONS) +#define PMC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PMC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PMC_CRITICAL_SECTION_ENTER() +#define PMC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pmc_ckgr_mcfr_reg_t; +typedef uint32_t hri_pmc_ckgr_mor_reg_t; +typedef uint32_t hri_pmc_ckgr_pllar_reg_t; +typedef uint32_t hri_pmc_ckgr_uckr_reg_t; +typedef uint32_t hri_pmc_focr_reg_t; +typedef uint32_t hri_pmc_fsmr_reg_t; +typedef uint32_t hri_pmc_fspr_reg_t; +typedef uint32_t hri_pmc_imr_reg_t; +typedef uint32_t hri_pmc_mckr_reg_t; +typedef uint32_t hri_pmc_ocr_reg_t; +typedef uint32_t hri_pmc_pck_reg_t; +typedef uint32_t hri_pmc_pcr_reg_t; +typedef uint32_t hri_pmc_pcsr0_reg_t; +typedef uint32_t hri_pmc_pcsr1_reg_t; +typedef uint32_t hri_pmc_pmmr_reg_t; +typedef uint32_t hri_pmc_scsr_reg_t; +typedef uint32_t hri_pmc_slpwk_aipr_reg_t; +typedef uint32_t hri_pmc_slpwk_asr0_reg_t; +typedef uint32_t hri_pmc_slpwk_asr1_reg_t; +typedef uint32_t hri_pmc_slpwk_sr0_reg_t; +typedef uint32_t hri_pmc_slpwk_sr1_reg_t; +typedef uint32_t hri_pmc_sr_reg_t; +typedef uint32_t hri_pmc_usb_reg_t; +typedef uint32_t hri_pmc_wpmr_reg_t; +typedef uint32_t hri_pmc_wpsr_reg_t; + +static inline bool hri_pmc_get_SCSR_HCLKS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_HCLKS) >> PMC_SCSR_HCLKS_Pos; +} + +static inline void hri_pmc_set_SCSR_USBCLK_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_USBCLK; +} + +static inline bool hri_pmc_get_SCSR_USBCLK_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_USBCLK) >> PMC_SCSR_USBCLK_Pos; +} + +static inline void hri_pmc_write_SCSR_USBCLK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_USBCLK; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_USBCLK; + } +} + +static inline void hri_pmc_clear_SCSR_USBCLK_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_USBCLK; +} + +static inline void hri_pmc_set_SCSR_PCK0_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK0; +} + +static inline bool hri_pmc_get_SCSR_PCK0_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK0) >> PMC_SCSR_PCK0_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK0; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK0; + } +} + +static inline void hri_pmc_clear_SCSR_PCK0_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK0; +} + +static inline void hri_pmc_set_SCSR_PCK1_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK1; +} + +static inline bool hri_pmc_get_SCSR_PCK1_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK1) >> PMC_SCSR_PCK1_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK1; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK1; + } +} + +static inline void hri_pmc_clear_SCSR_PCK1_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK1; +} + +static inline void hri_pmc_set_SCSR_PCK2_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK2; +} + +static inline bool hri_pmc_get_SCSR_PCK2_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK2) >> PMC_SCSR_PCK2_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK2; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK2; + } +} + +static inline void hri_pmc_clear_SCSR_PCK2_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK2; +} + +static inline void hri_pmc_set_SCSR_PCK3_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK3; +} + +static inline bool hri_pmc_get_SCSR_PCK3_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK3) >> PMC_SCSR_PCK3_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK3; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK3; + } +} + +static inline void hri_pmc_clear_SCSR_PCK3_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK3; +} + +static inline void hri_pmc_set_SCSR_PCK4_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK4; +} + +static inline bool hri_pmc_get_SCSR_PCK4_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK4) >> PMC_SCSR_PCK4_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK4; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK4; + } +} + +static inline void hri_pmc_clear_SCSR_PCK4_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK4; +} + +static inline void hri_pmc_set_SCSR_PCK5_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK5; +} + +static inline bool hri_pmc_get_SCSR_PCK5_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK5) >> PMC_SCSR_PCK5_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK5; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK5; + } +} + +static inline void hri_pmc_clear_SCSR_PCK5_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK5; +} + +static inline void hri_pmc_set_SCSR_PCK6_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK6; +} + +static inline bool hri_pmc_get_SCSR_PCK6_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK6) >> PMC_SCSR_PCK6_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK6; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK6; + } +} + +static inline void hri_pmc_clear_SCSR_PCK6_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK6; +} + +static inline void hri_pmc_set_SCSR_PCK7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK7; +} + +static inline bool hri_pmc_get_SCSR_PCK7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SCSR & PMC_SCSR_PCK7) >> PMC_SCSR_PCK7_Pos; +} + +static inline void hri_pmc_write_SCSR_PCK7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK7; + } else { + ((Pmc *)hw)->PMC_SCER = PMC_SCSR_PCK7; + } +} + +static inline void hri_pmc_clear_SCSR_PCK7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SCDR = PMC_SCSR_PCK7; +} + +static inline void hri_pmc_set_SCSR_reg(const void *const hw, hri_pmc_scsr_reg_t mask) +{ + ((Pmc *)hw)->PMC_SCER = mask; +} + +static inline hri_pmc_scsr_reg_t hri_pmc_get_SCSR_reg(const void *const hw, hri_pmc_scsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SCSR; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_scsr_reg_t hri_pmc_read_SCSR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SCSR; +} + +static inline void hri_pmc_write_SCSR_reg(const void *const hw, hri_pmc_scsr_reg_t data) +{ + ((Pmc *)hw)->PMC_SCER = data; + ((Pmc *)hw)->PMC_SCDR = ~data; +} + +static inline void hri_pmc_clear_SCSR_reg(const void *const hw, hri_pmc_scsr_reg_t mask) +{ + ((Pmc *)hw)->PMC_SCDR = mask; +} + +static inline void hri_pmc_write_SCDR_reg(const void *const hw, hri_pmc_scsr_reg_t data) +{ + ((Pmc *)hw)->PMC_SCDR = data; +} + +static inline void hri_pmc_write_SCER_reg(const void *const hw, hri_pmc_scsr_reg_t data) +{ + ((Pmc *)hw)->PMC_SCER = data; +} + +static inline void hri_pmc_set_PCSR0_PID7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID7; +} + +static inline bool hri_pmc_get_PCSR0_PID7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID7) >> PMC_PCSR0_PID7_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID7; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID7; + } +} + +static inline void hri_pmc_clear_PCSR0_PID7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID7; +} + +static inline void hri_pmc_set_PCSR0_PID8_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID8; +} + +static inline bool hri_pmc_get_PCSR0_PID8_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID8) >> PMC_PCSR0_PID8_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID8; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID8; + } +} + +static inline void hri_pmc_clear_PCSR0_PID8_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID8; +} + +static inline void hri_pmc_set_PCSR0_PID9_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID9; +} + +static inline bool hri_pmc_get_PCSR0_PID9_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID9) >> PMC_PCSR0_PID9_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID9; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID9; + } +} + +static inline void hri_pmc_clear_PCSR0_PID9_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID9; +} + +static inline void hri_pmc_set_PCSR0_PID10_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID10; +} + +static inline bool hri_pmc_get_PCSR0_PID10_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID10) >> PMC_PCSR0_PID10_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID10; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID10; + } +} + +static inline void hri_pmc_clear_PCSR0_PID10_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID10; +} + +static inline void hri_pmc_set_PCSR0_PID11_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID11; +} + +static inline bool hri_pmc_get_PCSR0_PID11_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID11) >> PMC_PCSR0_PID11_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID11; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID11; + } +} + +static inline void hri_pmc_clear_PCSR0_PID11_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID11; +} + +static inline void hri_pmc_set_PCSR0_PID12_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID12; +} + +static inline bool hri_pmc_get_PCSR0_PID12_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID12) >> PMC_PCSR0_PID12_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID12; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID12; + } +} + +static inline void hri_pmc_clear_PCSR0_PID12_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID12; +} + +static inline void hri_pmc_set_PCSR0_PID13_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID13; +} + +static inline bool hri_pmc_get_PCSR0_PID13_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID13) >> PMC_PCSR0_PID13_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID13; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID13; + } +} + +static inline void hri_pmc_clear_PCSR0_PID13_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID13; +} + +static inline void hri_pmc_set_PCSR0_PID14_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID14; +} + +static inline bool hri_pmc_get_PCSR0_PID14_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID14) >> PMC_PCSR0_PID14_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID14; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID14; + } +} + +static inline void hri_pmc_clear_PCSR0_PID14_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID14; +} + +static inline void hri_pmc_set_PCSR0_PID15_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID15; +} + +static inline bool hri_pmc_get_PCSR0_PID15_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID15) >> PMC_PCSR0_PID15_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID15; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID15; + } +} + +static inline void hri_pmc_clear_PCSR0_PID15_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID15; +} + +static inline void hri_pmc_set_PCSR0_PID16_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID16; +} + +static inline bool hri_pmc_get_PCSR0_PID16_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID16) >> PMC_PCSR0_PID16_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID16; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID16; + } +} + +static inline void hri_pmc_clear_PCSR0_PID16_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID16; +} + +static inline void hri_pmc_set_PCSR0_PID17_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID17; +} + +static inline bool hri_pmc_get_PCSR0_PID17_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID17) >> PMC_PCSR0_PID17_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID17; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID17; + } +} + +static inline void hri_pmc_clear_PCSR0_PID17_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID17; +} + +static inline void hri_pmc_set_PCSR0_PID18_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID18; +} + +static inline bool hri_pmc_get_PCSR0_PID18_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID18) >> PMC_PCSR0_PID18_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID18; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID18; + } +} + +static inline void hri_pmc_clear_PCSR0_PID18_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID18; +} + +static inline void hri_pmc_set_PCSR0_PID19_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID19; +} + +static inline bool hri_pmc_get_PCSR0_PID19_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID19) >> PMC_PCSR0_PID19_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID19; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID19; + } +} + +static inline void hri_pmc_clear_PCSR0_PID19_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID19; +} + +static inline void hri_pmc_set_PCSR0_PID20_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID20; +} + +static inline bool hri_pmc_get_PCSR0_PID20_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID20) >> PMC_PCSR0_PID20_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID20; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID20; + } +} + +static inline void hri_pmc_clear_PCSR0_PID20_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID20; +} + +static inline void hri_pmc_set_PCSR0_PID21_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID21; +} + +static inline bool hri_pmc_get_PCSR0_PID21_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID21) >> PMC_PCSR0_PID21_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID21; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID21; + } +} + +static inline void hri_pmc_clear_PCSR0_PID21_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID21; +} + +static inline void hri_pmc_set_PCSR0_PID22_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID22; +} + +static inline bool hri_pmc_get_PCSR0_PID22_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID22) >> PMC_PCSR0_PID22_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID22; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID22; + } +} + +static inline void hri_pmc_clear_PCSR0_PID22_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID22; +} + +static inline void hri_pmc_set_PCSR0_PID23_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID23; +} + +static inline bool hri_pmc_get_PCSR0_PID23_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID23) >> PMC_PCSR0_PID23_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID23; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID23; + } +} + +static inline void hri_pmc_clear_PCSR0_PID23_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID23; +} + +static inline void hri_pmc_set_PCSR0_PID24_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID24; +} + +static inline bool hri_pmc_get_PCSR0_PID24_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID24) >> PMC_PCSR0_PID24_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID24; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID24; + } +} + +static inline void hri_pmc_clear_PCSR0_PID24_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID24; +} + +static inline void hri_pmc_set_PCSR0_PID25_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID25; +} + +static inline bool hri_pmc_get_PCSR0_PID25_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID25) >> PMC_PCSR0_PID25_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID25; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID25; + } +} + +static inline void hri_pmc_clear_PCSR0_PID25_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID25; +} + +static inline void hri_pmc_set_PCSR0_PID26_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID26; +} + +static inline bool hri_pmc_get_PCSR0_PID26_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID26) >> PMC_PCSR0_PID26_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID26; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID26; + } +} + +static inline void hri_pmc_clear_PCSR0_PID26_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID26; +} + +static inline void hri_pmc_set_PCSR0_PID27_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID27; +} + +static inline bool hri_pmc_get_PCSR0_PID27_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID27) >> PMC_PCSR0_PID27_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID27; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID27; + } +} + +static inline void hri_pmc_clear_PCSR0_PID27_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID27; +} + +static inline void hri_pmc_set_PCSR0_PID28_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID28; +} + +static inline bool hri_pmc_get_PCSR0_PID28_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID28) >> PMC_PCSR0_PID28_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID28; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID28; + } +} + +static inline void hri_pmc_clear_PCSR0_PID28_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID28; +} + +static inline void hri_pmc_set_PCSR0_PID29_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID29; +} + +static inline bool hri_pmc_get_PCSR0_PID29_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID29) >> PMC_PCSR0_PID29_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID29; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID29; + } +} + +static inline void hri_pmc_clear_PCSR0_PID29_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID29; +} + +static inline void hri_pmc_set_PCSR0_PID30_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID30; +} + +static inline bool hri_pmc_get_PCSR0_PID30_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID30) >> PMC_PCSR0_PID30_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID30; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID30; + } +} + +static inline void hri_pmc_clear_PCSR0_PID30_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID30; +} + +static inline void hri_pmc_set_PCSR0_PID31_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID31; +} + +static inline bool hri_pmc_get_PCSR0_PID31_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR0 & PMC_PCSR0_PID31) >> PMC_PCSR0_PID31_Pos; +} + +static inline void hri_pmc_write_PCSR0_PID31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID31; + } else { + ((Pmc *)hw)->PMC_PCER0 = PMC_PCSR0_PID31; + } +} + +static inline void hri_pmc_clear_PCSR0_PID31_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR0 = PMC_PCSR0_PID31; +} + +static inline void hri_pmc_set_PCSR0_reg(const void *const hw, hri_pmc_pcsr0_reg_t mask) +{ + ((Pmc *)hw)->PMC_PCER0 = mask; +} + +static inline hri_pmc_pcsr0_reg_t hri_pmc_get_PCSR0_reg(const void *const hw, hri_pmc_pcsr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCSR0; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_pcsr0_reg_t hri_pmc_read_PCSR0_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_PCSR0; +} + +static inline void hri_pmc_write_PCSR0_reg(const void *const hw, hri_pmc_pcsr0_reg_t data) +{ + ((Pmc *)hw)->PMC_PCER0 = data; + ((Pmc *)hw)->PMC_PCDR0 = ~data; +} + +static inline void hri_pmc_clear_PCSR0_reg(const void *const hw, hri_pmc_pcsr0_reg_t mask) +{ + ((Pmc *)hw)->PMC_PCDR0 = mask; +} + +static inline void hri_pmc_set_IMR_MOSCXTS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCXTS; +} + +static inline bool hri_pmc_get_IMR_MOSCXTS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_MOSCXTS) >> PMC_IMR_MOSCXTS_Pos; +} + +static inline void hri_pmc_write_IMR_MOSCXTS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCXTS; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCXTS; + } +} + +static inline void hri_pmc_clear_IMR_MOSCXTS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCXTS; +} + +static inline void hri_pmc_set_IMR_LOCKA_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_LOCKA; +} + +static inline bool hri_pmc_get_IMR_LOCKA_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_LOCKA) >> PMC_IMR_LOCKA_Pos; +} + +static inline void hri_pmc_write_IMR_LOCKA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_LOCKA; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_LOCKA; + } +} + +static inline void hri_pmc_clear_IMR_LOCKA_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_LOCKA; +} + +static inline void hri_pmc_set_IMR_MCKRDY_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_MCKRDY; +} + +static inline bool hri_pmc_get_IMR_MCKRDY_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_MCKRDY) >> PMC_IMR_MCKRDY_Pos; +} + +static inline void hri_pmc_write_IMR_MCKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MCKRDY; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_MCKRDY; + } +} + +static inline void hri_pmc_clear_IMR_MCKRDY_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MCKRDY; +} + +static inline void hri_pmc_set_IMR_LOCKU_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_LOCKU; +} + +static inline bool hri_pmc_get_IMR_LOCKU_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_LOCKU) >> PMC_IMR_LOCKU_Pos; +} + +static inline void hri_pmc_write_IMR_LOCKU_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_LOCKU; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_LOCKU; + } +} + +static inline void hri_pmc_clear_IMR_LOCKU_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_LOCKU; +} + +static inline void hri_pmc_set_IMR_PCKRDY0_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY0; +} + +static inline bool hri_pmc_get_IMR_PCKRDY0_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY0) >> PMC_IMR_PCKRDY0_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY0; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY0; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY0_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY0; +} + +static inline void hri_pmc_set_IMR_PCKRDY1_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY1; +} + +static inline bool hri_pmc_get_IMR_PCKRDY1_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY1) >> PMC_IMR_PCKRDY1_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY1; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY1; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY1_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY1; +} + +static inline void hri_pmc_set_IMR_PCKRDY2_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY2; +} + +static inline bool hri_pmc_get_IMR_PCKRDY2_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY2) >> PMC_IMR_PCKRDY2_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY2; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY2; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY2_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY2; +} + +static inline void hri_pmc_set_IMR_PCKRDY3_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY3; +} + +static inline bool hri_pmc_get_IMR_PCKRDY3_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY3) >> PMC_IMR_PCKRDY3_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY3; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY3; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY3_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY3; +} + +static inline void hri_pmc_set_IMR_PCKRDY4_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY4; +} + +static inline bool hri_pmc_get_IMR_PCKRDY4_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY4) >> PMC_IMR_PCKRDY4_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY4; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY4; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY4_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY4; +} + +static inline void hri_pmc_set_IMR_PCKRDY5_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY5; +} + +static inline bool hri_pmc_get_IMR_PCKRDY5_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY5) >> PMC_IMR_PCKRDY5_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY5; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY5; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY5_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY5; +} + +static inline void hri_pmc_set_IMR_PCKRDY6_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY6; +} + +static inline bool hri_pmc_get_IMR_PCKRDY6_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY6) >> PMC_IMR_PCKRDY6_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY6; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY6; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY6_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY6; +} + +static inline void hri_pmc_set_IMR_PCKRDY7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY7; +} + +static inline bool hri_pmc_get_IMR_PCKRDY7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_PCKRDY7) >> PMC_IMR_PCKRDY7_Pos; +} + +static inline void hri_pmc_write_IMR_PCKRDY7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY7; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_PCKRDY7; + } +} + +static inline void hri_pmc_clear_IMR_PCKRDY7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_PCKRDY7; +} + +static inline void hri_pmc_set_IMR_MOSCSELS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCSELS; +} + +static inline bool hri_pmc_get_IMR_MOSCSELS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_MOSCSELS) >> PMC_IMR_MOSCSELS_Pos; +} + +static inline void hri_pmc_write_IMR_MOSCSELS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCSELS; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCSELS; + } +} + +static inline void hri_pmc_clear_IMR_MOSCSELS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCSELS; +} + +static inline void hri_pmc_set_IMR_MOSCRCS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCRCS; +} + +static inline bool hri_pmc_get_IMR_MOSCRCS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_MOSCRCS) >> PMC_IMR_MOSCRCS_Pos; +} + +static inline void hri_pmc_write_IMR_MOSCRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCRCS; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_MOSCRCS; + } +} + +static inline void hri_pmc_clear_IMR_MOSCRCS_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_MOSCRCS; +} + +static inline void hri_pmc_set_IMR_CFDEV_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_CFDEV; +} + +static inline bool hri_pmc_get_IMR_CFDEV_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_CFDEV) >> PMC_IMR_CFDEV_Pos; +} + +static inline void hri_pmc_write_IMR_CFDEV_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_CFDEV; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_CFDEV; + } +} + +static inline void hri_pmc_clear_IMR_CFDEV_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_CFDEV; +} + +static inline void hri_pmc_set_IMR_XT32KERR_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IER = PMC_IMR_XT32KERR; +} + +static inline bool hri_pmc_get_IMR_XT32KERR_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_IMR & PMC_IMR_XT32KERR) >> PMC_IMR_XT32KERR_Pos; +} + +static inline void hri_pmc_write_IMR_XT32KERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_IDR = PMC_IMR_XT32KERR; + } else { + ((Pmc *)hw)->PMC_IER = PMC_IMR_XT32KERR; + } +} + +static inline void hri_pmc_clear_IMR_XT32KERR_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_IDR = PMC_IMR_XT32KERR; +} + +static inline void hri_pmc_set_IMR_reg(const void *const hw, hri_pmc_imr_reg_t mask) +{ + ((Pmc *)hw)->PMC_IER = mask; +} + +static inline hri_pmc_imr_reg_t hri_pmc_get_IMR_reg(const void *const hw, hri_pmc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_imr_reg_t hri_pmc_read_IMR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_IMR; +} + +static inline void hri_pmc_write_IMR_reg(const void *const hw, hri_pmc_imr_reg_t data) +{ + ((Pmc *)hw)->PMC_IER = data; + ((Pmc *)hw)->PMC_IDR = ~data; +} + +static inline void hri_pmc_clear_IMR_reg(const void *const hw, hri_pmc_imr_reg_t mask) +{ + ((Pmc *)hw)->PMC_IDR = mask; +} + +static inline void hri_pmc_set_PCSR1_PID32_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID32; +} + +static inline bool hri_pmc_get_PCSR1_PID32_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID32) >> PMC_PCSR1_PID32_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID32_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID32; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID32; + } +} + +static inline void hri_pmc_clear_PCSR1_PID32_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID32; +} + +static inline void hri_pmc_set_PCSR1_PID33_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID33; +} + +static inline bool hri_pmc_get_PCSR1_PID33_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID33) >> PMC_PCSR1_PID33_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID33_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID33; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID33; + } +} + +static inline void hri_pmc_clear_PCSR1_PID33_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID33; +} + +static inline void hri_pmc_set_PCSR1_PID34_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID34; +} + +static inline bool hri_pmc_get_PCSR1_PID34_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID34) >> PMC_PCSR1_PID34_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID34_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID34; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID34; + } +} + +static inline void hri_pmc_clear_PCSR1_PID34_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID34; +} + +static inline void hri_pmc_set_PCSR1_PID35_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID35; +} + +static inline bool hri_pmc_get_PCSR1_PID35_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID35) >> PMC_PCSR1_PID35_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID35_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID35; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID35; + } +} + +static inline void hri_pmc_clear_PCSR1_PID35_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID35; +} + +static inline void hri_pmc_set_PCSR1_PID37_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID37; +} + +static inline bool hri_pmc_get_PCSR1_PID37_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID37) >> PMC_PCSR1_PID37_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID37_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID37; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID37; + } +} + +static inline void hri_pmc_clear_PCSR1_PID37_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID37; +} + +static inline void hri_pmc_set_PCSR1_PID39_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID39; +} + +static inline bool hri_pmc_get_PCSR1_PID39_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID39) >> PMC_PCSR1_PID39_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID39_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID39; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID39; + } +} + +static inline void hri_pmc_clear_PCSR1_PID39_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID39; +} + +static inline void hri_pmc_set_PCSR1_PID40_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID40; +} + +static inline bool hri_pmc_get_PCSR1_PID40_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID40) >> PMC_PCSR1_PID40_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID40_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID40; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID40; + } +} + +static inline void hri_pmc_clear_PCSR1_PID40_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID40; +} + +static inline void hri_pmc_set_PCSR1_PID41_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID41; +} + +static inline bool hri_pmc_get_PCSR1_PID41_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID41) >> PMC_PCSR1_PID41_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID41_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID41; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID41; + } +} + +static inline void hri_pmc_clear_PCSR1_PID41_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID41; +} + +static inline void hri_pmc_set_PCSR1_PID42_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID42; +} + +static inline bool hri_pmc_get_PCSR1_PID42_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID42) >> PMC_PCSR1_PID42_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID42_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID42; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID42; + } +} + +static inline void hri_pmc_clear_PCSR1_PID42_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID42; +} + +static inline void hri_pmc_set_PCSR1_PID43_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID43; +} + +static inline bool hri_pmc_get_PCSR1_PID43_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID43) >> PMC_PCSR1_PID43_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID43_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID43; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID43; + } +} + +static inline void hri_pmc_clear_PCSR1_PID43_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID43; +} + +static inline void hri_pmc_set_PCSR1_PID44_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID44; +} + +static inline bool hri_pmc_get_PCSR1_PID44_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID44) >> PMC_PCSR1_PID44_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID44_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID44; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID44; + } +} + +static inline void hri_pmc_clear_PCSR1_PID44_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID44; +} + +static inline void hri_pmc_set_PCSR1_PID45_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID45; +} + +static inline bool hri_pmc_get_PCSR1_PID45_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID45) >> PMC_PCSR1_PID45_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID45_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID45; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID45; + } +} + +static inline void hri_pmc_clear_PCSR1_PID45_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID45; +} + +static inline void hri_pmc_set_PCSR1_PID46_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID46; +} + +static inline bool hri_pmc_get_PCSR1_PID46_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID46) >> PMC_PCSR1_PID46_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID46_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID46; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID46; + } +} + +static inline void hri_pmc_clear_PCSR1_PID46_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID46; +} + +static inline void hri_pmc_set_PCSR1_PID47_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID47; +} + +static inline bool hri_pmc_get_PCSR1_PID47_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID47) >> PMC_PCSR1_PID47_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID47_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID47; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID47; + } +} + +static inline void hri_pmc_clear_PCSR1_PID47_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID47; +} + +static inline void hri_pmc_set_PCSR1_PID48_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID48; +} + +static inline bool hri_pmc_get_PCSR1_PID48_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID48) >> PMC_PCSR1_PID48_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID48_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID48; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID48; + } +} + +static inline void hri_pmc_clear_PCSR1_PID48_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID48; +} + +static inline void hri_pmc_set_PCSR1_PID49_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID49; +} + +static inline bool hri_pmc_get_PCSR1_PID49_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID49) >> PMC_PCSR1_PID49_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID49_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID49; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID49; + } +} + +static inline void hri_pmc_clear_PCSR1_PID49_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID49; +} + +static inline void hri_pmc_set_PCSR1_PID50_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID50; +} + +static inline bool hri_pmc_get_PCSR1_PID50_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID50) >> PMC_PCSR1_PID50_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID50_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID50; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID50; + } +} + +static inline void hri_pmc_clear_PCSR1_PID50_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID50; +} + +static inline void hri_pmc_set_PCSR1_PID51_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID51; +} + +static inline bool hri_pmc_get_PCSR1_PID51_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID51) >> PMC_PCSR1_PID51_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID51_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID51; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID51; + } +} + +static inline void hri_pmc_clear_PCSR1_PID51_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID51; +} + +static inline void hri_pmc_set_PCSR1_PID52_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID52; +} + +static inline bool hri_pmc_get_PCSR1_PID52_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID52) >> PMC_PCSR1_PID52_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID52_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID52; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID52; + } +} + +static inline void hri_pmc_clear_PCSR1_PID52_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID52; +} + +static inline void hri_pmc_set_PCSR1_PID56_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID56; +} + +static inline bool hri_pmc_get_PCSR1_PID56_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID56) >> PMC_PCSR1_PID56_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID56_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID56; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID56; + } +} + +static inline void hri_pmc_clear_PCSR1_PID56_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID56; +} + +static inline void hri_pmc_set_PCSR1_PID57_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID57; +} + +static inline bool hri_pmc_get_PCSR1_PID57_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID57) >> PMC_PCSR1_PID57_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID57_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID57; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID57; + } +} + +static inline void hri_pmc_clear_PCSR1_PID57_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID57; +} + +static inline void hri_pmc_set_PCSR1_PID58_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID58; +} + +static inline bool hri_pmc_get_PCSR1_PID58_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID58) >> PMC_PCSR1_PID58_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID58_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID58; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID58; + } +} + +static inline void hri_pmc_clear_PCSR1_PID58_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID58; +} + +static inline void hri_pmc_set_PCSR1_PID59_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID59; +} + +static inline bool hri_pmc_get_PCSR1_PID59_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID59) >> PMC_PCSR1_PID59_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID59_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID59; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID59; + } +} + +static inline void hri_pmc_clear_PCSR1_PID59_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID59; +} + +static inline void hri_pmc_set_PCSR1_PID60_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID60; +} + +static inline bool hri_pmc_get_PCSR1_PID60_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_PCSR1 & PMC_PCSR1_PID60) >> PMC_PCSR1_PID60_Pos; +} + +static inline void hri_pmc_write_PCSR1_PID60_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID60; + } else { + ((Pmc *)hw)->PMC_PCER1 = PMC_PCSR1_PID60; + } +} + +static inline void hri_pmc_clear_PCSR1_PID60_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_PCDR1 = PMC_PCSR1_PID60; +} + +static inline void hri_pmc_set_PCSR1_reg(const void *const hw, hri_pmc_pcsr1_reg_t mask) +{ + ((Pmc *)hw)->PMC_PCER1 = mask; +} + +static inline hri_pmc_pcsr1_reg_t hri_pmc_get_PCSR1_reg(const void *const hw, hri_pmc_pcsr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCSR1; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_pcsr1_reg_t hri_pmc_read_PCSR1_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_PCSR1; +} + +static inline void hri_pmc_write_PCSR1_reg(const void *const hw, hri_pmc_pcsr1_reg_t data) +{ + ((Pmc *)hw)->PMC_PCER1 = data; + ((Pmc *)hw)->PMC_PCDR1 = ~data; +} + +static inline void hri_pmc_clear_PCSR1_reg(const void *const hw, hri_pmc_pcsr1_reg_t mask) +{ + ((Pmc *)hw)->PMC_PCDR1 = mask; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID7; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID7) >> PMC_SLPWK_SR0_PID7_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID7; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID7; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID7_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID7; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID8_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID8; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID8_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID8) >> PMC_SLPWK_SR0_PID8_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID8; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID8; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID8_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID8; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID9_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID9; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID9_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID9) >> PMC_SLPWK_SR0_PID9_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID9; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID9; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID9_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID9; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID10_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID10; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID10_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID10) >> PMC_SLPWK_SR0_PID10_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID10; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID10; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID10_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID10; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID11_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID11; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID11_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID11) >> PMC_SLPWK_SR0_PID11_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID11; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID11; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID11_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID11; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID12_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID12; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID12_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID12) >> PMC_SLPWK_SR0_PID12_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID12; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID12; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID12_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID12; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID13_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID13; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID13_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID13) >> PMC_SLPWK_SR0_PID13_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID13; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID13; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID13_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID13; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID14_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID14; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID14_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID14) >> PMC_SLPWK_SR0_PID14_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID14; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID14; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID14_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID14; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID15_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID15; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID15_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID15) >> PMC_SLPWK_SR0_PID15_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID15; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID15; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID15_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID15; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID16_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID16; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID16_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID16) >> PMC_SLPWK_SR0_PID16_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID16; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID16; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID16_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID16; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID17_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID17; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID17_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID17) >> PMC_SLPWK_SR0_PID17_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID17; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID17; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID17_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID17; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID18_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID18; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID18_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID18) >> PMC_SLPWK_SR0_PID18_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID18; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID18; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID18_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID18; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID19_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID19; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID19_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID19) >> PMC_SLPWK_SR0_PID19_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID19; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID19; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID19_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID19; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID20_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID20; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID20_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID20) >> PMC_SLPWK_SR0_PID20_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID20; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID20; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID20_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID20; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID21_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID21; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID21_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID21) >> PMC_SLPWK_SR0_PID21_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID21; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID21; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID21_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID21; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID22_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID22; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID22_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID22) >> PMC_SLPWK_SR0_PID22_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID22; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID22; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID22_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID22; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID23_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID23; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID23_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID23) >> PMC_SLPWK_SR0_PID23_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID23; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID23; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID23_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID23; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID24_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID24; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID24_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID24) >> PMC_SLPWK_SR0_PID24_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID24_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID24; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID24; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID24_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID24; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID25_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID25; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID25_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID25) >> PMC_SLPWK_SR0_PID25_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID25_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID25; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID25; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID25_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID25; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID26_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID26; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID26_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID26) >> PMC_SLPWK_SR0_PID26_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID26_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID26; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID26; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID26_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID26; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID27_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID27; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID27_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID27) >> PMC_SLPWK_SR0_PID27_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID27_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID27; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID27; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID27_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID27; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID28_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID28; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID28_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID28) >> PMC_SLPWK_SR0_PID28_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID28_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID28; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID28; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID28_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID28; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID29_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID29; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID29_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID29) >> PMC_SLPWK_SR0_PID29_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID29_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID29; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID29; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID29_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID29; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID30_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID30; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID30_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID30) >> PMC_SLPWK_SR0_PID30_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID30_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID30; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID30; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID30_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID30; +} + +static inline void hri_pmc_set_SLPWK_SR0_PID31_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID31; +} + +static inline bool hri_pmc_get_SLPWK_SR0_PID31_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR0 & PMC_SLPWK_SR0_PID31) >> PMC_SLPWK_SR0_PID31_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR0_PID31_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID31; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER0 = PMC_SLPWK_SR0_PID31; + } +} + +static inline void hri_pmc_clear_SLPWK_SR0_PID31_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = PMC_SLPWK_SR0_PID31; +} + +static inline void hri_pmc_set_SLPWK_SR0_reg(const void *const hw, hri_pmc_slpwk_sr0_reg_t mask) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = mask; +} + +static inline hri_pmc_slpwk_sr0_reg_t hri_pmc_get_SLPWK_SR0_reg(const void *const hw, hri_pmc_slpwk_sr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SLPWK_SR0; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_slpwk_sr0_reg_t hri_pmc_read_SLPWK_SR0_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SLPWK_SR0; +} + +static inline void hri_pmc_write_SLPWK_SR0_reg(const void *const hw, hri_pmc_slpwk_sr0_reg_t data) +{ + ((Pmc *)hw)->PMC_SLPWK_ER0 = data; + ((Pmc *)hw)->PMC_SLPWK_DR0 = ~data; +} + +static inline void hri_pmc_clear_SLPWK_SR0_reg(const void *const hw, hri_pmc_slpwk_sr0_reg_t mask) +{ + ((Pmc *)hw)->PMC_SLPWK_DR0 = mask; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID32_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID32; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID32_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID32) >> PMC_SLPWK_SR1_PID32_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID32_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID32; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID32; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID32_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID32; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID33_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID33; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID33_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID33) >> PMC_SLPWK_SR1_PID33_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID33_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID33; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID33; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID33_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID33; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID34_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID34; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID34_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID34) >> PMC_SLPWK_SR1_PID34_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID34_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID34; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID34; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID34_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID34; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID35_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID35; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID35_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID35) >> PMC_SLPWK_SR1_PID35_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID35_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID35; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID35; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID35_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID35; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID37_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID37; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID37_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID37) >> PMC_SLPWK_SR1_PID37_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID37_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID37; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID37; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID37_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID37; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID39_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID39; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID39_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID39) >> PMC_SLPWK_SR1_PID39_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID39_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID39; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID39; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID39_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID39; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID40_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID40; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID40_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID40) >> PMC_SLPWK_SR1_PID40_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID40_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID40; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID40; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID40_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID40; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID41_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID41; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID41_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID41) >> PMC_SLPWK_SR1_PID41_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID41_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID41; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID41; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID41_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID41; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID42_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID42; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID42_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID42) >> PMC_SLPWK_SR1_PID42_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID42_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID42; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID42; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID42_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID42; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID43_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID43; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID43_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID43) >> PMC_SLPWK_SR1_PID43_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID43_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID43; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID43; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID43_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID43; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID44_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID44; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID44_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID44) >> PMC_SLPWK_SR1_PID44_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID44_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID44; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID44; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID44_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID44; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID45_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID45; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID45_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID45) >> PMC_SLPWK_SR1_PID45_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID45_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID45; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID45; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID45_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID45; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID46_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID46; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID46_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID46) >> PMC_SLPWK_SR1_PID46_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID46_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID46; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID46; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID46_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID46; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID47_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID47; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID47_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID47) >> PMC_SLPWK_SR1_PID47_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID47_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID47; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID47; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID47_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID47; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID48_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID48; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID48_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID48) >> PMC_SLPWK_SR1_PID48_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID48_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID48; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID48; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID48_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID48; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID49_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID49; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID49_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID49) >> PMC_SLPWK_SR1_PID49_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID49_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID49; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID49; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID49_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID49; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID50_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID50; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID50_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID50) >> PMC_SLPWK_SR1_PID50_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID50_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID50; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID50; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID50_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID50; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID51_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID51; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID51_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID51) >> PMC_SLPWK_SR1_PID51_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID51_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID51; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID51; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID51_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID51; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID52_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID52; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID52_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID52) >> PMC_SLPWK_SR1_PID52_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID52_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID52; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID52; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID52_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID52; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID56_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID56; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID56_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID56) >> PMC_SLPWK_SR1_PID56_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID56_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID56; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID56; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID56_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID56; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID57_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID57; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID57_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID57) >> PMC_SLPWK_SR1_PID57_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID57_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID57; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID57; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID57_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID57; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID58_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID58; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID58_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID58) >> PMC_SLPWK_SR1_PID58_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID58_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID58; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID58; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID58_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID58; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID59_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID59; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID59_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID59) >> PMC_SLPWK_SR1_PID59_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID59_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID59; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID59; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID59_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID59; +} + +static inline void hri_pmc_set_SLPWK_SR1_PID60_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID60; +} + +static inline bool hri_pmc_get_SLPWK_SR1_PID60_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_SR1 & PMC_SLPWK_SR1_PID60) >> PMC_SLPWK_SR1_PID60_Pos; +} + +static inline void hri_pmc_write_SLPWK_SR1_PID60_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID60; + } else { + ((Pmc *)hw)->PMC_SLPWK_ER1 = PMC_SLPWK_SR1_PID60; + } +} + +static inline void hri_pmc_clear_SLPWK_SR1_PID60_bit(const void *const hw) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = PMC_SLPWK_SR1_PID60; +} + +static inline void hri_pmc_set_SLPWK_SR1_reg(const void *const hw, hri_pmc_slpwk_sr1_reg_t mask) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = mask; +} + +static inline hri_pmc_slpwk_sr1_reg_t hri_pmc_get_SLPWK_SR1_reg(const void *const hw, hri_pmc_slpwk_sr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SLPWK_SR1; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_slpwk_sr1_reg_t hri_pmc_read_SLPWK_SR1_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SLPWK_SR1; +} + +static inline void hri_pmc_write_SLPWK_SR1_reg(const void *const hw, hri_pmc_slpwk_sr1_reg_t data) +{ + ((Pmc *)hw)->PMC_SLPWK_ER1 = data; + ((Pmc *)hw)->PMC_SLPWK_DR1 = ~data; +} + +static inline void hri_pmc_clear_SLPWK_SR1_reg(const void *const hw, hri_pmc_slpwk_sr1_reg_t mask) +{ + ((Pmc *)hw)->PMC_SLPWK_DR1 = mask; +} + +static inline bool hri_pmc_get_SR_MOSCXTS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_MOSCXTS) > 0; +} + +static inline bool hri_pmc_get_SR_LOCKA_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_LOCKA) > 0; +} + +static inline bool hri_pmc_get_SR_MCKRDY_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_MCKRDY) > 0; +} + +static inline bool hri_pmc_get_SR_LOCKU_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_LOCKU) > 0; +} + +static inline bool hri_pmc_get_SR_OSCSELS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_OSCSELS) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY0_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY0) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY1_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY1) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY2_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY2) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY3_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY3) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY4_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY4) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY5_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY5) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY6_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY6) > 0; +} + +static inline bool hri_pmc_get_SR_PCKRDY7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_PCKRDY7) > 0; +} + +static inline bool hri_pmc_get_SR_MOSCSELS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_MOSCSELS) > 0; +} + +static inline bool hri_pmc_get_SR_MOSCRCS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_MOSCRCS) > 0; +} + +static inline bool hri_pmc_get_SR_CFDEV_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_CFDEV) > 0; +} + +static inline bool hri_pmc_get_SR_CFDS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_CFDS) > 0; +} + +static inline bool hri_pmc_get_SR_FOS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_FOS) > 0; +} + +static inline bool hri_pmc_get_SR_XT32KERR_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SR & PMC_SR_XT32KERR) > 0; +} + +static inline hri_pmc_sr_reg_t hri_pmc_get_SR_reg(const void *const hw, hri_pmc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_sr_reg_t hri_pmc_read_SR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SR; +} + +static inline bool hri_pmc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_WPSR & PMC_WPSR_WPVS) > 0; +} + +static inline hri_pmc_wpsr_reg_t hri_pmc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pmc_wpsr_reg_t mask) +{ + return (((Pmc *)hw)->PMC_WPSR & PMC_WPSR_WPVSRC(mask)) >> PMC_WPSR_WPVSRC_Pos; +} + +static inline hri_pmc_wpsr_reg_t hri_pmc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pmc *)hw)->PMC_WPSR & PMC_WPSR_WPVSRC_Msk) >> PMC_WPSR_WPVSRC_Pos; +} + +static inline hri_pmc_wpsr_reg_t hri_pmc_get_WPSR_reg(const void *const hw, hri_pmc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_wpsr_reg_t hri_pmc_read_WPSR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_WPSR; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID7_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID7) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID8_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID8) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID9_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID9) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID10_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID10) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID11_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID11) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID12_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID12) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID13_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID13) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID14_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID14) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID15_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID15) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID16_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID16) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID17_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID17) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID18_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID18) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID19_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID19) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID20_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID20) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID21_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID21) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID22_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID22) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID23_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID23) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID24_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID24) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID25_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID25) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID26_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID26) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID27_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID27) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID28_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID28) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID29_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID29) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID30_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID30) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR0_PID31_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR0 & PMC_SLPWK_ASR0_PID31) > 0; +} + +static inline hri_pmc_slpwk_asr0_reg_t hri_pmc_get_SLPWK_ASR0_reg(const void *const hw, hri_pmc_slpwk_asr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SLPWK_ASR0; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_slpwk_asr0_reg_t hri_pmc_read_SLPWK_ASR0_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SLPWK_ASR0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID32_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID32) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID33_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID33) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID34_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID34) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID35_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID35) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID37_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID37) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID39_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID39) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID40_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID40) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID41_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID41) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID42_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID42) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID43_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID43) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID44_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID44) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID45_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID45) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID46_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID46) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID47_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID47) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID48_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID48) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID49_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID49) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID50_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID50) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID51_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID51) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID52_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID52) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID56_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID56) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID57_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID57) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID58_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID58) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID59_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID59) > 0; +} + +static inline bool hri_pmc_get_SLPWK_ASR1_PID60_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_ASR1 & PMC_SLPWK_ASR1_PID60) > 0; +} + +static inline hri_pmc_slpwk_asr1_reg_t hri_pmc_get_SLPWK_ASR1_reg(const void *const hw, hri_pmc_slpwk_asr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SLPWK_ASR1; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_slpwk_asr1_reg_t hri_pmc_read_SLPWK_ASR1_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SLPWK_ASR1; +} + +static inline bool hri_pmc_get_SLPWK_AIPR_AIP_bit(const void *const hw) +{ + return (((Pmc *)hw)->PMC_SLPWK_AIPR & PMC_SLPWK_AIPR_AIP) > 0; +} + +static inline hri_pmc_slpwk_aipr_reg_t hri_pmc_get_SLPWK_AIPR_reg(const void *const hw, hri_pmc_slpwk_aipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_SLPWK_AIPR; + tmp &= mask; + return tmp; +} + +static inline hri_pmc_slpwk_aipr_reg_t hri_pmc_read_SLPWK_AIPR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_SLPWK_AIPR; +} + +static inline void hri_pmc_set_CKGR_UCKR_UPLLEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR |= CKGR_UCKR_UPLLEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_UCKR_UPLLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp = (tmp & CKGR_UCKR_UPLLEN) >> CKGR_UCKR_UPLLEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_UCKR_UPLLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp &= ~CKGR_UCKR_UPLLEN; + tmp |= value << CKGR_UCKR_UPLLEN_Pos; + ((Pmc *)hw)->CKGR_UCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_UCKR_UPLLEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_UCKR_UPLLEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR ^= CKGR_UCKR_UPLLEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR |= CKGR_UCKR_UPLLCOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_uckr_reg_t hri_pmc_get_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw, + hri_pmc_ckgr_uckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp = (tmp & CKGR_UCKR_UPLLCOUNT(mask)) >> CKGR_UCKR_UPLLCOUNT_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw, hri_pmc_ckgr_uckr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp &= ~CKGR_UCKR_UPLLCOUNT_Msk; + tmp |= CKGR_UCKR_UPLLCOUNT(data); + ((Pmc *)hw)->CKGR_UCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR &= ~CKGR_UCKR_UPLLCOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR ^= CKGR_UCKR_UPLLCOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_uckr_reg_t hri_pmc_read_CKGR_UCKR_UPLLCOUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp = (tmp & CKGR_UCKR_UPLLCOUNT_Msk) >> CKGR_UCKR_UPLLCOUNT_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_UCKR_reg(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_uckr_reg_t hri_pmc_get_CKGR_UCKR_reg(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_UCKR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_CKGR_UCKR_reg(const void *const hw, hri_pmc_ckgr_uckr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_UCKR_reg(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_UCKR_reg(const void *const hw, hri_pmc_ckgr_uckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_UCKR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_uckr_reg_t hri_pmc_read_CKGR_UCKR_reg(const void *const hw) +{ + return ((Pmc *)hw)->CKGR_UCKR; +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCXTEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCXTEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_MOSCXTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCXTEN) >> CKGR_MOR_MOSCXTEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCXTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCXTEN; + tmp |= value << CKGR_MOR_MOSCXTEN_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCXTEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCXTEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCXTEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCXTEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCXTBY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCXTBY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_MOSCXTBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCXTBY) >> CKGR_MOR_MOSCXTBY_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCXTBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCXTBY; + tmp |= value << CKGR_MOR_MOSCXTBY_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCXTBY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCXTBY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCXTBY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCXTBY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_WAITMODE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_WAITMODE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_WAITMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_WAITMODE) >> CKGR_MOR_WAITMODE_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_WAITMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_WAITMODE; + tmp |= value << CKGR_MOR_WAITMODE_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_WAITMODE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_WAITMODE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_WAITMODE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_WAITMODE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCRCEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCRCEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_MOSCRCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCRCEN) >> CKGR_MOR_MOSCRCEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCRCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCRCEN; + tmp |= value << CKGR_MOR_MOSCRCEN_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCRCEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCRCEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCRCEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCRCEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCSEL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCSEL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_MOSCSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCSEL) >> CKGR_MOR_MOSCSEL_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCSEL; + tmp |= value << CKGR_MOR_MOSCSEL_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCSEL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCSEL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCSEL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCSEL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_CFDEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_CFDEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_CFDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_CFDEN) >> CKGR_MOR_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_CFDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_CFDEN; + tmp |= value << CKGR_MOR_CFDEN_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_CFDEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_CFDEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_CFDEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_CFDEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_XT32KFME_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_XT32KFME; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MOR_XT32KFME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_XT32KFME) >> CKGR_MOR_XT32KFME_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_XT32KFME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_XT32KFME; + tmp |= value << CKGR_MOR_XT32KFME_Pos; + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_XT32KFME_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_XT32KFME; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_XT32KFME_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_XT32KFME; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCRCF_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCRCF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_get_CKGR_MOR_MOSCRCF_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCRCF(mask)) >> CKGR_MOR_MOSCRCF_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCRCF_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCRCF_Msk; + tmp |= CKGR_MOR_MOSCRCF(data); + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCRCF_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCRCF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCRCF_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCRCF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_read_CKGR_MOR_MOSCRCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCRCF_Msk) >> CKGR_MOR_MOSCRCF_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_MOR_MOSCXTST_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_MOSCXTST(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_get_CKGR_MOR_MOSCXTST_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCXTST(mask)) >> CKGR_MOR_MOSCXTST_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_MOSCXTST_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_MOSCXTST_Msk; + tmp |= CKGR_MOR_MOSCXTST(data); + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_MOSCXTST_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_MOSCXTST(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_MOSCXTST_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_MOSCXTST(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_read_CKGR_MOR_MOSCXTST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_MOSCXTST_Msk) >> CKGR_MOR_MOSCXTST_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_MOR_KEY_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= CKGR_MOR_KEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_get_CKGR_MOR_KEY_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_KEY(mask)) >> CKGR_MOR_KEY_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_KEY_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= ~CKGR_MOR_KEY_Msk; + tmp |= CKGR_MOR_KEY(data); + ((Pmc *)hw)->CKGR_MOR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_KEY_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~CKGR_MOR_KEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_KEY_bf(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= CKGR_MOR_KEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_read_CKGR_MOR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp = (tmp & CKGR_MOR_KEY_Msk) >> CKGR_MOR_KEY_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_MOR_reg(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_get_CKGR_MOR_reg(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MOR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MOR_reg(const void *const hw, hri_pmc_ckgr_mor_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MOR_reg(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MOR_reg(const void *const hw, hri_pmc_ckgr_mor_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MOR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mor_reg_t hri_pmc_read_CKGR_MOR_reg(const void *const hw) +{ + return ((Pmc *)hw)->CKGR_MOR; +} + +static inline void hri_pmc_set_CKGR_MCFR_MAINFRDY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR |= CKGR_MCFR_MAINFRDY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MCFR_MAINFRDY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp = (tmp & CKGR_MCFR_MAINFRDY) >> CKGR_MCFR_MAINFRDY_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MCFR_MAINFRDY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp &= ~CKGR_MCFR_MAINFRDY; + tmp |= value << CKGR_MCFR_MAINFRDY_Pos; + ((Pmc *)hw)->CKGR_MCFR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MCFR_MAINFRDY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR &= ~CKGR_MCFR_MAINFRDY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MCFR_MAINFRDY_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR ^= CKGR_MCFR_MAINFRDY; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MCFR_RCMEAS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR |= CKGR_MCFR_RCMEAS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MCFR_RCMEAS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp = (tmp & CKGR_MCFR_RCMEAS) >> CKGR_MCFR_RCMEAS_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MCFR_RCMEAS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp &= ~CKGR_MCFR_RCMEAS; + tmp |= value << CKGR_MCFR_RCMEAS_Pos; + ((Pmc *)hw)->CKGR_MCFR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MCFR_RCMEAS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR &= ~CKGR_MCFR_RCMEAS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MCFR_RCMEAS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR ^= CKGR_MCFR_RCMEAS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MCFR_CCSS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR |= CKGR_MCFR_CCSS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_MCFR_CCSS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp = (tmp & CKGR_MCFR_CCSS) >> CKGR_MCFR_CCSS_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_MCFR_CCSS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp &= ~CKGR_MCFR_CCSS; + tmp |= value << CKGR_MCFR_CCSS_Pos; + ((Pmc *)hw)->CKGR_MCFR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MCFR_CCSS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR &= ~CKGR_MCFR_CCSS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MCFR_CCSS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR ^= CKGR_MCFR_CCSS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_MCFR_MAINF_bf(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR |= CKGR_MCFR_MAINF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mcfr_reg_t hri_pmc_get_CKGR_MCFR_MAINF_bf(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp = (tmp & CKGR_MCFR_MAINF(mask)) >> CKGR_MCFR_MAINF_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MCFR_MAINF_bf(const void *const hw, hri_pmc_ckgr_mcfr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp &= ~CKGR_MCFR_MAINF_Msk; + tmp |= CKGR_MCFR_MAINF(data); + ((Pmc *)hw)->CKGR_MCFR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MCFR_MAINF_bf(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR &= ~CKGR_MCFR_MAINF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MCFR_MAINF_bf(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR ^= CKGR_MCFR_MAINF(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mcfr_reg_t hri_pmc_read_CKGR_MCFR_MAINF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp = (tmp & CKGR_MCFR_MAINF_Msk) >> CKGR_MCFR_MAINF_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_MCFR_reg(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mcfr_reg_t hri_pmc_get_CKGR_MCFR_reg(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_MCFR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_CKGR_MCFR_reg(const void *const hw, hri_pmc_ckgr_mcfr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_MCFR_reg(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_MCFR_reg(const void *const hw, hri_pmc_ckgr_mcfr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_MCFR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_mcfr_reg_t hri_pmc_read_CKGR_MCFR_reg(const void *const hw) +{ + return ((Pmc *)hw)->CKGR_MCFR; +} + +static inline void hri_pmc_set_CKGR_PLLAR_ONE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR |= CKGR_PLLAR_ONE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_CKGR_PLLAR_ONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_ONE) >> CKGR_PLLAR_ONE_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_CKGR_PLLAR_ONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp &= ~CKGR_PLLAR_ONE; + tmp |= value << CKGR_PLLAR_ONE_Pos; + ((Pmc *)hw)->CKGR_PLLAR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_PLLAR_ONE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR &= ~CKGR_PLLAR_ONE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_PLLAR_ONE_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR ^= CKGR_PLLAR_ONE; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_CKGR_PLLAR_DIVA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR |= CKGR_PLLAR_DIVA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_get_CKGR_PLLAR_DIVA_bf(const void *const hw, + hri_pmc_ckgr_pllar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_DIVA(mask)) >> CKGR_PLLAR_DIVA_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_PLLAR_DIVA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp &= ~CKGR_PLLAR_DIVA_Msk; + tmp |= CKGR_PLLAR_DIVA(data); + ((Pmc *)hw)->CKGR_PLLAR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_PLLAR_DIVA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR &= ~CKGR_PLLAR_DIVA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_PLLAR_DIVA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR ^= CKGR_PLLAR_DIVA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_read_CKGR_PLLAR_DIVA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR |= CKGR_PLLAR_PLLACOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_get_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw, + hri_pmc_ckgr_pllar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_PLLACOUNT(mask)) >> CKGR_PLLAR_PLLACOUNT_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp &= ~CKGR_PLLAR_PLLACOUNT_Msk; + tmp |= CKGR_PLLAR_PLLACOUNT(data); + ((Pmc *)hw)->CKGR_PLLAR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR &= ~CKGR_PLLAR_PLLACOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR ^= CKGR_PLLAR_PLLACOUNT(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_read_CKGR_PLLAR_PLLACOUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_PLLACOUNT_Msk) >> CKGR_PLLAR_PLLACOUNT_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_PLLAR_MULA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR |= CKGR_PLLAR_MULA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_get_CKGR_PLLAR_MULA_bf(const void *const hw, + hri_pmc_ckgr_pllar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_MULA(mask)) >> CKGR_PLLAR_MULA_Pos; + return tmp; +} + +static inline void hri_pmc_write_CKGR_PLLAR_MULA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp &= ~CKGR_PLLAR_MULA_Msk; + tmp |= CKGR_PLLAR_MULA(data); + ((Pmc *)hw)->CKGR_PLLAR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_PLLAR_MULA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR &= ~CKGR_PLLAR_MULA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_PLLAR_MULA_bf(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR ^= CKGR_PLLAR_MULA(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_read_CKGR_PLLAR_MULA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp = (tmp & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos; + return tmp; +} + +static inline void hri_pmc_set_CKGR_PLLAR_reg(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_get_CKGR_PLLAR_reg(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->CKGR_PLLAR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_CKGR_PLLAR_reg(const void *const hw, hri_pmc_ckgr_pllar_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_CKGR_PLLAR_reg(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_CKGR_PLLAR_reg(const void *const hw, hri_pmc_ckgr_pllar_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->CKGR_PLLAR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ckgr_pllar_reg_t hri_pmc_read_CKGR_PLLAR_reg(const void *const hw) +{ + return ((Pmc *)hw)->CKGR_PLLAR; +} + +static inline void hri_pmc_set_MCKR_UPLLDIV2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR |= PMC_MCKR_UPLLDIV2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_MCKR_UPLLDIV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_UPLLDIV2) >> PMC_MCKR_UPLLDIV2_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_MCKR_UPLLDIV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp &= ~PMC_MCKR_UPLLDIV2; + tmp |= value << PMC_MCKR_UPLLDIV2_Pos; + ((Pmc *)hw)->PMC_MCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_MCKR_UPLLDIV2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_MCKR_UPLLDIV2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR ^= PMC_MCKR_UPLLDIV2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_MCKR_CSS_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR |= PMC_MCKR_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_get_MCKR_CSS_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_CSS(mask)) >> PMC_MCKR_CSS_Pos; + return tmp; +} + +static inline void hri_pmc_write_MCKR_CSS_bf(const void *const hw, hri_pmc_mckr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp &= ~PMC_MCKR_CSS_Msk; + tmp |= PMC_MCKR_CSS(data); + ((Pmc *)hw)->PMC_MCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_MCKR_CSS_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR &= ~PMC_MCKR_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_MCKR_CSS_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR ^= PMC_MCKR_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_read_MCKR_CSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_CSS_Msk) >> PMC_MCKR_CSS_Pos; + return tmp; +} + +static inline void hri_pmc_set_MCKR_PRES_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR |= PMC_MCKR_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_get_MCKR_PRES_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_PRES(mask)) >> PMC_MCKR_PRES_Pos; + return tmp; +} + +static inline void hri_pmc_write_MCKR_PRES_bf(const void *const hw, hri_pmc_mckr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp &= ~PMC_MCKR_PRES_Msk; + tmp |= PMC_MCKR_PRES(data); + ((Pmc *)hw)->PMC_MCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_MCKR_PRES_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR &= ~PMC_MCKR_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_MCKR_PRES_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR ^= PMC_MCKR_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_read_MCKR_PRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos; + return tmp; +} + +static inline void hri_pmc_set_MCKR_MDIV_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR |= PMC_MCKR_MDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_get_MCKR_MDIV_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_MDIV(mask)) >> PMC_MCKR_MDIV_Pos; + return tmp; +} + +static inline void hri_pmc_write_MCKR_MDIV_bf(const void *const hw, hri_pmc_mckr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp &= ~PMC_MCKR_MDIV_Msk; + tmp |= PMC_MCKR_MDIV(data); + ((Pmc *)hw)->PMC_MCKR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_MCKR_MDIV_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR &= ~PMC_MCKR_MDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_MCKR_MDIV_bf(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR ^= PMC_MCKR_MDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_read_MCKR_MDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp = (tmp & PMC_MCKR_MDIV_Msk) >> PMC_MCKR_MDIV_Pos; + return tmp; +} + +static inline void hri_pmc_set_MCKR_reg(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_get_MCKR_reg(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_MCKR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_MCKR_reg(const void *const hw, hri_pmc_mckr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_MCKR_reg(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_MCKR_reg(const void *const hw, hri_pmc_mckr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_MCKR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_mckr_reg_t hri_pmc_read_MCKR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_MCKR; +} + +static inline void hri_pmc_set_USB_USBS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB |= PMC_USB_USBS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_USB_USBS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_USB; + tmp = (tmp & PMC_USB_USBS) >> PMC_USB_USBS_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_USB_USBS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_USB; + tmp &= ~PMC_USB_USBS; + tmp |= value << PMC_USB_USBS_Pos; + ((Pmc *)hw)->PMC_USB = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_USB_USBS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB &= ~PMC_USB_USBS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_USB_USBS_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB ^= PMC_USB_USBS; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_USB_USBDIV_bf(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB |= PMC_USB_USBDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_usb_reg_t hri_pmc_get_USB_USBDIV_bf(const void *const hw, hri_pmc_usb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_USB; + tmp = (tmp & PMC_USB_USBDIV(mask)) >> PMC_USB_USBDIV_Pos; + return tmp; +} + +static inline void hri_pmc_write_USB_USBDIV_bf(const void *const hw, hri_pmc_usb_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_USB; + tmp &= ~PMC_USB_USBDIV_Msk; + tmp |= PMC_USB_USBDIV(data); + ((Pmc *)hw)->PMC_USB = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_USB_USBDIV_bf(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB &= ~PMC_USB_USBDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_USB_USBDIV_bf(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB ^= PMC_USB_USBDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_usb_reg_t hri_pmc_read_USB_USBDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_USB; + tmp = (tmp & PMC_USB_USBDIV_Msk) >> PMC_USB_USBDIV_Pos; + return tmp; +} + +static inline void hri_pmc_set_USB_reg(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_usb_reg_t hri_pmc_get_USB_reg(const void *const hw, hri_pmc_usb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_USB; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_USB_reg(const void *const hw, hri_pmc_usb_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_USB_reg(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_USB_reg(const void *const hw, hri_pmc_usb_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_USB ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_usb_reg_t hri_pmc_read_USB_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_USB; +} + +static inline void hri_pmc_set_PCK_CSS_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] |= PMC_PCK_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_get_PCK_CSS_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp = (tmp & PMC_PCK_CSS(mask)) >> PMC_PCK_CSS_Pos; + return tmp; +} + +static inline void hri_pmc_write_PCK_CSS_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp &= ~PMC_PCK_CSS_Msk; + tmp |= PMC_PCK_CSS(data); + ((Pmc *)hw)->PMC_PCK[index] = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCK_CSS_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] &= ~PMC_PCK_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCK_CSS_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] ^= PMC_PCK_CSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_read_PCK_CSS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp = (tmp & PMC_PCK_CSS_Msk) >> PMC_PCK_CSS_Pos; + return tmp; +} + +static inline void hri_pmc_set_PCK_PRES_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] |= PMC_PCK_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_get_PCK_PRES_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp = (tmp & PMC_PCK_PRES(mask)) >> PMC_PCK_PRES_Pos; + return tmp; +} + +static inline void hri_pmc_write_PCK_PRES_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp &= ~PMC_PCK_PRES_Msk; + tmp |= PMC_PCK_PRES(data); + ((Pmc *)hw)->PMC_PCK[index] = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCK_PRES_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] &= ~PMC_PCK_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCK_PRES_bf(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] ^= PMC_PCK_PRES(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_read_PCK_PRES_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp = (tmp & PMC_PCK_PRES_Msk) >> PMC_PCK_PRES_Pos; + return tmp; +} + +static inline void hri_pmc_set_PCK_reg(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_get_PCK_reg(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCK[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_PCK_reg(const void *const hw, uint8_t index, hri_pmc_pck_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCK_reg(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCK_reg(const void *const hw, uint8_t index, hri_pmc_pck_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCK[index] ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pck_reg_t hri_pmc_read_PCK_reg(const void *const hw, uint8_t index) +{ + return ((Pmc *)hw)->PMC_PCK[index]; +} + +static inline void hri_pmc_set_FSMR_FSTT0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT0) >> PMC_FSMR_FSTT0_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT0; + tmp |= value << PMC_FSMR_FSTT0_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT1) >> PMC_FSMR_FSTT1_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT1; + tmp |= value << PMC_FSMR_FSTT1_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT2) >> PMC_FSMR_FSTT2_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT2; + tmp |= value << PMC_FSMR_FSTT2_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT3) >> PMC_FSMR_FSTT3_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT3; + tmp |= value << PMC_FSMR_FSTT3_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT4) >> PMC_FSMR_FSTT4_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT4; + tmp |= value << PMC_FSMR_FSTT4_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT5) >> PMC_FSMR_FSTT5_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT5; + tmp |= value << PMC_FSMR_FSTT5_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT6) >> PMC_FSMR_FSTT6_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT6; + tmp |= value << PMC_FSMR_FSTT6_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT7) >> PMC_FSMR_FSTT7_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT7; + tmp |= value << PMC_FSMR_FSTT7_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT8) >> PMC_FSMR_FSTT8_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT8; + tmp |= value << PMC_FSMR_FSTT8_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT9) >> PMC_FSMR_FSTT9_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT9; + tmp |= value << PMC_FSMR_FSTT9_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT10) >> PMC_FSMR_FSTT10_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT10; + tmp |= value << PMC_FSMR_FSTT10_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT11) >> PMC_FSMR_FSTT11_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT11; + tmp |= value << PMC_FSMR_FSTT11_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT12) >> PMC_FSMR_FSTT12_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT12; + tmp |= value << PMC_FSMR_FSTT12_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT13) >> PMC_FSMR_FSTT13_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT13; + tmp |= value << PMC_FSMR_FSTT13_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT14) >> PMC_FSMR_FSTT14_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT14; + tmp |= value << PMC_FSMR_FSTT14_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FSTT15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FSTT15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FSTT15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FSTT15) >> PMC_FSMR_FSTT15_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FSTT15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FSTT15; + tmp |= value << PMC_FSMR_FSTT15_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FSTT15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FSTT15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FSTT15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FSTT15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_RTTAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_RTTAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_RTTAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_RTTAL) >> PMC_FSMR_RTTAL_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_RTTAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_RTTAL; + tmp |= value << PMC_FSMR_RTTAL_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_RTTAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_RTTAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_RTTAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_RTTAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_RTCAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_RTCAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_RTCAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_RTCAL) >> PMC_FSMR_RTCAL_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_RTCAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_RTCAL; + tmp |= value << PMC_FSMR_RTCAL_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_RTCAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_RTCAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_RTCAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_RTCAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_USBAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_USBAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_USBAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_USBAL) >> PMC_FSMR_USBAL_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_USBAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_USBAL; + tmp |= value << PMC_FSMR_USBAL_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_USBAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_USBAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_USBAL_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_USBAL; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_LPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_LPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_LPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_LPM) >> PMC_FSMR_LPM_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_LPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_LPM; + tmp |= value << PMC_FSMR_LPM_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_LPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_LPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_LPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_LPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FFLPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FFLPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSMR_FFLPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FFLPM) >> PMC_FSMR_FFLPM_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSMR_FFLPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FFLPM; + tmp |= value << PMC_FSMR_FFLPM_Pos; + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FFLPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FFLPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FFLPM_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FFLPM; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSMR_FLPM_bf(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= PMC_FSMR_FLPM(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fsmr_reg_t hri_pmc_get_FSMR_FLPM_bf(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FLPM(mask)) >> PMC_FSMR_FLPM_Pos; + return tmp; +} + +static inline void hri_pmc_write_FSMR_FLPM_bf(const void *const hw, hri_pmc_fsmr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= ~PMC_FSMR_FLPM_Msk; + tmp |= PMC_FSMR_FLPM(data); + ((Pmc *)hw)->PMC_FSMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_FLPM_bf(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~PMC_FSMR_FLPM(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_FLPM_bf(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= PMC_FSMR_FLPM(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fsmr_reg_t hri_pmc_read_FSMR_FLPM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp = (tmp & PMC_FSMR_FLPM_Msk) >> PMC_FSMR_FLPM_Pos; + return tmp; +} + +static inline void hri_pmc_set_FSMR_reg(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fsmr_reg_t hri_pmc_get_FSMR_reg(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_FSMR_reg(const void *const hw, hri_pmc_fsmr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSMR_reg(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSMR_reg(const void *const hw, hri_pmc_fsmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSMR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fsmr_reg_t hri_pmc_read_FSMR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_FSMR; +} + +static inline void hri_pmc_set_FSPR_FSTP0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP0) >> PMC_FSPR_FSTP0_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP0; + tmp |= value << PMC_FSPR_FSTP0_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP0_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP0; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP1) >> PMC_FSPR_FSTP1_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP1; + tmp |= value << PMC_FSPR_FSTP1_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP1_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP1; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP2) >> PMC_FSPR_FSTP2_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP2; + tmp |= value << PMC_FSPR_FSTP2_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP2_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP2; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP3) >> PMC_FSPR_FSTP3_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP3; + tmp |= value << PMC_FSPR_FSTP3_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP3_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP3; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP4) >> PMC_FSPR_FSTP4_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP4; + tmp |= value << PMC_FSPR_FSTP4_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP5) >> PMC_FSPR_FSTP5_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP5; + tmp |= value << PMC_FSPR_FSTP5_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP5_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP5; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP6) >> PMC_FSPR_FSTP6_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP6; + tmp |= value << PMC_FSPR_FSTP6_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP6_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP6; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP7) >> PMC_FSPR_FSTP7_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP7; + tmp |= value << PMC_FSPR_FSTP7_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP7_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP7; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP8) >> PMC_FSPR_FSTP8_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP8; + tmp |= value << PMC_FSPR_FSTP8_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP9) >> PMC_FSPR_FSTP9_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP9; + tmp |= value << PMC_FSPR_FSTP9_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP9_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP9; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP10) >> PMC_FSPR_FSTP10_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP10; + tmp |= value << PMC_FSPR_FSTP10_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP10_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP10; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP11) >> PMC_FSPR_FSTP11_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP11; + tmp |= value << PMC_FSPR_FSTP11_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP11_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP11; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP12) >> PMC_FSPR_FSTP12_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP12; + tmp |= value << PMC_FSPR_FSTP12_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP13) >> PMC_FSPR_FSTP13_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP13; + tmp |= value << PMC_FSPR_FSTP13_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP13_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP13; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP14) >> PMC_FSPR_FSTP14_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP14; + tmp |= value << PMC_FSPR_FSTP14_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP14_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP14; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_FSTP15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= PMC_FSPR_FSTP15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_FSPR_FSTP15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp = (tmp & PMC_FSPR_FSTP15) >> PMC_FSPR_FSTP15_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_FSPR_FSTP15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= ~PMC_FSPR_FSTP15; + tmp |= value << PMC_FSPR_FSTP15_Pos; + ((Pmc *)hw)->PMC_FSPR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_FSTP15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~PMC_FSPR_FSTP15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_FSTP15_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= PMC_FSPR_FSTP15; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_FSPR_reg(const void *const hw, hri_pmc_fspr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fspr_reg_t hri_pmc_get_FSPR_reg(const void *const hw, hri_pmc_fspr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_FSPR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_FSPR_reg(const void *const hw, hri_pmc_fspr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_FSPR_reg(const void *const hw, hri_pmc_fspr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_FSPR_reg(const void *const hw, hri_pmc_fspr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FSPR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_fspr_reg_t hri_pmc_read_FSPR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_FSPR; +} + +static inline void hri_pmc_set_WPMR_WPEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR |= PMC_WPMR_WPEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp = (tmp & PMC_WPMR_WPEN) >> PMC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp &= ~PMC_WPMR_WPEN; + tmp |= value << PMC_WPMR_WPEN_Pos; + ((Pmc *)hw)->PMC_WPMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_WPMR_WPEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR &= ~PMC_WPMR_WPEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR ^= PMC_WPMR_WPEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_WPMR_WPKEY_bf(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR |= PMC_WPMR_WPKEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_wpmr_reg_t hri_pmc_get_WPMR_WPKEY_bf(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp = (tmp & PMC_WPMR_WPKEY(mask)) >> PMC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_pmc_write_WPMR_WPKEY_bf(const void *const hw, hri_pmc_wpmr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp &= ~PMC_WPMR_WPKEY_Msk; + tmp |= PMC_WPMR_WPKEY(data); + ((Pmc *)hw)->PMC_WPMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_WPMR_WPKEY_bf(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR &= ~PMC_WPMR_WPKEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR ^= PMC_WPMR_WPKEY(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_wpmr_reg_t hri_pmc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp = (tmp & PMC_WPMR_WPKEY_Msk) >> PMC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_pmc_set_WPMR_reg(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_wpmr_reg_t hri_pmc_get_WPMR_reg(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_WPMR_reg(const void *const hw, hri_pmc_wpmr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_WPMR_reg(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_WPMR_reg(const void *const hw, hri_pmc_wpmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_WPMR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_wpmr_reg_t hri_pmc_read_WPMR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_WPMR; +} + +static inline void hri_pmc_set_PCR_CMD_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_CMD; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_PCR_CMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_CMD) >> PMC_PCR_CMD_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_PCR_CMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_CMD; + tmp |= value << PMC_PCR_CMD_Pos; + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_CMD_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_CMD; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_CMD_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_CMD; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_PCR_EN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_EN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_PCR_EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_EN) >> PMC_PCR_EN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_PCR_EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_EN; + tmp |= value << PMC_PCR_EN_Pos; + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_EN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_EN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_EN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_EN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_PCR_GCLKEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_GCLKEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_PCR_GCLKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_GCLKEN) >> PMC_PCR_GCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_PCR_GCLKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_GCLKEN; + tmp |= value << PMC_PCR_GCLKEN_Pos; + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_GCLKEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_GCLKEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_GCLKEN_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_GCLKEN; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_PCR_PID_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_PID(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_get_PCR_PID_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_PID(mask)) >> PMC_PCR_PID_Pos; + return tmp; +} + +static inline void hri_pmc_write_PCR_PID_bf(const void *const hw, hri_pmc_pcr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_PID_Msk; + tmp |= PMC_PCR_PID(data); + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_PID_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_PID(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_PID_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_PID(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_read_PCR_PID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_PID_Msk) >> PMC_PCR_PID_Pos; + return tmp; +} + +static inline void hri_pmc_set_PCR_GCLKCSS_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_GCLKCSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_get_PCR_GCLKCSS_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_GCLKCSS(mask)) >> PMC_PCR_GCLKCSS_Pos; + return tmp; +} + +static inline void hri_pmc_write_PCR_GCLKCSS_bf(const void *const hw, hri_pmc_pcr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_GCLKCSS_Msk; + tmp |= PMC_PCR_GCLKCSS(data); + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_GCLKCSS_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_GCLKCSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_GCLKCSS_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_GCLKCSS(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_read_PCR_GCLKCSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_GCLKCSS_Msk) >> PMC_PCR_GCLKCSS_Pos; + return tmp; +} + +static inline void hri_pmc_set_PCR_GCLKDIV_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= PMC_PCR_GCLKDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_get_PCR_GCLKDIV_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_GCLKDIV(mask)) >> PMC_PCR_GCLKDIV_Pos; + return tmp; +} + +static inline void hri_pmc_write_PCR_GCLKDIV_bf(const void *const hw, hri_pmc_pcr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= ~PMC_PCR_GCLKDIV_Msk; + tmp |= PMC_PCR_GCLKDIV(data); + ((Pmc *)hw)->PMC_PCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_GCLKDIV_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~PMC_PCR_GCLKDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_GCLKDIV_bf(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= PMC_PCR_GCLKDIV(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_read_PCR_GCLKDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp = (tmp & PMC_PCR_GCLKDIV_Msk) >> PMC_PCR_GCLKDIV_Pos; + return tmp; +} + +static inline void hri_pmc_set_PCR_reg(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_get_PCR_reg(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PCR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_PCR_reg(const void *const hw, hri_pmc_pcr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PCR_reg(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PCR_reg(const void *const hw, hri_pmc_pcr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PCR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pcr_reg_t hri_pmc_read_PCR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_PCR; +} + +static inline void hri_pmc_set_OCR_SEL4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_SEL4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_OCR_SEL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_SEL4) >> PMC_OCR_SEL4_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_OCR_SEL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_SEL4; + tmp |= value << PMC_OCR_SEL4_Pos; + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_SEL4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_SEL4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_SEL4_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_SEL4; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_OCR_SEL8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_SEL8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_OCR_SEL8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_SEL8) >> PMC_OCR_SEL8_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_OCR_SEL8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_SEL8; + tmp |= value << PMC_OCR_SEL8_Pos; + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_SEL8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_SEL8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_SEL8_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_SEL8; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_OCR_SEL12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_SEL12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pmc_get_OCR_SEL12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_SEL12) >> PMC_OCR_SEL12_Pos; + return (bool)tmp; +} + +static inline void hri_pmc_write_OCR_SEL12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_SEL12; + tmp |= value << PMC_OCR_SEL12_Pos; + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_SEL12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_SEL12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_SEL12_bit(const void *const hw) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_SEL12; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_set_OCR_CAL4_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_CAL4(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_get_OCR_CAL4_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL4(mask)) >> PMC_OCR_CAL4_Pos; + return tmp; +} + +static inline void hri_pmc_write_OCR_CAL4_bf(const void *const hw, hri_pmc_ocr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_CAL4_Msk; + tmp |= PMC_OCR_CAL4(data); + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_CAL4_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_CAL4(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_CAL4_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_CAL4(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_read_OCR_CAL4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL4_Msk) >> PMC_OCR_CAL4_Pos; + return tmp; +} + +static inline void hri_pmc_set_OCR_CAL8_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_CAL8(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_get_OCR_CAL8_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL8(mask)) >> PMC_OCR_CAL8_Pos; + return tmp; +} + +static inline void hri_pmc_write_OCR_CAL8_bf(const void *const hw, hri_pmc_ocr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_CAL8_Msk; + tmp |= PMC_OCR_CAL8(data); + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_CAL8_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_CAL8(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_CAL8_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_CAL8(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_read_OCR_CAL8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL8_Msk) >> PMC_OCR_CAL8_Pos; + return tmp; +} + +static inline void hri_pmc_set_OCR_CAL12_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= PMC_OCR_CAL12(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_get_OCR_CAL12_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL12(mask)) >> PMC_OCR_CAL12_Pos; + return tmp; +} + +static inline void hri_pmc_write_OCR_CAL12_bf(const void *const hw, hri_pmc_ocr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= ~PMC_OCR_CAL12_Msk; + tmp |= PMC_OCR_CAL12(data); + ((Pmc *)hw)->PMC_OCR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_CAL12_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~PMC_OCR_CAL12(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_CAL12_bf(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= PMC_OCR_CAL12(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_read_OCR_CAL12_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp = (tmp & PMC_OCR_CAL12_Msk) >> PMC_OCR_CAL12_Pos; + return tmp; +} + +static inline void hri_pmc_set_OCR_reg(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_get_OCR_reg(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_OCR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_OCR_reg(const void *const hw, hri_pmc_ocr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_OCR_reg(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_OCR_reg(const void *const hw, hri_pmc_ocr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_OCR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_ocr_reg_t hri_pmc_read_OCR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_OCR; +} + +static inline void hri_pmc_set_PMMR_PLLA_MMAX_bf(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR |= PMC_PMMR_PLLA_MMAX(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pmmr_reg_t hri_pmc_get_PMMR_PLLA_MMAX_bf(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PMMR; + tmp = (tmp & PMC_PMMR_PLLA_MMAX(mask)) >> PMC_PMMR_PLLA_MMAX_Pos; + return tmp; +} + +static inline void hri_pmc_write_PMMR_PLLA_MMAX_bf(const void *const hw, hri_pmc_pmmr_reg_t data) +{ + uint32_t tmp; + PMC_CRITICAL_SECTION_ENTER(); + tmp = ((Pmc *)hw)->PMC_PMMR; + tmp &= ~PMC_PMMR_PLLA_MMAX_Msk; + tmp |= PMC_PMMR_PLLA_MMAX(data); + ((Pmc *)hw)->PMC_PMMR = tmp; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PMMR_PLLA_MMAX_bf(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR &= ~PMC_PMMR_PLLA_MMAX(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PMMR_PLLA_MMAX_bf(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR ^= PMC_PMMR_PLLA_MMAX(mask); + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pmmr_reg_t hri_pmc_read_PMMR_PLLA_MMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PMMR; + tmp = (tmp & PMC_PMMR_PLLA_MMAX_Msk) >> PMC_PMMR_PLLA_MMAX_Pos; + return tmp; +} + +static inline void hri_pmc_set_PMMR_reg(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR |= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pmmr_reg_t hri_pmc_get_PMMR_reg(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pmc *)hw)->PMC_PMMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pmc_write_PMMR_reg(const void *const hw, hri_pmc_pmmr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_clear_PMMR_reg(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR &= ~mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pmc_toggle_PMMR_reg(const void *const hw, hri_pmc_pmmr_reg_t mask) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_PMMR ^= mask; + PMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pmc_pmmr_reg_t hri_pmc_read_PMMR_reg(const void *const hw) +{ + return ((Pmc *)hw)->PMC_PMMR; +} + +static inline void hri_pmc_write_FOCR_reg(const void *const hw, hri_pmc_focr_reg_t data) +{ + PMC_CRITICAL_SECTION_ENTER(); + ((Pmc *)hw)->PMC_FOCR = data; + PMC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PMC_E70B_H_INCLUDED */ +#endif /* _SAME70_PMC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_pwm_e70b.h b/bsp/microchip/same70/bsp/hri/hri_pwm_e70b.h new file mode 100644 index 0000000000..33af67c698 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_pwm_e70b.h @@ -0,0 +1,8295 @@ +/** + * \file + * + * \brief SAM PWM + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_PWM_COMPONENT_ +#ifndef _HRI_PWM_E70B_H_INCLUDED_ +#define _HRI_PWM_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PWM_CRITICAL_SECTIONS) +#define PWM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PWM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PWM_CRITICAL_SECTION_ENTER() +#define PWM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pwm_ccnt_reg_t; +typedef uint32_t hri_pwm_cdty_reg_t; +typedef uint32_t hri_pwm_cdtyupd_reg_t; +typedef uint32_t hri_pwm_clk_reg_t; +typedef uint32_t hri_pwm_cmpm_reg_t; +typedef uint32_t hri_pwm_cmpmupd_reg_t; +typedef uint32_t hri_pwm_cmpv_reg_t; +typedef uint32_t hri_pwm_cmpvupd_reg_t; +typedef uint32_t hri_pwm_cmr_reg_t; +typedef uint32_t hri_pwm_cmupd0_reg_t; +typedef uint32_t hri_pwm_cmupd1_reg_t; +typedef uint32_t hri_pwm_cmupd2_reg_t; +typedef uint32_t hri_pwm_cmupd3_reg_t; +typedef uint32_t hri_pwm_cprd_reg_t; +typedef uint32_t hri_pwm_cprdupd_reg_t; +typedef uint32_t hri_pwm_dis_reg_t; +typedef uint32_t hri_pwm_dmar_reg_t; +typedef uint32_t hri_pwm_dt_reg_t; +typedef uint32_t hri_pwm_dtupd_reg_t; +typedef uint32_t hri_pwm_elmr_reg_t; +typedef uint32_t hri_pwm_ena_reg_t; +typedef uint32_t hri_pwm_etrg1_reg_t; +typedef uint32_t hri_pwm_etrg2_reg_t; +typedef uint32_t hri_pwm_fcr_reg_t; +typedef uint32_t hri_pwm_fmr_reg_t; +typedef uint32_t hri_pwm_fpe_reg_t; +typedef uint32_t hri_pwm_fpv1_reg_t; +typedef uint32_t hri_pwm_fpv2_reg_t; +typedef uint32_t hri_pwm_fsr_reg_t; +typedef uint32_t hri_pwm_imr1_reg_t; +typedef uint32_t hri_pwm_imr2_reg_t; +typedef uint32_t hri_pwm_isr1_reg_t; +typedef uint32_t hri_pwm_isr2_reg_t; +typedef uint32_t hri_pwm_lebr1_reg_t; +typedef uint32_t hri_pwm_lebr2_reg_t; +typedef uint32_t hri_pwm_oov_reg_t; +typedef uint32_t hri_pwm_os_reg_t; +typedef uint32_t hri_pwm_osc_reg_t; +typedef uint32_t hri_pwm_oscupd_reg_t; +typedef uint32_t hri_pwm_oss_reg_t; +typedef uint32_t hri_pwm_ossupd_reg_t; +typedef uint32_t hri_pwm_scm_reg_t; +typedef uint32_t hri_pwm_scuc_reg_t; +typedef uint32_t hri_pwm_scup_reg_t; +typedef uint32_t hri_pwm_scupupd_reg_t; +typedef uint32_t hri_pwm_smmr_reg_t; +typedef uint32_t hri_pwm_sr_reg_t; +typedef uint32_t hri_pwm_sspr_reg_t; +typedef uint32_t hri_pwm_sspup_reg_t; +typedef uint32_t hri_pwm_wpcr_reg_t; +typedef uint32_t hri_pwm_wpsr_reg_t; +typedef uint32_t hri_pwmch_num_ccnt_reg_t; +typedef uint32_t hri_pwmch_num_cdty_reg_t; +typedef uint32_t hri_pwmch_num_cdtyupd_reg_t; +typedef uint32_t hri_pwmch_num_cmr_reg_t; +typedef uint32_t hri_pwmch_num_cprd_reg_t; +typedef uint32_t hri_pwmch_num_cprdupd_reg_t; +typedef uint32_t hri_pwmch_num_dt_reg_t; +typedef uint32_t hri_pwmch_num_dtupd_reg_t; +typedef uint32_t hri_pwmcmp_cmpm_reg_t; +typedef uint32_t hri_pwmcmp_cmpmupd_reg_t; +typedef uint32_t hri_pwmcmp_cmpv_reg_t; +typedef uint32_t hri_pwmcmp_cmpvupd_reg_t; + +static inline hri_pwm_ccnt_reg_t hri_pwmchnum_get_CCNT_CNT_bf(const void *const hw, hri_pwm_ccnt_reg_t mask) +{ + return (((PwmChNum *)hw)->PWM_CCNT & PWM_CCNT_CNT(mask)) >> PWM_CCNT_CNT_Pos; +} + +static inline hri_pwm_ccnt_reg_t hri_pwmchnum_read_CCNT_CNT_bf(const void *const hw) +{ + return (((PwmChNum *)hw)->PWM_CCNT & PWM_CCNT_CNT_Msk) >> PWM_CCNT_CNT_Pos; +} + +static inline hri_pwm_ccnt_reg_t hri_pwmchnum_get_CCNT_reg(const void *const hw, hri_pwm_ccnt_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CCNT; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_ccnt_reg_t hri_pwmchnum_read_CCNT_reg(const void *const hw) +{ + return ((PwmChNum *)hw)->PWM_CCNT; +} + +static inline void hri_pwmchnum_set_CMR_CALG_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_CALG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_CALG) >> PWM_CMR_CALG_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_CALG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_CALG; + tmp |= value << PWM_CMR_CALG_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_CALG_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_CALG_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_CPOL_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_CPOL) >> PWM_CMR_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_CPOL; + tmp |= value << PWM_CMR_CPOL_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_CPOL_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_CPOL_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_CES_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_CES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_CES) >> PWM_CMR_CES_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_CES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_CES; + tmp |= value << PWM_CMR_CES_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_CES_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_CES_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_UPDS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_UPDS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_UPDS) >> PWM_CMR_UPDS_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_UPDS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_UPDS; + tmp |= value << PWM_CMR_UPDS_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_UPDS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_UPDS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_DPOLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_DPOLI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_DPOLI) >> PWM_CMR_DPOLI_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_DPOLI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_DPOLI; + tmp |= value << PWM_CMR_DPOLI_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_DPOLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_DPOLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_TCTS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_TCTS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_TCTS) >> PWM_CMR_TCTS_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_TCTS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_TCTS; + tmp |= value << PWM_CMR_TCTS_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_TCTS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_TCTS_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_DTE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_DTE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_DTE) >> PWM_CMR_DTE_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_DTE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_DTE; + tmp |= value << PWM_CMR_DTE_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_DTE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_DTE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_DTHI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_DTHI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_DTHI) >> PWM_CMR_DTHI_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_DTHI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_DTHI; + tmp |= value << PWM_CMR_DTHI_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_DTHI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_DTHI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_DTLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_DTLI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_DTLI) >> PWM_CMR_DTLI_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_DTLI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_DTLI; + tmp |= value << PWM_CMR_DTLI_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_DTLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_DTLI_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_PPM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmchnum_get_CMR_PPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_PPM) >> PWM_CMR_PPM_Pos; + return (bool)tmp; +} + +static inline void hri_pwmchnum_write_CMR_PPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_PPM; + tmp |= value << PWM_CMR_PPM_Pos; + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_PPM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_PPM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_set_CMR_CPRE_bf(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwmchnum_get_CMR_CPRE_bf(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_CPRE(mask)) >> PWM_CMR_CPRE_Pos; + return tmp; +} + +static inline void hri_pwmchnum_write_CMR_CPRE_bf(const void *const hw, hri_pwm_cmr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= ~PWM_CMR_CPRE_Msk; + tmp |= PWM_CMR_CPRE(data); + ((PwmChNum *)hw)->PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_CPRE_bf(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_CPRE_bf(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwmchnum_read_CMR_CPRE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp = (tmp & PWM_CMR_CPRE_Msk) >> PWM_CMR_CPRE_Pos; + return tmp; +} + +static inline void hri_pwmchnum_set_CMR_reg(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwmchnum_get_CMR_reg(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmchnum_write_CMR_reg(const void *const hw, hri_pwm_cmr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CMR_reg(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CMR_reg(const void *const hw, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CMR ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwmchnum_read_CMR_reg(const void *const hw) +{ + return ((PwmChNum *)hw)->PWM_CMR; +} + +static inline void hri_pwmchnum_set_CDTY_CDTY_bf(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY |= PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwmchnum_get_CDTY_CDTY_bf(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CDTY; + tmp = (tmp & PWM_CDTY_CDTY(mask)) >> PWM_CDTY_CDTY_Pos; + return tmp; +} + +static inline void hri_pwmchnum_write_CDTY_CDTY_bf(const void *const hw, hri_pwm_cdty_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CDTY; + tmp &= ~PWM_CDTY_CDTY_Msk; + tmp |= PWM_CDTY_CDTY(data); + ((PwmChNum *)hw)->PWM_CDTY = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CDTY_CDTY_bf(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY &= ~PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CDTY_CDTY_bf(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY ^= PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwmchnum_read_CDTY_CDTY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CDTY; + tmp = (tmp & PWM_CDTY_CDTY_Msk) >> PWM_CDTY_CDTY_Pos; + return tmp; +} + +static inline void hri_pwmchnum_set_CDTY_reg(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwmchnum_get_CDTY_reg(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CDTY; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmchnum_write_CDTY_reg(const void *const hw, hri_pwm_cdty_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CDTY_reg(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CDTY_reg(const void *const hw, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTY ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwmchnum_read_CDTY_reg(const void *const hw) +{ + return ((PwmChNum *)hw)->PWM_CDTY; +} + +static inline void hri_pwmchnum_set_CPRD_CPRD_bf(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD |= PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwmchnum_get_CPRD_CPRD_bf(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CPRD; + tmp = (tmp & PWM_CPRD_CPRD(mask)) >> PWM_CPRD_CPRD_Pos; + return tmp; +} + +static inline void hri_pwmchnum_write_CPRD_CPRD_bf(const void *const hw, hri_pwm_cprd_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_CPRD; + tmp &= ~PWM_CPRD_CPRD_Msk; + tmp |= PWM_CPRD_CPRD(data); + ((PwmChNum *)hw)->PWM_CPRD = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CPRD_CPRD_bf(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD &= ~PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CPRD_CPRD_bf(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD ^= PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwmchnum_read_CPRD_CPRD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CPRD; + tmp = (tmp & PWM_CPRD_CPRD_Msk) >> PWM_CPRD_CPRD_Pos; + return tmp; +} + +static inline void hri_pwmchnum_set_CPRD_reg(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwmchnum_get_CPRD_reg(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_CPRD; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmchnum_write_CPRD_reg(const void *const hw, hri_pwm_cprd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_CPRD_reg(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_CPRD_reg(const void *const hw, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRD ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwmchnum_read_CPRD_reg(const void *const hw) +{ + return ((PwmChNum *)hw)->PWM_CPRD; +} + +static inline void hri_pwmchnum_set_DT_DTH_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT |= PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_get_DT_DTH_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp = (tmp & PWM_DT_DTH(mask)) >> PWM_DT_DTH_Pos; + return tmp; +} + +static inline void hri_pwmchnum_write_DT_DTH_bf(const void *const hw, hri_pwm_dt_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp &= ~PWM_DT_DTH_Msk; + tmp |= PWM_DT_DTH(data); + ((PwmChNum *)hw)->PWM_DT = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_DT_DTH_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT &= ~PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_DT_DTH_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT ^= PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_read_DT_DTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp = (tmp & PWM_DT_DTH_Msk) >> PWM_DT_DTH_Pos; + return tmp; +} + +static inline void hri_pwmchnum_set_DT_DTL_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT |= PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_get_DT_DTL_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp = (tmp & PWM_DT_DTL(mask)) >> PWM_DT_DTL_Pos; + return tmp; +} + +static inline void hri_pwmchnum_write_DT_DTL_bf(const void *const hw, hri_pwm_dt_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp &= ~PWM_DT_DTL_Msk; + tmp |= PWM_DT_DTL(data); + ((PwmChNum *)hw)->PWM_DT = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_DT_DTL_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT &= ~PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_DT_DTL_bf(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT ^= PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_read_DT_DTL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp = (tmp & PWM_DT_DTL_Msk) >> PWM_DT_DTL_Pos; + return tmp; +} + +static inline void hri_pwmchnum_set_DT_reg(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_get_DT_reg(const void *const hw, hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmChNum *)hw)->PWM_DT; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmchnum_write_DT_reg(const void *const hw, hri_pwm_dt_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_clear_DT_reg(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_toggle_DT_reg(const void *const hw, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DT ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwmchnum_read_DT_reg(const void *const hw) +{ + return ((PwmChNum *)hw)->PWM_DT; +} + +static inline void hri_pwmchnum_write_CDTYUPD_reg(const void *const hw, hri_pwm_cdtyupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CDTYUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_write_CPRDUPD_reg(const void *const hw, hri_pwm_cprdupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_CPRDUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmchnum_write_DTUPD_reg(const void *const hw, hri_pwm_dtupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmChNum *)hw)->PWM_DTUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_ccnt_reg_t hri_pwm_get_CCNT_CNT_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_ccnt_reg_t mask) +{ + return (((Pwm *)hw)->PwmChNum[submodule_index].PWM_CCNT & PWM_CCNT_CNT(mask)) >> PWM_CCNT_CNT_Pos; +} + +static inline hri_pwm_ccnt_reg_t hri_pwm_read_CCNT_CNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Pwm *)hw)->PwmChNum[submodule_index].PWM_CCNT & PWM_CCNT_CNT_Msk) >> PWM_CCNT_CNT_Pos; +} + +static inline hri_pwm_ccnt_reg_t hri_pwm_get_CCNT_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_ccnt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CCNT; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_ccnt_reg_t hri_pwm_read_CCNT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CCNT; +} + +static inline void hri_pwm_set_CMR_CALG_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_CALG_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_CALG) >> PWM_CMR_CALG_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_CALG_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_CALG; + tmp |= value << PWM_CMR_CALG_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_CALG_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_CALG_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_CALG; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_CPOL_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_CPOL_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_CPOL) >> PWM_CMR_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_CPOL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_CPOL; + tmp |= value << PWM_CMR_CPOL_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_CPOL_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_CPOL_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_CPOL; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_CES_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_CES_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_CES) >> PWM_CMR_CES_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_CES_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_CES; + tmp |= value << PWM_CMR_CES_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_CES_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_CES_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_CES; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_UPDS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_UPDS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_UPDS) >> PWM_CMR_UPDS_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_UPDS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_UPDS; + tmp |= value << PWM_CMR_UPDS_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_UPDS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_UPDS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_UPDS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_DPOLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_DPOLI_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_DPOLI) >> PWM_CMR_DPOLI_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_DPOLI_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_DPOLI; + tmp |= value << PWM_CMR_DPOLI_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_DPOLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_DPOLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_DPOLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_TCTS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_TCTS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_TCTS) >> PWM_CMR_TCTS_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_TCTS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_TCTS; + tmp |= value << PWM_CMR_TCTS_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_TCTS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_TCTS_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_TCTS; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_DTE_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_DTE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_DTE) >> PWM_CMR_DTE_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_DTE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_DTE; + tmp |= value << PWM_CMR_DTE_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_DTE_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_DTE_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_DTE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_DTHI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_DTHI_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_DTHI) >> PWM_CMR_DTHI_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_DTHI_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_DTHI; + tmp |= value << PWM_CMR_DTHI_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_DTHI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_DTHI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_DTHI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_DTLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_DTLI_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_DTLI) >> PWM_CMR_DTLI_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_DTLI_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_DTLI; + tmp |= value << PWM_CMR_DTLI_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_DTLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_DTLI_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_DTLI; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_PPM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMR_PPM_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_PPM) >> PWM_CMR_PPM_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMR_PPM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_PPM; + tmp |= value << PWM_CMR_PPM_Pos; + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_PPM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_PPM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_PPM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwm_get_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_CPRE(mask)) >> PWM_CMR_CPRE_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= ~PWM_CMR_CPRE_Msk; + tmp |= PWM_CMR_CPRE(data); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= PWM_CMR_CPRE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwm_read_CMR_CPRE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp = (tmp & PWM_CMR_CPRE_Msk) >> PWM_CMR_CPRE_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMR_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwm_get_CMR_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CMR_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMR_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMR_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmr_reg_t hri_pwm_read_CMR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CMR; +} + +static inline void hri_pwm_set_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY |= PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwm_get_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cdty_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY; + tmp = (tmp & PWM_CDTY_CDTY(mask)) >> PWM_CDTY_CDTY_Pos; + return tmp; +} + +static inline void hri_pwm_write_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY; + tmp &= ~PWM_CDTY_CDTY_Msk; + tmp |= PWM_CDTY_CDTY(data); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY &= ~PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY ^= PWM_CDTY_CDTY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwm_read_CDTY_CDTY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY; + tmp = (tmp & PWM_CDTY_CDTY_Msk) >> PWM_CDTY_CDTY_Pos; + return tmp; +} + +static inline void hri_pwm_set_CDTY_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwm_get_CDTY_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_cdty_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CDTY_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CDTY_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CDTY_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cdty_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cdty_reg_t hri_pwm_read_CDTY_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTY; +} + +static inline void hri_pwm_set_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD |= PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwm_get_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cprd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD; + tmp = (tmp & PWM_CPRD_CPRD(mask)) >> PWM_CPRD_CPRD_Pos; + return tmp; +} + +static inline void hri_pwm_write_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD; + tmp &= ~PWM_CPRD_CPRD_Msk; + tmp |= PWM_CPRD_CPRD(data); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD &= ~PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD ^= PWM_CPRD_CPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwm_read_CPRD_CPRD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD; + tmp = (tmp & PWM_CPRD_CPRD_Msk) >> PWM_CPRD_CPRD_Pos; + return tmp; +} + +static inline void hri_pwm_set_CPRD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwm_get_CPRD_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_cprd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CPRD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CPRD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CPRD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cprd_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cprd_reg_t hri_pwm_read_CPRD_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRD; +} + +static inline void hri_pwm_set_DT_DTH_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT |= PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_get_DT_DTH_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp = (tmp & PWM_DT_DTH(mask)) >> PWM_DT_DTH_Pos; + return tmp; +} + +static inline void hri_pwm_write_DT_DTH_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp &= ~PWM_DT_DTH_Msk; + tmp |= PWM_DT_DTH(data); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_DT_DTH_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT &= ~PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_DT_DTH_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT ^= PWM_DT_DTH(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_read_DT_DTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp = (tmp & PWM_DT_DTH_Msk) >> PWM_DT_DTH_Pos; + return tmp; +} + +static inline void hri_pwm_set_DT_DTL_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT |= PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_get_DT_DTL_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp = (tmp & PWM_DT_DTL(mask)) >> PWM_DT_DTL_Pos; + return tmp; +} + +static inline void hri_pwm_write_DT_DTL_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp &= ~PWM_DT_DTL_Msk; + tmp |= PWM_DT_DTL(data); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_DT_DTL_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT &= ~PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_DT_DTL_bf(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT ^= PWM_DT_DTL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_read_DT_DTL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp = (tmp & PWM_DT_DTL_Msk) >> PWM_DT_DTL_Pos; + return tmp; +} + +static inline void hri_pwm_set_DT_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_get_DT_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_DT_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_DT_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_DT_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dt_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_dt_reg_t hri_pwm_read_DT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DT; +} + +static inline void hri_pwm_write_CDTYUPD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cdtyupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CDTYUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CPRDUPD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cprdupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_CPRDUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_DTUPD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_dtupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmChNum[submodule_index].PWM_DTUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_set_CMPV_CVM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV |= PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmcmp_get_CMPV_CVM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp = (tmp & PWM_CMPV_CVM) >> PWM_CMPV_CVM_Pos; + return (bool)tmp; +} + +static inline void hri_pwmcmp_write_CMPV_CVM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp &= ~PWM_CMPV_CVM; + tmp |= value << PWM_CMPV_CVM_Pos; + ((PwmCmp *)hw)->PWM_CMPV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPV_CVM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV &= ~PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPV_CVM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV ^= PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_set_CMPV_CV_bf(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV |= PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwmcmp_get_CMPV_CV_bf(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp = (tmp & PWM_CMPV_CV(mask)) >> PWM_CMPV_CV_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPV_CV_bf(const void *const hw, hri_pwm_cmpv_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp &= ~PWM_CMPV_CV_Msk; + tmp |= PWM_CMPV_CV(data); + ((PwmCmp *)hw)->PWM_CMPV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPV_CV_bf(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV &= ~PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPV_CV_bf(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV ^= PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwmcmp_read_CMPV_CV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp = (tmp & PWM_CMPV_CV_Msk) >> PWM_CMPV_CV_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPV_reg(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwmcmp_get_CMPV_reg(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPV; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPV_reg(const void *const hw, hri_pwm_cmpv_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPV_reg(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPV_reg(const void *const hw, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPV ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwmcmp_read_CMPV_reg(const void *const hw) +{ + return ((PwmCmp *)hw)->PWM_CMPV; +} + +static inline void hri_pwmcmp_set_CMPM_CEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwmcmp_get_CMPM_CEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CEN) >> PWM_CMPM_CEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CEN; + tmp |= value << PWM_CMPM_CEN_Pos; + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_set_CMPM_CTR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_CTR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CTR(mask)) >> PWM_CMPM_CTR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CTR_bf(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CTR_Msk; + tmp |= PWM_CMPM_CTR(data); + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CTR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CTR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_CTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CTR_Msk) >> PWM_CMPM_CTR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPM_CPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_CPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPR(mask)) >> PWM_CMPM_CPR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CPR_bf(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CPR_Msk; + tmp |= PWM_CMPM_CPR(data); + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_CPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPR_Msk) >> PWM_CMPM_CPR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPM_CPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_CPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPRCNT(mask)) >> PWM_CMPM_CPRCNT_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CPRCNT_Msk; + tmp |= PWM_CMPM_CPRCNT(data); + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_CPRCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPRCNT_Msk) >> PWM_CMPM_CPRCNT_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPM_CUPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_CUPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPR(mask)) >> PWM_CMPM_CUPR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CUPR_bf(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CUPR_Msk; + tmp |= PWM_CMPM_CUPR(data); + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CUPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CUPR_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_CUPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPR_Msk) >> PWM_CMPM_CUPR_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPM_CUPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_CUPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPRCNT(mask)) >> PWM_CMPM_CUPRCNT_Pos; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_CUPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= ~PWM_CMPM_CUPRCNT_Msk; + tmp |= PWM_CMPM_CUPRCNT(data); + ((PwmCmp *)hw)->PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_CUPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_CUPRCNT_bf(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_CUPRCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPRCNT_Msk) >> PWM_CMPM_CUPRCNT_Pos; + return tmp; +} + +static inline void hri_pwmcmp_set_CMPM_reg(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_get_CMPM_reg(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((PwmCmp *)hw)->PWM_CMPM; + tmp &= mask; + return tmp; +} + +static inline void hri_pwmcmp_write_CMPM_reg(const void *const hw, hri_pwm_cmpm_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_clear_CMPM_reg(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_toggle_CMPM_reg(const void *const hw, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPM ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwmcmp_read_CMPM_reg(const void *const hw) +{ + return ((PwmCmp *)hw)->PWM_CMPM; +} + +static inline void hri_pwmcmp_write_CMPVUPD_reg(const void *const hw, hri_pwm_cmpvupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPVUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwmcmp_write_CMPMUPD_reg(const void *const hw, hri_pwm_cmpmupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((PwmCmp *)hw)->PWM_CMPMUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMPV_CVM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV |= PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMPV_CVM_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp = (tmp & PWM_CMPV_CVM) >> PWM_CMPV_CVM_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMPV_CVM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp &= ~PWM_CMPV_CVM; + tmp |= value << PWM_CMPV_CVM_Pos; + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPV_CVM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV &= ~PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPV_CVM_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV ^= PWM_CMPV_CVM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMPV_CV_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV |= PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwm_get_CMPV_CV_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp = (tmp & PWM_CMPV_CV(mask)) >> PWM_CMPV_CV_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPV_CV_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp &= ~PWM_CMPV_CV_Msk; + tmp |= PWM_CMPV_CV(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPV_CV_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV &= ~PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPV_CV_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV ^= PWM_CMPV_CV(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwm_read_CMPV_CV_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp = (tmp & PWM_CMPV_CV_Msk) >> PWM_CMPV_CV_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPV_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwm_get_CMPV_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CMPV_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPV_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPV_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpv_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpv_reg_t hri_pwm_read_CMPV_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPV; +} + +static inline void hri_pwm_set_CMPM_CEN_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_CMPM_CEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CEN) >> PWM_CMPM_CEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_CMPM_CEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CEN; + tmp |= value << PWM_CMPM_CEN_Pos; + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CEN_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CEN_bit(const void *const hw, uint8_t submodule_index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CTR(mask)) >> PWM_CMPM_CTR_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CTR_Msk; + tmp |= PWM_CMPM_CTR(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CTR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_CTR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CTR_Msk) >> PWM_CMPM_CTR_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPR(mask)) >> PWM_CMPM_CPR_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CPR_Msk; + tmp |= PWM_CMPM_CPR(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_CPR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPR_Msk) >> PWM_CMPM_CPR_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPRCNT(mask)) >> PWM_CMPM_CPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CPRCNT_Msk; + tmp |= PWM_CMPM_CPRCNT(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_CPRCNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CPRCNT_Msk) >> PWM_CMPM_CPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPR(mask)) >> PWM_CMPM_CUPR_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CUPR_Msk; + tmp |= PWM_CMPM_CUPR(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CUPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_CUPR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPR_Msk) >> PWM_CMPM_CUPR_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPRCNT(mask)) >> PWM_CMPM_CUPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_write_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= ~PWM_CMPM_CUPRCNT_Msk; + tmp |= PWM_CMPM_CUPRCNT(data); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= PWM_CMPM_CUPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_CUPRCNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp = (tmp & PWM_CMPM_CUPRCNT_Msk) >> PWM_CMPM_CUPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_set_CMPM_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_get_CMPM_reg(const void *const hw, uint8_t submodule_index, + hri_pwm_cmpm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CMPM_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CMPM_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CMPM_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_cmpm_reg_t hri_pwm_read_CMPM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPM; +} + +static inline void hri_pwm_write_CMPVUPD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpvupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPVUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CMPMUPD_reg(const void *const hw, uint8_t submodule_index, hri_pwm_cmpmupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PwmCmp[submodule_index].PWM_CMPMUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ISR1_CHID0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_CHID0) >> PWM_ISR1_CHID0_Pos; +} + +static inline bool hri_pwm_get_ISR1_CHID1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_CHID1) >> PWM_ISR1_CHID1_Pos; +} + +static inline bool hri_pwm_get_ISR1_CHID2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_CHID2) >> PWM_ISR1_CHID2_Pos; +} + +static inline bool hri_pwm_get_ISR1_CHID3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_CHID3) >> PWM_ISR1_CHID3_Pos; +} + +static inline bool hri_pwm_get_ISR1_FCHID0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_FCHID0) >> PWM_ISR1_FCHID0_Pos; +} + +static inline bool hri_pwm_get_ISR1_FCHID1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_FCHID1) >> PWM_ISR1_FCHID1_Pos; +} + +static inline bool hri_pwm_get_ISR1_FCHID2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_FCHID2) >> PWM_ISR1_FCHID2_Pos; +} + +static inline bool hri_pwm_get_ISR1_FCHID3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR1 & PWM_ISR1_FCHID3) >> PWM_ISR1_FCHID3_Pos; +} + +static inline hri_pwm_isr1_reg_t hri_pwm_get_ISR1_reg(const void *const hw, hri_pwm_isr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ISR1; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_isr1_reg_t hri_pwm_read_ISR1_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_ISR1; +} + +static inline bool hri_pwm_get_ISR2_WRDY_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_WRDY) >> PWM_ISR2_WRDY_Pos; +} + +static inline bool hri_pwm_get_ISR2_UNRE_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_UNRE) >> PWM_ISR2_UNRE_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM0) >> PWM_ISR2_CMPM0_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM1) >> PWM_ISR2_CMPM1_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM2) >> PWM_ISR2_CMPM2_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM3) >> PWM_ISR2_CMPM3_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM4) >> PWM_ISR2_CMPM4_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM5) >> PWM_ISR2_CMPM5_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM6_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM6) >> PWM_ISR2_CMPM6_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPM7_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPM7) >> PWM_ISR2_CMPM7_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU0) >> PWM_ISR2_CMPU0_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU1) >> PWM_ISR2_CMPU1_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU2) >> PWM_ISR2_CMPU2_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU3) >> PWM_ISR2_CMPU3_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU4) >> PWM_ISR2_CMPU4_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU5) >> PWM_ISR2_CMPU5_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU6_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU6) >> PWM_ISR2_CMPU6_Pos; +} + +static inline bool hri_pwm_get_ISR2_CMPU7_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_ISR2 & PWM_ISR2_CMPU7) >> PWM_ISR2_CMPU7_Pos; +} + +static inline hri_pwm_isr2_reg_t hri_pwm_get_ISR2_reg(const void *const hw, hri_pwm_isr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ISR2; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_isr2_reg_t hri_pwm_read_ISR2_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_ISR2; +} + +static inline void hri_pwm_set_IMR1_CHID0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID0; +} + +static inline bool hri_pwm_get_IMR1_CHID0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_CHID0) >> PWM_IMR1_CHID0_Pos; +} + +static inline void hri_pwm_write_IMR1_CHID0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID0; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID0; + } +} + +static inline void hri_pwm_clear_IMR1_CHID0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID0; +} + +static inline void hri_pwm_set_IMR1_CHID1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID1; +} + +static inline bool hri_pwm_get_IMR1_CHID1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_CHID1) >> PWM_IMR1_CHID1_Pos; +} + +static inline void hri_pwm_write_IMR1_CHID1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID1; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID1; + } +} + +static inline void hri_pwm_clear_IMR1_CHID1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID1; +} + +static inline void hri_pwm_set_IMR1_CHID2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID2; +} + +static inline bool hri_pwm_get_IMR1_CHID2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_CHID2) >> PWM_IMR1_CHID2_Pos; +} + +static inline void hri_pwm_write_IMR1_CHID2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID2; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID2; + } +} + +static inline void hri_pwm_clear_IMR1_CHID2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID2; +} + +static inline void hri_pwm_set_IMR1_CHID3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID3; +} + +static inline bool hri_pwm_get_IMR1_CHID3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_CHID3) >> PWM_IMR1_CHID3_Pos; +} + +static inline void hri_pwm_write_IMR1_CHID3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID3; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_CHID3; + } +} + +static inline void hri_pwm_clear_IMR1_CHID3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_CHID3; +} + +static inline void hri_pwm_set_IMR1_FCHID0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID0; +} + +static inline bool hri_pwm_get_IMR1_FCHID0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_FCHID0) >> PWM_IMR1_FCHID0_Pos; +} + +static inline void hri_pwm_write_IMR1_FCHID0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID0; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID0; + } +} + +static inline void hri_pwm_clear_IMR1_FCHID0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID0; +} + +static inline void hri_pwm_set_IMR1_FCHID1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID1; +} + +static inline bool hri_pwm_get_IMR1_FCHID1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_FCHID1) >> PWM_IMR1_FCHID1_Pos; +} + +static inline void hri_pwm_write_IMR1_FCHID1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID1; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID1; + } +} + +static inline void hri_pwm_clear_IMR1_FCHID1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID1; +} + +static inline void hri_pwm_set_IMR1_FCHID2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID2; +} + +static inline bool hri_pwm_get_IMR1_FCHID2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_FCHID2) >> PWM_IMR1_FCHID2_Pos; +} + +static inline void hri_pwm_write_IMR1_FCHID2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID2; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID2; + } +} + +static inline void hri_pwm_clear_IMR1_FCHID2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID2; +} + +static inline void hri_pwm_set_IMR1_FCHID3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID3; +} + +static inline bool hri_pwm_get_IMR1_FCHID3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR1 & PWM_IMR1_FCHID3) >> PWM_IMR1_FCHID3_Pos; +} + +static inline void hri_pwm_write_IMR1_FCHID3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID3; + } else { + ((Pwm *)hw)->PWM_IER1 = PWM_IMR1_FCHID3; + } +} + +static inline void hri_pwm_clear_IMR1_FCHID3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR1 = PWM_IMR1_FCHID3; +} + +static inline void hri_pwm_set_IMR1_reg(const void *const hw, hri_pwm_imr1_reg_t mask) +{ + ((Pwm *)hw)->PWM_IER1 = mask; +} + +static inline hri_pwm_imr1_reg_t hri_pwm_get_IMR1_reg(const void *const hw, hri_pwm_imr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_IMR1; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_imr1_reg_t hri_pwm_read_IMR1_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_IMR1; +} + +static inline void hri_pwm_write_IMR1_reg(const void *const hw, hri_pwm_imr1_reg_t data) +{ + ((Pwm *)hw)->PWM_IER1 = data; + ((Pwm *)hw)->PWM_IDR1 = ~data; +} + +static inline void hri_pwm_clear_IMR1_reg(const void *const hw, hri_pwm_imr1_reg_t mask) +{ + ((Pwm *)hw)->PWM_IDR1 = mask; +} + +static inline void hri_pwm_set_IMR2_WRDY_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_WRDY; +} + +static inline bool hri_pwm_get_IMR2_WRDY_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_WRDY) >> PWM_IMR2_WRDY_Pos; +} + +static inline void hri_pwm_write_IMR2_WRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_WRDY; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_WRDY; + } +} + +static inline void hri_pwm_clear_IMR2_WRDY_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_WRDY; +} + +static inline void hri_pwm_set_IMR2_UNRE_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_UNRE; +} + +static inline bool hri_pwm_get_IMR2_UNRE_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_UNRE) >> PWM_IMR2_UNRE_Pos; +} + +static inline void hri_pwm_write_IMR2_UNRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_UNRE; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_UNRE; + } +} + +static inline void hri_pwm_clear_IMR2_UNRE_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_UNRE; +} + +static inline void hri_pwm_set_IMR2_CMPM0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM0; +} + +static inline bool hri_pwm_get_IMR2_CMPM0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM0) >> PWM_IMR2_CMPM0_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM0; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM0; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM0; +} + +static inline void hri_pwm_set_IMR2_CMPM1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM1; +} + +static inline bool hri_pwm_get_IMR2_CMPM1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM1) >> PWM_IMR2_CMPM1_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM1; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM1; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM1; +} + +static inline void hri_pwm_set_IMR2_CMPM2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM2; +} + +static inline bool hri_pwm_get_IMR2_CMPM2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM2) >> PWM_IMR2_CMPM2_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM2; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM2; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM2; +} + +static inline void hri_pwm_set_IMR2_CMPM3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM3; +} + +static inline bool hri_pwm_get_IMR2_CMPM3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM3) >> PWM_IMR2_CMPM3_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM3; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM3; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM3; +} + +static inline void hri_pwm_set_IMR2_CMPM4_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM4; +} + +static inline bool hri_pwm_get_IMR2_CMPM4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM4) >> PWM_IMR2_CMPM4_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM4; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM4; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM4_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM4; +} + +static inline void hri_pwm_set_IMR2_CMPM5_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM5; +} + +static inline bool hri_pwm_get_IMR2_CMPM5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM5) >> PWM_IMR2_CMPM5_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM5; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM5; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM5_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM5; +} + +static inline void hri_pwm_set_IMR2_CMPM6_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM6; +} + +static inline bool hri_pwm_get_IMR2_CMPM6_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM6) >> PWM_IMR2_CMPM6_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM6; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM6; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM6_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM6; +} + +static inline void hri_pwm_set_IMR2_CMPM7_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM7; +} + +static inline bool hri_pwm_get_IMR2_CMPM7_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPM7) >> PWM_IMR2_CMPM7_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPM7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM7; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPM7; + } +} + +static inline void hri_pwm_clear_IMR2_CMPM7_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPM7; +} + +static inline void hri_pwm_set_IMR2_CMPU0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU0; +} + +static inline bool hri_pwm_get_IMR2_CMPU0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU0) >> PWM_IMR2_CMPU0_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU0; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU0; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU0_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU0; +} + +static inline void hri_pwm_set_IMR2_CMPU1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU1; +} + +static inline bool hri_pwm_get_IMR2_CMPU1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU1) >> PWM_IMR2_CMPU1_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU1; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU1; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU1_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU1; +} + +static inline void hri_pwm_set_IMR2_CMPU2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU2; +} + +static inline bool hri_pwm_get_IMR2_CMPU2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU2) >> PWM_IMR2_CMPU2_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU2; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU2; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU2_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU2; +} + +static inline void hri_pwm_set_IMR2_CMPU3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU3; +} + +static inline bool hri_pwm_get_IMR2_CMPU3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU3) >> PWM_IMR2_CMPU3_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU3; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU3; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU3_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU3; +} + +static inline void hri_pwm_set_IMR2_CMPU4_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU4; +} + +static inline bool hri_pwm_get_IMR2_CMPU4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU4) >> PWM_IMR2_CMPU4_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU4; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU4; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU4_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU4; +} + +static inline void hri_pwm_set_IMR2_CMPU5_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU5; +} + +static inline bool hri_pwm_get_IMR2_CMPU5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU5) >> PWM_IMR2_CMPU5_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU5; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU5; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU5_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU5; +} + +static inline void hri_pwm_set_IMR2_CMPU6_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU6; +} + +static inline bool hri_pwm_get_IMR2_CMPU6_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU6) >> PWM_IMR2_CMPU6_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU6; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU6; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU6_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU6; +} + +static inline void hri_pwm_set_IMR2_CMPU7_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU7; +} + +static inline bool hri_pwm_get_IMR2_CMPU7_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_IMR2 & PWM_IMR2_CMPU7) >> PWM_IMR2_CMPU7_Pos; +} + +static inline void hri_pwm_write_IMR2_CMPU7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU7; + } else { + ((Pwm *)hw)->PWM_IER2 = PWM_IMR2_CMPU7; + } +} + +static inline void hri_pwm_clear_IMR2_CMPU7_bit(const void *const hw) +{ + ((Pwm *)hw)->PWM_IDR2 = PWM_IMR2_CMPU7; +} + +static inline void hri_pwm_set_IMR2_reg(const void *const hw, hri_pwm_imr2_reg_t mask) +{ + ((Pwm *)hw)->PWM_IER2 = mask; +} + +static inline hri_pwm_imr2_reg_t hri_pwm_get_IMR2_reg(const void *const hw, hri_pwm_imr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_IMR2; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_imr2_reg_t hri_pwm_read_IMR2_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_IMR2; +} + +static inline void hri_pwm_write_IMR2_reg(const void *const hw, hri_pwm_imr2_reg_t data) +{ + ((Pwm *)hw)->PWM_IER2 = data; + ((Pwm *)hw)->PWM_IDR2 = ~data; +} + +static inline void hri_pwm_clear_IMR2_reg(const void *const hw, hri_pwm_imr2_reg_t mask) +{ + ((Pwm *)hw)->PWM_IDR2 = mask; +} + +static inline bool hri_pwm_get_SR_CHID0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_SR & PWM_SR_CHID0) > 0; +} + +static inline bool hri_pwm_get_SR_CHID1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_SR & PWM_SR_CHID1) > 0; +} + +static inline bool hri_pwm_get_SR_CHID2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_SR & PWM_SR_CHID2) > 0; +} + +static inline bool hri_pwm_get_SR_CHID3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_SR & PWM_SR_CHID3) > 0; +} + +static inline hri_pwm_sr_reg_t hri_pwm_get_SR_reg(const void *const hw, hri_pwm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SR; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_sr_reg_t hri_pwm_read_SR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SR; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_get_FSR_FIV_bf(const void *const hw, hri_pwm_fsr_reg_t mask) +{ + return (((Pwm *)hw)->PWM_FSR & PWM_FSR_FIV(mask)) >> PWM_FSR_FIV_Pos; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_read_FSR_FIV_bf(const void *const hw) +{ + return (((Pwm *)hw)->PWM_FSR & PWM_FSR_FIV_Msk) >> PWM_FSR_FIV_Pos; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_get_FSR_FS_bf(const void *const hw, hri_pwm_fsr_reg_t mask) +{ + return (((Pwm *)hw)->PWM_FSR & PWM_FSR_FS(mask)) >> PWM_FSR_FS_Pos; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_read_FSR_FS_bf(const void *const hw) +{ + return (((Pwm *)hw)->PWM_FSR & PWM_FSR_FS_Msk) >> PWM_FSR_FS_Pos; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_get_FSR_reg(const void *const hw, hri_pwm_fsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FSR; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_fsr_reg_t hri_pwm_read_FSR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_FSR; +} + +static inline bool hri_pwm_get_WPSR_WPSWS0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS0) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPSWS1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS1) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPSWS2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS2) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPSWS3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS3) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPSWS4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS4) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPSWS5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPSWS5) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPVS) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS0_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS0) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS1_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS1) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS2_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS2) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS3_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS3) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS4_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS4) > 0; +} + +static inline bool hri_pwm_get_WPSR_WPHWS5_bit(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPHWS5) > 0; +} + +static inline hri_pwm_wpsr_reg_t hri_pwm_get_WPSR_WPVSRC_bf(const void *const hw, hri_pwm_wpsr_reg_t mask) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPVSRC(mask)) >> PWM_WPSR_WPVSRC_Pos; +} + +static inline hri_pwm_wpsr_reg_t hri_pwm_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pwm *)hw)->PWM_WPSR & PWM_WPSR_WPVSRC_Msk) >> PWM_WPSR_WPVSRC_Pos; +} + +static inline hri_pwm_wpsr_reg_t hri_pwm_get_WPSR_reg(const void *const hw, hri_pwm_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_pwm_wpsr_reg_t hri_pwm_read_WPSR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_WPSR; +} + +static inline void hri_pwm_set_CLK_DIVA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK |= PWM_CLK_DIVA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_get_CLK_DIVA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_DIVA(mask)) >> PWM_CLK_DIVA_Pos; + return tmp; +} + +static inline void hri_pwm_write_CLK_DIVA_bf(const void *const hw, hri_pwm_clk_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_CLK; + tmp &= ~PWM_CLK_DIVA_Msk; + tmp |= PWM_CLK_DIVA(data); + ((Pwm *)hw)->PWM_CLK = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CLK_DIVA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK &= ~PWM_CLK_DIVA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CLK_DIVA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK ^= PWM_CLK_DIVA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_read_CLK_DIVA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_DIVA_Msk) >> PWM_CLK_DIVA_Pos; + return tmp; +} + +static inline void hri_pwm_set_CLK_PREA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK |= PWM_CLK_PREA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_get_CLK_PREA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_PREA(mask)) >> PWM_CLK_PREA_Pos; + return tmp; +} + +static inline void hri_pwm_write_CLK_PREA_bf(const void *const hw, hri_pwm_clk_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_CLK; + tmp &= ~PWM_CLK_PREA_Msk; + tmp |= PWM_CLK_PREA(data); + ((Pwm *)hw)->PWM_CLK = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CLK_PREA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK &= ~PWM_CLK_PREA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CLK_PREA_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK ^= PWM_CLK_PREA(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_read_CLK_PREA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_PREA_Msk) >> PWM_CLK_PREA_Pos; + return tmp; +} + +static inline void hri_pwm_set_CLK_DIVB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK |= PWM_CLK_DIVB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_get_CLK_DIVB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_DIVB(mask)) >> PWM_CLK_DIVB_Pos; + return tmp; +} + +static inline void hri_pwm_write_CLK_DIVB_bf(const void *const hw, hri_pwm_clk_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_CLK; + tmp &= ~PWM_CLK_DIVB_Msk; + tmp |= PWM_CLK_DIVB(data); + ((Pwm *)hw)->PWM_CLK = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CLK_DIVB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK &= ~PWM_CLK_DIVB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CLK_DIVB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK ^= PWM_CLK_DIVB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_read_CLK_DIVB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_DIVB_Msk) >> PWM_CLK_DIVB_Pos; + return tmp; +} + +static inline void hri_pwm_set_CLK_PREB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK |= PWM_CLK_PREB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_get_CLK_PREB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_PREB(mask)) >> PWM_CLK_PREB_Pos; + return tmp; +} + +static inline void hri_pwm_write_CLK_PREB_bf(const void *const hw, hri_pwm_clk_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_CLK; + tmp &= ~PWM_CLK_PREB_Msk; + tmp |= PWM_CLK_PREB(data); + ((Pwm *)hw)->PWM_CLK = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CLK_PREB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK &= ~PWM_CLK_PREB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CLK_PREB_bf(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK ^= PWM_CLK_PREB(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_read_CLK_PREB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp = (tmp & PWM_CLK_PREB_Msk) >> PWM_CLK_PREB_Pos; + return tmp; +} + +static inline void hri_pwm_set_CLK_reg(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_get_CLK_reg(const void *const hw, hri_pwm_clk_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_CLK; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_CLK_reg(const void *const hw, hri_pwm_clk_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_CLK_reg(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_CLK_reg(const void *const hw, hri_pwm_clk_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CLK ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_clk_reg_t hri_pwm_read_CLK_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_CLK; +} + +static inline void hri_pwm_set_SCM_SYNC0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_SYNC0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCM_SYNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_SYNC0) >> PWM_SCM_SYNC0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCM_SYNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_SYNC0; + tmp |= value << PWM_SCM_SYNC0_Pos; + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_SYNC0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_SYNC0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_SYNC0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_SYNC0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCM_SYNC1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_SYNC1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCM_SYNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_SYNC1) >> PWM_SCM_SYNC1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCM_SYNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_SYNC1; + tmp |= value << PWM_SCM_SYNC1_Pos; + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_SYNC1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_SYNC1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_SYNC1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_SYNC1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCM_SYNC2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_SYNC2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCM_SYNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_SYNC2) >> PWM_SCM_SYNC2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCM_SYNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_SYNC2; + tmp |= value << PWM_SCM_SYNC2_Pos; + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_SYNC2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_SYNC2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_SYNC2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_SYNC2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCM_SYNC3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_SYNC3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCM_SYNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_SYNC3) >> PWM_SCM_SYNC3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCM_SYNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_SYNC3; + tmp |= value << PWM_SCM_SYNC3_Pos; + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_SYNC3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_SYNC3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_SYNC3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_SYNC3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCM_PTRM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_PTRM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCM_PTRM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_PTRM) >> PWM_SCM_PTRM_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCM_PTRM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_PTRM; + tmp |= value << PWM_SCM_PTRM_Pos; + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_PTRM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_PTRM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_PTRM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_PTRM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCM_UPDM_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_UPDM(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_get_SCM_UPDM_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_UPDM(mask)) >> PWM_SCM_UPDM_Pos; + return tmp; +} + +static inline void hri_pwm_write_SCM_UPDM_bf(const void *const hw, hri_pwm_scm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_UPDM_Msk; + tmp |= PWM_SCM_UPDM(data); + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_UPDM_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_UPDM(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_UPDM_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_UPDM(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_read_SCM_UPDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_UPDM_Msk) >> PWM_SCM_UPDM_Pos; + return tmp; +} + +static inline void hri_pwm_set_SCM_PTRCS_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= PWM_SCM_PTRCS(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_get_SCM_PTRCS_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_PTRCS(mask)) >> PWM_SCM_PTRCS_Pos; + return tmp; +} + +static inline void hri_pwm_write_SCM_PTRCS_bf(const void *const hw, hri_pwm_scm_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= ~PWM_SCM_PTRCS_Msk; + tmp |= PWM_SCM_PTRCS(data); + ((Pwm *)hw)->PWM_SCM = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_PTRCS_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~PWM_SCM_PTRCS(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_PTRCS_bf(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= PWM_SCM_PTRCS(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_read_SCM_PTRCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp = (tmp & PWM_SCM_PTRCS_Msk) >> PWM_SCM_PTRCS_Pos; + return tmp; +} + +static inline void hri_pwm_set_SCM_reg(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_get_SCM_reg(const void *const hw, hri_pwm_scm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCM; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_SCM_reg(const void *const hw, hri_pwm_scm_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCM_reg(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCM_reg(const void *const hw, hri_pwm_scm_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCM ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scm_reg_t hri_pwm_read_SCM_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SCM; +} + +static inline void hri_pwm_set_SCUC_UPDULOCK_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC |= PWM_SCUC_UPDULOCK; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SCUC_UPDULOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUC; + tmp = (tmp & PWM_SCUC_UPDULOCK) >> PWM_SCUC_UPDULOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SCUC_UPDULOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCUC; + tmp &= ~PWM_SCUC_UPDULOCK; + tmp |= value << PWM_SCUC_UPDULOCK_Pos; + ((Pwm *)hw)->PWM_SCUC = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCUC_UPDULOCK_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC &= ~PWM_SCUC_UPDULOCK; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCUC_UPDULOCK_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC ^= PWM_SCUC_UPDULOCK; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SCUC_reg(const void *const hw, hri_pwm_scuc_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scuc_reg_t hri_pwm_get_SCUC_reg(const void *const hw, hri_pwm_scuc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUC; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_SCUC_reg(const void *const hw, hri_pwm_scuc_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCUC_reg(const void *const hw, hri_pwm_scuc_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCUC_reg(const void *const hw, hri_pwm_scuc_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUC ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scuc_reg_t hri_pwm_read_SCUC_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SCUC; +} + +static inline void hri_pwm_set_SCUP_UPR_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP |= PWM_SCUP_UPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_get_SCUP_UPR_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp = (tmp & PWM_SCUP_UPR(mask)) >> PWM_SCUP_UPR_Pos; + return tmp; +} + +static inline void hri_pwm_write_SCUP_UPR_bf(const void *const hw, hri_pwm_scup_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp &= ~PWM_SCUP_UPR_Msk; + tmp |= PWM_SCUP_UPR(data); + ((Pwm *)hw)->PWM_SCUP = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCUP_UPR_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP &= ~PWM_SCUP_UPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCUP_UPR_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP ^= PWM_SCUP_UPR(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_read_SCUP_UPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp = (tmp & PWM_SCUP_UPR_Msk) >> PWM_SCUP_UPR_Pos; + return tmp; +} + +static inline void hri_pwm_set_SCUP_UPRCNT_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP |= PWM_SCUP_UPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_get_SCUP_UPRCNT_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp = (tmp & PWM_SCUP_UPRCNT(mask)) >> PWM_SCUP_UPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_write_SCUP_UPRCNT_bf(const void *const hw, hri_pwm_scup_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp &= ~PWM_SCUP_UPRCNT_Msk; + tmp |= PWM_SCUP_UPRCNT(data); + ((Pwm *)hw)->PWM_SCUP = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCUP_UPRCNT_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP &= ~PWM_SCUP_UPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCUP_UPRCNT_bf(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP ^= PWM_SCUP_UPRCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_read_SCUP_UPRCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp = (tmp & PWM_SCUP_UPRCNT_Msk) >> PWM_SCUP_UPRCNT_Pos; + return tmp; +} + +static inline void hri_pwm_set_SCUP_reg(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_get_SCUP_reg(const void *const hw, hri_pwm_scup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SCUP; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_SCUP_reg(const void *const hw, hri_pwm_scup_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SCUP_reg(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SCUP_reg(const void *const hw, hri_pwm_scup_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUP ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_scup_reg_t hri_pwm_read_SCUP_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SCUP; +} + +static inline void hri_pwm_set_OOV_OOVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVH0) >> PWM_OOV_OOVH0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVH0; + tmp |= value << PWM_OOV_OOVH0_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVH1) >> PWM_OOV_OOVH1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVH1; + tmp |= value << PWM_OOV_OOVH1_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVH2) >> PWM_OOV_OOVH2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVH2; + tmp |= value << PWM_OOV_OOVH2_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVH3) >> PWM_OOV_OOVH3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVH3; + tmp |= value << PWM_OOV_OOVH3_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVL0) >> PWM_OOV_OOVL0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVL0; + tmp |= value << PWM_OOV_OOVL0_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVL1) >> PWM_OOV_OOVL1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVL1; + tmp |= value << PWM_OOV_OOVL1_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVL2) >> PWM_OOV_OOVL2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVL2; + tmp |= value << PWM_OOV_OOVL2_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_OOVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= PWM_OOV_OOVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OOV_OOVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp = (tmp & PWM_OOV_OOVL3) >> PWM_OOV_OOVL3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OOV_OOVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= ~PWM_OOV_OOVL3; + tmp |= value << PWM_OOV_OOVL3_Pos; + ((Pwm *)hw)->PWM_OOV = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_OOVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~PWM_OOV_OOVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_OOVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= PWM_OOV_OOVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OOV_reg(const void *const hw, hri_pwm_oov_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_oov_reg_t hri_pwm_get_OOV_reg(const void *const hw, hri_pwm_oov_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OOV; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_OOV_reg(const void *const hw, hri_pwm_oov_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OOV_reg(const void *const hw, hri_pwm_oov_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OOV_reg(const void *const hw, hri_pwm_oov_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OOV ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_oov_reg_t hri_pwm_read_OOV_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_OOV; +} + +static inline void hri_pwm_set_OS_OSH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSH0) >> PWM_OS_OSH0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSH0; + tmp |= value << PWM_OS_OSH0_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSH1) >> PWM_OS_OSH1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSH1; + tmp |= value << PWM_OS_OSH1_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSH2) >> PWM_OS_OSH2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSH2; + tmp |= value << PWM_OS_OSH2_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSH3) >> PWM_OS_OSH3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSH3; + tmp |= value << PWM_OS_OSH3_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSL0) >> PWM_OS_OSL0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSL0; + tmp |= value << PWM_OS_OSL0_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSL1) >> PWM_OS_OSL1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSL1; + tmp |= value << PWM_OS_OSL1_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSL2) >> PWM_OS_OSL2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSL2; + tmp |= value << PWM_OS_OSL2_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_OSL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= PWM_OS_OSL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_OS_OSL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp = (tmp & PWM_OS_OSL3) >> PWM_OS_OSL3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_OS_OSL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= ~PWM_OS_OSL3; + tmp |= value << PWM_OS_OSL3_Pos; + ((Pwm *)hw)->PWM_OS = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_OSL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~PWM_OS_OSL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_OSL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= PWM_OS_OSL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_OS_reg(const void *const hw, hri_pwm_os_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_os_reg_t hri_pwm_get_OS_reg(const void *const hw, hri_pwm_os_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_OS; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_OS_reg(const void *const hw, hri_pwm_os_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_OS_reg(const void *const hw, hri_pwm_os_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_OS_reg(const void *const hw, hri_pwm_os_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OS ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_os_reg_t hri_pwm_read_OS_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_OS; +} + +static inline void hri_pwm_set_FMR_FPOL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR |= PWM_FMR_FPOL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_get_FMR_FPOL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FPOL(mask)) >> PWM_FMR_FPOL_Pos; + return tmp; +} + +static inline void hri_pwm_write_FMR_FPOL_bf(const void *const hw, hri_pwm_fmr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FMR; + tmp &= ~PWM_FMR_FPOL_Msk; + tmp |= PWM_FMR_FPOL(data); + ((Pwm *)hw)->PWM_FMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FMR_FPOL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR &= ~PWM_FMR_FPOL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FMR_FPOL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR ^= PWM_FMR_FPOL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_read_FMR_FPOL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FPOL_Msk) >> PWM_FMR_FPOL_Pos; + return tmp; +} + +static inline void hri_pwm_set_FMR_FMOD_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR |= PWM_FMR_FMOD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_get_FMR_FMOD_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FMOD(mask)) >> PWM_FMR_FMOD_Pos; + return tmp; +} + +static inline void hri_pwm_write_FMR_FMOD_bf(const void *const hw, hri_pwm_fmr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FMR; + tmp &= ~PWM_FMR_FMOD_Msk; + tmp |= PWM_FMR_FMOD(data); + ((Pwm *)hw)->PWM_FMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FMR_FMOD_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR &= ~PWM_FMR_FMOD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FMR_FMOD_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR ^= PWM_FMR_FMOD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_read_FMR_FMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FMOD_Msk) >> PWM_FMR_FMOD_Pos; + return tmp; +} + +static inline void hri_pwm_set_FMR_FFIL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR |= PWM_FMR_FFIL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_get_FMR_FFIL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FFIL(mask)) >> PWM_FMR_FFIL_Pos; + return tmp; +} + +static inline void hri_pwm_write_FMR_FFIL_bf(const void *const hw, hri_pwm_fmr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FMR; + tmp &= ~PWM_FMR_FFIL_Msk; + tmp |= PWM_FMR_FFIL(data); + ((Pwm *)hw)->PWM_FMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FMR_FFIL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR &= ~PWM_FMR_FFIL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FMR_FFIL_bf(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR ^= PWM_FMR_FFIL(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_read_FMR_FFIL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp = (tmp & PWM_FMR_FFIL_Msk) >> PWM_FMR_FFIL_Pos; + return tmp; +} + +static inline void hri_pwm_set_FMR_reg(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_get_FMR_reg(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_FMR_reg(const void *const hw, hri_pwm_fmr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FMR_reg(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FMR_reg(const void *const hw, hri_pwm_fmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FMR ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fmr_reg_t hri_pwm_read_FMR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_FMR; +} + +static inline void hri_pwm_set_FPV1_FPVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVH0) >> PWM_FPV1_FPVH0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVH0; + tmp |= value << PWM_FPV1_FPVH0_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVH1) >> PWM_FPV1_FPVH1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVH1; + tmp |= value << PWM_FPV1_FPVH1_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVH2) >> PWM_FPV1_FPVH2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVH2; + tmp |= value << PWM_FPV1_FPVH2_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVH3) >> PWM_FPV1_FPVH3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVH3; + tmp |= value << PWM_FPV1_FPVH3_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVL0) >> PWM_FPV1_FPVL0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVL0; + tmp |= value << PWM_FPV1_FPVL0_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVL1) >> PWM_FPV1_FPVL1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVL1; + tmp |= value << PWM_FPV1_FPVL1_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVL2) >> PWM_FPV1_FPVL2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVL2; + tmp |= value << PWM_FPV1_FPVL2_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_FPVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= PWM_FPV1_FPVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV1_FPVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp = (tmp & PWM_FPV1_FPVL3) >> PWM_FPV1_FPVL3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV1_FPVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= ~PWM_FPV1_FPVL3; + tmp |= value << PWM_FPV1_FPVL3_Pos; + ((Pwm *)hw)->PWM_FPV1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_FPVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~PWM_FPV1_FPVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_FPVL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= PWM_FPV1_FPVL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV1_reg(const void *const hw, hri_pwm_fpv1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpv1_reg_t hri_pwm_get_FPV1_reg(const void *const hw, hri_pwm_fpv1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV1; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_FPV1_reg(const void *const hw, hri_pwm_fpv1_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV1_reg(const void *const hw, hri_pwm_fpv1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV1_reg(const void *const hw, hri_pwm_fpv1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV1 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpv1_reg_t hri_pwm_read_FPV1_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_FPV1; +} + +static inline void hri_pwm_set_FPE_FPE0_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE |= PWM_FPE_FPE0(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_get_FPE_FPE0_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE0(mask)) >> PWM_FPE_FPE0_Pos; + return tmp; +} + +static inline void hri_pwm_write_FPE_FPE0_bf(const void *const hw, hri_pwm_fpe_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPE; + tmp &= ~PWM_FPE_FPE0_Msk; + tmp |= PWM_FPE_FPE0(data); + ((Pwm *)hw)->PWM_FPE = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPE_FPE0_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE &= ~PWM_FPE_FPE0(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPE_FPE0_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE ^= PWM_FPE_FPE0(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_read_FPE_FPE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE0_Msk) >> PWM_FPE_FPE0_Pos; + return tmp; +} + +static inline void hri_pwm_set_FPE_FPE1_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE |= PWM_FPE_FPE1(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_get_FPE_FPE1_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE1(mask)) >> PWM_FPE_FPE1_Pos; + return tmp; +} + +static inline void hri_pwm_write_FPE_FPE1_bf(const void *const hw, hri_pwm_fpe_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPE; + tmp &= ~PWM_FPE_FPE1_Msk; + tmp |= PWM_FPE_FPE1(data); + ((Pwm *)hw)->PWM_FPE = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPE_FPE1_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE &= ~PWM_FPE_FPE1(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPE_FPE1_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE ^= PWM_FPE_FPE1(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_read_FPE_FPE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE1_Msk) >> PWM_FPE_FPE1_Pos; + return tmp; +} + +static inline void hri_pwm_set_FPE_FPE2_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE |= PWM_FPE_FPE2(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_get_FPE_FPE2_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE2(mask)) >> PWM_FPE_FPE2_Pos; + return tmp; +} + +static inline void hri_pwm_write_FPE_FPE2_bf(const void *const hw, hri_pwm_fpe_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPE; + tmp &= ~PWM_FPE_FPE2_Msk; + tmp |= PWM_FPE_FPE2(data); + ((Pwm *)hw)->PWM_FPE = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPE_FPE2_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE &= ~PWM_FPE_FPE2(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPE_FPE2_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE ^= PWM_FPE_FPE2(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_read_FPE_FPE2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE2_Msk) >> PWM_FPE_FPE2_Pos; + return tmp; +} + +static inline void hri_pwm_set_FPE_FPE3_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE |= PWM_FPE_FPE3(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_get_FPE_FPE3_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE3(mask)) >> PWM_FPE_FPE3_Pos; + return tmp; +} + +static inline void hri_pwm_write_FPE_FPE3_bf(const void *const hw, hri_pwm_fpe_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPE; + tmp &= ~PWM_FPE_FPE3_Msk; + tmp |= PWM_FPE_FPE3(data); + ((Pwm *)hw)->PWM_FPE = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPE_FPE3_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE &= ~PWM_FPE_FPE3(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPE_FPE3_bf(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE ^= PWM_FPE_FPE3(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_read_FPE_FPE3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp = (tmp & PWM_FPE_FPE3_Msk) >> PWM_FPE_FPE3_Pos; + return tmp; +} + +static inline void hri_pwm_set_FPE_reg(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_get_FPE_reg(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPE; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_FPE_reg(const void *const hw, hri_pwm_fpe_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPE_reg(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPE_reg(const void *const hw, hri_pwm_fpe_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPE ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpe_reg_t hri_pwm_read_FPE_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_FPE; +} + +static inline void hri_pwm_set_ELMR_CSEL0_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL0) >> PWM_ELMR_CSEL0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL0; + tmp |= value << PWM_ELMR_CSEL0_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL0_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL0_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL1_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL1) >> PWM_ELMR_CSEL1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL1; + tmp |= value << PWM_ELMR_CSEL1_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL1_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL1_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL2_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL2) >> PWM_ELMR_CSEL2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL2; + tmp |= value << PWM_ELMR_CSEL2_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL2_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL2_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL3_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL3) >> PWM_ELMR_CSEL3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL3; + tmp |= value << PWM_ELMR_CSEL3_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL3_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL3_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL4_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL4; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL4) >> PWM_ELMR_CSEL4_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL4; + tmp |= value << PWM_ELMR_CSEL4_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL4_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL4; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL4_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL4; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL5_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL5; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL5) >> PWM_ELMR_CSEL5_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL5; + tmp |= value << PWM_ELMR_CSEL5_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL5_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL5; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL5_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL5; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL6_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL6; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL6) >> PWM_ELMR_CSEL6_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL6; + tmp |= value << PWM_ELMR_CSEL6_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL6_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL6; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL6_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL6; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_CSEL7_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= PWM_ELMR_CSEL7; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ELMR_CSEL7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp = (tmp & PWM_ELMR_CSEL7) >> PWM_ELMR_CSEL7_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ELMR_CSEL7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= ~PWM_ELMR_CSEL7; + tmp |= value << PWM_ELMR_CSEL7_Pos; + ((Pwm *)hw)->PWM_ELMR[index] = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_CSEL7_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~PWM_ELMR_CSEL7; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_CSEL7_bit(const void *const hw, uint8_t index) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= PWM_ELMR_CSEL7; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ELMR_reg(const void *const hw, uint8_t index, hri_pwm_elmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_elmr_reg_t hri_pwm_get_ELMR_reg(const void *const hw, uint8_t index, hri_pwm_elmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ELMR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_ELMR_reg(const void *const hw, uint8_t index, hri_pwm_elmr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ELMR_reg(const void *const hw, uint8_t index, hri_pwm_elmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ELMR_reg(const void *const hw, uint8_t index, hri_pwm_elmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ELMR[index] ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_elmr_reg_t hri_pwm_read_ELMR_reg(const void *const hw, uint8_t index) +{ + return ((Pwm *)hw)->PWM_ELMR[index]; +} + +static inline void hri_pwm_set_SSPR_SPRDM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR |= PWM_SSPR_SPRDM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SSPR_SPRDM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp = (tmp & PWM_SSPR_SPRDM) >> PWM_SSPR_SPRDM_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SSPR_SPRDM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp &= ~PWM_SSPR_SPRDM; + tmp |= value << PWM_SSPR_SPRDM_Pos; + ((Pwm *)hw)->PWM_SSPR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SSPR_SPRDM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR &= ~PWM_SSPR_SPRDM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SSPR_SPRDM_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR ^= PWM_SSPR_SPRDM; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SSPR_SPRD_bf(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR |= PWM_SSPR_SPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_sspr_reg_t hri_pwm_get_SSPR_SPRD_bf(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp = (tmp & PWM_SSPR_SPRD(mask)) >> PWM_SSPR_SPRD_Pos; + return tmp; +} + +static inline void hri_pwm_write_SSPR_SPRD_bf(const void *const hw, hri_pwm_sspr_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp &= ~PWM_SSPR_SPRD_Msk; + tmp |= PWM_SSPR_SPRD(data); + ((Pwm *)hw)->PWM_SSPR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SSPR_SPRD_bf(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR &= ~PWM_SSPR_SPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SSPR_SPRD_bf(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR ^= PWM_SSPR_SPRD(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_sspr_reg_t hri_pwm_read_SSPR_SPRD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp = (tmp & PWM_SSPR_SPRD_Msk) >> PWM_SSPR_SPRD_Pos; + return tmp; +} + +static inline void hri_pwm_set_SSPR_reg(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_sspr_reg_t hri_pwm_get_SSPR_reg(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SSPR; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_SSPR_reg(const void *const hw, hri_pwm_sspr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SSPR_reg(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SSPR_reg(const void *const hw, hri_pwm_sspr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPR ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_sspr_reg_t hri_pwm_read_SSPR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SSPR; +} + +static inline void hri_pwm_set_SMMR_GCEN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR |= PWM_SMMR_GCEN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SMMR_GCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp = (tmp & PWM_SMMR_GCEN0) >> PWM_SMMR_GCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SMMR_GCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp &= ~PWM_SMMR_GCEN0; + tmp |= value << PWM_SMMR_GCEN0_Pos; + ((Pwm *)hw)->PWM_SMMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SMMR_GCEN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR &= ~PWM_SMMR_GCEN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SMMR_GCEN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR ^= PWM_SMMR_GCEN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SMMR_GCEN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR |= PWM_SMMR_GCEN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SMMR_GCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp = (tmp & PWM_SMMR_GCEN1) >> PWM_SMMR_GCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SMMR_GCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp &= ~PWM_SMMR_GCEN1; + tmp |= value << PWM_SMMR_GCEN1_Pos; + ((Pwm *)hw)->PWM_SMMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SMMR_GCEN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR &= ~PWM_SMMR_GCEN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SMMR_GCEN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR ^= PWM_SMMR_GCEN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SMMR_DOWN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR |= PWM_SMMR_DOWN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SMMR_DOWN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp = (tmp & PWM_SMMR_DOWN0) >> PWM_SMMR_DOWN0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SMMR_DOWN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp &= ~PWM_SMMR_DOWN0; + tmp |= value << PWM_SMMR_DOWN0_Pos; + ((Pwm *)hw)->PWM_SMMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SMMR_DOWN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR &= ~PWM_SMMR_DOWN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SMMR_DOWN0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR ^= PWM_SMMR_DOWN0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SMMR_DOWN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR |= PWM_SMMR_DOWN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_SMMR_DOWN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp = (tmp & PWM_SMMR_DOWN1) >> PWM_SMMR_DOWN1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_SMMR_DOWN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp &= ~PWM_SMMR_DOWN1; + tmp |= value << PWM_SMMR_DOWN1_Pos; + ((Pwm *)hw)->PWM_SMMR = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SMMR_DOWN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR &= ~PWM_SMMR_DOWN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SMMR_DOWN1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR ^= PWM_SMMR_DOWN1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_SMMR_reg(const void *const hw, hri_pwm_smmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_smmr_reg_t hri_pwm_get_SMMR_reg(const void *const hw, hri_pwm_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_SMMR; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_SMMR_reg(const void *const hw, hri_pwm_smmr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_SMMR_reg(const void *const hw, hri_pwm_smmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_SMMR_reg(const void *const hw, hri_pwm_smmr_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SMMR ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_smmr_reg_t hri_pwm_read_SMMR_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_SMMR; +} + +static inline void hri_pwm_set_FPV2_FPZH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZH0) >> PWM_FPV2_FPZH0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZH0; + tmp |= value << PWM_FPV2_FPZH0_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZH0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZH0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZH1) >> PWM_FPV2_FPZH1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZH1; + tmp |= value << PWM_FPV2_FPZH1_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZH1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZH1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZH2) >> PWM_FPV2_FPZH2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZH2; + tmp |= value << PWM_FPV2_FPZH2_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZH2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZH2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZH3) >> PWM_FPV2_FPZH3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZH3; + tmp |= value << PWM_FPV2_FPZH3_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZH3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZH3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZL0) >> PWM_FPV2_FPZL0_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZL0; + tmp |= value << PWM_FPV2_FPZL0_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZL0_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZL0; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZL1) >> PWM_FPV2_FPZL1_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZL1; + tmp |= value << PWM_FPV2_FPZL1_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZL1_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZL1; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZL2) >> PWM_FPV2_FPZL2_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZL2; + tmp |= value << PWM_FPV2_FPZL2_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZL2_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZL2; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_FPZL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= PWM_FPV2_FPZL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_FPV2_FPZL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp = (tmp & PWM_FPV2_FPZL3) >> PWM_FPV2_FPZL3_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_FPV2_FPZL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= ~PWM_FPV2_FPZL3; + tmp |= value << PWM_FPV2_FPZL3_Pos; + ((Pwm *)hw)->PWM_FPV2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_FPZL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~PWM_FPV2_FPZL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_FPZL3_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= PWM_FPV2_FPZL3; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_FPV2_reg(const void *const hw, hri_pwm_fpv2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpv2_reg_t hri_pwm_get_FPV2_reg(const void *const hw, hri_pwm_fpv2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_FPV2; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_FPV2_reg(const void *const hw, hri_pwm_fpv2_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_FPV2_reg(const void *const hw, hri_pwm_fpv2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_FPV2_reg(const void *const hw, hri_pwm_fpv2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FPV2 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_fpv2_reg_t hri_pwm_read_FPV2_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_FPV2; +} + +static inline void hri_pwm_set_ETRG1_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG1_TRGEDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_TRGEDGE) >> PWM_ETRG1_TRGEDGE_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG1_TRGEDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_TRGEDGE; + tmp |= value << PWM_ETRG1_TRGEDGE_Pos; + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG1_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG1_TRGFILT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_TRGFILT) >> PWM_ETRG1_TRGFILT_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG1_TRGFILT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_TRGFILT; + tmp |= value << PWM_ETRG1_TRGFILT_Pos; + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG1_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG1_TRGSRC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_TRGSRC) >> PWM_ETRG1_TRGSRC_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG1_TRGSRC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_TRGSRC; + tmp |= value << PWM_ETRG1_TRGSRC_Pos; + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG1_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG1_RFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_RFEN) >> PWM_ETRG1_RFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG1_RFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_RFEN; + tmp |= value << PWM_ETRG1_RFEN_Pos; + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG1_MAXCNT_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_get_ETRG1_MAXCNT_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_MAXCNT(mask)) >> PWM_ETRG1_MAXCNT_Pos; + return tmp; +} + +static inline void hri_pwm_write_ETRG1_MAXCNT_bf(const void *const hw, hri_pwm_etrg1_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_MAXCNT_Msk; + tmp |= PWM_ETRG1_MAXCNT(data); + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_MAXCNT_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_MAXCNT_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_read_ETRG1_MAXCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_MAXCNT_Msk) >> PWM_ETRG1_MAXCNT_Pos; + return tmp; +} + +static inline void hri_pwm_set_ETRG1_TRGMODE_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= PWM_ETRG1_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_get_ETRG1_TRGMODE_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_TRGMODE(mask)) >> PWM_ETRG1_TRGMODE_Pos; + return tmp; +} + +static inline void hri_pwm_write_ETRG1_TRGMODE_bf(const void *const hw, hri_pwm_etrg1_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= ~PWM_ETRG1_TRGMODE_Msk; + tmp |= PWM_ETRG1_TRGMODE(data); + ((Pwm *)hw)->PWM_ETRG1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_TRGMODE_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~PWM_ETRG1_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_TRGMODE_bf(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= PWM_ETRG1_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_read_ETRG1_TRGMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp = (tmp & PWM_ETRG1_TRGMODE_Msk) >> PWM_ETRG1_TRGMODE_Pos; + return tmp; +} + +static inline void hri_pwm_set_ETRG1_reg(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_get_ETRG1_reg(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG1; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_ETRG1_reg(const void *const hw, hri_pwm_etrg1_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG1_reg(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG1_reg(const void *const hw, hri_pwm_etrg1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG1 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg1_reg_t hri_pwm_read_ETRG1_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_ETRG1; +} + +static inline void hri_pwm_set_LEBR1_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= PWM_LEBR1_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR1_PWMLFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_PWMLFEN) >> PWM_LEBR1_PWMLFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR1_PWMLFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= ~PWM_LEBR1_PWMLFEN; + tmp |= value << PWM_LEBR1_PWMLFEN_Pos; + ((Pwm *)hw)->PWM_LEBR1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~PWM_LEBR1_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= PWM_LEBR1_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR1_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= PWM_LEBR1_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR1_PWMLREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_PWMLREN) >> PWM_LEBR1_PWMLREN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR1_PWMLREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= ~PWM_LEBR1_PWMLREN; + tmp |= value << PWM_LEBR1_PWMLREN_Pos; + ((Pwm *)hw)->PWM_LEBR1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~PWM_LEBR1_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= PWM_LEBR1_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR1_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= PWM_LEBR1_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR1_PWMHFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_PWMHFEN) >> PWM_LEBR1_PWMHFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR1_PWMHFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= ~PWM_LEBR1_PWMHFEN; + tmp |= value << PWM_LEBR1_PWMHFEN_Pos; + ((Pwm *)hw)->PWM_LEBR1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~PWM_LEBR1_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= PWM_LEBR1_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR1_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= PWM_LEBR1_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR1_PWMHREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_PWMHREN) >> PWM_LEBR1_PWMHREN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR1_PWMHREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= ~PWM_LEBR1_PWMHREN; + tmp |= value << PWM_LEBR1_PWMHREN_Pos; + ((Pwm *)hw)->PWM_LEBR1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~PWM_LEBR1_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= PWM_LEBR1_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR1_LEBDELAY_bf(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= PWM_LEBR1_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr1_reg_t hri_pwm_get_LEBR1_LEBDELAY_bf(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_LEBDELAY(mask)) >> PWM_LEBR1_LEBDELAY_Pos; + return tmp; +} + +static inline void hri_pwm_write_LEBR1_LEBDELAY_bf(const void *const hw, hri_pwm_lebr1_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= ~PWM_LEBR1_LEBDELAY_Msk; + tmp |= PWM_LEBR1_LEBDELAY(data); + ((Pwm *)hw)->PWM_LEBR1 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_LEBDELAY_bf(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~PWM_LEBR1_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_LEBDELAY_bf(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= PWM_LEBR1_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr1_reg_t hri_pwm_read_LEBR1_LEBDELAY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp = (tmp & PWM_LEBR1_LEBDELAY_Msk) >> PWM_LEBR1_LEBDELAY_Pos; + return tmp; +} + +static inline void hri_pwm_set_LEBR1_reg(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr1_reg_t hri_pwm_get_LEBR1_reg(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR1; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_LEBR1_reg(const void *const hw, hri_pwm_lebr1_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR1_reg(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR1_reg(const void *const hw, hri_pwm_lebr1_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR1 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr1_reg_t hri_pwm_read_LEBR1_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_LEBR1; +} + +static inline void hri_pwm_set_ETRG2_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG2_TRGEDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_TRGEDGE) >> PWM_ETRG2_TRGEDGE_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG2_TRGEDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_TRGEDGE; + tmp |= value << PWM_ETRG2_TRGEDGE_Pos; + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_TRGEDGE_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_TRGEDGE; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG2_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG2_TRGFILT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_TRGFILT) >> PWM_ETRG2_TRGFILT_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG2_TRGFILT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_TRGFILT; + tmp |= value << PWM_ETRG2_TRGFILT_Pos; + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_TRGFILT_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_TRGFILT; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG2_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG2_TRGSRC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_TRGSRC) >> PWM_ETRG2_TRGSRC_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG2_TRGSRC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_TRGSRC; + tmp |= value << PWM_ETRG2_TRGSRC_Pos; + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_TRGSRC_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_TRGSRC; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG2_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_ETRG2_RFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_RFEN) >> PWM_ETRG2_RFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_ETRG2_RFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_RFEN; + tmp |= value << PWM_ETRG2_RFEN_Pos; + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_RFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_RFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_ETRG2_MAXCNT_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_get_ETRG2_MAXCNT_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_MAXCNT(mask)) >> PWM_ETRG2_MAXCNT_Pos; + return tmp; +} + +static inline void hri_pwm_write_ETRG2_MAXCNT_bf(const void *const hw, hri_pwm_etrg2_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_MAXCNT_Msk; + tmp |= PWM_ETRG2_MAXCNT(data); + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_MAXCNT_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_MAXCNT_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_MAXCNT(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_read_ETRG2_MAXCNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_MAXCNT_Msk) >> PWM_ETRG2_MAXCNT_Pos; + return tmp; +} + +static inline void hri_pwm_set_ETRG2_TRGMODE_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= PWM_ETRG2_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_get_ETRG2_TRGMODE_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_TRGMODE(mask)) >> PWM_ETRG2_TRGMODE_Pos; + return tmp; +} + +static inline void hri_pwm_write_ETRG2_TRGMODE_bf(const void *const hw, hri_pwm_etrg2_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= ~PWM_ETRG2_TRGMODE_Msk; + tmp |= PWM_ETRG2_TRGMODE(data); + ((Pwm *)hw)->PWM_ETRG2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_TRGMODE_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~PWM_ETRG2_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_TRGMODE_bf(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= PWM_ETRG2_TRGMODE(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_read_ETRG2_TRGMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp = (tmp & PWM_ETRG2_TRGMODE_Msk) >> PWM_ETRG2_TRGMODE_Pos; + return tmp; +} + +static inline void hri_pwm_set_ETRG2_reg(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_get_ETRG2_reg(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_ETRG2; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_ETRG2_reg(const void *const hw, hri_pwm_etrg2_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_ETRG2_reg(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_ETRG2_reg(const void *const hw, hri_pwm_etrg2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ETRG2 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_etrg2_reg_t hri_pwm_read_ETRG2_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_ETRG2; +} + +static inline void hri_pwm_set_LEBR2_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= PWM_LEBR2_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR2_PWMLFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_PWMLFEN) >> PWM_LEBR2_PWMLFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR2_PWMLFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= ~PWM_LEBR2_PWMLFEN; + tmp |= value << PWM_LEBR2_PWMLFEN_Pos; + ((Pwm *)hw)->PWM_LEBR2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~PWM_LEBR2_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_PWMLFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= PWM_LEBR2_PWMLFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR2_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= PWM_LEBR2_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR2_PWMLREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_PWMLREN) >> PWM_LEBR2_PWMLREN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR2_PWMLREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= ~PWM_LEBR2_PWMLREN; + tmp |= value << PWM_LEBR2_PWMLREN_Pos; + ((Pwm *)hw)->PWM_LEBR2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~PWM_LEBR2_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_PWMLREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= PWM_LEBR2_PWMLREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR2_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= PWM_LEBR2_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR2_PWMHFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_PWMHFEN) >> PWM_LEBR2_PWMHFEN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR2_PWMHFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= ~PWM_LEBR2_PWMHFEN; + tmp |= value << PWM_LEBR2_PWMHFEN_Pos; + ((Pwm *)hw)->PWM_LEBR2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~PWM_LEBR2_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_PWMHFEN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= PWM_LEBR2_PWMHFEN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR2_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= PWM_LEBR2_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pwm_get_LEBR2_PWMHREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_PWMHREN) >> PWM_LEBR2_PWMHREN_Pos; + return (bool)tmp; +} + +static inline void hri_pwm_write_LEBR2_PWMHREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= ~PWM_LEBR2_PWMHREN; + tmp |= value << PWM_LEBR2_PWMHREN_Pos; + ((Pwm *)hw)->PWM_LEBR2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~PWM_LEBR2_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_PWMHREN_bit(const void *const hw) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= PWM_LEBR2_PWMHREN; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_set_LEBR2_LEBDELAY_bf(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= PWM_LEBR2_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr2_reg_t hri_pwm_get_LEBR2_LEBDELAY_bf(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_LEBDELAY(mask)) >> PWM_LEBR2_LEBDELAY_Pos; + return tmp; +} + +static inline void hri_pwm_write_LEBR2_LEBDELAY_bf(const void *const hw, hri_pwm_lebr2_reg_t data) +{ + uint32_t tmp; + PWM_CRITICAL_SECTION_ENTER(); + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= ~PWM_LEBR2_LEBDELAY_Msk; + tmp |= PWM_LEBR2_LEBDELAY(data); + ((Pwm *)hw)->PWM_LEBR2 = tmp; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_LEBDELAY_bf(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~PWM_LEBR2_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_LEBDELAY_bf(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= PWM_LEBR2_LEBDELAY(mask); + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr2_reg_t hri_pwm_read_LEBR2_LEBDELAY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp = (tmp & PWM_LEBR2_LEBDELAY_Msk) >> PWM_LEBR2_LEBDELAY_Pos; + return tmp; +} + +static inline void hri_pwm_set_LEBR2_reg(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 |= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr2_reg_t hri_pwm_get_LEBR2_reg(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pwm *)hw)->PWM_LEBR2; + tmp &= mask; + return tmp; +} + +static inline void hri_pwm_write_LEBR2_reg(const void *const hw, hri_pwm_lebr2_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_clear_LEBR2_reg(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 &= ~mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_toggle_LEBR2_reg(const void *const hw, hri_pwm_lebr2_reg_t mask) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_LEBR2 ^= mask; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pwm_lebr2_reg_t hri_pwm_read_LEBR2_reg(const void *const hw) +{ + return ((Pwm *)hw)->PWM_LEBR2; +} + +static inline void hri_pwm_write_ENA_reg(const void *const hw, hri_pwm_ena_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_ENA = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_DIS_reg(const void *const hw, hri_pwm_dis_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_DIS = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_DMAR_reg(const void *const hw, hri_pwm_dmar_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_DMAR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_SCUPUPD_reg(const void *const hw, hri_pwm_scupupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SCUPUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_OSS_reg(const void *const hw, hri_pwm_oss_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OSS = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_OSC_reg(const void *const hw, hri_pwm_osc_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OSC = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_OSSUPD_reg(const void *const hw, hri_pwm_ossupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OSSUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_OSCUPD_reg(const void *const hw, hri_pwm_oscupd_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_OSCUPD = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_FCR_reg(const void *const hw, hri_pwm_fcr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_FCR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_SSPUP_reg(const void *const hw, hri_pwm_sspup_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_SSPUP = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_WPCR_reg(const void *const hw, hri_pwm_wpcr_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_WPCR = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CMUPD0_reg(const void *const hw, hri_pwm_cmupd0_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CMUPD0 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CMUPD1_reg(const void *const hw, hri_pwm_cmupd1_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CMUPD1 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CMUPD2_reg(const void *const hw, hri_pwm_cmupd2_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CMUPD2 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pwm_write_CMUPD3_reg(const void *const hw, hri_pwm_cmupd3_reg_t data) +{ + PWM_CRITICAL_SECTION_ENTER(); + ((Pwm *)hw)->PWM_CMUPD3 = data; + PWM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PWM_E70B_H_INCLUDED */ +#endif /* _SAME70_PWM_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_qspi_e70b.h b/bsp/microchip/same70/bsp/hri/hri_qspi_e70b.h new file mode 100644 index 0000000000..bc9595ae99 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_qspi_e70b.h @@ -0,0 +1,1913 @@ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_E70B_H_INCLUDED_ +#define _HRI_QSPI_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_cr_reg_t; +typedef uint32_t hri_qspi_iar_reg_t; +typedef uint32_t hri_qspi_icr_reg_t; +typedef uint32_t hri_qspi_ifr_reg_t; +typedef uint32_t hri_qspi_imr_reg_t; +typedef uint32_t hri_qspi_mr_reg_t; +typedef uint32_t hri_qspi_rdr_reg_t; +typedef uint32_t hri_qspi_scr_reg_t; +typedef uint32_t hri_qspi_skr_reg_t; +typedef uint32_t hri_qspi_smr_reg_t; +typedef uint32_t hri_qspi_sr_reg_t; +typedef uint32_t hri_qspi_tdr_reg_t; +typedef uint32_t hri_qspi_wpmr_reg_t; +typedef uint32_t hri_qspi_wpsr_reg_t; + +static inline void hri_qspi_set_IMR_RDRF_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_RDRF; +} + +static inline bool hri_qspi_get_IMR_RDRF_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_RDRF) >> QSPI_IMR_RDRF_Pos; +} + +static inline void hri_qspi_write_IMR_RDRF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_RDRF; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_RDRF; + } +} + +static inline void hri_qspi_clear_IMR_RDRF_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_RDRF; +} + +static inline void hri_qspi_set_IMR_TDRE_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_TDRE; +} + +static inline bool hri_qspi_get_IMR_TDRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_TDRE) >> QSPI_IMR_TDRE_Pos; +} + +static inline void hri_qspi_write_IMR_TDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_TDRE; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_TDRE; + } +} + +static inline void hri_qspi_clear_IMR_TDRE_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_TDRE; +} + +static inline void hri_qspi_set_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_TXEMPTY; +} + +static inline bool hri_qspi_get_IMR_TXEMPTY_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_TXEMPTY) >> QSPI_IMR_TXEMPTY_Pos; +} + +static inline void hri_qspi_write_IMR_TXEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_TXEMPTY; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_TXEMPTY; + } +} + +static inline void hri_qspi_clear_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_TXEMPTY; +} + +static inline void hri_qspi_set_IMR_OVRES_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_OVRES; +} + +static inline bool hri_qspi_get_IMR_OVRES_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_OVRES) >> QSPI_IMR_OVRES_Pos; +} + +static inline void hri_qspi_write_IMR_OVRES_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_OVRES; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_OVRES; + } +} + +static inline void hri_qspi_clear_IMR_OVRES_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_OVRES; +} + +static inline void hri_qspi_set_IMR_CSR_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_CSR; +} + +static inline bool hri_qspi_get_IMR_CSR_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_CSR) >> QSPI_IMR_CSR_Pos; +} + +static inline void hri_qspi_write_IMR_CSR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_CSR; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_CSR; + } +} + +static inline void hri_qspi_clear_IMR_CSR_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_CSR; +} + +static inline void hri_qspi_set_IMR_CSS_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_CSS; +} + +static inline bool hri_qspi_get_IMR_CSS_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_CSS) >> QSPI_IMR_CSS_Pos; +} + +static inline void hri_qspi_write_IMR_CSS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_CSS; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_CSS; + } +} + +static inline void hri_qspi_clear_IMR_CSS_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_CSS; +} + +static inline void hri_qspi_set_IMR_INSTRE_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_INSTRE; +} + +static inline bool hri_qspi_get_IMR_INSTRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_IMR & QSPI_IMR_INSTRE) >> QSPI_IMR_INSTRE_Pos; +} + +static inline void hri_qspi_write_IMR_INSTRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_INSTRE; + } else { + ((Qspi *)hw)->QSPI_IER = QSPI_IMR_INSTRE; + } +} + +static inline void hri_qspi_clear_IMR_INSTRE_bit(const void *const hw) +{ + ((Qspi *)hw)->QSPI_IDR = QSPI_IMR_INSTRE; +} + +static inline void hri_qspi_set_IMR_reg(const void *const hw, hri_qspi_imr_reg_t mask) +{ + ((Qspi *)hw)->QSPI_IER = mask; +} + +static inline hri_qspi_imr_reg_t hri_qspi_get_IMR_reg(const void *const hw, hri_qspi_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_imr_reg_t hri_qspi_read_IMR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_IMR; +} + +static inline void hri_qspi_write_IMR_reg(const void *const hw, hri_qspi_imr_reg_t data) +{ + ((Qspi *)hw)->QSPI_IER = data; + ((Qspi *)hw)->QSPI_IDR = ~data; +} + +static inline void hri_qspi_clear_IMR_reg(const void *const hw, hri_qspi_imr_reg_t mask) +{ + ((Qspi *)hw)->QSPI_IDR = mask; +} + +static inline hri_qspi_rdr_reg_t hri_qspi_get_RDR_RD_bf(const void *const hw, hri_qspi_rdr_reg_t mask) +{ + return (((Qspi *)hw)->QSPI_RDR & QSPI_RDR_RD(mask)) >> QSPI_RDR_RD_Pos; +} + +static inline hri_qspi_rdr_reg_t hri_qspi_read_RDR_RD_bf(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_RDR & QSPI_RDR_RD_Msk) >> QSPI_RDR_RD_Pos; +} + +static inline hri_qspi_rdr_reg_t hri_qspi_get_RDR_reg(const void *const hw, hri_qspi_rdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_RDR; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rdr_reg_t hri_qspi_read_RDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_RDR; +} + +static inline bool hri_qspi_get_SR_RDRF_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_RDRF) > 0; +} + +static inline bool hri_qspi_get_SR_TDRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_TDRE) > 0; +} + +static inline bool hri_qspi_get_SR_TXEMPTY_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_TXEMPTY) > 0; +} + +static inline bool hri_qspi_get_SR_OVRES_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_OVRES) > 0; +} + +static inline bool hri_qspi_get_SR_CSR_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_CSR) > 0; +} + +static inline bool hri_qspi_get_SR_CSS_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_CSS) > 0; +} + +static inline bool hri_qspi_get_SR_INSTRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_INSTRE) > 0; +} + +static inline bool hri_qspi_get_SR_QSPIENS_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_SR & QSPI_SR_QSPIENS) > 0; +} + +static inline hri_qspi_sr_reg_t hri_qspi_get_SR_reg(const void *const hw, hri_qspi_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SR; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_sr_reg_t hri_qspi_read_SR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_SR; +} + +static inline bool hri_qspi_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_WPSR & QSPI_WPSR_WPVS) > 0; +} + +static inline hri_qspi_wpsr_reg_t hri_qspi_get_WPSR_WPVSRC_bf(const void *const hw, hri_qspi_wpsr_reg_t mask) +{ + return (((Qspi *)hw)->QSPI_WPSR & QSPI_WPSR_WPVSRC(mask)) >> QSPI_WPSR_WPVSRC_Pos; +} + +static inline hri_qspi_wpsr_reg_t hri_qspi_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Qspi *)hw)->QSPI_WPSR & QSPI_WPSR_WPVSRC_Msk) >> QSPI_WPSR_WPVSRC_Pos; +} + +static inline hri_qspi_wpsr_reg_t hri_qspi_get_WPSR_reg(const void *const hw, hri_qspi_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_wpsr_reg_t hri_qspi_read_WPSR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_WPSR; +} + +static inline void hri_qspi_set_MR_SMM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_SMM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_MR_SMM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_SMM) >> QSPI_MR_SMM_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_MR_SMM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_SMM; + tmp |= value << QSPI_MR_SMM_Pos; + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_SMM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_SMM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_SMM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_SMM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_MR_LLB_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_LLB; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_MR_LLB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_LLB) >> QSPI_MR_LLB_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_MR_LLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_LLB; + tmp |= value << QSPI_MR_LLB_Pos; + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_LLB_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_LLB; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_LLB_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_LLB; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_MR_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_MR_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_WDRBT) >> QSPI_MR_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_MR_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_WDRBT; + tmp |= value << QSPI_MR_WDRBT_Pos; + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_MR_CSMODE_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_get_MR_CSMODE_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_CSMODE(mask)) >> QSPI_MR_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_MR_CSMODE_bf(const void *const hw, hri_qspi_mr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_CSMODE_Msk; + tmp |= QSPI_MR_CSMODE(data); + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_CSMODE_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_CSMODE_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_read_MR_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_CSMODE_Msk) >> QSPI_MR_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_MR_NBBITS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_NBBITS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_get_MR_NBBITS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_NBBITS(mask)) >> QSPI_MR_NBBITS_Pos; + return tmp; +} + +static inline void hri_qspi_write_MR_NBBITS_bf(const void *const hw, hri_qspi_mr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_NBBITS_Msk; + tmp |= QSPI_MR_NBBITS(data); + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_NBBITS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_NBBITS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_NBBITS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_NBBITS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_read_MR_NBBITS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_NBBITS_Msk) >> QSPI_MR_NBBITS_Pos; + return tmp; +} + +static inline void hri_qspi_set_MR_DLYBCT_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_get_MR_DLYBCT_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_DLYBCT(mask)) >> QSPI_MR_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_MR_DLYBCT_bf(const void *const hw, hri_qspi_mr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_DLYBCT_Msk; + tmp |= QSPI_MR_DLYBCT(data); + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_DLYBCT_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_DLYBCT_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_read_MR_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_DLYBCT_Msk) >> QSPI_MR_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_MR_DLYCS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= QSPI_MR_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_get_MR_DLYCS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_DLYCS(mask)) >> QSPI_MR_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_MR_DLYCS_bf(const void *const hw, hri_qspi_mr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= ~QSPI_MR_DLYCS_Msk; + tmp |= QSPI_MR_DLYCS(data); + ((Qspi *)hw)->QSPI_MR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_DLYCS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~QSPI_MR_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_DLYCS_bf(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= QSPI_MR_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_read_MR_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp = (tmp & QSPI_MR_DLYCS_Msk) >> QSPI_MR_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_MR_reg(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_get_MR_reg(const void *const hw, hri_qspi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_MR_reg(const void *const hw, hri_qspi_mr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_MR_reg(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_MR_reg(const void *const hw, hri_qspi_mr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_MR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_mr_reg_t hri_qspi_read_MR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_MR; +} + +static inline void hri_qspi_set_SCR_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR |= QSPI_SCR_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCR_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_CPOL) >> QSPI_SCR_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCR_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp &= ~QSPI_SCR_CPOL; + tmp |= value << QSPI_SCR_CPOL_Pos; + ((Qspi *)hw)->QSPI_SCR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCR_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR &= ~QSPI_SCR_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCR_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR ^= QSPI_SCR_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCR_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR |= QSPI_SCR_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCR_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_CPHA) >> QSPI_SCR_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCR_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp &= ~QSPI_SCR_CPHA; + tmp |= value << QSPI_SCR_CPHA_Pos; + ((Qspi *)hw)->QSPI_SCR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCR_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR &= ~QSPI_SCR_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCR_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR ^= QSPI_SCR_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCR_SCBR_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR |= QSPI_SCR_SCBR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_get_SCR_SCBR_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_SCBR(mask)) >> QSPI_SCR_SCBR_Pos; + return tmp; +} + +static inline void hri_qspi_write_SCR_SCBR_bf(const void *const hw, hri_qspi_scr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp &= ~QSPI_SCR_SCBR_Msk; + tmp |= QSPI_SCR_SCBR(data); + ((Qspi *)hw)->QSPI_SCR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCR_SCBR_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR &= ~QSPI_SCR_SCBR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCR_SCBR_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR ^= QSPI_SCR_SCBR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_read_SCR_SCBR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_SCBR_Msk) >> QSPI_SCR_SCBR_Pos; + return tmp; +} + +static inline void hri_qspi_set_SCR_DLYBS_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR |= QSPI_SCR_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_get_SCR_DLYBS_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_DLYBS(mask)) >> QSPI_SCR_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_SCR_DLYBS_bf(const void *const hw, hri_qspi_scr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp &= ~QSPI_SCR_DLYBS_Msk; + tmp |= QSPI_SCR_DLYBS(data); + ((Qspi *)hw)->QSPI_SCR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCR_DLYBS_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR &= ~QSPI_SCR_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCR_DLYBS_bf(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR ^= QSPI_SCR_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_read_SCR_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp = (tmp & QSPI_SCR_DLYBS_Msk) >> QSPI_SCR_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_SCR_reg(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_get_SCR_reg(const void *const hw, hri_qspi_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SCR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCR_reg(const void *const hw, hri_qspi_scr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCR_reg(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCR_reg(const void *const hw, hri_qspi_scr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SCR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scr_reg_t hri_qspi_read_SCR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_SCR; +} + +static inline void hri_qspi_set_IAR_ADDR_bf(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR |= QSPI_IAR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_iar_reg_t hri_qspi_get_IAR_ADDR_bf(const void *const hw, hri_qspi_iar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IAR; + tmp = (tmp & QSPI_IAR_ADDR(mask)) >> QSPI_IAR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_IAR_ADDR_bf(const void *const hw, hri_qspi_iar_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IAR; + tmp &= ~QSPI_IAR_ADDR_Msk; + tmp |= QSPI_IAR_ADDR(data); + ((Qspi *)hw)->QSPI_IAR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IAR_ADDR_bf(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR &= ~QSPI_IAR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IAR_ADDR_bf(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR ^= QSPI_IAR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_iar_reg_t hri_qspi_read_IAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IAR; + tmp = (tmp & QSPI_IAR_ADDR_Msk) >> QSPI_IAR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_IAR_reg(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_iar_reg_t hri_qspi_get_IAR_reg(const void *const hw, hri_qspi_iar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IAR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_IAR_reg(const void *const hw, hri_qspi_iar_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IAR_reg(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IAR_reg(const void *const hw, hri_qspi_iar_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IAR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_iar_reg_t hri_qspi_read_IAR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_IAR; +} + +static inline void hri_qspi_set_ICR_INST_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR |= QSPI_ICR_INST(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_get_ICR_INST_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp = (tmp & QSPI_ICR_INST(mask)) >> QSPI_ICR_INST_Pos; + return tmp; +} + +static inline void hri_qspi_write_ICR_INST_bf(const void *const hw, hri_qspi_icr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp &= ~QSPI_ICR_INST_Msk; + tmp |= QSPI_ICR_INST(data); + ((Qspi *)hw)->QSPI_ICR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_ICR_INST_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR &= ~QSPI_ICR_INST(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_ICR_INST_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR ^= QSPI_ICR_INST(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_read_ICR_INST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp = (tmp & QSPI_ICR_INST_Msk) >> QSPI_ICR_INST_Pos; + return tmp; +} + +static inline void hri_qspi_set_ICR_OPT_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR |= QSPI_ICR_OPT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_get_ICR_OPT_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp = (tmp & QSPI_ICR_OPT(mask)) >> QSPI_ICR_OPT_Pos; + return tmp; +} + +static inline void hri_qspi_write_ICR_OPT_bf(const void *const hw, hri_qspi_icr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp &= ~QSPI_ICR_OPT_Msk; + tmp |= QSPI_ICR_OPT(data); + ((Qspi *)hw)->QSPI_ICR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_ICR_OPT_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR &= ~QSPI_ICR_OPT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_ICR_OPT_bf(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR ^= QSPI_ICR_OPT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_read_ICR_OPT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp = (tmp & QSPI_ICR_OPT_Msk) >> QSPI_ICR_OPT_Pos; + return tmp; +} + +static inline void hri_qspi_set_ICR_reg(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_get_ICR_reg(const void *const hw, hri_qspi_icr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_ICR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_ICR_reg(const void *const hw, hri_qspi_icr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_ICR_reg(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_ICR_reg(const void *const hw, hri_qspi_icr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_ICR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_icr_reg_t hri_qspi_read_ICR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_ICR; +} + +static inline void hri_qspi_set_IFR_INSTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_INSTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_INSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_INSTEN) >> QSPI_IFR_INSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_INSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_INSTEN; + tmp |= value << QSPI_IFR_INSTEN_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_INSTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_INSTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_INSTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_INSTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_ADDREN) >> QSPI_IFR_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_ADDREN; + tmp |= value << QSPI_IFR_ADDREN_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_OPTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_OPTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_OPTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_OPTEN) >> QSPI_IFR_OPTEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_OPTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_OPTEN; + tmp |= value << QSPI_IFR_OPTEN_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_OPTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_OPTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_OPTEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_OPTEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_DATAEN) >> QSPI_IFR_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_DATAEN; + tmp |= value << QSPI_IFR_DATAEN_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_ADDRL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_ADDRL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_ADDRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_ADDRL) >> QSPI_IFR_ADDRL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_ADDRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_ADDRL; + tmp |= value << QSPI_IFR_ADDRL_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_ADDRL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_ADDRL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_ADDRL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_ADDRL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_CRM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_CRM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_IFR_CRM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_CRM) >> QSPI_IFR_CRM_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_IFR_CRM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_CRM; + tmp |= value << QSPI_IFR_CRM_Pos; + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_CRM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_CRM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_CRM_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_CRM; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_IFR_WIDTH_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_get_IFR_WIDTH_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_WIDTH(mask)) >> QSPI_IFR_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_IFR_WIDTH_bf(const void *const hw, hri_qspi_ifr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_WIDTH_Msk; + tmp |= QSPI_IFR_WIDTH(data); + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_WIDTH_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_WIDTH_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_read_IFR_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_WIDTH_Msk) >> QSPI_IFR_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_IFR_OPTL_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_OPTL(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_get_IFR_OPTL_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_OPTL(mask)) >> QSPI_IFR_OPTL_Pos; + return tmp; +} + +static inline void hri_qspi_write_IFR_OPTL_bf(const void *const hw, hri_qspi_ifr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_OPTL_Msk; + tmp |= QSPI_IFR_OPTL(data); + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_OPTL_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_OPTL(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_OPTL_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_OPTL(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_read_IFR_OPTL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_OPTL_Msk) >> QSPI_IFR_OPTL_Pos; + return tmp; +} + +static inline void hri_qspi_set_IFR_TFRTYP_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_TFRTYP(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_get_IFR_TFRTYP_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_TFRTYP(mask)) >> QSPI_IFR_TFRTYP_Pos; + return tmp; +} + +static inline void hri_qspi_write_IFR_TFRTYP_bf(const void *const hw, hri_qspi_ifr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_TFRTYP_Msk; + tmp |= QSPI_IFR_TFRTYP(data); + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_TFRTYP_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_TFRTYP(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_TFRTYP_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_TFRTYP(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_read_IFR_TFRTYP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_TFRTYP_Msk) >> QSPI_IFR_TFRTYP_Pos; + return tmp; +} + +static inline void hri_qspi_set_IFR_NBDUM_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= QSPI_IFR_NBDUM(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_get_IFR_NBDUM_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_NBDUM(mask)) >> QSPI_IFR_NBDUM_Pos; + return tmp; +} + +static inline void hri_qspi_write_IFR_NBDUM_bf(const void *const hw, hri_qspi_ifr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= ~QSPI_IFR_NBDUM_Msk; + tmp |= QSPI_IFR_NBDUM(data); + ((Qspi *)hw)->QSPI_IFR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_NBDUM_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~QSPI_IFR_NBDUM(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_NBDUM_bf(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= QSPI_IFR_NBDUM(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_read_IFR_NBDUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp = (tmp & QSPI_IFR_NBDUM_Msk) >> QSPI_IFR_NBDUM_Pos; + return tmp; +} + +static inline void hri_qspi_set_IFR_reg(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_get_IFR_reg(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_IFR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_IFR_reg(const void *const hw, hri_qspi_ifr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_IFR_reg(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_IFR_reg(const void *const hw, hri_qspi_ifr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_IFR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ifr_reg_t hri_qspi_read_IFR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_IFR; +} + +static inline void hri_qspi_set_SMR_SCREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR |= QSPI_SMR_SCREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SMR_SCREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SMR; + tmp = (tmp & QSPI_SMR_SCREN) >> QSPI_SMR_SCREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SMR_SCREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SMR; + tmp &= ~QSPI_SMR_SCREN; + tmp |= value << QSPI_SMR_SCREN_Pos; + ((Qspi *)hw)->QSPI_SMR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SMR_SCREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR &= ~QSPI_SMR_SCREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SMR_SCREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR ^= QSPI_SMR_SCREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SMR_RVDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR |= QSPI_SMR_RVDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SMR_RVDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SMR; + tmp = (tmp & QSPI_SMR_RVDIS) >> QSPI_SMR_RVDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SMR_RVDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_SMR; + tmp &= ~QSPI_SMR_RVDIS; + tmp |= value << QSPI_SMR_RVDIS_Pos; + ((Qspi *)hw)->QSPI_SMR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SMR_RVDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR &= ~QSPI_SMR_RVDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SMR_RVDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR ^= QSPI_SMR_RVDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SMR_reg(const void *const hw, hri_qspi_smr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_smr_reg_t hri_qspi_get_SMR_reg(const void *const hw, hri_qspi_smr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_SMR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SMR_reg(const void *const hw, hri_qspi_smr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SMR_reg(const void *const hw, hri_qspi_smr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SMR_reg(const void *const hw, hri_qspi_smr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SMR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_smr_reg_t hri_qspi_read_SMR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_SMR; +} + +static inline void hri_qspi_set_WPMR_WPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR |= QSPI_WPMR_WPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp = (tmp & QSPI_WPMR_WPEN) >> QSPI_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp &= ~QSPI_WPMR_WPEN; + tmp |= value << QSPI_WPMR_WPEN_Pos; + ((Qspi *)hw)->QSPI_WPMR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_WPMR_WPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR &= ~QSPI_WPMR_WPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_WPMR_WPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR ^= QSPI_WPMR_WPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_WPMR_WPKEY_bf(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR |= QSPI_WPMR_WPKEY(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_wpmr_reg_t hri_qspi_get_WPMR_WPKEY_bf(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp = (tmp & QSPI_WPMR_WPKEY(mask)) >> QSPI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_qspi_write_WPMR_WPKEY_bf(const void *const hw, hri_qspi_wpmr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp &= ~QSPI_WPMR_WPKEY_Msk; + tmp |= QSPI_WPMR_WPKEY(data); + ((Qspi *)hw)->QSPI_WPMR = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_WPMR_WPKEY_bf(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR &= ~QSPI_WPMR_WPKEY(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_WPMR_WPKEY_bf(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR ^= QSPI_WPMR_WPKEY(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_wpmr_reg_t hri_qspi_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp = (tmp & QSPI_WPMR_WPKEY_Msk) >> QSPI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_qspi_set_WPMR_reg(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_wpmr_reg_t hri_qspi_get_WPMR_reg(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->QSPI_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_WPMR_reg(const void *const hw, hri_qspi_wpmr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_WPMR_reg(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_WPMR_reg(const void *const hw, hri_qspi_wpmr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_WPMR ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_wpmr_reg_t hri_qspi_read_WPMR_reg(const void *const hw) +{ + return ((Qspi *)hw)->QSPI_WPMR; +} + +static inline void hri_qspi_write_CR_reg(const void *const hw, hri_qspi_cr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_CR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_TDR_reg(const void *const hw, hri_qspi_tdr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_TDR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SKR_reg(const void *const hw, hri_qspi_skr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->QSPI_SKR = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_E70B_H_INCLUDED */ +#endif /* _SAME70_QSPI_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_rstc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_rstc_e70b.h new file mode 100644 index 0000000000..f7947f39cb --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_rstc_e70b.h @@ -0,0 +1,323 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_E70B_H_INCLUDED_ +#define _HRI_RSTC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_rstc_cr_reg_t; +typedef uint32_t hri_rstc_mr_reg_t; +typedef uint32_t hri_rstc_sr_reg_t; + +static inline bool hri_rstc_get_SR_URSTS_bit(const void *const hw) +{ + return (((Rstc *)hw)->RSTC_SR & RSTC_SR_URSTS) > 0; +} + +static inline bool hri_rstc_get_SR_NRSTL_bit(const void *const hw) +{ + return (((Rstc *)hw)->RSTC_SR & RSTC_SR_NRSTL) > 0; +} + +static inline bool hri_rstc_get_SR_SRCMP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RSTC_SR & RSTC_SR_SRCMP) > 0; +} + +static inline hri_rstc_sr_reg_t hri_rstc_get_SR_RSTTYP_bf(const void *const hw, hri_rstc_sr_reg_t mask) +{ + return (((Rstc *)hw)->RSTC_SR & RSTC_SR_RSTTYP(mask)) >> RSTC_SR_RSTTYP_Pos; +} + +static inline hri_rstc_sr_reg_t hri_rstc_read_SR_RSTTYP_bf(const void *const hw) +{ + return (((Rstc *)hw)->RSTC_SR & RSTC_SR_RSTTYP_Msk) >> RSTC_SR_RSTTYP_Pos; +} + +static inline hri_rstc_sr_reg_t hri_rstc_get_SR_reg(const void *const hw, hri_rstc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_sr_reg_t hri_rstc_read_SR_reg(const void *const hw) +{ + return ((Rstc *)hw)->RSTC_SR; +} + +static inline void hri_rstc_set_MR_URSTEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR |= RSTC_MR_URSTEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rstc_get_MR_URSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_URSTEN) >> RSTC_MR_URSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_rstc_write_MR_URSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->RSTC_MR; + tmp &= ~RSTC_MR_URSTEN; + tmp |= value << RSTC_MR_URSTEN_Pos; + ((Rstc *)hw)->RSTC_MR = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_MR_URSTEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR &= ~RSTC_MR_URSTEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_MR_URSTEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR ^= RSTC_MR_URSTEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_set_MR_URSTIEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR |= RSTC_MR_URSTIEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rstc_get_MR_URSTIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_URSTIEN) >> RSTC_MR_URSTIEN_Pos; + return (bool)tmp; +} + +static inline void hri_rstc_write_MR_URSTIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->RSTC_MR; + tmp &= ~RSTC_MR_URSTIEN; + tmp |= value << RSTC_MR_URSTIEN_Pos; + ((Rstc *)hw)->RSTC_MR = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_MR_URSTIEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR &= ~RSTC_MR_URSTIEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_MR_URSTIEN_bit(const void *const hw) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR ^= RSTC_MR_URSTIEN; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_set_MR_ERSTL_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR |= RSTC_MR_ERSTL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_get_MR_ERSTL_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_ERSTL(mask)) >> RSTC_MR_ERSTL_Pos; + return tmp; +} + +static inline void hri_rstc_write_MR_ERSTL_bf(const void *const hw, hri_rstc_mr_reg_t data) +{ + uint32_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->RSTC_MR; + tmp &= ~RSTC_MR_ERSTL_Msk; + tmp |= RSTC_MR_ERSTL(data); + ((Rstc *)hw)->RSTC_MR = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_MR_ERSTL_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR &= ~RSTC_MR_ERSTL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_MR_ERSTL_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR ^= RSTC_MR_ERSTL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_read_MR_ERSTL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_ERSTL_Msk) >> RSTC_MR_ERSTL_Pos; + return tmp; +} + +static inline void hri_rstc_set_MR_KEY_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR |= RSTC_MR_KEY(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_get_MR_KEY_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_KEY(mask)) >> RSTC_MR_KEY_Pos; + return tmp; +} + +static inline void hri_rstc_write_MR_KEY_bf(const void *const hw, hri_rstc_mr_reg_t data) +{ + uint32_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->RSTC_MR; + tmp &= ~RSTC_MR_KEY_Msk; + tmp |= RSTC_MR_KEY(data); + ((Rstc *)hw)->RSTC_MR = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_MR_KEY_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR &= ~RSTC_MR_KEY(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_MR_KEY_bf(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR ^= RSTC_MR_KEY(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_read_MR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp = (tmp & RSTC_MR_KEY_Msk) >> RSTC_MR_KEY_Pos; + return tmp; +} + +static inline void hri_rstc_set_MR_reg(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_get_MR_reg(const void *const hw, hri_rstc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rstc *)hw)->RSTC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_MR_reg(const void *const hw, hri_rstc_mr_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_MR_reg(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_MR_reg(const void *const hw, hri_rstc_mr_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_MR ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_mr_reg_t hri_rstc_read_MR_reg(const void *const hw) +{ + return ((Rstc *)hw)->RSTC_MR; +} + +static inline void hri_rstc_write_CR_reg(const void *const hw, hri_rstc_cr_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->RSTC_CR = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_E70B_H_INCLUDED */ +#endif /* _SAME70_RSTC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_rswdt_e70b.h b/bsp/microchip/same70/bsp/hri/hri_rswdt_e70b.h new file mode 100644 index 0000000000..42a0670a6a --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_rswdt_e70b.h @@ -0,0 +1,423 @@ +/** + * \file + * + * \brief SAM RSWDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_RSWDT_COMPONENT_ +#ifndef _HRI_RSWDT_E70B_H_INCLUDED_ +#define _HRI_RSWDT_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSWDT_CRITICAL_SECTIONS) +#define RSWDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSWDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSWDT_CRITICAL_SECTION_ENTER() +#define RSWDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_rswdt_cr_reg_t; +typedef uint32_t hri_rswdt_mr_reg_t; +typedef uint32_t hri_rswdt_sr_reg_t; + +static inline bool hri_rswdt_get_SR_WDUNF_bit(const void *const hw) +{ + return (((Rswdt *)hw)->RSWDT_SR & RSWDT_SR_WDUNF) > 0; +} + +static inline hri_rswdt_sr_reg_t hri_rswdt_get_SR_reg(const void *const hw, hri_rswdt_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_SR; + tmp &= mask; + return tmp; +} + +static inline hri_rswdt_sr_reg_t hri_rswdt_read_SR_reg(const void *const hw) +{ + return ((Rswdt *)hw)->RSWDT_SR; +} + +static inline void hri_rswdt_set_MR_WDFIEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDFIEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rswdt_get_MR_WDFIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDFIEN) >> RSWDT_MR_WDFIEN_Pos; + return (bool)tmp; +} + +static inline void hri_rswdt_write_MR_WDFIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDFIEN; + tmp |= value << RSWDT_MR_WDFIEN_Pos; + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDFIEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDFIEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDFIEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDFIEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_set_MR_WDRSTEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDRSTEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rswdt_get_MR_WDRSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDRSTEN) >> RSWDT_MR_WDRSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_rswdt_write_MR_WDRSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDRSTEN; + tmp |= value << RSWDT_MR_WDRSTEN_Pos; + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDRSTEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDRSTEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDRSTEN_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDRSTEN; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_set_MR_WDDIS_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDDIS; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rswdt_get_MR_WDDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDDIS) >> RSWDT_MR_WDDIS_Pos; + return (bool)tmp; +} + +static inline void hri_rswdt_write_MR_WDDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDDIS; + tmp |= value << RSWDT_MR_WDDIS_Pos; + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDDIS_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDDIS; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDDIS_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDDIS; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_set_MR_WDDBGHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDDBGHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rswdt_get_MR_WDDBGHLT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDDBGHLT) >> RSWDT_MR_WDDBGHLT_Pos; + return (bool)tmp; +} + +static inline void hri_rswdt_write_MR_WDDBGHLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDDBGHLT; + tmp |= value << RSWDT_MR_WDDBGHLT_Pos; + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDDBGHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDDBGHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDDBGHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDDBGHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_set_MR_WDIDLEHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDIDLEHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rswdt_get_MR_WDIDLEHLT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDIDLEHLT) >> RSWDT_MR_WDIDLEHLT_Pos; + return (bool)tmp; +} + +static inline void hri_rswdt_write_MR_WDIDLEHLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDIDLEHLT; + tmp |= value << RSWDT_MR_WDIDLEHLT_Pos; + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDIDLEHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDIDLEHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDIDLEHLT_bit(const void *const hw) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDIDLEHLT; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_set_MR_WDV_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_WDV(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_get_MR_WDV_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDV(mask)) >> RSWDT_MR_WDV_Pos; + return tmp; +} + +static inline void hri_rswdt_write_MR_WDV_bf(const void *const hw, hri_rswdt_mr_reg_t data) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_WDV_Msk; + tmp |= RSWDT_MR_WDV(data); + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_WDV_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_WDV(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_WDV_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_WDV(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_read_MR_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_WDV_Msk) >> RSWDT_MR_WDV_Pos; + return tmp; +} + +static inline void hri_rswdt_set_MR_ALLONES_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= RSWDT_MR_ALLONES(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_get_MR_ALLONES_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_ALLONES(mask)) >> RSWDT_MR_ALLONES_Pos; + return tmp; +} + +static inline void hri_rswdt_write_MR_ALLONES_bf(const void *const hw, hri_rswdt_mr_reg_t data) +{ + uint32_t tmp; + RSWDT_CRITICAL_SECTION_ENTER(); + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= ~RSWDT_MR_ALLONES_Msk; + tmp |= RSWDT_MR_ALLONES(data); + ((Rswdt *)hw)->RSWDT_MR = tmp; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_ALLONES_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~RSWDT_MR_ALLONES(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_ALLONES_bf(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= RSWDT_MR_ALLONES(mask); + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_read_MR_ALLONES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp = (tmp & RSWDT_MR_ALLONES_Msk) >> RSWDT_MR_ALLONES_Pos; + return tmp; +} + +static inline void hri_rswdt_set_MR_reg(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR |= mask; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_get_MR_reg(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rswdt *)hw)->RSWDT_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_rswdt_write_MR_reg(const void *const hw, hri_rswdt_mr_reg_t data) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR = data; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_clear_MR_reg(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR &= ~mask; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rswdt_toggle_MR_reg(const void *const hw, hri_rswdt_mr_reg_t mask) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_MR ^= mask; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rswdt_mr_reg_t hri_rswdt_read_MR_reg(const void *const hw) +{ + return ((Rswdt *)hw)->RSWDT_MR; +} + +static inline void hri_rswdt_write_CR_reg(const void *const hw, hri_rswdt_cr_reg_t data) +{ + RSWDT_CRITICAL_SECTION_ENTER(); + ((Rswdt *)hw)->RSWDT_CR = data; + RSWDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSWDT_E70B_H_INCLUDED */ +#endif /* _SAME70_RSWDT_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_rtc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_rtc_e70b.h new file mode 100644 index 0000000000..2ba3cdd089 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_rtc_e70b.h @@ -0,0 +1,2050 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_RTC_COMPONENT_ +#ifndef _HRI_RTC_E70B_H_INCLUDED_ +#define _HRI_RTC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_rtc_calalr_reg_t; +typedef uint32_t hri_rtc_calr_reg_t; +typedef uint32_t hri_rtc_cr_reg_t; +typedef uint32_t hri_rtc_imr_reg_t; +typedef uint32_t hri_rtc_mr_reg_t; +typedef uint32_t hri_rtc_sccr_reg_t; +typedef uint32_t hri_rtc_sr_reg_t; +typedef uint32_t hri_rtc_timalr_reg_t; +typedef uint32_t hri_rtc_timr_reg_t; +typedef uint32_t hri_rtc_ver_reg_t; + +static inline void hri_rtc_set_IMR_ACK_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_ACK; +} + +static inline bool hri_rtc_get_IMR_ACK_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_ACK) >> RTC_IMR_ACK_Pos; +} + +static inline void hri_rtc_write_IMR_ACK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_ACK; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_ACK; + } +} + +static inline void hri_rtc_clear_IMR_ACK_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_ACK; +} + +static inline void hri_rtc_set_IMR_ALR_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_ALR; +} + +static inline bool hri_rtc_get_IMR_ALR_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_ALR) >> RTC_IMR_ALR_Pos; +} + +static inline void hri_rtc_write_IMR_ALR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_ALR; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_ALR; + } +} + +static inline void hri_rtc_clear_IMR_ALR_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_ALR; +} + +static inline void hri_rtc_set_IMR_SEC_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_SEC; +} + +static inline bool hri_rtc_get_IMR_SEC_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_SEC) >> RTC_IMR_SEC_Pos; +} + +static inline void hri_rtc_write_IMR_SEC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_SEC; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_SEC; + } +} + +static inline void hri_rtc_clear_IMR_SEC_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_SEC; +} + +static inline void hri_rtc_set_IMR_TIM_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_TIM; +} + +static inline bool hri_rtc_get_IMR_TIM_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_TIM) >> RTC_IMR_TIM_Pos; +} + +static inline void hri_rtc_write_IMR_TIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_TIM; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_TIM; + } +} + +static inline void hri_rtc_clear_IMR_TIM_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_TIM; +} + +static inline void hri_rtc_set_IMR_CAL_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_CAL; +} + +static inline bool hri_rtc_get_IMR_CAL_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_CAL) >> RTC_IMR_CAL_Pos; +} + +static inline void hri_rtc_write_IMR_CAL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_CAL; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_CAL; + } +} + +static inline void hri_rtc_clear_IMR_CAL_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_CAL; +} + +static inline void hri_rtc_set_IMR_TDERR_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IER = RTC_IMR_TDERR; +} + +static inline bool hri_rtc_get_IMR_TDERR_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_IMR & RTC_IMR_TDERR) >> RTC_IMR_TDERR_Pos; +} + +static inline void hri_rtc_write_IMR_TDERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->RTC_IDR = RTC_IMR_TDERR; + } else { + ((Rtc *)hw)->RTC_IER = RTC_IMR_TDERR; + } +} + +static inline void hri_rtc_clear_IMR_TDERR_bit(const void *const hw) +{ + ((Rtc *)hw)->RTC_IDR = RTC_IMR_TDERR; +} + +static inline void hri_rtc_set_IMR_reg(const void *const hw, hri_rtc_imr_reg_t mask) +{ + ((Rtc *)hw)->RTC_IER = mask; +} + +static inline hri_rtc_imr_reg_t hri_rtc_get_IMR_reg(const void *const hw, hri_rtc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_rtc_imr_reg_t hri_rtc_read_IMR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_IMR; +} + +static inline void hri_rtc_write_IMR_reg(const void *const hw, hri_rtc_imr_reg_t data) +{ + ((Rtc *)hw)->RTC_IER = data; + ((Rtc *)hw)->RTC_IDR = ~data; +} + +static inline void hri_rtc_clear_IMR_reg(const void *const hw, hri_rtc_imr_reg_t mask) +{ + ((Rtc *)hw)->RTC_IDR = mask; +} + +static inline bool hri_rtc_get_SR_ACKUPD_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_ACKUPD) > 0; +} + +static inline bool hri_rtc_get_SR_ALARM_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_ALARM) > 0; +} + +static inline bool hri_rtc_get_SR_SEC_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_SEC) > 0; +} + +static inline bool hri_rtc_get_SR_TIMEV_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_TIMEV) > 0; +} + +static inline bool hri_rtc_get_SR_CALEV_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_CALEV) > 0; +} + +static inline bool hri_rtc_get_SR_TDERR_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_SR & RTC_SR_TDERR) > 0; +} + +static inline hri_rtc_sr_reg_t hri_rtc_get_SR_reg(const void *const hw, hri_rtc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_rtc_sr_reg_t hri_rtc_read_SR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_SR; +} + +static inline bool hri_rtc_get_VER_NVTIM_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_VER & RTC_VER_NVTIM) > 0; +} + +static inline bool hri_rtc_get_VER_NVCAL_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_VER & RTC_VER_NVCAL) > 0; +} + +static inline bool hri_rtc_get_VER_NVTIMALR_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_VER & RTC_VER_NVTIMALR) > 0; +} + +static inline bool hri_rtc_get_VER_NVCALALR_bit(const void *const hw) +{ + return (((Rtc *)hw)->RTC_VER & RTC_VER_NVCALALR) > 0; +} + +static inline hri_rtc_ver_reg_t hri_rtc_get_VER_reg(const void *const hw, hri_rtc_ver_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_VER; + tmp &= mask; + return tmp; +} + +static inline hri_rtc_ver_reg_t hri_rtc_read_VER_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_VER; +} + +static inline void hri_rtc_set_CR_UPDTIM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR |= RTC_CR_UPDTIM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_CR_UPDTIM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_UPDTIM) >> RTC_CR_UPDTIM_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_CR_UPDTIM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CR; + tmp &= ~RTC_CR_UPDTIM; + tmp |= value << RTC_CR_UPDTIM_Pos; + ((Rtc *)hw)->RTC_CR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CR_UPDTIM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR &= ~RTC_CR_UPDTIM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CR_UPDTIM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR ^= RTC_CR_UPDTIM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_CR_UPDCAL_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR |= RTC_CR_UPDCAL; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_CR_UPDCAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_UPDCAL) >> RTC_CR_UPDCAL_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_CR_UPDCAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CR; + tmp &= ~RTC_CR_UPDCAL; + tmp |= value << RTC_CR_UPDCAL_Pos; + ((Rtc *)hw)->RTC_CR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CR_UPDCAL_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR &= ~RTC_CR_UPDCAL; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CR_UPDCAL_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR ^= RTC_CR_UPDCAL; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_CR_TIMEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR |= RTC_CR_TIMEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_get_CR_TIMEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_TIMEVSEL(mask)) >> RTC_CR_TIMEVSEL_Pos; + return tmp; +} + +static inline void hri_rtc_write_CR_TIMEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CR; + tmp &= ~RTC_CR_TIMEVSEL_Msk; + tmp |= RTC_CR_TIMEVSEL(data); + ((Rtc *)hw)->RTC_CR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CR_TIMEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR &= ~RTC_CR_TIMEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CR_TIMEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR ^= RTC_CR_TIMEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_read_CR_TIMEVSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_TIMEVSEL_Msk) >> RTC_CR_TIMEVSEL_Pos; + return tmp; +} + +static inline void hri_rtc_set_CR_CALEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR |= RTC_CR_CALEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_get_CR_CALEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_CALEVSEL(mask)) >> RTC_CR_CALEVSEL_Pos; + return tmp; +} + +static inline void hri_rtc_write_CR_CALEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CR; + tmp &= ~RTC_CR_CALEVSEL_Msk; + tmp |= RTC_CR_CALEVSEL(data); + ((Rtc *)hw)->RTC_CR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CR_CALEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR &= ~RTC_CR_CALEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CR_CALEVSEL_bf(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR ^= RTC_CR_CALEVSEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_read_CR_CALEVSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp = (tmp & RTC_CR_CALEVSEL_Msk) >> RTC_CR_CALEVSEL_Pos; + return tmp; +} + +static inline void hri_rtc_set_CR_reg(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_get_CR_reg(const void *const hw, hri_rtc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_CR_reg(const void *const hw, hri_rtc_cr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CR_reg(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CR_reg(const void *const hw, hri_rtc_cr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_cr_reg_t hri_rtc_read_CR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_CR; +} + +static inline void hri_rtc_set_MR_HRMOD_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_HRMOD; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_MR_HRMOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_HRMOD) >> RTC_MR_HRMOD_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_MR_HRMOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_HRMOD; + tmp |= value << RTC_MR_HRMOD_Pos; + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_HRMOD_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_HRMOD; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_HRMOD_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_HRMOD; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_MR_PERSIAN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_PERSIAN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_MR_PERSIAN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_PERSIAN) >> RTC_MR_PERSIAN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_MR_PERSIAN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_PERSIAN; + tmp |= value << RTC_MR_PERSIAN_Pos; + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_PERSIAN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_PERSIAN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_PERSIAN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_PERSIAN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_MR_NEGPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_NEGPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_MR_NEGPPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_NEGPPM) >> RTC_MR_NEGPPM_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_MR_NEGPPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_NEGPPM; + tmp |= value << RTC_MR_NEGPPM_Pos; + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_NEGPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_NEGPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_NEGPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_NEGPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_MR_HIGHPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_HIGHPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_MR_HIGHPPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_HIGHPPM) >> RTC_MR_HIGHPPM_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_MR_HIGHPPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_HIGHPPM; + tmp |= value << RTC_MR_HIGHPPM_Pos; + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_HIGHPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_HIGHPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_HIGHPPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_HIGHPPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_MR_CORRECTION_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_CORRECTION(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_CORRECTION_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_CORRECTION(mask)) >> RTC_MR_CORRECTION_Pos; + return tmp; +} + +static inline void hri_rtc_write_MR_CORRECTION_bf(const void *const hw, hri_rtc_mr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_CORRECTION_Msk; + tmp |= RTC_MR_CORRECTION(data); + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_CORRECTION_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_CORRECTION(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_CORRECTION_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_CORRECTION(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_CORRECTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_CORRECTION_Msk) >> RTC_MR_CORRECTION_Pos; + return tmp; +} + +static inline void hri_rtc_set_MR_OUT0_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_OUT0(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_OUT0_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_OUT0(mask)) >> RTC_MR_OUT0_Pos; + return tmp; +} + +static inline void hri_rtc_write_MR_OUT0_bf(const void *const hw, hri_rtc_mr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_OUT0_Msk; + tmp |= RTC_MR_OUT0(data); + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_OUT0_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_OUT0(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_OUT0_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_OUT0(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_OUT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_OUT0_Msk) >> RTC_MR_OUT0_Pos; + return tmp; +} + +static inline void hri_rtc_set_MR_OUT1_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_OUT1(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_OUT1_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_OUT1(mask)) >> RTC_MR_OUT1_Pos; + return tmp; +} + +static inline void hri_rtc_write_MR_OUT1_bf(const void *const hw, hri_rtc_mr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_OUT1_Msk; + tmp |= RTC_MR_OUT1(data); + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_OUT1_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_OUT1(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_OUT1_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_OUT1(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_OUT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_OUT1_Msk) >> RTC_MR_OUT1_Pos; + return tmp; +} + +static inline void hri_rtc_set_MR_THIGH_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_THIGH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_THIGH_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_THIGH(mask)) >> RTC_MR_THIGH_Pos; + return tmp; +} + +static inline void hri_rtc_write_MR_THIGH_bf(const void *const hw, hri_rtc_mr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_THIGH_Msk; + tmp |= RTC_MR_THIGH(data); + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_THIGH_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_THIGH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_THIGH_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_THIGH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_THIGH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_THIGH_Msk) >> RTC_MR_THIGH_Pos; + return tmp; +} + +static inline void hri_rtc_set_MR_TPERIOD_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= RTC_MR_TPERIOD(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_TPERIOD_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_TPERIOD(mask)) >> RTC_MR_TPERIOD_Pos; + return tmp; +} + +static inline void hri_rtc_write_MR_TPERIOD_bf(const void *const hw, hri_rtc_mr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= ~RTC_MR_TPERIOD_Msk; + tmp |= RTC_MR_TPERIOD(data); + ((Rtc *)hw)->RTC_MR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_TPERIOD_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~RTC_MR_TPERIOD(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_TPERIOD_bf(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= RTC_MR_TPERIOD(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_TPERIOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp = (tmp & RTC_MR_TPERIOD_Msk) >> RTC_MR_TPERIOD_Pos; + return tmp; +} + +static inline void hri_rtc_set_MR_reg(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_get_MR_reg(const void *const hw, hri_rtc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_MR_reg(const void *const hw, hri_rtc_mr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_MR_reg(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_MR_reg(const void *const hw, hri_rtc_mr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_MR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_mr_reg_t hri_rtc_read_MR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_MR; +} + +static inline void hri_rtc_set_TIMR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR |= RTC_TIMR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TIMR_AMPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_AMPM) >> RTC_TIMR_AMPM_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TIMR_AMPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp &= ~RTC_TIMR_AMPM; + tmp |= value << RTC_TIMR_AMPM_Pos; + ((Rtc *)hw)->RTC_TIMR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR &= ~RTC_TIMR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR ^= RTC_TIMR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TIMR_SEC_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR |= RTC_TIMR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_get_TIMR_SEC_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_SEC(mask)) >> RTC_TIMR_SEC_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMR_SEC_bf(const void *const hw, hri_rtc_timr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp &= ~RTC_TIMR_SEC_Msk; + tmp |= RTC_TIMR_SEC(data); + ((Rtc *)hw)->RTC_TIMR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMR_SEC_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR &= ~RTC_TIMR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMR_SEC_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR ^= RTC_TIMR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_read_TIMR_SEC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_SEC_Msk) >> RTC_TIMR_SEC_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMR_MIN_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR |= RTC_TIMR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_get_TIMR_MIN_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_MIN(mask)) >> RTC_TIMR_MIN_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMR_MIN_bf(const void *const hw, hri_rtc_timr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp &= ~RTC_TIMR_MIN_Msk; + tmp |= RTC_TIMR_MIN(data); + ((Rtc *)hw)->RTC_TIMR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMR_MIN_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR &= ~RTC_TIMR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMR_MIN_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR ^= RTC_TIMR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_read_TIMR_MIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_MIN_Msk) >> RTC_TIMR_MIN_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMR_HOUR_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR |= RTC_TIMR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_get_TIMR_HOUR_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_HOUR(mask)) >> RTC_TIMR_HOUR_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMR_HOUR_bf(const void *const hw, hri_rtc_timr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp &= ~RTC_TIMR_HOUR_Msk; + tmp |= RTC_TIMR_HOUR(data); + ((Rtc *)hw)->RTC_TIMR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMR_HOUR_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR &= ~RTC_TIMR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMR_HOUR_bf(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR ^= RTC_TIMR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_read_TIMR_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp = (tmp & RTC_TIMR_HOUR_Msk) >> RTC_TIMR_HOUR_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMR_reg(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_get_TIMR_reg(const void *const hw, hri_rtc_timr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TIMR_reg(const void *const hw, hri_rtc_timr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMR_reg(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMR_reg(const void *const hw, hri_rtc_timr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timr_reg_t hri_rtc_read_TIMR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_TIMR; +} + +static inline void hri_rtc_set_CALR_CENT_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= RTC_CALR_CENT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_CENT_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_CENT(mask)) >> RTC_CALR_CENT_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALR_CENT_bf(const void *const hw, hri_rtc_calr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= ~RTC_CALR_CENT_Msk; + tmp |= RTC_CALR_CENT(data); + ((Rtc *)hw)->RTC_CALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_CENT_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~RTC_CALR_CENT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_CENT_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= RTC_CALR_CENT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_CENT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_CENT_Msk) >> RTC_CALR_CENT_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALR_YEAR_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= RTC_CALR_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_YEAR_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_YEAR(mask)) >> RTC_CALR_YEAR_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALR_YEAR_bf(const void *const hw, hri_rtc_calr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= ~RTC_CALR_YEAR_Msk; + tmp |= RTC_CALR_YEAR(data); + ((Rtc *)hw)->RTC_CALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_YEAR_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~RTC_CALR_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_YEAR_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= RTC_CALR_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_YEAR_Msk) >> RTC_CALR_YEAR_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALR_MONTH_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= RTC_CALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_MONTH_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_MONTH(mask)) >> RTC_CALR_MONTH_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALR_MONTH_bf(const void *const hw, hri_rtc_calr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= ~RTC_CALR_MONTH_Msk; + tmp |= RTC_CALR_MONTH(data); + ((Rtc *)hw)->RTC_CALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_MONTH_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~RTC_CALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_MONTH_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= RTC_CALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_MONTH_Msk) >> RTC_CALR_MONTH_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALR_DAY_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= RTC_CALR_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_DAY_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_DAY(mask)) >> RTC_CALR_DAY_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALR_DAY_bf(const void *const hw, hri_rtc_calr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= ~RTC_CALR_DAY_Msk; + tmp |= RTC_CALR_DAY(data); + ((Rtc *)hw)->RTC_CALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_DAY_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~RTC_CALR_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_DAY_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= RTC_CALR_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_DAY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_DAY_Msk) >> RTC_CALR_DAY_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALR_DATE_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= RTC_CALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_DATE_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_DATE(mask)) >> RTC_CALR_DATE_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALR_DATE_bf(const void *const hw, hri_rtc_calr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= ~RTC_CALR_DATE_Msk; + tmp |= RTC_CALR_DATE(data); + ((Rtc *)hw)->RTC_CALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_DATE_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~RTC_CALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_DATE_bf(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= RTC_CALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_DATE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp = (tmp & RTC_CALR_DATE_Msk) >> RTC_CALR_DATE_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALR_reg(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_get_CALR_reg(const void *const hw, hri_rtc_calr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_CALR_reg(const void *const hw, hri_rtc_calr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALR_reg(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALR_reg(const void *const hw, hri_rtc_calr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calr_reg_t hri_rtc_read_CALR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_CALR; +} + +static inline void hri_rtc_set_TIMALR_SECEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_SECEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TIMALR_SECEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_SECEN) >> RTC_TIMALR_SECEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TIMALR_SECEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_SECEN; + tmp |= value << RTC_TIMALR_SECEN_Pos; + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_SECEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_SECEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_SECEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_SECEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TIMALR_MINEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_MINEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TIMALR_MINEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_MINEN) >> RTC_TIMALR_MINEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TIMALR_MINEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_MINEN; + tmp |= value << RTC_TIMALR_MINEN_Pos; + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_MINEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_MINEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_MINEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_MINEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TIMALR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TIMALR_AMPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_AMPM) >> RTC_TIMALR_AMPM_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TIMALR_AMPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_AMPM; + tmp |= value << RTC_TIMALR_AMPM_Pos; + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_AMPM_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_AMPM; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TIMALR_HOUREN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_HOUREN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TIMALR_HOUREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_HOUREN) >> RTC_TIMALR_HOUREN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TIMALR_HOUREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_HOUREN; + tmp |= value << RTC_TIMALR_HOUREN_Pos; + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_HOUREN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_HOUREN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_HOUREN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_HOUREN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TIMALR_SEC_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_get_TIMALR_SEC_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_SEC(mask)) >> RTC_TIMALR_SEC_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMALR_SEC_bf(const void *const hw, hri_rtc_timalr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_SEC_Msk; + tmp |= RTC_TIMALR_SEC(data); + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_SEC_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_SEC_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_SEC(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_read_TIMALR_SEC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_SEC_Msk) >> RTC_TIMALR_SEC_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMALR_MIN_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_get_TIMALR_MIN_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_MIN(mask)) >> RTC_TIMALR_MIN_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMALR_MIN_bf(const void *const hw, hri_rtc_timalr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_MIN_Msk; + tmp |= RTC_TIMALR_MIN(data); + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_MIN_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_MIN_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_MIN(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_read_TIMALR_MIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_MIN_Msk) >> RTC_TIMALR_MIN_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMALR_HOUR_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= RTC_TIMALR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_get_TIMALR_HOUR_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_HOUR(mask)) >> RTC_TIMALR_HOUR_Pos; + return tmp; +} + +static inline void hri_rtc_write_TIMALR_HOUR_bf(const void *const hw, hri_rtc_timalr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= ~RTC_TIMALR_HOUR_Msk; + tmp |= RTC_TIMALR_HOUR(data); + ((Rtc *)hw)->RTC_TIMALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_HOUR_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~RTC_TIMALR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_HOUR_bf(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= RTC_TIMALR_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_read_TIMALR_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp = (tmp & RTC_TIMALR_HOUR_Msk) >> RTC_TIMALR_HOUR_Pos; + return tmp; +} + +static inline void hri_rtc_set_TIMALR_reg(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_get_TIMALR_reg(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_TIMALR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TIMALR_reg(const void *const hw, hri_rtc_timalr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TIMALR_reg(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TIMALR_reg(const void *const hw, hri_rtc_timalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_TIMALR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_timalr_reg_t hri_rtc_read_TIMALR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_TIMALR; +} + +static inline void hri_rtc_set_CALALR_MTHEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR |= RTC_CALALR_MTHEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_CALALR_MTHEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_MTHEN) >> RTC_CALALR_MTHEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_CALALR_MTHEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp &= ~RTC_CALALR_MTHEN; + tmp |= value << RTC_CALALR_MTHEN_Pos; + ((Rtc *)hw)->RTC_CALALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALALR_MTHEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR &= ~RTC_CALALR_MTHEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALALR_MTHEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR ^= RTC_CALALR_MTHEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_CALALR_DATEEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR |= RTC_CALALR_DATEEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_CALALR_DATEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_DATEEN) >> RTC_CALALR_DATEEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_CALALR_DATEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp &= ~RTC_CALALR_DATEEN; + tmp |= value << RTC_CALALR_DATEEN_Pos; + ((Rtc *)hw)->RTC_CALALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALALR_DATEEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR &= ~RTC_CALALR_DATEEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALALR_DATEEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR ^= RTC_CALALR_DATEEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_CALALR_MONTH_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR |= RTC_CALALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_get_CALALR_MONTH_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_MONTH(mask)) >> RTC_CALALR_MONTH_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALALR_MONTH_bf(const void *const hw, hri_rtc_calalr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp &= ~RTC_CALALR_MONTH_Msk; + tmp |= RTC_CALALR_MONTH(data); + ((Rtc *)hw)->RTC_CALALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALALR_MONTH_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR &= ~RTC_CALALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALALR_MONTH_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR ^= RTC_CALALR_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_read_CALALR_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_MONTH_Msk) >> RTC_CALALR_MONTH_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALALR_DATE_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR |= RTC_CALALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_get_CALALR_DATE_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_DATE(mask)) >> RTC_CALALR_DATE_Pos; + return tmp; +} + +static inline void hri_rtc_write_CALALR_DATE_bf(const void *const hw, hri_rtc_calalr_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp &= ~RTC_CALALR_DATE_Msk; + tmp |= RTC_CALALR_DATE(data); + ((Rtc *)hw)->RTC_CALALR = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALALR_DATE_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR &= ~RTC_CALALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALALR_DATE_bf(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR ^= RTC_CALALR_DATE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_read_CALALR_DATE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp = (tmp & RTC_CALALR_DATE_Msk) >> RTC_CALALR_DATE_Pos; + return tmp; +} + +static inline void hri_rtc_set_CALALR_reg(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_get_CALALR_reg(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->RTC_CALALR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_CALALR_reg(const void *const hw, hri_rtc_calalr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_CALALR_reg(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_CALALR_reg(const void *const hw, hri_rtc_calalr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_CALALR ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_calalr_reg_t hri_rtc_read_CALALR_reg(const void *const hw) +{ + return ((Rtc *)hw)->RTC_CALALR; +} + +static inline void hri_rtc_write_SCCR_reg(const void *const hw, hri_rtc_sccr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->RTC_SCCR = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_E70B_H_INCLUDED */ +#endif /* _SAME70_RTC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_rtt_e70b.h b/bsp/microchip/same70/bsp/hri/hri_rtt_e70b.h new file mode 100644 index 0000000000..daffcdf4bc --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_rtt_e70b.h @@ -0,0 +1,486 @@ +/** + * \file + * + * \brief SAM RTT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_RTT_COMPONENT_ +#ifndef _HRI_RTT_E70B_H_INCLUDED_ +#define _HRI_RTT_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTT_CRITICAL_SECTIONS) +#define RTT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTT_CRITICAL_SECTION_ENTER() +#define RTT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_rtt_ar_reg_t; +typedef uint32_t hri_rtt_mr_reg_t; +typedef uint32_t hri_rtt_sr_reg_t; +typedef uint32_t hri_rtt_vr_reg_t; + +static inline hri_rtt_vr_reg_t hri_rtt_get_VR_CRTV_bf(const void *const hw, hri_rtt_vr_reg_t mask) +{ + return (((Rtt *)hw)->RTT_VR & RTT_VR_CRTV(mask)) >> RTT_VR_CRTV_Pos; +} + +static inline hri_rtt_vr_reg_t hri_rtt_read_VR_CRTV_bf(const void *const hw) +{ + return (((Rtt *)hw)->RTT_VR & RTT_VR_CRTV_Msk) >> RTT_VR_CRTV_Pos; +} + +static inline hri_rtt_vr_reg_t hri_rtt_get_VR_reg(const void *const hw, hri_rtt_vr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_VR; + tmp &= mask; + return tmp; +} + +static inline hri_rtt_vr_reg_t hri_rtt_read_VR_reg(const void *const hw) +{ + return ((Rtt *)hw)->RTT_VR; +} + +static inline bool hri_rtt_get_SR_ALMS_bit(const void *const hw) +{ + return (((Rtt *)hw)->RTT_SR & RTT_SR_ALMS) > 0; +} + +static inline bool hri_rtt_get_SR_RTTINC_bit(const void *const hw) +{ + return (((Rtt *)hw)->RTT_SR & RTT_SR_RTTINC) > 0; +} + +static inline hri_rtt_sr_reg_t hri_rtt_get_SR_reg(const void *const hw, hri_rtt_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_SR; + tmp &= mask; + return tmp; +} + +static inline hri_rtt_sr_reg_t hri_rtt_read_SR_reg(const void *const hw) +{ + return ((Rtt *)hw)->RTT_SR; +} + +static inline void hri_rtt_set_MR_ALMIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_ALMIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtt_get_MR_ALMIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_ALMIEN) >> RTT_MR_ALMIEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtt_write_MR_ALMIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_ALMIEN; + tmp |= value << RTT_MR_ALMIEN_Pos; + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_ALMIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_ALMIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_ALMIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_ALMIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_set_MR_RTTINCIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_RTTINCIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtt_get_MR_RTTINCIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTTINCIEN) >> RTT_MR_RTTINCIEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtt_write_MR_RTTINCIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_RTTINCIEN; + tmp |= value << RTT_MR_RTTINCIEN_Pos; + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_RTTINCIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_RTTINCIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_RTTINCIEN_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_RTTINCIEN; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_set_MR_RTTRST_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_RTTRST; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtt_get_MR_RTTRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTTRST) >> RTT_MR_RTTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtt_write_MR_RTTRST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_RTTRST; + tmp |= value << RTT_MR_RTTRST_Pos; + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_RTTRST_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_RTTRST; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_RTTRST_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_RTTRST; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_set_MR_RTTDIS_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_RTTDIS; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtt_get_MR_RTTDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTTDIS) >> RTT_MR_RTTDIS_Pos; + return (bool)tmp; +} + +static inline void hri_rtt_write_MR_RTTDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_RTTDIS; + tmp |= value << RTT_MR_RTTDIS_Pos; + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_RTTDIS_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_RTTDIS; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_RTTDIS_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_RTTDIS; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_set_MR_RTC1HZ_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_RTC1HZ; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtt_get_MR_RTC1HZ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTC1HZ) >> RTT_MR_RTC1HZ_Pos; + return (bool)tmp; +} + +static inline void hri_rtt_write_MR_RTC1HZ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_RTC1HZ; + tmp |= value << RTT_MR_RTC1HZ_Pos; + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_RTC1HZ_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_RTC1HZ; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_RTC1HZ_bit(const void *const hw) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_RTC1HZ; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_set_MR_RTPRES_bf(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= RTT_MR_RTPRES(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_mr_reg_t hri_rtt_get_MR_RTPRES_bf(const void *const hw, hri_rtt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTPRES(mask)) >> RTT_MR_RTPRES_Pos; + return tmp; +} + +static inline void hri_rtt_write_MR_RTPRES_bf(const void *const hw, hri_rtt_mr_reg_t data) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= ~RTT_MR_RTPRES_Msk; + tmp |= RTT_MR_RTPRES(data); + ((Rtt *)hw)->RTT_MR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_RTPRES_bf(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~RTT_MR_RTPRES(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_RTPRES_bf(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= RTT_MR_RTPRES(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_mr_reg_t hri_rtt_read_MR_RTPRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp = (tmp & RTT_MR_RTPRES_Msk) >> RTT_MR_RTPRES_Pos; + return tmp; +} + +static inline void hri_rtt_set_MR_reg(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR |= mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_mr_reg_t hri_rtt_get_MR_reg(const void *const hw, hri_rtt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtt_write_MR_reg(const void *const hw, hri_rtt_mr_reg_t data) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR = data; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_MR_reg(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR &= ~mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_MR_reg(const void *const hw, hri_rtt_mr_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_MR ^= mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_mr_reg_t hri_rtt_read_MR_reg(const void *const hw) +{ + return ((Rtt *)hw)->RTT_MR; +} + +static inline void hri_rtt_set_AR_ALMV_bf(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR |= RTT_AR_ALMV(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_ar_reg_t hri_rtt_get_AR_ALMV_bf(const void *const hw, hri_rtt_ar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_AR; + tmp = (tmp & RTT_AR_ALMV(mask)) >> RTT_AR_ALMV_Pos; + return tmp; +} + +static inline void hri_rtt_write_AR_ALMV_bf(const void *const hw, hri_rtt_ar_reg_t data) +{ + uint32_t tmp; + RTT_CRITICAL_SECTION_ENTER(); + tmp = ((Rtt *)hw)->RTT_AR; + tmp &= ~RTT_AR_ALMV_Msk; + tmp |= RTT_AR_ALMV(data); + ((Rtt *)hw)->RTT_AR = tmp; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_AR_ALMV_bf(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR &= ~RTT_AR_ALMV(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_AR_ALMV_bf(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR ^= RTT_AR_ALMV(mask); + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_ar_reg_t hri_rtt_read_AR_ALMV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_AR; + tmp = (tmp & RTT_AR_ALMV_Msk) >> RTT_AR_ALMV_Pos; + return tmp; +} + +static inline void hri_rtt_set_AR_reg(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR |= mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_ar_reg_t hri_rtt_get_AR_reg(const void *const hw, hri_rtt_ar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtt *)hw)->RTT_AR; + tmp &= mask; + return tmp; +} + +static inline void hri_rtt_write_AR_reg(const void *const hw, hri_rtt_ar_reg_t data) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR = data; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_clear_AR_reg(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR &= ~mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtt_toggle_AR_reg(const void *const hw, hri_rtt_ar_reg_t mask) +{ + RTT_CRITICAL_SECTION_ENTER(); + ((Rtt *)hw)->RTT_AR ^= mask; + RTT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtt_ar_reg_t hri_rtt_read_AR_reg(const void *const hw) +{ + return ((Rtt *)hw)->RTT_AR; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTT_E70B_H_INCLUDED */ +#endif /* _SAME70_RTT_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_sdramc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_sdramc_e70b.h new file mode 100644 index 0000000000..1275334361 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_sdramc_e70b.h @@ -0,0 +1,1465 @@ +/** + * \file + * + * \brief SAM SDRAMC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_SDRAMC_COMPONENT_ +#ifndef _HRI_SDRAMC_E70B_H_INCLUDED_ +#define _HRI_SDRAMC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDRAMC_CRITICAL_SECTIONS) +#define SDRAMC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDRAMC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDRAMC_CRITICAL_SECTION_ENTER() +#define SDRAMC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_sdramc_cfr1_reg_t; +typedef uint32_t hri_sdramc_cr_reg_t; +typedef uint32_t hri_sdramc_imr_reg_t; +typedef uint32_t hri_sdramc_isr_reg_t; +typedef uint32_t hri_sdramc_lpr_reg_t; +typedef uint32_t hri_sdramc_mdr_reg_t; +typedef uint32_t hri_sdramc_mr_reg_t; +typedef uint32_t hri_sdramc_ocms_key1_reg_t; +typedef uint32_t hri_sdramc_ocms_key2_reg_t; +typedef uint32_t hri_sdramc_ocms_reg_t; +typedef uint32_t hri_sdramc_tr_reg_t; + +static inline bool hri_sdramc_get_ISR_RES_bit(const void *const hw) +{ + return (((Sdramc *)hw)->SDRAMC_ISR & SDRAMC_ISR_RES) >> SDRAMC_ISR_RES_Pos; +} + +static inline hri_sdramc_isr_reg_t hri_sdramc_get_ISR_reg(const void *const hw, hri_sdramc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_sdramc_isr_reg_t hri_sdramc_read_ISR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_ISR; +} + +static inline void hri_sdramc_set_IMR_RES_bit(const void *const hw) +{ + ((Sdramc *)hw)->SDRAMC_IER = SDRAMC_IMR_RES; +} + +static inline bool hri_sdramc_get_IMR_RES_bit(const void *const hw) +{ + return (((Sdramc *)hw)->SDRAMC_IMR & SDRAMC_IMR_RES) >> SDRAMC_IMR_RES_Pos; +} + +static inline void hri_sdramc_write_IMR_RES_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sdramc *)hw)->SDRAMC_IDR = SDRAMC_IMR_RES; + } else { + ((Sdramc *)hw)->SDRAMC_IER = SDRAMC_IMR_RES; + } +} + +static inline void hri_sdramc_clear_IMR_RES_bit(const void *const hw) +{ + ((Sdramc *)hw)->SDRAMC_IDR = SDRAMC_IMR_RES; +} + +static inline void hri_sdramc_set_IMR_reg(const void *const hw, hri_sdramc_imr_reg_t mask) +{ + ((Sdramc *)hw)->SDRAMC_IER = mask; +} + +static inline hri_sdramc_imr_reg_t hri_sdramc_get_IMR_reg(const void *const hw, hri_sdramc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_sdramc_imr_reg_t hri_sdramc_read_IMR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_IMR; +} + +static inline void hri_sdramc_write_IMR_reg(const void *const hw, hri_sdramc_imr_reg_t data) +{ + ((Sdramc *)hw)->SDRAMC_IER = data; + ((Sdramc *)hw)->SDRAMC_IDR = ~data; +} + +static inline void hri_sdramc_clear_IMR_reg(const void *const hw, hri_sdramc_imr_reg_t mask) +{ + ((Sdramc *)hw)->SDRAMC_IDR = mask; +} + +static inline void hri_sdramc_set_MR_MODE_bf(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR |= SDRAMC_MR_MODE(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mr_reg_t hri_sdramc_get_MR_MODE_bf(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MR; + tmp = (tmp & SDRAMC_MR_MODE(mask)) >> SDRAMC_MR_MODE_Pos; + return tmp; +} + +static inline void hri_sdramc_write_MR_MODE_bf(const void *const hw, hri_sdramc_mr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_MR; + tmp &= ~SDRAMC_MR_MODE_Msk; + tmp |= SDRAMC_MR_MODE(data); + ((Sdramc *)hw)->SDRAMC_MR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_MR_MODE_bf(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR &= ~SDRAMC_MR_MODE(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_MR_MODE_bf(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR ^= SDRAMC_MR_MODE(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mr_reg_t hri_sdramc_read_MR_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MR; + tmp = (tmp & SDRAMC_MR_MODE_Msk) >> SDRAMC_MR_MODE_Pos; + return tmp; +} + +static inline void hri_sdramc_set_MR_reg(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mr_reg_t hri_sdramc_get_MR_reg(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_MR_reg(const void *const hw, hri_sdramc_mr_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_MR_reg(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_MR_reg(const void *const hw, hri_sdramc_mr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MR ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mr_reg_t hri_sdramc_read_MR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_MR; +} + +static inline void hri_sdramc_set_TR_COUNT_bf(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR |= SDRAMC_TR_COUNT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_tr_reg_t hri_sdramc_get_TR_COUNT_bf(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_TR; + tmp = (tmp & SDRAMC_TR_COUNT(mask)) >> SDRAMC_TR_COUNT_Pos; + return tmp; +} + +static inline void hri_sdramc_write_TR_COUNT_bf(const void *const hw, hri_sdramc_tr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_TR; + tmp &= ~SDRAMC_TR_COUNT_Msk; + tmp |= SDRAMC_TR_COUNT(data); + ((Sdramc *)hw)->SDRAMC_TR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_TR_COUNT_bf(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR &= ~SDRAMC_TR_COUNT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_TR_COUNT_bf(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR ^= SDRAMC_TR_COUNT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_tr_reg_t hri_sdramc_read_TR_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_TR; + tmp = (tmp & SDRAMC_TR_COUNT_Msk) >> SDRAMC_TR_COUNT_Pos; + return tmp; +} + +static inline void hri_sdramc_set_TR_reg(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_tr_reg_t hri_sdramc_get_TR_reg(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_TR; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_TR_reg(const void *const hw, hri_sdramc_tr_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_TR_reg(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_TR_reg(const void *const hw, hri_sdramc_tr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_TR ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_tr_reg_t hri_sdramc_read_TR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_TR; +} + +static inline void hri_sdramc_set_CR_NB_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_NB; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdramc_get_CR_NB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_NB) >> SDRAMC_CR_NB_Pos; + return (bool)tmp; +} + +static inline void hri_sdramc_write_CR_NB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_NB; + tmp |= value << SDRAMC_CR_NB_Pos; + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_NB_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_NB; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_NB_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_NB; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_set_CR_DBW_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_DBW; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdramc_get_CR_DBW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_DBW) >> SDRAMC_CR_DBW_Pos; + return (bool)tmp; +} + +static inline void hri_sdramc_write_CR_DBW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_DBW; + tmp |= value << SDRAMC_CR_DBW_Pos; + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_DBW_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_DBW; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_DBW_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_DBW; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_set_CR_NC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_NC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_NC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_NC(mask)) >> SDRAMC_CR_NC_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_NC_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_NC_Msk; + tmp |= SDRAMC_CR_NC(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_NC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_NC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_NC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_NC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_NC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_NC_Msk) >> SDRAMC_CR_NC_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_NR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_NR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_NR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_NR(mask)) >> SDRAMC_CR_NR_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_NR_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_NR_Msk; + tmp |= SDRAMC_CR_NR(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_NR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_NR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_NR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_NR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_NR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_NR_Msk) >> SDRAMC_CR_NR_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_CAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_CAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_CAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_CAS(mask)) >> SDRAMC_CR_CAS_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_CAS_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_CAS_Msk; + tmp |= SDRAMC_CR_CAS(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_CAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_CAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_CAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_CAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_CAS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_CAS_Msk) >> SDRAMC_CR_CAS_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TWR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TWR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TWR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TWR(mask)) >> SDRAMC_CR_TWR_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TWR_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TWR_Msk; + tmp |= SDRAMC_CR_TWR(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TWR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TWR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TWR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TWR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TWR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TWR_Msk) >> SDRAMC_CR_TWR_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TRC_TRFC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TRC_TRFC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TRC_TRFC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRC_TRFC(mask)) >> SDRAMC_CR_TRC_TRFC_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TRC_TRFC_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TRC_TRFC_Msk; + tmp |= SDRAMC_CR_TRC_TRFC(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TRC_TRFC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TRC_TRFC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TRC_TRFC_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TRC_TRFC(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TRC_TRFC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRC_TRFC_Msk) >> SDRAMC_CR_TRC_TRFC_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TRP_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TRP(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TRP_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRP(mask)) >> SDRAMC_CR_TRP_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TRP_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TRP_Msk; + tmp |= SDRAMC_CR_TRP(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TRP_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TRP(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TRP_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TRP(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRP_Msk) >> SDRAMC_CR_TRP_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TRCD_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TRCD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TRCD_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRCD(mask)) >> SDRAMC_CR_TRCD_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TRCD_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TRCD_Msk; + tmp |= SDRAMC_CR_TRCD(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TRCD_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TRCD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TRCD_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TRCD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TRCD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRCD_Msk) >> SDRAMC_CR_TRCD_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TRAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TRAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TRAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRAS(mask)) >> SDRAMC_CR_TRAS_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TRAS_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TRAS_Msk; + tmp |= SDRAMC_CR_TRAS(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TRAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TRAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TRAS_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TRAS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TRAS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TRAS_Msk) >> SDRAMC_CR_TRAS_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_TXSR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= SDRAMC_CR_TXSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_TXSR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TXSR(mask)) >> SDRAMC_CR_TXSR_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CR_TXSR_bf(const void *const hw, hri_sdramc_cr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= ~SDRAMC_CR_TXSR_Msk; + tmp |= SDRAMC_CR_TXSR(data); + ((Sdramc *)hw)->SDRAMC_CR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_TXSR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~SDRAMC_CR_TXSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_TXSR_bf(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= SDRAMC_CR_TXSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_TXSR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp = (tmp & SDRAMC_CR_TXSR_Msk) >> SDRAMC_CR_TXSR_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CR_reg(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_get_CR_reg(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CR; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_CR_reg(const void *const hw, hri_sdramc_cr_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CR_reg(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CR_reg(const void *const hw, hri_sdramc_cr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CR ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cr_reg_t hri_sdramc_read_CR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_CR; +} + +static inline void hri_sdramc_set_LPR_LPCB_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= SDRAMC_LPR_LPCB(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_LPCB_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_LPCB(mask)) >> SDRAMC_LPR_LPCB_Pos; + return tmp; +} + +static inline void hri_sdramc_write_LPR_LPCB_bf(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= ~SDRAMC_LPR_LPCB_Msk; + tmp |= SDRAMC_LPR_LPCB(data); + ((Sdramc *)hw)->SDRAMC_LPR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_LPCB_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~SDRAMC_LPR_LPCB(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_LPCB_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= SDRAMC_LPR_LPCB(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_LPCB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_LPCB_Msk) >> SDRAMC_LPR_LPCB_Pos; + return tmp; +} + +static inline void hri_sdramc_set_LPR_PASR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= SDRAMC_LPR_PASR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_PASR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_PASR(mask)) >> SDRAMC_LPR_PASR_Pos; + return tmp; +} + +static inline void hri_sdramc_write_LPR_PASR_bf(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= ~SDRAMC_LPR_PASR_Msk; + tmp |= SDRAMC_LPR_PASR(data); + ((Sdramc *)hw)->SDRAMC_LPR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_PASR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~SDRAMC_LPR_PASR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_PASR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= SDRAMC_LPR_PASR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_PASR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_PASR_Msk) >> SDRAMC_LPR_PASR_Pos; + return tmp; +} + +static inline void hri_sdramc_set_LPR_TCSR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= SDRAMC_LPR_TCSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_TCSR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_TCSR(mask)) >> SDRAMC_LPR_TCSR_Pos; + return tmp; +} + +static inline void hri_sdramc_write_LPR_TCSR_bf(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= ~SDRAMC_LPR_TCSR_Msk; + tmp |= SDRAMC_LPR_TCSR(data); + ((Sdramc *)hw)->SDRAMC_LPR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_TCSR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~SDRAMC_LPR_TCSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_TCSR_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= SDRAMC_LPR_TCSR(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_TCSR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_TCSR_Msk) >> SDRAMC_LPR_TCSR_Pos; + return tmp; +} + +static inline void hri_sdramc_set_LPR_DS_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= SDRAMC_LPR_DS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_DS_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_DS(mask)) >> SDRAMC_LPR_DS_Pos; + return tmp; +} + +static inline void hri_sdramc_write_LPR_DS_bf(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= ~SDRAMC_LPR_DS_Msk; + tmp |= SDRAMC_LPR_DS(data); + ((Sdramc *)hw)->SDRAMC_LPR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_DS_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~SDRAMC_LPR_DS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_DS_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= SDRAMC_LPR_DS(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_DS_Msk) >> SDRAMC_LPR_DS_Pos; + return tmp; +} + +static inline void hri_sdramc_set_LPR_TIMEOUT_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= SDRAMC_LPR_TIMEOUT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_TIMEOUT_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_TIMEOUT(mask)) >> SDRAMC_LPR_TIMEOUT_Pos; + return tmp; +} + +static inline void hri_sdramc_write_LPR_TIMEOUT_bf(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= ~SDRAMC_LPR_TIMEOUT_Msk; + tmp |= SDRAMC_LPR_TIMEOUT(data); + ((Sdramc *)hw)->SDRAMC_LPR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_TIMEOUT_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~SDRAMC_LPR_TIMEOUT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_TIMEOUT_bf(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= SDRAMC_LPR_TIMEOUT(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_TIMEOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp = (tmp & SDRAMC_LPR_TIMEOUT_Msk) >> SDRAMC_LPR_TIMEOUT_Pos; + return tmp; +} + +static inline void hri_sdramc_set_LPR_reg(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_get_LPR_reg(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_LPR; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_LPR_reg(const void *const hw, hri_sdramc_lpr_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_LPR_reg(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_LPR_reg(const void *const hw, hri_sdramc_lpr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_LPR ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_lpr_reg_t hri_sdramc_read_LPR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_LPR; +} + +static inline void hri_sdramc_set_MDR_MD_bf(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR |= SDRAMC_MDR_MD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mdr_reg_t hri_sdramc_get_MDR_MD_bf(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MDR; + tmp = (tmp & SDRAMC_MDR_MD(mask)) >> SDRAMC_MDR_MD_Pos; + return tmp; +} + +static inline void hri_sdramc_write_MDR_MD_bf(const void *const hw, hri_sdramc_mdr_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_MDR; + tmp &= ~SDRAMC_MDR_MD_Msk; + tmp |= SDRAMC_MDR_MD(data); + ((Sdramc *)hw)->SDRAMC_MDR = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_MDR_MD_bf(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR &= ~SDRAMC_MDR_MD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_MDR_MD_bf(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR ^= SDRAMC_MDR_MD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mdr_reg_t hri_sdramc_read_MDR_MD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MDR; + tmp = (tmp & SDRAMC_MDR_MD_Msk) >> SDRAMC_MDR_MD_Pos; + return tmp; +} + +static inline void hri_sdramc_set_MDR_reg(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mdr_reg_t hri_sdramc_get_MDR_reg(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_MDR; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_MDR_reg(const void *const hw, hri_sdramc_mdr_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_MDR_reg(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_MDR_reg(const void *const hw, hri_sdramc_mdr_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_MDR ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_mdr_reg_t hri_sdramc_read_MDR_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_MDR; +} + +static inline void hri_sdramc_set_CFR1_UNAL_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdramc_get_CFR1_UNAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp = (tmp & SDRAMC_CFR1_UNAL) >> SDRAMC_CFR1_UNAL_Pos; + return (bool)tmp; +} + +static inline void hri_sdramc_write_CFR1_UNAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp &= ~SDRAMC_CFR1_UNAL; + tmp |= value << SDRAMC_CFR1_UNAL_Pos; + ((Sdramc *)hw)->SDRAMC_CFR1 = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CFR1_UNAL_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 &= ~SDRAMC_CFR1_UNAL; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CFR1_UNAL_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 ^= SDRAMC_CFR1_UNAL; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_set_CFR1_TMRD_bf(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 |= SDRAMC_CFR1_TMRD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cfr1_reg_t hri_sdramc_get_CFR1_TMRD_bf(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp = (tmp & SDRAMC_CFR1_TMRD(mask)) >> SDRAMC_CFR1_TMRD_Pos; + return tmp; +} + +static inline void hri_sdramc_write_CFR1_TMRD_bf(const void *const hw, hri_sdramc_cfr1_reg_t data) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp &= ~SDRAMC_CFR1_TMRD_Msk; + tmp |= SDRAMC_CFR1_TMRD(data); + ((Sdramc *)hw)->SDRAMC_CFR1 = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CFR1_TMRD_bf(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 &= ~SDRAMC_CFR1_TMRD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CFR1_TMRD_bf(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 ^= SDRAMC_CFR1_TMRD(mask); + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cfr1_reg_t hri_sdramc_read_CFR1_TMRD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp = (tmp & SDRAMC_CFR1_TMRD_Msk) >> SDRAMC_CFR1_TMRD_Pos; + return tmp; +} + +static inline void hri_sdramc_set_CFR1_reg(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cfr1_reg_t hri_sdramc_get_CFR1_reg(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_CFR1; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_CFR1_reg(const void *const hw, hri_sdramc_cfr1_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_CFR1_reg(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_CFR1_reg(const void *const hw, hri_sdramc_cfr1_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_CFR1 ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_cfr1_reg_t hri_sdramc_read_CFR1_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_CFR1; +} + +static inline void hri_sdramc_set_OCMS_SDR_SE_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS |= SDRAMC_OCMS_SDR_SE; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdramc_get_OCMS_SDR_SE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_OCMS; + tmp = (tmp & SDRAMC_OCMS_SDR_SE) >> SDRAMC_OCMS_SDR_SE_Pos; + return (bool)tmp; +} + +static inline void hri_sdramc_write_OCMS_SDR_SE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDRAMC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdramc *)hw)->SDRAMC_OCMS; + tmp &= ~SDRAMC_OCMS_SDR_SE; + tmp |= value << SDRAMC_OCMS_SDR_SE_Pos; + ((Sdramc *)hw)->SDRAMC_OCMS = tmp; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_OCMS_SDR_SE_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS &= ~SDRAMC_OCMS_SDR_SE; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_OCMS_SDR_SE_bit(const void *const hw) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS ^= SDRAMC_OCMS_SDR_SE; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_set_OCMS_reg(const void *const hw, hri_sdramc_ocms_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS |= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_ocms_reg_t hri_sdramc_get_OCMS_reg(const void *const hw, hri_sdramc_ocms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdramc *)hw)->SDRAMC_OCMS; + tmp &= mask; + return tmp; +} + +static inline void hri_sdramc_write_OCMS_reg(const void *const hw, hri_sdramc_ocms_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_clear_OCMS_reg(const void *const hw, hri_sdramc_ocms_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS &= ~mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_toggle_OCMS_reg(const void *const hw, hri_sdramc_ocms_reg_t mask) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS ^= mask; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdramc_ocms_reg_t hri_sdramc_read_OCMS_reg(const void *const hw) +{ + return ((Sdramc *)hw)->SDRAMC_OCMS; +} + +static inline void hri_sdramc_write_OCMS_KEY1_reg(const void *const hw, hri_sdramc_ocms_key1_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS_KEY1 = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdramc_write_OCMS_KEY2_reg(const void *const hw, hri_sdramc_ocms_key2_reg_t data) +{ + SDRAMC_CRITICAL_SECTION_ENTER(); + ((Sdramc *)hw)->SDRAMC_OCMS_KEY2 = data; + SDRAMC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDRAMC_E70B_H_INCLUDED */ +#endif /* _SAME70_SDRAMC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_smc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_smc_e70b.h new file mode 100644 index 0000000000..038f2e9a15 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_smc_e70b.h @@ -0,0 +1,2608 @@ +/** + * \file + * + * \brief SAM SMC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_SMC_COMPONENT_ +#ifndef _HRI_SMC_E70B_H_INCLUDED_ +#define _HRI_SMC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SMC_CRITICAL_SECTIONS) +#define SMC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SMC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SMC_CRITICAL_SECTION_ENTER() +#define SMC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_smc_cycle_reg_t; +typedef uint32_t hri_smc_key1_reg_t; +typedef uint32_t hri_smc_key2_reg_t; +typedef uint32_t hri_smc_mode_reg_t; +typedef uint32_t hri_smc_ocms_reg_t; +typedef uint32_t hri_smc_pulse_reg_t; +typedef uint32_t hri_smc_setup_reg_t; +typedef uint32_t hri_smc_wpmr_reg_t; +typedef uint32_t hri_smc_wpsr_reg_t; +typedef uint32_t hri_smccs_number_cycle_reg_t; +typedef uint32_t hri_smccs_number_mode_reg_t; +typedef uint32_t hri_smccs_number_pulse_reg_t; +typedef uint32_t hri_smccs_number_setup_reg_t; + +static inline void hri_smccsnumber_set_SETUP_NWE_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP |= SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_get_SETUP_NWE_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NWE_SETUP(mask)) >> SMC_SETUP_NWE_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_SETUP_NWE_SETUP_bf(const void *const hw, hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp &= ~SMC_SETUP_NWE_SETUP_Msk; + tmp |= SMC_SETUP_NWE_SETUP(data); + ((SmcCsNumber *)hw)->SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_SETUP_NWE_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP &= ~SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_SETUP_NWE_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP ^= SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_read_SETUP_NWE_SETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NWE_SETUP_Msk) >> SMC_SETUP_NWE_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_SETUP_NCS_WR_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP |= SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_get_SETUP_NCS_WR_SETUP_bf(const void *const hw, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_WR_SETUP(mask)) >> SMC_SETUP_NCS_WR_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_SETUP_NCS_WR_SETUP_bf(const void *const hw, hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp &= ~SMC_SETUP_NCS_WR_SETUP_Msk; + tmp |= SMC_SETUP_NCS_WR_SETUP(data); + ((SmcCsNumber *)hw)->SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_SETUP_NCS_WR_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP &= ~SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_SETUP_NCS_WR_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP ^= SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_read_SETUP_NCS_WR_SETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_WR_SETUP_Msk) >> SMC_SETUP_NCS_WR_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_SETUP_NRD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP |= SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_get_SETUP_NRD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NRD_SETUP(mask)) >> SMC_SETUP_NRD_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_SETUP_NRD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp &= ~SMC_SETUP_NRD_SETUP_Msk; + tmp |= SMC_SETUP_NRD_SETUP(data); + ((SmcCsNumber *)hw)->SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_SETUP_NRD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP &= ~SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_SETUP_NRD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP ^= SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_read_SETUP_NRD_SETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NRD_SETUP_Msk) >> SMC_SETUP_NRD_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_SETUP_NCS_RD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP |= SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_get_SETUP_NCS_RD_SETUP_bf(const void *const hw, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_RD_SETUP(mask)) >> SMC_SETUP_NCS_RD_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_SETUP_NCS_RD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp &= ~SMC_SETUP_NCS_RD_SETUP_Msk; + tmp |= SMC_SETUP_NCS_RD_SETUP(data); + ((SmcCsNumber *)hw)->SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_SETUP_NCS_RD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP &= ~SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_SETUP_NCS_RD_SETUP_bf(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP ^= SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_read_SETUP_NCS_RD_SETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_RD_SETUP_Msk) >> SMC_SETUP_NCS_RD_SETUP_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_SETUP_reg(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_get_SETUP_reg(const void *const hw, hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_SETUP; + tmp &= mask; + return tmp; +} + +static inline void hri_smccsnumber_write_SETUP_reg(const void *const hw, hri_smc_setup_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_SETUP_reg(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_SETUP_reg(const void *const hw, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_SETUP ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smccsnumber_read_SETUP_reg(const void *const hw) +{ + return ((SmcCsNumber *)hw)->SMC_SETUP; +} + +static inline void hri_smccsnumber_set_PULSE_NWE_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE |= SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_get_PULSE_NWE_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NWE_PULSE(mask)) >> SMC_PULSE_NWE_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_PULSE_NWE_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp &= ~SMC_PULSE_NWE_PULSE_Msk; + tmp |= SMC_PULSE_NWE_PULSE(data); + ((SmcCsNumber *)hw)->SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_PULSE_NWE_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE &= ~SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_PULSE_NWE_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE ^= SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_read_PULSE_NWE_PULSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NWE_PULSE_Msk) >> SMC_PULSE_NWE_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_PULSE_NCS_WR_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE |= SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_get_PULSE_NCS_WR_PULSE_bf(const void *const hw, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_WR_PULSE(mask)) >> SMC_PULSE_NCS_WR_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_PULSE_NCS_WR_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp &= ~SMC_PULSE_NCS_WR_PULSE_Msk; + tmp |= SMC_PULSE_NCS_WR_PULSE(data); + ((SmcCsNumber *)hw)->SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_PULSE_NCS_WR_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE &= ~SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_PULSE_NCS_WR_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE ^= SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_read_PULSE_NCS_WR_PULSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_WR_PULSE_Msk) >> SMC_PULSE_NCS_WR_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_PULSE_NRD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE |= SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_get_PULSE_NRD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NRD_PULSE(mask)) >> SMC_PULSE_NRD_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_PULSE_NRD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp &= ~SMC_PULSE_NRD_PULSE_Msk; + tmp |= SMC_PULSE_NRD_PULSE(data); + ((SmcCsNumber *)hw)->SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_PULSE_NRD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE &= ~SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_PULSE_NRD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE ^= SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_read_PULSE_NRD_PULSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NRD_PULSE_Msk) >> SMC_PULSE_NRD_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_PULSE_NCS_RD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE |= SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_get_PULSE_NCS_RD_PULSE_bf(const void *const hw, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_RD_PULSE(mask)) >> SMC_PULSE_NCS_RD_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_PULSE_NCS_RD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp &= ~SMC_PULSE_NCS_RD_PULSE_Msk; + tmp |= SMC_PULSE_NCS_RD_PULSE(data); + ((SmcCsNumber *)hw)->SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_PULSE_NCS_RD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE &= ~SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_PULSE_NCS_RD_PULSE_bf(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE ^= SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_read_PULSE_NCS_RD_PULSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_RD_PULSE_Msk) >> SMC_PULSE_NCS_RD_PULSE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_PULSE_reg(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_get_PULSE_reg(const void *const hw, hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_PULSE; + tmp &= mask; + return tmp; +} + +static inline void hri_smccsnumber_write_PULSE_reg(const void *const hw, hri_smc_pulse_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_PULSE_reg(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_PULSE_reg(const void *const hw, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_PULSE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smccsnumber_read_PULSE_reg(const void *const hw) +{ + return ((SmcCsNumber *)hw)->SMC_PULSE; +} + +static inline void hri_smccsnumber_set_CYCLE_NWE_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE |= SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_get_CYCLE_NWE_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NWE_CYCLE(mask)) >> SMC_CYCLE_NWE_CYCLE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_CYCLE_NWE_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp &= ~SMC_CYCLE_NWE_CYCLE_Msk; + tmp |= SMC_CYCLE_NWE_CYCLE(data); + ((SmcCsNumber *)hw)->SMC_CYCLE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_CYCLE_NWE_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE &= ~SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_CYCLE_NWE_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE ^= SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_read_CYCLE_NWE_CYCLE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NWE_CYCLE_Msk) >> SMC_CYCLE_NWE_CYCLE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_CYCLE_NRD_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE |= SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_get_CYCLE_NRD_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NRD_CYCLE(mask)) >> SMC_CYCLE_NRD_CYCLE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_CYCLE_NRD_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp &= ~SMC_CYCLE_NRD_CYCLE_Msk; + tmp |= SMC_CYCLE_NRD_CYCLE(data); + ((SmcCsNumber *)hw)->SMC_CYCLE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_CYCLE_NRD_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE &= ~SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_CYCLE_NRD_CYCLE_bf(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE ^= SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_read_CYCLE_NRD_CYCLE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NRD_CYCLE_Msk) >> SMC_CYCLE_NRD_CYCLE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_CYCLE_reg(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_get_CYCLE_reg(const void *const hw, hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_CYCLE; + tmp &= mask; + return tmp; +} + +static inline void hri_smccsnumber_write_CYCLE_reg(const void *const hw, hri_smc_cycle_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_CYCLE_reg(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_CYCLE_reg(const void *const hw, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_CYCLE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smccsnumber_read_CYCLE_reg(const void *const hw) +{ + return ((SmcCsNumber *)hw)->SMC_CYCLE; +} + +static inline void hri_smccsnumber_set_MODE_READ_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_READ_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_READ_MODE) >> SMC_MODE_READ_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_READ_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_READ_MODE; + tmp |= value << SMC_MODE_READ_MODE_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_READ_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_READ_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_WRITE_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_WRITE_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_WRITE_MODE) >> SMC_MODE_WRITE_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_WRITE_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_WRITE_MODE; + tmp |= value << SMC_MODE_WRITE_MODE_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_WRITE_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_WRITE_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_BAT_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_BAT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_BAT) >> SMC_MODE_BAT_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_BAT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_BAT; + tmp |= value << SMC_MODE_BAT_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_BAT_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_BAT_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_DBW_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_DBW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_DBW) >> SMC_MODE_DBW_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_DBW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_DBW; + tmp |= value << SMC_MODE_DBW_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_DBW_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_DBW_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_TDF_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_TDF_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_MODE) >> SMC_MODE_TDF_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_TDF_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_TDF_MODE; + tmp |= value << SMC_MODE_TDF_MODE_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_TDF_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_TDF_MODE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_PMEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smccsnumber_get_MODE_PMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_PMEN) >> SMC_MODE_PMEN_Pos; + return (bool)tmp; +} + +static inline void hri_smccsnumber_write_MODE_PMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_PMEN; + tmp |= value << SMC_MODE_PMEN_Pos; + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_PMEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_PMEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_set_MODE_EXNW_MODE_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_get_MODE_EXNW_MODE_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_EXNW_MODE(mask)) >> SMC_MODE_EXNW_MODE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_MODE_EXNW_MODE_bf(const void *const hw, hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_EXNW_MODE_Msk; + tmp |= SMC_MODE_EXNW_MODE(data); + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_EXNW_MODE_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_EXNW_MODE_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_read_MODE_EXNW_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_EXNW_MODE_Msk) >> SMC_MODE_EXNW_MODE_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_MODE_TDF_CYCLES_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_get_MODE_TDF_CYCLES_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_CYCLES(mask)) >> SMC_MODE_TDF_CYCLES_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_MODE_TDF_CYCLES_bf(const void *const hw, hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_TDF_CYCLES_Msk; + tmp |= SMC_MODE_TDF_CYCLES(data); + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_TDF_CYCLES_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_TDF_CYCLES_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_read_MODE_TDF_CYCLES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_CYCLES_Msk) >> SMC_MODE_TDF_CYCLES_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_MODE_PS_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_get_MODE_PS_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_PS(mask)) >> SMC_MODE_PS_Pos; + return tmp; +} + +static inline void hri_smccsnumber_write_MODE_PS_bf(const void *const hw, hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= ~SMC_MODE_PS_Msk; + tmp |= SMC_MODE_PS(data); + ((SmcCsNumber *)hw)->SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_PS_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_PS_bf(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_read_MODE_PS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp = (tmp & SMC_MODE_PS_Msk) >> SMC_MODE_PS_Pos; + return tmp; +} + +static inline void hri_smccsnumber_set_MODE_reg(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_get_MODE_reg(const void *const hw, hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((SmcCsNumber *)hw)->SMC_MODE; + tmp &= mask; + return tmp; +} + +static inline void hri_smccsnumber_write_MODE_reg(const void *const hw, hri_smc_mode_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_clear_MODE_reg(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smccsnumber_toggle_MODE_reg(const void *const hw, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((SmcCsNumber *)hw)->SMC_MODE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smccsnumber_read_MODE_reg(const void *const hw) +{ + return ((SmcCsNumber *)hw)->SMC_MODE; +} + +static inline void hri_smc_set_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP |= SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_get_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NWE_SETUP(mask)) >> SMC_SETUP_NWE_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_write_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp &= ~SMC_SETUP_NWE_SETUP_Msk; + tmp |= SMC_SETUP_NWE_SETUP(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP &= ~SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP ^= SMC_SETUP_NWE_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_read_SETUP_NWE_SETUP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NWE_SETUP_Msk) >> SMC_SETUP_NWE_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_set_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP |= SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_get_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_WR_SETUP(mask)) >> SMC_SETUP_NCS_WR_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_write_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp &= ~SMC_SETUP_NCS_WR_SETUP_Msk; + tmp |= SMC_SETUP_NCS_WR_SETUP(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP &= ~SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP ^= SMC_SETUP_NCS_WR_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_read_SETUP_NCS_WR_SETUP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_WR_SETUP_Msk) >> SMC_SETUP_NCS_WR_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_set_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP |= SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_get_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NRD_SETUP(mask)) >> SMC_SETUP_NRD_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_write_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp &= ~SMC_SETUP_NRD_SETUP_Msk; + tmp |= SMC_SETUP_NRD_SETUP(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP &= ~SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP ^= SMC_SETUP_NRD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_read_SETUP_NRD_SETUP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NRD_SETUP_Msk) >> SMC_SETUP_NRD_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_set_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP |= SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_get_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_RD_SETUP(mask)) >> SMC_SETUP_NCS_RD_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_write_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp &= ~SMC_SETUP_NCS_RD_SETUP_Msk; + tmp |= SMC_SETUP_NCS_RD_SETUP(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP &= ~SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP ^= SMC_SETUP_NCS_RD_SETUP(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_read_SETUP_NCS_RD_SETUP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp = (tmp & SMC_SETUP_NCS_RD_SETUP_Msk) >> SMC_SETUP_NCS_RD_SETUP_Pos; + return tmp; +} + +static inline void hri_smc_set_SETUP_reg(const void *const hw, uint8_t submodule_index, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_get_SETUP_reg(const void *const hw, uint8_t submodule_index, + hri_smc_setup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_SETUP_reg(const void *const hw, uint8_t submodule_index, hri_smc_setup_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_SETUP_reg(const void *const hw, uint8_t submodule_index, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_SETUP_reg(const void *const hw, uint8_t submodule_index, hri_smc_setup_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_setup_reg_t hri_smc_read_SETUP_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_SETUP; +} + +static inline void hri_smc_set_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE |= SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_get_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NWE_PULSE(mask)) >> SMC_PULSE_NWE_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_write_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp &= ~SMC_PULSE_NWE_PULSE_Msk; + tmp |= SMC_PULSE_NWE_PULSE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE &= ~SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE ^= SMC_PULSE_NWE_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_read_PULSE_NWE_PULSE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NWE_PULSE_Msk) >> SMC_PULSE_NWE_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_set_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE |= SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_get_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_WR_PULSE(mask)) >> SMC_PULSE_NCS_WR_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_write_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp &= ~SMC_PULSE_NCS_WR_PULSE_Msk; + tmp |= SMC_PULSE_NCS_WR_PULSE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE &= ~SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE ^= SMC_PULSE_NCS_WR_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_read_PULSE_NCS_WR_PULSE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_WR_PULSE_Msk) >> SMC_PULSE_NCS_WR_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_set_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE |= SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_get_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NRD_PULSE(mask)) >> SMC_PULSE_NRD_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_write_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp &= ~SMC_PULSE_NRD_PULSE_Msk; + tmp |= SMC_PULSE_NRD_PULSE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE &= ~SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE ^= SMC_PULSE_NRD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_read_PULSE_NRD_PULSE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NRD_PULSE_Msk) >> SMC_PULSE_NRD_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_set_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE |= SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_get_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_RD_PULSE(mask)) >> SMC_PULSE_NCS_RD_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_write_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp &= ~SMC_PULSE_NCS_RD_PULSE_Msk; + tmp |= SMC_PULSE_NCS_RD_PULSE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE &= ~SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE ^= SMC_PULSE_NCS_RD_PULSE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_read_PULSE_NCS_RD_PULSE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp = (tmp & SMC_PULSE_NCS_RD_PULSE_Msk) >> SMC_PULSE_NCS_RD_PULSE_Pos; + return tmp; +} + +static inline void hri_smc_set_PULSE_reg(const void *const hw, uint8_t submodule_index, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_get_PULSE_reg(const void *const hw, uint8_t submodule_index, + hri_smc_pulse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_PULSE_reg(const void *const hw, uint8_t submodule_index, hri_smc_pulse_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_PULSE_reg(const void *const hw, uint8_t submodule_index, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_PULSE_reg(const void *const hw, uint8_t submodule_index, hri_smc_pulse_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_pulse_reg_t hri_smc_read_PULSE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_PULSE; +} + +static inline void hri_smc_set_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE |= SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_get_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NWE_CYCLE(mask)) >> SMC_CYCLE_NWE_CYCLE_Pos; + return tmp; +} + +static inline void hri_smc_write_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp &= ~SMC_CYCLE_NWE_CYCLE_Msk; + tmp |= SMC_CYCLE_NWE_CYCLE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE &= ~SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE ^= SMC_CYCLE_NWE_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_read_CYCLE_NWE_CYCLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NWE_CYCLE_Msk) >> SMC_CYCLE_NWE_CYCLE_Pos; + return tmp; +} + +static inline void hri_smc_set_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE |= SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_get_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NRD_CYCLE(mask)) >> SMC_CYCLE_NRD_CYCLE_Pos; + return tmp; +} + +static inline void hri_smc_write_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp &= ~SMC_CYCLE_NRD_CYCLE_Msk; + tmp |= SMC_CYCLE_NRD_CYCLE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE &= ~SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE ^= SMC_CYCLE_NRD_CYCLE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_read_CYCLE_NRD_CYCLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp = (tmp & SMC_CYCLE_NRD_CYCLE_Msk) >> SMC_CYCLE_NRD_CYCLE_Pos; + return tmp; +} + +static inline void hri_smc_set_CYCLE_reg(const void *const hw, uint8_t submodule_index, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_get_CYCLE_reg(const void *const hw, uint8_t submodule_index, + hri_smc_cycle_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_CYCLE_reg(const void *const hw, uint8_t submodule_index, hri_smc_cycle_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_CYCLE_reg(const void *const hw, uint8_t submodule_index, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_CYCLE_reg(const void *const hw, uint8_t submodule_index, hri_smc_cycle_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_cycle_reg_t hri_smc_read_CYCLE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_CYCLE; +} + +static inline void hri_smc_set_MODE_READ_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_READ_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_READ_MODE) >> SMC_MODE_READ_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_READ_MODE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_READ_MODE; + tmp |= value << SMC_MODE_READ_MODE_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_READ_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_READ_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_READ_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_WRITE_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_WRITE_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_WRITE_MODE) >> SMC_MODE_WRITE_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_WRITE_MODE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_WRITE_MODE; + tmp |= value << SMC_MODE_WRITE_MODE_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_WRITE_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_WRITE_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_WRITE_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_BAT_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_BAT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_BAT) >> SMC_MODE_BAT_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_BAT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_BAT; + tmp |= value << SMC_MODE_BAT_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_BAT_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_BAT_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_BAT; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_DBW_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_DBW_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_DBW) >> SMC_MODE_DBW_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_DBW_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_DBW; + tmp |= value << SMC_MODE_DBW_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_DBW_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_DBW_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_DBW; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_TDF_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_TDF_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_MODE) >> SMC_MODE_TDF_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_TDF_MODE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_TDF_MODE; + tmp |= value << SMC_MODE_TDF_MODE_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_TDF_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_TDF_MODE_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_TDF_MODE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_PMEN_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_MODE_PMEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_PMEN) >> SMC_MODE_PMEN_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_MODE_PMEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_PMEN; + tmp |= value << SMC_MODE_PMEN_Pos; + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_PMEN_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_PMEN_bit(const void *const hw, uint8_t submodule_index) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_PMEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_get_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_EXNW_MODE(mask)) >> SMC_MODE_EXNW_MODE_Pos; + return tmp; +} + +static inline void hri_smc_write_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_EXNW_MODE_Msk; + tmp |= SMC_MODE_EXNW_MODE(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_EXNW_MODE(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_read_MODE_EXNW_MODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_EXNW_MODE_Msk) >> SMC_MODE_EXNW_MODE_Pos; + return tmp; +} + +static inline void hri_smc_set_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_get_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_CYCLES(mask)) >> SMC_MODE_TDF_CYCLES_Pos; + return tmp; +} + +static inline void hri_smc_write_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_TDF_CYCLES_Msk; + tmp |= SMC_MODE_TDF_CYCLES(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_TDF_CYCLES(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_read_MODE_TDF_CYCLES_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_TDF_CYCLES_Msk) >> SMC_MODE_TDF_CYCLES_Pos; + return tmp; +} + +static inline void hri_smc_set_MODE_PS_bf(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_get_MODE_PS_bf(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_PS(mask)) >> SMC_MODE_PS_Pos; + return tmp; +} + +static inline void hri_smc_write_MODE_PS_bf(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= ~SMC_MODE_PS_Msk; + tmp |= SMC_MODE_PS(data); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_PS_bf(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_PS_bf(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= SMC_MODE_PS(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_read_MODE_PS_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp = (tmp & SMC_MODE_PS_Msk) >> SMC_MODE_PS_Pos; + return tmp; +} + +static inline void hri_smc_set_MODE_reg(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_get_MODE_reg(const void *const hw, uint8_t submodule_index, + hri_smc_mode_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_MODE_reg(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_MODE_reg(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_MODE_reg(const void *const hw, uint8_t submodule_index, hri_smc_mode_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_mode_reg_t hri_smc_read_MODE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Smc *)hw)->SmcCsNumber[submodule_index].SMC_MODE; +} + +static inline bool hri_smc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Smc *)hw)->SMC_WPSR & SMC_WPSR_WPVS) > 0; +} + +static inline hri_smc_wpsr_reg_t hri_smc_get_WPSR_WPVSRC_bf(const void *const hw, hri_smc_wpsr_reg_t mask) +{ + return (((Smc *)hw)->SMC_WPSR & SMC_WPSR_WPVSRC(mask)) >> SMC_WPSR_WPVSRC_Pos; +} + +static inline hri_smc_wpsr_reg_t hri_smc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Smc *)hw)->SMC_WPSR & SMC_WPSR_WPVSRC_Msk) >> SMC_WPSR_WPVSRC_Pos; +} + +static inline hri_smc_wpsr_reg_t hri_smc_get_WPSR_reg(const void *const hw, hri_smc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_smc_wpsr_reg_t hri_smc_read_WPSR_reg(const void *const hw) +{ + return ((Smc *)hw)->SMC_WPSR; +} + +static inline void hri_smc_set_OCMS_SMSE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= SMC_OCMS_SMSE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_OCMS_SMSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp = (tmp & SMC_OCMS_SMSE) >> SMC_OCMS_SMSE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_OCMS_SMSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= ~SMC_OCMS_SMSE; + tmp |= value << SMC_OCMS_SMSE_Pos; + ((Smc *)hw)->SMC_OCMS = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_SMSE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~SMC_OCMS_SMSE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_SMSE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= SMC_OCMS_SMSE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_OCMS_CS0SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= SMC_OCMS_CS0SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_OCMS_CS0SE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp = (tmp & SMC_OCMS_CS0SE) >> SMC_OCMS_CS0SE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_OCMS_CS0SE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= ~SMC_OCMS_CS0SE; + tmp |= value << SMC_OCMS_CS0SE_Pos; + ((Smc *)hw)->SMC_OCMS = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_CS0SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~SMC_OCMS_CS0SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_CS0SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= SMC_OCMS_CS0SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_OCMS_CS1SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= SMC_OCMS_CS1SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_OCMS_CS1SE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp = (tmp & SMC_OCMS_CS1SE) >> SMC_OCMS_CS1SE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_OCMS_CS1SE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= ~SMC_OCMS_CS1SE; + tmp |= value << SMC_OCMS_CS1SE_Pos; + ((Smc *)hw)->SMC_OCMS = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_CS1SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~SMC_OCMS_CS1SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_CS1SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= SMC_OCMS_CS1SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_OCMS_CS2SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= SMC_OCMS_CS2SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_OCMS_CS2SE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp = (tmp & SMC_OCMS_CS2SE) >> SMC_OCMS_CS2SE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_OCMS_CS2SE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= ~SMC_OCMS_CS2SE; + tmp |= value << SMC_OCMS_CS2SE_Pos; + ((Smc *)hw)->SMC_OCMS = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_CS2SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~SMC_OCMS_CS2SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_CS2SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= SMC_OCMS_CS2SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_OCMS_CS3SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= SMC_OCMS_CS3SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_OCMS_CS3SE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp = (tmp & SMC_OCMS_CS3SE) >> SMC_OCMS_CS3SE_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_OCMS_CS3SE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= ~SMC_OCMS_CS3SE; + tmp |= value << SMC_OCMS_CS3SE_Pos; + ((Smc *)hw)->SMC_OCMS = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_CS3SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~SMC_OCMS_CS3SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_CS3SE_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= SMC_OCMS_CS3SE; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_OCMS_reg(const void *const hw, hri_smc_ocms_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_ocms_reg_t hri_smc_get_OCMS_reg(const void *const hw, hri_smc_ocms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_OCMS; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_OCMS_reg(const void *const hw, hri_smc_ocms_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_OCMS_reg(const void *const hw, hri_smc_ocms_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_OCMS_reg(const void *const hw, hri_smc_ocms_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_OCMS ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_ocms_reg_t hri_smc_read_OCMS_reg(const void *const hw) +{ + return ((Smc *)hw)->SMC_OCMS; +} + +static inline void hri_smc_set_WPMR_WPEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR |= SMC_WPMR_WPEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_smc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_WPMR; + tmp = (tmp & SMC_WPMR_WPEN) >> SMC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_smc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_WPMR; + tmp &= ~SMC_WPMR_WPEN; + tmp |= value << SMC_WPMR_WPEN_Pos; + ((Smc *)hw)->SMC_WPMR = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_WPMR_WPEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR &= ~SMC_WPMR_WPEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR ^= SMC_WPMR_WPEN; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_set_WPMR_WPKEY_bf(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR |= SMC_WPMR_WPKEY(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_wpmr_reg_t hri_smc_get_WPMR_WPKEY_bf(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_WPMR; + tmp = (tmp & SMC_WPMR_WPKEY(mask)) >> SMC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_smc_write_WPMR_WPKEY_bf(const void *const hw, hri_smc_wpmr_reg_t data) +{ + uint32_t tmp; + SMC_CRITICAL_SECTION_ENTER(); + tmp = ((Smc *)hw)->SMC_WPMR; + tmp &= ~SMC_WPMR_WPKEY_Msk; + tmp |= SMC_WPMR_WPKEY(data); + ((Smc *)hw)->SMC_WPMR = tmp; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_WPMR_WPKEY_bf(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR &= ~SMC_WPMR_WPKEY(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR ^= SMC_WPMR_WPKEY(mask); + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_wpmr_reg_t hri_smc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_WPMR; + tmp = (tmp & SMC_WPMR_WPKEY_Msk) >> SMC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_smc_set_WPMR_reg(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR |= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_wpmr_reg_t hri_smc_get_WPMR_reg(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Smc *)hw)->SMC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_smc_write_WPMR_reg(const void *const hw, hri_smc_wpmr_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_clear_WPMR_reg(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR &= ~mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_toggle_WPMR_reg(const void *const hw, hri_smc_wpmr_reg_t mask) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_WPMR ^= mask; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_smc_wpmr_reg_t hri_smc_read_WPMR_reg(const void *const hw) +{ + return ((Smc *)hw)->SMC_WPMR; +} + +static inline void hri_smc_write_KEY1_reg(const void *const hw, hri_smc_key1_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_KEY1 = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_smc_write_KEY2_reg(const void *const hw, hri_smc_key2_reg_t data) +{ + SMC_CRITICAL_SECTION_ENTER(); + ((Smc *)hw)->SMC_KEY2 = data; + SMC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SMC_E70B_H_INCLUDED */ +#endif /* _SAME70_SMC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_spi_e70b.h b/bsp/microchip/same70/bsp/hri/hri_spi_e70b.h new file mode 100644 index 0000000000..d022f1532e --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_spi_e70b.h @@ -0,0 +1,1291 @@ +/** + * \file + * + * \brief SAM SPI + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_SPI_COMPONENT_ +#ifndef _HRI_SPI_E70B_H_INCLUDED_ +#define _HRI_SPI_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SPI_CRITICAL_SECTIONS) +#define SPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SPI_CRITICAL_SECTION_ENTER() +#define SPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_spi_cr_reg_t; +typedef uint32_t hri_spi_csr_reg_t; +typedef uint32_t hri_spi_imr_reg_t; +typedef uint32_t hri_spi_mr_reg_t; +typedef uint32_t hri_spi_rdr_reg_t; +typedef uint32_t hri_spi_sr_reg_t; +typedef uint32_t hri_spi_tdr_reg_t; +typedef uint32_t hri_spi_wpmr_reg_t; +typedef uint32_t hri_spi_wpsr_reg_t; + +static inline void hri_spi_set_IMR_RDRF_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_RDRF; +} + +static inline bool hri_spi_get_IMR_RDRF_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_RDRF) >> SPI_IMR_RDRF_Pos; +} + +static inline void hri_spi_write_IMR_RDRF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_RDRF; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_RDRF; + } +} + +static inline void hri_spi_clear_IMR_RDRF_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_RDRF; +} + +static inline void hri_spi_set_IMR_TDRE_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_TDRE; +} + +static inline bool hri_spi_get_IMR_TDRE_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_TDRE) >> SPI_IMR_TDRE_Pos; +} + +static inline void hri_spi_write_IMR_TDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_TDRE; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_TDRE; + } +} + +static inline void hri_spi_clear_IMR_TDRE_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_TDRE; +} + +static inline void hri_spi_set_IMR_MODF_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_MODF; +} + +static inline bool hri_spi_get_IMR_MODF_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_MODF) >> SPI_IMR_MODF_Pos; +} + +static inline void hri_spi_write_IMR_MODF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_MODF; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_MODF; + } +} + +static inline void hri_spi_clear_IMR_MODF_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_MODF; +} + +static inline void hri_spi_set_IMR_OVRES_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_OVRES; +} + +static inline bool hri_spi_get_IMR_OVRES_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_OVRES) >> SPI_IMR_OVRES_Pos; +} + +static inline void hri_spi_write_IMR_OVRES_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_OVRES; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_OVRES; + } +} + +static inline void hri_spi_clear_IMR_OVRES_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_OVRES; +} + +static inline void hri_spi_set_IMR_NSSR_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_NSSR; +} + +static inline bool hri_spi_get_IMR_NSSR_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_NSSR) >> SPI_IMR_NSSR_Pos; +} + +static inline void hri_spi_write_IMR_NSSR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_NSSR; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_NSSR; + } +} + +static inline void hri_spi_clear_IMR_NSSR_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_NSSR; +} + +static inline void hri_spi_set_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_TXEMPTY; +} + +static inline bool hri_spi_get_IMR_TXEMPTY_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_TXEMPTY) >> SPI_IMR_TXEMPTY_Pos; +} + +static inline void hri_spi_write_IMR_TXEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_TXEMPTY; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_TXEMPTY; + } +} + +static inline void hri_spi_clear_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_TXEMPTY; +} + +static inline void hri_spi_set_IMR_UNDES_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IER = SPI_IMR_UNDES; +} + +static inline bool hri_spi_get_IMR_UNDES_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_IMR & SPI_IMR_UNDES) >> SPI_IMR_UNDES_Pos; +} + +static inline void hri_spi_write_IMR_UNDES_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Spi *)hw)->SPI_IDR = SPI_IMR_UNDES; + } else { + ((Spi *)hw)->SPI_IER = SPI_IMR_UNDES; + } +} + +static inline void hri_spi_clear_IMR_UNDES_bit(const void *const hw) +{ + ((Spi *)hw)->SPI_IDR = SPI_IMR_UNDES; +} + +static inline void hri_spi_set_IMR_reg(const void *const hw, hri_spi_imr_reg_t mask) +{ + ((Spi *)hw)->SPI_IER = mask; +} + +static inline hri_spi_imr_reg_t hri_spi_get_IMR_reg(const void *const hw, hri_spi_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_spi_imr_reg_t hri_spi_read_IMR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_IMR; +} + +static inline void hri_spi_write_IMR_reg(const void *const hw, hri_spi_imr_reg_t data) +{ + ((Spi *)hw)->SPI_IER = data; + ((Spi *)hw)->SPI_IDR = ~data; +} + +static inline void hri_spi_clear_IMR_reg(const void *const hw, hri_spi_imr_reg_t mask) +{ + ((Spi *)hw)->SPI_IDR = mask; +} + +static inline hri_spi_rdr_reg_t hri_spi_get_RDR_RD_bf(const void *const hw, hri_spi_rdr_reg_t mask) +{ + return (((Spi *)hw)->SPI_RDR & SPI_RDR_RD(mask)) >> SPI_RDR_RD_Pos; +} + +static inline hri_spi_rdr_reg_t hri_spi_read_RDR_RD_bf(const void *const hw) +{ + return (((Spi *)hw)->SPI_RDR & SPI_RDR_RD_Msk) >> SPI_RDR_RD_Pos; +} + +static inline hri_spi_rdr_reg_t hri_spi_get_RDR_PCS_bf(const void *const hw, hri_spi_rdr_reg_t mask) +{ + return (((Spi *)hw)->SPI_RDR & SPI_RDR_PCS(mask)) >> SPI_RDR_PCS_Pos; +} + +static inline hri_spi_rdr_reg_t hri_spi_read_RDR_PCS_bf(const void *const hw) +{ + return (((Spi *)hw)->SPI_RDR & SPI_RDR_PCS_Msk) >> SPI_RDR_PCS_Pos; +} + +static inline hri_spi_rdr_reg_t hri_spi_get_RDR_reg(const void *const hw, hri_spi_rdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_RDR; + tmp &= mask; + return tmp; +} + +static inline hri_spi_rdr_reg_t hri_spi_read_RDR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_RDR; +} + +static inline bool hri_spi_get_SR_RDRF_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_RDRF) > 0; +} + +static inline bool hri_spi_get_SR_TDRE_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_TDRE) > 0; +} + +static inline bool hri_spi_get_SR_MODF_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_MODF) > 0; +} + +static inline bool hri_spi_get_SR_OVRES_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_OVRES) > 0; +} + +static inline bool hri_spi_get_SR_NSSR_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_NSSR) > 0; +} + +static inline bool hri_spi_get_SR_TXEMPTY_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_TXEMPTY) > 0; +} + +static inline bool hri_spi_get_SR_UNDES_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_UNDES) > 0; +} + +static inline bool hri_spi_get_SR_SPIENS_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_SR & SPI_SR_SPIENS) > 0; +} + +static inline hri_spi_sr_reg_t hri_spi_get_SR_reg(const void *const hw, hri_spi_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_SR; + tmp &= mask; + return tmp; +} + +static inline hri_spi_sr_reg_t hri_spi_read_SR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_SR; +} + +static inline bool hri_spi_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Spi *)hw)->SPI_WPSR & SPI_WPSR_WPVS) > 0; +} + +static inline hri_spi_wpsr_reg_t hri_spi_get_WPSR_WPVSRC_bf(const void *const hw, hri_spi_wpsr_reg_t mask) +{ + return (((Spi *)hw)->SPI_WPSR & SPI_WPSR_WPVSRC(mask)) >> SPI_WPSR_WPVSRC_Pos; +} + +static inline hri_spi_wpsr_reg_t hri_spi_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Spi *)hw)->SPI_WPSR & SPI_WPSR_WPVSRC_Msk) >> SPI_WPSR_WPVSRC_Pos; +} + +static inline hri_spi_wpsr_reg_t hri_spi_get_WPSR_reg(const void *const hw, hri_spi_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_spi_wpsr_reg_t hri_spi_read_WPSR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_WPSR; +} + +static inline void hri_spi_set_MR_MSTR_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_MSTR; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_MSTR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_MSTR) >> SPI_MR_MSTR_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_MSTR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_MSTR; + tmp |= value << SPI_MR_MSTR_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_MSTR_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_MSTR; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_MSTR_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_MSTR; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_PS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_PS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_PS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_PS) >> SPI_MR_PS_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_PS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_PS; + tmp |= value << SPI_MR_PS_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_PS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_PS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_PS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_PS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_PCSDEC_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_PCSDEC; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_PCSDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_PCSDEC) >> SPI_MR_PCSDEC_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_PCSDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_PCSDEC; + tmp |= value << SPI_MR_PCSDEC_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_PCSDEC_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_PCSDEC; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_PCSDEC_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_PCSDEC; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_MODFDIS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_MODFDIS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_MODFDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_MODFDIS) >> SPI_MR_MODFDIS_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_MODFDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_MODFDIS; + tmp |= value << SPI_MR_MODFDIS_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_MODFDIS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_MODFDIS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_MODFDIS_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_MODFDIS; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_WDRBT_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_WDRBT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_WDRBT) >> SPI_MR_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_WDRBT; + tmp |= value << SPI_MR_WDRBT_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_WDRBT_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_WDRBT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_WDRBT_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_WDRBT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_LLB_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_LLB; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_MR_LLB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_LLB) >> SPI_MR_LLB_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_MR_LLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_LLB; + tmp |= value << SPI_MR_LLB_Pos; + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_LLB_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_LLB; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_LLB_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_LLB; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_MR_PCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_PCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_get_MR_PCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_PCS(mask)) >> SPI_MR_PCS_Pos; + return tmp; +} + +static inline void hri_spi_write_MR_PCS_bf(const void *const hw, hri_spi_mr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_PCS_Msk; + tmp |= SPI_MR_PCS(data); + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_PCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_PCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_PCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_PCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_read_MR_PCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_PCS_Msk) >> SPI_MR_PCS_Pos; + return tmp; +} + +static inline void hri_spi_set_MR_DLYBCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= SPI_MR_DLYBCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_get_MR_DLYBCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_DLYBCS(mask)) >> SPI_MR_DLYBCS_Pos; + return tmp; +} + +static inline void hri_spi_write_MR_DLYBCS_bf(const void *const hw, hri_spi_mr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_MR; + tmp &= ~SPI_MR_DLYBCS_Msk; + tmp |= SPI_MR_DLYBCS(data); + ((Spi *)hw)->SPI_MR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_DLYBCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~SPI_MR_DLYBCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_DLYBCS_bf(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= SPI_MR_DLYBCS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_read_MR_DLYBCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp = (tmp & SPI_MR_DLYBCS_Msk) >> SPI_MR_DLYBCS_Pos; + return tmp; +} + +static inline void hri_spi_set_MR_reg(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR |= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_get_MR_reg(const void *const hw, hri_spi_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_spi_write_MR_reg(const void *const hw, hri_spi_mr_reg_t data) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR = data; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_MR_reg(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR &= ~mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_MR_reg(const void *const hw, hri_spi_mr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_MR ^= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_mr_reg_t hri_spi_read_MR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_MR; +} + +static inline void hri_spi_set_CSR_CPOL_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_CPOL; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_CSR_CPOL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_CPOL) >> SPI_CSR_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_CSR_CPOL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_CPOL; + tmp |= value << SPI_CSR_CPOL_Pos; + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_CPOL_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_CPOL; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_CPOL_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_CPOL; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_CSR_NCPHA_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_NCPHA; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_CSR_NCPHA_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_NCPHA) >> SPI_CSR_NCPHA_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_CSR_NCPHA_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_NCPHA; + tmp |= value << SPI_CSR_NCPHA_Pos; + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_NCPHA_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_NCPHA; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_NCPHA_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_NCPHA; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_CSR_CSNAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_CSNAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_CSR_CSNAAT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_CSNAAT) >> SPI_CSR_CSNAAT_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_CSR_CSNAAT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_CSNAAT; + tmp |= value << SPI_CSR_CSNAAT_Pos; + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_CSNAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_CSNAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_CSNAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_CSNAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_CSR_CSAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_CSAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_CSR_CSAAT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_CSAAT) >> SPI_CSR_CSAAT_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_CSR_CSAAT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_CSAAT; + tmp |= value << SPI_CSR_CSAAT_Pos; + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_CSAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_CSAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_CSAAT_bit(const void *const hw, uint8_t index) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_CSAAT; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_CSR_BITS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_BITS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_get_CSR_BITS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_BITS(mask)) >> SPI_CSR_BITS_Pos; + return tmp; +} + +static inline void hri_spi_write_CSR_BITS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_BITS_Msk; + tmp |= SPI_CSR_BITS(data); + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_BITS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_BITS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_BITS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_BITS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_read_CSR_BITS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_BITS_Msk) >> SPI_CSR_BITS_Pos; + return tmp; +} + +static inline void hri_spi_set_CSR_SCBR_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_SCBR(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_get_CSR_SCBR_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_SCBR(mask)) >> SPI_CSR_SCBR_Pos; + return tmp; +} + +static inline void hri_spi_write_CSR_SCBR_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_SCBR_Msk; + tmp |= SPI_CSR_SCBR(data); + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_SCBR_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_SCBR(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_SCBR_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_SCBR(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_read_CSR_SCBR_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_SCBR_Msk) >> SPI_CSR_SCBR_Pos; + return tmp; +} + +static inline void hri_spi_set_CSR_DLYBS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_DLYBS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_get_CSR_DLYBS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_DLYBS(mask)) >> SPI_CSR_DLYBS_Pos; + return tmp; +} + +static inline void hri_spi_write_CSR_DLYBS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_DLYBS_Msk; + tmp |= SPI_CSR_DLYBS(data); + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_DLYBS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_DLYBS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_DLYBS_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_DLYBS(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_read_CSR_DLYBS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_DLYBS_Msk) >> SPI_CSR_DLYBS_Pos; + return tmp; +} + +static inline void hri_spi_set_CSR_DLYBCT_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= SPI_CSR_DLYBCT(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_get_CSR_DLYBCT_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_DLYBCT(mask)) >> SPI_CSR_DLYBCT_Pos; + return tmp; +} + +static inline void hri_spi_write_CSR_DLYBCT_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= ~SPI_CSR_DLYBCT_Msk; + tmp |= SPI_CSR_DLYBCT(data); + ((Spi *)hw)->SPI_CSR[index] = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_DLYBCT_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~SPI_CSR_DLYBCT(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_DLYBCT_bf(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= SPI_CSR_DLYBCT(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_read_CSR_DLYBCT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp = (tmp & SPI_CSR_DLYBCT_Msk) >> SPI_CSR_DLYBCT_Pos; + return tmp; +} + +static inline void hri_spi_set_CSR_reg(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] |= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_get_CSR_reg(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_CSR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_spi_write_CSR_reg(const void *const hw, uint8_t index, hri_spi_csr_reg_t data) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] = data; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_CSR_reg(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] &= ~mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_CSR_reg(const void *const hw, uint8_t index, hri_spi_csr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CSR[index] ^= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_csr_reg_t hri_spi_read_CSR_reg(const void *const hw, uint8_t index) +{ + return ((Spi *)hw)->SPI_CSR[index]; +} + +static inline void hri_spi_set_WPMR_WPEN_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR |= SPI_WPMR_WPEN; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_spi_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_WPMR; + tmp = (tmp & SPI_WPMR_WPEN) >> SPI_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_spi_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_WPMR; + tmp &= ~SPI_WPMR_WPEN; + tmp |= value << SPI_WPMR_WPEN_Pos; + ((Spi *)hw)->SPI_WPMR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_WPMR_WPEN_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR &= ~SPI_WPMR_WPEN; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_WPMR_WPEN_bit(const void *const hw) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR ^= SPI_WPMR_WPEN; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_set_WPMR_WPKEY_bf(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR |= SPI_WPMR_WPKEY(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_wpmr_reg_t hri_spi_get_WPMR_WPKEY_bf(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_WPMR; + tmp = (tmp & SPI_WPMR_WPKEY(mask)) >> SPI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_spi_write_WPMR_WPKEY_bf(const void *const hw, hri_spi_wpmr_reg_t data) +{ + uint32_t tmp; + SPI_CRITICAL_SECTION_ENTER(); + tmp = ((Spi *)hw)->SPI_WPMR; + tmp &= ~SPI_WPMR_WPKEY_Msk; + tmp |= SPI_WPMR_WPKEY(data); + ((Spi *)hw)->SPI_WPMR = tmp; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_WPMR_WPKEY_bf(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR &= ~SPI_WPMR_WPKEY(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_WPMR_WPKEY_bf(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR ^= SPI_WPMR_WPKEY(mask); + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_wpmr_reg_t hri_spi_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_WPMR; + tmp = (tmp & SPI_WPMR_WPKEY_Msk) >> SPI_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_spi_set_WPMR_reg(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR |= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_wpmr_reg_t hri_spi_get_WPMR_reg(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Spi *)hw)->SPI_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_spi_write_WPMR_reg(const void *const hw, hri_spi_wpmr_reg_t data) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR = data; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_clear_WPMR_reg(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR &= ~mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_toggle_WPMR_reg(const void *const hw, hri_spi_wpmr_reg_t mask) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_WPMR ^= mask; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_spi_wpmr_reg_t hri_spi_read_WPMR_reg(const void *const hw) +{ + return ((Spi *)hw)->SPI_WPMR; +} + +static inline void hri_spi_write_CR_reg(const void *const hw, hri_spi_cr_reg_t data) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_CR = data; + SPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_spi_write_TDR_reg(const void *const hw, hri_spi_tdr_reg_t data) +{ + SPI_CRITICAL_SECTION_ENTER(); + ((Spi *)hw)->SPI_TDR = data; + SPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SPI_E70B_H_INCLUDED */ +#endif /* _SAME70_SPI_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_ssc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_ssc_e70b.h new file mode 100644 index 0000000000..9f2349c497 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_ssc_e70b.h @@ -0,0 +1,2551 @@ +/** + * \file + * + * \brief SAM SSC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_SSC_COMPONENT_ +#ifndef _HRI_SSC_E70B_H_INCLUDED_ +#define _HRI_SSC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SSC_CRITICAL_SECTIONS) +#define SSC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SSC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SSC_CRITICAL_SECTION_ENTER() +#define SSC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ssc_cmr_reg_t; +typedef uint32_t hri_ssc_cr_reg_t; +typedef uint32_t hri_ssc_imr_reg_t; +typedef uint32_t hri_ssc_rc0r_reg_t; +typedef uint32_t hri_ssc_rc1r_reg_t; +typedef uint32_t hri_ssc_rcmr_reg_t; +typedef uint32_t hri_ssc_rfmr_reg_t; +typedef uint32_t hri_ssc_rhr_reg_t; +typedef uint32_t hri_ssc_rshr_reg_t; +typedef uint32_t hri_ssc_sr_reg_t; +typedef uint32_t hri_ssc_tcmr_reg_t; +typedef uint32_t hri_ssc_tfmr_reg_t; +typedef uint32_t hri_ssc_thr_reg_t; +typedef uint32_t hri_ssc_tshr_reg_t; +typedef uint32_t hri_ssc_wpmr_reg_t; +typedef uint32_t hri_ssc_wpsr_reg_t; + +static inline void hri_ssc_set_IMR_TXRDY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXRDY; +} + +static inline bool hri_ssc_get_IMR_TXRDY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_TXRDY) >> SSC_IMR_TXRDY_Pos; +} + +static inline void hri_ssc_write_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXRDY; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXRDY; + } +} + +static inline void hri_ssc_clear_IMR_TXRDY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXRDY; +} + +static inline void hri_ssc_set_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXEMPTY; +} + +static inline bool hri_ssc_get_IMR_TXEMPTY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_TXEMPTY) >> SSC_IMR_TXEMPTY_Pos; +} + +static inline void hri_ssc_write_IMR_TXEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXEMPTY; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXEMPTY; + } +} + +static inline void hri_ssc_clear_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXEMPTY; +} + +static inline void hri_ssc_set_IMR_RXRDY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_RXRDY; +} + +static inline bool hri_ssc_get_IMR_RXRDY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_RXRDY) >> SSC_IMR_RXRDY_Pos; +} + +static inline void hri_ssc_write_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_RXRDY; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_RXRDY; + } +} + +static inline void hri_ssc_clear_IMR_RXRDY_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_RXRDY; +} + +static inline void hri_ssc_set_IMR_OVRUN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_OVRUN; +} + +static inline bool hri_ssc_get_IMR_OVRUN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_OVRUN) >> SSC_IMR_OVRUN_Pos; +} + +static inline void hri_ssc_write_IMR_OVRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_OVRUN; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_OVRUN; + } +} + +static inline void hri_ssc_clear_IMR_OVRUN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_OVRUN; +} + +static inline void hri_ssc_set_IMR_CP0_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_CP0; +} + +static inline bool hri_ssc_get_IMR_CP0_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_CP0) >> SSC_IMR_CP0_Pos; +} + +static inline void hri_ssc_write_IMR_CP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_CP0; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_CP0; + } +} + +static inline void hri_ssc_clear_IMR_CP0_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_CP0; +} + +static inline void hri_ssc_set_IMR_CP1_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_CP1; +} + +static inline bool hri_ssc_get_IMR_CP1_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_CP1) >> SSC_IMR_CP1_Pos; +} + +static inline void hri_ssc_write_IMR_CP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_CP1; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_CP1; + } +} + +static inline void hri_ssc_clear_IMR_CP1_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_CP1; +} + +static inline void hri_ssc_set_IMR_TXSYN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXSYN; +} + +static inline bool hri_ssc_get_IMR_TXSYN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_TXSYN) >> SSC_IMR_TXSYN_Pos; +} + +static inline void hri_ssc_write_IMR_TXSYN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXSYN; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_TXSYN; + } +} + +static inline void hri_ssc_clear_IMR_TXSYN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_TXSYN; +} + +static inline void hri_ssc_set_IMR_RXSYN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IER = SSC_IMR_RXSYN; +} + +static inline bool hri_ssc_get_IMR_RXSYN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_IMR & SSC_IMR_RXSYN) >> SSC_IMR_RXSYN_Pos; +} + +static inline void hri_ssc_write_IMR_RXSYN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ssc *)hw)->SSC_IDR = SSC_IMR_RXSYN; + } else { + ((Ssc *)hw)->SSC_IER = SSC_IMR_RXSYN; + } +} + +static inline void hri_ssc_clear_IMR_RXSYN_bit(const void *const hw) +{ + ((Ssc *)hw)->SSC_IDR = SSC_IMR_RXSYN; +} + +static inline void hri_ssc_set_IMR_reg(const void *const hw, hri_ssc_imr_reg_t mask) +{ + ((Ssc *)hw)->SSC_IER = mask; +} + +static inline hri_ssc_imr_reg_t hri_ssc_get_IMR_reg(const void *const hw, hri_ssc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_ssc_imr_reg_t hri_ssc_read_IMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_IMR; +} + +static inline void hri_ssc_write_IMR_reg(const void *const hw, hri_ssc_imr_reg_t data) +{ + ((Ssc *)hw)->SSC_IER = data; + ((Ssc *)hw)->SSC_IDR = ~data; +} + +static inline void hri_ssc_clear_IMR_reg(const void *const hw, hri_ssc_imr_reg_t mask) +{ + ((Ssc *)hw)->SSC_IDR = mask; +} + +static inline hri_ssc_rhr_reg_t hri_ssc_get_RHR_RDAT_bf(const void *const hw, hri_ssc_rhr_reg_t mask) +{ + return (((Ssc *)hw)->SSC_RHR & SSC_RHR_RDAT(mask)) >> SSC_RHR_RDAT_Pos; +} + +static inline hri_ssc_rhr_reg_t hri_ssc_read_RHR_RDAT_bf(const void *const hw) +{ + return (((Ssc *)hw)->SSC_RHR & SSC_RHR_RDAT_Msk) >> SSC_RHR_RDAT_Pos; +} + +static inline hri_ssc_rhr_reg_t hri_ssc_get_RHR_reg(const void *const hw, hri_ssc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RHR; + tmp &= mask; + return tmp; +} + +static inline hri_ssc_rhr_reg_t hri_ssc_read_RHR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RHR; +} + +static inline hri_ssc_rshr_reg_t hri_ssc_get_RSHR_RSDAT_bf(const void *const hw, hri_ssc_rshr_reg_t mask) +{ + return (((Ssc *)hw)->SSC_RSHR & SSC_RSHR_RSDAT(mask)) >> SSC_RSHR_RSDAT_Pos; +} + +static inline hri_ssc_rshr_reg_t hri_ssc_read_RSHR_RSDAT_bf(const void *const hw) +{ + return (((Ssc *)hw)->SSC_RSHR & SSC_RSHR_RSDAT_Msk) >> SSC_RSHR_RSDAT_Pos; +} + +static inline hri_ssc_rshr_reg_t hri_ssc_get_RSHR_reg(const void *const hw, hri_ssc_rshr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RSHR; + tmp &= mask; + return tmp; +} + +static inline hri_ssc_rshr_reg_t hri_ssc_read_RSHR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RSHR; +} + +static inline bool hri_ssc_get_SR_TXRDY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_TXRDY) > 0; +} + +static inline bool hri_ssc_get_SR_TXEMPTY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_TXEMPTY) > 0; +} + +static inline bool hri_ssc_get_SR_RXRDY_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_RXRDY) > 0; +} + +static inline bool hri_ssc_get_SR_OVRUN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_OVRUN) > 0; +} + +static inline bool hri_ssc_get_SR_CP0_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_CP0) > 0; +} + +static inline bool hri_ssc_get_SR_CP1_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_CP1) > 0; +} + +static inline bool hri_ssc_get_SR_TXSYN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_TXSYN) > 0; +} + +static inline bool hri_ssc_get_SR_RXSYN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_RXSYN) > 0; +} + +static inline bool hri_ssc_get_SR_TXEN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_TXEN) > 0; +} + +static inline bool hri_ssc_get_SR_RXEN_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_SR & SSC_SR_RXEN) > 0; +} + +static inline hri_ssc_sr_reg_t hri_ssc_get_SR_reg(const void *const hw, hri_ssc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_ssc_sr_reg_t hri_ssc_read_SR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_SR; +} + +static inline bool hri_ssc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Ssc *)hw)->SSC_WPSR & SSC_WPSR_WPVS) > 0; +} + +static inline hri_ssc_wpsr_reg_t hri_ssc_get_WPSR_WPVSRC_bf(const void *const hw, hri_ssc_wpsr_reg_t mask) +{ + return (((Ssc *)hw)->SSC_WPSR & SSC_WPSR_WPVSRC(mask)) >> SSC_WPSR_WPVSRC_Pos; +} + +static inline hri_ssc_wpsr_reg_t hri_ssc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Ssc *)hw)->SSC_WPSR & SSC_WPSR_WPVSRC_Msk) >> SSC_WPSR_WPVSRC_Pos; +} + +static inline hri_ssc_wpsr_reg_t hri_ssc_get_WPSR_reg(const void *const hw, hri_ssc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_ssc_wpsr_reg_t hri_ssc_read_WPSR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_WPSR; +} + +static inline void hri_ssc_set_CMR_DIV_bf(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR |= SSC_CMR_DIV(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_cmr_reg_t hri_ssc_get_CMR_DIV_bf(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_CMR; + tmp = (tmp & SSC_CMR_DIV(mask)) >> SSC_CMR_DIV_Pos; + return tmp; +} + +static inline void hri_ssc_write_CMR_DIV_bf(const void *const hw, hri_ssc_cmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_CMR; + tmp &= ~SSC_CMR_DIV_Msk; + tmp |= SSC_CMR_DIV(data); + ((Ssc *)hw)->SSC_CMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_CMR_DIV_bf(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR &= ~SSC_CMR_DIV(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_CMR_DIV_bf(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR ^= SSC_CMR_DIV(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_cmr_reg_t hri_ssc_read_CMR_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_CMR; + tmp = (tmp & SSC_CMR_DIV_Msk) >> SSC_CMR_DIV_Pos; + return tmp; +} + +static inline void hri_ssc_set_CMR_reg(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_cmr_reg_t hri_ssc_get_CMR_reg(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_CMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_CMR_reg(const void *const hw, hri_ssc_cmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_CMR_reg(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_CMR_reg(const void *const hw, hri_ssc_cmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_cmr_reg_t hri_ssc_read_CMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_CMR; +} + +static inline void hri_ssc_set_RCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_RCMR_CKI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKI) >> SSC_RCMR_CKI_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_RCMR_CKI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_CKI; + tmp |= value << SSC_RCMR_CKI_Pos; + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_RCMR_STOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_STOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_RCMR_STOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_STOP) >> SSC_RCMR_STOP_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_RCMR_STOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_STOP; + tmp |= value << SSC_RCMR_STOP_Pos; + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_STOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_STOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_STOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_STOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_RCMR_CKS_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_CKS_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKS(mask)) >> SSC_RCMR_CKS_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_CKS_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_CKS_Msk; + tmp |= SSC_RCMR_CKS(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_CKS_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_CKS_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_CKS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKS_Msk) >> SSC_RCMR_CKS_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_CKO_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_CKO_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKO(mask)) >> SSC_RCMR_CKO_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_CKO_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_CKO_Msk; + tmp |= SSC_RCMR_CKO(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_CKO_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_CKO_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_CKO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKO_Msk) >> SSC_RCMR_CKO_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_CKG_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_CKG_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKG(mask)) >> SSC_RCMR_CKG_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_CKG_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_CKG_Msk; + tmp |= SSC_RCMR_CKG(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_CKG_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_CKG_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_CKG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_CKG_Msk) >> SSC_RCMR_CKG_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_START_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_START_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_START(mask)) >> SSC_RCMR_START_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_START_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_START_Msk; + tmp |= SSC_RCMR_START(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_START_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_START_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_START_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_START_Msk) >> SSC_RCMR_START_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_STTDLY_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_STTDLY_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_STTDLY(mask)) >> SSC_RCMR_STTDLY_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_STTDLY_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_STTDLY_Msk; + tmp |= SSC_RCMR_STTDLY(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_STTDLY_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_STTDLY_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_STTDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_STTDLY_Msk) >> SSC_RCMR_STTDLY_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_PERIOD_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= SSC_RCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_PERIOD_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_PERIOD(mask)) >> SSC_RCMR_PERIOD_Pos; + return tmp; +} + +static inline void hri_ssc_write_RCMR_PERIOD_bf(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= ~SSC_RCMR_PERIOD_Msk; + tmp |= SSC_RCMR_PERIOD(data); + ((Ssc *)hw)->SSC_RCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_PERIOD_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~SSC_RCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_PERIOD_bf(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= SSC_RCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_PERIOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp = (tmp & SSC_RCMR_PERIOD_Msk) >> SSC_RCMR_PERIOD_Pos; + return tmp; +} + +static inline void hri_ssc_set_RCMR_reg(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_get_RCMR_reg(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RCMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_RCMR_reg(const void *const hw, hri_ssc_rcmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RCMR_reg(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RCMR_reg(const void *const hw, hri_ssc_rcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RCMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rcmr_reg_t hri_ssc_read_RCMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RCMR; +} + +static inline void hri_ssc_set_RFMR_LOOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_LOOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_RFMR_LOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_LOOP) >> SSC_RFMR_LOOP_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_RFMR_LOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_LOOP; + tmp |= value << SSC_RFMR_LOOP_Pos; + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_LOOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_LOOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_LOOP_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_LOOP; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_RFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_RFMR_MSBF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_MSBF) >> SSC_RFMR_MSBF_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_RFMR_MSBF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_MSBF; + tmp |= value << SSC_RFMR_MSBF_Pos; + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_RFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_RFMR_FSEDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSEDGE) >> SSC_RFMR_FSEDGE_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_RFMR_FSEDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_FSEDGE; + tmp |= value << SSC_RFMR_FSEDGE_Pos; + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_RFMR_DATLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_DATLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_DATLEN(mask)) >> SSC_RFMR_DATLEN_Pos; + return tmp; +} + +static inline void hri_ssc_write_RFMR_DATLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_DATLEN_Msk; + tmp |= SSC_RFMR_DATLEN(data); + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_DATLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_DATLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_DATLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_DATLEN_Msk) >> SSC_RFMR_DATLEN_Pos; + return tmp; +} + +static inline void hri_ssc_set_RFMR_DATNB_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_DATNB_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_DATNB(mask)) >> SSC_RFMR_DATNB_Pos; + return tmp; +} + +static inline void hri_ssc_write_RFMR_DATNB_bf(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_DATNB_Msk; + tmp |= SSC_RFMR_DATNB(data); + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_DATNB_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_DATNB_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_DATNB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_DATNB_Msk) >> SSC_RFMR_DATNB_Pos; + return tmp; +} + +static inline void hri_ssc_set_RFMR_FSLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_FSLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSLEN(mask)) >> SSC_RFMR_FSLEN_Pos; + return tmp; +} + +static inline void hri_ssc_write_RFMR_FSLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_FSLEN_Msk; + tmp |= SSC_RFMR_FSLEN(data); + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_FSLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_FSLEN_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_FSLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSLEN_Msk) >> SSC_RFMR_FSLEN_Pos; + return tmp; +} + +static inline void hri_ssc_set_RFMR_FSOS_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_FSOS_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSOS(mask)) >> SSC_RFMR_FSOS_Pos; + return tmp; +} + +static inline void hri_ssc_write_RFMR_FSOS_bf(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_FSOS_Msk; + tmp |= SSC_RFMR_FSOS(data); + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_FSOS_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_FSOS_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_FSOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSOS_Msk) >> SSC_RFMR_FSOS_Pos; + return tmp; +} + +static inline void hri_ssc_set_RFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= SSC_RFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSLEN_EXT(mask)) >> SSC_RFMR_FSLEN_EXT_Pos; + return tmp; +} + +static inline void hri_ssc_write_RFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= ~SSC_RFMR_FSLEN_EXT_Msk; + tmp |= SSC_RFMR_FSLEN_EXT(data); + ((Ssc *)hw)->SSC_RFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~SSC_RFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= SSC_RFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_FSLEN_EXT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp = (tmp & SSC_RFMR_FSLEN_EXT_Msk) >> SSC_RFMR_FSLEN_EXT_Pos; + return tmp; +} + +static inline void hri_ssc_set_RFMR_reg(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_get_RFMR_reg(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RFMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_RFMR_reg(const void *const hw, hri_ssc_rfmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RFMR_reg(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RFMR_reg(const void *const hw, hri_ssc_rfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RFMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rfmr_reg_t hri_ssc_read_RFMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RFMR; +} + +static inline void hri_ssc_set_TCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_TCMR_CKI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKI) >> SSC_TCMR_CKI_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_TCMR_CKI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_CKI; + tmp |= value << SSC_TCMR_CKI_Pos; + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_CKI_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_CKI; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_TCMR_CKS_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_CKS_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKS(mask)) >> SSC_TCMR_CKS_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_CKS_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_CKS_Msk; + tmp |= SSC_TCMR_CKS(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_CKS_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_CKS_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_CKS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_CKS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKS_Msk) >> SSC_TCMR_CKS_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_CKO_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_CKO_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKO(mask)) >> SSC_TCMR_CKO_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_CKO_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_CKO_Msk; + tmp |= SSC_TCMR_CKO(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_CKO_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_CKO_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_CKO(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_CKO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKO_Msk) >> SSC_TCMR_CKO_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_CKG_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_CKG_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKG(mask)) >> SSC_TCMR_CKG_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_CKG_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_CKG_Msk; + tmp |= SSC_TCMR_CKG(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_CKG_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_CKG_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_CKG(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_CKG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_CKG_Msk) >> SSC_TCMR_CKG_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_START_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_START_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_START(mask)) >> SSC_TCMR_START_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_START_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_START_Msk; + tmp |= SSC_TCMR_START(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_START_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_START_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_START(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_START_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_START_Msk) >> SSC_TCMR_START_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_STTDLY_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_STTDLY_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_STTDLY(mask)) >> SSC_TCMR_STTDLY_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_STTDLY_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_STTDLY_Msk; + tmp |= SSC_TCMR_STTDLY(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_STTDLY_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_STTDLY_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_STTDLY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_STTDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_STTDLY_Msk) >> SSC_TCMR_STTDLY_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_PERIOD_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= SSC_TCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_PERIOD_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_PERIOD(mask)) >> SSC_TCMR_PERIOD_Pos; + return tmp; +} + +static inline void hri_ssc_write_TCMR_PERIOD_bf(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= ~SSC_TCMR_PERIOD_Msk; + tmp |= SSC_TCMR_PERIOD(data); + ((Ssc *)hw)->SSC_TCMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_PERIOD_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~SSC_TCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_PERIOD_bf(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= SSC_TCMR_PERIOD(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_PERIOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp = (tmp & SSC_TCMR_PERIOD_Msk) >> SSC_TCMR_PERIOD_Pos; + return tmp; +} + +static inline void hri_ssc_set_TCMR_reg(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_get_TCMR_reg(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TCMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_TCMR_reg(const void *const hw, hri_ssc_tcmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TCMR_reg(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TCMR_reg(const void *const hw, hri_ssc_tcmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TCMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tcmr_reg_t hri_ssc_read_TCMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_TCMR; +} + +static inline void hri_ssc_set_TFMR_DATDEF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_DATDEF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_TFMR_DATDEF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_DATDEF) >> SSC_TFMR_DATDEF_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_TFMR_DATDEF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_DATDEF; + tmp |= value << SSC_TFMR_DATDEF_Pos; + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_DATDEF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_DATDEF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_DATDEF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_DATDEF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_TFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_TFMR_MSBF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_MSBF) >> SSC_TFMR_MSBF_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_TFMR_MSBF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_MSBF; + tmp |= value << SSC_TFMR_MSBF_Pos; + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_MSBF_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_MSBF; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_TFMR_FSDEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_FSDEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_TFMR_FSDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSDEN) >> SSC_TFMR_FSDEN_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_TFMR_FSDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_FSDEN; + tmp |= value << SSC_TFMR_FSDEN_Pos; + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_FSDEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_FSDEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_FSDEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_FSDEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_TFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_TFMR_FSEDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSEDGE) >> SSC_TFMR_FSEDGE_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_TFMR_FSEDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_FSEDGE; + tmp |= value << SSC_TFMR_FSEDGE_Pos; + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_FSEDGE_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_FSEDGE; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_TFMR_DATLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_DATLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_DATLEN(mask)) >> SSC_TFMR_DATLEN_Pos; + return tmp; +} + +static inline void hri_ssc_write_TFMR_DATLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_DATLEN_Msk; + tmp |= SSC_TFMR_DATLEN(data); + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_DATLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_DATLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_DATLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_DATLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_DATLEN_Msk) >> SSC_TFMR_DATLEN_Pos; + return tmp; +} + +static inline void hri_ssc_set_TFMR_DATNB_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_DATNB_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_DATNB(mask)) >> SSC_TFMR_DATNB_Pos; + return tmp; +} + +static inline void hri_ssc_write_TFMR_DATNB_bf(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_DATNB_Msk; + tmp |= SSC_TFMR_DATNB(data); + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_DATNB_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_DATNB_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_DATNB(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_DATNB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_DATNB_Msk) >> SSC_TFMR_DATNB_Pos; + return tmp; +} + +static inline void hri_ssc_set_TFMR_FSLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_FSLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSLEN(mask)) >> SSC_TFMR_FSLEN_Pos; + return tmp; +} + +static inline void hri_ssc_write_TFMR_FSLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_FSLEN_Msk; + tmp |= SSC_TFMR_FSLEN(data); + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_FSLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_FSLEN_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_FSLEN(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_FSLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSLEN_Msk) >> SSC_TFMR_FSLEN_Pos; + return tmp; +} + +static inline void hri_ssc_set_TFMR_FSOS_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_FSOS_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSOS(mask)) >> SSC_TFMR_FSOS_Pos; + return tmp; +} + +static inline void hri_ssc_write_TFMR_FSOS_bf(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_FSOS_Msk; + tmp |= SSC_TFMR_FSOS(data); + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_FSOS_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_FSOS_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_FSOS(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_FSOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSOS_Msk) >> SSC_TFMR_FSOS_Pos; + return tmp; +} + +static inline void hri_ssc_set_TFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= SSC_TFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSLEN_EXT(mask)) >> SSC_TFMR_FSLEN_EXT_Pos; + return tmp; +} + +static inline void hri_ssc_write_TFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= ~SSC_TFMR_FSLEN_EXT_Msk; + tmp |= SSC_TFMR_FSLEN_EXT(data); + ((Ssc *)hw)->SSC_TFMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~SSC_TFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_FSLEN_EXT_bf(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= SSC_TFMR_FSLEN_EXT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_FSLEN_EXT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp = (tmp & SSC_TFMR_FSLEN_EXT_Msk) >> SSC_TFMR_FSLEN_EXT_Pos; + return tmp; +} + +static inline void hri_ssc_set_TFMR_reg(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_get_TFMR_reg(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TFMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_TFMR_reg(const void *const hw, hri_ssc_tfmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TFMR_reg(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TFMR_reg(const void *const hw, hri_ssc_tfmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TFMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tfmr_reg_t hri_ssc_read_TFMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_TFMR; +} + +static inline void hri_ssc_set_TSHR_TSDAT_bf(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR |= SSC_TSHR_TSDAT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tshr_reg_t hri_ssc_get_TSHR_TSDAT_bf(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TSHR; + tmp = (tmp & SSC_TSHR_TSDAT(mask)) >> SSC_TSHR_TSDAT_Pos; + return tmp; +} + +static inline void hri_ssc_write_TSHR_TSDAT_bf(const void *const hw, hri_ssc_tshr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_TSHR; + tmp &= ~SSC_TSHR_TSDAT_Msk; + tmp |= SSC_TSHR_TSDAT(data); + ((Ssc *)hw)->SSC_TSHR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TSHR_TSDAT_bf(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR &= ~SSC_TSHR_TSDAT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TSHR_TSDAT_bf(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR ^= SSC_TSHR_TSDAT(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tshr_reg_t hri_ssc_read_TSHR_TSDAT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TSHR; + tmp = (tmp & SSC_TSHR_TSDAT_Msk) >> SSC_TSHR_TSDAT_Pos; + return tmp; +} + +static inline void hri_ssc_set_TSHR_reg(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tshr_reg_t hri_ssc_get_TSHR_reg(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_TSHR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_TSHR_reg(const void *const hw, hri_ssc_tshr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_TSHR_reg(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_TSHR_reg(const void *const hw, hri_ssc_tshr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_TSHR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_tshr_reg_t hri_ssc_read_TSHR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_TSHR; +} + +static inline void hri_ssc_set_RC0R_CP0_bf(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R |= SSC_RC0R_CP0(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc0r_reg_t hri_ssc_get_RC0R_CP0_bf(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC0R; + tmp = (tmp & SSC_RC0R_CP0(mask)) >> SSC_RC0R_CP0_Pos; + return tmp; +} + +static inline void hri_ssc_write_RC0R_CP0_bf(const void *const hw, hri_ssc_rc0r_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RC0R; + tmp &= ~SSC_RC0R_CP0_Msk; + tmp |= SSC_RC0R_CP0(data); + ((Ssc *)hw)->SSC_RC0R = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RC0R_CP0_bf(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R &= ~SSC_RC0R_CP0(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RC0R_CP0_bf(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R ^= SSC_RC0R_CP0(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc0r_reg_t hri_ssc_read_RC0R_CP0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC0R; + tmp = (tmp & SSC_RC0R_CP0_Msk) >> SSC_RC0R_CP0_Pos; + return tmp; +} + +static inline void hri_ssc_set_RC0R_reg(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc0r_reg_t hri_ssc_get_RC0R_reg(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC0R; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_RC0R_reg(const void *const hw, hri_ssc_rc0r_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RC0R_reg(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RC0R_reg(const void *const hw, hri_ssc_rc0r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC0R ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc0r_reg_t hri_ssc_read_RC0R_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RC0R; +} + +static inline void hri_ssc_set_RC1R_CP1_bf(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R |= SSC_RC1R_CP1(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc1r_reg_t hri_ssc_get_RC1R_CP1_bf(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC1R; + tmp = (tmp & SSC_RC1R_CP1(mask)) >> SSC_RC1R_CP1_Pos; + return tmp; +} + +static inline void hri_ssc_write_RC1R_CP1_bf(const void *const hw, hri_ssc_rc1r_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_RC1R; + tmp &= ~SSC_RC1R_CP1_Msk; + tmp |= SSC_RC1R_CP1(data); + ((Ssc *)hw)->SSC_RC1R = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RC1R_CP1_bf(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R &= ~SSC_RC1R_CP1(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RC1R_CP1_bf(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R ^= SSC_RC1R_CP1(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc1r_reg_t hri_ssc_read_RC1R_CP1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC1R; + tmp = (tmp & SSC_RC1R_CP1_Msk) >> SSC_RC1R_CP1_Pos; + return tmp; +} + +static inline void hri_ssc_set_RC1R_reg(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc1r_reg_t hri_ssc_get_RC1R_reg(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_RC1R; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_RC1R_reg(const void *const hw, hri_ssc_rc1r_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_RC1R_reg(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_RC1R_reg(const void *const hw, hri_ssc_rc1r_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_RC1R ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_rc1r_reg_t hri_ssc_read_RC1R_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_RC1R; +} + +static inline void hri_ssc_set_WPMR_WPEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR |= SSC_WPMR_WPEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ssc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp = (tmp & SSC_WPMR_WPEN) >> SSC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_ssc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp &= ~SSC_WPMR_WPEN; + tmp |= value << SSC_WPMR_WPEN_Pos; + ((Ssc *)hw)->SSC_WPMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_WPMR_WPEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR &= ~SSC_WPMR_WPEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR ^= SSC_WPMR_WPEN; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_set_WPMR_WPKEY_bf(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR |= SSC_WPMR_WPKEY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_wpmr_reg_t hri_ssc_get_WPMR_WPKEY_bf(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp = (tmp & SSC_WPMR_WPKEY(mask)) >> SSC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_ssc_write_WPMR_WPKEY_bf(const void *const hw, hri_ssc_wpmr_reg_t data) +{ + uint32_t tmp; + SSC_CRITICAL_SECTION_ENTER(); + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp &= ~SSC_WPMR_WPKEY_Msk; + tmp |= SSC_WPMR_WPKEY(data); + ((Ssc *)hw)->SSC_WPMR = tmp; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_WPMR_WPKEY_bf(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR &= ~SSC_WPMR_WPKEY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR ^= SSC_WPMR_WPKEY(mask); + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_wpmr_reg_t hri_ssc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp = (tmp & SSC_WPMR_WPKEY_Msk) >> SSC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_ssc_set_WPMR_reg(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR |= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_wpmr_reg_t hri_ssc_get_WPMR_reg(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ssc *)hw)->SSC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_ssc_write_WPMR_reg(const void *const hw, hri_ssc_wpmr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_clear_WPMR_reg(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR &= ~mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_toggle_WPMR_reg(const void *const hw, hri_ssc_wpmr_reg_t mask) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_WPMR ^= mask; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ssc_wpmr_reg_t hri_ssc_read_WPMR_reg(const void *const hw) +{ + return ((Ssc *)hw)->SSC_WPMR; +} + +static inline void hri_ssc_write_CR_reg(const void *const hw, hri_ssc_cr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_CR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ssc_write_THR_reg(const void *const hw, hri_ssc_thr_reg_t data) +{ + SSC_CRITICAL_SECTION_ENTER(); + ((Ssc *)hw)->SSC_THR = data; + SSC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SSC_E70B_H_INCLUDED */ +#endif /* _SAME70_SSC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_supc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_supc_e70b.h new file mode 100644 index 0000000000..f58fc3694f --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_supc_e70b.h @@ -0,0 +1,2243 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_E70B_H_INCLUDED_ +#define _HRI_SUPC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_cr_reg_t; +typedef uint32_t hri_supc_mr_reg_t; +typedef uint32_t hri_supc_smmr_reg_t; +typedef uint32_t hri_supc_sr_reg_t; +typedef uint32_t hri_supc_wuir_reg_t; +typedef uint32_t hri_supc_wumr_reg_t; + +static inline bool hri_supc_get_SR_WKUPS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPS) > 0; +} + +static inline bool hri_supc_get_SR_SMWS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_SMWS) > 0; +} + +static inline bool hri_supc_get_SR_BODRSTS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_BODRSTS) > 0; +} + +static inline bool hri_supc_get_SR_SMRSTS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_SMRSTS) > 0; +} + +static inline bool hri_supc_get_SR_SMS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_SMS) > 0; +} + +static inline bool hri_supc_get_SR_SMOS_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_SMOS) > 0; +} + +static inline bool hri_supc_get_SR_OSCSEL_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_OSCSEL) > 0; +} + +static inline bool hri_supc_get_SR_LPDBCS0_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_LPDBCS0) > 0; +} + +static inline bool hri_supc_get_SR_LPDBCS1_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_LPDBCS1) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS0_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS0) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS1_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS1) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS2_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS2) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS3_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS3) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS4_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS4) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS5_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS5) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS6_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS6) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS7_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS7) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS8_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS8) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS9_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS9) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS10_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS10) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS11_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS11) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS12_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS12) > 0; +} + +static inline bool hri_supc_get_SR_WKUPIS13_bit(const void *const hw) +{ + return (((Supc *)hw)->SUPC_SR & SUPC_SR_WKUPIS13) > 0; +} + +static inline hri_supc_sr_reg_t hri_supc_get_SR_reg(const void *const hw, hri_supc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_supc_sr_reg_t hri_supc_read_SR_reg(const void *const hw) +{ + return ((Supc *)hw)->SUPC_SR; +} + +static inline void hri_supc_set_SMMR_SMRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR |= SUPC_SMMR_SMRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_SMMR_SMRSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMRSTEN) >> SUPC_SMMR_SMRSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_SMMR_SMRSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp &= ~SUPC_SMMR_SMRSTEN; + tmp |= value << SUPC_SMMR_SMRSTEN_Pos; + ((Supc *)hw)->SUPC_SMMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_SMMR_SMRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR &= ~SUPC_SMMR_SMRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_SMMR_SMRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR ^= SUPC_SMMR_SMRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_SMMR_SMIEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR |= SUPC_SMMR_SMIEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_SMMR_SMIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMIEN) >> SUPC_SMMR_SMIEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_SMMR_SMIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp &= ~SUPC_SMMR_SMIEN; + tmp |= value << SUPC_SMMR_SMIEN_Pos; + ((Supc *)hw)->SUPC_SMMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_SMMR_SMIEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR &= ~SUPC_SMMR_SMIEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_SMMR_SMIEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR ^= SUPC_SMMR_SMIEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_SMMR_SMTH_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR |= SUPC_SMMR_SMTH(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_get_SMMR_SMTH_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMTH(mask)) >> SUPC_SMMR_SMTH_Pos; + return tmp; +} + +static inline void hri_supc_write_SMMR_SMTH_bf(const void *const hw, hri_supc_smmr_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp &= ~SUPC_SMMR_SMTH_Msk; + tmp |= SUPC_SMMR_SMTH(data); + ((Supc *)hw)->SUPC_SMMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_SMMR_SMTH_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR &= ~SUPC_SMMR_SMTH(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_SMMR_SMTH_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR ^= SUPC_SMMR_SMTH(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_read_SMMR_SMTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMTH_Msk) >> SUPC_SMMR_SMTH_Pos; + return tmp; +} + +static inline void hri_supc_set_SMMR_SMSMPL_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR |= SUPC_SMMR_SMSMPL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_get_SMMR_SMSMPL_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMSMPL(mask)) >> SUPC_SMMR_SMSMPL_Pos; + return tmp; +} + +static inline void hri_supc_write_SMMR_SMSMPL_bf(const void *const hw, hri_supc_smmr_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp &= ~SUPC_SMMR_SMSMPL_Msk; + tmp |= SUPC_SMMR_SMSMPL(data); + ((Supc *)hw)->SUPC_SMMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_SMMR_SMSMPL_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR &= ~SUPC_SMMR_SMSMPL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_SMMR_SMSMPL_bf(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR ^= SUPC_SMMR_SMSMPL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_read_SMMR_SMSMPL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp = (tmp & SUPC_SMMR_SMSMPL_Msk) >> SUPC_SMMR_SMSMPL_Pos; + return tmp; +} + +static inline void hri_supc_set_SMMR_reg(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_get_SMMR_reg(const void *const hw, hri_supc_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_SMMR; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_SMMR_reg(const void *const hw, hri_supc_smmr_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_SMMR_reg(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_SMMR_reg(const void *const hw, hri_supc_smmr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_SMMR ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_smmr_reg_t hri_supc_read_SMMR_reg(const void *const hw) +{ + return ((Supc *)hw)->SUPC_SMMR; +} + +static inline void hri_supc_set_MR_BODRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_BODRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_MR_BODRSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_BODRSTEN) >> SUPC_MR_BODRSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_MR_BODRSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_BODRSTEN; + tmp |= value << SUPC_MR_BODRSTEN_Pos; + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_BODRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_BODRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_BODRSTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_BODRSTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_MR_BODDIS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_BODDIS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_MR_BODDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_BODDIS) >> SUPC_MR_BODDIS_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_MR_BODDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_BODDIS; + tmp |= value << SUPC_MR_BODDIS_Pos; + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_BODDIS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_BODDIS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_BODDIS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_BODDIS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_MR_ONREG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_ONREG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_MR_ONREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_ONREG) >> SUPC_MR_ONREG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_MR_ONREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_ONREG; + tmp |= value << SUPC_MR_ONREG_Pos; + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_ONREG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_ONREG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_ONREG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_ONREG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_MR_BKUPRETON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_BKUPRETON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_MR_BKUPRETON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_BKUPRETON) >> SUPC_MR_BKUPRETON_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_MR_BKUPRETON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_BKUPRETON; + tmp |= value << SUPC_MR_BKUPRETON_Pos; + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_BKUPRETON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_BKUPRETON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_BKUPRETON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_BKUPRETON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_MR_OSCBYPASS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_OSCBYPASS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_MR_OSCBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_OSCBYPASS) >> SUPC_MR_OSCBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_MR_OSCBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_OSCBYPASS; + tmp |= value << SUPC_MR_OSCBYPASS_Pos; + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_OSCBYPASS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_OSCBYPASS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_OSCBYPASS_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_OSCBYPASS; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_MR_KEY_bf(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= SUPC_MR_KEY(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_mr_reg_t hri_supc_get_MR_KEY_bf(const void *const hw, hri_supc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_KEY(mask)) >> SUPC_MR_KEY_Pos; + return tmp; +} + +static inline void hri_supc_write_MR_KEY_bf(const void *const hw, hri_supc_mr_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= ~SUPC_MR_KEY_Msk; + tmp |= SUPC_MR_KEY(data); + ((Supc *)hw)->SUPC_MR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_KEY_bf(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~SUPC_MR_KEY(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_KEY_bf(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= SUPC_MR_KEY(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_mr_reg_t hri_supc_read_MR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp = (tmp & SUPC_MR_KEY_Msk) >> SUPC_MR_KEY_Pos; + return tmp; +} + +static inline void hri_supc_set_MR_reg(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_mr_reg_t hri_supc_get_MR_reg(const void *const hw, hri_supc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_MR_reg(const void *const hw, hri_supc_mr_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_MR_reg(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_MR_reg(const void *const hw, hri_supc_mr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_MR ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_mr_reg_t hri_supc_read_MR_reg(const void *const hw) +{ + return ((Supc *)hw)->SUPC_MR; +} + +static inline void hri_supc_set_WUMR_SMEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_SMEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_SMEN) >> SUPC_WUMR_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_SMEN; + tmp |= value << SUPC_WUMR_SMEN_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_SMEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_SMEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_SMEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_SMEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_RTTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_RTTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_RTTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_RTTEN) >> SUPC_WUMR_RTTEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_RTTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_RTTEN; + tmp |= value << SUPC_WUMR_RTTEN_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_RTTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_RTTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_RTTEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_RTTEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_RTCEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_RTCEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_RTCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_RTCEN) >> SUPC_WUMR_RTCEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_RTCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_RTCEN; + tmp |= value << SUPC_WUMR_RTCEN_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_RTCEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_RTCEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_RTCEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_RTCEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_LPDBCEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_LPDBCEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_LPDBCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_LPDBCEN0) >> SUPC_WUMR_LPDBCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_LPDBCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_LPDBCEN0; + tmp |= value << SUPC_WUMR_LPDBCEN0_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_LPDBCEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_LPDBCEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_LPDBCEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_LPDBCEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_LPDBCEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_LPDBCEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_LPDBCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_LPDBCEN1) >> SUPC_WUMR_LPDBCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_LPDBCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_LPDBCEN1; + tmp |= value << SUPC_WUMR_LPDBCEN1_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_LPDBCEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_LPDBCEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_LPDBCEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_LPDBCEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_LPDBCCLR_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_LPDBCCLR; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUMR_LPDBCCLR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_LPDBCCLR) >> SUPC_WUMR_LPDBCCLR_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUMR_LPDBCCLR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_LPDBCCLR; + tmp |= value << SUPC_WUMR_LPDBCCLR_Pos; + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_LPDBCCLR_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_LPDBCCLR; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_LPDBCCLR_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_LPDBCCLR; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUMR_WKUPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_WKUPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_get_WUMR_WKUPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_WKUPDBC(mask)) >> SUPC_WUMR_WKUPDBC_Pos; + return tmp; +} + +static inline void hri_supc_write_WUMR_WKUPDBC_bf(const void *const hw, hri_supc_wumr_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_WKUPDBC_Msk; + tmp |= SUPC_WUMR_WKUPDBC(data); + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_WKUPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_WKUPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_WKUPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_WKUPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_read_WUMR_WKUPDBC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_WKUPDBC_Msk) >> SUPC_WUMR_WKUPDBC_Pos; + return tmp; +} + +static inline void hri_supc_set_WUMR_LPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= SUPC_WUMR_LPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_get_WUMR_LPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_LPDBC(mask)) >> SUPC_WUMR_LPDBC_Pos; + return tmp; +} + +static inline void hri_supc_write_WUMR_LPDBC_bf(const void *const hw, hri_supc_wumr_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= ~SUPC_WUMR_LPDBC_Msk; + tmp |= SUPC_WUMR_LPDBC(data); + ((Supc *)hw)->SUPC_WUMR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_LPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~SUPC_WUMR_LPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_LPDBC_bf(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= SUPC_WUMR_LPDBC(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_read_WUMR_LPDBC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp = (tmp & SUPC_WUMR_LPDBC_Msk) >> SUPC_WUMR_LPDBC_Pos; + return tmp; +} + +static inline void hri_supc_set_WUMR_reg(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_get_WUMR_reg(const void *const hw, hri_supc_wumr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUMR; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_WUMR_reg(const void *const hw, hri_supc_wumr_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUMR_reg(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUMR_reg(const void *const hw, hri_supc_wumr_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUMR ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wumr_reg_t hri_supc_read_WUMR_reg(const void *const hw) +{ + return ((Supc *)hw)->SUPC_WUMR; +} + +static inline void hri_supc_set_WUIR_WKUPEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN0) >> SUPC_WUIR_WKUPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN0; + tmp |= value << SUPC_WUIR_WKUPEN0_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN1) >> SUPC_WUIR_WKUPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN1; + tmp |= value << SUPC_WUIR_WKUPEN1_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN2) >> SUPC_WUIR_WKUPEN2_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN2; + tmp |= value << SUPC_WUIR_WKUPEN2_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN3) >> SUPC_WUIR_WKUPEN3_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN3; + tmp |= value << SUPC_WUIR_WKUPEN3_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN4) >> SUPC_WUIR_WKUPEN4_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN4; + tmp |= value << SUPC_WUIR_WKUPEN4_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN5) >> SUPC_WUIR_WKUPEN5_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN5; + tmp |= value << SUPC_WUIR_WKUPEN5_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN6) >> SUPC_WUIR_WKUPEN6_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN6; + tmp |= value << SUPC_WUIR_WKUPEN6_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN7) >> SUPC_WUIR_WKUPEN7_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN7; + tmp |= value << SUPC_WUIR_WKUPEN7_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN8) >> SUPC_WUIR_WKUPEN8_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN8; + tmp |= value << SUPC_WUIR_WKUPEN8_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN9) >> SUPC_WUIR_WKUPEN9_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN9; + tmp |= value << SUPC_WUIR_WKUPEN9_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN10) >> SUPC_WUIR_WKUPEN10_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN10; + tmp |= value << SUPC_WUIR_WKUPEN10_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN11) >> SUPC_WUIR_WKUPEN11_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN11; + tmp |= value << SUPC_WUIR_WKUPEN11_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN12) >> SUPC_WUIR_WKUPEN12_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN12; + tmp |= value << SUPC_WUIR_WKUPEN12_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPEN13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPEN13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPEN13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPEN13) >> SUPC_WUIR_WKUPEN13_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPEN13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPEN13; + tmp |= value << SUPC_WUIR_WKUPEN13_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPEN13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPEN13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPEN13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPEN13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT0) >> SUPC_WUIR_WKUPT0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT0; + tmp |= value << SUPC_WUIR_WKUPT0_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT1) >> SUPC_WUIR_WKUPT1_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT1; + tmp |= value << SUPC_WUIR_WKUPT1_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT1_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT1; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT2) >> SUPC_WUIR_WKUPT2_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT2; + tmp |= value << SUPC_WUIR_WKUPT2_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT2_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT2; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT3) >> SUPC_WUIR_WKUPT3_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT3; + tmp |= value << SUPC_WUIR_WKUPT3_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT3_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT3; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT4) >> SUPC_WUIR_WKUPT4_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT4; + tmp |= value << SUPC_WUIR_WKUPT4_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT4_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT4; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT5) >> SUPC_WUIR_WKUPT5_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT5; + tmp |= value << SUPC_WUIR_WKUPT5_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT5_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT5; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT6) >> SUPC_WUIR_WKUPT6_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT6; + tmp |= value << SUPC_WUIR_WKUPT6_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT6_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT6; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT7) >> SUPC_WUIR_WKUPT7_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT7; + tmp |= value << SUPC_WUIR_WKUPT7_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT7_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT7; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT8) >> SUPC_WUIR_WKUPT8_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT8; + tmp |= value << SUPC_WUIR_WKUPT8_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT8_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT8; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT9) >> SUPC_WUIR_WKUPT9_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT9; + tmp |= value << SUPC_WUIR_WKUPT9_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT9_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT9; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT10) >> SUPC_WUIR_WKUPT10_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT10; + tmp |= value << SUPC_WUIR_WKUPT10_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT10_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT10; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT11) >> SUPC_WUIR_WKUPT11_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT11; + tmp |= value << SUPC_WUIR_WKUPT11_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT11_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT11; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT12) >> SUPC_WUIR_WKUPT12_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT12; + tmp |= value << SUPC_WUIR_WKUPT12_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT12_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT12; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_WKUPT13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= SUPC_WUIR_WKUPT13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_WUIR_WKUPT13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp = (tmp & SUPC_WUIR_WKUPT13) >> SUPC_WUIR_WKUPT13_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_WUIR_WKUPT13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= ~SUPC_WUIR_WKUPT13; + tmp |= value << SUPC_WUIR_WKUPT13_Pos; + ((Supc *)hw)->SUPC_WUIR = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_WKUPT13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~SUPC_WUIR_WKUPT13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_WKUPT13_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= SUPC_WUIR_WKUPT13; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_WUIR_reg(const void *const hw, hri_supc_wuir_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wuir_reg_t hri_supc_get_WUIR_reg(const void *const hw, hri_supc_wuir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->SUPC_WUIR; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_WUIR_reg(const void *const hw, hri_supc_wuir_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_WUIR_reg(const void *const hw, hri_supc_wuir_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_WUIR_reg(const void *const hw, hri_supc_wuir_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_WUIR ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_wuir_reg_t hri_supc_read_WUIR_reg(const void *const hw) +{ + return ((Supc *)hw)->SUPC_WUIR; +} + +static inline void hri_supc_write_CR_reg(const void *const hw, hri_supc_cr_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->SUPC_CR = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_E70B_H_INCLUDED */ +#endif /* _SAME70_SUPC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_tc_e70b.h b/bsp/microchip/same70/bsp/hri/hri_tc_e70b.h new file mode 100644 index 0000000000..dfd3672cbe --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_tc_e70b.h @@ -0,0 +1,5553 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_TC_COMPONENT_ +#ifndef _HRI_TC_E70B_H_INCLUDED_ +#define _HRI_TC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_tc_bcr_reg_t; +typedef uint32_t hri_tc_bmr_reg_t; +typedef uint32_t hri_tc_ccr_reg_t; +typedef uint32_t hri_tc_cmr_reg_t; +typedef uint32_t hri_tc_cv_reg_t; +typedef uint32_t hri_tc_emr_reg_t; +typedef uint32_t hri_tc_fmr_reg_t; +typedef uint32_t hri_tc_imr_reg_t; +typedef uint32_t hri_tc_qidr_reg_t; +typedef uint32_t hri_tc_qier_reg_t; +typedef uint32_t hri_tc_qimr_reg_t; +typedef uint32_t hri_tc_qisr_reg_t; +typedef uint32_t hri_tc_ra_reg_t; +typedef uint32_t hri_tc_rab_reg_t; +typedef uint32_t hri_tc_rb_reg_t; +typedef uint32_t hri_tc_rc_reg_t; +typedef uint32_t hri_tc_smmr_reg_t; +typedef uint32_t hri_tc_sr_reg_t; +typedef uint32_t hri_tc_wpmr_reg_t; + +static inline void hri_tcchannel_set_IMR_COVFS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_COVFS; +} + +static inline bool hri_tcchannel_get_IMR_COVFS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_COVFS) >> TC_IMR_COVFS_Pos; +} + +static inline void hri_tcchannel_write_IMR_COVFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_COVFS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_COVFS; + } +} + +static inline void hri_tcchannel_clear_IMR_COVFS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_COVFS; +} + +static inline void hri_tcchannel_set_IMR_LOVRS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_LOVRS; +} + +static inline bool hri_tcchannel_get_IMR_LOVRS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_LOVRS) >> TC_IMR_LOVRS_Pos; +} + +static inline void hri_tcchannel_write_IMR_LOVRS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_LOVRS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_LOVRS; + } +} + +static inline void hri_tcchannel_clear_IMR_LOVRS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_LOVRS; +} + +static inline void hri_tcchannel_set_IMR_CPAS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_CPAS; +} + +static inline bool hri_tcchannel_get_IMR_CPAS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_CPAS) >> TC_IMR_CPAS_Pos; +} + +static inline void hri_tcchannel_write_IMR_CPAS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPAS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_CPAS; + } +} + +static inline void hri_tcchannel_clear_IMR_CPAS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPAS; +} + +static inline void hri_tcchannel_set_IMR_CPBS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_CPBS; +} + +static inline bool hri_tcchannel_get_IMR_CPBS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_CPBS) >> TC_IMR_CPBS_Pos; +} + +static inline void hri_tcchannel_write_IMR_CPBS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPBS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_CPBS; + } +} + +static inline void hri_tcchannel_clear_IMR_CPBS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPBS; +} + +static inline void hri_tcchannel_set_IMR_CPCS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_CPCS; +} + +static inline bool hri_tcchannel_get_IMR_CPCS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_CPCS) >> TC_IMR_CPCS_Pos; +} + +static inline void hri_tcchannel_write_IMR_CPCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPCS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_CPCS; + } +} + +static inline void hri_tcchannel_clear_IMR_CPCS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_CPCS; +} + +static inline void hri_tcchannel_set_IMR_LDRAS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_LDRAS; +} + +static inline bool hri_tcchannel_get_IMR_LDRAS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_LDRAS) >> TC_IMR_LDRAS_Pos; +} + +static inline void hri_tcchannel_write_IMR_LDRAS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_LDRAS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_LDRAS; + } +} + +static inline void hri_tcchannel_clear_IMR_LDRAS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_LDRAS; +} + +static inline void hri_tcchannel_set_IMR_LDRBS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_LDRBS; +} + +static inline bool hri_tcchannel_get_IMR_LDRBS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_LDRBS) >> TC_IMR_LDRBS_Pos; +} + +static inline void hri_tcchannel_write_IMR_LDRBS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_LDRBS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_LDRBS; + } +} + +static inline void hri_tcchannel_clear_IMR_LDRBS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_LDRBS; +} + +static inline void hri_tcchannel_set_IMR_ETRGS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IER = TC_IMR_ETRGS; +} + +static inline bool hri_tcchannel_get_IMR_ETRGS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_IMR & TC_IMR_ETRGS) >> TC_IMR_ETRGS_Pos; +} + +static inline void hri_tcchannel_write_IMR_ETRGS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((TcChannel *)hw)->TC_IDR = TC_IMR_ETRGS; + } else { + ((TcChannel *)hw)->TC_IER = TC_IMR_ETRGS; + } +} + +static inline void hri_tcchannel_clear_IMR_ETRGS_bit(const void *const hw) +{ + ((TcChannel *)hw)->TC_IDR = TC_IMR_ETRGS; +} + +static inline void hri_tcchannel_set_IMR_reg(const void *const hw, hri_tc_imr_reg_t mask) +{ + ((TcChannel *)hw)->TC_IER = mask; +} + +static inline hri_tc_imr_reg_t hri_tcchannel_get_IMR_reg(const void *const hw, hri_tc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_imr_reg_t hri_tcchannel_read_IMR_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_IMR; +} + +static inline void hri_tcchannel_write_IMR_reg(const void *const hw, hri_tc_imr_reg_t data) +{ + ((TcChannel *)hw)->TC_IER = data; + ((TcChannel *)hw)->TC_IDR = ~data; +} + +static inline void hri_tcchannel_clear_IMR_reg(const void *const hw, hri_tc_imr_reg_t mask) +{ + ((TcChannel *)hw)->TC_IDR = mask; +} + +static inline hri_tc_rab_reg_t hri_tcchannel_get_RAB_RAB_bf(const void *const hw, hri_tc_rab_reg_t mask) +{ + return (((TcChannel *)hw)->TC_RAB & TC_RAB_RAB(mask)) >> TC_RAB_RAB_Pos; +} + +static inline hri_tc_rab_reg_t hri_tcchannel_read_RAB_RAB_bf(const void *const hw) +{ + return (((TcChannel *)hw)->TC_RAB & TC_RAB_RAB_Msk) >> TC_RAB_RAB_Pos; +} + +static inline hri_tc_rab_reg_t hri_tcchannel_get_RAB_reg(const void *const hw, hri_tc_rab_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RAB; + tmp &= mask; + return tmp; +} + +static inline hri_tc_rab_reg_t hri_tcchannel_read_RAB_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_RAB; +} + +static inline hri_tc_cv_reg_t hri_tcchannel_get_CV_CV_bf(const void *const hw, hri_tc_cv_reg_t mask) +{ + return (((TcChannel *)hw)->TC_CV & TC_CV_CV(mask)) >> TC_CV_CV_Pos; +} + +static inline hri_tc_cv_reg_t hri_tcchannel_read_CV_CV_bf(const void *const hw) +{ + return (((TcChannel *)hw)->TC_CV & TC_CV_CV_Msk) >> TC_CV_CV_Pos; +} + +static inline hri_tc_cv_reg_t hri_tcchannel_get_CV_reg(const void *const hw, hri_tc_cv_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CV; + tmp &= mask; + return tmp; +} + +static inline hri_tc_cv_reg_t hri_tcchannel_read_CV_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_CV; +} + +static inline bool hri_tcchannel_get_SR_COVFS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_COVFS) > 0; +} + +static inline bool hri_tcchannel_get_SR_LOVRS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_LOVRS) > 0; +} + +static inline bool hri_tcchannel_get_SR_CPAS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_CPAS) > 0; +} + +static inline bool hri_tcchannel_get_SR_CPBS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_CPBS) > 0; +} + +static inline bool hri_tcchannel_get_SR_CPCS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_CPCS) > 0; +} + +static inline bool hri_tcchannel_get_SR_LDRAS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_LDRAS) > 0; +} + +static inline bool hri_tcchannel_get_SR_LDRBS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_LDRBS) > 0; +} + +static inline bool hri_tcchannel_get_SR_ETRGS_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_ETRGS) > 0; +} + +static inline bool hri_tcchannel_get_SR_CLKSTA_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_CLKSTA) > 0; +} + +static inline bool hri_tcchannel_get_SR_MTIOA_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_MTIOA) > 0; +} + +static inline bool hri_tcchannel_get_SR_MTIOB_bit(const void *const hw) +{ + return (((TcChannel *)hw)->TC_SR & TC_SR_MTIOB) > 0; +} + +static inline hri_tc_sr_reg_t hri_tcchannel_get_SR_reg(const void *const hw, hri_tc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_sr_reg_t hri_tcchannel_read_SR_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_SR; +} + +static inline void hri_tcchannel_set_CMR_CLKI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_CLKI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CLKI) >> TC_CMR_CLKI_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_CLKI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CLKI; + tmp |= value << TC_CMR_CLKI_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CLKI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CLKI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_LDBSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_CAPTURE_LDBSTOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDBSTOP) >> TC_CMR_CAPTURE_LDBSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDBSTOP; + tmp |= value << TC_CMR_CAPTURE_LDBSTOP_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_LDBSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_LDBSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_CPCSTOP) >> TC_CMR_WAVEFORM_CPCSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_CPCSTOP; + tmp |= value << TC_CMR_WAVEFORM_CPCSTOP_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_LDBDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_CAPTURE_LDBDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDBDIS) >> TC_CMR_CAPTURE_LDBDIS_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_LDBDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDBDIS; + tmp |= value << TC_CMR_CAPTURE_LDBDIS_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_LDBDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_LDBDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_CPCDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_WAVEFORM_CPCDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_CPCDIS) >> TC_CMR_WAVEFORM_CPCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_CPCDIS; + tmp |= value << TC_CMR_WAVEFORM_CPCDIS_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_CPCDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_CPCDIS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_ABETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_CAPTURE_ABETRG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ABETRG) >> TC_CMR_CAPTURE_ABETRG_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_ABETRG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_ABETRG; + tmp |= value << TC_CMR_CAPTURE_ABETRG_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_ABETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_ABETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_ENETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_WAVEFORM_ENETRG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ENETRG) >> TC_CMR_WAVEFORM_ENETRG_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_ENETRG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ENETRG; + tmp |= value << TC_CMR_WAVEFORM_ENETRG_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_ENETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_ENETRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_CPCTRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_CAPTURE_CPCTRG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_CPCTRG) >> TC_CMR_CAPTURE_CPCTRG_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_CPCTRG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_CPCTRG; + tmp |= value << TC_CMR_CAPTURE_CPCTRG_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_CPCTRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_CPCTRG_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_WAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_CMR_WAVE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVE) >> TC_CMR_WAVE_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVE; + tmp |= value << TC_CMR_WAVE_Pos; + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_CMR_TCCLKS_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_TCCLKS_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_TCCLKS(mask)) >> TC_CMR_TCCLKS_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_TCCLKS_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_TCCLKS_Msk; + tmp |= TC_CMR_TCCLKS(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_TCCLKS_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_TCCLKS_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_TCCLKS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_TCCLKS_Msk) >> TC_CMR_TCCLKS_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_BURST_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_BURST_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_BURST(mask)) >> TC_CMR_BURST_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_BURST_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_BURST_Msk; + tmp |= TC_CMR_BURST(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_BURST_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_BURST_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_BURST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_BURST_Msk) >> TC_CMR_BURST_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ETRGEDG(mask)) >> TC_CMR_CAPTURE_ETRGEDG_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_ETRGEDG_Msk; + tmp |= TC_CMR_CAPTURE_ETRGEDG(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_CAPTURE_ETRGEDG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ETRGEDG_Msk) >> TC_CMR_CAPTURE_ETRGEDG_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVTEDG(mask)) >> TC_CMR_WAVEFORM_EEVTEDG_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_EEVTEDG_Msk; + tmp |= TC_CMR_WAVEFORM_EEVTEDG(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVTEDG_Msk) >> TC_CMR_WAVEFORM_EEVTEDG_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_EEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_EEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVT(mask)) >> TC_CMR_WAVEFORM_EEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_EEVT_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_EEVT_Msk; + tmp |= TC_CMR_WAVEFORM_EEVT(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_EEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_EEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_EEVT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVT_Msk) >> TC_CMR_WAVEFORM_EEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_WAVSEL(mask)) >> TC_CMR_WAVEFORM_WAVSEL_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_WAVSEL_Msk; + tmp |= TC_CMR_WAVEFORM_WAVSEL(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_WAVSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_WAVSEL_Msk) >> TC_CMR_WAVEFORM_WAVSEL_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_LDRA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_CAPTURE_LDRA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRA(mask)) >> TC_CMR_CAPTURE_LDRA_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_LDRA_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDRA_Msk; + tmp |= TC_CMR_CAPTURE_LDRA(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_LDRA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_LDRA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_CAPTURE_LDRA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRA_Msk) >> TC_CMR_CAPTURE_LDRA_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_ACPA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_ACPA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPA(mask)) >> TC_CMR_WAVEFORM_ACPA_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_ACPA_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ACPA_Msk; + tmp |= TC_CMR_WAVEFORM_ACPA(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_ACPA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_ACPA_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_ACPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPA_Msk) >> TC_CMR_WAVEFORM_ACPA_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_LDRB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_CAPTURE_LDRB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRB(mask)) >> TC_CMR_CAPTURE_LDRB_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_LDRB_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDRB_Msk; + tmp |= TC_CMR_CAPTURE_LDRB(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_LDRB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_LDRB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_CAPTURE_LDRB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRB_Msk) >> TC_CMR_CAPTURE_LDRB_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_ACPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_ACPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPC(mask)) >> TC_CMR_WAVEFORM_ACPC_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_ACPC_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ACPC_Msk; + tmp |= TC_CMR_WAVEFORM_ACPC(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_ACPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_ACPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_ACPC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPC_Msk) >> TC_CMR_WAVEFORM_ACPC_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_SBSMPLR(mask)) >> TC_CMR_CAPTURE_SBSMPLR_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_CAPTURE_SBSMPLR_Msk; + tmp |= TC_CMR_CAPTURE_SBSMPLR(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_CAPTURE_SBSMPLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_SBSMPLR_Msk) >> TC_CMR_CAPTURE_SBSMPLR_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_AEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_AEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_AEEVT(mask)) >> TC_CMR_WAVEFORM_AEEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_AEEVT_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_AEEVT_Msk; + tmp |= TC_CMR_WAVEFORM_AEEVT(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_AEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_AEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_AEEVT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_AEEVT_Msk) >> TC_CMR_WAVEFORM_AEEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ASWTRG(mask)) >> TC_CMR_WAVEFORM_ASWTRG_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ASWTRG_Msk; + tmp |= TC_CMR_WAVEFORM_ASWTRG(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_ASWTRG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ASWTRG_Msk) >> TC_CMR_WAVEFORM_ASWTRG_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_BCPB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_BCPB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPB(mask)) >> TC_CMR_WAVEFORM_BCPB_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_BCPB_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BCPB_Msk; + tmp |= TC_CMR_WAVEFORM_BCPB(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_BCPB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_BCPB_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_BCPB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPB_Msk) >> TC_CMR_WAVEFORM_BCPB_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_BCPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_BCPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPC(mask)) >> TC_CMR_WAVEFORM_BCPC_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_BCPC_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BCPC_Msk; + tmp |= TC_CMR_WAVEFORM_BCPC(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_BCPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_BCPC_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_BCPC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPC_Msk) >> TC_CMR_WAVEFORM_BCPC_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_BEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_BEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BEEVT(mask)) >> TC_CMR_WAVEFORM_BEEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_BEEVT_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BEEVT_Msk; + tmp |= TC_CMR_WAVEFORM_BEEVT(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_BEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_BEEVT_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_BEEVT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BEEVT_Msk) >> TC_CMR_WAVEFORM_BEEVT_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BSWTRG(mask)) >> TC_CMR_WAVEFORM_BSWTRG_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BSWTRG_Msk; + tmp |= TC_CMR_WAVEFORM_BSWTRG(data); + ((TcChannel *)hw)->TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_WAVEFORM_BSWTRG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BSWTRG_Msk) >> TC_CMR_WAVEFORM_BSWTRG_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_CMR_reg(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_get_CMR_reg(const void *const hw, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_CMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_CMR_reg(const void *const hw, hri_tc_cmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_CMR_reg(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_CMR_reg(const void *const hw, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tcchannel_read_CMR_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_CMR; +} + +static inline void hri_tcchannel_set_SMMR_GCEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR |= TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_SMMR_GCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_SMMR; + tmp = (tmp & TC_SMMR_GCEN) >> TC_SMMR_GCEN_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_SMMR_GCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_SMMR; + tmp &= ~TC_SMMR_GCEN; + tmp |= value << TC_SMMR_GCEN_Pos; + ((TcChannel *)hw)->TC_SMMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_SMMR_GCEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR &= ~TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_SMMR_GCEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR ^= TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_SMMR_DOWN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR |= TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_SMMR_DOWN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_SMMR; + tmp = (tmp & TC_SMMR_DOWN) >> TC_SMMR_DOWN_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_SMMR_DOWN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_SMMR; + tmp &= ~TC_SMMR_DOWN; + tmp |= value << TC_SMMR_DOWN_Pos; + ((TcChannel *)hw)->TC_SMMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_SMMR_DOWN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR &= ~TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_SMMR_DOWN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR ^= TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_SMMR_reg(const void *const hw, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_smmr_reg_t hri_tcchannel_get_SMMR_reg(const void *const hw, hri_tc_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_SMMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_SMMR_reg(const void *const hw, hri_tc_smmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_SMMR_reg(const void *const hw, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_SMMR_reg(const void *const hw, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_SMMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_smmr_reg_t hri_tcchannel_read_SMMR_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_SMMR; +} + +static inline void hri_tcchannel_set_RA_RA_bf(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA |= TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tcchannel_get_RA_RA_bf(const void *const hw, hri_tc_ra_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RA; + tmp = (tmp & TC_RA_RA(mask)) >> TC_RA_RA_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_RA_RA_bf(const void *const hw, hri_tc_ra_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_RA; + tmp &= ~TC_RA_RA_Msk; + tmp |= TC_RA_RA(data); + ((TcChannel *)hw)->TC_RA = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RA_RA_bf(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA &= ~TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RA_RA_bf(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA ^= TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tcchannel_read_RA_RA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RA; + tmp = (tmp & TC_RA_RA_Msk) >> TC_RA_RA_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_RA_reg(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tcchannel_get_RA_reg(const void *const hw, hri_tc_ra_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RA; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_RA_reg(const void *const hw, hri_tc_ra_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RA_reg(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RA_reg(const void *const hw, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RA ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tcchannel_read_RA_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_RA; +} + +static inline void hri_tcchannel_set_RB_RB_bf(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB |= TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tcchannel_get_RB_RB_bf(const void *const hw, hri_tc_rb_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RB; + tmp = (tmp & TC_RB_RB(mask)) >> TC_RB_RB_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_RB_RB_bf(const void *const hw, hri_tc_rb_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_RB; + tmp &= ~TC_RB_RB_Msk; + tmp |= TC_RB_RB(data); + ((TcChannel *)hw)->TC_RB = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RB_RB_bf(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB &= ~TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RB_RB_bf(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB ^= TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tcchannel_read_RB_RB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RB; + tmp = (tmp & TC_RB_RB_Msk) >> TC_RB_RB_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_RB_reg(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tcchannel_get_RB_reg(const void *const hw, hri_tc_rb_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RB; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_RB_reg(const void *const hw, hri_tc_rb_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RB_reg(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RB_reg(const void *const hw, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RB ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tcchannel_read_RB_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_RB; +} + +static inline void hri_tcchannel_set_RC_RC_bf(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC |= TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tcchannel_get_RC_RC_bf(const void *const hw, hri_tc_rc_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RC; + tmp = (tmp & TC_RC_RC(mask)) >> TC_RC_RC_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_RC_RC_bf(const void *const hw, hri_tc_rc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_RC; + tmp &= ~TC_RC_RC_Msk; + tmp |= TC_RC_RC(data); + ((TcChannel *)hw)->TC_RC = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RC_RC_bf(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC &= ~TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RC_RC_bf(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC ^= TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tcchannel_read_RC_RC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RC; + tmp = (tmp & TC_RC_RC_Msk) >> TC_RC_RC_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_RC_reg(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tcchannel_get_RC_reg(const void *const hw, hri_tc_rc_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_RC; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_RC_reg(const void *const hw, hri_tc_rc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_RC_reg(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_RC_reg(const void *const hw, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_RC ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tcchannel_read_RC_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_RC; +} + +static inline void hri_tcchannel_set_EMR_NODIVCLK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR |= TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcchannel_get_EMR_NODIVCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp = (tmp & TC_EMR_NODIVCLK) >> TC_EMR_NODIVCLK_Pos; + return (bool)tmp; +} + +static inline void hri_tcchannel_write_EMR_NODIVCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_EMR; + tmp &= ~TC_EMR_NODIVCLK; + tmp |= value << TC_EMR_NODIVCLK_Pos; + ((TcChannel *)hw)->TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_EMR_NODIVCLK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR &= ~TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_EMR_NODIVCLK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR ^= TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_set_EMR_TRIGSRCA_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR |= TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_get_EMR_TRIGSRCA_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCA(mask)) >> TC_EMR_TRIGSRCA_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_EMR_TRIGSRCA_bf(const void *const hw, hri_tc_emr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_EMR; + tmp &= ~TC_EMR_TRIGSRCA_Msk; + tmp |= TC_EMR_TRIGSRCA(data); + ((TcChannel *)hw)->TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_EMR_TRIGSRCA_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR &= ~TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_EMR_TRIGSRCA_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR ^= TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_read_EMR_TRIGSRCA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCA_Msk) >> TC_EMR_TRIGSRCA_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_EMR_TRIGSRCB_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR |= TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_get_EMR_TRIGSRCB_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCB(mask)) >> TC_EMR_TRIGSRCB_Pos; + return tmp; +} + +static inline void hri_tcchannel_write_EMR_TRIGSRCB_bf(const void *const hw, hri_tc_emr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((TcChannel *)hw)->TC_EMR; + tmp &= ~TC_EMR_TRIGSRCB_Msk; + tmp |= TC_EMR_TRIGSRCB(data); + ((TcChannel *)hw)->TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_EMR_TRIGSRCB_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR &= ~TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_EMR_TRIGSRCB_bf(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR ^= TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_read_EMR_TRIGSRCB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCB_Msk) >> TC_EMR_TRIGSRCB_Pos; + return tmp; +} + +static inline void hri_tcchannel_set_EMR_reg(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_get_EMR_reg(const void *const hw, hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((TcChannel *)hw)->TC_EMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tcchannel_write_EMR_reg(const void *const hw, hri_tc_emr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_clear_EMR_reg(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcchannel_toggle_EMR_reg(const void *const hw, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_EMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tcchannel_read_EMR_reg(const void *const hw) +{ + return ((TcChannel *)hw)->TC_EMR; +} + +static inline void hri_tcchannel_write_CCR_reg(const void *const hw, hri_tc_ccr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((TcChannel *)hw)->TC_CCR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_IMR_COVFS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_COVFS; +} + +static inline bool hri_tc_get_IMR_COVFS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_COVFS) >> TC_IMR_COVFS_Pos; +} + +static inline void hri_tc_write_IMR_COVFS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_COVFS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_COVFS; + } +} + +static inline void hri_tc_clear_IMR_COVFS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_COVFS; +} + +static inline void hri_tc_set_IMR_LOVRS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LOVRS; +} + +static inline bool hri_tc_get_IMR_LOVRS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_LOVRS) >> TC_IMR_LOVRS_Pos; +} + +static inline void hri_tc_write_IMR_LOVRS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LOVRS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LOVRS; + } +} + +static inline void hri_tc_clear_IMR_LOVRS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LOVRS; +} + +static inline void hri_tc_set_IMR_CPAS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPAS; +} + +static inline bool hri_tc_get_IMR_CPAS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_CPAS) >> TC_IMR_CPAS_Pos; +} + +static inline void hri_tc_write_IMR_CPAS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPAS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPAS; + } +} + +static inline void hri_tc_clear_IMR_CPAS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPAS; +} + +static inline void hri_tc_set_IMR_CPBS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPBS; +} + +static inline bool hri_tc_get_IMR_CPBS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_CPBS) >> TC_IMR_CPBS_Pos; +} + +static inline void hri_tc_write_IMR_CPBS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPBS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPBS; + } +} + +static inline void hri_tc_clear_IMR_CPBS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPBS; +} + +static inline void hri_tc_set_IMR_CPCS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPCS; +} + +static inline bool hri_tc_get_IMR_CPCS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_CPCS) >> TC_IMR_CPCS_Pos; +} + +static inline void hri_tc_write_IMR_CPCS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPCS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_CPCS; + } +} + +static inline void hri_tc_clear_IMR_CPCS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_CPCS; +} + +static inline void hri_tc_set_IMR_LDRAS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LDRAS; +} + +static inline bool hri_tc_get_IMR_LDRAS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_LDRAS) >> TC_IMR_LDRAS_Pos; +} + +static inline void hri_tc_write_IMR_LDRAS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LDRAS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LDRAS; + } +} + +static inline void hri_tc_clear_IMR_LDRAS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LDRAS; +} + +static inline void hri_tc_set_IMR_LDRBS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LDRBS; +} + +static inline bool hri_tc_get_IMR_LDRBS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_LDRBS) >> TC_IMR_LDRBS_Pos; +} + +static inline void hri_tc_write_IMR_LDRBS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LDRBS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_LDRBS; + } +} + +static inline void hri_tc_clear_IMR_LDRBS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_LDRBS; +} + +static inline void hri_tc_set_IMR_ETRGS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_ETRGS; +} + +static inline bool hri_tc_get_IMR_ETRGS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_IMR & TC_IMR_ETRGS) >> TC_IMR_ETRGS_Pos; +} + +static inline void hri_tc_write_IMR_ETRGS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_ETRGS; + } else { + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = TC_IMR_ETRGS; + } +} + +static inline void hri_tc_clear_IMR_ETRGS_bit(const void *const hw, uint8_t submodule_index) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = TC_IMR_ETRGS; +} + +static inline void hri_tc_set_IMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_imr_reg_t mask) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = mask; +} + +static inline hri_tc_imr_reg_t hri_tc_get_IMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_imr_reg_t hri_tc_read_IMR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_IMR; +} + +static inline void hri_tc_write_IMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_imr_reg_t data) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IER = data; + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = ~data; +} + +static inline void hri_tc_clear_IMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_imr_reg_t mask) +{ + ((Tc *)hw)->TcChannel[submodule_index].TC_IDR = mask; +} + +static inline hri_tc_rab_reg_t hri_tc_get_RAB_RAB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_rab_reg_t mask) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_RAB & TC_RAB_RAB(mask)) >> TC_RAB_RAB_Pos; +} + +static inline hri_tc_rab_reg_t hri_tc_read_RAB_RAB_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_RAB & TC_RAB_RAB_Msk) >> TC_RAB_RAB_Pos; +} + +static inline hri_tc_rab_reg_t hri_tc_get_RAB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RAB; + tmp &= mask; + return tmp; +} + +static inline hri_tc_rab_reg_t hri_tc_read_RAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_RAB; +} + +static inline hri_tc_cv_reg_t hri_tc_get_CV_CV_bf(const void *const hw, uint8_t submodule_index, hri_tc_cv_reg_t mask) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_CV & TC_CV_CV(mask)) >> TC_CV_CV_Pos; +} + +static inline hri_tc_cv_reg_t hri_tc_read_CV_CV_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_CV & TC_CV_CV_Msk) >> TC_CV_CV_Pos; +} + +static inline hri_tc_cv_reg_t hri_tc_get_CV_reg(const void *const hw, uint8_t submodule_index, hri_tc_cv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CV; + tmp &= mask; + return tmp; +} + +static inline hri_tc_cv_reg_t hri_tc_read_CV_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_CV; +} + +static inline bool hri_tc_get_SR_COVFS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_COVFS) > 0; +} + +static inline bool hri_tc_get_SR_LOVRS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_LOVRS) > 0; +} + +static inline bool hri_tc_get_SR_CPAS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_CPAS) > 0; +} + +static inline bool hri_tc_get_SR_CPBS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_CPBS) > 0; +} + +static inline bool hri_tc_get_SR_CPCS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_CPCS) > 0; +} + +static inline bool hri_tc_get_SR_LDRAS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_LDRAS) > 0; +} + +static inline bool hri_tc_get_SR_LDRBS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_LDRBS) > 0; +} + +static inline bool hri_tc_get_SR_ETRGS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_ETRGS) > 0; +} + +static inline bool hri_tc_get_SR_CLKSTA_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_CLKSTA) > 0; +} + +static inline bool hri_tc_get_SR_MTIOA_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_MTIOA) > 0; +} + +static inline bool hri_tc_get_SR_MTIOB_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Tc *)hw)->TcChannel[submodule_index].TC_SR & TC_SR_MTIOB) > 0; +} + +static inline hri_tc_sr_reg_t hri_tc_get_SR_reg(const void *const hw, uint8_t submodule_index, hri_tc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_sr_reg_t hri_tc_read_SR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_SR; +} + +static inline void hri_tc_set_CMR_CLKI_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_CLKI_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CLKI) >> TC_CMR_CLKI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_CLKI_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CLKI; + tmp |= value << TC_CMR_CLKI_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CLKI_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CLKI_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CLKI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDBSTOP) >> TC_CMR_CAPTURE_LDBSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDBSTOP; + tmp |= value << TC_CMR_CAPTURE_LDBSTOP_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_LDBSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_LDBSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_CPCSTOP) >> TC_CMR_WAVEFORM_CPCSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_CPCSTOP; + tmp |= value << TC_CMR_WAVEFORM_CPCSTOP_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_CPCSTOP_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_CPCSTOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_CAPTURE_LDBDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_CAPTURE_LDBDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDBDIS) >> TC_CMR_CAPTURE_LDBDIS_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_LDBDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDBDIS; + tmp |= value << TC_CMR_CAPTURE_LDBDIS_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_LDBDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_LDBDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_LDBDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_CPCDIS) >> TC_CMR_WAVEFORM_CPCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_CPCDIS; + tmp |= value << TC_CMR_WAVEFORM_CPCDIS_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_CPCDIS_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_CPCDIS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_CAPTURE_ABETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_CAPTURE_ABETRG_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ABETRG) >> TC_CMR_CAPTURE_ABETRG_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_ABETRG_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_ABETRG; + tmp |= value << TC_CMR_CAPTURE_ABETRG_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_ABETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_ABETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_ABETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_WAVEFORM_ENETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_WAVEFORM_ENETRG_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ENETRG) >> TC_CMR_WAVEFORM_ENETRG_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_ENETRG_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ENETRG; + tmp |= value << TC_CMR_WAVEFORM_ENETRG_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_ENETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_ENETRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_ENETRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_CAPTURE_CPCTRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_CAPTURE_CPCTRG_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_CPCTRG) >> TC_CMR_CAPTURE_CPCTRG_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_CPCTRG_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_CPCTRG; + tmp |= value << TC_CMR_CAPTURE_CPCTRG_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_CPCTRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_CPCTRG_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_CPCTRG; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_WAVE_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CMR_WAVE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVE) >> TC_CMR_WAVE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CMR_WAVE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVE; + tmp |= value << TC_CMR_WAVE_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVE_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVE_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_TCCLKS(mask)) >> TC_CMR_TCCLKS_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_TCCLKS_Msk; + tmp |= TC_CMR_TCCLKS(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_TCCLKS(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_TCCLKS_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_TCCLKS_Msk) >> TC_CMR_TCCLKS_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_BURST_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_BURST_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_BURST(mask)) >> TC_CMR_BURST_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_BURST_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_BURST_Msk; + tmp |= TC_CMR_BURST(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_BURST_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_BURST_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_BURST(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_BURST_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_BURST_Msk) >> TC_CMR_BURST_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ETRGEDG(mask)) >> TC_CMR_CAPTURE_ETRGEDG_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_ETRGEDG_Msk; + tmp |= TC_CMR_CAPTURE_ETRGEDG(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_ETRGEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_CAPTURE_ETRGEDG_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_ETRGEDG_Msk) >> TC_CMR_CAPTURE_ETRGEDG_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVTEDG(mask)) >> TC_CMR_WAVEFORM_EEVTEDG_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_EEVTEDG_Msk; + tmp |= TC_CMR_WAVEFORM_EEVTEDG(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_EEVTEDG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_EEVTEDG_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVTEDG_Msk) >> TC_CMR_WAVEFORM_EEVTEDG_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVT(mask)) >> TC_CMR_WAVEFORM_EEVT_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_EEVT_Msk; + tmp |= TC_CMR_WAVEFORM_EEVT(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_EEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_EEVT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_EEVT_Msk) >> TC_CMR_WAVEFORM_EEVT_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_WAVSEL(mask)) >> TC_CMR_WAVEFORM_WAVSEL_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_WAVSEL_Msk; + tmp |= TC_CMR_WAVEFORM_WAVSEL(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_WAVSEL(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_WAVSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_WAVSEL_Msk) >> TC_CMR_WAVEFORM_WAVSEL_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRA(mask)) >> TC_CMR_CAPTURE_LDRA_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDRA_Msk; + tmp |= TC_CMR_CAPTURE_LDRA(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_LDRA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_CAPTURE_LDRA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRA_Msk) >> TC_CMR_CAPTURE_LDRA_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPA(mask)) >> TC_CMR_WAVEFORM_ACPA_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ACPA_Msk; + tmp |= TC_CMR_WAVEFORM_ACPA(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_ACPA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_ACPA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPA_Msk) >> TC_CMR_WAVEFORM_ACPA_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRB(mask)) >> TC_CMR_CAPTURE_LDRB_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_LDRB_Msk; + tmp |= TC_CMR_CAPTURE_LDRB(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_LDRB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_CAPTURE_LDRB_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_LDRB_Msk) >> TC_CMR_CAPTURE_LDRB_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPC(mask)) >> TC_CMR_WAVEFORM_ACPC_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ACPC_Msk; + tmp |= TC_CMR_WAVEFORM_ACPC(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_ACPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_ACPC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ACPC_Msk) >> TC_CMR_WAVEFORM_ACPC_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_SBSMPLR(mask)) >> TC_CMR_CAPTURE_SBSMPLR_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_CAPTURE_SBSMPLR_Msk; + tmp |= TC_CMR_CAPTURE_SBSMPLR(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_CAPTURE_SBSMPLR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_CAPTURE_SBSMPLR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_CAPTURE_SBSMPLR_Msk) >> TC_CMR_CAPTURE_SBSMPLR_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_AEEVT(mask)) >> TC_CMR_WAVEFORM_AEEVT_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_AEEVT_Msk; + tmp |= TC_CMR_WAVEFORM_AEEVT(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_AEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_AEEVT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_AEEVT_Msk) >> TC_CMR_WAVEFORM_AEEVT_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ASWTRG(mask)) >> TC_CMR_WAVEFORM_ASWTRG_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_ASWTRG_Msk; + tmp |= TC_CMR_WAVEFORM_ASWTRG(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_ASWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_ASWTRG_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_ASWTRG_Msk) >> TC_CMR_WAVEFORM_ASWTRG_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPB(mask)) >> TC_CMR_WAVEFORM_BCPB_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BCPB_Msk; + tmp |= TC_CMR_WAVEFORM_BCPB(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_BCPB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_BCPB_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPB_Msk) >> TC_CMR_WAVEFORM_BCPB_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPC(mask)) >> TC_CMR_WAVEFORM_BCPC_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BCPC_Msk; + tmp |= TC_CMR_WAVEFORM_BCPC(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_BCPC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_BCPC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BCPC_Msk) >> TC_CMR_WAVEFORM_BCPC_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BEEVT(mask)) >> TC_CMR_WAVEFORM_BEEVT_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BEEVT_Msk; + tmp |= TC_CMR_WAVEFORM_BEEVT(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_BEEVT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_BEEVT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BEEVT_Msk) >> TC_CMR_WAVEFORM_BEEVT_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BSWTRG(mask)) >> TC_CMR_WAVEFORM_BSWTRG_Pos; + return tmp; +} + +static inline void hri_tc_write_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= ~TC_CMR_WAVEFORM_BSWTRG_Msk; + tmp |= TC_CMR_WAVEFORM_BSWTRG(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index, + hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= TC_CMR_WAVEFORM_BSWTRG(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_WAVEFORM_BSWTRG_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp = (tmp & TC_CMR_WAVEFORM_BSWTRG_Msk) >> TC_CMR_WAVEFORM_BSWTRG_Pos; + return tmp; +} + +static inline void hri_tc_set_CMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_get_CMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_cmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cmr_reg_t hri_tc_read_CMR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_CMR; +} + +static inline void hri_tc_set_SMMR_GCEN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR |= TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_SMMR_GCEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; + tmp = (tmp & TC_SMMR_GCEN) >> TC_SMMR_GCEN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_SMMR_GCEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; + tmp &= ~TC_SMMR_GCEN; + tmp |= value << TC_SMMR_GCEN_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_SMMR_GCEN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR &= ~TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_SMMR_GCEN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR ^= TC_SMMR_GCEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_SMMR_DOWN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR |= TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_SMMR_DOWN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; + tmp = (tmp & TC_SMMR_DOWN) >> TC_SMMR_DOWN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_SMMR_DOWN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; + tmp &= ~TC_SMMR_DOWN; + tmp |= value << TC_SMMR_DOWN_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_SMMR_DOWN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR &= ~TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_SMMR_DOWN_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR ^= TC_SMMR_DOWN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_SMMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_smmr_reg_t hri_tc_get_SMMR_reg(const void *const hw, uint8_t submodule_index, + hri_tc_smmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_SMMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_smmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_SMMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_SMMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_smmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_smmr_reg_t hri_tc_read_SMMR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_SMMR; +} + +static inline void hri_tc_set_RA_RA_bf(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA |= TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tc_get_RA_RA_bf(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RA; + tmp = (tmp & TC_RA_RA(mask)) >> TC_RA_RA_Pos; + return tmp; +} + +static inline void hri_tc_write_RA_RA_bf(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RA; + tmp &= ~TC_RA_RA_Msk; + tmp |= TC_RA_RA(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RA_RA_bf(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA &= ~TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RA_RA_bf(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA ^= TC_RA_RA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tc_read_RA_RA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RA; + tmp = (tmp & TC_RA_RA_Msk) >> TC_RA_RA_Pos; + return tmp; +} + +static inline void hri_tc_set_RA_reg(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tc_get_RA_reg(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RA; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_RA_reg(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RA_reg(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RA_reg(const void *const hw, uint8_t submodule_index, hri_tc_ra_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RA ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ra_reg_t hri_tc_read_RA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_RA; +} + +static inline void hri_tc_set_RB_RB_bf(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB |= TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tc_get_RB_RB_bf(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RB; + tmp = (tmp & TC_RB_RB(mask)) >> TC_RB_RB_Pos; + return tmp; +} + +static inline void hri_tc_write_RB_RB_bf(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RB; + tmp &= ~TC_RB_RB_Msk; + tmp |= TC_RB_RB(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RB_RB_bf(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB &= ~TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RB_RB_bf(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB ^= TC_RB_RB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tc_read_RB_RB_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RB; + tmp = (tmp & TC_RB_RB_Msk) >> TC_RB_RB_Pos; + return tmp; +} + +static inline void hri_tc_set_RB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tc_get_RB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RB; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_RB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RB_reg(const void *const hw, uint8_t submodule_index, hri_tc_rb_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RB ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rb_reg_t hri_tc_read_RB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_RB; +} + +static inline void hri_tc_set_RC_RC_bf(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC |= TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tc_get_RC_RC_bf(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RC; + tmp = (tmp & TC_RC_RC(mask)) >> TC_RC_RC_Pos; + return tmp; +} + +static inline void hri_tc_write_RC_RC_bf(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RC; + tmp &= ~TC_RC_RC_Msk; + tmp |= TC_RC_RC(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RC_RC_bf(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC &= ~TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RC_RC_bf(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC ^= TC_RC_RC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tc_read_RC_RC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RC; + tmp = (tmp & TC_RC_RC_Msk) >> TC_RC_RC_Pos; + return tmp; +} + +static inline void hri_tc_set_RC_reg(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tc_get_RC_reg(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_RC; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_RC_reg(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_RC_reg(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_RC_reg(const void *const hw, uint8_t submodule_index, hri_tc_rc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_RC ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_rc_reg_t hri_tc_read_RC_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_RC; +} + +static inline void hri_tc_set_EMR_NODIVCLK_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR |= TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EMR_NODIVCLK_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp = (tmp & TC_EMR_NODIVCLK) >> TC_EMR_NODIVCLK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EMR_NODIVCLK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp &= ~TC_EMR_NODIVCLK; + tmp |= value << TC_EMR_NODIVCLK_Pos; + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EMR_NODIVCLK_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR &= ~TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EMR_NODIVCLK_bit(const void *const hw, uint8_t submodule_index) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR ^= TC_EMR_NODIVCLK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR |= TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_get_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index, + hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCA(mask)) >> TC_EMR_TRIGSRCA_Pos; + return tmp; +} + +static inline void hri_tc_write_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp &= ~TC_EMR_TRIGSRCA_Msk; + tmp |= TC_EMR_TRIGSRCA(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR &= ~TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR ^= TC_EMR_TRIGSRCA(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_read_EMR_TRIGSRCA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCA_Msk) >> TC_EMR_TRIGSRCA_Pos; + return tmp; +} + +static inline void hri_tc_set_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR |= TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_get_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index, + hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCB(mask)) >> TC_EMR_TRIGSRCB_Pos; + return tmp; +} + +static inline void hri_tc_write_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp &= ~TC_EMR_TRIGSRCB_Msk; + tmp |= TC_EMR_TRIGSRCB(data); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR &= ~TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR ^= TC_EMR_TRIGSRCB(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_read_EMR_TRIGSRCB_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp = (tmp & TC_EMR_TRIGSRCB_Msk) >> TC_EMR_TRIGSRCB_Pos; + return tmp; +} + +static inline void hri_tc_set_EMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_get_EMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EMR_reg(const void *const hw, uint8_t submodule_index, hri_tc_emr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_EMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_emr_reg_t hri_tc_read_EMR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tc *)hw)->TcChannel[submodule_index].TC_EMR; +} + +static inline void hri_tc_write_CCR_reg(const void *const hw, uint8_t submodule_index, hri_tc_ccr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TcChannel[submodule_index].TC_CCR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_QIMR_IDX_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QIMR & TC_QIMR_IDX) > 0; +} + +static inline bool hri_tc_get_QIMR_DIRCHG_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QIMR & TC_QIMR_DIRCHG) > 0; +} + +static inline bool hri_tc_get_QIMR_QERR_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QIMR & TC_QIMR_QERR) > 0; +} + +static inline bool hri_tc_get_QIMR_MPE_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QIMR & TC_QIMR_MPE) > 0; +} + +static inline hri_tc_qimr_reg_t hri_tc_get_QIMR_reg(const void *const hw, hri_tc_qimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_QIMR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_qimr_reg_t hri_tc_read_QIMR_reg(const void *const hw) +{ + return ((Tc *)hw)->TC_QIMR; +} + +static inline bool hri_tc_get_QISR_IDX_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QISR & TC_QISR_IDX) > 0; +} + +static inline bool hri_tc_get_QISR_DIRCHG_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QISR & TC_QISR_DIRCHG) > 0; +} + +static inline bool hri_tc_get_QISR_QERR_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QISR & TC_QISR_QERR) > 0; +} + +static inline bool hri_tc_get_QISR_MPE_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QISR & TC_QISR_MPE) > 0; +} + +static inline bool hri_tc_get_QISR_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->TC_QISR & TC_QISR_DIR) > 0; +} + +static inline hri_tc_qisr_reg_t hri_tc_get_QISR_reg(const void *const hw, hri_tc_qisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_QISR; + tmp &= mask; + return tmp; +} + +static inline hri_tc_qisr_reg_t hri_tc_read_QISR_reg(const void *const hw) +{ + return ((Tc *)hw)->TC_QISR; +} + +static inline void hri_tc_set_BMR_QDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_QDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_QDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_QDEN) >> TC_BMR_QDEN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_QDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_QDEN; + tmp |= value << TC_BMR_QDEN_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_QDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_QDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_QDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_QDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_POSEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_POSEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_POSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_POSEN) >> TC_BMR_POSEN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_POSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_POSEN; + tmp |= value << TC_BMR_POSEN_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_POSEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_POSEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_POSEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_POSEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_SPEEDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_SPEEDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_SPEEDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_SPEEDEN) >> TC_BMR_SPEEDEN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_SPEEDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_SPEEDEN; + tmp |= value << TC_BMR_SPEEDEN_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_SPEEDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_SPEEDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_SPEEDEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_SPEEDEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_QDTRANS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_QDTRANS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_QDTRANS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_QDTRANS) >> TC_BMR_QDTRANS_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_QDTRANS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_QDTRANS; + tmp |= value << TC_BMR_QDTRANS_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_QDTRANS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_QDTRANS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_QDTRANS_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_QDTRANS; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_EDGPHA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_EDGPHA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_EDGPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_EDGPHA) >> TC_BMR_EDGPHA_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_EDGPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_EDGPHA; + tmp |= value << TC_BMR_EDGPHA_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_EDGPHA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_EDGPHA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_EDGPHA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_EDGPHA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_INVA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_INVA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_INVA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_INVA) >> TC_BMR_INVA_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_INVA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_INVA; + tmp |= value << TC_BMR_INVA_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_INVA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_INVA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_INVA_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_INVA; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_INVB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_INVB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_INVB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_INVB) >> TC_BMR_INVB_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_INVB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_INVB; + tmp |= value << TC_BMR_INVB_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_INVB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_INVB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_INVB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_INVB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_INVIDX_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_INVIDX; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_INVIDX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_INVIDX) >> TC_BMR_INVIDX_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_INVIDX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_INVIDX; + tmp |= value << TC_BMR_INVIDX_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_INVIDX_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_INVIDX; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_INVIDX_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_INVIDX; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_SWAP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_SWAP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_SWAP) >> TC_BMR_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_SWAP; + tmp |= value << TC_BMR_SWAP_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_SWAP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_SWAP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_SWAP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_SWAP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_IDXPHB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_IDXPHB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_IDXPHB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_IDXPHB) >> TC_BMR_IDXPHB_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_IDXPHB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_IDXPHB; + tmp |= value << TC_BMR_IDXPHB_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_IDXPHB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_IDXPHB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_IDXPHB_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_IDXPHB; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_AUTOC_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_AUTOC; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_BMR_AUTOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_AUTOC) >> TC_BMR_AUTOC_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_BMR_AUTOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_AUTOC; + tmp |= value << TC_BMR_AUTOC_Pos; + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_AUTOC_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_AUTOC; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_AUTOC_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_AUTOC; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_BMR_TC0XC0S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_TC0XC0S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_TC0XC0S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC0XC0S(mask)) >> TC_BMR_TC0XC0S_Pos; + return tmp; +} + +static inline void hri_tc_write_BMR_TC0XC0S_bf(const void *const hw, hri_tc_bmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_TC0XC0S_Msk; + tmp |= TC_BMR_TC0XC0S(data); + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_TC0XC0S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_TC0XC0S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_TC0XC0S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_TC0XC0S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_TC0XC0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC0XC0S_Msk) >> TC_BMR_TC0XC0S_Pos; + return tmp; +} + +static inline void hri_tc_set_BMR_TC1XC1S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_TC1XC1S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_TC1XC1S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC1XC1S(mask)) >> TC_BMR_TC1XC1S_Pos; + return tmp; +} + +static inline void hri_tc_write_BMR_TC1XC1S_bf(const void *const hw, hri_tc_bmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_TC1XC1S_Msk; + tmp |= TC_BMR_TC1XC1S(data); + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_TC1XC1S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_TC1XC1S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_TC1XC1S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_TC1XC1S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_TC1XC1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC1XC1S_Msk) >> TC_BMR_TC1XC1S_Pos; + return tmp; +} + +static inline void hri_tc_set_BMR_TC2XC2S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_TC2XC2S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_TC2XC2S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC2XC2S(mask)) >> TC_BMR_TC2XC2S_Pos; + return tmp; +} + +static inline void hri_tc_write_BMR_TC2XC2S_bf(const void *const hw, hri_tc_bmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_TC2XC2S_Msk; + tmp |= TC_BMR_TC2XC2S(data); + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_TC2XC2S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_TC2XC2S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_TC2XC2S_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_TC2XC2S(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_TC2XC2S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_TC2XC2S_Msk) >> TC_BMR_TC2XC2S_Pos; + return tmp; +} + +static inline void hri_tc_set_BMR_MAXFILT_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_MAXFILT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_MAXFILT_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_MAXFILT(mask)) >> TC_BMR_MAXFILT_Pos; + return tmp; +} + +static inline void hri_tc_write_BMR_MAXFILT_bf(const void *const hw, hri_tc_bmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_MAXFILT_Msk; + tmp |= TC_BMR_MAXFILT(data); + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_MAXFILT_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_MAXFILT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_MAXFILT_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_MAXFILT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_MAXFILT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_MAXFILT_Msk) >> TC_BMR_MAXFILT_Pos; + return tmp; +} + +static inline void hri_tc_set_BMR_MAXCMP_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= TC_BMR_MAXCMP(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_MAXCMP_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_MAXCMP(mask)) >> TC_BMR_MAXCMP_Pos; + return tmp; +} + +static inline void hri_tc_write_BMR_MAXCMP_bf(const void *const hw, hri_tc_bmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_BMR; + tmp &= ~TC_BMR_MAXCMP_Msk; + tmp |= TC_BMR_MAXCMP(data); + ((Tc *)hw)->TC_BMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_MAXCMP_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~TC_BMR_MAXCMP(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_MAXCMP_bf(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= TC_BMR_MAXCMP(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp = (tmp & TC_BMR_MAXCMP_Msk) >> TC_BMR_MAXCMP_Pos; + return tmp; +} + +static inline void hri_tc_set_BMR_reg(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_get_BMR_reg(const void *const hw, hri_tc_bmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_BMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_BMR_reg(const void *const hw, hri_tc_bmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_BMR_reg(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_BMR_reg(const void *const hw, hri_tc_bmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_bmr_reg_t hri_tc_read_BMR_reg(const void *const hw) +{ + return ((Tc *)hw)->TC_BMR; +} + +static inline void hri_tc_set_FMR_ENCF0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR |= TC_FMR_ENCF0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_FMR_ENCF0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_FMR; + tmp = (tmp & TC_FMR_ENCF0) >> TC_FMR_ENCF0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_FMR_ENCF0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_FMR; + tmp &= ~TC_FMR_ENCF0; + tmp |= value << TC_FMR_ENCF0_Pos; + ((Tc *)hw)->TC_FMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_FMR_ENCF0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR &= ~TC_FMR_ENCF0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_FMR_ENCF0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR ^= TC_FMR_ENCF0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_FMR_ENCF1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR |= TC_FMR_ENCF1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_FMR_ENCF1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_FMR; + tmp = (tmp & TC_FMR_ENCF1) >> TC_FMR_ENCF1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_FMR_ENCF1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_FMR; + tmp &= ~TC_FMR_ENCF1; + tmp |= value << TC_FMR_ENCF1_Pos; + ((Tc *)hw)->TC_FMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_FMR_ENCF1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR &= ~TC_FMR_ENCF1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_FMR_ENCF1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR ^= TC_FMR_ENCF1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_FMR_reg(const void *const hw, hri_tc_fmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_fmr_reg_t hri_tc_get_FMR_reg(const void *const hw, hri_tc_fmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_FMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_FMR_reg(const void *const hw, hri_tc_fmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_FMR_reg(const void *const hw, hri_tc_fmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_FMR_reg(const void *const hw, hri_tc_fmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_FMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_fmr_reg_t hri_tc_read_FMR_reg(const void *const hw) +{ + return ((Tc *)hw)->TC_FMR; +} + +static inline void hri_tc_set_WPMR_WPEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR |= TC_WPMR_WPEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_WPMR; + tmp = (tmp & TC_WPMR_WPEN) >> TC_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_WPMR; + tmp &= ~TC_WPMR_WPEN; + tmp |= value << TC_WPMR_WPEN_Pos; + ((Tc *)hw)->TC_WPMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WPMR_WPEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR &= ~TC_WPMR_WPEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WPMR_WPEN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR ^= TC_WPMR_WPEN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_WPMR_WPKEY_bf(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR |= TC_WPMR_WPKEY(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wpmr_reg_t hri_tc_get_WPMR_WPKEY_bf(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_WPMR; + tmp = (tmp & TC_WPMR_WPKEY(mask)) >> TC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_tc_write_WPMR_WPKEY_bf(const void *const hw, hri_tc_wpmr_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->TC_WPMR; + tmp &= ~TC_WPMR_WPKEY_Msk; + tmp |= TC_WPMR_WPKEY(data); + ((Tc *)hw)->TC_WPMR = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WPMR_WPKEY_bf(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR &= ~TC_WPMR_WPKEY(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WPMR_WPKEY_bf(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR ^= TC_WPMR_WPKEY(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wpmr_reg_t hri_tc_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_WPMR; + tmp = (tmp & TC_WPMR_WPKEY_Msk) >> TC_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_tc_set_WPMR_reg(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wpmr_reg_t hri_tc_get_WPMR_reg(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->TC_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WPMR_reg(const void *const hw, hri_tc_wpmr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WPMR_reg(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WPMR_reg(const void *const hw, hri_tc_wpmr_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_WPMR ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wpmr_reg_t hri_tc_read_WPMR_reg(const void *const hw) +{ + return ((Tc *)hw)->TC_WPMR; +} + +static inline void hri_tc_write_BCR_reg(const void *const hw, hri_tc_bcr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_BCR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_write_QIER_reg(const void *const hw, hri_tc_qier_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_QIER = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_write_QIDR_reg(const void *const hw, hri_tc_qidr_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->TC_QIDR = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcchannel_set_CMR_LDBSTOP_bit(a) hri_tcchannel_set_CMR_CAPTURE_LDBSTOP_bit(a) +#define hri_tcchannel_get_CMR_LDBSTOP_bit(a) hri_tcchannel_get_CMR_CAPTURE_LDBSTOP_bit(a) +#define hri_tcchannel_write_CMR_LDBSTOP_bit(a, b) hri_tcchannel_write_CMR_CAPTURE_LDBSTOP_bit(a, b) +#define hri_tcchannel_clear_CMR_LDBSTOP_bit(a) hri_tcchannel_clear_CMR_CAPTURE_LDBSTOP_bit(a) +#define hri_tcchannel_toggle_CMR_LDBSTOP_bit(a) hri_tcchannel_toggle_CMR_CAPTURE_LDBSTOP_bit(a) +#define hri_tcchannel_set_CMR_LDBDIS_bit(a) hri_tcchannel_set_CMR_CAPTURE_LDBDIS_bit(a) +#define hri_tcchannel_get_CMR_LDBDIS_bit(a) hri_tcchannel_get_CMR_CAPTURE_LDBDIS_bit(a) +#define hri_tcchannel_write_CMR_LDBDIS_bit(a, b) hri_tcchannel_write_CMR_CAPTURE_LDBDIS_bit(a, b) +#define hri_tcchannel_clear_CMR_LDBDIS_bit(a) hri_tcchannel_clear_CMR_CAPTURE_LDBDIS_bit(a) +#define hri_tcchannel_toggle_CMR_LDBDIS_bit(a) hri_tcchannel_toggle_CMR_CAPTURE_LDBDIS_bit(a) +#define hri_tcchannel_set_CMR_ABETRG_bit(a) hri_tcchannel_set_CMR_CAPTURE_ABETRG_bit(a) +#define hri_tcchannel_get_CMR_ABETRG_bit(a) hri_tcchannel_get_CMR_CAPTURE_ABETRG_bit(a) +#define hri_tcchannel_write_CMR_ABETRG_bit(a, b) hri_tcchannel_write_CMR_CAPTURE_ABETRG_bit(a, b) +#define hri_tcchannel_clear_CMR_ABETRG_bit(a) hri_tcchannel_clear_CMR_CAPTURE_ABETRG_bit(a) +#define hri_tcchannel_toggle_CMR_ABETRG_bit(a) hri_tcchannel_toggle_CMR_CAPTURE_ABETRG_bit(a) +#define hri_tcchannel_set_CMR_CPCTRG_bit(a) hri_tcchannel_set_CMR_CAPTURE_CPCTRG_bit(a) +#define hri_tcchannel_get_CMR_CPCTRG_bit(a) hri_tcchannel_get_CMR_CAPTURE_CPCTRG_bit(a) +#define hri_tcchannel_write_CMR_CPCTRG_bit(a, b) hri_tcchannel_write_CMR_CAPTURE_CPCTRG_bit(a, b) +#define hri_tcchannel_clear_CMR_CPCTRG_bit(a) hri_tcchannel_clear_CMR_CAPTURE_CPCTRG_bit(a) +#define hri_tcchannel_toggle_CMR_CPCTRG_bit(a) hri_tcchannel_toggle_CMR_CAPTURE_CPCTRG_bit(a) +#define hri_tcchannel_set_CMR_ETRGEDG_bf(a, b) hri_tcchannel_set_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tcchannel_get_CMR_ETRGEDG_bf(a, b) hri_tcchannel_get_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tcchannel_write_CMR_ETRGEDG_bf(a, b) hri_tcchannel_write_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tcchannel_clear_CMR_ETRGEDG_bf(a, b) hri_tcchannel_clear_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tcchannel_toggle_CMR_ETRGEDG_bf(a, b) hri_tcchannel_toggle_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tcchannel_read_CMR_ETRGEDG_bf(a) hri_tcchannel_read_CMR_CAPTURE_ETRGEDG_bf(a) +#define hri_tcchannel_set_CMR_LDRA_bf(a, b) hri_tcchannel_set_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tcchannel_get_CMR_LDRA_bf(a, b) hri_tcchannel_get_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tcchannel_write_CMR_LDRA_bf(a, b) hri_tcchannel_write_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tcchannel_clear_CMR_LDRA_bf(a, b) hri_tcchannel_clear_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tcchannel_toggle_CMR_LDRA_bf(a, b) hri_tcchannel_toggle_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tcchannel_read_CMR_LDRA_bf(a) hri_tcchannel_read_CMR_CAPTURE_LDRA_bf(a) +#define hri_tcchannel_set_CMR_LDRB_bf(a, b) hri_tcchannel_set_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tcchannel_get_CMR_LDRB_bf(a, b) hri_tcchannel_get_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tcchannel_write_CMR_LDRB_bf(a, b) hri_tcchannel_write_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tcchannel_clear_CMR_LDRB_bf(a, b) hri_tcchannel_clear_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tcchannel_toggle_CMR_LDRB_bf(a, b) hri_tcchannel_toggle_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tcchannel_read_CMR_LDRB_bf(a) hri_tcchannel_read_CMR_CAPTURE_LDRB_bf(a) +#define hri_tcchannel_set_CMR_SBSMPLR_bf(a, b) hri_tcchannel_set_CMR_CAPTURE_SBSMPLR_bf(a, b) +#define hri_tcchannel_get_CMR_SBSMPLR_bf(a, b) hri_tcchannel_get_CMR_CAPTURE_SBSMPLR_bf(a, b) +#define hri_tcchannel_write_CMR_SBSMPLR_bf(a, b) hri_tcchannel_write_CMR_CAPTURE_SBSMPLR_bf(a, b) +#define hri_tcchannel_clear_CMR_SBSMPLR_bf(a, b) hri_tcchannel_clear_CMR_CAPTURE_SBSMPLR_bf(a, b) +#define hri_tcchannel_toggle_CMR_SBSMPLR_bf(a, b) hri_tcchannel_toggle_CMR_CAPTURE_SBSMPLR_bf(a, b) +#define hri_tcchannel_read_CMR_SBSMPLR_bf(a) hri_tcchannel_read_CMR_CAPTURE_SBSMPLR_bf(a) +#define hri_tc_set_CMR_LDBSTOP_bit(a, b) hri_tc_set_CMR_CAPTURE_LDBSTOP_bit(a, b) +#define hri_tc_get_CMR_LDBSTOP_bit(a, b) hri_tc_get_CMR_CAPTURE_LDBSTOP_bit(a, b) +#define hri_tc_write_CMR_LDBSTOP_bit(a, b, c) hri_tc_write_CMR_CAPTURE_LDBSTOP_bit(a, b, c) +#define hri_tc_clear_CMR_LDBSTOP_bit(a, b) hri_tc_clear_CMR_CAPTURE_LDBSTOP_bit(a, b) +#define hri_tc_toggle_CMR_LDBSTOP_bit(a, b) hri_tc_toggle_CMR_CAPTURE_LDBSTOP_bit(a, b) +#define hri_tc_set_CMR_LDBDIS_bit(a, b) hri_tc_set_CMR_CAPTURE_LDBDIS_bit(a, b) +#define hri_tc_get_CMR_LDBDIS_bit(a, b) hri_tc_get_CMR_CAPTURE_LDBDIS_bit(a, b) +#define hri_tc_write_CMR_LDBDIS_bit(a, b, c) hri_tc_write_CMR_CAPTURE_LDBDIS_bit(a, b, c) +#define hri_tc_clear_CMR_LDBDIS_bit(a, b) hri_tc_clear_CMR_CAPTURE_LDBDIS_bit(a, b) +#define hri_tc_toggle_CMR_LDBDIS_bit(a, b) hri_tc_toggle_CMR_CAPTURE_LDBDIS_bit(a, b) +#define hri_tc_set_CMR_ABETRG_bit(a, b) hri_tc_set_CMR_CAPTURE_ABETRG_bit(a, b) +#define hri_tc_get_CMR_ABETRG_bit(a, b) hri_tc_get_CMR_CAPTURE_ABETRG_bit(a, b) +#define hri_tc_write_CMR_ABETRG_bit(a, b, c) hri_tc_write_CMR_CAPTURE_ABETRG_bit(a, b, c) +#define hri_tc_clear_CMR_ABETRG_bit(a, b) hri_tc_clear_CMR_CAPTURE_ABETRG_bit(a, b) +#define hri_tc_toggle_CMR_ABETRG_bit(a, b) hri_tc_toggle_CMR_CAPTURE_ABETRG_bit(a, b) +#define hri_tc_set_CMR_CPCTRG_bit(a, b) hri_tc_set_CMR_CAPTURE_CPCTRG_bit(a, b) +#define hri_tc_get_CMR_CPCTRG_bit(a, b) hri_tc_get_CMR_CAPTURE_CPCTRG_bit(a, b) +#define hri_tc_write_CMR_CPCTRG_bit(a, b, c) hri_tc_write_CMR_CAPTURE_CPCTRG_bit(a, b, c) +#define hri_tc_clear_CMR_CPCTRG_bit(a, b) hri_tc_clear_CMR_CAPTURE_CPCTRG_bit(a, b) +#define hri_tc_toggle_CMR_CPCTRG_bit(a, b) hri_tc_toggle_CMR_CAPTURE_CPCTRG_bit(a, b) +#define hri_tc_set_CMR_ETRGEDG_bf(a, b, c) hri_tc_set_CMR_CAPTURE_ETRGEDG_bf(a, b, c) +#define hri_tc_get_CMR_ETRGEDG_bf(a, b, c) hri_tc_get_CMR_CAPTURE_ETRGEDG_bf(a, b, c) +#define hri_tc_write_CMR_ETRGEDG_bf(a, b, c) hri_tc_write_CMR_CAPTURE_ETRGEDG_bf(a, b, c) +#define hri_tc_clear_CMR_ETRGEDG_bf(a, b, c) hri_tc_clear_CMR_CAPTURE_ETRGEDG_bf(a, b, c) +#define hri_tc_toggle_CMR_ETRGEDG_bf(a, b, c) hri_tc_toggle_CMR_CAPTURE_ETRGEDG_bf(a, b, c) +#define hri_tc_read_CMR_ETRGEDG_bf(a, b) hri_tc_read_CMR_CAPTURE_ETRGEDG_bf(a, b) +#define hri_tc_set_CMR_LDRA_bf(a, b, c) hri_tc_set_CMR_CAPTURE_LDRA_bf(a, b, c) +#define hri_tc_get_CMR_LDRA_bf(a, b, c) hri_tc_get_CMR_CAPTURE_LDRA_bf(a, b, c) +#define hri_tc_write_CMR_LDRA_bf(a, b, c) hri_tc_write_CMR_CAPTURE_LDRA_bf(a, b, c) +#define hri_tc_clear_CMR_LDRA_bf(a, b, c) hri_tc_clear_CMR_CAPTURE_LDRA_bf(a, b, c) +#define hri_tc_toggle_CMR_LDRA_bf(a, b, c) hri_tc_toggle_CMR_CAPTURE_LDRA_bf(a, b, c) +#define hri_tc_read_CMR_LDRA_bf(a, b) hri_tc_read_CMR_CAPTURE_LDRA_bf(a, b) +#define hri_tc_set_CMR_LDRB_bf(a, b, c) hri_tc_set_CMR_CAPTURE_LDRB_bf(a, b, c) +#define hri_tc_get_CMR_LDRB_bf(a, b, c) hri_tc_get_CMR_CAPTURE_LDRB_bf(a, b, c) +#define hri_tc_write_CMR_LDRB_bf(a, b, c) hri_tc_write_CMR_CAPTURE_LDRB_bf(a, b, c) +#define hri_tc_clear_CMR_LDRB_bf(a, b, c) hri_tc_clear_CMR_CAPTURE_LDRB_bf(a, b, c) +#define hri_tc_toggle_CMR_LDRB_bf(a, b, c) hri_tc_toggle_CMR_CAPTURE_LDRB_bf(a, b, c) +#define hri_tc_read_CMR_LDRB_bf(a, b) hri_tc_read_CMR_CAPTURE_LDRB_bf(a, b) +#define hri_tc_set_CMR_SBSMPLR_bf(a, b, c) hri_tc_set_CMR_CAPTURE_SBSMPLR_bf(a, b, c) +#define hri_tc_get_CMR_SBSMPLR_bf(a, b, c) hri_tc_get_CMR_CAPTURE_SBSMPLR_bf(a, b, c) +#define hri_tc_write_CMR_SBSMPLR_bf(a, b, c) hri_tc_write_CMR_CAPTURE_SBSMPLR_bf(a, b, c) +#define hri_tc_clear_CMR_SBSMPLR_bf(a, b, c) hri_tc_clear_CMR_CAPTURE_SBSMPLR_bf(a, b, c) +#define hri_tc_toggle_CMR_SBSMPLR_bf(a, b, c) hri_tc_toggle_CMR_CAPTURE_SBSMPLR_bf(a, b, c) +#define hri_tc_read_CMR_SBSMPLR_bf(a, b) hri_tc_read_CMR_CAPTURE_SBSMPLR_bf(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_E70B_H_INCLUDED */ +#endif /* _SAME70_TC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_trng_e70b.h b/bsp/microchip/same70/bsp/hri/hri_trng_e70b.h new file mode 100644 index 0000000000..7a77498f12 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_trng_e70b.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_E70B_H_INCLUDED_ +#define _HRI_TRNG_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_cr_reg_t; +typedef uint32_t hri_trng_imr_reg_t; +typedef uint32_t hri_trng_isr_reg_t; +typedef uint32_t hri_trng_odata_reg_t; + +static inline bool hri_trng_get_ISR_DATRDY_bit(const void *const hw) +{ + return (((Trng *)hw)->TRNG_ISR & TRNG_ISR_DATRDY) >> TRNG_ISR_DATRDY_Pos; +} + +static inline hri_trng_isr_reg_t hri_trng_get_ISR_reg(const void *const hw, hri_trng_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->TRNG_ISR; + tmp &= mask; + return tmp; +} + +static inline hri_trng_isr_reg_t hri_trng_read_ISR_reg(const void *const hw) +{ + return ((Trng *)hw)->TRNG_ISR; +} + +static inline void hri_trng_set_IMR_DATRDY_bit(const void *const hw) +{ + ((Trng *)hw)->TRNG_IER = TRNG_IMR_DATRDY; +} + +static inline bool hri_trng_get_IMR_DATRDY_bit(const void *const hw) +{ + return (((Trng *)hw)->TRNG_IMR & TRNG_IMR_DATRDY) >> TRNG_IMR_DATRDY_Pos; +} + +static inline void hri_trng_write_IMR_DATRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->TRNG_IDR = TRNG_IMR_DATRDY; + } else { + ((Trng *)hw)->TRNG_IER = TRNG_IMR_DATRDY; + } +} + +static inline void hri_trng_clear_IMR_DATRDY_bit(const void *const hw) +{ + ((Trng *)hw)->TRNG_IDR = TRNG_IMR_DATRDY; +} + +static inline void hri_trng_set_IMR_reg(const void *const hw, hri_trng_imr_reg_t mask) +{ + ((Trng *)hw)->TRNG_IER = mask; +} + +static inline hri_trng_imr_reg_t hri_trng_get_IMR_reg(const void *const hw, hri_trng_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->TRNG_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_trng_imr_reg_t hri_trng_read_IMR_reg(const void *const hw) +{ + return ((Trng *)hw)->TRNG_IMR; +} + +static inline void hri_trng_write_IMR_reg(const void *const hw, hri_trng_imr_reg_t data) +{ + ((Trng *)hw)->TRNG_IER = data; + ((Trng *)hw)->TRNG_IDR = ~data; +} + +static inline void hri_trng_clear_IMR_reg(const void *const hw, hri_trng_imr_reg_t mask) +{ + ((Trng *)hw)->TRNG_IDR = mask; +} + +static inline hri_trng_odata_reg_t hri_trng_get_ODATA_ODATA_bf(const void *const hw, hri_trng_odata_reg_t mask) +{ + return (((Trng *)hw)->TRNG_ODATA & TRNG_ODATA_ODATA(mask)) >> TRNG_ODATA_ODATA_Pos; +} + +static inline hri_trng_odata_reg_t hri_trng_read_ODATA_ODATA_bf(const void *const hw) +{ + return (((Trng *)hw)->TRNG_ODATA & TRNG_ODATA_ODATA_Msk) >> TRNG_ODATA_ODATA_Pos; +} + +static inline hri_trng_odata_reg_t hri_trng_get_ODATA_reg(const void *const hw, hri_trng_odata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->TRNG_ODATA; + tmp &= mask; + return tmp; +} + +static inline hri_trng_odata_reg_t hri_trng_read_ODATA_reg(const void *const hw) +{ + return ((Trng *)hw)->TRNG_ODATA; +} + +static inline void hri_trng_write_CR_reg(const void *const hw, hri_trng_cr_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->TRNG_CR = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_E70B_H_INCLUDED */ +#endif /* _SAME70_TRNG_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_twihs_e70b.h b/bsp/microchip/same70/bsp/hri/hri_twihs_e70b.h new file mode 100644 index 0000000000..4f9c6e2fba --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_twihs_e70b.h @@ -0,0 +1,2418 @@ +/** + * \file + * + * \brief SAM TWIHS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_TWIHS_COMPONENT_ +#ifndef _HRI_TWIHS_E70B_H_INCLUDED_ +#define _HRI_TWIHS_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TWIHS_CRITICAL_SECTIONS) +#define TWIHS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TWIHS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TWIHS_CRITICAL_SECTION_ENTER() +#define TWIHS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_twihs_cr_reg_t; +typedef uint32_t hri_twihs_cwgr_reg_t; +typedef uint32_t hri_twihs_filtr_reg_t; +typedef uint32_t hri_twihs_iadr_reg_t; +typedef uint32_t hri_twihs_imr_reg_t; +typedef uint32_t hri_twihs_mmr_reg_t; +typedef uint32_t hri_twihs_rhr_reg_t; +typedef uint32_t hri_twihs_smbtr_reg_t; +typedef uint32_t hri_twihs_smr_reg_t; +typedef uint32_t hri_twihs_sr_reg_t; +typedef uint32_t hri_twihs_swmr_reg_t; +typedef uint32_t hri_twihs_thr_reg_t; +typedef uint32_t hri_twihs_wpmr_reg_t; +typedef uint32_t hri_twihs_wpsr_reg_t; + +static inline void hri_twihs_set_IMR_TXCOMP_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TXCOMP; +} + +static inline bool hri_twihs_get_IMR_TXCOMP_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_TXCOMP) >> TWIHS_IMR_TXCOMP_Pos; +} + +static inline void hri_twihs_write_IMR_TXCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TXCOMP; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TXCOMP; + } +} + +static inline void hri_twihs_clear_IMR_TXCOMP_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TXCOMP; +} + +static inline void hri_twihs_set_IMR_RXRDY_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_RXRDY; +} + +static inline bool hri_twihs_get_IMR_RXRDY_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_RXRDY) >> TWIHS_IMR_RXRDY_Pos; +} + +static inline void hri_twihs_write_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_RXRDY; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_RXRDY; + } +} + +static inline void hri_twihs_clear_IMR_RXRDY_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_RXRDY; +} + +static inline void hri_twihs_set_IMR_TXRDY_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TXRDY; +} + +static inline bool hri_twihs_get_IMR_TXRDY_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_TXRDY) >> TWIHS_IMR_TXRDY_Pos; +} + +static inline void hri_twihs_write_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TXRDY; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TXRDY; + } +} + +static inline void hri_twihs_clear_IMR_TXRDY_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TXRDY; +} + +static inline void hri_twihs_set_IMR_SVACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SVACC; +} + +static inline bool hri_twihs_get_IMR_SVACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_SVACC) >> TWIHS_IMR_SVACC_Pos; +} + +static inline void hri_twihs_write_IMR_SVACC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SVACC; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SVACC; + } +} + +static inline void hri_twihs_clear_IMR_SVACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SVACC; +} + +static inline void hri_twihs_set_IMR_GACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_GACC; +} + +static inline bool hri_twihs_get_IMR_GACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_GACC) >> TWIHS_IMR_GACC_Pos; +} + +static inline void hri_twihs_write_IMR_GACC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_GACC; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_GACC; + } +} + +static inline void hri_twihs_clear_IMR_GACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_GACC; +} + +static inline void hri_twihs_set_IMR_OVRE_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_OVRE; +} + +static inline bool hri_twihs_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_OVRE) >> TWIHS_IMR_OVRE_Pos; +} + +static inline void hri_twihs_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_OVRE; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_OVRE; + } +} + +static inline void hri_twihs_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_OVRE; +} + +static inline void hri_twihs_set_IMR_UNRE_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_UNRE; +} + +static inline bool hri_twihs_get_IMR_UNRE_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_UNRE) >> TWIHS_IMR_UNRE_Pos; +} + +static inline void hri_twihs_write_IMR_UNRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_UNRE; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_UNRE; + } +} + +static inline void hri_twihs_clear_IMR_UNRE_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_UNRE; +} + +static inline void hri_twihs_set_IMR_NACK_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_NACK; +} + +static inline bool hri_twihs_get_IMR_NACK_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_NACK) >> TWIHS_IMR_NACK_Pos; +} + +static inline void hri_twihs_write_IMR_NACK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_NACK; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_NACK; + } +} + +static inline void hri_twihs_clear_IMR_NACK_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_NACK; +} + +static inline void hri_twihs_set_IMR_ARBLST_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_ARBLST; +} + +static inline bool hri_twihs_get_IMR_ARBLST_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_ARBLST) >> TWIHS_IMR_ARBLST_Pos; +} + +static inline void hri_twihs_write_IMR_ARBLST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_ARBLST; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_ARBLST; + } +} + +static inline void hri_twihs_clear_IMR_ARBLST_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_ARBLST; +} + +static inline void hri_twihs_set_IMR_SCL_WS_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SCL_WS; +} + +static inline bool hri_twihs_get_IMR_SCL_WS_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_SCL_WS) >> TWIHS_IMR_SCL_WS_Pos; +} + +static inline void hri_twihs_write_IMR_SCL_WS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SCL_WS; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SCL_WS; + } +} + +static inline void hri_twihs_clear_IMR_SCL_WS_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SCL_WS; +} + +static inline void hri_twihs_set_IMR_EOSACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_EOSACC; +} + +static inline bool hri_twihs_get_IMR_EOSACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_EOSACC) >> TWIHS_IMR_EOSACC_Pos; +} + +static inline void hri_twihs_write_IMR_EOSACC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_EOSACC; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_EOSACC; + } +} + +static inline void hri_twihs_clear_IMR_EOSACC_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_EOSACC; +} + +static inline void hri_twihs_set_IMR_MCACK_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_MCACK; +} + +static inline bool hri_twihs_get_IMR_MCACK_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_MCACK) >> TWIHS_IMR_MCACK_Pos; +} + +static inline void hri_twihs_write_IMR_MCACK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_MCACK; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_MCACK; + } +} + +static inline void hri_twihs_clear_IMR_MCACK_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_MCACK; +} + +static inline void hri_twihs_set_IMR_TOUT_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TOUT; +} + +static inline bool hri_twihs_get_IMR_TOUT_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_TOUT) >> TWIHS_IMR_TOUT_Pos; +} + +static inline void hri_twihs_write_IMR_TOUT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TOUT; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_TOUT; + } +} + +static inline void hri_twihs_clear_IMR_TOUT_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_TOUT; +} + +static inline void hri_twihs_set_IMR_PECERR_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_PECERR; +} + +static inline bool hri_twihs_get_IMR_PECERR_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_PECERR) >> TWIHS_IMR_PECERR_Pos; +} + +static inline void hri_twihs_write_IMR_PECERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_PECERR; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_PECERR; + } +} + +static inline void hri_twihs_clear_IMR_PECERR_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_PECERR; +} + +static inline void hri_twihs_set_IMR_SMBDAM_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SMBDAM; +} + +static inline bool hri_twihs_get_IMR_SMBDAM_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_SMBDAM) >> TWIHS_IMR_SMBDAM_Pos; +} + +static inline void hri_twihs_write_IMR_SMBDAM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SMBDAM; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SMBDAM; + } +} + +static inline void hri_twihs_clear_IMR_SMBDAM_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SMBDAM; +} + +static inline void hri_twihs_set_IMR_SMBHHM_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SMBHHM; +} + +static inline bool hri_twihs_get_IMR_SMBHHM_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_IMR & TWIHS_IMR_SMBHHM) >> TWIHS_IMR_SMBHHM_Pos; +} + +static inline void hri_twihs_write_IMR_SMBHHM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SMBHHM; + } else { + ((Twihs *)hw)->TWIHS_IER = TWIHS_IMR_SMBHHM; + } +} + +static inline void hri_twihs_clear_IMR_SMBHHM_bit(const void *const hw) +{ + ((Twihs *)hw)->TWIHS_IDR = TWIHS_IMR_SMBHHM; +} + +static inline void hri_twihs_set_IMR_reg(const void *const hw, hri_twihs_imr_reg_t mask) +{ + ((Twihs *)hw)->TWIHS_IER = mask; +} + +static inline hri_twihs_imr_reg_t hri_twihs_get_IMR_reg(const void *const hw, hri_twihs_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_twihs_imr_reg_t hri_twihs_read_IMR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_IMR; +} + +static inline void hri_twihs_write_IMR_reg(const void *const hw, hri_twihs_imr_reg_t data) +{ + ((Twihs *)hw)->TWIHS_IER = data; + ((Twihs *)hw)->TWIHS_IDR = ~data; +} + +static inline void hri_twihs_clear_IMR_reg(const void *const hw, hri_twihs_imr_reg_t mask) +{ + ((Twihs *)hw)->TWIHS_IDR = mask; +} + +static inline bool hri_twihs_get_SR_TXCOMP_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_TXCOMP) > 0; +} + +static inline bool hri_twihs_get_SR_RXRDY_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_RXRDY) > 0; +} + +static inline bool hri_twihs_get_SR_TXRDY_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_TXRDY) > 0; +} + +static inline bool hri_twihs_get_SR_SVREAD_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SVREAD) > 0; +} + +static inline bool hri_twihs_get_SR_SVACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SVACC) > 0; +} + +static inline bool hri_twihs_get_SR_GACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_GACC) > 0; +} + +static inline bool hri_twihs_get_SR_OVRE_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_OVRE) > 0; +} + +static inline bool hri_twihs_get_SR_UNRE_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_UNRE) > 0; +} + +static inline bool hri_twihs_get_SR_NACK_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_NACK) > 0; +} + +static inline bool hri_twihs_get_SR_ARBLST_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_ARBLST) > 0; +} + +static inline bool hri_twihs_get_SR_SCLWS_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SCLWS) > 0; +} + +static inline bool hri_twihs_get_SR_EOSACC_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_EOSACC) > 0; +} + +static inline bool hri_twihs_get_SR_MCACK_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_MCACK) > 0; +} + +static inline bool hri_twihs_get_SR_TOUT_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_TOUT) > 0; +} + +static inline bool hri_twihs_get_SR_PECERR_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_PECERR) > 0; +} + +static inline bool hri_twihs_get_SR_SMBDAM_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SMBDAM) > 0; +} + +static inline bool hri_twihs_get_SR_SMBHHM_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SMBHHM) > 0; +} + +static inline bool hri_twihs_get_SR_SCL_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SCL) > 0; +} + +static inline bool hri_twihs_get_SR_SDA_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_SR & TWIHS_SR_SDA) > 0; +} + +static inline hri_twihs_sr_reg_t hri_twihs_get_SR_reg(const void *const hw, hri_twihs_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SR; + tmp &= mask; + return tmp; +} + +static inline hri_twihs_sr_reg_t hri_twihs_read_SR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_SR; +} + +static inline hri_twihs_rhr_reg_t hri_twihs_get_RHR_RXDATA_bf(const void *const hw, hri_twihs_rhr_reg_t mask) +{ + return (((Twihs *)hw)->TWIHS_RHR & TWIHS_RHR_RXDATA(mask)) >> TWIHS_RHR_RXDATA_Pos; +} + +static inline hri_twihs_rhr_reg_t hri_twihs_read_RHR_RXDATA_bf(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_RHR & TWIHS_RHR_RXDATA_Msk) >> TWIHS_RHR_RXDATA_Pos; +} + +static inline hri_twihs_rhr_reg_t hri_twihs_get_RHR_reg(const void *const hw, hri_twihs_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_RHR; + tmp &= mask; + return tmp; +} + +static inline hri_twihs_rhr_reg_t hri_twihs_read_RHR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_RHR; +} + +static inline bool hri_twihs_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_WPSR & TWIHS_WPSR_WPVS) > 0; +} + +static inline hri_twihs_wpsr_reg_t hri_twihs_get_WPSR_WPVSRC_bf(const void *const hw, hri_twihs_wpsr_reg_t mask) +{ + return (((Twihs *)hw)->TWIHS_WPSR & TWIHS_WPSR_WPVSRC(mask)) >> TWIHS_WPSR_WPVSRC_Pos; +} + +static inline hri_twihs_wpsr_reg_t hri_twihs_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Twihs *)hw)->TWIHS_WPSR & TWIHS_WPSR_WPVSRC_Msk) >> TWIHS_WPSR_WPVSRC_Pos; +} + +static inline hri_twihs_wpsr_reg_t hri_twihs_get_WPSR_reg(const void *const hw, hri_twihs_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_twihs_wpsr_reg_t hri_twihs_read_WPSR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_WPSR; +} + +static inline void hri_twihs_set_MMR_MREAD_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR |= TWIHS_MMR_MREAD; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_MMR_MREAD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp = (tmp & TWIHS_MMR_MREAD) >> TWIHS_MMR_MREAD_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_MMR_MREAD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp &= ~TWIHS_MMR_MREAD; + tmp |= value << TWIHS_MMR_MREAD_Pos; + ((Twihs *)hw)->TWIHS_MMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_MMR_MREAD_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR &= ~TWIHS_MMR_MREAD; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_MMR_MREAD_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR ^= TWIHS_MMR_MREAD; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_MMR_IADRSZ_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR |= TWIHS_MMR_IADRSZ(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_get_MMR_IADRSZ_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp = (tmp & TWIHS_MMR_IADRSZ(mask)) >> TWIHS_MMR_IADRSZ_Pos; + return tmp; +} + +static inline void hri_twihs_write_MMR_IADRSZ_bf(const void *const hw, hri_twihs_mmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp &= ~TWIHS_MMR_IADRSZ_Msk; + tmp |= TWIHS_MMR_IADRSZ(data); + ((Twihs *)hw)->TWIHS_MMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_MMR_IADRSZ_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR &= ~TWIHS_MMR_IADRSZ(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_MMR_IADRSZ_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR ^= TWIHS_MMR_IADRSZ(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_read_MMR_IADRSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp = (tmp & TWIHS_MMR_IADRSZ_Msk) >> TWIHS_MMR_IADRSZ_Pos; + return tmp; +} + +static inline void hri_twihs_set_MMR_DADR_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR |= TWIHS_MMR_DADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_get_MMR_DADR_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp = (tmp & TWIHS_MMR_DADR(mask)) >> TWIHS_MMR_DADR_Pos; + return tmp; +} + +static inline void hri_twihs_write_MMR_DADR_bf(const void *const hw, hri_twihs_mmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp &= ~TWIHS_MMR_DADR_Msk; + tmp |= TWIHS_MMR_DADR(data); + ((Twihs *)hw)->TWIHS_MMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_MMR_DADR_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR &= ~TWIHS_MMR_DADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_MMR_DADR_bf(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR ^= TWIHS_MMR_DADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_read_MMR_DADR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp = (tmp & TWIHS_MMR_DADR_Msk) >> TWIHS_MMR_DADR_Pos; + return tmp; +} + +static inline void hri_twihs_set_MMR_reg(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_get_MMR_reg(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_MMR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_MMR_reg(const void *const hw, hri_twihs_mmr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_MMR_reg(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_MMR_reg(const void *const hw, hri_twihs_mmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_MMR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_mmr_reg_t hri_twihs_read_MMR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_MMR; +} + +static inline void hri_twihs_set_SMR_NACKEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_NACKEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_NACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_NACKEN) >> TWIHS_SMR_NACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_NACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_NACKEN; + tmp |= value << TWIHS_SMR_NACKEN_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_NACKEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_NACKEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_NACKEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_NACKEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SMDA_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SMDA; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SMDA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SMDA) >> TWIHS_SMR_SMDA_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SMDA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SMDA; + tmp |= value << TWIHS_SMR_SMDA_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SMDA_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SMDA; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SMDA_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SMDA; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SMHH_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SMHH; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SMHH_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SMHH) >> TWIHS_SMR_SMHH_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SMHH_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SMHH; + tmp |= value << TWIHS_SMR_SMHH_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SMHH_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SMHH; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SMHH_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SMHH; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SCLWSDIS_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SCLWSDIS; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SCLWSDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SCLWSDIS) >> TWIHS_SMR_SCLWSDIS_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SCLWSDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SCLWSDIS; + tmp |= value << TWIHS_SMR_SCLWSDIS_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SCLWSDIS_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SCLWSDIS; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SCLWSDIS_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SCLWSDIS; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SADR1EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SADR1EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SADR1EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SADR1EN) >> TWIHS_SMR_SADR1EN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SADR1EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SADR1EN; + tmp |= value << TWIHS_SMR_SADR1EN_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SADR1EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SADR1EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SADR1EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SADR1EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SADR2EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SADR2EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SADR2EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SADR2EN) >> TWIHS_SMR_SADR2EN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SADR2EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SADR2EN; + tmp |= value << TWIHS_SMR_SADR2EN_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SADR2EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SADR2EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SADR2EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SADR2EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_SADR3EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SADR3EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_SADR3EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SADR3EN) >> TWIHS_SMR_SADR3EN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_SADR3EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SADR3EN; + tmp |= value << TWIHS_SMR_SADR3EN_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SADR3EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SADR3EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SADR3EN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SADR3EN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_DATAMEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_DATAMEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_SMR_DATAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_DATAMEN) >> TWIHS_SMR_DATAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_SMR_DATAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_DATAMEN; + tmp |= value << TWIHS_SMR_DATAMEN_Pos; + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_DATAMEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_DATAMEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_DATAMEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_DATAMEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_SMR_MASK_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_MASK(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_get_SMR_MASK_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_MASK(mask)) >> TWIHS_SMR_MASK_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMR_MASK_bf(const void *const hw, hri_twihs_smr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_MASK_Msk; + tmp |= TWIHS_SMR_MASK(data); + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_MASK_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_MASK(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_MASK_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_MASK(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_read_SMR_MASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_MASK_Msk) >> TWIHS_SMR_MASK_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMR_SADR_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= TWIHS_SMR_SADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_get_SMR_SADR_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SADR(mask)) >> TWIHS_SMR_SADR_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMR_SADR_bf(const void *const hw, hri_twihs_smr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= ~TWIHS_SMR_SADR_Msk; + tmp |= TWIHS_SMR_SADR(data); + ((Twihs *)hw)->TWIHS_SMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_SADR_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~TWIHS_SMR_SADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_SADR_bf(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= TWIHS_SMR_SADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_read_SMR_SADR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp = (tmp & TWIHS_SMR_SADR_Msk) >> TWIHS_SMR_SADR_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMR_reg(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_get_SMR_reg(const void *const hw, hri_twihs_smr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_SMR_reg(const void *const hw, hri_twihs_smr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMR_reg(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMR_reg(const void *const hw, hri_twihs_smr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smr_reg_t hri_twihs_read_SMR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_SMR; +} + +static inline void hri_twihs_set_IADR_IADR_bf(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR |= TWIHS_IADR_IADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_iadr_reg_t hri_twihs_get_IADR_IADR_bf(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_IADR; + tmp = (tmp & TWIHS_IADR_IADR(mask)) >> TWIHS_IADR_IADR_Pos; + return tmp; +} + +static inline void hri_twihs_write_IADR_IADR_bf(const void *const hw, hri_twihs_iadr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_IADR; + tmp &= ~TWIHS_IADR_IADR_Msk; + tmp |= TWIHS_IADR_IADR(data); + ((Twihs *)hw)->TWIHS_IADR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_IADR_IADR_bf(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR &= ~TWIHS_IADR_IADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_IADR_IADR_bf(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR ^= TWIHS_IADR_IADR(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_iadr_reg_t hri_twihs_read_IADR_IADR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_IADR; + tmp = (tmp & TWIHS_IADR_IADR_Msk) >> TWIHS_IADR_IADR_Pos; + return tmp; +} + +static inline void hri_twihs_set_IADR_reg(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_iadr_reg_t hri_twihs_get_IADR_reg(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_IADR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_IADR_reg(const void *const hw, hri_twihs_iadr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_IADR_reg(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_IADR_reg(const void *const hw, hri_twihs_iadr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_IADR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_iadr_reg_t hri_twihs_read_IADR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_IADR; +} + +static inline void hri_twihs_set_CWGR_CLDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR |= TWIHS_CWGR_CLDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_get_CWGR_CLDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CLDIV(mask)) >> TWIHS_CWGR_CLDIV_Pos; + return tmp; +} + +static inline void hri_twihs_write_CWGR_CLDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp &= ~TWIHS_CWGR_CLDIV_Msk; + tmp |= TWIHS_CWGR_CLDIV(data); + ((Twihs *)hw)->TWIHS_CWGR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_CWGR_CLDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR &= ~TWIHS_CWGR_CLDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_CWGR_CLDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR ^= TWIHS_CWGR_CLDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_read_CWGR_CLDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CLDIV_Msk) >> TWIHS_CWGR_CLDIV_Pos; + return tmp; +} + +static inline void hri_twihs_set_CWGR_CHDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR |= TWIHS_CWGR_CHDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_get_CWGR_CHDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CHDIV(mask)) >> TWIHS_CWGR_CHDIV_Pos; + return tmp; +} + +static inline void hri_twihs_write_CWGR_CHDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp &= ~TWIHS_CWGR_CHDIV_Msk; + tmp |= TWIHS_CWGR_CHDIV(data); + ((Twihs *)hw)->TWIHS_CWGR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_CWGR_CHDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR &= ~TWIHS_CWGR_CHDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_CWGR_CHDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR ^= TWIHS_CWGR_CHDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_read_CWGR_CHDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CHDIV_Msk) >> TWIHS_CWGR_CHDIV_Pos; + return tmp; +} + +static inline void hri_twihs_set_CWGR_CKDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR |= TWIHS_CWGR_CKDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_get_CWGR_CKDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CKDIV(mask)) >> TWIHS_CWGR_CKDIV_Pos; + return tmp; +} + +static inline void hri_twihs_write_CWGR_CKDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp &= ~TWIHS_CWGR_CKDIV_Msk; + tmp |= TWIHS_CWGR_CKDIV(data); + ((Twihs *)hw)->TWIHS_CWGR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_CWGR_CKDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR &= ~TWIHS_CWGR_CKDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_CWGR_CKDIV_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR ^= TWIHS_CWGR_CKDIV(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_read_CWGR_CKDIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_CKDIV_Msk) >> TWIHS_CWGR_CKDIV_Pos; + return tmp; +} + +static inline void hri_twihs_set_CWGR_HOLD_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR |= TWIHS_CWGR_HOLD(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_get_CWGR_HOLD_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_HOLD(mask)) >> TWIHS_CWGR_HOLD_Pos; + return tmp; +} + +static inline void hri_twihs_write_CWGR_HOLD_bf(const void *const hw, hri_twihs_cwgr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp &= ~TWIHS_CWGR_HOLD_Msk; + tmp |= TWIHS_CWGR_HOLD(data); + ((Twihs *)hw)->TWIHS_CWGR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_CWGR_HOLD_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR &= ~TWIHS_CWGR_HOLD(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_CWGR_HOLD_bf(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR ^= TWIHS_CWGR_HOLD(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_read_CWGR_HOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp = (tmp & TWIHS_CWGR_HOLD_Msk) >> TWIHS_CWGR_HOLD_Pos; + return tmp; +} + +static inline void hri_twihs_set_CWGR_reg(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_get_CWGR_reg(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_CWGR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_CWGR_reg(const void *const hw, hri_twihs_cwgr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_CWGR_reg(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_CWGR_reg(const void *const hw, hri_twihs_cwgr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CWGR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_cwgr_reg_t hri_twihs_read_CWGR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_CWGR; +} + +static inline void hri_twihs_set_SMBTR_PRESC_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR |= TWIHS_SMBTR_PRESC(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_get_SMBTR_PRESC_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_PRESC(mask)) >> TWIHS_SMBTR_PRESC_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMBTR_PRESC_bf(const void *const hw, hri_twihs_smbtr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp &= ~TWIHS_SMBTR_PRESC_Msk; + tmp |= TWIHS_SMBTR_PRESC(data); + ((Twihs *)hw)->TWIHS_SMBTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMBTR_PRESC_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR &= ~TWIHS_SMBTR_PRESC(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMBTR_PRESC_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR ^= TWIHS_SMBTR_PRESC(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_read_SMBTR_PRESC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_PRESC_Msk) >> TWIHS_SMBTR_PRESC_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMBTR_TLOWS_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR |= TWIHS_SMBTR_TLOWS(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_get_SMBTR_TLOWS_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_TLOWS(mask)) >> TWIHS_SMBTR_TLOWS_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMBTR_TLOWS_bf(const void *const hw, hri_twihs_smbtr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp &= ~TWIHS_SMBTR_TLOWS_Msk; + tmp |= TWIHS_SMBTR_TLOWS(data); + ((Twihs *)hw)->TWIHS_SMBTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMBTR_TLOWS_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR &= ~TWIHS_SMBTR_TLOWS(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMBTR_TLOWS_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR ^= TWIHS_SMBTR_TLOWS(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_read_SMBTR_TLOWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_TLOWS_Msk) >> TWIHS_SMBTR_TLOWS_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMBTR_TLOWM_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR |= TWIHS_SMBTR_TLOWM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_get_SMBTR_TLOWM_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_TLOWM(mask)) >> TWIHS_SMBTR_TLOWM_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMBTR_TLOWM_bf(const void *const hw, hri_twihs_smbtr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp &= ~TWIHS_SMBTR_TLOWM_Msk; + tmp |= TWIHS_SMBTR_TLOWM(data); + ((Twihs *)hw)->TWIHS_SMBTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMBTR_TLOWM_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR &= ~TWIHS_SMBTR_TLOWM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMBTR_TLOWM_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR ^= TWIHS_SMBTR_TLOWM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_read_SMBTR_TLOWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_TLOWM_Msk) >> TWIHS_SMBTR_TLOWM_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMBTR_THMAX_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR |= TWIHS_SMBTR_THMAX(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_get_SMBTR_THMAX_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_THMAX(mask)) >> TWIHS_SMBTR_THMAX_Pos; + return tmp; +} + +static inline void hri_twihs_write_SMBTR_THMAX_bf(const void *const hw, hri_twihs_smbtr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp &= ~TWIHS_SMBTR_THMAX_Msk; + tmp |= TWIHS_SMBTR_THMAX(data); + ((Twihs *)hw)->TWIHS_SMBTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMBTR_THMAX_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR &= ~TWIHS_SMBTR_THMAX(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMBTR_THMAX_bf(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR ^= TWIHS_SMBTR_THMAX(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_read_SMBTR_THMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp = (tmp & TWIHS_SMBTR_THMAX_Msk) >> TWIHS_SMBTR_THMAX_Pos; + return tmp; +} + +static inline void hri_twihs_set_SMBTR_reg(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_get_SMBTR_reg(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SMBTR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_SMBTR_reg(const void *const hw, hri_twihs_smbtr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SMBTR_reg(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SMBTR_reg(const void *const hw, hri_twihs_smbtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SMBTR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_smbtr_reg_t hri_twihs_read_SMBTR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_SMBTR; +} + +static inline void hri_twihs_set_FILTR_FILT_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR |= TWIHS_FILTR_FILT; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_FILTR_FILT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp = (tmp & TWIHS_FILTR_FILT) >> TWIHS_FILTR_FILT_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_FILTR_FILT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp &= ~TWIHS_FILTR_FILT; + tmp |= value << TWIHS_FILTR_FILT_Pos; + ((Twihs *)hw)->TWIHS_FILTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_FILTR_FILT_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR &= ~TWIHS_FILTR_FILT; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_FILTR_FILT_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR ^= TWIHS_FILTR_FILT; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_FILTR_PADFEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR |= TWIHS_FILTR_PADFEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_FILTR_PADFEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp = (tmp & TWIHS_FILTR_PADFEN) >> TWIHS_FILTR_PADFEN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_FILTR_PADFEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp &= ~TWIHS_FILTR_PADFEN; + tmp |= value << TWIHS_FILTR_PADFEN_Pos; + ((Twihs *)hw)->TWIHS_FILTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_FILTR_PADFEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR &= ~TWIHS_FILTR_PADFEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_FILTR_PADFEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR ^= TWIHS_FILTR_PADFEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_FILTR_PADFCFG_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR |= TWIHS_FILTR_PADFCFG; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_FILTR_PADFCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp = (tmp & TWIHS_FILTR_PADFCFG) >> TWIHS_FILTR_PADFCFG_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_FILTR_PADFCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp &= ~TWIHS_FILTR_PADFCFG; + tmp |= value << TWIHS_FILTR_PADFCFG_Pos; + ((Twihs *)hw)->TWIHS_FILTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_FILTR_PADFCFG_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR &= ~TWIHS_FILTR_PADFCFG; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_FILTR_PADFCFG_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR ^= TWIHS_FILTR_PADFCFG; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_FILTR_THRES_bf(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR |= TWIHS_FILTR_THRES(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_filtr_reg_t hri_twihs_get_FILTR_THRES_bf(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp = (tmp & TWIHS_FILTR_THRES(mask)) >> TWIHS_FILTR_THRES_Pos; + return tmp; +} + +static inline void hri_twihs_write_FILTR_THRES_bf(const void *const hw, hri_twihs_filtr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp &= ~TWIHS_FILTR_THRES_Msk; + tmp |= TWIHS_FILTR_THRES(data); + ((Twihs *)hw)->TWIHS_FILTR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_FILTR_THRES_bf(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR &= ~TWIHS_FILTR_THRES(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_FILTR_THRES_bf(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR ^= TWIHS_FILTR_THRES(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_filtr_reg_t hri_twihs_read_FILTR_THRES_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp = (tmp & TWIHS_FILTR_THRES_Msk) >> TWIHS_FILTR_THRES_Pos; + return tmp; +} + +static inline void hri_twihs_set_FILTR_reg(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_filtr_reg_t hri_twihs_get_FILTR_reg(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_FILTR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_FILTR_reg(const void *const hw, hri_twihs_filtr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_FILTR_reg(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_FILTR_reg(const void *const hw, hri_twihs_filtr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_FILTR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_filtr_reg_t hri_twihs_read_FILTR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_FILTR; +} + +static inline void hri_twihs_set_SWMR_SADR1_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR |= TWIHS_SWMR_SADR1(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_get_SWMR_SADR1_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR1(mask)) >> TWIHS_SWMR_SADR1_Pos; + return tmp; +} + +static inline void hri_twihs_write_SWMR_SADR1_bf(const void *const hw, hri_twihs_swmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp &= ~TWIHS_SWMR_SADR1_Msk; + tmp |= TWIHS_SWMR_SADR1(data); + ((Twihs *)hw)->TWIHS_SWMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SWMR_SADR1_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR &= ~TWIHS_SWMR_SADR1(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SWMR_SADR1_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR ^= TWIHS_SWMR_SADR1(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_read_SWMR_SADR1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR1_Msk) >> TWIHS_SWMR_SADR1_Pos; + return tmp; +} + +static inline void hri_twihs_set_SWMR_SADR2_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR |= TWIHS_SWMR_SADR2(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_get_SWMR_SADR2_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR2(mask)) >> TWIHS_SWMR_SADR2_Pos; + return tmp; +} + +static inline void hri_twihs_write_SWMR_SADR2_bf(const void *const hw, hri_twihs_swmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp &= ~TWIHS_SWMR_SADR2_Msk; + tmp |= TWIHS_SWMR_SADR2(data); + ((Twihs *)hw)->TWIHS_SWMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SWMR_SADR2_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR &= ~TWIHS_SWMR_SADR2(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SWMR_SADR2_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR ^= TWIHS_SWMR_SADR2(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_read_SWMR_SADR2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR2_Msk) >> TWIHS_SWMR_SADR2_Pos; + return tmp; +} + +static inline void hri_twihs_set_SWMR_SADR3_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR |= TWIHS_SWMR_SADR3(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_get_SWMR_SADR3_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR3(mask)) >> TWIHS_SWMR_SADR3_Pos; + return tmp; +} + +static inline void hri_twihs_write_SWMR_SADR3_bf(const void *const hw, hri_twihs_swmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp &= ~TWIHS_SWMR_SADR3_Msk; + tmp |= TWIHS_SWMR_SADR3(data); + ((Twihs *)hw)->TWIHS_SWMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SWMR_SADR3_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR &= ~TWIHS_SWMR_SADR3(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SWMR_SADR3_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR ^= TWIHS_SWMR_SADR3(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_read_SWMR_SADR3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_SADR3_Msk) >> TWIHS_SWMR_SADR3_Pos; + return tmp; +} + +static inline void hri_twihs_set_SWMR_DATAM_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR |= TWIHS_SWMR_DATAM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_get_SWMR_DATAM_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_DATAM(mask)) >> TWIHS_SWMR_DATAM_Pos; + return tmp; +} + +static inline void hri_twihs_write_SWMR_DATAM_bf(const void *const hw, hri_twihs_swmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp &= ~TWIHS_SWMR_DATAM_Msk; + tmp |= TWIHS_SWMR_DATAM(data); + ((Twihs *)hw)->TWIHS_SWMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SWMR_DATAM_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR &= ~TWIHS_SWMR_DATAM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SWMR_DATAM_bf(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR ^= TWIHS_SWMR_DATAM(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_read_SWMR_DATAM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp = (tmp & TWIHS_SWMR_DATAM_Msk) >> TWIHS_SWMR_DATAM_Pos; + return tmp; +} + +static inline void hri_twihs_set_SWMR_reg(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_get_SWMR_reg(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_SWMR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_SWMR_reg(const void *const hw, hri_twihs_swmr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_SWMR_reg(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_SWMR_reg(const void *const hw, hri_twihs_swmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_SWMR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_swmr_reg_t hri_twihs_read_SWMR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_SWMR; +} + +static inline void hri_twihs_set_WPMR_WPEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR |= TWIHS_WPMR_WPEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_twihs_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp = (tmp & TWIHS_WPMR_WPEN) >> TWIHS_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_twihs_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp &= ~TWIHS_WPMR_WPEN; + tmp |= value << TWIHS_WPMR_WPEN_Pos; + ((Twihs *)hw)->TWIHS_WPMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_WPMR_WPEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR &= ~TWIHS_WPMR_WPEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_WPMR_WPEN_bit(const void *const hw) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR ^= TWIHS_WPMR_WPEN; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_set_WPMR_WPKEY_bf(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR |= TWIHS_WPMR_WPKEY(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_wpmr_reg_t hri_twihs_get_WPMR_WPKEY_bf(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp = (tmp & TWIHS_WPMR_WPKEY(mask)) >> TWIHS_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_twihs_write_WPMR_WPKEY_bf(const void *const hw, hri_twihs_wpmr_reg_t data) +{ + uint32_t tmp; + TWIHS_CRITICAL_SECTION_ENTER(); + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp &= ~TWIHS_WPMR_WPKEY_Msk; + tmp |= TWIHS_WPMR_WPKEY(data); + ((Twihs *)hw)->TWIHS_WPMR = tmp; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_WPMR_WPKEY_bf(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR &= ~TWIHS_WPMR_WPKEY(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_WPMR_WPKEY_bf(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR ^= TWIHS_WPMR_WPKEY(mask); + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_wpmr_reg_t hri_twihs_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp = (tmp & TWIHS_WPMR_WPKEY_Msk) >> TWIHS_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_twihs_set_WPMR_reg(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR |= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_wpmr_reg_t hri_twihs_get_WPMR_reg(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Twihs *)hw)->TWIHS_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_twihs_write_WPMR_reg(const void *const hw, hri_twihs_wpmr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_clear_WPMR_reg(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR &= ~mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_toggle_WPMR_reg(const void *const hw, hri_twihs_wpmr_reg_t mask) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_WPMR ^= mask; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_twihs_wpmr_reg_t hri_twihs_read_WPMR_reg(const void *const hw) +{ + return ((Twihs *)hw)->TWIHS_WPMR; +} + +static inline void hri_twihs_write_CR_reg(const void *const hw, hri_twihs_cr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_CR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_twihs_write_THR_reg(const void *const hw, hri_twihs_thr_reg_t data) +{ + TWIHS_CRITICAL_SECTION_ENTER(); + ((Twihs *)hw)->TWIHS_THR = data; + TWIHS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TWIHS_E70B_H_INCLUDED */ +#endif /* _SAME70_TWIHS_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_uart_e70b.h b/bsp/microchip/same70/bsp/hri/hri_uart_e70b.h new file mode 100644 index 0000000000..f55c3239e3 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_uart_e70b.h @@ -0,0 +1,1001 @@ +/** + * \file + * + * \brief SAM UART + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_UART_COMPONENT_ +#ifndef _HRI_UART_E70B_H_INCLUDED_ +#define _HRI_UART_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_UART_CRITICAL_SECTIONS) +#define UART_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define UART_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define UART_CRITICAL_SECTION_ENTER() +#define UART_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_uart_brgr_reg_t; +typedef uint32_t hri_uart_cmpr_reg_t; +typedef uint32_t hri_uart_cr_reg_t; +typedef uint32_t hri_uart_imr_reg_t; +typedef uint32_t hri_uart_mr_reg_t; +typedef uint32_t hri_uart_rhr_reg_t; +typedef uint32_t hri_uart_sr_reg_t; +typedef uint32_t hri_uart_thr_reg_t; +typedef uint32_t hri_uart_wpmr_reg_t; + +static inline void hri_uart_set_IMR_RXRDY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_RXRDY; +} + +static inline bool hri_uart_get_IMR_RXRDY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_RXRDY) >> UART_IMR_RXRDY_Pos; +} + +static inline void hri_uart_write_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_RXRDY; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_RXRDY; + } +} + +static inline void hri_uart_clear_IMR_RXRDY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_RXRDY; +} + +static inline void hri_uart_set_IMR_TXRDY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_TXRDY; +} + +static inline bool hri_uart_get_IMR_TXRDY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_TXRDY) >> UART_IMR_TXRDY_Pos; +} + +static inline void hri_uart_write_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_TXRDY; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_TXRDY; + } +} + +static inline void hri_uart_clear_IMR_TXRDY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_TXRDY; +} + +static inline void hri_uart_set_IMR_OVRE_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_OVRE; +} + +static inline bool hri_uart_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_OVRE) >> UART_IMR_OVRE_Pos; +} + +static inline void hri_uart_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_OVRE; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_OVRE; + } +} + +static inline void hri_uart_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_OVRE; +} + +static inline void hri_uart_set_IMR_FRAME_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_FRAME; +} + +static inline bool hri_uart_get_IMR_FRAME_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_FRAME) >> UART_IMR_FRAME_Pos; +} + +static inline void hri_uart_write_IMR_FRAME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_FRAME; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_FRAME; + } +} + +static inline void hri_uart_clear_IMR_FRAME_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_FRAME; +} + +static inline void hri_uart_set_IMR_PARE_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_PARE; +} + +static inline bool hri_uart_get_IMR_PARE_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_PARE) >> UART_IMR_PARE_Pos; +} + +static inline void hri_uart_write_IMR_PARE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_PARE; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_PARE; + } +} + +static inline void hri_uart_clear_IMR_PARE_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_PARE; +} + +static inline void hri_uart_set_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_TXEMPTY; +} + +static inline bool hri_uart_get_IMR_TXEMPTY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_TXEMPTY) >> UART_IMR_TXEMPTY_Pos; +} + +static inline void hri_uart_write_IMR_TXEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_TXEMPTY; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_TXEMPTY; + } +} + +static inline void hri_uart_clear_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_TXEMPTY; +} + +static inline void hri_uart_set_IMR_CMP_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IER = UART_IMR_CMP; +} + +static inline bool hri_uart_get_IMR_CMP_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_IMR & UART_IMR_CMP) >> UART_IMR_CMP_Pos; +} + +static inline void hri_uart_write_IMR_CMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Uart *)hw)->UART_IDR = UART_IMR_CMP; + } else { + ((Uart *)hw)->UART_IER = UART_IMR_CMP; + } +} + +static inline void hri_uart_clear_IMR_CMP_bit(const void *const hw) +{ + ((Uart *)hw)->UART_IDR = UART_IMR_CMP; +} + +static inline void hri_uart_set_IMR_reg(const void *const hw, hri_uart_imr_reg_t mask) +{ + ((Uart *)hw)->UART_IER = mask; +} + +static inline hri_uart_imr_reg_t hri_uart_get_IMR_reg(const void *const hw, hri_uart_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_uart_imr_reg_t hri_uart_read_IMR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_IMR; +} + +static inline void hri_uart_write_IMR_reg(const void *const hw, hri_uart_imr_reg_t data) +{ + ((Uart *)hw)->UART_IER = data; + ((Uart *)hw)->UART_IDR = ~data; +} + +static inline void hri_uart_clear_IMR_reg(const void *const hw, hri_uart_imr_reg_t mask) +{ + ((Uart *)hw)->UART_IDR = mask; +} + +static inline bool hri_uart_get_SR_RXRDY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_RXRDY) > 0; +} + +static inline bool hri_uart_get_SR_TXRDY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_TXRDY) > 0; +} + +static inline bool hri_uart_get_SR_OVRE_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_OVRE) > 0; +} + +static inline bool hri_uart_get_SR_FRAME_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_FRAME) > 0; +} + +static inline bool hri_uart_get_SR_PARE_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_PARE) > 0; +} + +static inline bool hri_uart_get_SR_TXEMPTY_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_TXEMPTY) > 0; +} + +static inline bool hri_uart_get_SR_CMP_bit(const void *const hw) +{ + return (((Uart *)hw)->UART_SR & UART_SR_CMP) > 0; +} + +static inline hri_uart_sr_reg_t hri_uart_get_SR_reg(const void *const hw, hri_uart_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_SR; + tmp &= mask; + return tmp; +} + +static inline hri_uart_sr_reg_t hri_uart_read_SR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_SR; +} + +static inline hri_uart_rhr_reg_t hri_uart_get_RHR_RXCHR_bf(const void *const hw, hri_uart_rhr_reg_t mask) +{ + return (((Uart *)hw)->UART_RHR & UART_RHR_RXCHR(mask)) >> UART_RHR_RXCHR_Pos; +} + +static inline hri_uart_rhr_reg_t hri_uart_read_RHR_RXCHR_bf(const void *const hw) +{ + return (((Uart *)hw)->UART_RHR & UART_RHR_RXCHR_Msk) >> UART_RHR_RXCHR_Pos; +} + +static inline hri_uart_rhr_reg_t hri_uart_get_RHR_reg(const void *const hw, hri_uart_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_RHR; + tmp &= mask; + return tmp; +} + +static inline hri_uart_rhr_reg_t hri_uart_read_RHR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_RHR; +} + +static inline void hri_uart_set_MR_FILTER_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR |= UART_MR_FILTER; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_uart_get_MR_FILTER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_FILTER) >> UART_MR_FILTER_Pos; + return (bool)tmp; +} + +static inline void hri_uart_write_MR_FILTER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_MR; + tmp &= ~UART_MR_FILTER; + tmp |= value << UART_MR_FILTER_Pos; + ((Uart *)hw)->UART_MR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_MR_FILTER_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR &= ~UART_MR_FILTER; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_MR_FILTER_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR ^= UART_MR_FILTER; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_set_MR_BRSRCCK_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR |= UART_MR_BRSRCCK; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_uart_get_MR_BRSRCCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_BRSRCCK) >> UART_MR_BRSRCCK_Pos; + return (bool)tmp; +} + +static inline void hri_uart_write_MR_BRSRCCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_MR; + tmp &= ~UART_MR_BRSRCCK; + tmp |= value << UART_MR_BRSRCCK_Pos; + ((Uart *)hw)->UART_MR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_MR_BRSRCCK_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR &= ~UART_MR_BRSRCCK; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_MR_BRSRCCK_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR ^= UART_MR_BRSRCCK; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_set_MR_PAR_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR |= UART_MR_PAR(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_get_MR_PAR_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_PAR(mask)) >> UART_MR_PAR_Pos; + return tmp; +} + +static inline void hri_uart_write_MR_PAR_bf(const void *const hw, hri_uart_mr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_MR; + tmp &= ~UART_MR_PAR_Msk; + tmp |= UART_MR_PAR(data); + ((Uart *)hw)->UART_MR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_MR_PAR_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR &= ~UART_MR_PAR(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_MR_PAR_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR ^= UART_MR_PAR(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_read_MR_PAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_PAR_Msk) >> UART_MR_PAR_Pos; + return tmp; +} + +static inline void hri_uart_set_MR_CHMODE_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR |= UART_MR_CHMODE(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_get_MR_CHMODE_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_CHMODE(mask)) >> UART_MR_CHMODE_Pos; + return tmp; +} + +static inline void hri_uart_write_MR_CHMODE_bf(const void *const hw, hri_uart_mr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_MR; + tmp &= ~UART_MR_CHMODE_Msk; + tmp |= UART_MR_CHMODE(data); + ((Uart *)hw)->UART_MR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_MR_CHMODE_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR &= ~UART_MR_CHMODE(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_MR_CHMODE_bf(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR ^= UART_MR_CHMODE(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_read_MR_CHMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp = (tmp & UART_MR_CHMODE_Msk) >> UART_MR_CHMODE_Pos; + return tmp; +} + +static inline void hri_uart_set_MR_reg(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR |= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_get_MR_reg(const void *const hw, hri_uart_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_uart_write_MR_reg(const void *const hw, hri_uart_mr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_MR_reg(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR &= ~mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_MR_reg(const void *const hw, hri_uart_mr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_MR ^= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_mr_reg_t hri_uart_read_MR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_MR; +} + +static inline void hri_uart_set_BRGR_CD_bf(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR |= UART_BRGR_CD(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_brgr_reg_t hri_uart_get_BRGR_CD_bf(const void *const hw, hri_uart_brgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_BRGR; + tmp = (tmp & UART_BRGR_CD(mask)) >> UART_BRGR_CD_Pos; + return tmp; +} + +static inline void hri_uart_write_BRGR_CD_bf(const void *const hw, hri_uart_brgr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_BRGR; + tmp &= ~UART_BRGR_CD_Msk; + tmp |= UART_BRGR_CD(data); + ((Uart *)hw)->UART_BRGR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_BRGR_CD_bf(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR &= ~UART_BRGR_CD(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_BRGR_CD_bf(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR ^= UART_BRGR_CD(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_brgr_reg_t hri_uart_read_BRGR_CD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_BRGR; + tmp = (tmp & UART_BRGR_CD_Msk) >> UART_BRGR_CD_Pos; + return tmp; +} + +static inline void hri_uart_set_BRGR_reg(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR |= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_brgr_reg_t hri_uart_get_BRGR_reg(const void *const hw, hri_uart_brgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_BRGR; + tmp &= mask; + return tmp; +} + +static inline void hri_uart_write_BRGR_reg(const void *const hw, hri_uart_brgr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_BRGR_reg(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR &= ~mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_BRGR_reg(const void *const hw, hri_uart_brgr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_BRGR ^= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_brgr_reg_t hri_uart_read_BRGR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_BRGR; +} + +static inline void hri_uart_set_CMPR_CMPMODE_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR |= UART_CMPR_CMPMODE; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_uart_get_CMPR_CMPMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_CMPMODE) >> UART_CMPR_CMPMODE_Pos; + return (bool)tmp; +} + +static inline void hri_uart_write_CMPR_CMPMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_CMPR; + tmp &= ~UART_CMPR_CMPMODE; + tmp |= value << UART_CMPR_CMPMODE_Pos; + ((Uart *)hw)->UART_CMPR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_CMPR_CMPMODE_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR &= ~UART_CMPR_CMPMODE; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_CMPR_CMPMODE_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR ^= UART_CMPR_CMPMODE; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_set_CMPR_CMPPAR_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR |= UART_CMPR_CMPPAR; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_uart_get_CMPR_CMPPAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_CMPPAR) >> UART_CMPR_CMPPAR_Pos; + return (bool)tmp; +} + +static inline void hri_uart_write_CMPR_CMPPAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_CMPR; + tmp &= ~UART_CMPR_CMPPAR; + tmp |= value << UART_CMPR_CMPPAR_Pos; + ((Uart *)hw)->UART_CMPR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_CMPR_CMPPAR_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR &= ~UART_CMPR_CMPPAR; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_CMPR_CMPPAR_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR ^= UART_CMPR_CMPPAR; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_set_CMPR_VAL1_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR |= UART_CMPR_VAL1(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_get_CMPR_VAL1_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_VAL1(mask)) >> UART_CMPR_VAL1_Pos; + return tmp; +} + +static inline void hri_uart_write_CMPR_VAL1_bf(const void *const hw, hri_uart_cmpr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_CMPR; + tmp &= ~UART_CMPR_VAL1_Msk; + tmp |= UART_CMPR_VAL1(data); + ((Uart *)hw)->UART_CMPR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_CMPR_VAL1_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR &= ~UART_CMPR_VAL1(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_CMPR_VAL1_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR ^= UART_CMPR_VAL1(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_read_CMPR_VAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_VAL1_Msk) >> UART_CMPR_VAL1_Pos; + return tmp; +} + +static inline void hri_uart_set_CMPR_VAL2_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR |= UART_CMPR_VAL2(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_get_CMPR_VAL2_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_VAL2(mask)) >> UART_CMPR_VAL2_Pos; + return tmp; +} + +static inline void hri_uart_write_CMPR_VAL2_bf(const void *const hw, hri_uart_cmpr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_CMPR; + tmp &= ~UART_CMPR_VAL2_Msk; + tmp |= UART_CMPR_VAL2(data); + ((Uart *)hw)->UART_CMPR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_CMPR_VAL2_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR &= ~UART_CMPR_VAL2(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_CMPR_VAL2_bf(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR ^= UART_CMPR_VAL2(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_read_CMPR_VAL2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp = (tmp & UART_CMPR_VAL2_Msk) >> UART_CMPR_VAL2_Pos; + return tmp; +} + +static inline void hri_uart_set_CMPR_reg(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR |= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_get_CMPR_reg(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_CMPR; + tmp &= mask; + return tmp; +} + +static inline void hri_uart_write_CMPR_reg(const void *const hw, hri_uart_cmpr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_CMPR_reg(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR &= ~mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_CMPR_reg(const void *const hw, hri_uart_cmpr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CMPR ^= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_cmpr_reg_t hri_uart_read_CMPR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_CMPR; +} + +static inline void hri_uart_set_WPMR_WPEN_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR |= UART_WPMR_WPEN; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_uart_get_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_WPMR; + tmp = (tmp & UART_WPMR_WPEN) >> UART_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_uart_write_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_WPMR; + tmp &= ~UART_WPMR_WPEN; + tmp |= value << UART_WPMR_WPEN_Pos; + ((Uart *)hw)->UART_WPMR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_WPMR_WPEN_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR &= ~UART_WPMR_WPEN; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_WPMR_WPEN_bit(const void *const hw) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR ^= UART_WPMR_WPEN; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_set_WPMR_WPKEY_bf(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR |= UART_WPMR_WPKEY(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_wpmr_reg_t hri_uart_get_WPMR_WPKEY_bf(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_WPMR; + tmp = (tmp & UART_WPMR_WPKEY(mask)) >> UART_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_uart_write_WPMR_WPKEY_bf(const void *const hw, hri_uart_wpmr_reg_t data) +{ + uint32_t tmp; + UART_CRITICAL_SECTION_ENTER(); + tmp = ((Uart *)hw)->UART_WPMR; + tmp &= ~UART_WPMR_WPKEY_Msk; + tmp |= UART_WPMR_WPKEY(data); + ((Uart *)hw)->UART_WPMR = tmp; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_WPMR_WPKEY_bf(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR &= ~UART_WPMR_WPKEY(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_WPMR_WPKEY_bf(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR ^= UART_WPMR_WPKEY(mask); + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_wpmr_reg_t hri_uart_read_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_WPMR; + tmp = (tmp & UART_WPMR_WPKEY_Msk) >> UART_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_uart_set_WPMR_reg(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR |= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_wpmr_reg_t hri_uart_get_WPMR_reg(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Uart *)hw)->UART_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_uart_write_WPMR_reg(const void *const hw, hri_uart_wpmr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_clear_WPMR_reg(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR &= ~mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_toggle_WPMR_reg(const void *const hw, hri_uart_wpmr_reg_t mask) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_WPMR ^= mask; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_uart_wpmr_reg_t hri_uart_read_WPMR_reg(const void *const hw) +{ + return ((Uart *)hw)->UART_WPMR; +} + +static inline void hri_uart_write_CR_reg(const void *const hw, hri_uart_cr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_CR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_uart_write_THR_reg(const void *const hw, hri_uart_thr_reg_t data) +{ + UART_CRITICAL_SECTION_ENTER(); + ((Uart *)hw)->UART_THR = data; + UART_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_UART_E70B_H_INCLUDED */ +#endif /* _SAME70_UART_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_usart_e70b.h b/bsp/microchip/same70/bsp/hri/hri_usart_e70b.h new file mode 100644 index 0000000000..79ffff017d --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_usart_e70b.h @@ -0,0 +1,5424 @@ +/** + * \file + * + * \brief SAM USART + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_USART_COMPONENT_ +#ifndef _HRI_USART_E70B_H_INCLUDED_ +#define _HRI_USART_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USART_CRITICAL_SECTIONS) +#define USART_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USART_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USART_CRITICAL_SECTION_ENTER() +#define USART_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_usart_us_brgr_reg_t; +typedef uint32_t hri_usart_us_cr_reg_t; +typedef uint32_t hri_usart_us_csr_reg_t; +typedef uint32_t hri_usart_us_fidi_reg_t; +typedef uint32_t hri_usart_us_icdiff_reg_t; +typedef uint32_t hri_usart_us_idtrx_reg_t; +typedef uint32_t hri_usart_us_idttx_reg_t; +typedef uint32_t hri_usart_us_if_reg_t; +typedef uint32_t hri_usart_us_imr_reg_t; +typedef uint32_t hri_usart_us_linbrr_reg_t; +typedef uint32_t hri_usart_us_linir_reg_t; +typedef uint32_t hri_usart_us_linmr_reg_t; +typedef uint32_t hri_usart_us_lonb1rx_reg_t; +typedef uint32_t hri_usart_us_lonb1tx_reg_t; +typedef uint32_t hri_usart_us_lonbl_reg_t; +typedef uint32_t hri_usart_us_londl_reg_t; +typedef uint32_t hri_usart_us_lonl2hdr_reg_t; +typedef uint32_t hri_usart_us_lonmr_reg_t; +typedef uint32_t hri_usart_us_lonpr_reg_t; +typedef uint32_t hri_usart_us_lonprio_reg_t; +typedef uint32_t hri_usart_us_man_reg_t; +typedef uint32_t hri_usart_us_mr_reg_t; +typedef uint32_t hri_usart_us_ner_reg_t; +typedef uint32_t hri_usart_us_rhr_reg_t; +typedef uint32_t hri_usart_us_rtor_reg_t; +typedef uint32_t hri_usart_us_thr_reg_t; +typedef uint32_t hri_usart_us_ttgr_reg_t; +typedef uint32_t hri_usart_us_wpmr_reg_t; +typedef uint32_t hri_usart_us_wpsr_reg_t; + +static inline void hri_usart_set_US_IMR_RXRDY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_RXRDY; +} + +static inline bool hri_usart_get_US_IMR_RXRDY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_RXRDY) >> US_IMR_RXRDY_Pos; +} + +static inline void hri_usart_write_US_IMR_RXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_RXRDY; + } else { + ((Usart *)hw)->US_IER = US_IMR_RXRDY; + } +} + +static inline void hri_usart_clear_US_IMR_RXRDY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_RXRDY; +} + +static inline void hri_usart_set_US_IMR_TXRDY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_TXRDY; +} + +static inline bool hri_usart_get_US_IMR_TXRDY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_TXRDY) >> US_IMR_TXRDY_Pos; +} + +static inline void hri_usart_write_US_IMR_TXRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_TXRDY; + } else { + ((Usart *)hw)->US_IER = US_IMR_TXRDY; + } +} + +static inline void hri_usart_clear_US_IMR_TXRDY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_TXRDY; +} + +static inline void hri_usart_set_US_IMR_USART_RXBRK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_RXBRK; +} + +static inline bool hri_usart_get_US_IMR_USART_RXBRK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_RXBRK) >> US_IMR_USART_RXBRK_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_RXBRK; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_RXBRK; + } +} + +static inline void hri_usart_clear_US_IMR_USART_RXBRK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_RXBRK; +} + +static inline void hri_usart_set_US_IMR_OVRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_OVRE; +} + +static inline bool hri_usart_get_US_IMR_OVRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_OVRE) >> US_IMR_OVRE_Pos; +} + +static inline void hri_usart_write_US_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_OVRE; + } else { + ((Usart *)hw)->US_IER = US_IMR_OVRE; + } +} + +static inline void hri_usart_clear_US_IMR_OVRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_OVRE; +} + +static inline void hri_usart_set_US_IMR_USART_LIN_FRAME_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_FRAME; +} + +static inline bool hri_usart_get_US_IMR_USART_LIN_FRAME_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_LIN_FRAME) >> US_IMR_USART_LIN_FRAME_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_LIN_FRAME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_FRAME; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_FRAME; + } +} + +static inline void hri_usart_clear_US_IMR_USART_LIN_FRAME_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_FRAME; +} + +static inline void hri_usart_set_US_IMR_USART_LIN_PARE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_PARE; +} + +static inline bool hri_usart_get_US_IMR_USART_LIN_PARE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_LIN_PARE) >> US_IMR_USART_LIN_PARE_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_LIN_PARE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_PARE; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_PARE; + } +} + +static inline void hri_usart_clear_US_IMR_USART_LIN_PARE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_PARE; +} + +static inline void hri_usart_set_US_IMR_USART_LIN_TIMEOUT_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_TIMEOUT; +} + +static inline bool hri_usart_get_US_IMR_USART_LIN_TIMEOUT_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_LIN_TIMEOUT) >> US_IMR_USART_LIN_TIMEOUT_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_LIN_TIMEOUT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_TIMEOUT; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_LIN_TIMEOUT; + } +} + +static inline void hri_usart_clear_US_IMR_USART_LIN_TIMEOUT_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_LIN_TIMEOUT; +} + +static inline void hri_usart_set_US_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_TXEMPTY; +} + +static inline bool hri_usart_get_US_IMR_TXEMPTY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_TXEMPTY) >> US_IMR_TXEMPTY_Pos; +} + +static inline void hri_usart_write_US_IMR_TXEMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_TXEMPTY; + } else { + ((Usart *)hw)->US_IER = US_IMR_TXEMPTY; + } +} + +static inline void hri_usart_clear_US_IMR_TXEMPTY_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_TXEMPTY; +} + +static inline void hri_usart_set_US_IMR_USART_ITER_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_ITER; +} + +static inline bool hri_usart_get_US_IMR_USART_ITER_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_ITER) >> US_IMR_USART_ITER_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_ITER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_ITER; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_ITER; + } +} + +static inline void hri_usart_clear_US_IMR_USART_ITER_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_ITER; +} + +static inline void hri_usart_set_US_IMR_USART_NACK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_NACK; +} + +static inline bool hri_usart_get_US_IMR_USART_NACK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_NACK) >> US_IMR_USART_NACK_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_NACK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_NACK; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_NACK; + } +} + +static inline void hri_usart_clear_US_IMR_USART_NACK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_NACK; +} + +static inline void hri_usart_set_US_IMR_RIIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_RIIC; +} + +static inline bool hri_usart_get_US_IMR_RIIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_RIIC) >> US_IMR_RIIC_Pos; +} + +static inline void hri_usart_write_US_IMR_RIIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_RIIC; + } else { + ((Usart *)hw)->US_IER = US_IMR_RIIC; + } +} + +static inline void hri_usart_clear_US_IMR_RIIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_RIIC; +} + +static inline void hri_usart_set_US_IMR_DSRIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_DSRIC; +} + +static inline bool hri_usart_get_US_IMR_DSRIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_DSRIC) >> US_IMR_DSRIC_Pos; +} + +static inline void hri_usart_write_US_IMR_DSRIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_DSRIC; + } else { + ((Usart *)hw)->US_IER = US_IMR_DSRIC; + } +} + +static inline void hri_usart_clear_US_IMR_DSRIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_DSRIC; +} + +static inline void hri_usart_set_US_IMR_DCDIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_DCDIC; +} + +static inline bool hri_usart_get_US_IMR_DCDIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_DCDIC) >> US_IMR_DCDIC_Pos; +} + +static inline void hri_usart_write_US_IMR_DCDIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_DCDIC; + } else { + ((Usart *)hw)->US_IER = US_IMR_DCDIC; + } +} + +static inline void hri_usart_clear_US_IMR_DCDIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_DCDIC; +} + +static inline void hri_usart_set_US_IMR_USART_CTSIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_CTSIC; +} + +static inline bool hri_usart_get_US_IMR_USART_CTSIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_CTSIC) >> US_IMR_USART_CTSIC_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_CTSIC; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_CTSIC; + } +} + +static inline void hri_usart_clear_US_IMR_USART_CTSIC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_CTSIC; +} + +static inline void hri_usart_set_US_IMR_USART_MANE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_USART_MANE; +} + +static inline bool hri_usart_get_US_IMR_USART_MANE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_USART_MANE) >> US_IMR_USART_MANE_Pos; +} + +static inline void hri_usart_write_US_IMR_USART_MANE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_USART_MANE; + } else { + ((Usart *)hw)->US_IER = US_IMR_USART_MANE; + } +} + +static inline void hri_usart_clear_US_IMR_USART_MANE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_USART_MANE; +} + +static inline void hri_usart_set_US_IMR_LON_SPI_UNRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_SPI_UNRE; +} + +static inline bool hri_usart_get_US_IMR_LON_SPI_UNRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_SPI_UNRE) >> US_IMR_LON_SPI_UNRE_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_SPI_UNRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_SPI_UNRE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_SPI_UNRE; + } +} + +static inline void hri_usart_clear_US_IMR_LON_SPI_UNRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_SPI_UNRE; +} + +static inline void hri_usart_set_US_IMR_SPI_NSSE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_SPI_NSSE; +} + +static inline bool hri_usart_get_US_IMR_SPI_NSSE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_SPI_NSSE) >> US_IMR_SPI_NSSE_Pos; +} + +static inline void hri_usart_write_US_IMR_SPI_NSSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_SPI_NSSE; + } else { + ((Usart *)hw)->US_IER = US_IMR_SPI_NSSE; + } +} + +static inline void hri_usart_clear_US_IMR_SPI_NSSE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_SPI_NSSE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINBK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINBK; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINBK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINBK) >> US_IMR_LIN_LINBK_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINBK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINBK; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINBK; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINBK_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINBK; +} + +static inline void hri_usart_set_US_IMR_LIN_LINID_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINID; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINID_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINID) >> US_IMR_LIN_LINID_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINID_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINID; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINID; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINID_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINID; +} + +static inline void hri_usart_set_US_IMR_LIN_LINTC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINTC; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINTC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINTC) >> US_IMR_LIN_LINTC_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINTC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINTC; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINTC; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINTC_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINTC; +} + +static inline void hri_usart_set_US_IMR_LIN_LINBE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINBE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINBE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINBE) >> US_IMR_LIN_LINBE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINBE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINBE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINBE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINBE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINBE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINISFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINISFE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINISFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINISFE) >> US_IMR_LIN_LINISFE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINISFE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINISFE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINISFE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINISFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINISFE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINIPE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINIPE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINIPE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINIPE) >> US_IMR_LIN_LINIPE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINIPE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINIPE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINIPE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINIPE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINIPE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINCE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINCE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINCE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINCE) >> US_IMR_LIN_LINCE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINCE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINCE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINCE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINCE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINCE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINSNRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINSNRE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINSNRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINSNRE) >> US_IMR_LIN_LINSNRE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINSNRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINSNRE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINSNRE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINSNRE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINSNRE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINSTE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINSTE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINSTE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINSTE) >> US_IMR_LIN_LINSTE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINSTE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINSTE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINSTE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINSTE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINSTE; +} + +static inline void hri_usart_set_US_IMR_LIN_LINHTE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LIN_LINHTE; +} + +static inline bool hri_usart_get_US_IMR_LIN_LINHTE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LIN_LINHTE) >> US_IMR_LIN_LINHTE_Pos; +} + +static inline void hri_usart_write_US_IMR_LIN_LINHTE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINHTE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LIN_LINHTE; + } +} + +static inline void hri_usart_clear_US_IMR_LIN_LINHTE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LIN_LINHTE; +} + +static inline void hri_usart_set_US_IMR_LON_LSFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LSFE; +} + +static inline bool hri_usart_get_US_IMR_LON_LSFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LSFE) >> US_IMR_LON_LSFE_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LSFE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LSFE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LSFE; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LSFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LSFE; +} + +static inline void hri_usart_set_US_IMR_LON_LCRCE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LCRCE; +} + +static inline bool hri_usart_get_US_IMR_LON_LCRCE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LCRCE) >> US_IMR_LON_LCRCE_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LCRCE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LCRCE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LCRCE; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LCRCE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LCRCE; +} + +static inline void hri_usart_set_US_IMR_LON_LTXD_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LTXD; +} + +static inline bool hri_usart_get_US_IMR_LON_LTXD_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LTXD) >> US_IMR_LON_LTXD_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LTXD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LTXD; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LTXD; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LTXD_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LTXD; +} + +static inline void hri_usart_set_US_IMR_LON_LCOL_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LCOL; +} + +static inline bool hri_usart_get_US_IMR_LON_LCOL_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LCOL) >> US_IMR_LON_LCOL_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LCOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LCOL; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LCOL; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LCOL_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LCOL; +} + +static inline void hri_usart_set_US_IMR_LON_LFET_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LFET; +} + +static inline bool hri_usart_get_US_IMR_LON_LFET_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LFET) >> US_IMR_LON_LFET_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LFET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LFET; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LFET; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LFET_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LFET; +} + +static inline void hri_usart_set_US_IMR_LON_LRXD_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LRXD; +} + +static inline bool hri_usart_get_US_IMR_LON_LRXD_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LRXD) >> US_IMR_LON_LRXD_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LRXD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LRXD; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LRXD; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LRXD_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LRXD; +} + +static inline void hri_usart_set_US_IMR_LON_LBLOVFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IER = US_IMR_LON_LBLOVFE; +} + +static inline bool hri_usart_get_US_IMR_LON_LBLOVFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_IMR & US_IMR_LON_LBLOVFE) >> US_IMR_LON_LBLOVFE_Pos; +} + +static inline void hri_usart_write_US_IMR_LON_LBLOVFE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usart *)hw)->US_IDR = US_IMR_LON_LBLOVFE; + } else { + ((Usart *)hw)->US_IER = US_IMR_LON_LBLOVFE; + } +} + +static inline void hri_usart_clear_US_IMR_LON_LBLOVFE_bit(const void *const hw) +{ + ((Usart *)hw)->US_IDR = US_IMR_LON_LBLOVFE; +} + +static inline void hri_usart_set_US_IMR_reg(const void *const hw, hri_usart_us_imr_reg_t mask) +{ + ((Usart *)hw)->US_IER = mask; +} + +static inline hri_usart_us_imr_reg_t hri_usart_get_US_IMR_reg(const void *const hw, hri_usart_us_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IMR; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_imr_reg_t hri_usart_read_US_IMR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_IMR; +} + +static inline void hri_usart_write_US_IMR_reg(const void *const hw, hri_usart_us_imr_reg_t data) +{ + ((Usart *)hw)->US_IER = data; + ((Usart *)hw)->US_IDR = ~data; +} + +static inline void hri_usart_clear_US_IMR_reg(const void *const hw, hri_usart_us_imr_reg_t mask) +{ + ((Usart *)hw)->US_IDR = mask; +} + +static inline bool hri_usart_get_US_CSR_RXRDY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_RXRDY) > 0; +} + +static inline bool hri_usart_get_US_CSR_TXRDY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_TXRDY) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_RXBRK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_RXBRK) > 0; +} + +static inline bool hri_usart_get_US_CSR_OVRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_OVRE) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_LIN_FRAME_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_LIN_FRAME) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_LIN_PARE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_LIN_PARE) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_LIN_TIMEOUT_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_LIN_TIMEOUT) > 0; +} + +static inline bool hri_usart_get_US_CSR_TXEMPTY_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_TXEMPTY) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_ITER_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_ITER) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_NACK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_NACK) > 0; +} + +static inline bool hri_usart_get_US_CSR_RIIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_RIIC) > 0; +} + +static inline bool hri_usart_get_US_CSR_DSRIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_DSRIC) > 0; +} + +static inline bool hri_usart_get_US_CSR_DCDIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_DCDIC) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_CTSIC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_CTSIC) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_RI_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_RI) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_DSR_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_DSR) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_DCD_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_DCD) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_CTS_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_CTS) > 0; +} + +static inline bool hri_usart_get_US_CSR_USART_MANERR_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_USART_MANERR) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_SPI_UNRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_SPI_UNRE) > 0; +} + +static inline bool hri_usart_get_US_CSR_SPI_NSSE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_SPI_NSSE) > 0; +} + +static inline bool hri_usart_get_US_CSR_SPI_NSS_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_SPI_NSS) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINBK_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINBK) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINID_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINID) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINTC_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINTC) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINBLS_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINBLS) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINBE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINBE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINISFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINISFE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINIPE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINIPE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINCE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINCE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINSNRE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINSNRE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINSTE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINSTE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LIN_LINHTE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LIN_LINHTE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LSFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LSFE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LCRCE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LCRCE) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LTXD_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LTXD) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LCOL_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LCOL) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LFET_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LFET) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LRXD_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LRXD) > 0; +} + +static inline bool hri_usart_get_US_CSR_LON_LBLOVFE_bit(const void *const hw) +{ + return (((Usart *)hw)->US_CSR & US_CSR_LON_LBLOVFE) > 0; +} + +static inline hri_usart_us_csr_reg_t hri_usart_get_US_CSR_reg(const void *const hw, hri_usart_us_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_CSR; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_csr_reg_t hri_usart_read_US_CSR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_CSR; +} + +static inline bool hri_usart_get_US_RHR_RXSYNH_bit(const void *const hw) +{ + return (((Usart *)hw)->US_RHR & US_RHR_RXSYNH) > 0; +} + +static inline hri_usart_us_rhr_reg_t hri_usart_get_US_RHR_RXCHR_bf(const void *const hw, hri_usart_us_rhr_reg_t mask) +{ + return (((Usart *)hw)->US_RHR & US_RHR_RXCHR(mask)) >> US_RHR_RXCHR_Pos; +} + +static inline hri_usart_us_rhr_reg_t hri_usart_read_US_RHR_RXCHR_bf(const void *const hw) +{ + return (((Usart *)hw)->US_RHR & US_RHR_RXCHR_Msk) >> US_RHR_RXCHR_Pos; +} + +static inline hri_usart_us_rhr_reg_t hri_usart_get_US_RHR_reg(const void *const hw, hri_usart_us_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_RHR; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_rhr_reg_t hri_usart_read_US_RHR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_RHR; +} + +static inline hri_usart_us_ner_reg_t hri_usart_get_US_NER_NB_ERRORS_bf(const void *const hw, + hri_usart_us_ner_reg_t mask) +{ + return (((Usart *)hw)->US_NER & US_NER_NB_ERRORS(mask)) >> US_NER_NB_ERRORS_Pos; +} + +static inline hri_usart_us_ner_reg_t hri_usart_read_US_NER_NB_ERRORS_bf(const void *const hw) +{ + return (((Usart *)hw)->US_NER & US_NER_NB_ERRORS_Msk) >> US_NER_NB_ERRORS_Pos; +} + +static inline hri_usart_us_ner_reg_t hri_usart_get_US_NER_reg(const void *const hw, hri_usart_us_ner_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_NER; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_ner_reg_t hri_usart_read_US_NER_reg(const void *const hw) +{ + return ((Usart *)hw)->US_NER; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_get_US_LINBRR_LINCD_bf(const void *const hw, + hri_usart_us_linbrr_reg_t mask) +{ + return (((Usart *)hw)->US_LINBRR & US_LINBRR_LINCD(mask)) >> US_LINBRR_LINCD_Pos; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_read_US_LINBRR_LINCD_bf(const void *const hw) +{ + return (((Usart *)hw)->US_LINBRR & US_LINBRR_LINCD_Msk) >> US_LINBRR_LINCD_Pos; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_get_US_LINBRR_LINFP_bf(const void *const hw, + hri_usart_us_linbrr_reg_t mask) +{ + return (((Usart *)hw)->US_LINBRR & US_LINBRR_LINFP(mask)) >> US_LINBRR_LINFP_Pos; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_read_US_LINBRR_LINFP_bf(const void *const hw) +{ + return (((Usart *)hw)->US_LINBRR & US_LINBRR_LINFP_Msk) >> US_LINBRR_LINFP_Pos; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_get_US_LINBRR_reg(const void *const hw, + hri_usart_us_linbrr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINBRR; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_linbrr_reg_t hri_usart_read_US_LINBRR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LINBRR; +} + +static inline hri_usart_us_lonbl_reg_t hri_usart_get_US_LONBL_LONBL_bf(const void *const hw, + hri_usart_us_lonbl_reg_t mask) +{ + return (((Usart *)hw)->US_LONBL & US_LONBL_LONBL(mask)) >> US_LONBL_LONBL_Pos; +} + +static inline hri_usart_us_lonbl_reg_t hri_usart_read_US_LONBL_LONBL_bf(const void *const hw) +{ + return (((Usart *)hw)->US_LONBL & US_LONBL_LONBL_Msk) >> US_LONBL_LONBL_Pos; +} + +static inline hri_usart_us_lonbl_reg_t hri_usart_get_US_LONBL_reg(const void *const hw, hri_usart_us_lonbl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONBL; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_lonbl_reg_t hri_usart_read_US_LONBL_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONBL; +} + +static inline bool hri_usart_get_US_WPSR_WPVS_bit(const void *const hw) +{ + return (((Usart *)hw)->US_WPSR & US_WPSR_WPVS) > 0; +} + +static inline hri_usart_us_wpsr_reg_t hri_usart_get_US_WPSR_WPVSRC_bf(const void *const hw, + hri_usart_us_wpsr_reg_t mask) +{ + return (((Usart *)hw)->US_WPSR & US_WPSR_WPVSRC(mask)) >> US_WPSR_WPVSRC_Pos; +} + +static inline hri_usart_us_wpsr_reg_t hri_usart_read_US_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Usart *)hw)->US_WPSR & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; +} + +static inline hri_usart_us_wpsr_reg_t hri_usart_get_US_WPSR_reg(const void *const hw, hri_usart_us_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_WPSR; + tmp &= mask; + return tmp; +} + +static inline hri_usart_us_wpsr_reg_t hri_usart_read_US_WPSR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_WPSR; +} + +static inline void hri_usart_set_US_MR_USART_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_SYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_SYNC) >> US_MR_USART_SYNC_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_SYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_SYNC; + tmp |= value << US_MR_USART_SYNC_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_MSBF_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MSBF; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_MSBF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MSBF) >> US_MR_USART_MSBF_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_MSBF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MSBF; + tmp |= value << US_MR_USART_MSBF_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MSBF_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MSBF; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MSBF_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MSBF; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_MODE9_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MODE9; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_MODE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MODE9) >> US_MR_USART_MODE9_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_MODE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MODE9; + tmp |= value << US_MR_USART_MODE9_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MODE9_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MODE9; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MODE9_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MODE9; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_CLKO_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_CLKO; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_CLKO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_CLKO) >> US_MR_CLKO_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_CLKO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_CLKO; + tmp |= value << US_MR_CLKO_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_CLKO_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_CLKO; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_CLKO_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_CLKO; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_OVER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_OVER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_OVER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_OVER) >> US_MR_USART_OVER_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_OVER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_OVER; + tmp |= value << US_MR_USART_OVER_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_OVER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_OVER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_OVER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_OVER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_INACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_INACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_INACK) >> US_MR_USART_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_INACK; + tmp |= value << US_MR_USART_INACK_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_INACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_INACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_INACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_INACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_DSNACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_DSNACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_DSNACK) >> US_MR_USART_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_DSNACK; + tmp |= value << US_MR_USART_DSNACK_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_DSNACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_DSNACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_DSNACK_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_DSNACK; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_VAR_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_VAR_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_VAR_SYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_VAR_SYNC) >> US_MR_USART_VAR_SYNC_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_VAR_SYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_VAR_SYNC; + tmp |= value << US_MR_USART_VAR_SYNC_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_VAR_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_VAR_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_VAR_SYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_VAR_SYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_INVDATA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_INVDATA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_INVDATA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_INVDATA) >> US_MR_USART_INVDATA_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_INVDATA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_INVDATA; + tmp |= value << US_MR_USART_INVDATA_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_INVDATA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_INVDATA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_INVDATA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_INVDATA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_FILTER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_FILTER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_FILTER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_FILTER) >> US_MR_USART_FILTER_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_FILTER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_FILTER; + tmp |= value << US_MR_USART_FILTER_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_FILTER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_FILTER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_FILTER_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_FILTER; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_MAN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MAN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_MAN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MAN) >> US_MR_USART_MAN_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_MAN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MAN; + tmp |= value << US_MR_USART_MAN_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MAN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MAN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MAN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MAN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_MODSYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MODSYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_MODSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MODSYNC) >> US_MR_USART_MODSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_MODSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MODSYNC; + tmp |= value << US_MR_USART_MODSYNC_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MODSYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MODSYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MODSYNC_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MODSYNC; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_ONEBIT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_ONEBIT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_USART_ONEBIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_ONEBIT) >> US_MR_USART_ONEBIT_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_USART_ONEBIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_ONEBIT; + tmp |= value << US_MR_USART_ONEBIT_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_ONEBIT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_ONEBIT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_ONEBIT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_ONEBIT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_SPI_CPHA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_SPI_CPHA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_SPI_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_SPI_CPHA) >> US_MR_SPI_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_SPI_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_SPI_CPHA; + tmp |= value << US_MR_SPI_CPHA_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_SPI_CPHA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_SPI_CPHA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_SPI_CPHA_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_SPI_CPHA; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_SPI_CPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_SPI_CPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_SPI_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_SPI_CPOL) >> US_MR_SPI_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_SPI_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_SPI_CPOL; + tmp |= value << US_MR_SPI_CPOL_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_SPI_CPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_SPI_CPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_SPI_CPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_SPI_CPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_SPI_WRDBT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_SPI_WRDBT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MR_SPI_WRDBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_SPI_WRDBT) >> US_MR_SPI_WRDBT_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MR_SPI_WRDBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_SPI_WRDBT; + tmp |= value << US_MR_SPI_WRDBT_Pos; + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_SPI_WRDBT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_SPI_WRDBT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_SPI_WRDBT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_SPI_WRDBT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MR_USART_MODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USART_MODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MODE(mask)) >> US_MR_USART_MODE_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USART_MODE_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MODE_Msk; + tmp |= US_MR_USART_MODE(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USART_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MODE_Msk) >> US_MR_USART_MODE_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_USCLKS_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USCLKS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USCLKS_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USCLKS(mask)) >> US_MR_USCLKS_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USCLKS_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USCLKS_Msk; + tmp |= US_MR_USCLKS(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USCLKS_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USCLKS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USCLKS_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USCLKS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USCLKS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USCLKS_Msk) >> US_MR_USCLKS_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_CHRL_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_CHRL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_CHRL_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_CHRL(mask)) >> US_MR_CHRL_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_CHRL_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_CHRL_Msk; + tmp |= US_MR_CHRL(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_CHRL_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_CHRL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_CHRL_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_CHRL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_CHRL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_CHRL_Msk) >> US_MR_CHRL_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_USART_PAR_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_PAR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USART_PAR_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_PAR(mask)) >> US_MR_USART_PAR_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USART_PAR_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_PAR_Msk; + tmp |= US_MR_USART_PAR(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_PAR_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_PAR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_PAR_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_PAR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USART_PAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_PAR_Msk) >> US_MR_USART_PAR_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_USART_NBSTOP_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_NBSTOP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USART_NBSTOP_bf(const void *const hw, + hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_NBSTOP(mask)) >> US_MR_USART_NBSTOP_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USART_NBSTOP_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_NBSTOP_Msk; + tmp |= US_MR_USART_NBSTOP(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_NBSTOP_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_NBSTOP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_NBSTOP_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_NBSTOP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USART_NBSTOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_NBSTOP_Msk) >> US_MR_USART_NBSTOP_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_USART_CHMODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_CHMODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USART_CHMODE_bf(const void *const hw, + hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_CHMODE(mask)) >> US_MR_USART_CHMODE_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USART_CHMODE_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_CHMODE_Msk; + tmp |= US_MR_USART_CHMODE(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_CHMODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_CHMODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_CHMODE_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_CHMODE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USART_CHMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_CHMODE_Msk) >> US_MR_USART_CHMODE_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_USART_MAX_ITERATION_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= US_MR_USART_MAX_ITERATION(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_USART_MAX_ITERATION_bf(const void *const hw, + hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MAX_ITERATION(mask)) >> US_MR_USART_MAX_ITERATION_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MR_USART_MAX_ITERATION_bf(const void *const hw, hri_usart_us_mr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MR; + tmp &= ~US_MR_USART_MAX_ITERATION_Msk; + tmp |= US_MR_USART_MAX_ITERATION(data); + ((Usart *)hw)->US_MR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_USART_MAX_ITERATION_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~US_MR_USART_MAX_ITERATION(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_USART_MAX_ITERATION_bf(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= US_MR_USART_MAX_ITERATION(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_USART_MAX_ITERATION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp = (tmp & US_MR_USART_MAX_ITERATION_Msk) >> US_MR_USART_MAX_ITERATION_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MR_reg(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_get_US_MR_reg(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_MR_reg(const void *const hw, hri_usart_us_mr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MR_reg(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MR_reg(const void *const hw, hri_usart_us_mr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_mr_reg_t hri_usart_read_US_MR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_MR; +} + +static inline void hri_usart_set_US_BRGR_CD_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR |= US_BRGR_CD(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_get_US_BRGR_CD_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_BRGR; + tmp = (tmp & US_BRGR_CD(mask)) >> US_BRGR_CD_Pos; + return tmp; +} + +static inline void hri_usart_write_US_BRGR_CD_bf(const void *const hw, hri_usart_us_brgr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_BRGR; + tmp &= ~US_BRGR_CD_Msk; + tmp |= US_BRGR_CD(data); + ((Usart *)hw)->US_BRGR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_BRGR_CD_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR &= ~US_BRGR_CD(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_BRGR_CD_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR ^= US_BRGR_CD(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_read_US_BRGR_CD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_BRGR; + tmp = (tmp & US_BRGR_CD_Msk) >> US_BRGR_CD_Pos; + return tmp; +} + +static inline void hri_usart_set_US_BRGR_FP_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR |= US_BRGR_FP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_get_US_BRGR_FP_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_BRGR; + tmp = (tmp & US_BRGR_FP(mask)) >> US_BRGR_FP_Pos; + return tmp; +} + +static inline void hri_usart_write_US_BRGR_FP_bf(const void *const hw, hri_usart_us_brgr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_BRGR; + tmp &= ~US_BRGR_FP_Msk; + tmp |= US_BRGR_FP(data); + ((Usart *)hw)->US_BRGR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_BRGR_FP_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR &= ~US_BRGR_FP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_BRGR_FP_bf(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR ^= US_BRGR_FP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_read_US_BRGR_FP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_BRGR; + tmp = (tmp & US_BRGR_FP_Msk) >> US_BRGR_FP_Pos; + return tmp; +} + +static inline void hri_usart_set_US_BRGR_reg(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_get_US_BRGR_reg(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_BRGR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_BRGR_reg(const void *const hw, hri_usart_us_brgr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_BRGR_reg(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_BRGR_reg(const void *const hw, hri_usart_us_brgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_BRGR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_brgr_reg_t hri_usart_read_US_BRGR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_BRGR; +} + +static inline void hri_usart_set_US_RTOR_TO_bf(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR |= US_RTOR_TO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_rtor_reg_t hri_usart_get_US_RTOR_TO_bf(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_RTOR; + tmp = (tmp & US_RTOR_TO(mask)) >> US_RTOR_TO_Pos; + return tmp; +} + +static inline void hri_usart_write_US_RTOR_TO_bf(const void *const hw, hri_usart_us_rtor_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_RTOR; + tmp &= ~US_RTOR_TO_Msk; + tmp |= US_RTOR_TO(data); + ((Usart *)hw)->US_RTOR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_RTOR_TO_bf(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR &= ~US_RTOR_TO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_RTOR_TO_bf(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR ^= US_RTOR_TO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_rtor_reg_t hri_usart_read_US_RTOR_TO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_RTOR; + tmp = (tmp & US_RTOR_TO_Msk) >> US_RTOR_TO_Pos; + return tmp; +} + +static inline void hri_usart_set_US_RTOR_reg(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_rtor_reg_t hri_usart_get_US_RTOR_reg(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_RTOR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_RTOR_reg(const void *const hw, hri_usart_us_rtor_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_RTOR_reg(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_RTOR_reg(const void *const hw, hri_usart_us_rtor_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_RTOR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_rtor_reg_t hri_usart_read_US_RTOR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_RTOR; +} + +static inline void hri_usart_set_US_TTGR_USART_TG_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR |= US_TTGR_USART_TG(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_get_US_TTGR_USART_TG_bf(const void *const hw, + hri_usart_us_ttgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_TTGR; + tmp = (tmp & US_TTGR_USART_TG(mask)) >> US_TTGR_USART_TG_Pos; + return tmp; +} + +static inline void hri_usart_write_US_TTGR_USART_TG_bf(const void *const hw, hri_usart_us_ttgr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_TTGR; + tmp &= ~US_TTGR_USART_TG_Msk; + tmp |= US_TTGR_USART_TG(data); + ((Usart *)hw)->US_TTGR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_TTGR_USART_TG_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR &= ~US_TTGR_USART_TG(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_TTGR_USART_TG_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR ^= US_TTGR_USART_TG(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_read_US_TTGR_USART_TG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_TTGR; + tmp = (tmp & US_TTGR_USART_TG_Msk) >> US_TTGR_USART_TG_Pos; + return tmp; +} + +static inline void hri_usart_set_US_TTGR_LON_PCYCLE_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR |= US_TTGR_LON_PCYCLE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_get_US_TTGR_LON_PCYCLE_bf(const void *const hw, + hri_usart_us_ttgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_TTGR; + tmp = (tmp & US_TTGR_LON_PCYCLE(mask)) >> US_TTGR_LON_PCYCLE_Pos; + return tmp; +} + +static inline void hri_usart_write_US_TTGR_LON_PCYCLE_bf(const void *const hw, hri_usart_us_ttgr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_TTGR; + tmp &= ~US_TTGR_LON_PCYCLE_Msk; + tmp |= US_TTGR_LON_PCYCLE(data); + ((Usart *)hw)->US_TTGR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_TTGR_LON_PCYCLE_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR &= ~US_TTGR_LON_PCYCLE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_TTGR_LON_PCYCLE_bf(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR ^= US_TTGR_LON_PCYCLE(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_read_US_TTGR_LON_PCYCLE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_TTGR; + tmp = (tmp & US_TTGR_LON_PCYCLE_Msk) >> US_TTGR_LON_PCYCLE_Pos; + return tmp; +} + +static inline void hri_usart_set_US_TTGR_reg(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_get_US_TTGR_reg(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_TTGR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_TTGR_reg(const void *const hw, hri_usart_us_ttgr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_TTGR_reg(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_TTGR_reg(const void *const hw, hri_usart_us_ttgr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_TTGR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_ttgr_reg_t hri_usart_read_US_TTGR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_TTGR; +} + +static inline void hri_usart_set_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI |= US_FIDI_USART_FI_DI_RATIO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_get_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw, + hri_usart_us_fidi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_FIDI; + tmp = (tmp & US_FIDI_USART_FI_DI_RATIO(mask)) >> US_FIDI_USART_FI_DI_RATIO_Pos; + return tmp; +} + +static inline void hri_usart_write_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw, hri_usart_us_fidi_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_FIDI; + tmp &= ~US_FIDI_USART_FI_DI_RATIO_Msk; + tmp |= US_FIDI_USART_FI_DI_RATIO(data); + ((Usart *)hw)->US_FIDI = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI &= ~US_FIDI_USART_FI_DI_RATIO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI ^= US_FIDI_USART_FI_DI_RATIO(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_read_US_FIDI_USART_FI_DI_RATIO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_FIDI; + tmp = (tmp & US_FIDI_USART_FI_DI_RATIO_Msk) >> US_FIDI_USART_FI_DI_RATIO_Pos; + return tmp; +} + +static inline void hri_usart_set_US_FIDI_LON_BETA2_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI |= US_FIDI_LON_BETA2(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_get_US_FIDI_LON_BETA2_bf(const void *const hw, + hri_usart_us_fidi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_FIDI; + tmp = (tmp & US_FIDI_LON_BETA2(mask)) >> US_FIDI_LON_BETA2_Pos; + return tmp; +} + +static inline void hri_usart_write_US_FIDI_LON_BETA2_bf(const void *const hw, hri_usart_us_fidi_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_FIDI; + tmp &= ~US_FIDI_LON_BETA2_Msk; + tmp |= US_FIDI_LON_BETA2(data); + ((Usart *)hw)->US_FIDI = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_FIDI_LON_BETA2_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI &= ~US_FIDI_LON_BETA2(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_FIDI_LON_BETA2_bf(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI ^= US_FIDI_LON_BETA2(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_read_US_FIDI_LON_BETA2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_FIDI; + tmp = (tmp & US_FIDI_LON_BETA2_Msk) >> US_FIDI_LON_BETA2_Pos; + return tmp; +} + +static inline void hri_usart_set_US_FIDI_reg(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_get_US_FIDI_reg(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_FIDI; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_FIDI_reg(const void *const hw, hri_usart_us_fidi_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_FIDI_reg(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_FIDI_reg(const void *const hw, hri_usart_us_fidi_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_FIDI ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_fidi_reg_t hri_usart_read_US_FIDI_reg(const void *const hw) +{ + return ((Usart *)hw)->US_FIDI; +} + +static inline void hri_usart_set_US_IF_IRDA_FILTER_bf(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF |= US_IF_IRDA_FILTER(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_if_reg_t hri_usart_get_US_IF_IRDA_FILTER_bf(const void *const hw, hri_usart_us_if_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IF; + tmp = (tmp & US_IF_IRDA_FILTER(mask)) >> US_IF_IRDA_FILTER_Pos; + return tmp; +} + +static inline void hri_usart_write_US_IF_IRDA_FILTER_bf(const void *const hw, hri_usart_us_if_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_IF; + tmp &= ~US_IF_IRDA_FILTER_Msk; + tmp |= US_IF_IRDA_FILTER(data); + ((Usart *)hw)->US_IF = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IF_IRDA_FILTER_bf(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF &= ~US_IF_IRDA_FILTER(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IF_IRDA_FILTER_bf(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF ^= US_IF_IRDA_FILTER(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_if_reg_t hri_usart_read_US_IF_IRDA_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IF; + tmp = (tmp & US_IF_IRDA_FILTER_Msk) >> US_IF_IRDA_FILTER_Pos; + return tmp; +} + +static inline void hri_usart_set_US_IF_reg(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_if_reg_t hri_usart_get_US_IF_reg(const void *const hw, hri_usart_us_if_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IF; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_IF_reg(const void *const hw, hri_usart_us_if_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IF_reg(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IF_reg(const void *const hw, hri_usart_us_if_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IF ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_if_reg_t hri_usart_read_US_IF_reg(const void *const hw) +{ + return ((Usart *)hw)->US_IF; +} + +static inline void hri_usart_set_US_MAN_TX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_TX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MAN_TX_MPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_TX_MPOL) >> US_MAN_TX_MPOL_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MAN_TX_MPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_TX_MPOL; + tmp |= value << US_MAN_TX_MPOL_Pos; + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_TX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_TX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_TX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_TX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MAN_RX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_RX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MAN_RX_MPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RX_MPOL) >> US_MAN_RX_MPOL_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MAN_RX_MPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_RX_MPOL; + tmp |= value << US_MAN_RX_MPOL_Pos; + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_RX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_RX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_RX_MPOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_RX_MPOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MAN_ONE_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_ONE; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MAN_ONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_ONE) >> US_MAN_ONE_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MAN_ONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_ONE; + tmp |= value << US_MAN_ONE_Pos; + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_ONE_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_ONE; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_ONE_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_ONE; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MAN_DRIFT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_DRIFT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MAN_DRIFT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_DRIFT) >> US_MAN_DRIFT_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MAN_DRIFT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_DRIFT; + tmp |= value << US_MAN_DRIFT_Pos; + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_DRIFT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_DRIFT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_DRIFT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_DRIFT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MAN_RXIDLEV_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_RXIDLEV; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_MAN_RXIDLEV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RXIDLEV) >> US_MAN_RXIDLEV_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_MAN_RXIDLEV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_RXIDLEV; + tmp |= value << US_MAN_RXIDLEV_Pos; + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_RXIDLEV_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_RXIDLEV; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_RXIDLEV_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_RXIDLEV; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_MAN_TX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_TX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_get_US_MAN_TX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_TX_PL(mask)) >> US_MAN_TX_PL_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MAN_TX_PL_bf(const void *const hw, hri_usart_us_man_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_TX_PL_Msk; + tmp |= US_MAN_TX_PL(data); + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_TX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_TX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_TX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_TX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_read_US_MAN_TX_PL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_TX_PL_Msk) >> US_MAN_TX_PL_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MAN_TX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_TX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_get_US_MAN_TX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_TX_PP(mask)) >> US_MAN_TX_PP_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MAN_TX_PP_bf(const void *const hw, hri_usart_us_man_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_TX_PP_Msk; + tmp |= US_MAN_TX_PP(data); + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_TX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_TX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_TX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_TX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_read_US_MAN_TX_PP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_TX_PP_Msk) >> US_MAN_TX_PP_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MAN_RX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_RX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_get_US_MAN_RX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RX_PL(mask)) >> US_MAN_RX_PL_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MAN_RX_PL_bf(const void *const hw, hri_usart_us_man_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_RX_PL_Msk; + tmp |= US_MAN_RX_PL(data); + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_RX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_RX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_RX_PL_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_RX_PL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_read_US_MAN_RX_PL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RX_PL_Msk) >> US_MAN_RX_PL_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MAN_RX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= US_MAN_RX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_get_US_MAN_RX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RX_PP(mask)) >> US_MAN_RX_PP_Pos; + return tmp; +} + +static inline void hri_usart_write_US_MAN_RX_PP_bf(const void *const hw, hri_usart_us_man_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_MAN; + tmp &= ~US_MAN_RX_PP_Msk; + tmp |= US_MAN_RX_PP(data); + ((Usart *)hw)->US_MAN = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_RX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~US_MAN_RX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_RX_PP_bf(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= US_MAN_RX_PP(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_read_US_MAN_RX_PP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp = (tmp & US_MAN_RX_PP_Msk) >> US_MAN_RX_PP_Pos; + return tmp; +} + +static inline void hri_usart_set_US_MAN_reg(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_get_US_MAN_reg(const void *const hw, hri_usart_us_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_MAN; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_MAN_reg(const void *const hw, hri_usart_us_man_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_MAN_reg(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_MAN_reg(const void *const hw, hri_usart_us_man_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_MAN ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_man_reg_t hri_usart_read_US_MAN_reg(const void *const hw) +{ + return ((Usart *)hw)->US_MAN; +} + +static inline void hri_usart_set_US_LINMR_PARDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_PARDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_PARDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_PARDIS) >> US_LINMR_PARDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_PARDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_PARDIS; + tmp |= value << US_LINMR_PARDIS_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_PARDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_PARDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_PARDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_PARDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_CHKDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_CHKDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_CHKDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_CHKDIS) >> US_LINMR_CHKDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_CHKDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_CHKDIS; + tmp |= value << US_LINMR_CHKDIS_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_CHKDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_CHKDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_CHKDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_CHKDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_CHKTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_CHKTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_CHKTYP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_CHKTYP) >> US_LINMR_CHKTYP_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_CHKTYP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_CHKTYP; + tmp |= value << US_LINMR_CHKTYP_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_CHKTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_CHKTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_CHKTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_CHKTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_DLM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_DLM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_DLM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_DLM) >> US_LINMR_DLM_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_DLM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_DLM; + tmp |= value << US_LINMR_DLM_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_DLM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_DLM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_DLM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_DLM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_FSDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_FSDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_FSDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_FSDIS) >> US_LINMR_FSDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_FSDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_FSDIS; + tmp |= value << US_LINMR_FSDIS_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_FSDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_FSDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_FSDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_FSDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_WKUPTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_WKUPTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_WKUPTYP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_WKUPTYP) >> US_LINMR_WKUPTYP_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_WKUPTYP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_WKUPTYP; + tmp |= value << US_LINMR_WKUPTYP_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_WKUPTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_WKUPTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_WKUPTYP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_WKUPTYP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_PDCM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_PDCM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_PDCM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_PDCM) >> US_LINMR_PDCM_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_PDCM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_PDCM; + tmp |= value << US_LINMR_PDCM_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_PDCM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_PDCM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_PDCM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_PDCM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_SYNCDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_SYNCDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LINMR_SYNCDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_SYNCDIS) >> US_LINMR_SYNCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LINMR_SYNCDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_SYNCDIS; + tmp |= value << US_LINMR_SYNCDIS_Pos; + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_SYNCDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_SYNCDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_SYNCDIS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_SYNCDIS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LINMR_NACT_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_NACT(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_get_US_LINMR_NACT_bf(const void *const hw, + hri_usart_us_linmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_NACT(mask)) >> US_LINMR_NACT_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LINMR_NACT_bf(const void *const hw, hri_usart_us_linmr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_NACT_Msk; + tmp |= US_LINMR_NACT(data); + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_NACT_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_NACT(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_NACT_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_NACT(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_read_US_LINMR_NACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_NACT_Msk) >> US_LINMR_NACT_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LINMR_DLC_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= US_LINMR_DLC(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_get_US_LINMR_DLC_bf(const void *const hw, + hri_usart_us_linmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_DLC(mask)) >> US_LINMR_DLC_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LINMR_DLC_bf(const void *const hw, hri_usart_us_linmr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINMR; + tmp &= ~US_LINMR_DLC_Msk; + tmp |= US_LINMR_DLC(data); + ((Usart *)hw)->US_LINMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_DLC_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~US_LINMR_DLC(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_DLC_bf(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= US_LINMR_DLC(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_read_US_LINMR_DLC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp = (tmp & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LINMR_reg(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_get_US_LINMR_reg(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINMR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LINMR_reg(const void *const hw, hri_usart_us_linmr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINMR_reg(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINMR_reg(const void *const hw, hri_usart_us_linmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINMR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linmr_reg_t hri_usart_read_US_LINMR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LINMR; +} + +static inline void hri_usart_set_US_LINIR_IDCHR_bf(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR |= US_LINIR_IDCHR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linir_reg_t hri_usart_get_US_LINIR_IDCHR_bf(const void *const hw, + hri_usart_us_linir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINIR; + tmp = (tmp & US_LINIR_IDCHR(mask)) >> US_LINIR_IDCHR_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LINIR_IDCHR_bf(const void *const hw, hri_usart_us_linir_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LINIR; + tmp &= ~US_LINIR_IDCHR_Msk; + tmp |= US_LINIR_IDCHR(data); + ((Usart *)hw)->US_LINIR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINIR_IDCHR_bf(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR &= ~US_LINIR_IDCHR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINIR_IDCHR_bf(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR ^= US_LINIR_IDCHR(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linir_reg_t hri_usart_read_US_LINIR_IDCHR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINIR; + tmp = (tmp & US_LINIR_IDCHR_Msk) >> US_LINIR_IDCHR_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LINIR_reg(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linir_reg_t hri_usart_get_US_LINIR_reg(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LINIR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LINIR_reg(const void *const hw, hri_usart_us_linir_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LINIR_reg(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LINIR_reg(const void *const hw, hri_usart_us_linir_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LINIR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_linir_reg_t hri_usart_read_US_LINIR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LINIR; +} + +static inline void hri_usart_set_US_LONMR_COMMT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_COMMT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_COMMT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_COMMT) >> US_LONMR_COMMT_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_COMMT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_COMMT; + tmp |= value << US_LONMR_COMMT_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_COMMT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_COMMT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_COMMT_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_COMMT; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_COLDET_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_COLDET; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_COLDET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_COLDET) >> US_LONMR_COLDET_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_COLDET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_COLDET; + tmp |= value << US_LONMR_COLDET_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_COLDET_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_COLDET; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_COLDET_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_COLDET; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_TCOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_TCOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_TCOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_TCOL) >> US_LONMR_TCOL_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_TCOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_TCOL; + tmp |= value << US_LONMR_TCOL_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_TCOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_TCOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_TCOL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_TCOL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_CDTAIL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_CDTAIL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_CDTAIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_CDTAIL) >> US_LONMR_CDTAIL_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_CDTAIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_CDTAIL; + tmp |= value << US_LONMR_CDTAIL_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_CDTAIL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_CDTAIL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_CDTAIL_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_CDTAIL; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_DMAM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_DMAM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_DMAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_DMAM) >> US_LONMR_DMAM_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_DMAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_DMAM; + tmp |= value << US_LONMR_DMAM_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_DMAM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_DMAM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_DMAM_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_DMAM; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_LCDS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_LCDS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONMR_LCDS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_LCDS) >> US_LONMR_LCDS_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONMR_LCDS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_LCDS; + tmp |= value << US_LONMR_LCDS_Pos; + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_LCDS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_LCDS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_LCDS_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_LCDS; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONMR_EOFS_bf(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= US_LONMR_EOFS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonmr_reg_t hri_usart_get_US_LONMR_EOFS_bf(const void *const hw, + hri_usart_us_lonmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_EOFS(mask)) >> US_LONMR_EOFS_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONMR_EOFS_bf(const void *const hw, hri_usart_us_lonmr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONMR; + tmp &= ~US_LONMR_EOFS_Msk; + tmp |= US_LONMR_EOFS(data); + ((Usart *)hw)->US_LONMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_EOFS_bf(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~US_LONMR_EOFS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_EOFS_bf(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= US_LONMR_EOFS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonmr_reg_t hri_usart_read_US_LONMR_EOFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp = (tmp & US_LONMR_EOFS_Msk) >> US_LONMR_EOFS_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONMR_reg(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonmr_reg_t hri_usart_get_US_LONMR_reg(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONMR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONMR_reg(const void *const hw, hri_usart_us_lonmr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONMR_reg(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONMR_reg(const void *const hw, hri_usart_us_lonmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONMR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonmr_reg_t hri_usart_read_US_LONMR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONMR; +} + +static inline void hri_usart_set_US_LONPR_LONPL_bf(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR |= US_LONPR_LONPL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonpr_reg_t hri_usart_get_US_LONPR_LONPL_bf(const void *const hw, + hri_usart_us_lonpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPR; + tmp = (tmp & US_LONPR_LONPL(mask)) >> US_LONPR_LONPL_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONPR_LONPL_bf(const void *const hw, hri_usart_us_lonpr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONPR; + tmp &= ~US_LONPR_LONPL_Msk; + tmp |= US_LONPR_LONPL(data); + ((Usart *)hw)->US_LONPR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONPR_LONPL_bf(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR &= ~US_LONPR_LONPL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONPR_LONPL_bf(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR ^= US_LONPR_LONPL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonpr_reg_t hri_usart_read_US_LONPR_LONPL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPR; + tmp = (tmp & US_LONPR_LONPL_Msk) >> US_LONPR_LONPL_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONPR_reg(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonpr_reg_t hri_usart_get_US_LONPR_reg(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONPR_reg(const void *const hw, hri_usart_us_lonpr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONPR_reg(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONPR_reg(const void *const hw, hri_usart_us_lonpr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonpr_reg_t hri_usart_read_US_LONPR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONPR; +} + +static inline void hri_usart_set_US_LONDL_LONDL_bf(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL |= US_LONDL_LONDL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_londl_reg_t hri_usart_get_US_LONDL_LONDL_bf(const void *const hw, + hri_usart_us_londl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONDL; + tmp = (tmp & US_LONDL_LONDL(mask)) >> US_LONDL_LONDL_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONDL_LONDL_bf(const void *const hw, hri_usart_us_londl_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONDL; + tmp &= ~US_LONDL_LONDL_Msk; + tmp |= US_LONDL_LONDL(data); + ((Usart *)hw)->US_LONDL = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONDL_LONDL_bf(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL &= ~US_LONDL_LONDL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONDL_LONDL_bf(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL ^= US_LONDL_LONDL(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_londl_reg_t hri_usart_read_US_LONDL_LONDL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONDL; + tmp = (tmp & US_LONDL_LONDL_Msk) >> US_LONDL_LONDL_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONDL_reg(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_londl_reg_t hri_usart_get_US_LONDL_reg(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONDL; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONDL_reg(const void *const hw, hri_usart_us_londl_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONDL_reg(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONDL_reg(const void *const hw, hri_usart_us_londl_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONDL ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_londl_reg_t hri_usart_read_US_LONDL_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONDL; +} + +static inline void hri_usart_set_US_LONL2HDR_ALTP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR |= US_LONL2HDR_ALTP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONL2HDR_ALTP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp = (tmp & US_LONL2HDR_ALTP) >> US_LONL2HDR_ALTP_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONL2HDR_ALTP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp &= ~US_LONL2HDR_ALTP; + tmp |= value << US_LONL2HDR_ALTP_Pos; + ((Usart *)hw)->US_LONL2HDR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONL2HDR_ALTP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR &= ~US_LONL2HDR_ALTP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONL2HDR_ALTP_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR ^= US_LONL2HDR_ALTP; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONL2HDR_PB_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR |= US_LONL2HDR_PB; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_LONL2HDR_PB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp = (tmp & US_LONL2HDR_PB) >> US_LONL2HDR_PB_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_LONL2HDR_PB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp &= ~US_LONL2HDR_PB; + tmp |= value << US_LONL2HDR_PB_Pos; + ((Usart *)hw)->US_LONL2HDR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONL2HDR_PB_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR &= ~US_LONL2HDR_PB; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONL2HDR_PB_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR ^= US_LONL2HDR_PB; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_LONL2HDR_BLI_bf(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR |= US_LONL2HDR_BLI(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonl2hdr_reg_t hri_usart_get_US_LONL2HDR_BLI_bf(const void *const hw, + hri_usart_us_lonl2hdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp = (tmp & US_LONL2HDR_BLI(mask)) >> US_LONL2HDR_BLI_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONL2HDR_BLI_bf(const void *const hw, hri_usart_us_lonl2hdr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp &= ~US_LONL2HDR_BLI_Msk; + tmp |= US_LONL2HDR_BLI(data); + ((Usart *)hw)->US_LONL2HDR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONL2HDR_BLI_bf(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR &= ~US_LONL2HDR_BLI(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONL2HDR_BLI_bf(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR ^= US_LONL2HDR_BLI(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonl2hdr_reg_t hri_usart_read_US_LONL2HDR_BLI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp = (tmp & US_LONL2HDR_BLI_Msk) >> US_LONL2HDR_BLI_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONL2HDR_reg(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonl2hdr_reg_t hri_usart_get_US_LONL2HDR_reg(const void *const hw, + hri_usart_us_lonl2hdr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONL2HDR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONL2HDR_reg(const void *const hw, hri_usart_us_lonl2hdr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONL2HDR_reg(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONL2HDR_reg(const void *const hw, hri_usart_us_lonl2hdr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONL2HDR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonl2hdr_reg_t hri_usart_read_US_LONL2HDR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONL2HDR; +} + +static inline void hri_usart_set_US_LONB1TX_BETA1TX_bf(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX |= US_LONB1TX_BETA1TX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1tx_reg_t hri_usart_get_US_LONB1TX_BETA1TX_bf(const void *const hw, + hri_usart_us_lonb1tx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1TX; + tmp = (tmp & US_LONB1TX_BETA1TX(mask)) >> US_LONB1TX_BETA1TX_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONB1TX_BETA1TX_bf(const void *const hw, hri_usart_us_lonb1tx_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONB1TX; + tmp &= ~US_LONB1TX_BETA1TX_Msk; + tmp |= US_LONB1TX_BETA1TX(data); + ((Usart *)hw)->US_LONB1TX = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONB1TX_BETA1TX_bf(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX &= ~US_LONB1TX_BETA1TX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONB1TX_BETA1TX_bf(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX ^= US_LONB1TX_BETA1TX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1tx_reg_t hri_usart_read_US_LONB1TX_BETA1TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1TX; + tmp = (tmp & US_LONB1TX_BETA1TX_Msk) >> US_LONB1TX_BETA1TX_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONB1TX_reg(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1tx_reg_t hri_usart_get_US_LONB1TX_reg(const void *const hw, + hri_usart_us_lonb1tx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1TX; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONB1TX_reg(const void *const hw, hri_usart_us_lonb1tx_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONB1TX_reg(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONB1TX_reg(const void *const hw, hri_usart_us_lonb1tx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1TX ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1tx_reg_t hri_usart_read_US_LONB1TX_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONB1TX; +} + +static inline void hri_usart_set_US_LONB1RX_BETA1RX_bf(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX |= US_LONB1RX_BETA1RX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1rx_reg_t hri_usart_get_US_LONB1RX_BETA1RX_bf(const void *const hw, + hri_usart_us_lonb1rx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1RX; + tmp = (tmp & US_LONB1RX_BETA1RX(mask)) >> US_LONB1RX_BETA1RX_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONB1RX_BETA1RX_bf(const void *const hw, hri_usart_us_lonb1rx_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONB1RX; + tmp &= ~US_LONB1RX_BETA1RX_Msk; + tmp |= US_LONB1RX_BETA1RX(data); + ((Usart *)hw)->US_LONB1RX = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONB1RX_BETA1RX_bf(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX &= ~US_LONB1RX_BETA1RX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONB1RX_BETA1RX_bf(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX ^= US_LONB1RX_BETA1RX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1rx_reg_t hri_usart_read_US_LONB1RX_BETA1RX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1RX; + tmp = (tmp & US_LONB1RX_BETA1RX_Msk) >> US_LONB1RX_BETA1RX_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONB1RX_reg(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1rx_reg_t hri_usart_get_US_LONB1RX_reg(const void *const hw, + hri_usart_us_lonb1rx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONB1RX; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONB1RX_reg(const void *const hw, hri_usart_us_lonb1rx_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONB1RX_reg(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONB1RX_reg(const void *const hw, hri_usart_us_lonb1rx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONB1RX ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonb1rx_reg_t hri_usart_read_US_LONB1RX_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONB1RX; +} + +static inline void hri_usart_set_US_LONPRIO_PSNB_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO |= US_LONPRIO_PSNB(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_get_US_LONPRIO_PSNB_bf(const void *const hw, + hri_usart_us_lonprio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPRIO; + tmp = (tmp & US_LONPRIO_PSNB(mask)) >> US_LONPRIO_PSNB_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONPRIO_PSNB_bf(const void *const hw, hri_usart_us_lonprio_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONPRIO; + tmp &= ~US_LONPRIO_PSNB_Msk; + tmp |= US_LONPRIO_PSNB(data); + ((Usart *)hw)->US_LONPRIO = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONPRIO_PSNB_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO &= ~US_LONPRIO_PSNB(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONPRIO_PSNB_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO ^= US_LONPRIO_PSNB(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_read_US_LONPRIO_PSNB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPRIO; + tmp = (tmp & US_LONPRIO_PSNB_Msk) >> US_LONPRIO_PSNB_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONPRIO_NPS_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO |= US_LONPRIO_NPS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_get_US_LONPRIO_NPS_bf(const void *const hw, + hri_usart_us_lonprio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPRIO; + tmp = (tmp & US_LONPRIO_NPS(mask)) >> US_LONPRIO_NPS_Pos; + return tmp; +} + +static inline void hri_usart_write_US_LONPRIO_NPS_bf(const void *const hw, hri_usart_us_lonprio_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_LONPRIO; + tmp &= ~US_LONPRIO_NPS_Msk; + tmp |= US_LONPRIO_NPS(data); + ((Usart *)hw)->US_LONPRIO = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONPRIO_NPS_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO &= ~US_LONPRIO_NPS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONPRIO_NPS_bf(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO ^= US_LONPRIO_NPS(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_read_US_LONPRIO_NPS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPRIO; + tmp = (tmp & US_LONPRIO_NPS_Msk) >> US_LONPRIO_NPS_Pos; + return tmp; +} + +static inline void hri_usart_set_US_LONPRIO_reg(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_get_US_LONPRIO_reg(const void *const hw, + hri_usart_us_lonprio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_LONPRIO; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_LONPRIO_reg(const void *const hw, hri_usart_us_lonprio_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_LONPRIO_reg(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_LONPRIO_reg(const void *const hw, hri_usart_us_lonprio_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_LONPRIO ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_lonprio_reg_t hri_usart_read_US_LONPRIO_reg(const void *const hw) +{ + return ((Usart *)hw)->US_LONPRIO; +} + +static inline void hri_usart_set_US_IDTTX_IDTTX_bf(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX |= US_IDTTX_IDTTX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idttx_reg_t hri_usart_get_US_IDTTX_IDTTX_bf(const void *const hw, + hri_usart_us_idttx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTTX; + tmp = (tmp & US_IDTTX_IDTTX(mask)) >> US_IDTTX_IDTTX_Pos; + return tmp; +} + +static inline void hri_usart_write_US_IDTTX_IDTTX_bf(const void *const hw, hri_usart_us_idttx_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_IDTTX; + tmp &= ~US_IDTTX_IDTTX_Msk; + tmp |= US_IDTTX_IDTTX(data); + ((Usart *)hw)->US_IDTTX = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IDTTX_IDTTX_bf(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX &= ~US_IDTTX_IDTTX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IDTTX_IDTTX_bf(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX ^= US_IDTTX_IDTTX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idttx_reg_t hri_usart_read_US_IDTTX_IDTTX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTTX; + tmp = (tmp & US_IDTTX_IDTTX_Msk) >> US_IDTTX_IDTTX_Pos; + return tmp; +} + +static inline void hri_usart_set_US_IDTTX_reg(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idttx_reg_t hri_usart_get_US_IDTTX_reg(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTTX; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_IDTTX_reg(const void *const hw, hri_usart_us_idttx_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IDTTX_reg(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IDTTX_reg(const void *const hw, hri_usart_us_idttx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTTX ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idttx_reg_t hri_usart_read_US_IDTTX_reg(const void *const hw) +{ + return ((Usart *)hw)->US_IDTTX; +} + +static inline void hri_usart_set_US_IDTRX_IDTRX_bf(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX |= US_IDTRX_IDTRX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idtrx_reg_t hri_usart_get_US_IDTRX_IDTRX_bf(const void *const hw, + hri_usart_us_idtrx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTRX; + tmp = (tmp & US_IDTRX_IDTRX(mask)) >> US_IDTRX_IDTRX_Pos; + return tmp; +} + +static inline void hri_usart_write_US_IDTRX_IDTRX_bf(const void *const hw, hri_usart_us_idtrx_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_IDTRX; + tmp &= ~US_IDTRX_IDTRX_Msk; + tmp |= US_IDTRX_IDTRX(data); + ((Usart *)hw)->US_IDTRX = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IDTRX_IDTRX_bf(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX &= ~US_IDTRX_IDTRX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IDTRX_IDTRX_bf(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX ^= US_IDTRX_IDTRX(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idtrx_reg_t hri_usart_read_US_IDTRX_IDTRX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTRX; + tmp = (tmp & US_IDTRX_IDTRX_Msk) >> US_IDTRX_IDTRX_Pos; + return tmp; +} + +static inline void hri_usart_set_US_IDTRX_reg(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idtrx_reg_t hri_usart_get_US_IDTRX_reg(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_IDTRX; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_IDTRX_reg(const void *const hw, hri_usart_us_idtrx_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_IDTRX_reg(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_IDTRX_reg(const void *const hw, hri_usart_us_idtrx_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_IDTRX ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_idtrx_reg_t hri_usart_read_US_IDTRX_reg(const void *const hw) +{ + return ((Usart *)hw)->US_IDTRX; +} + +static inline void hri_usart_set_US_ICDIFF_ICDIFF_bf(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF |= US_ICDIFF_ICDIFF(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_icdiff_reg_t hri_usart_get_US_ICDIFF_ICDIFF_bf(const void *const hw, + hri_usart_us_icdiff_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_ICDIFF; + tmp = (tmp & US_ICDIFF_ICDIFF(mask)) >> US_ICDIFF_ICDIFF_Pos; + return tmp; +} + +static inline void hri_usart_write_US_ICDIFF_ICDIFF_bf(const void *const hw, hri_usart_us_icdiff_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_ICDIFF; + tmp &= ~US_ICDIFF_ICDIFF_Msk; + tmp |= US_ICDIFF_ICDIFF(data); + ((Usart *)hw)->US_ICDIFF = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_ICDIFF_ICDIFF_bf(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF &= ~US_ICDIFF_ICDIFF(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_ICDIFF_ICDIFF_bf(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF ^= US_ICDIFF_ICDIFF(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_icdiff_reg_t hri_usart_read_US_ICDIFF_ICDIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_ICDIFF; + tmp = (tmp & US_ICDIFF_ICDIFF_Msk) >> US_ICDIFF_ICDIFF_Pos; + return tmp; +} + +static inline void hri_usart_set_US_ICDIFF_reg(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_icdiff_reg_t hri_usart_get_US_ICDIFF_reg(const void *const hw, + hri_usart_us_icdiff_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_ICDIFF; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_ICDIFF_reg(const void *const hw, hri_usart_us_icdiff_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_ICDIFF_reg(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_ICDIFF_reg(const void *const hw, hri_usart_us_icdiff_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_ICDIFF ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_icdiff_reg_t hri_usart_read_US_ICDIFF_reg(const void *const hw) +{ + return ((Usart *)hw)->US_ICDIFF; +} + +static inline void hri_usart_set_US_WPMR_WPEN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR |= US_WPMR_WPEN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usart_get_US_WPMR_WPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_WPMR; + tmp = (tmp & US_WPMR_WPEN) >> US_WPMR_WPEN_Pos; + return (bool)tmp; +} + +static inline void hri_usart_write_US_WPMR_WPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_WPMR; + tmp &= ~US_WPMR_WPEN; + tmp |= value << US_WPMR_WPEN_Pos; + ((Usart *)hw)->US_WPMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_WPMR_WPEN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR &= ~US_WPMR_WPEN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_WPMR_WPEN_bit(const void *const hw) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR ^= US_WPMR_WPEN; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_set_US_WPMR_WPKEY_bf(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR |= US_WPMR_WPKEY(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_wpmr_reg_t hri_usart_get_US_WPMR_WPKEY_bf(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_WPMR; + tmp = (tmp & US_WPMR_WPKEY(mask)) >> US_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_usart_write_US_WPMR_WPKEY_bf(const void *const hw, hri_usart_us_wpmr_reg_t data) +{ + uint32_t tmp; + USART_CRITICAL_SECTION_ENTER(); + tmp = ((Usart *)hw)->US_WPMR; + tmp &= ~US_WPMR_WPKEY_Msk; + tmp |= US_WPMR_WPKEY(data); + ((Usart *)hw)->US_WPMR = tmp; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_WPMR_WPKEY_bf(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR &= ~US_WPMR_WPKEY(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_WPMR_WPKEY_bf(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR ^= US_WPMR_WPKEY(mask); + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_wpmr_reg_t hri_usart_read_US_WPMR_WPKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_WPMR; + tmp = (tmp & US_WPMR_WPKEY_Msk) >> US_WPMR_WPKEY_Pos; + return tmp; +} + +static inline void hri_usart_set_US_WPMR_reg(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR |= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_wpmr_reg_t hri_usart_get_US_WPMR_reg(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usart *)hw)->US_WPMR; + tmp &= mask; + return tmp; +} + +static inline void hri_usart_write_US_WPMR_reg(const void *const hw, hri_usart_us_wpmr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_clear_US_WPMR_reg(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR &= ~mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_toggle_US_WPMR_reg(const void *const hw, hri_usart_us_wpmr_reg_t mask) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_WPMR ^= mask; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usart_us_wpmr_reg_t hri_usart_read_US_WPMR_reg(const void *const hw) +{ + return ((Usart *)hw)->US_WPMR; +} + +static inline void hri_usart_write_US_CR_reg(const void *const hw, hri_usart_us_cr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_CR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usart_write_US_THR_reg(const void *const hw, hri_usart_us_thr_reg_t data) +{ + USART_CRITICAL_SECTION_ENTER(); + ((Usart *)hw)->US_THR = data; + USART_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usart_set_US_IMR_RXBRK_bit(a) hri_usart_set_US_IMR_USART_RXBRK_bit(a) +#define hri_usart_get_US_IMR_RXBRK_bit(a) hri_usart_get_US_IMR_USART_RXBRK_bit(a) +#define hri_usart_write_US_IMR_RXBRK_bit(a, b) hri_usart_write_US_IMR_USART_RXBRK_bit(a, b) +#define hri_usart_clear_US_IMR_RXBRK_bit(a) hri_usart_clear_US_IMR_USART_RXBRK_bit(a) +#define hri_usart_set_US_IMR_FRAME_bit(a) hri_usart_set_US_IMR_USART_LIN_FRAME_bit(a) +#define hri_usart_get_US_IMR_FRAME_bit(a) hri_usart_get_US_IMR_USART_LIN_FRAME_bit(a) +#define hri_usart_write_US_IMR_FRAME_bit(a, b) hri_usart_write_US_IMR_USART_LIN_FRAME_bit(a, b) +#define hri_usart_clear_US_IMR_FRAME_bit(a) hri_usart_clear_US_IMR_USART_LIN_FRAME_bit(a) +#define hri_usart_set_US_IMR_PARE_bit(a) hri_usart_set_US_IMR_USART_LIN_PARE_bit(a) +#define hri_usart_get_US_IMR_PARE_bit(a) hri_usart_get_US_IMR_USART_LIN_PARE_bit(a) +#define hri_usart_write_US_IMR_PARE_bit(a, b) hri_usart_write_US_IMR_USART_LIN_PARE_bit(a, b) +#define hri_usart_clear_US_IMR_PARE_bit(a) hri_usart_clear_US_IMR_USART_LIN_PARE_bit(a) +#define hri_usart_set_US_IMR_TIMEOUT_bit(a) hri_usart_set_US_IMR_USART_LIN_TIMEOUT_bit(a) +#define hri_usart_get_US_IMR_TIMEOUT_bit(a) hri_usart_get_US_IMR_USART_LIN_TIMEOUT_bit(a) +#define hri_usart_write_US_IMR_TIMEOUT_bit(a, b) hri_usart_write_US_IMR_USART_LIN_TIMEOUT_bit(a, b) +#define hri_usart_clear_US_IMR_TIMEOUT_bit(a) hri_usart_clear_US_IMR_USART_LIN_TIMEOUT_bit(a) +#define hri_usart_set_US_IMR_ITER_bit(a) hri_usart_set_US_IMR_USART_ITER_bit(a) +#define hri_usart_get_US_IMR_ITER_bit(a) hri_usart_get_US_IMR_USART_ITER_bit(a) +#define hri_usart_write_US_IMR_ITER_bit(a, b) hri_usart_write_US_IMR_USART_ITER_bit(a, b) +#define hri_usart_clear_US_IMR_ITER_bit(a) hri_usart_clear_US_IMR_USART_ITER_bit(a) +#define hri_usart_set_US_IMR_NACK_bit(a) hri_usart_set_US_IMR_USART_NACK_bit(a) +#define hri_usart_get_US_IMR_NACK_bit(a) hri_usart_get_US_IMR_USART_NACK_bit(a) +#define hri_usart_write_US_IMR_NACK_bit(a, b) hri_usart_write_US_IMR_USART_NACK_bit(a, b) +#define hri_usart_clear_US_IMR_NACK_bit(a) hri_usart_clear_US_IMR_USART_NACK_bit(a) +#define hri_usart_set_US_IMR_CTSIC_bit(a) hri_usart_set_US_IMR_USART_CTSIC_bit(a) +#define hri_usart_get_US_IMR_CTSIC_bit(a) hri_usart_get_US_IMR_USART_CTSIC_bit(a) +#define hri_usart_write_US_IMR_CTSIC_bit(a, b) hri_usart_write_US_IMR_USART_CTSIC_bit(a, b) +#define hri_usart_clear_US_IMR_CTSIC_bit(a) hri_usart_clear_US_IMR_USART_CTSIC_bit(a) +#define hri_usart_set_US_IMR_MANE_bit(a) hri_usart_set_US_IMR_USART_MANE_bit(a) +#define hri_usart_get_US_IMR_MANE_bit(a) hri_usart_get_US_IMR_USART_MANE_bit(a) +#define hri_usart_write_US_IMR_MANE_bit(a, b) hri_usart_write_US_IMR_USART_MANE_bit(a, b) +#define hri_usart_clear_US_IMR_MANE_bit(a) hri_usart_clear_US_IMR_USART_MANE_bit(a) +#define hri_usart_get_US_CSR_RXBRK_bit(a) hri_usart_get_US_CSR_USART_RXBRK_bit(a) +#define hri_usart_get_US_CSR_FRAME_bit(a) hri_usart_get_US_CSR_USART_LIN_FRAME_bit(a) +#define hri_usart_get_US_CSR_PARE_bit(a) hri_usart_get_US_CSR_USART_LIN_PARE_bit(a) +#define hri_usart_get_US_CSR_TIMEOUT_bit(a) hri_usart_get_US_CSR_USART_LIN_TIMEOUT_bit(a) +#define hri_usart_get_US_CSR_ITER_bit(a) hri_usart_get_US_CSR_USART_ITER_bit(a) +#define hri_usart_get_US_CSR_NACK_bit(a) hri_usart_get_US_CSR_USART_NACK_bit(a) +#define hri_usart_get_US_CSR_CTSIC_bit(a) hri_usart_get_US_CSR_USART_CTSIC_bit(a) +#define hri_usart_get_US_CSR_RI_bit(a) hri_usart_get_US_CSR_USART_RI_bit(a) +#define hri_usart_get_US_CSR_DSR_bit(a) hri_usart_get_US_CSR_USART_DSR_bit(a) +#define hri_usart_get_US_CSR_DCD_bit(a) hri_usart_get_US_CSR_USART_DCD_bit(a) +#define hri_usart_get_US_CSR_CTS_bit(a) hri_usart_get_US_CSR_USART_CTS_bit(a) +#define hri_usart_get_US_CSR_MANERR_bit(a) hri_usart_get_US_CSR_USART_MANERR_bit(a) +#define hri_usart_set_US_MR_SYNC_bit(a) hri_usart_set_US_MR_USART_SYNC_bit(a) +#define hri_usart_get_US_MR_SYNC_bit(a) hri_usart_get_US_MR_USART_SYNC_bit(a) +#define hri_usart_write_US_MR_SYNC_bit(a, b) hri_usart_write_US_MR_USART_SYNC_bit(a, b) +#define hri_usart_clear_US_MR_SYNC_bit(a) hri_usart_clear_US_MR_USART_SYNC_bit(a) +#define hri_usart_toggle_US_MR_SYNC_bit(a) hri_usart_toggle_US_MR_USART_SYNC_bit(a) +#define hri_usart_set_US_MR_MSBF_bit(a) hri_usart_set_US_MR_USART_MSBF_bit(a) +#define hri_usart_get_US_MR_MSBF_bit(a) hri_usart_get_US_MR_USART_MSBF_bit(a) +#define hri_usart_write_US_MR_MSBF_bit(a, b) hri_usart_write_US_MR_USART_MSBF_bit(a, b) +#define hri_usart_clear_US_MR_MSBF_bit(a) hri_usart_clear_US_MR_USART_MSBF_bit(a) +#define hri_usart_toggle_US_MR_MSBF_bit(a) hri_usart_toggle_US_MR_USART_MSBF_bit(a) +#define hri_usart_set_US_MR_MODE9_bit(a) hri_usart_set_US_MR_USART_MODE9_bit(a) +#define hri_usart_get_US_MR_MODE9_bit(a) hri_usart_get_US_MR_USART_MODE9_bit(a) +#define hri_usart_write_US_MR_MODE9_bit(a, b) hri_usart_write_US_MR_USART_MODE9_bit(a, b) +#define hri_usart_clear_US_MR_MODE9_bit(a) hri_usart_clear_US_MR_USART_MODE9_bit(a) +#define hri_usart_toggle_US_MR_MODE9_bit(a) hri_usart_toggle_US_MR_USART_MODE9_bit(a) +#define hri_usart_set_US_MR_OVER_bit(a) hri_usart_set_US_MR_USART_OVER_bit(a) +#define hri_usart_get_US_MR_OVER_bit(a) hri_usart_get_US_MR_USART_OVER_bit(a) +#define hri_usart_write_US_MR_OVER_bit(a, b) hri_usart_write_US_MR_USART_OVER_bit(a, b) +#define hri_usart_clear_US_MR_OVER_bit(a) hri_usart_clear_US_MR_USART_OVER_bit(a) +#define hri_usart_toggle_US_MR_OVER_bit(a) hri_usart_toggle_US_MR_USART_OVER_bit(a) +#define hri_usart_set_US_MR_INACK_bit(a) hri_usart_set_US_MR_USART_INACK_bit(a) +#define hri_usart_get_US_MR_INACK_bit(a) hri_usart_get_US_MR_USART_INACK_bit(a) +#define hri_usart_write_US_MR_INACK_bit(a, b) hri_usart_write_US_MR_USART_INACK_bit(a, b) +#define hri_usart_clear_US_MR_INACK_bit(a) hri_usart_clear_US_MR_USART_INACK_bit(a) +#define hri_usart_toggle_US_MR_INACK_bit(a) hri_usart_toggle_US_MR_USART_INACK_bit(a) +#define hri_usart_set_US_MR_DSNACK_bit(a) hri_usart_set_US_MR_USART_DSNACK_bit(a) +#define hri_usart_get_US_MR_DSNACK_bit(a) hri_usart_get_US_MR_USART_DSNACK_bit(a) +#define hri_usart_write_US_MR_DSNACK_bit(a, b) hri_usart_write_US_MR_USART_DSNACK_bit(a, b) +#define hri_usart_clear_US_MR_DSNACK_bit(a) hri_usart_clear_US_MR_USART_DSNACK_bit(a) +#define hri_usart_toggle_US_MR_DSNACK_bit(a) hri_usart_toggle_US_MR_USART_DSNACK_bit(a) +#define hri_usart_set_US_MR_INVDATA_bit(a) hri_usart_set_US_MR_USART_INVDATA_bit(a) +#define hri_usart_get_US_MR_INVDATA_bit(a) hri_usart_get_US_MR_USART_INVDATA_bit(a) +#define hri_usart_write_US_MR_INVDATA_bit(a, b) hri_usart_write_US_MR_USART_INVDATA_bit(a, b) +#define hri_usart_clear_US_MR_INVDATA_bit(a) hri_usart_clear_US_MR_USART_INVDATA_bit(a) +#define hri_usart_toggle_US_MR_INVDATA_bit(a) hri_usart_toggle_US_MR_USART_INVDATA_bit(a) +#define hri_usart_set_US_MR_FILTER_bit(a) hri_usart_set_US_MR_USART_FILTER_bit(a) +#define hri_usart_get_US_MR_FILTER_bit(a) hri_usart_get_US_MR_USART_FILTER_bit(a) +#define hri_usart_write_US_MR_FILTER_bit(a, b) hri_usart_write_US_MR_USART_FILTER_bit(a, b) +#define hri_usart_clear_US_MR_FILTER_bit(a) hri_usart_clear_US_MR_USART_FILTER_bit(a) +#define hri_usart_toggle_US_MR_FILTER_bit(a) hri_usart_toggle_US_MR_USART_FILTER_bit(a) +#define hri_usart_set_US_MR_MAN_bit(a) hri_usart_set_US_MR_USART_MAN_bit(a) +#define hri_usart_get_US_MR_MAN_bit(a) hri_usart_get_US_MR_USART_MAN_bit(a) +#define hri_usart_write_US_MR_MAN_bit(a, b) hri_usart_write_US_MR_USART_MAN_bit(a, b) +#define hri_usart_clear_US_MR_MAN_bit(a) hri_usart_clear_US_MR_USART_MAN_bit(a) +#define hri_usart_toggle_US_MR_MAN_bit(a) hri_usart_toggle_US_MR_USART_MAN_bit(a) +#define hri_usart_set_US_MR_MODSYNC_bit(a) hri_usart_set_US_MR_USART_MODSYNC_bit(a) +#define hri_usart_get_US_MR_MODSYNC_bit(a) hri_usart_get_US_MR_USART_MODSYNC_bit(a) +#define hri_usart_write_US_MR_MODSYNC_bit(a, b) hri_usart_write_US_MR_USART_MODSYNC_bit(a, b) +#define hri_usart_clear_US_MR_MODSYNC_bit(a) hri_usart_clear_US_MR_USART_MODSYNC_bit(a) +#define hri_usart_toggle_US_MR_MODSYNC_bit(a) hri_usart_toggle_US_MR_USART_MODSYNC_bit(a) +#define hri_usart_set_US_MR_ONEBIT_bit(a) hri_usart_set_US_MR_USART_ONEBIT_bit(a) +#define hri_usart_get_US_MR_ONEBIT_bit(a) hri_usart_get_US_MR_USART_ONEBIT_bit(a) +#define hri_usart_write_US_MR_ONEBIT_bit(a, b) hri_usart_write_US_MR_USART_ONEBIT_bit(a, b) +#define hri_usart_clear_US_MR_ONEBIT_bit(a) hri_usart_clear_US_MR_USART_ONEBIT_bit(a) +#define hri_usart_toggle_US_MR_ONEBIT_bit(a) hri_usart_toggle_US_MR_USART_ONEBIT_bit(a) +#define hri_usart_set_US_MR_PAR_bf(a, b) hri_usart_set_US_MR_USART_PAR_bf(a, b) +#define hri_usart_get_US_MR_PAR_bf(a, b) hri_usart_get_US_MR_USART_PAR_bf(a, b) +#define hri_usart_write_US_MR_PAR_bf(a, b) hri_usart_write_US_MR_USART_PAR_bf(a, b) +#define hri_usart_clear_US_MR_PAR_bf(a, b) hri_usart_clear_US_MR_USART_PAR_bf(a, b) +#define hri_usart_toggle_US_MR_PAR_bf(a, b) hri_usart_toggle_US_MR_USART_PAR_bf(a, b) +#define hri_usart_read_US_MR_PAR_bf(a) hri_usart_read_US_MR_USART_PAR_bf(a) +#define hri_usart_set_US_MR_NBSTOP_bf(a, b) hri_usart_set_US_MR_USART_NBSTOP_bf(a, b) +#define hri_usart_get_US_MR_NBSTOP_bf(a, b) hri_usart_get_US_MR_USART_NBSTOP_bf(a, b) +#define hri_usart_write_US_MR_NBSTOP_bf(a, b) hri_usart_write_US_MR_USART_NBSTOP_bf(a, b) +#define hri_usart_clear_US_MR_NBSTOP_bf(a, b) hri_usart_clear_US_MR_USART_NBSTOP_bf(a, b) +#define hri_usart_toggle_US_MR_NBSTOP_bf(a, b) hri_usart_toggle_US_MR_USART_NBSTOP_bf(a, b) +#define hri_usart_read_US_MR_NBSTOP_bf(a) hri_usart_read_US_MR_USART_NBSTOP_bf(a) +#define hri_usart_set_US_MR_CHMODE_bf(a, b) hri_usart_set_US_MR_USART_CHMODE_bf(a, b) +#define hri_usart_get_US_MR_CHMODE_bf(a, b) hri_usart_get_US_MR_USART_CHMODE_bf(a, b) +#define hri_usart_write_US_MR_CHMODE_bf(a, b) hri_usart_write_US_MR_USART_CHMODE_bf(a, b) +#define hri_usart_clear_US_MR_CHMODE_bf(a, b) hri_usart_clear_US_MR_USART_CHMODE_bf(a, b) +#define hri_usart_toggle_US_MR_CHMODE_bf(a, b) hri_usart_toggle_US_MR_USART_CHMODE_bf(a, b) +#define hri_usart_read_US_MR_CHMODE_bf(a) hri_usart_read_US_MR_USART_CHMODE_bf(a) +#define hri_usart_set_US_TTGR_TG_bf(a, b) hri_usart_set_US_TTGR_USART_TG_bf(a, b) +#define hri_usart_get_US_TTGR_TG_bf(a, b) hri_usart_get_US_TTGR_USART_TG_bf(a, b) +#define hri_usart_write_US_TTGR_TG_bf(a, b) hri_usart_write_US_TTGR_USART_TG_bf(a, b) +#define hri_usart_clear_US_TTGR_TG_bf(a, b) hri_usart_clear_US_TTGR_USART_TG_bf(a, b) +#define hri_usart_toggle_US_TTGR_TG_bf(a, b) hri_usart_toggle_US_TTGR_USART_TG_bf(a, b) +#define hri_usart_read_US_TTGR_TG_bf(a) hri_usart_read_US_TTGR_USART_TG_bf(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USART_E70B_H_INCLUDED */ +#endif /* _SAME70_USART_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_usbhs_e70b.h b/bsp/microchip/same70/bsp/hri/hri_usbhs_e70b.h new file mode 100644 index 0000000000..bf8ef546d1 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_usbhs_e70b.h @@ -0,0 +1,10222 @@ +/** + * \file + * + * \brief SAM USBHS + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_USBHS_COMPONENT_ +#ifndef _HRI_USBHS_E70B_H_INCLUDED_ +#define _HRI_USBHS_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USBHS_CRITICAL_SECTIONS) +#define USBHS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USBHS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USBHS_CRITICAL_SECTION_ENTER() +#define USBHS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_usbhs_ctrl_reg_t; +typedef uint32_t hri_usbhs_devctrl_reg_t; +typedef uint32_t hri_usbhs_devdmaaddress_reg_t; +typedef uint32_t hri_usbhs_devdmacontrol_reg_t; +typedef uint32_t hri_usbhs_devdmanxtdsc_reg_t; +typedef uint32_t hri_usbhs_devdmastatus_reg_t; +typedef uint32_t hri_usbhs_devept_reg_t; +typedef uint32_t hri_usbhs_deveptcfg_reg_t; +typedef uint32_t hri_usbhs_deveptidr_reg_t; +typedef uint32_t hri_usbhs_deveptier_reg_t; +typedef uint32_t hri_usbhs_deveptifr_reg_t; +typedef uint32_t hri_usbhs_deveptimr_reg_t; +typedef uint32_t hri_usbhs_deveptisr_reg_t; +typedef uint32_t hri_usbhs_devfnum_reg_t; +typedef uint32_t hri_usbhs_devicr_reg_t; +typedef uint32_t hri_usbhs_devifr_reg_t; +typedef uint32_t hri_usbhs_devimr_reg_t; +typedef uint32_t hri_usbhs_devisr_reg_t; +typedef uint32_t hri_usbhs_hstaddr1_reg_t; +typedef uint32_t hri_usbhs_hstaddr2_reg_t; +typedef uint32_t hri_usbhs_hstaddr3_reg_t; +typedef uint32_t hri_usbhs_hstctrl_reg_t; +typedef uint32_t hri_usbhs_hstdmaaddress_reg_t; +typedef uint32_t hri_usbhs_hstdmacontrol_reg_t; +typedef uint32_t hri_usbhs_hstdmanxtdsc_reg_t; +typedef uint32_t hri_usbhs_hstdmastatus_reg_t; +typedef uint32_t hri_usbhs_hstfnum_reg_t; +typedef uint32_t hri_usbhs_hsticr_reg_t; +typedef uint32_t hri_usbhs_hstifr_reg_t; +typedef uint32_t hri_usbhs_hstimr_reg_t; +typedef uint32_t hri_usbhs_hstisr_reg_t; +typedef uint32_t hri_usbhs_hstpip_reg_t; +typedef uint32_t hri_usbhs_hstpipcfg_reg_t; +typedef uint32_t hri_usbhs_hstpiperr_reg_t; +typedef uint32_t hri_usbhs_hstpipidr_reg_t; +typedef uint32_t hri_usbhs_hstpipier_reg_t; +typedef uint32_t hri_usbhs_hstpipifr_reg_t; +typedef uint32_t hri_usbhs_hstpipimr_reg_t; +typedef uint32_t hri_usbhs_hstpipinrq_reg_t; +typedef uint32_t hri_usbhs_hstpipisr_reg_t; +typedef uint32_t hri_usbhs_sfr_reg_t; +typedef uint32_t hri_usbhs_sr_reg_t; +typedef uint32_t hri_usbhsdevdma_devdmaaddress_reg_t; +typedef uint32_t hri_usbhsdevdma_devdmacontrol_reg_t; +typedef uint32_t hri_usbhsdevdma_devdmanxtdsc_reg_t; +typedef uint32_t hri_usbhsdevdma_devdmastatus_reg_t; +typedef uint32_t hri_usbhshstdma_hstdmaaddress_reg_t; +typedef uint32_t hri_usbhshstdma_hstdmacontrol_reg_t; +typedef uint32_t hri_usbhshstdma_hstdmanxtdsc_reg_t; +typedef uint32_t hri_usbhshstdma_hstdmastatus_reg_t; + +static inline bool hri_usbhs_get_DEVEPTISR_TXINI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_TXINI) >> USBHS_DEVEPTISR_TXINI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_TXINI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_TXINI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_RXOUTI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_RXOUTI) >> USBHS_DEVEPTISR_RXOUTI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_RXOUTI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_RXOUTI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CTRL_RXSTPI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CTRL_RXSTPI) >> USBHS_DEVEPTISR_CTRL_RXSTPI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_BLK_RXSTPI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_BLK_RXSTPI) >> USBHS_DEVEPTISR_BLK_RXSTPI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_INTRPT_RXSTPI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_INTRPT_RXSTPI) >> USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_CTRL_RXSTPI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_CTRL_RXSTPI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_BLK_RXSTPI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_BLK_RXSTPI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_INTRPT_RXSTPI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_INTRPT_RXSTPI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_ISO_UNDERFI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_ISO_UNDERFI) >> USBHS_DEVEPTISR_ISO_UNDERFI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_ISO_UNDERFI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_ISO_UNDERFI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CTRL_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CTRL_NAKOUTI) >> USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_BLK_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_BLK_NAKOUTI) >> USBHS_DEVEPTISR_BLK_NAKOUTI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_INTRPT_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_INTRPT_NAKOUTI) + >> USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_CTRL_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_CTRL_NAKOUTI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_BLK_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_BLK_NAKOUTI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_INTRPT_NAKOUTI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_INTRPT_NAKOUTI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_ISO_HBISOINERRI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_ISO_HBISOINERRI) + >> USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_ISO_HBISOINERRI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_ISO_HBISOINERRI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CTRL_NAKINI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CTRL_NAKINI) >> USBHS_DEVEPTISR_CTRL_NAKINI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_BLK_NAKINI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_BLK_NAKINI) >> USBHS_DEVEPTISR_BLK_NAKINI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_INTRPT_NAKINI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_INTRPT_NAKINI) >> USBHS_DEVEPTISR_INTRPT_NAKINI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_CTRL_NAKINI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_CTRL_NAKINI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_BLK_NAKINI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_BLK_NAKINI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_INTRPT_NAKINI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_INTRPT_NAKINI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_ISO_HBISOFLUSHI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_ISO_HBISOFLUSHI) + >> USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_ISO_HBISOFLUSHI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_ISO_HBISOFLUSHI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_OVERFI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_OVERFI) >> USBHS_DEVEPTISR_OVERFI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_OVERFI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_OVERFI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CTRL_STALLEDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CTRL_STALLEDI) >> USBHS_DEVEPTISR_CTRL_STALLEDI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_BLK_STALLEDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_BLK_STALLEDI) >> USBHS_DEVEPTISR_BLK_STALLEDI_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_INTRPT_STALLEDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_INTRPT_STALLEDI) + >> USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_CTRL_STALLEDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_CTRL_STALLEDI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_BLK_STALLEDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_BLK_STALLEDI; +} + +static inline void hri_usbhs_clear_DEVEPTISR_INTRPT_STALLEDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_INTRPT_STALLEDI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_ISO_CRCERRI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_ISO_CRCERRI) >> USBHS_DEVEPTISR_ISO_CRCERRI_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_ISO_CRCERRI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_ISO_CRCERRI; +} + +static inline bool hri_usbhs_get_DEVEPTISR_SHORTPACKET_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_SHORTPACKET) >> USBHS_DEVEPTISR_SHORTPACKET_Pos; +} + +static inline void hri_usbhs_clear_DEVEPTISR_SHORTPACKET_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = USBHS_DEVEPTISR_SHORTPACKET; +} + +static inline bool hri_usbhs_get_DEVEPTISR_ISO_ERRORTRANS_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_ISO_ERRORTRANS) + >> USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_RWALL_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_RWALL) >> USBHS_DEVEPTISR_RWALL_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CTRL_CTRLDIR_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CTRL_CTRLDIR) >> USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_BLK_CTRLDIR_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_BLK_CTRLDIR) >> USBHS_DEVEPTISR_BLK_CTRLDIR_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_INTRPT_CTRLDIR_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_INTRPT_CTRLDIR) + >> USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos; +} + +static inline bool hri_usbhs_get_DEVEPTISR_CFGOK_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTISR[index] & USBHS_DEVEPTISR_CFGOK) >> USBHS_DEVEPTISR_CFGOK_Pos; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_get_DEVEPTISR_DTSEQ_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_DTSEQ(mask)) >> USBHS_DEVEPTISR_DTSEQ_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_read_DEVEPTISR_DTSEQ_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_DTSEQ_Msk) >> USBHS_DEVEPTISR_DTSEQ_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_get_DEVEPTISR_NBUSYBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_NBUSYBK(mask)) >> USBHS_DEVEPTISR_NBUSYBK_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_read_DEVEPTISR_NBUSYBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_NBUSYBK_Msk) >> USBHS_DEVEPTISR_NBUSYBK_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_get_DEVEPTISR_CURRBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_CURRBK(mask)) >> USBHS_DEVEPTISR_CURRBK_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_read_DEVEPTISR_CURRBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_CURRBK_Msk) >> USBHS_DEVEPTISR_CURRBK_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_get_DEVEPTISR_BYCT_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_BYCT(mask)) >> USBHS_DEVEPTISR_BYCT_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_read_DEVEPTISR_BYCT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp = (tmp & USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_get_DEVEPTISR_reg(const void *const hw, uint8_t index, + hri_usbhs_deveptisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_deveptisr_reg_t hri_usbhs_read_DEVEPTISR_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_DEVEPTISR[index]; +} + +static inline void hri_usbhs_clear_DEVEPTISR_reg(const void *const hw, uint8_t index, hri_usbhs_deveptisr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = mask; +} + +static inline void hri_usbhs_write_DEVEPTICR_reg(const void *const hw, uint8_t index, hri_usbhs_deveptisr_reg_t data) +{ + ((Usbhs *)hw)->USBHS_DEVEPTICR[index] = data; +} + +static inline bool hri_usbhs_get_HSTPIPISR_RXINI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_RXINI) >> USBHS_HSTPIPISR_RXINI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_RXINI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_RXINI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_TXOUTI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_TXOUTI) >> USBHS_HSTPIPISR_TXOUTI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_TXOUTI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_TXOUTI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_CTRL_TXSTPI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_CTRL_TXSTPI) >> USBHS_HSTPIPISR_CTRL_TXSTPI_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_BLK_TXSTPI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_BLK_TXSTPI) >> USBHS_HSTPIPISR_BLK_TXSTPI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_CTRL_TXSTPI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_CTRL_TXSTPI; +} + +static inline void hri_usbhs_clear_HSTPIPISR_BLK_TXSTPI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_BLK_TXSTPI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_ISO_UNDERFI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_ISO_UNDERFI) >> USBHS_HSTPIPISR_ISO_UNDERFI_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_INTRPT_UNDERFI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_INTRPT_UNDERFI) + >> USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_ISO_UNDERFI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_ISO_UNDERFI; +} + +static inline void hri_usbhs_clear_HSTPIPISR_INTRPT_UNDERFI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_INTRPT_UNDERFI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_PERRI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_PERRI) >> USBHS_HSTPIPISR_PERRI_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_NAKEDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_NAKEDI) >> USBHS_HSTPIPISR_NAKEDI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_NAKEDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_NAKEDI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_OVERFI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_OVERFI) >> USBHS_HSTPIPISR_OVERFI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_OVERFI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_OVERFI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_CTRL_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_CTRL_RXSTALLDI) + >> USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_BLK_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_BLK_RXSTALLDI) >> USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_INTRPT_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_INTRPT_RXSTALLDI) + >> USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_CTRL_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_CTRL_RXSTALLDI; +} + +static inline void hri_usbhs_clear_HSTPIPISR_BLK_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_BLK_RXSTALLDI; +} + +static inline void hri_usbhs_clear_HSTPIPISR_INTRPT_RXSTALLDI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_INTRPT_RXSTALLDI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_ISO_CRCERRI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_ISO_CRCERRI) >> USBHS_HSTPIPISR_ISO_CRCERRI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_ISO_CRCERRI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_ISO_CRCERRI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_SHORTPACKETI_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_SHORTPACKETI) >> USBHS_HSTPIPISR_SHORTPACKETI_Pos; +} + +static inline void hri_usbhs_clear_HSTPIPISR_SHORTPACKETI_bit(const void *const hw, uint8_t index) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = USBHS_HSTPIPISR_SHORTPACKETI; +} + +static inline bool hri_usbhs_get_HSTPIPISR_RWALL_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_RWALL) >> USBHS_HSTPIPISR_RWALL_Pos; +} + +static inline bool hri_usbhs_get_HSTPIPISR_CFGOK_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPISR[index] & USBHS_HSTPIPISR_CFGOK) >> USBHS_HSTPIPISR_CFGOK_Pos; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_get_HSTPIPISR_DTSEQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_DTSEQ(mask)) >> USBHS_HSTPIPISR_DTSEQ_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_read_HSTPIPISR_DTSEQ_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_DTSEQ_Msk) >> USBHS_HSTPIPISR_DTSEQ_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_get_HSTPIPISR_NBUSYBK_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_NBUSYBK(mask)) >> USBHS_HSTPIPISR_NBUSYBK_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_read_HSTPIPISR_NBUSYBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_NBUSYBK_Msk) >> USBHS_HSTPIPISR_NBUSYBK_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_get_HSTPIPISR_CURRBK_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_CURRBK(mask)) >> USBHS_HSTPIPISR_CURRBK_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_read_HSTPIPISR_CURRBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_CURRBK_Msk) >> USBHS_HSTPIPISR_CURRBK_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_get_HSTPIPISR_PBYCT_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_PBYCT(mask)) >> USBHS_HSTPIPISR_PBYCT_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_read_HSTPIPISR_PBYCT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp = (tmp & USBHS_HSTPIPISR_PBYCT_Msk) >> USBHS_HSTPIPISR_PBYCT_Pos; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_get_HSTPIPISR_reg(const void *const hw, uint8_t index, + hri_usbhs_hstpipisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_hstpipisr_reg_t hri_usbhs_read_HSTPIPISR_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_HSTPIPISR[index]; +} + +static inline void hri_usbhs_clear_HSTPIPISR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipisr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = mask; +} + +static inline void hri_usbhs_write_HSTPIPICR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipisr_reg_t data) +{ + ((Usbhs *)hw)->USBHS_HSTPIPICR[index] = data; +} + +static inline bool hri_usbhs_get_SR_RDERRI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_SR & USBHS_SR_RDERRI) >> USBHS_SR_RDERRI_Pos; +} + +static inline void hri_usbhs_clear_SR_RDERRI_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_SCR = USBHS_SR_RDERRI; +} + +static inline bool hri_usbhs_get_SR_CLKUSABLE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_SR & USBHS_SR_CLKUSABLE) >> USBHS_SR_CLKUSABLE_Pos; +} + +static inline hri_usbhs_sr_reg_t hri_usbhs_get_SR_SPEED_bf(const void *const hw, hri_usbhs_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_SR; + tmp = (tmp & USBHS_SR_SPEED(mask)) >> USBHS_SR_SPEED_Pos; + return tmp; +} + +static inline hri_usbhs_sr_reg_t hri_usbhs_read_SR_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_SR; + tmp = (tmp & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos; + return tmp; +} + +static inline hri_usbhs_sr_reg_t hri_usbhs_get_SR_reg(const void *const hw, hri_usbhs_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_SR; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_sr_reg_t hri_usbhs_read_SR_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_SR; +} + +static inline void hri_usbhs_clear_SR_reg(const void *const hw, hri_usbhs_sr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_SCR = mask; +} + +static inline void hri_usbhs_write_SCR_reg(const void *const hw, hri_usbhs_sr_reg_t data) +{ + ((Usbhs *)hw)->USBHS_SCR = data; +} + +static inline void hri_usbhs_set_DEVIMR_SUSPE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_SUSPE; +} + +static inline bool hri_usbhs_get_DEVIMR_SUSPE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_SUSPE) >> USBHS_DEVIMR_SUSPE_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_SUSPE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_SUSPE; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_SUSPE; + } +} + +static inline void hri_usbhs_clear_DEVIMR_SUSPE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_SUSPE; +} + +static inline void hri_usbhs_set_DEVIMR_MSOFE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_MSOFE; +} + +static inline bool hri_usbhs_get_DEVIMR_MSOFE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_MSOFE) >> USBHS_DEVIMR_MSOFE_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_MSOFE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_MSOFE; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_MSOFE; + } +} + +static inline void hri_usbhs_clear_DEVIMR_MSOFE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_MSOFE; +} + +static inline void hri_usbhs_set_DEVIMR_SOFE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_SOFE; +} + +static inline bool hri_usbhs_get_DEVIMR_SOFE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_SOFE) >> USBHS_DEVIMR_SOFE_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_SOFE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_SOFE; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_SOFE; + } +} + +static inline void hri_usbhs_clear_DEVIMR_SOFE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_SOFE; +} + +static inline void hri_usbhs_set_DEVIMR_EORSTE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_EORSTE; +} + +static inline bool hri_usbhs_get_DEVIMR_EORSTE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_EORSTE) >> USBHS_DEVIMR_EORSTE_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_EORSTE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_EORSTE; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_EORSTE; + } +} + +static inline void hri_usbhs_clear_DEVIMR_EORSTE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_EORSTE; +} + +static inline void hri_usbhs_set_DEVIMR_WAKEUPE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_WAKEUPE; +} + +static inline bool hri_usbhs_get_DEVIMR_WAKEUPE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_WAKEUPE) >> USBHS_DEVIMR_WAKEUPE_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_WAKEUPE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_WAKEUPE; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_WAKEUPE; + } +} + +static inline void hri_usbhs_clear_DEVIMR_WAKEUPE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_WAKEUPE; +} + +static inline void hri_usbhs_set_DEVIMR_EORSME_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_EORSME; +} + +static inline bool hri_usbhs_get_DEVIMR_EORSME_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_EORSME) >> USBHS_DEVIMR_EORSME_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_EORSME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_EORSME; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_EORSME; + } +} + +static inline void hri_usbhs_clear_DEVIMR_EORSME_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_EORSME; +} + +static inline void hri_usbhs_set_DEVIMR_UPRSME_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_UPRSME; +} + +static inline bool hri_usbhs_get_DEVIMR_UPRSME_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_UPRSME) >> USBHS_DEVIMR_UPRSME_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_UPRSME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_UPRSME; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_UPRSME; + } +} + +static inline void hri_usbhs_clear_DEVIMR_UPRSME_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_UPRSME; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_0; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_0) >> USBHS_DEVIMR_PEP_0_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_0; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_0; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_0; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_1; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_1) >> USBHS_DEVIMR_PEP_1_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_1; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_1; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_1; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_2; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_2) >> USBHS_DEVIMR_PEP_2_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_2; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_2; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_2; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_3; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_3) >> USBHS_DEVIMR_PEP_3_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_3; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_3; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_3; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_4; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_4) >> USBHS_DEVIMR_PEP_4_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_4; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_4; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_4; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_5; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_5) >> USBHS_DEVIMR_PEP_5_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_5; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_5; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_5; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_6; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_6) >> USBHS_DEVIMR_PEP_6_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_6; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_6; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_6; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_7; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_7) >> USBHS_DEVIMR_PEP_7_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_7; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_7; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_7; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_8_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_8; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_8_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_8) >> USBHS_DEVIMR_PEP_8_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_8; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_8; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_8_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_8; +} + +static inline void hri_usbhs_set_DEVIMR_PEP_9_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_9; +} + +static inline bool hri_usbhs_get_DEVIMR_PEP_9_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_PEP_9) >> USBHS_DEVIMR_PEP_9_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_PEP_9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_9; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_PEP_9; + } +} + +static inline void hri_usbhs_clear_DEVIMR_PEP_9_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_PEP_9; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_1; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_1) >> USBHS_DEVIMR_DMA_1_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_1; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_1; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_1; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_2; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_2) >> USBHS_DEVIMR_DMA_2_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_2; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_2; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_2; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_3; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_3) >> USBHS_DEVIMR_DMA_3_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_3; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_3; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_3; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_4; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_4) >> USBHS_DEVIMR_DMA_4_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_4; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_4; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_4; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_5; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_5) >> USBHS_DEVIMR_DMA_5_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_5; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_5; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_5; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_6; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_6) >> USBHS_DEVIMR_DMA_6_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_6; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_6; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_6; +} + +static inline void hri_usbhs_set_DEVIMR_DMA_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_7; +} + +static inline bool hri_usbhs_get_DEVIMR_DMA_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVIMR & USBHS_DEVIMR_DMA_7) >> USBHS_DEVIMR_DMA_7_Pos; +} + +static inline void hri_usbhs_write_DEVIMR_DMA_7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_7; + } else { + ((Usbhs *)hw)->USBHS_DEVIER = USBHS_DEVIMR_DMA_7; + } +} + +static inline void hri_usbhs_clear_DEVIMR_DMA_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = USBHS_DEVIMR_DMA_7; +} + +static inline void hri_usbhs_set_DEVIMR_reg(const void *const hw, hri_usbhs_devimr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_DEVIER = mask; +} + +static inline hri_usbhs_devimr_reg_t hri_usbhs_get_DEVIMR_reg(const void *const hw, hri_usbhs_devimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVIMR; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_devimr_reg_t hri_usbhs_read_DEVIMR_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_DEVIMR; +} + +static inline void hri_usbhs_write_DEVIMR_reg(const void *const hw, hri_usbhs_devimr_reg_t data) +{ + ((Usbhs *)hw)->USBHS_DEVIER = data; + ((Usbhs *)hw)->USBHS_DEVIDR = ~data; +} + +static inline void hri_usbhs_clear_DEVIMR_reg(const void *const hw, hri_usbhs_devimr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_DEVIDR = mask; +} + +static inline void hri_usbhs_set_HSTIMR_DCONNIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DCONNIE; +} + +static inline bool hri_usbhs_get_HSTIMR_DCONNIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DCONNIE) >> USBHS_HSTIMR_DCONNIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DCONNIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DCONNIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DCONNIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DCONNIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DCONNIE; +} + +static inline void hri_usbhs_set_HSTIMR_DDISCIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DDISCIE; +} + +static inline bool hri_usbhs_get_HSTIMR_DDISCIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DDISCIE) >> USBHS_HSTIMR_DDISCIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DDISCIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DDISCIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DDISCIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DDISCIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DDISCIE; +} + +static inline void hri_usbhs_set_HSTIMR_RSTIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RSTIE; +} + +static inline bool hri_usbhs_get_HSTIMR_RSTIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_RSTIE) >> USBHS_HSTIMR_RSTIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_RSTIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RSTIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RSTIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_RSTIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RSTIE; +} + +static inline void hri_usbhs_set_HSTIMR_RSMEDIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RSMEDIE; +} + +static inline bool hri_usbhs_get_HSTIMR_RSMEDIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_RSMEDIE) >> USBHS_HSTIMR_RSMEDIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_RSMEDIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RSMEDIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RSMEDIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_RSMEDIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RSMEDIE; +} + +static inline void hri_usbhs_set_HSTIMR_RXRSMIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RXRSMIE; +} + +static inline bool hri_usbhs_get_HSTIMR_RXRSMIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_RXRSMIE) >> USBHS_HSTIMR_RXRSMIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_RXRSMIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RXRSMIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_RXRSMIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_RXRSMIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_RXRSMIE; +} + +static inline void hri_usbhs_set_HSTIMR_HSOFIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_HSOFIE; +} + +static inline bool hri_usbhs_get_HSTIMR_HSOFIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_HSOFIE) >> USBHS_HSTIMR_HSOFIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_HSOFIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_HSOFIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_HSOFIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_HSOFIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_HSOFIE; +} + +static inline void hri_usbhs_set_HSTIMR_HWUPIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_HWUPIE; +} + +static inline bool hri_usbhs_get_HSTIMR_HWUPIE_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_HWUPIE) >> USBHS_HSTIMR_HWUPIE_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_HWUPIE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_HWUPIE; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_HWUPIE; + } +} + +static inline void hri_usbhs_clear_HSTIMR_HWUPIE_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_HWUPIE; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_0; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_0) >> USBHS_HSTIMR_PEP_0_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_0; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_0; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_0; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_1; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_1) >> USBHS_HSTIMR_PEP_1_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_1; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_1; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_1; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_2; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_2) >> USBHS_HSTIMR_PEP_2_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_2; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_2; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_2; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_3; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_3) >> USBHS_HSTIMR_PEP_3_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_3; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_3; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_3; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_4; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_4) >> USBHS_HSTIMR_PEP_4_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_4; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_4; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_4; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_5; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_5) >> USBHS_HSTIMR_PEP_5_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_5; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_5; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_5; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_6; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_6) >> USBHS_HSTIMR_PEP_6_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_6; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_6; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_6; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_7; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_7) >> USBHS_HSTIMR_PEP_7_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_7; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_7; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_7_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_7; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_8_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_8; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_8_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_8) >> USBHS_HSTIMR_PEP_8_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_8; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_8; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_8_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_8; +} + +static inline void hri_usbhs_set_HSTIMR_PEP_9_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_9; +} + +static inline bool hri_usbhs_get_HSTIMR_PEP_9_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_PEP_9) >> USBHS_HSTIMR_PEP_9_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_PEP_9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_9; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_PEP_9; + } +} + +static inline void hri_usbhs_clear_HSTIMR_PEP_9_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_PEP_9; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_0; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_0) >> USBHS_HSTIMR_DMA_0_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_0; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_0; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_0_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_0; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_1; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_1) >> USBHS_HSTIMR_DMA_1_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_1; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_1; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_1_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_1; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_2; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_2) >> USBHS_HSTIMR_DMA_2_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_2; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_2; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_2_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_2; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_3; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_3) >> USBHS_HSTIMR_DMA_3_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_3; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_3; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_3_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_3; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_4; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_4) >> USBHS_HSTIMR_DMA_4_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_4; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_4; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_4_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_4; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_5; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_5) >> USBHS_HSTIMR_DMA_5_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_5; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_5; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_5_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_5; +} + +static inline void hri_usbhs_set_HSTIMR_DMA_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_6; +} + +static inline bool hri_usbhs_get_HSTIMR_DMA_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTIMR & USBHS_HSTIMR_DMA_6) >> USBHS_HSTIMR_DMA_6_Pos; +} + +static inline void hri_usbhs_write_HSTIMR_DMA_6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_6; + } else { + ((Usbhs *)hw)->USBHS_HSTIER = USBHS_HSTIMR_DMA_6; + } +} + +static inline void hri_usbhs_clear_HSTIMR_DMA_6_bit(const void *const hw) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = USBHS_HSTIMR_DMA_6; +} + +static inline void hri_usbhs_set_HSTIMR_reg(const void *const hw, hri_usbhs_hstimr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_HSTIER = mask; +} + +static inline hri_usbhs_hstimr_reg_t hri_usbhs_get_HSTIMR_reg(const void *const hw, hri_usbhs_hstimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTIMR; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_hstimr_reg_t hri_usbhs_read_HSTIMR_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTIMR; +} + +static inline void hri_usbhs_write_HSTIMR_reg(const void *const hw, hri_usbhs_hstimr_reg_t data) +{ + ((Usbhs *)hw)->USBHS_HSTIER = data; + ((Usbhs *)hw)->USBHS_HSTIDR = ~data; +} + +static inline void hri_usbhs_clear_HSTIMR_reg(const void *const hw, hri_usbhs_hstimr_reg_t mask) +{ + ((Usbhs *)hw)->USBHS_HSTIDR = mask; +} + +static inline bool hri_usbhs_get_DEVISR_SUSP_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_SUSP) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_MSOF_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_MSOF) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_SOF_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_SOF) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_EORST_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_EORST) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_WAKEUP_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_WAKEUP) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_EORSM_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_EORSM) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_UPRSM_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_UPRSM) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_0) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_1) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_2) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_3) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_4) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_5) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_6) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_7) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_8_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_8) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_PEP_9_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_PEP_9) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_1) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_2) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_3) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_4) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_5) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_6) > 0; +} + +static inline bool hri_usbhs_get_DEVISR_DMA_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVISR & USBHS_DEVISR_DMA_7) > 0; +} + +static inline hri_usbhs_devisr_reg_t hri_usbhs_get_DEVISR_reg(const void *const hw, hri_usbhs_devisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVISR; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_devisr_reg_t hri_usbhs_read_DEVISR_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_DEVISR; +} + +static inline bool hri_usbhs_get_DEVFNUM_FNCERR_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) > 0; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_get_DEVFNUM_MFNUM_bf(const void *const hw, hri_usbhs_devfnum_reg_t mask) +{ + return (((Usbhs *)hw)->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM(mask)) >> USBHS_DEVFNUM_MFNUM_Pos; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_read_DEVFNUM_MFNUM_bf(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk) >> USBHS_DEVFNUM_MFNUM_Pos; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_get_DEVFNUM_FNUM_bf(const void *const hw, hri_usbhs_devfnum_reg_t mask) +{ + return (((Usbhs *)hw)->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM(mask)) >> USBHS_DEVFNUM_FNUM_Pos; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_read_DEVFNUM_FNUM_bf(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) >> USBHS_DEVFNUM_FNUM_Pos; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_get_DEVFNUM_reg(const void *const hw, hri_usbhs_devfnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVFNUM; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_devfnum_reg_t hri_usbhs_read_DEVFNUM_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_DEVFNUM; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_TXINE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_TXINE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_RXOUTE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_RXOUTE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_RXSTPE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_RXSTPE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_RXSTPE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_RXSTPE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_RXSTPE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_RXSTPE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_UNDERFE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_UNDERFE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_NAKOUTE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_NAKOUTE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_NAKOUTE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_NAKOUTE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_NAKOUTE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_NAKOUTE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_HBISOINERRE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_HBISOINERRE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_NAKINE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_NAKINE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_NAKINE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_NAKINE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_NAKINE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_NAKINE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_HBISOFLUSHE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_HBISOFLUSHE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_OVERFE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_OVERFE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_STALLEDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_STALLEDE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_STALLEDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_STALLEDE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_STALLEDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_STALLEDE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_CRCERRE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_CRCERRE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_SHORTPACKETE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_SHORTPACKETE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_MDATAE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_MDATAE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_DATAXE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_DATAXE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_ISO_ERRORTRANSE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_ISO_ERRORTRANSE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_NBUSYBKE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_NBUSYBKE) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_KILLBK_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_KILLBK) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_FIFOCON_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_FIFOCON) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_EPDISHDMA_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_EPDISHDMA) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_NYETDIS_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_NYETDIS) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_NYETDIS_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_NYETDIS) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_NYETDIS_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_NYETDIS) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_RSTDT_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_RSTDT) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_CTRL_STALLRQ_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_CTRL_STALLRQ) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_BLK_STALLRQ_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_BLK_STALLRQ) > 0; +} + +static inline bool hri_usbhs_get_DEVEPTIMR_INTRPT_STALLRQ_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_DEVEPTIMR[index] & USBHS_DEVEPTIMR_INTRPT_STALLRQ) > 0; +} + +static inline hri_usbhs_deveptimr_reg_t hri_usbhs_get_DEVEPTIMR_reg(const void *const hw, uint8_t index, + hri_usbhs_deveptimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTIMR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_deveptimr_reg_t hri_usbhs_read_DEVEPTIMR_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_DEVEPTIMR[index]; +} + +static inline bool hri_usbhs_get_HSTISR_DCONNI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DCONNI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DDISCI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DDISCI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_RSTI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_RSTI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_RSMEDI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_RSMEDI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_RXRSMI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_RXRSMI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_HSOFI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_HSOFI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_HWUPI_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_HWUPI) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_0) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_1) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_2) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_3) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_4) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_5) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_6) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_7_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_7) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_8_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_8) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_PEP_9_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_PEP_9) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_0_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_0) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_1_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_1) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_2_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_2) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_3_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_3) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_4_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_4) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_5_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_5) > 0; +} + +static inline bool hri_usbhs_get_HSTISR_DMA_6_bit(const void *const hw) +{ + return (((Usbhs *)hw)->USBHS_HSTISR & USBHS_HSTISR_DMA_6) > 0; +} + +static inline hri_usbhs_hstisr_reg_t hri_usbhs_get_HSTISR_reg(const void *const hw, hri_usbhs_hstisr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTISR; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_hstisr_reg_t hri_usbhs_read_HSTISR_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTISR; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_RXINE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_RXINE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_TXOUTE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_TXOUTE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_CTRL_TXSTPE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_CTRL_TXSTPE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_BLK_TXSTPE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_BLK_TXSTPE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_ISO_UNDERFIE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_ISO_UNDERFIE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_INTRPT_UNDERFIE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_INTRPT_UNDERFIE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_PERRE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_PERRE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_NAKEDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_NAKEDE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_OVERFIE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_OVERFIE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_CTRL_RXSTALLDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_CTRL_RXSTALLDE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_BLK_RXSTALLDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_BLK_RXSTALLDE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_INTRPT_RXSTALLDE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_INTRPT_RXSTALLDE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_ISO_CRCERRE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_ISO_CRCERRE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_SHORTPACKETIE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_SHORTPACKETIE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_NBUSYBKE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_NBUSYBKE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_FIFOCON_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_FIFOCON) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_PDISHDMA_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_PDISHDMA) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_PFREEZE_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_PFREEZE) > 0; +} + +static inline bool hri_usbhs_get_HSTPIPIMR_RSTDT_bit(const void *const hw, uint8_t index) +{ + return (((Usbhs *)hw)->USBHS_HSTPIPIMR[index] & USBHS_HSTPIPIMR_RSTDT) > 0; +} + +static inline hri_usbhs_hstpipimr_reg_t hri_usbhs_get_HSTPIPIMR_reg(const void *const hw, uint8_t index, + hri_usbhs_hstpipimr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPIMR[index]; + tmp &= mask; + return tmp; +} + +static inline hri_usbhs_hstpipimr_reg_t hri_usbhs_read_HSTPIPIMR_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_HSTPIPIMR[index]; +} + +static inline void hri_usbhs_set_DEVCTRL_ADDEN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_ADDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_ADDEN) >> USBHS_DEVCTRL_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_ADDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_ADDEN; + tmp |= value << USBHS_DEVCTRL_ADDEN_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_ADDEN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_ADDEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_ADDEN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_ADDEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_DETACH_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_DETACH_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_DETACH) >> USBHS_DEVCTRL_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_DETACH_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_DETACH; + tmp |= value << USBHS_DEVCTRL_DETACH_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_DETACH_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_DETACH_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_DETACH; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_RMWKUP_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_RMWKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_RMWKUP) >> USBHS_DEVCTRL_RMWKUP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_RMWKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_RMWKUP; + tmp |= value << USBHS_DEVCTRL_RMWKUP_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_RMWKUP_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_RMWKUP; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_RMWKUP_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_RMWKUP; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_LS_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_LS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_LS) >> USBHS_DEVCTRL_LS_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_LS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_LS; + tmp |= value << USBHS_DEVCTRL_LS_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_LS_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_LS; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_LS_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_LS; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_TSTJ_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_TSTJ; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_TSTJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_TSTJ) >> USBHS_DEVCTRL_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_TSTJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_TSTJ; + tmp |= value << USBHS_DEVCTRL_TSTJ_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_TSTJ_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_TSTJ; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_TSTJ_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_TSTJ; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_TSTK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_TSTK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_TSTK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_TSTK) >> USBHS_DEVCTRL_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_TSTK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_TSTK; + tmp |= value << USBHS_DEVCTRL_TSTK_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_TSTK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_TSTK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_TSTK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_TSTK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_TSTPCKT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_TSTPCKT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_TSTPCKT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_TSTPCKT) >> USBHS_DEVCTRL_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_TSTPCKT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_TSTPCKT; + tmp |= value << USBHS_DEVCTRL_TSTPCKT_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_TSTPCKT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_TSTPCKT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_TSTPCKT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_TSTPCKT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_OPMODE2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_OPMODE2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVCTRL_OPMODE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_OPMODE2) >> USBHS_DEVCTRL_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_OPMODE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_OPMODE2; + tmp |= value << USBHS_DEVCTRL_OPMODE2_Pos; + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_OPMODE2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_OPMODE2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_OPMODE2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_OPMODE2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVCTRL_UADD_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_get_DEVCTRL_UADD_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_UADD(mask)) >> USBHS_DEVCTRL_UADD_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_UADD_bf(const void *const hw, hri_usbhs_devctrl_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_UADD_Msk; + tmp |= USBHS_DEVCTRL_UADD(data); + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_UADD_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_UADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_UADD_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_UADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_read_DEVCTRL_UADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_UADD_Msk) >> USBHS_DEVCTRL_UADD_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_get_DEVCTRL_SPDCONF_bf(const void *const hw, + hri_usbhs_devctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_SPDCONF(mask)) >> USBHS_DEVCTRL_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_devctrl_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= ~USBHS_DEVCTRL_SPDCONF_Msk; + tmp |= USBHS_DEVCTRL_SPDCONF(data); + ((Usbhs *)hw)->USBHS_DEVCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= USBHS_DEVCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_read_DEVCTRL_SPDCONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp = (tmp & USBHS_DEVCTRL_SPDCONF_Msk) >> USBHS_DEVCTRL_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVCTRL_reg(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_get_DEVCTRL_reg(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVCTRL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVCTRL_reg(const void *const hw, hri_usbhs_devctrl_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVCTRL_reg(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVCTRL_reg(const void *const hw, hri_usbhs_devctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVCTRL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devctrl_reg_t hri_usbhs_read_DEVCTRL_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_DEVCTRL; +} + +static inline void hri_usbhs_set_DEVEPT_EPEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN0) >> USBHS_DEVEPT_EPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN0; + tmp |= value << USBHS_DEVEPT_EPEN0_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN1) >> USBHS_DEVEPT_EPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN1; + tmp |= value << USBHS_DEVEPT_EPEN1_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN2) >> USBHS_DEVEPT_EPEN2_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN2; + tmp |= value << USBHS_DEVEPT_EPEN2_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN3) >> USBHS_DEVEPT_EPEN3_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN3; + tmp |= value << USBHS_DEVEPT_EPEN3_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN4) >> USBHS_DEVEPT_EPEN4_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN4; + tmp |= value << USBHS_DEVEPT_EPEN4_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN5) >> USBHS_DEVEPT_EPEN5_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN5; + tmp |= value << USBHS_DEVEPT_EPEN5_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN6) >> USBHS_DEVEPT_EPEN6_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN6; + tmp |= value << USBHS_DEVEPT_EPEN6_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN7) >> USBHS_DEVEPT_EPEN7_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN7; + tmp |= value << USBHS_DEVEPT_EPEN7_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN8) >> USBHS_DEVEPT_EPEN8_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN8; + tmp |= value << USBHS_DEVEPT_EPEN8_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPEN9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPEN9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPEN9) >> USBHS_DEVEPT_EPEN9_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPEN9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPEN9; + tmp |= value << USBHS_DEVEPT_EPEN9_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPEN9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPEN9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPEN9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPEN9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST0) >> USBHS_DEVEPT_EPRST0_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST0; + tmp |= value << USBHS_DEVEPT_EPRST0_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST1) >> USBHS_DEVEPT_EPRST1_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST1; + tmp |= value << USBHS_DEVEPT_EPRST1_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST2) >> USBHS_DEVEPT_EPRST2_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST2; + tmp |= value << USBHS_DEVEPT_EPRST2_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST3) >> USBHS_DEVEPT_EPRST3_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST3; + tmp |= value << USBHS_DEVEPT_EPRST3_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST4) >> USBHS_DEVEPT_EPRST4_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST4; + tmp |= value << USBHS_DEVEPT_EPRST4_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST5) >> USBHS_DEVEPT_EPRST5_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST5; + tmp |= value << USBHS_DEVEPT_EPRST5_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST6) >> USBHS_DEVEPT_EPRST6_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST6; + tmp |= value << USBHS_DEVEPT_EPRST6_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST7) >> USBHS_DEVEPT_EPRST7_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST7; + tmp |= value << USBHS_DEVEPT_EPRST7_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST8) >> USBHS_DEVEPT_EPRST8_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST8; + tmp |= value << USBHS_DEVEPT_EPRST8_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_EPRST9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= USBHS_DEVEPT_EPRST9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPT_EPRST9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp = (tmp & USBHS_DEVEPT_EPRST9) >> USBHS_DEVEPT_EPRST9_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPT_EPRST9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= ~USBHS_DEVEPT_EPRST9; + tmp |= value << USBHS_DEVEPT_EPRST9_Pos; + ((Usbhs *)hw)->USBHS_DEVEPT = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_EPRST9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~USBHS_DEVEPT_EPRST9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_EPRST9_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= USBHS_DEVEPT_EPRST9; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPT_reg(const void *const hw, hri_usbhs_devept_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devept_reg_t hri_usbhs_get_DEVEPT_reg(const void *const hw, hri_usbhs_devept_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPT; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPT_reg(const void *const hw, hri_usbhs_devept_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPT_reg(const void *const hw, hri_usbhs_devept_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPT_reg(const void *const hw, hri_usbhs_devept_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPT ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devept_reg_t hri_usbhs_read_DEVEPT_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_DEVEPT; +} + +static inline void hri_usbhs_set_DEVEPTCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPTCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_ALLOC) >> USBHS_DEVEPTCFG_ALLOC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_ALLOC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_ALLOC; + tmp |= value << USBHS_DEVEPTCFG_ALLOC_Pos; + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPTCFG_EPDIR_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_EPDIR; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPTCFG_EPDIR_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPDIR) >> USBHS_DEVEPTCFG_EPDIR_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_EPDIR_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_EPDIR; + tmp |= value << USBHS_DEVEPTCFG_EPDIR_Pos; + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_EPDIR_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_EPDIR; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_EPDIR_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_EPDIR; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPTCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVEPTCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_AUTOSW) >> USBHS_DEVEPTCFG_AUTOSW_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_AUTOSW_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_AUTOSW; + tmp |= value << USBHS_DEVEPTCFG_AUTOSW_Pos; + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index, hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_EPBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_get_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPBK(mask)) >> USBHS_DEVEPTCFG_EPBK_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_EPBK_Msk; + tmp |= USBHS_DEVEPTCFG_EPBK(data); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_EPBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_EPBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_read_DEVEPTCFG_EPBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPBK_Msk) >> USBHS_DEVEPTCFG_EPBK_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_EPSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_get_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPSIZE(mask)) >> USBHS_DEVEPTCFG_EPSIZE_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_EPSIZE_Msk; + tmp |= USBHS_DEVEPTCFG_EPSIZE(data); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_EPSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_EPSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_read_DEVEPTCFG_EPSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPSIZE_Msk) >> USBHS_DEVEPTCFG_EPSIZE_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_EPTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_get_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPTYPE(mask)) >> USBHS_DEVEPTCFG_EPTYPE_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_EPTYPE_Msk; + tmp |= USBHS_DEVEPTCFG_EPTYPE(data); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_EPTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_EPTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_read_DEVEPTCFG_EPTYPE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_EPTYPE_Msk) >> USBHS_DEVEPTCFG_EPTYPE_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= USBHS_DEVEPTCFG_NBTRANS(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_get_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_NBTRANS(mask)) >> USBHS_DEVEPTCFG_NBTRANS_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= ~USBHS_DEVEPTCFG_NBTRANS_Msk; + tmp |= USBHS_DEVEPTCFG_NBTRANS(data); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~USBHS_DEVEPTCFG_NBTRANS(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= USBHS_DEVEPTCFG_NBTRANS(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_read_DEVEPTCFG_NBTRANS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp = (tmp & USBHS_DEVEPTCFG_NBTRANS_Msk) >> USBHS_DEVEPTCFG_NBTRANS_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVEPTCFG_reg(const void *const hw, uint8_t index, hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_get_DEVEPTCFG_reg(const void *const hw, uint8_t index, + hri_usbhs_deveptcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVEPTCFG_reg(const void *const hw, uint8_t index, hri_usbhs_deveptcfg_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVEPTCFG_reg(const void *const hw, uint8_t index, hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVEPTCFG_reg(const void *const hw, uint8_t index, hri_usbhs_deveptcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTCFG[index] ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_deveptcfg_reg_t hri_usbhs_read_DEVEPTCFG_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_DEVEPTCFG[index]; +} + +static inline void hri_usbhs_set_HSTCTRL_SOFE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTCTRL_SOFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp = (tmp & USBHS_HSTCTRL_SOFE) >> USBHS_HSTCTRL_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTCTRL_SOFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp &= ~USBHS_HSTCTRL_SOFE; + tmp |= value << USBHS_HSTCTRL_SOFE_Pos; + ((Usbhs *)hw)->USBHS_HSTCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTCTRL_SOFE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTCTRL_SOFE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL ^= USBHS_HSTCTRL_SOFE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTCTRL_RESET_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTCTRL_RESET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp = (tmp & USBHS_HSTCTRL_RESET) >> USBHS_HSTCTRL_RESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTCTRL_RESET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp &= ~USBHS_HSTCTRL_RESET; + tmp |= value << USBHS_HSTCTRL_RESET_Pos; + ((Usbhs *)hw)->USBHS_HSTCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTCTRL_RESET_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTCTRL_RESET_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL ^= USBHS_HSTCTRL_RESET; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTCTRL_RESUME_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTCTRL_RESUME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp = (tmp & USBHS_HSTCTRL_RESUME) >> USBHS_HSTCTRL_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTCTRL_RESUME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp &= ~USBHS_HSTCTRL_RESUME; + tmp |= value << USBHS_HSTCTRL_RESUME_Pos; + ((Usbhs *)hw)->USBHS_HSTCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTCTRL_RESUME_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESUME; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTCTRL_RESUME_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL ^= USBHS_HSTCTRL_RESUME; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstctrl_reg_t hri_usbhs_get_HSTCTRL_SPDCONF_bf(const void *const hw, + hri_usbhs_hstctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp = (tmp & USBHS_HSTCTRL_SPDCONF(mask)) >> USBHS_HSTCTRL_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_hstctrl_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp &= ~USBHS_HSTCTRL_SPDCONF_Msk; + tmp |= USBHS_HSTCTRL_SPDCONF(data); + ((Usbhs *)hw)->USBHS_HSTCTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTCTRL_SPDCONF_bf(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL ^= USBHS_HSTCTRL_SPDCONF(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstctrl_reg_t hri_usbhs_read_HSTCTRL_SPDCONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp = (tmp & USBHS_HSTCTRL_SPDCONF_Msk) >> USBHS_HSTCTRL_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTCTRL_reg(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstctrl_reg_t hri_usbhs_get_HSTCTRL_reg(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTCTRL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTCTRL_reg(const void *const hw, hri_usbhs_hstctrl_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTCTRL_reg(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTCTRL_reg(const void *const hw, hri_usbhs_hstctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTCTRL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstctrl_reg_t hri_usbhs_read_HSTCTRL_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTCTRL; +} + +static inline void hri_usbhs_set_HSTPIP_PEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN0) >> USBHS_HSTPIP_PEN0_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN0; + tmp |= value << USBHS_HSTPIP_PEN0_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN1) >> USBHS_HSTPIP_PEN1_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN1; + tmp |= value << USBHS_HSTPIP_PEN1_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN2) >> USBHS_HSTPIP_PEN2_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN2; + tmp |= value << USBHS_HSTPIP_PEN2_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN3) >> USBHS_HSTPIP_PEN3_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN3; + tmp |= value << USBHS_HSTPIP_PEN3_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN4) >> USBHS_HSTPIP_PEN4_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN4; + tmp |= value << USBHS_HSTPIP_PEN4_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN5) >> USBHS_HSTPIP_PEN5_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN5; + tmp |= value << USBHS_HSTPIP_PEN5_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN6) >> USBHS_HSTPIP_PEN6_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN6; + tmp |= value << USBHS_HSTPIP_PEN6_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN7) >> USBHS_HSTPIP_PEN7_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN7; + tmp |= value << USBHS_HSTPIP_PEN7_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PEN8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PEN8) >> USBHS_HSTPIP_PEN8_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PEN8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PEN8; + tmp |= value << USBHS_HSTPIP_PEN8_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PEN8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PEN8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST0) >> USBHS_HSTPIP_PRST0_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST0; + tmp |= value << USBHS_HSTPIP_PRST0_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST0_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST0; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST1) >> USBHS_HSTPIP_PRST1_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST1; + tmp |= value << USBHS_HSTPIP_PRST1_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST1_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST1; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST2) >> USBHS_HSTPIP_PRST2_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST2; + tmp |= value << USBHS_HSTPIP_PRST2_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST2_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST2; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST3) >> USBHS_HSTPIP_PRST3_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST3; + tmp |= value << USBHS_HSTPIP_PRST3_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST3_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST3; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST4) >> USBHS_HSTPIP_PRST4_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST4; + tmp |= value << USBHS_HSTPIP_PRST4_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST4_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST4; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST5) >> USBHS_HSTPIP_PRST5_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST5; + tmp |= value << USBHS_HSTPIP_PRST5_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST5_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST5; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST6) >> USBHS_HSTPIP_PRST6_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST6; + tmp |= value << USBHS_HSTPIP_PRST6_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST6_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST6; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST7) >> USBHS_HSTPIP_PRST7_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST7; + tmp |= value << USBHS_HSTPIP_PRST7_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST7_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST7; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_PRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= USBHS_HSTPIP_PRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIP_PRST8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp = (tmp & USBHS_HSTPIP_PRST8) >> USBHS_HSTPIP_PRST8_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIP_PRST8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= ~USBHS_HSTPIP_PRST8; + tmp |= value << USBHS_HSTPIP_PRST8_Pos; + ((Usbhs *)hw)->USBHS_HSTPIP = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_PRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~USBHS_HSTPIP_PRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_PRST8_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= USBHS_HSTPIP_PRST8; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIP_reg(const void *const hw, hri_usbhs_hstpip_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpip_reg_t hri_usbhs_get_HSTPIP_reg(const void *const hw, hri_usbhs_hstpip_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIP; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIP_reg(const void *const hw, hri_usbhs_hstpip_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIP_reg(const void *const hw, hri_usbhs_hstpip_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIP_reg(const void *const hw, hri_usbhs_hstpip_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIP ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpip_reg_t hri_usbhs_read_HSTPIP_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTPIP; +} + +static inline void hri_usbhs_set_HSTFNUM_MFNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM |= USBHS_HSTFNUM_MFNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_get_HSTFNUM_MFNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_MFNUM(mask)) >> USBHS_HSTFNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTFNUM_MFNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp &= ~USBHS_HSTFNUM_MFNUM_Msk; + tmp |= USBHS_HSTFNUM_MFNUM(data); + ((Usbhs *)hw)->USBHS_HSTFNUM = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTFNUM_MFNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM &= ~USBHS_HSTFNUM_MFNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTFNUM_MFNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM ^= USBHS_HSTFNUM_MFNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_read_HSTFNUM_MFNUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_MFNUM_Msk) >> USBHS_HSTFNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTFNUM_FNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM |= USBHS_HSTFNUM_FNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_get_HSTFNUM_FNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_FNUM(mask)) >> USBHS_HSTFNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTFNUM_FNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp &= ~USBHS_HSTFNUM_FNUM_Msk; + tmp |= USBHS_HSTFNUM_FNUM(data); + ((Usbhs *)hw)->USBHS_HSTFNUM = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTFNUM_FNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM &= ~USBHS_HSTFNUM_FNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTFNUM_FNUM_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM ^= USBHS_HSTFNUM_FNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_read_HSTFNUM_FNUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_FNUM_Msk) >> USBHS_HSTFNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTFNUM_FLENHIGH_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM |= USBHS_HSTFNUM_FLENHIGH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_get_HSTFNUM_FLENHIGH_bf(const void *const hw, + hri_usbhs_hstfnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_FLENHIGH(mask)) >> USBHS_HSTFNUM_FLENHIGH_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTFNUM_FLENHIGH_bf(const void *const hw, hri_usbhs_hstfnum_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp &= ~USBHS_HSTFNUM_FLENHIGH_Msk; + tmp |= USBHS_HSTFNUM_FLENHIGH(data); + ((Usbhs *)hw)->USBHS_HSTFNUM = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTFNUM_FLENHIGH_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM &= ~USBHS_HSTFNUM_FLENHIGH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTFNUM_FLENHIGH_bf(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM ^= USBHS_HSTFNUM_FLENHIGH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_read_HSTFNUM_FLENHIGH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp = (tmp & USBHS_HSTFNUM_FLENHIGH_Msk) >> USBHS_HSTFNUM_FLENHIGH_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTFNUM_reg(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_get_HSTFNUM_reg(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTFNUM; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTFNUM_reg(const void *const hw, hri_usbhs_hstfnum_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTFNUM_reg(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTFNUM_reg(const void *const hw, hri_usbhs_hstfnum_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTFNUM ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstfnum_reg_t hri_usbhs_read_HSTFNUM_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTFNUM; +} + +static inline void hri_usbhs_set_HSTADDR1_HSTADDRP0_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 |= USBHS_HSTADDR1_HSTADDRP0(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_get_HSTADDR1_HSTADDRP0_bf(const void *const hw, + hri_usbhs_hstaddr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP0(mask)) >> USBHS_HSTADDR1_HSTADDRP0_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR1_HSTADDRP0_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp &= ~USBHS_HSTADDR1_HSTADDRP0_Msk; + tmp |= USBHS_HSTADDR1_HSTADDRP0(data); + ((Usbhs *)hw)->USBHS_HSTADDR1 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR1_HSTADDRP0_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 &= ~USBHS_HSTADDR1_HSTADDRP0(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR1_HSTADDRP0_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 ^= USBHS_HSTADDR1_HSTADDRP0(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_read_HSTADDR1_HSTADDRP0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP0_Msk) >> USBHS_HSTADDR1_HSTADDRP0_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR1_HSTADDRP1_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 |= USBHS_HSTADDR1_HSTADDRP1(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_get_HSTADDR1_HSTADDRP1_bf(const void *const hw, + hri_usbhs_hstaddr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP1(mask)) >> USBHS_HSTADDR1_HSTADDRP1_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR1_HSTADDRP1_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp &= ~USBHS_HSTADDR1_HSTADDRP1_Msk; + tmp |= USBHS_HSTADDR1_HSTADDRP1(data); + ((Usbhs *)hw)->USBHS_HSTADDR1 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR1_HSTADDRP1_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 &= ~USBHS_HSTADDR1_HSTADDRP1(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR1_HSTADDRP1_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 ^= USBHS_HSTADDR1_HSTADDRP1(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_read_HSTADDR1_HSTADDRP1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP1_Msk) >> USBHS_HSTADDR1_HSTADDRP1_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR1_HSTADDRP2_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 |= USBHS_HSTADDR1_HSTADDRP2(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_get_HSTADDR1_HSTADDRP2_bf(const void *const hw, + hri_usbhs_hstaddr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP2(mask)) >> USBHS_HSTADDR1_HSTADDRP2_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR1_HSTADDRP2_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp &= ~USBHS_HSTADDR1_HSTADDRP2_Msk; + tmp |= USBHS_HSTADDR1_HSTADDRP2(data); + ((Usbhs *)hw)->USBHS_HSTADDR1 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR1_HSTADDRP2_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 &= ~USBHS_HSTADDR1_HSTADDRP2(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR1_HSTADDRP2_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 ^= USBHS_HSTADDR1_HSTADDRP2(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_read_HSTADDR1_HSTADDRP2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP2_Msk) >> USBHS_HSTADDR1_HSTADDRP2_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR1_HSTADDRP3_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 |= USBHS_HSTADDR1_HSTADDRP3(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_get_HSTADDR1_HSTADDRP3_bf(const void *const hw, + hri_usbhs_hstaddr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP3(mask)) >> USBHS_HSTADDR1_HSTADDRP3_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR1_HSTADDRP3_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp &= ~USBHS_HSTADDR1_HSTADDRP3_Msk; + tmp |= USBHS_HSTADDR1_HSTADDRP3(data); + ((Usbhs *)hw)->USBHS_HSTADDR1 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR1_HSTADDRP3_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 &= ~USBHS_HSTADDR1_HSTADDRP3(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR1_HSTADDRP3_bf(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 ^= USBHS_HSTADDR1_HSTADDRP3(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_read_HSTADDR1_HSTADDRP3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp = (tmp & USBHS_HSTADDR1_HSTADDRP3_Msk) >> USBHS_HSTADDR1_HSTADDRP3_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR1_reg(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_get_HSTADDR1_reg(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR1; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR1_reg(const void *const hw, hri_usbhs_hstaddr1_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR1_reg(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR1_reg(const void *const hw, hri_usbhs_hstaddr1_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR1 ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr1_reg_t hri_usbhs_read_HSTADDR1_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTADDR1; +} + +static inline void hri_usbhs_set_HSTADDR2_HSTADDRP4_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 |= USBHS_HSTADDR2_HSTADDRP4(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_get_HSTADDR2_HSTADDRP4_bf(const void *const hw, + hri_usbhs_hstaddr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP4(mask)) >> USBHS_HSTADDR2_HSTADDRP4_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR2_HSTADDRP4_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp &= ~USBHS_HSTADDR2_HSTADDRP4_Msk; + tmp |= USBHS_HSTADDR2_HSTADDRP4(data); + ((Usbhs *)hw)->USBHS_HSTADDR2 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR2_HSTADDRP4_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 &= ~USBHS_HSTADDR2_HSTADDRP4(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR2_HSTADDRP4_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 ^= USBHS_HSTADDR2_HSTADDRP4(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_read_HSTADDR2_HSTADDRP4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP4_Msk) >> USBHS_HSTADDR2_HSTADDRP4_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR2_HSTADDRP5_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 |= USBHS_HSTADDR2_HSTADDRP5(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_get_HSTADDR2_HSTADDRP5_bf(const void *const hw, + hri_usbhs_hstaddr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP5(mask)) >> USBHS_HSTADDR2_HSTADDRP5_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR2_HSTADDRP5_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp &= ~USBHS_HSTADDR2_HSTADDRP5_Msk; + tmp |= USBHS_HSTADDR2_HSTADDRP5(data); + ((Usbhs *)hw)->USBHS_HSTADDR2 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR2_HSTADDRP5_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 &= ~USBHS_HSTADDR2_HSTADDRP5(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR2_HSTADDRP5_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 ^= USBHS_HSTADDR2_HSTADDRP5(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_read_HSTADDR2_HSTADDRP5_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP5_Msk) >> USBHS_HSTADDR2_HSTADDRP5_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR2_HSTADDRP6_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 |= USBHS_HSTADDR2_HSTADDRP6(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_get_HSTADDR2_HSTADDRP6_bf(const void *const hw, + hri_usbhs_hstaddr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP6(mask)) >> USBHS_HSTADDR2_HSTADDRP6_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR2_HSTADDRP6_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp &= ~USBHS_HSTADDR2_HSTADDRP6_Msk; + tmp |= USBHS_HSTADDR2_HSTADDRP6(data); + ((Usbhs *)hw)->USBHS_HSTADDR2 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR2_HSTADDRP6_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 &= ~USBHS_HSTADDR2_HSTADDRP6(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR2_HSTADDRP6_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 ^= USBHS_HSTADDR2_HSTADDRP6(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_read_HSTADDR2_HSTADDRP6_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP6_Msk) >> USBHS_HSTADDR2_HSTADDRP6_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR2_HSTADDRP7_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 |= USBHS_HSTADDR2_HSTADDRP7(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_get_HSTADDR2_HSTADDRP7_bf(const void *const hw, + hri_usbhs_hstaddr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP7(mask)) >> USBHS_HSTADDR2_HSTADDRP7_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR2_HSTADDRP7_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp &= ~USBHS_HSTADDR2_HSTADDRP7_Msk; + tmp |= USBHS_HSTADDR2_HSTADDRP7(data); + ((Usbhs *)hw)->USBHS_HSTADDR2 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR2_HSTADDRP7_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 &= ~USBHS_HSTADDR2_HSTADDRP7(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR2_HSTADDRP7_bf(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 ^= USBHS_HSTADDR2_HSTADDRP7(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_read_HSTADDR2_HSTADDRP7_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp = (tmp & USBHS_HSTADDR2_HSTADDRP7_Msk) >> USBHS_HSTADDR2_HSTADDRP7_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR2_reg(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_get_HSTADDR2_reg(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR2; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR2_reg(const void *const hw, hri_usbhs_hstaddr2_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR2_reg(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR2_reg(const void *const hw, hri_usbhs_hstaddr2_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR2 ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr2_reg_t hri_usbhs_read_HSTADDR2_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTADDR2; +} + +static inline void hri_usbhs_set_HSTADDR3_HSTADDRP8_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 |= USBHS_HSTADDR3_HSTADDRP8(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_get_HSTADDR3_HSTADDRP8_bf(const void *const hw, + hri_usbhs_hstaddr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp = (tmp & USBHS_HSTADDR3_HSTADDRP8(mask)) >> USBHS_HSTADDR3_HSTADDRP8_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR3_HSTADDRP8_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp &= ~USBHS_HSTADDR3_HSTADDRP8_Msk; + tmp |= USBHS_HSTADDR3_HSTADDRP8(data); + ((Usbhs *)hw)->USBHS_HSTADDR3 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR3_HSTADDRP8_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 &= ~USBHS_HSTADDR3_HSTADDRP8(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR3_HSTADDRP8_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 ^= USBHS_HSTADDR3_HSTADDRP8(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_read_HSTADDR3_HSTADDRP8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp = (tmp & USBHS_HSTADDR3_HSTADDRP8_Msk) >> USBHS_HSTADDR3_HSTADDRP8_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR3_HSTADDRP9_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 |= USBHS_HSTADDR3_HSTADDRP9(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_get_HSTADDR3_HSTADDRP9_bf(const void *const hw, + hri_usbhs_hstaddr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp = (tmp & USBHS_HSTADDR3_HSTADDRP9(mask)) >> USBHS_HSTADDR3_HSTADDRP9_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR3_HSTADDRP9_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp &= ~USBHS_HSTADDR3_HSTADDRP9_Msk; + tmp |= USBHS_HSTADDR3_HSTADDRP9(data); + ((Usbhs *)hw)->USBHS_HSTADDR3 = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR3_HSTADDRP9_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 &= ~USBHS_HSTADDR3_HSTADDRP9(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR3_HSTADDRP9_bf(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 ^= USBHS_HSTADDR3_HSTADDRP9(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_read_HSTADDR3_HSTADDRP9_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp = (tmp & USBHS_HSTADDR3_HSTADDRP9_Msk) >> USBHS_HSTADDR3_HSTADDRP9_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTADDR3_reg(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_get_HSTADDR3_reg(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTADDR3; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTADDR3_reg(const void *const hw, hri_usbhs_hstaddr3_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTADDR3_reg(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTADDR3_reg(const void *const hw, hri_usbhs_hstaddr3_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTADDR3 ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstaddr3_reg_t hri_usbhs_read_HSTADDR3_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_HSTADDR3; +} + +static inline void hri_usbhs_set_HSTPIPCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_ALLOC) >> USBHS_HSTPIPCFG_ALLOC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_ALLOC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_ALLOC; + tmp |= value << USBHS_HSTPIPCFG_ALLOC_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_ALLOC_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_ALLOC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_AUTOSW) >> USBHS_HSTPIPCFG_AUTOSW_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_AUTOSW_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_AUTOSW; + tmp |= value << USBHS_HSTPIPCFG_AUTOSW_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_AUTOSW_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_AUTOSW; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPCFG_CTRL_BULK_PINGEN_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_CTRL_BULK_PINGEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPCFG_CTRL_BULK_PINGEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_CTRL_BULK_PINGEN) >> USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_CTRL_BULK_PINGEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_CTRL_BULK_PINGEN; + tmp |= value << USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_CTRL_BULK_PINGEN_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_CTRL_BULK_PINGEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_CTRL_BULK_PINGEN_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_CTRL_BULK_PINGEN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_PBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PBK(mask)) >> USBHS_HSTPIPCFG_PBK_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_PBK_Msk; + tmp |= USBHS_HSTPIPCFG_PBK(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_PBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_PBK(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_PBK_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PBK_Msk) >> USBHS_HSTPIPCFG_PBK_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_PSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PSIZE(mask)) >> USBHS_HSTPIPCFG_PSIZE_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_PSIZE_Msk; + tmp |= USBHS_HSTPIPCFG_PSIZE(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_PSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_PSIZE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_PSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PSIZE_Msk) >> USBHS_HSTPIPCFG_PSIZE_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_PTOKEN(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PTOKEN(mask)) >> USBHS_HSTPIPCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_PTOKEN_Msk; + tmp |= USBHS_HSTPIPCFG_PTOKEN(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_PTOKEN(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_PTOKEN(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_PTOKEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PTOKEN_Msk) >> USBHS_HSTPIPCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_PTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PTYPE(mask)) >> USBHS_HSTPIPCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_PTYPE_Msk; + tmp |= USBHS_HSTPIPCFG_PTYPE(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_PTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_PTYPE(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_PTYPE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PTYPE_Msk) >> USBHS_HSTPIPCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_PEPNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PEPNUM(mask)) >> USBHS_HSTPIPCFG_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_PEPNUM_Msk; + tmp |= USBHS_HSTPIPCFG_PEPNUM(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_PEPNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_PEPNUM(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_PEPNUM_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_INTFRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_INTFRQ(mask)) >> USBHS_HSTPIPCFG_INTFRQ_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_INTFRQ_Msk; + tmp |= USBHS_HSTPIPCFG_INTFRQ(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_INTFRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_INTFRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_INTFRQ_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_INTFRQ_Msk) >> USBHS_HSTPIPCFG_INTFRQ_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t +hri_usbhs_get_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(mask)) >> USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= ~USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk; + tmp |= USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(data); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_CTRL_BULK_BINTERVAL_bf(const void *const hw, + uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp = (tmp & USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk) >> USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPCFG_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_get_HSTPIPCFG_reg(const void *const hw, uint8_t index, + hri_usbhs_hstpipcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPCFG_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPCFG_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPCFG_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipcfg_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPCFG[index] ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipcfg_reg_t hri_usbhs_read_HSTPIPCFG_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_HSTPIPCFG[index]; +} + +static inline void hri_usbhs_set_HSTPIPINRQ_INMODE_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] |= USBHS_HSTPIPINRQ_INMODE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPINRQ_INMODE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp = (tmp & USBHS_HSTPIPINRQ_INMODE) >> USBHS_HSTPIPINRQ_INMODE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPINRQ_INMODE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp &= ~USBHS_HSTPIPINRQ_INMODE; + tmp |= value << USBHS_HSTPIPINRQ_INMODE_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPINRQ_INMODE_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] &= ~USBHS_HSTPIPINRQ_INMODE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPINRQ_INMODE_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] ^= USBHS_HSTPIPINRQ_INMODE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] |= USBHS_HSTPIPINRQ_INRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipinrq_reg_t hri_usbhs_get_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp = (tmp & USBHS_HSTPIPINRQ_INRQ(mask)) >> USBHS_HSTPIPINRQ_INRQ_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp &= ~USBHS_HSTPIPINRQ_INRQ_Msk; + tmp |= USBHS_HSTPIPINRQ_INRQ(data); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] &= ~USBHS_HSTPIPINRQ_INRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] ^= USBHS_HSTPIPINRQ_INRQ(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipinrq_reg_t hri_usbhs_read_HSTPIPINRQ_INRQ_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp = (tmp & USBHS_HSTPIPINRQ_INRQ_Msk) >> USBHS_HSTPIPINRQ_INRQ_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPINRQ_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipinrq_reg_t hri_usbhs_get_HSTPIPINRQ_reg(const void *const hw, uint8_t index, + hri_usbhs_hstpipinrq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPINRQ_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipinrq_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPINRQ_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPINRQ_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipinrq_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index] ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpipinrq_reg_t hri_usbhs_read_HSTPIPINRQ_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_HSTPIPINRQ[index]; +} + +static inline void hri_usbhs_set_HSTPIPERR_DATATGL_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_DATATGL; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPERR_DATATGL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_DATATGL) >> USBHS_HSTPIPERR_DATATGL_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_DATATGL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_DATATGL; + tmp |= value << USBHS_HSTPIPERR_DATATGL_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_DATATGL_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_DATATGL; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_DATATGL_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_DATATGL; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPERR_DATAPID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_DATAPID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPERR_DATAPID_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_DATAPID) >> USBHS_HSTPIPERR_DATAPID_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_DATAPID_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_DATAPID; + tmp |= value << USBHS_HSTPIPERR_DATAPID_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_DATAPID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_DATAPID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_DATAPID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_DATAPID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPERR_PID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_PID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPERR_PID_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_PID) >> USBHS_HSTPIPERR_PID_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_PID_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_PID; + tmp |= value << USBHS_HSTPIPERR_PID_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_PID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_PID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_PID_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_PID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPERR_TIMEOUT_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_TIMEOUT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPERR_TIMEOUT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_TIMEOUT) >> USBHS_HSTPIPERR_TIMEOUT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_TIMEOUT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_TIMEOUT; + tmp |= value << USBHS_HSTPIPERR_TIMEOUT_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_TIMEOUT_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_TIMEOUT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_TIMEOUT_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_TIMEOUT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPERR_CRC16_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_CRC16; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTPIPERR_CRC16_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_CRC16) >> USBHS_HSTPIPERR_CRC16_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_CRC16_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_CRC16; + tmp |= value << USBHS_HSTPIPERR_CRC16_Pos; + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_CRC16_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_CRC16; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_CRC16_bit(const void *const hw, uint8_t index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_CRC16; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= USBHS_HSTPIPERR_COUNTER(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpiperr_reg_t hri_usbhs_get_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_COUNTER(mask)) >> USBHS_HSTPIPERR_COUNTER_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= ~USBHS_HSTPIPERR_COUNTER_Msk; + tmp |= USBHS_HSTPIPERR_COUNTER(data); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~USBHS_HSTPIPERR_COUNTER(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= USBHS_HSTPIPERR_COUNTER(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpiperr_reg_t hri_usbhs_read_HSTPIPERR_COUNTER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp = (tmp & USBHS_HSTPIPERR_COUNTER_Msk) >> USBHS_HSTPIPERR_COUNTER_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTPIPERR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpiperr_reg_t hri_usbhs_get_HSTPIPERR_reg(const void *const hw, uint8_t index, + hri_usbhs_hstpiperr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTPIPERR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpiperr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTPIPERR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTPIPERR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpiperr_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPERR[index] ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstpiperr_reg_t hri_usbhs_read_HSTPIPERR_reg(const void *const hw, uint8_t index) +{ + return ((Usbhs *)hw)->USBHS_HSTPIPERR[index]; +} + +static inline void hri_usbhs_set_CTRL_RDERRE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_RDERRE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_RDERRE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_RDERRE) >> USBHS_CTRL_RDERRE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_RDERRE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_RDERRE; + tmp |= value << USBHS_CTRL_RDERRE_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_RDERRE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_RDERRE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_RDERRE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_RDERRE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_VBUSHWC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_VBUSHWC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_VBUSHWC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_VBUSHWC) >> USBHS_CTRL_VBUSHWC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_VBUSHWC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_VBUSHWC; + tmp |= value << USBHS_CTRL_VBUSHWC_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_VBUSHWC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_VBUSHWC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_VBUSHWC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_VBUSHWC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_FRZCLK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_FRZCLK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_FRZCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_FRZCLK) >> USBHS_CTRL_FRZCLK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_FRZCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_FRZCLK; + tmp |= value << USBHS_CTRL_FRZCLK_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_FRZCLK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_FRZCLK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_FRZCLK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_USBE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_USBE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_USBE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_USBE) >> USBHS_CTRL_USBE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_USBE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_USBE; + tmp |= value << USBHS_CTRL_USBE_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_USBE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_USBE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_USBE_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_USBE; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_UID_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_UID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_UID_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_UID) >> USBHS_CTRL_UID_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_UID_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_UID; + tmp |= value << USBHS_CTRL_UID_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_UID_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_UID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_UID_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_UID; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_UIMOD_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= USBHS_CTRL_UIMOD; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_CTRL_UIMOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp = (tmp & USBHS_CTRL_UIMOD) >> USBHS_CTRL_UIMOD_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_CTRL_UIMOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= ~USBHS_CTRL_UIMOD; + tmp |= value << USBHS_CTRL_UIMOD_Pos; + ((Usbhs *)hw)->USBHS_CTRL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_UIMOD_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~USBHS_CTRL_UIMOD; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_UIMOD_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= USBHS_CTRL_UIMOD; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_CTRL_reg(const void *const hw, hri_usbhs_ctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_ctrl_reg_t hri_usbhs_get_CTRL_reg(const void *const hw, hri_usbhs_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->USBHS_CTRL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_CTRL_reg(const void *const hw, hri_usbhs_ctrl_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_CTRL_reg(const void *const hw, hri_usbhs_ctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_CTRL_reg(const void *const hw, hri_usbhs_ctrl_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_CTRL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_ctrl_reg_t hri_usbhs_read_CTRL_reg(const void *const hw) +{ + return ((Usbhs *)hw)->USBHS_CTRL; +} + +static inline void hri_usbhs_write_DEVICR_reg(const void *const hw, hri_usbhs_devicr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVICR = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_DEVIFR_reg(const void *const hw, hri_usbhs_devifr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVIFR = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_DEVEPTIFR_reg(const void *const hw, uint8_t index, hri_usbhs_deveptifr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTIFR[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_DEVEPTIER_reg(const void *const hw, uint8_t index, hri_usbhs_deveptier_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTIER[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_DEVEPTIDR_reg(const void *const hw, uint8_t index, hri_usbhs_deveptidr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_DEVEPTIDR[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_HSTICR_reg(const void *const hw, hri_usbhs_hsticr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTICR = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_HSTIFR_reg(const void *const hw, hri_usbhs_hstifr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTIFR = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_HSTPIPIFR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipifr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPIFR[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_HSTPIPIER_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipier_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPIER[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_HSTPIPIDR_reg(const void *const hw, uint8_t index, hri_usbhs_hstpipidr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_HSTPIPIDR[index] = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_write_SFR_reg(const void *const hw, hri_usbhs_sfr_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->USBHS_SFR = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC |= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t +hri_usbhsdevdma_get_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, hri_usbhs_devdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC; + tmp = (tmp & USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask)) >> USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_devdmanxtdsc_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC; + tmp &= ~USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk; + tmp |= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(data); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC &= ~USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC ^= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhsdevdma_read_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC; + tmp = (tmp & USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk) >> USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_set_DEVDMANXTDSC_reg(const void *const hw, hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhsdevdma_get_DEVDMANXTDSC_reg(const void *const hw, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMANXTDSC_reg(const void *const hw, hri_usbhs_devdmanxtdsc_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMANXTDSC_reg(const void *const hw, hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMANXTDSC_reg(const void *const hw, hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhsdevdma_read_DEVDMANXTDSC_reg(const void *const hw) +{ + return ((UsbhsDevdma *)hw)->USBHS_DEVDMANXTDSC; +} + +static inline void hri_usbhsdevdma_set_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS |= USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t +hri_usbhsdevdma_get_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, hri_usbhs_devdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS; + tmp = (tmp & USBHS_DEVDMAADDRESS_BUFF_ADD(mask)) >> USBHS_DEVDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_devdmaaddress_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS; + tmp &= ~USBHS_DEVDMAADDRESS_BUFF_ADD_Msk; + tmp |= USBHS_DEVDMAADDRESS_BUFF_ADD(data); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS &= ~USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS ^= USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhsdevdma_read_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS; + tmp = (tmp & USBHS_DEVDMAADDRESS_BUFF_ADD_Msk) >> USBHS_DEVDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_set_DEVDMAADDRESS_reg(const void *const hw, hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhsdevdma_get_DEVDMAADDRESS_reg(const void *const hw, + hri_usbhs_devdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMAADDRESS_reg(const void *const hw, hri_usbhs_devdmaaddress_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMAADDRESS_reg(const void *const hw, hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMAADDRESS_reg(const void *const hw, hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhsdevdma_read_DEVDMAADDRESS_reg(const void *const hw) +{ + return ((UsbhsDevdma *)hw)->USBHS_DEVDMAADDRESS; +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_CHANN_ENB) >> USBHS_DEVDMACONTROL_CHANN_ENB_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_CHANN_ENB; + tmp |= value << USBHS_DEVDMACONTROL_CHANN_ENB_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_LDNXT_DSC) >> USBHS_DEVDMACONTROL_LDNXT_DSC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_LDNXT_DSC; + tmp |= value << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_TR_EN) >> USBHS_DEVDMACONTROL_END_TR_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_TR_EN; + tmp |= value << USBHS_DEVDMACONTROL_END_TR_EN_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_END_B_EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_B_EN) >> USBHS_DEVDMACONTROL_END_B_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_END_B_EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_B_EN; + tmp |= value << USBHS_DEVDMACONTROL_END_B_EN_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_TR_IT) >> USBHS_DEVDMACONTROL_END_TR_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_TR_IT; + tmp |= value << USBHS_DEVDMACONTROL_END_TR_IT_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_BUFFIT) >> USBHS_DEVDMACONTROL_END_BUFFIT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_BUFFIT; + tmp |= value << USBHS_DEVDMACONTROL_END_BUFFIT_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_DESC_LD_IT) >> USBHS_DEVDMACONTROL_DESC_LD_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_DESC_LD_IT; + tmp |= value << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BURST_LCK) >> USBHS_DEVDMACONTROL_BURST_LCK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_BURST_LCK; + tmp |= value << USBHS_DEVDMACONTROL_BURST_LCK_Pos; + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t +hri_usbhsdevdma_get_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, hri_usbhs_devdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BUFF_LENGTH(mask)) >> USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_devdmacontrol_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk; + tmp |= USBHS_DEVDMACONTROL_BUFF_LENGTH(data); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t hri_usbhsdevdma_read_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk) >> USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhsdevdma_set_DEVDMACONTROL_reg(const void *const hw, hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t hri_usbhsdevdma_get_DEVDMACONTROL_reg(const void *const hw, + hri_usbhs_devdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhsdevdma_write_DEVDMACONTROL_reg(const void *const hw, hri_usbhs_devdmacontrol_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_clear_DEVDMACONTROL_reg(const void *const hw, hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhsdevdma_toggle_DEVDMACONTROL_reg(const void *const hw, hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t hri_usbhsdevdma_read_DEVDMACONTROL_reg(const void *const hw) +{ + return ((UsbhsDevdma *)hw)->USBHS_DEVDMACONTROL; +} + +static inline bool hri_usbhsdevdma_get_DEVDMASTATUS_CHANN_ENB_bit(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_CHANN_ENB) >> USBHS_DEVDMASTATUS_CHANN_ENB_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMASTATUS_CHANN_ACT_bit(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_CHANN_ACT) >> USBHS_DEVDMASTATUS_CHANN_ACT_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_CHANN_ACT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_CHANN_ACT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMASTATUS_END_TR_ST_bit(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST) >> USBHS_DEVDMASTATUS_END_TR_ST_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_END_TR_ST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_END_TR_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMASTATUS_END_BF_ST_bit(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_BF_ST) >> USBHS_DEVDMASTATUS_END_BF_ST_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_END_BF_ST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_END_BF_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhsdevdma_get_DEVDMASTATUS_DESC_LDST_bit(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_DESC_LDST) >> USBHS_DEVDMASTATUS_DESC_LDST_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_DESC_LDST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_DESC_LDST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t +hri_usbhsdevdma_get_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw, hri_usbhs_devdmastatus_reg_t mask) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT(mask)) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw, + hri_usbhs_devdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_BUFF_COUNT(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhsdevdma_read_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw) +{ + return (((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhsdevdma_get_DEVDMASTATUS_reg(const void *const hw, + hri_usbhs_devdmastatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhsdevdma_clear_DEVDMASTATUS_reg(const void *const hw, hri_usbhs_devdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS = mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhsdevdma_read_DEVDMASTATUS_reg(const void *const hw) +{ + return ((UsbhsDevdma *)hw)->USBHS_DEVDMASTATUS; +} + +static inline void hri_usbhs_set_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC |= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhs_get_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC; + tmp = (tmp & USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask)) >> USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC; + tmp &= ~USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk; + tmp |= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(data); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC &= ~USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC ^= USBHS_DEVDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhs_read_DEVDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC; + tmp = (tmp & USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk) >> USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhs_get_DEVDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmanxtdsc_reg_t hri_usbhs_read_DEVDMANXTDSC_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMANXTDSC; +} + +static inline void hri_usbhs_set_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS |= USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhs_get_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS; + tmp = (tmp & USBHS_DEVDMAADDRESS_BUFF_ADD(mask)) >> USBHS_DEVDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS; + tmp &= ~USBHS_DEVDMAADDRESS_BUFF_ADD_Msk; + tmp |= USBHS_DEVDMAADDRESS_BUFF_ADD(data); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS &= ~USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS ^= USBHS_DEVDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhs_read_DEVDMAADDRESS_BUFF_ADD_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS; + tmp = (tmp & USBHS_DEVDMAADDRESS_BUFF_ADD_Msk) >> USBHS_DEVDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t +hri_usbhs_get_DEVDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, hri_usbhs_devdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmaaddress_reg_t hri_usbhs_read_DEVDMAADDRESS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMAADDRESS; +} + +static inline void hri_usbhs_set_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_CHANN_ENB) >> USBHS_DEVDMACONTROL_CHANN_ENB_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_CHANN_ENB; + tmp |= value << USBHS_DEVDMACONTROL_CHANN_ENB_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_LDNXT_DSC) >> USBHS_DEVDMACONTROL_LDNXT_DSC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_LDNXT_DSC; + tmp |= value << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_TR_EN) >> USBHS_DEVDMACONTROL_END_TR_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_TR_EN; + tmp |= value << USBHS_DEVDMACONTROL_END_TR_EN_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_B_EN) >> USBHS_DEVDMACONTROL_END_B_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_B_EN; + tmp |= value << USBHS_DEVDMACONTROL_END_B_EN_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_TR_IT) >> USBHS_DEVDMACONTROL_END_TR_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_TR_IT; + tmp |= value << USBHS_DEVDMACONTROL_END_TR_IT_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_END_BUFFIT) >> USBHS_DEVDMACONTROL_END_BUFFIT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_END_BUFFIT; + tmp |= value << USBHS_DEVDMACONTROL_END_BUFFIT_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_DESC_LD_IT) >> USBHS_DEVDMACONTROL_DESC_LD_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_DESC_LD_IT; + tmp |= value << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BURST_LCK) >> USBHS_DEVDMACONTROL_BURST_LCK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_BURST_LCK; + tmp |= value << USBHS_DEVDMACONTROL_BURST_LCK_Pos; + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t +hri_usbhs_get_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BUFF_LENGTH(mask)) >> USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= ~USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk; + tmp |= USBHS_DEVDMACONTROL_BUFF_LENGTH(data); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= USBHS_DEVDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t hri_usbhs_read_DEVDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp = (tmp & USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk) >> USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhs_set_DEVDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t +hri_usbhs_get_DEVDMACONTROL_reg(const void *const hw, uint8_t submodule_index, hri_usbhs_devdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_DEVDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_DEVDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_DEVDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmacontrol_reg_t hri_usbhs_read_DEVDMACONTROL_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMACONTROL; +} + +static inline bool hri_usbhs_get_DEVDMASTATUS_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_CHANN_ENB) + >> USBHS_DEVDMASTATUS_CHANN_ENB_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMASTATUS_CHANN_ACT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_CHANN_ACT) + >> USBHS_DEVDMASTATUS_CHANN_ACT_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_CHANN_ACT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_CHANN_ACT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMASTATUS_END_TR_ST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST) + >> USBHS_DEVDMASTATUS_END_TR_ST_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_END_TR_ST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_END_TR_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMASTATUS_END_BF_ST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_BF_ST) + >> USBHS_DEVDMASTATUS_END_BF_ST_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_END_BF_ST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_END_BF_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_DEVDMASTATUS_DESC_LDST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_DESC_LDST) + >> USBHS_DEVDMASTATUS_DESC_LDST_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_DESC_LDST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_DESC_LDST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhs_get_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_devdmastatus_reg_t mask) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT(mask)) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = USBHS_DEVDMASTATUS_BUFF_COUNT(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhs_read_DEVDMASTATUS_BUFF_COUNT_bf(const void *const hw, + uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhs_get_DEVDMASTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmastatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_clear_DEVDMASTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_devdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS = mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_devdmastatus_reg_t hri_usbhs_read_DEVDMASTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsDevdma[submodule_index].USBHS_DEVDMASTATUS; +} + +static inline void hri_usbhshstdma_set_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC |= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t +hri_usbhshstdma_get_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC; + tmp = (tmp & USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask)) >> USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_hstdmanxtdsc_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC; + tmp &= ~USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk; + tmp |= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(data); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC &= ~USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC ^= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhshstdma_read_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC; + tmp = (tmp & USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk) >> USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_set_HSTDMANXTDSC_reg(const void *const hw, hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhshstdma_get_HSTDMANXTDSC_reg(const void *const hw, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMANXTDSC_reg(const void *const hw, hri_usbhs_hstdmanxtdsc_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMANXTDSC_reg(const void *const hw, hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMANXTDSC_reg(const void *const hw, hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhshstdma_read_HSTDMANXTDSC_reg(const void *const hw) +{ + return ((UsbhsHstdma *)hw)->USBHS_HSTDMANXTDSC; +} + +static inline void hri_usbhshstdma_set_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS |= USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t +hri_usbhshstdma_get_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, hri_usbhs_hstdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS; + tmp = (tmp & USBHS_HSTDMAADDRESS_BUFF_ADD(mask)) >> USBHS_HSTDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_hstdmaaddress_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS; + tmp &= ~USBHS_HSTDMAADDRESS_BUFF_ADD_Msk; + tmp |= USBHS_HSTDMAADDRESS_BUFF_ADD(data); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS &= ~USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS ^= USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhshstdma_read_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS; + tmp = (tmp & USBHS_HSTDMAADDRESS_BUFF_ADD_Msk) >> USBHS_HSTDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_set_HSTDMAADDRESS_reg(const void *const hw, hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhshstdma_get_HSTDMAADDRESS_reg(const void *const hw, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMAADDRESS_reg(const void *const hw, hri_usbhs_hstdmaaddress_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMAADDRESS_reg(const void *const hw, hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMAADDRESS_reg(const void *const hw, hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhshstdma_read_HSTDMAADDRESS_reg(const void *const hw) +{ + return ((UsbhsHstdma *)hw)->USBHS_HSTDMAADDRESS; +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_CHANN_ENB) >> USBHS_HSTDMACONTROL_CHANN_ENB_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_CHANN_ENB; + tmp |= value << USBHS_HSTDMACONTROL_CHANN_ENB_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_LDNXT_DSC) >> USBHS_HSTDMACONTROL_LDNXT_DSC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_LDNXT_DSC; + tmp |= value << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_TR_EN) >> USBHS_HSTDMACONTROL_END_TR_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_TR_EN; + tmp |= value << USBHS_HSTDMACONTROL_END_TR_EN_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_END_TR_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_END_B_EN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_B_EN) >> USBHS_HSTDMACONTROL_END_B_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_END_B_EN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_B_EN; + tmp |= value << USBHS_HSTDMACONTROL_END_B_EN_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_END_B_EN_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_TR_IT) >> USBHS_HSTDMACONTROL_END_TR_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_TR_IT; + tmp |= value << USBHS_HSTDMACONTROL_END_TR_IT_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_END_TR_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_BUFFIT) >> USBHS_HSTDMACONTROL_END_BUFFIT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_BUFFIT; + tmp |= value << USBHS_HSTDMACONTROL_END_BUFFIT_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_DESC_LD_IT) >> USBHS_HSTDMACONTROL_DESC_LD_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_DESC_LD_IT; + tmp |= value << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BURST_LCK) >> USBHS_HSTDMACONTROL_BURST_LCK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_BURST_LCK; + tmp |= value << USBHS_HSTDMACONTROL_BURST_LCK_Pos; + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_BURST_LCK_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t +hri_usbhshstdma_get_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, hri_usbhs_hstdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BUFF_LENGTH(mask)) >> USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_hstdmacontrol_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk; + tmp |= USBHS_HSTDMACONTROL_BUFF_LENGTH(data); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t hri_usbhshstdma_read_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk) >> USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhshstdma_set_HSTDMACONTROL_reg(const void *const hw, hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t hri_usbhshstdma_get_HSTDMACONTROL_reg(const void *const hw, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhshstdma_write_HSTDMACONTROL_reg(const void *const hw, hri_usbhs_hstdmacontrol_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_clear_HSTDMACONTROL_reg(const void *const hw, hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhshstdma_toggle_HSTDMACONTROL_reg(const void *const hw, hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t hri_usbhshstdma_read_HSTDMACONTROL_reg(const void *const hw) +{ + return ((UsbhsHstdma *)hw)->USBHS_HSTDMACONTROL; +} + +static inline bool hri_usbhshstdma_get_HSTDMASTATUS_CHANN_ENB_bit(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_CHANN_ENB) >> USBHS_HSTDMASTATUS_CHANN_ENB_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_CHANN_ENB_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMASTATUS_CHANN_ACT_bit(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_CHANN_ACT) >> USBHS_HSTDMASTATUS_CHANN_ACT_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_CHANN_ACT_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_CHANN_ACT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMASTATUS_END_TR_ST_bit(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_END_TR_ST) >> USBHS_HSTDMASTATUS_END_TR_ST_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_END_TR_ST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_END_TR_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMASTATUS_END_BF_ST_bit(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_END_BF_ST) >> USBHS_HSTDMASTATUS_END_BF_ST_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_END_BF_ST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_END_BF_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhshstdma_get_HSTDMASTATUS_DESC_LDST_bit(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_DESC_LDST) >> USBHS_HSTDMASTATUS_DESC_LDST_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_DESC_LDST_bit(const void *const hw) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_DESC_LDST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t +hri_usbhshstdma_get_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw, hri_usbhs_hstdmastatus_reg_t mask) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_BUFF_COUNT(mask)) + >> USBHS_HSTDMASTATUS_BUFF_COUNT_Pos; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw, + hri_usbhs_hstdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_BUFF_COUNT(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhshstdma_read_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw) +{ + return (((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_HSTDMASTATUS_BUFF_COUNT_Pos; +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhshstdma_get_HSTDMASTATUS_reg(const void *const hw, + hri_usbhs_hstdmastatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhshstdma_clear_HSTDMASTATUS_reg(const void *const hw, hri_usbhs_hstdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS = mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhshstdma_read_HSTDMASTATUS_reg(const void *const hw) +{ + return ((UsbhsHstdma *)hw)->USBHS_HSTDMASTATUS; +} + +static inline void hri_usbhs_set_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC |= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhs_get_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC; + tmp = (tmp & USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask)) >> USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC; + tmp &= ~USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk; + tmp |= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(data); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC &= ~USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC ^= USBHS_HSTDMANXTDSC_NXT_DSC_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhs_read_HSTDMANXTDSC_NXT_DSC_ADD_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC; + tmp = (tmp & USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk) >> USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhs_get_HSTDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMANXTDSC_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmanxtdsc_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmanxtdsc_reg_t hri_usbhs_read_HSTDMANXTDSC_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMANXTDSC; +} + +static inline void hri_usbhs_set_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS |= USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhs_get_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS; + tmp = (tmp & USBHS_HSTDMAADDRESS_BUFF_ADD(mask)) >> USBHS_HSTDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS; + tmp &= ~USBHS_HSTDMAADDRESS_BUFF_ADD_Msk; + tmp |= USBHS_HSTDMAADDRESS_BUFF_ADD(data); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS &= ~USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS ^= USBHS_HSTDMAADDRESS_BUFF_ADD(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhs_read_HSTDMAADDRESS_BUFF_ADD_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS; + tmp = (tmp & USBHS_HSTDMAADDRESS_BUFF_ADD_Msk) >> USBHS_HSTDMAADDRESS_BUFF_ADD_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t +hri_usbhs_get_HSTDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, hri_usbhs_hstdmaaddress_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMAADDRESS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmaaddress_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmaaddress_reg_t hri_usbhs_read_HSTDMAADDRESS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMAADDRESS; +} + +static inline void hri_usbhs_set_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_CHANN_ENB) >> USBHS_HSTDMACONTROL_CHANN_ENB_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_CHANN_ENB; + tmp |= value << USBHS_HSTDMACONTROL_CHANN_ENB_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_LDNXT_DSC) >> USBHS_HSTDMACONTROL_LDNXT_DSC_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_LDNXT_DSC; + tmp |= value << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_LDNXT_DSC_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_LDNXT_DSC; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_TR_EN) >> USBHS_HSTDMACONTROL_END_TR_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_TR_EN; + tmp |= value << USBHS_HSTDMACONTROL_END_TR_EN_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_END_TR_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_TR_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_B_EN) >> USBHS_HSTDMACONTROL_END_B_EN_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_B_EN; + tmp |= value << USBHS_HSTDMACONTROL_END_B_EN_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_END_B_EN_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_B_EN; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_TR_IT) >> USBHS_HSTDMACONTROL_END_TR_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_TR_IT; + tmp |= value << USBHS_HSTDMACONTROL_END_TR_IT_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_END_TR_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_TR_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_END_BUFFIT) >> USBHS_HSTDMACONTROL_END_BUFFIT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_END_BUFFIT; + tmp |= value << USBHS_HSTDMACONTROL_END_BUFFIT_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_END_BUFFIT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_END_BUFFIT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_DESC_LD_IT) >> USBHS_HSTDMACONTROL_DESC_LD_IT_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_DESC_LD_IT; + tmp |= value << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_DESC_LD_IT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_DESC_LD_IT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BURST_LCK) >> USBHS_HSTDMACONTROL_BURST_LCK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_BURST_LCK; + tmp |= value << USBHS_HSTDMACONTROL_BURST_LCK_Pos; + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_BURST_LCK_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_BURST_LCK; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_set_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t +hri_usbhs_get_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BUFF_LENGTH(mask)) >> USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t data) +{ + uint32_t tmp; + USBHS_CRITICAL_SECTION_ENTER(); + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= ~USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk; + tmp |= USBHS_HSTDMACONTROL_BUFF_LENGTH(data); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = tmp; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= USBHS_HSTDMACONTROL_BUFF_LENGTH(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t hri_usbhs_read_HSTDMACONTROL_BUFF_LENGTH_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp = (tmp & USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk) >> USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos; + return tmp; +} + +static inline void hri_usbhs_set_HSTDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL |= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t +hri_usbhs_get_HSTDMACONTROL_reg(const void *const hw, uint8_t submodule_index, hri_usbhs_hstdmacontrol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_write_HSTDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t data) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL = data; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_clear_HSTDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL &= ~mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhs_toggle_HSTDMACONTROL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmacontrol_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL ^= mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmacontrol_reg_t hri_usbhs_read_HSTDMACONTROL_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMACONTROL; +} + +static inline bool hri_usbhs_get_HSTDMASTATUS_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_CHANN_ENB) + >> USBHS_HSTDMASTATUS_CHANN_ENB_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_CHANN_ENB_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_CHANN_ENB; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMASTATUS_CHANN_ACT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_CHANN_ACT) + >> USBHS_HSTDMASTATUS_CHANN_ACT_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_CHANN_ACT_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_CHANN_ACT; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMASTATUS_END_TR_ST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_END_TR_ST) + >> USBHS_HSTDMASTATUS_END_TR_ST_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_END_TR_ST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_END_TR_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMASTATUS_END_BF_ST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_END_BF_ST) + >> USBHS_HSTDMASTATUS_END_BF_ST_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_END_BF_ST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_END_BF_ST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhs_get_HSTDMASTATUS_DESC_LDST_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_DESC_LDST) + >> USBHS_HSTDMASTATUS_DESC_LDST_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_DESC_LDST_bit(const void *const hw, uint8_t submodule_index) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_DESC_LDST; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhs_get_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhs_hstdmastatus_reg_t mask) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_BUFF_COUNT(mask)) + >> USBHS_HSTDMASTATUS_BUFF_COUNT_Pos; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = USBHS_HSTDMASTATUS_BUFF_COUNT(mask); + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhs_read_HSTDMASTATUS_BUFF_COUNT_bf(const void *const hw, + uint8_t submodule_index) +{ + return (((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS & USBHS_HSTDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_HSTDMASTATUS_BUFF_COUNT_Pos; +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhs_get_HSTDMASTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmastatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhs_clear_HSTDMASTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhs_hstdmastatus_reg_t mask) +{ + USBHS_CRITICAL_SECTION_ENTER(); + ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS = mask; + USBHS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhs_hstdmastatus_reg_t hri_usbhs_read_HSTDMASTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usbhs *)hw)->UsbhsHstdma[submodule_index].USBHS_HSTDMASTATUS; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbhs_get_DEVEPTISR_RXSTPI_bit(a, b) hri_usbhs_get_DEVEPTISR_CTRL_RXSTPI_bit(a, b) +#define hri_usbhs_clear_DEVEPTISR_RXSTPI_bit(a, b) hri_usbhs_clear_DEVEPTISR_CTRL_RXSTPI_bit(a, b) +#define hri_usbhs_get_DEVEPTISR_NAKOUTI_bit(a, b) hri_usbhs_get_DEVEPTISR_CTRL_NAKOUTI_bit(a, b) +#define hri_usbhs_clear_DEVEPTISR_NAKOUTI_bit(a, b) hri_usbhs_clear_DEVEPTISR_CTRL_NAKOUTI_bit(a, b) +#define hri_usbhs_get_DEVEPTISR_NAKINI_bit(a, b) hri_usbhs_get_DEVEPTISR_CTRL_NAKINI_bit(a, b) +#define hri_usbhs_clear_DEVEPTISR_NAKINI_bit(a, b) hri_usbhs_clear_DEVEPTISR_CTRL_NAKINI_bit(a, b) +#define hri_usbhs_get_DEVEPTISR_STALLEDI_bit(a, b) hri_usbhs_get_DEVEPTISR_CTRL_STALLEDI_bit(a, b) +#define hri_usbhs_clear_DEVEPTISR_STALLEDI_bit(a, b) hri_usbhs_clear_DEVEPTISR_CTRL_STALLEDI_bit(a, b) +#define hri_usbhs_get_DEVEPTISR_CTRLDIR_bit(a, b) hri_usbhs_get_DEVEPTISR_CTRL_CTRLDIR_bit(a, b) +#define hri_usbhs_get_HSTPIPISR_TXSTPI_bit(a, b) hri_usbhs_get_HSTPIPISR_CTRL_TXSTPI_bit(a, b) +#define hri_usbhs_clear_HSTPIPISR_TXSTPI_bit(a, b) hri_usbhs_clear_HSTPIPISR_CTRL_TXSTPI_bit(a, b) +#define hri_usbhs_get_HSTPIPISR_RXSTALLDI_bit(a, b) hri_usbhs_get_HSTPIPISR_CTRL_RXSTALLDI_bit(a, b) +#define hri_usbhs_clear_HSTPIPISR_RXSTALLDI_bit(a, b) hri_usbhs_clear_HSTPIPISR_CTRL_RXSTALLDI_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_RXSTPE_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_RXSTPE_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_NAKOUTE_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_NAKOUTE_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_NAKINE_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_NAKINE_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_STALLEDE_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_STALLEDE_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_NYETDIS_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_NYETDIS_bit(a, b) +#define hri_usbhs_get_DEVEPTIMR_STALLRQ_bit(a, b) hri_usbhs_get_DEVEPTIMR_CTRL_STALLRQ_bit(a, b) +#define hri_usbhs_get_HSTPIPIMR_TXSTPE_bit(a, b) hri_usbhs_get_HSTPIPIMR_CTRL_TXSTPE_bit(a, b) +#define hri_usbhs_get_HSTPIPIMR_RXSTALLDE_bit(a, b) hri_usbhs_get_HSTPIPIMR_CTRL_RXSTALLDE_bit(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USBHS_E70B_H_INCLUDED */ +#endif /* _SAME70_USBHS_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_utmi_e70b.h b/bsp/microchip/same70/bsp/hri/hri_utmi_e70b.h new file mode 100644 index 0000000000..6792d5268c --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_utmi_e70b.h @@ -0,0 +1,350 @@ +/** + * \file + * + * \brief SAM UTMI + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_UTMI_COMPONENT_ +#ifndef _HRI_UTMI_E70B_H_INCLUDED_ +#define _HRI_UTMI_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_UTMI_CRITICAL_SECTIONS) +#define UTMI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define UTMI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define UTMI_CRITICAL_SECTION_ENTER() +#define UTMI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_utmi_cktrim_reg_t; +typedef uint32_t hri_utmi_ohciicr_reg_t; + +static inline void hri_utmi_set_OHCIICR_RES0_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR |= UTMI_OHCIICR_RES0; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_utmi_get_OHCIICR_RES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp = (tmp & UTMI_OHCIICR_RES0) >> UTMI_OHCIICR_RES0_Pos; + return (bool)tmp; +} + +static inline void hri_utmi_write_OHCIICR_RES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UTMI_CRITICAL_SECTION_ENTER(); + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp &= ~UTMI_OHCIICR_RES0; + tmp |= value << UTMI_OHCIICR_RES0_Pos; + ((Utmi *)hw)->UTMI_OHCIICR = tmp; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_OHCIICR_RES0_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR &= ~UTMI_OHCIICR_RES0; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_OHCIICR_RES0_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR ^= UTMI_OHCIICR_RES0; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_set_OHCIICR_ARIE_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR |= UTMI_OHCIICR_ARIE; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_utmi_get_OHCIICR_ARIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp = (tmp & UTMI_OHCIICR_ARIE) >> UTMI_OHCIICR_ARIE_Pos; + return (bool)tmp; +} + +static inline void hri_utmi_write_OHCIICR_ARIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UTMI_CRITICAL_SECTION_ENTER(); + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp &= ~UTMI_OHCIICR_ARIE; + tmp |= value << UTMI_OHCIICR_ARIE_Pos; + ((Utmi *)hw)->UTMI_OHCIICR = tmp; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_OHCIICR_ARIE_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR &= ~UTMI_OHCIICR_ARIE; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_OHCIICR_ARIE_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR ^= UTMI_OHCIICR_ARIE; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_set_OHCIICR_APPSTART_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR |= UTMI_OHCIICR_APPSTART; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_utmi_get_OHCIICR_APPSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp = (tmp & UTMI_OHCIICR_APPSTART) >> UTMI_OHCIICR_APPSTART_Pos; + return (bool)tmp; +} + +static inline void hri_utmi_write_OHCIICR_APPSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UTMI_CRITICAL_SECTION_ENTER(); + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp &= ~UTMI_OHCIICR_APPSTART; + tmp |= value << UTMI_OHCIICR_APPSTART_Pos; + ((Utmi *)hw)->UTMI_OHCIICR = tmp; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_OHCIICR_APPSTART_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR &= ~UTMI_OHCIICR_APPSTART; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_OHCIICR_APPSTART_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR ^= UTMI_OHCIICR_APPSTART; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_set_OHCIICR_UDPPUDIS_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR |= UTMI_OHCIICR_UDPPUDIS; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_utmi_get_OHCIICR_UDPPUDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp = (tmp & UTMI_OHCIICR_UDPPUDIS) >> UTMI_OHCIICR_UDPPUDIS_Pos; + return (bool)tmp; +} + +static inline void hri_utmi_write_OHCIICR_UDPPUDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + UTMI_CRITICAL_SECTION_ENTER(); + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp &= ~UTMI_OHCIICR_UDPPUDIS; + tmp |= value << UTMI_OHCIICR_UDPPUDIS_Pos; + ((Utmi *)hw)->UTMI_OHCIICR = tmp; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_OHCIICR_UDPPUDIS_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR &= ~UTMI_OHCIICR_UDPPUDIS; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_OHCIICR_UDPPUDIS_bit(const void *const hw) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR ^= UTMI_OHCIICR_UDPPUDIS; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_set_OHCIICR_reg(const void *const hw, hri_utmi_ohciicr_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR |= mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_ohciicr_reg_t hri_utmi_get_OHCIICR_reg(const void *const hw, hri_utmi_ohciicr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_OHCIICR; + tmp &= mask; + return tmp; +} + +static inline void hri_utmi_write_OHCIICR_reg(const void *const hw, hri_utmi_ohciicr_reg_t data) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR = data; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_OHCIICR_reg(const void *const hw, hri_utmi_ohciicr_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR &= ~mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_OHCIICR_reg(const void *const hw, hri_utmi_ohciicr_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_OHCIICR ^= mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_ohciicr_reg_t hri_utmi_read_OHCIICR_reg(const void *const hw) +{ + return ((Utmi *)hw)->UTMI_OHCIICR; +} + +static inline void hri_utmi_set_CKTRIM_FREQ_bf(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM |= UTMI_CKTRIM_FREQ(mask); + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_cktrim_reg_t hri_utmi_get_CKTRIM_FREQ_bf(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_CKTRIM; + tmp = (tmp & UTMI_CKTRIM_FREQ(mask)) >> UTMI_CKTRIM_FREQ_Pos; + return tmp; +} + +static inline void hri_utmi_write_CKTRIM_FREQ_bf(const void *const hw, hri_utmi_cktrim_reg_t data) +{ + uint32_t tmp; + UTMI_CRITICAL_SECTION_ENTER(); + tmp = ((Utmi *)hw)->UTMI_CKTRIM; + tmp &= ~UTMI_CKTRIM_FREQ_Msk; + tmp |= UTMI_CKTRIM_FREQ(data); + ((Utmi *)hw)->UTMI_CKTRIM = tmp; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_CKTRIM_FREQ_bf(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM &= ~UTMI_CKTRIM_FREQ(mask); + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_CKTRIM_FREQ_bf(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM ^= UTMI_CKTRIM_FREQ(mask); + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_cktrim_reg_t hri_utmi_read_CKTRIM_FREQ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_CKTRIM; + tmp = (tmp & UTMI_CKTRIM_FREQ_Msk) >> UTMI_CKTRIM_FREQ_Pos; + return tmp; +} + +static inline void hri_utmi_set_CKTRIM_reg(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM |= mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_cktrim_reg_t hri_utmi_get_CKTRIM_reg(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + uint32_t tmp; + tmp = ((Utmi *)hw)->UTMI_CKTRIM; + tmp &= mask; + return tmp; +} + +static inline void hri_utmi_write_CKTRIM_reg(const void *const hw, hri_utmi_cktrim_reg_t data) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM = data; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_clear_CKTRIM_reg(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM &= ~mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_utmi_toggle_CKTRIM_reg(const void *const hw, hri_utmi_cktrim_reg_t mask) +{ + UTMI_CRITICAL_SECTION_ENTER(); + ((Utmi *)hw)->UTMI_CKTRIM ^= mask; + UTMI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_utmi_cktrim_reg_t hri_utmi_read_CKTRIM_reg(const void *const hw) +{ + return ((Utmi *)hw)->UTMI_CKTRIM; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_UTMI_E70B_H_INCLUDED */ +#endif /* _SAME70_UTMI_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_wdt_e70b.h b/bsp/microchip/same70/bsp/hri/hri_wdt_e70b.h new file mode 100644 index 0000000000..fd3cef092f --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_wdt_e70b.h @@ -0,0 +1,428 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifdef _SAME70_WDT_COMPONENT_ +#ifndef _HRI_WDT_E70B_H_INCLUDED_ +#define _HRI_WDT_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_cr_reg_t; +typedef uint32_t hri_wdt_mr_reg_t; +typedef uint32_t hri_wdt_sr_reg_t; + +static inline bool hri_wdt_get_SR_WDUNF_bit(const void *const hw) +{ + return (((Wdt *)hw)->WDT_SR & WDT_SR_WDUNF) > 0; +} + +static inline bool hri_wdt_get_SR_WDERR_bit(const void *const hw) +{ + return (((Wdt *)hw)->WDT_SR & WDT_SR_WDERR) > 0; +} + +static inline hri_wdt_sr_reg_t hri_wdt_get_SR_reg(const void *const hw, hri_wdt_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_SR; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_sr_reg_t hri_wdt_read_SR_reg(const void *const hw) +{ + return ((Wdt *)hw)->WDT_SR; +} + +static inline void hri_wdt_set_MR_WDFIEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDFIEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_MR_WDFIEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDFIEN) >> WDT_MR_WDFIEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_MR_WDFIEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDFIEN; + tmp |= value << WDT_MR_WDFIEN_Pos; + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDFIEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDFIEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDFIEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDFIEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_MR_WDRSTEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDRSTEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_MR_WDRSTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDRSTEN) >> WDT_MR_WDRSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_MR_WDRSTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDRSTEN; + tmp |= value << WDT_MR_WDRSTEN_Pos; + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDRSTEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDRSTEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDRSTEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDRSTEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_MR_WDDIS_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDDIS; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_MR_WDDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDDIS) >> WDT_MR_WDDIS_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_MR_WDDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDDIS; + tmp |= value << WDT_MR_WDDIS_Pos; + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDDIS_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDDIS; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDDIS_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDDIS; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_MR_WDDBGHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDDBGHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_MR_WDDBGHLT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDDBGHLT) >> WDT_MR_WDDBGHLT_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_MR_WDDBGHLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDDBGHLT; + tmp |= value << WDT_MR_WDDBGHLT_Pos; + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDDBGHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDDBGHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDDBGHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDDBGHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_MR_WDIDLEHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDIDLEHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_MR_WDIDLEHLT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDIDLEHLT) >> WDT_MR_WDIDLEHLT_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_MR_WDIDLEHLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDIDLEHLT; + tmp |= value << WDT_MR_WDIDLEHLT_Pos; + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDIDLEHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDIDLEHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDIDLEHLT_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDIDLEHLT; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_MR_WDV_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDV(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_get_MR_WDV_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDV(mask)) >> WDT_MR_WDV_Pos; + return tmp; +} + +static inline void hri_wdt_write_MR_WDV_bf(const void *const hw, hri_wdt_mr_reg_t data) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDV_Msk; + tmp |= WDT_MR_WDV(data); + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDV_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDV(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDV_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDV(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_read_MR_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDV_Msk) >> WDT_MR_WDV_Pos; + return tmp; +} + +static inline void hri_wdt_set_MR_WDD_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= WDT_MR_WDD(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_get_MR_WDD_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDD(mask)) >> WDT_MR_WDD_Pos; + return tmp; +} + +static inline void hri_wdt_write_MR_WDD_bf(const void *const hw, hri_wdt_mr_reg_t data) +{ + uint32_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= ~WDT_MR_WDD_Msk; + tmp |= WDT_MR_WDD(data); + ((Wdt *)hw)->WDT_MR = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_WDD_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~WDT_MR_WDD(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_WDD_bf(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= WDT_MR_WDD(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_read_MR_WDD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp = (tmp & WDT_MR_WDD_Msk) >> WDT_MR_WDD_Pos; + return tmp; +} + +static inline void hri_wdt_set_MR_reg(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_get_MR_reg(const void *const hw, hri_wdt_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->WDT_MR; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_MR_reg(const void *const hw, hri_wdt_mr_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_MR_reg(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_MR_reg(const void *const hw, hri_wdt_mr_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_MR ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_mr_reg_t hri_wdt_read_MR_reg(const void *const hw) +{ + return ((Wdt *)hw)->WDT_MR; +} + +static inline void hri_wdt_write_CR_reg(const void *const hw, hri_wdt_cr_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->WDT_CR = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_E70B_H_INCLUDED */ +#endif /* _SAME70_WDT_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/hri/hri_xdmac_e70b.h b/bsp/microchip/same70/bsp/hri/hri_xdmac_e70b.h new file mode 100644 index 0000000000..a994c70df3 --- /dev/null +++ b/bsp/microchip/same70/bsp/hri/hri_xdmac_e70b.h @@ -0,0 +1,8061 @@ +/** + * \file + * + * \brief SAM XDMAC + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME70_XDMAC_COMPONENT_ +#ifndef _HRI_XDMAC_E70B_H_INCLUDED_ +#define _HRI_XDMAC_E70B_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_XDMAC_CRITICAL_SECTIONS) +#define XDMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define XDMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define XDMAC_CRITICAL_SECTION_ENTER() +#define XDMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_xdmac_cbc_reg_t; +typedef uint32_t hri_xdmac_cc_reg_t; +typedef uint32_t hri_xdmac_cda_reg_t; +typedef uint32_t hri_xdmac_cds_msp_reg_t; +typedef uint32_t hri_xdmac_cdus_reg_t; +typedef uint32_t hri_xdmac_cim_reg_t; +typedef uint32_t hri_xdmac_cis_reg_t; +typedef uint32_t hri_xdmac_cnda_reg_t; +typedef uint32_t hri_xdmac_cndc_reg_t; +typedef uint32_t hri_xdmac_csa_reg_t; +typedef uint32_t hri_xdmac_csus_reg_t; +typedef uint32_t hri_xdmac_cubc_reg_t; +typedef uint32_t hri_xdmac_gcfg_reg_t; +typedef uint32_t hri_xdmac_gim_reg_t; +typedef uint32_t hri_xdmac_gis_reg_t; +typedef uint32_t hri_xdmac_grs_reg_t; +typedef uint32_t hri_xdmac_grwr_reg_t; +typedef uint32_t hri_xdmac_grws_reg_t; +typedef uint32_t hri_xdmac_gs_reg_t; +typedef uint32_t hri_xdmac_gswf_reg_t; +typedef uint32_t hri_xdmac_gswr_reg_t; +typedef uint32_t hri_xdmac_gsws_reg_t; +typedef uint32_t hri_xdmac_gtype_reg_t; +typedef uint32_t hri_xdmac_gwac_reg_t; +typedef uint32_t hri_xdmac_gws_reg_t; +typedef uint32_t hri_xdmacchid_cbc_reg_t; +typedef uint32_t hri_xdmacchid_cc_reg_t; +typedef uint32_t hri_xdmacchid_cda_reg_t; +typedef uint32_t hri_xdmacchid_cds_msp_reg_t; +typedef uint32_t hri_xdmacchid_cdus_reg_t; +typedef uint32_t hri_xdmacchid_cis_reg_t; +typedef uint32_t hri_xdmacchid_cnda_reg_t; +typedef uint32_t hri_xdmacchid_cndc_reg_t; +typedef uint32_t hri_xdmacchid_csa_reg_t; +typedef uint32_t hri_xdmacchid_csus_reg_t; +typedef uint32_t hri_xdmacchid_cubc_reg_t; +typedef uint32_t hri_xdmacchid_xdmac_cim_reg_t; + +static inline void hri_xdmacchid_set_CIM_BIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_BIM; +} + +static inline bool hri_xdmacchid_get_CIM_BIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_BIM) >> XDMAC_CIM_BIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_BIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_BIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_BIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_BIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_BIM; +} + +static inline void hri_xdmacchid_set_CIM_LIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_LIM; +} + +static inline bool hri_xdmacchid_get_CIM_LIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_LIM) >> XDMAC_CIM_LIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_LIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_LIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_LIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_LIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_LIM; +} + +static inline void hri_xdmacchid_set_CIM_DIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_DIM; +} + +static inline bool hri_xdmacchid_get_CIM_DIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_DIM) >> XDMAC_CIM_DIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_DIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_DIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_DIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_DIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_DIM; +} + +static inline void hri_xdmacchid_set_CIM_FIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_FIM; +} + +static inline bool hri_xdmacchid_get_CIM_FIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_FIM) >> XDMAC_CIM_FIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_FIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_FIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_FIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_FIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_FIM; +} + +static inline void hri_xdmacchid_set_CIM_RBEIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_RBEIM; +} + +static inline bool hri_xdmacchid_get_CIM_RBEIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_RBEIM) >> XDMAC_CIM_RBEIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_RBEIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_RBEIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_RBEIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_RBEIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_RBEIM; +} + +static inline void hri_xdmacchid_set_CIM_WBEIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_WBEIM; +} + +static inline bool hri_xdmacchid_get_CIM_WBEIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_WBEIM) >> XDMAC_CIM_WBEIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_WBEIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_WBEIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_WBEIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_WBEIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_WBEIM; +} + +static inline void hri_xdmacchid_set_CIM_ROIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_ROIM; +} + +static inline bool hri_xdmacchid_get_CIM_ROIM_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIM & XDMAC_CIM_ROIM) >> XDMAC_CIM_ROIM_Pos; +} + +static inline void hri_xdmacchid_write_CIM_ROIM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_ROIM; + } else { + ((XdmacChid *)hw)->XDMAC_CIE = XDMAC_CIM_ROIM; + } +} + +static inline void hri_xdmacchid_clear_CIM_ROIM_bit(const void *const hw) +{ + ((XdmacChid *)hw)->XDMAC_CID = XDMAC_CIM_ROIM; +} + +static inline void hri_xdmacchid_set_CIM_reg(const void *const hw, hri_xdmac_cim_reg_t mask) +{ + ((XdmacChid *)hw)->XDMAC_CIE = mask; +} + +static inline hri_xdmac_cim_reg_t hri_xdmacchid_get_CIM_reg(const void *const hw, hri_xdmac_cim_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CIM; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_cim_reg_t hri_xdmacchid_read_CIM_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CIM; +} + +static inline void hri_xdmacchid_write_CIM_reg(const void *const hw, hri_xdmac_cim_reg_t data) +{ + ((XdmacChid *)hw)->XDMAC_CIE = data; + ((XdmacChid *)hw)->XDMAC_CID = ~data; +} + +static inline void hri_xdmacchid_clear_CIM_reg(const void *const hw, hri_xdmac_cim_reg_t mask) +{ + ((XdmacChid *)hw)->XDMAC_CID = mask; +} + +static inline bool hri_xdmacchid_get_CIS_BIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_BIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_LIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_LIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_DIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_DIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_FIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_FIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_RBEIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_RBEIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_WBEIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_WBEIS) > 0; +} + +static inline bool hri_xdmacchid_get_CIS_ROIS_bit(const void *const hw) +{ + return (((XdmacChid *)hw)->XDMAC_CIS & XDMAC_CIS_ROIS) > 0; +} + +static inline hri_xdmac_cis_reg_t hri_xdmacchid_get_CIS_reg(const void *const hw, hri_xdmac_cis_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CIS; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_cis_reg_t hri_xdmacchid_read_CIS_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CIS; +} + +static inline void hri_xdmacchid_set_CSA_SA_bf(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA |= XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmacchid_get_CSA_SA_bf(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSA; + tmp = (tmp & XDMAC_CSA_SA(mask)) >> XDMAC_CSA_SA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CSA_SA_bf(const void *const hw, hri_xdmac_csa_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CSA; + tmp &= ~XDMAC_CSA_SA_Msk; + tmp |= XDMAC_CSA_SA(data); + ((XdmacChid *)hw)->XDMAC_CSA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CSA_SA_bf(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA &= ~XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CSA_SA_bf(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA ^= XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmacchid_read_CSA_SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSA; + tmp = (tmp & XDMAC_CSA_SA_Msk) >> XDMAC_CSA_SA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CSA_reg(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmacchid_get_CSA_reg(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CSA_reg(const void *const hw, hri_xdmac_csa_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CSA_reg(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CSA_reg(const void *const hw, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmacchid_read_CSA_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CSA; +} + +static inline void hri_xdmacchid_set_CDA_DA_bf(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA |= XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmacchid_get_CDA_DA_bf(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDA; + tmp = (tmp & XDMAC_CDA_DA(mask)) >> XDMAC_CDA_DA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CDA_DA_bf(const void *const hw, hri_xdmac_cda_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CDA; + tmp &= ~XDMAC_CDA_DA_Msk; + tmp |= XDMAC_CDA_DA(data); + ((XdmacChid *)hw)->XDMAC_CDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDA_DA_bf(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA &= ~XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDA_DA_bf(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA ^= XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmacchid_read_CDA_DA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDA; + tmp = (tmp & XDMAC_CDA_DA_Msk) >> XDMAC_CDA_DA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CDA_reg(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmacchid_get_CDA_reg(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CDA_reg(const void *const hw, hri_xdmac_cda_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDA_reg(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDA_reg(const void *const hw, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmacchid_read_CDA_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CDA; +} + +static inline void hri_xdmacchid_set_CNDA_NDAIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA |= XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CNDA_NDAIF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDAIF) >> XDMAC_CNDA_NDAIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CNDA_NDAIF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp &= ~XDMAC_CNDA_NDAIF; + tmp |= value << XDMAC_CNDA_NDAIF_Pos; + ((XdmacChid *)hw)->XDMAC_CNDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDA_NDAIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA &= ~XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDA_NDAIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA ^= XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CNDA_NDA_bf(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA |= XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmacchid_get_CNDA_NDA_bf(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDA(mask)) >> XDMAC_CNDA_NDA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CNDA_NDA_bf(const void *const hw, hri_xdmac_cnda_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp &= ~XDMAC_CNDA_NDA_Msk; + tmp |= XDMAC_CNDA_NDA(data); + ((XdmacChid *)hw)->XDMAC_CNDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDA_NDA_bf(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA &= ~XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDA_NDA_bf(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA ^= XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmacchid_read_CNDA_NDA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDA_Msk) >> XDMAC_CNDA_NDA_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CNDA_reg(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmacchid_get_CNDA_reg(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CNDA_reg(const void *const hw, hri_xdmac_cnda_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDA_reg(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDA_reg(const void *const hw, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmacchid_read_CNDA_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CNDA; +} + +static inline void hri_xdmacchid_set_CNDC_NDE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC |= XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CNDC_NDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDE) >> XDMAC_CNDC_NDE_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CNDC_NDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDE; + tmp |= value << XDMAC_CNDC_NDE_Pos; + ((XdmacChid *)hw)->XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDC_NDE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC &= ~XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDC_NDE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC ^= XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CNDC_NDSUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC |= XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CNDC_NDSUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDSUP) >> XDMAC_CNDC_NDSUP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CNDC_NDSUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDSUP; + tmp |= value << XDMAC_CNDC_NDSUP_Pos; + ((XdmacChid *)hw)->XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDC_NDSUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC &= ~XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDC_NDSUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC ^= XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CNDC_NDDUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC |= XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CNDC_NDDUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDDUP) >> XDMAC_CNDC_NDDUP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CNDC_NDDUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDDUP; + tmp |= value << XDMAC_CNDC_NDDUP_Pos; + ((XdmacChid *)hw)->XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDC_NDDUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC &= ~XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDC_NDDUP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC ^= XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CNDC_NDVIEW_bf(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC |= XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmacchid_get_CNDC_NDVIEW_bf(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDVIEW(mask)) >> XDMAC_CNDC_NDVIEW_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CNDC_NDVIEW_bf(const void *const hw, hri_xdmac_cndc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDVIEW_Msk; + tmp |= XDMAC_CNDC_NDVIEW(data); + ((XdmacChid *)hw)->XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDC_NDVIEW_bf(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC &= ~XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDC_NDVIEW_bf(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC ^= XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmacchid_read_CNDC_NDVIEW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDVIEW_Msk) >> XDMAC_CNDC_NDVIEW_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CNDC_reg(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmacchid_get_CNDC_reg(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CNDC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CNDC_reg(const void *const hw, hri_xdmac_cndc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CNDC_reg(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CNDC_reg(const void *const hw, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CNDC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmacchid_read_CNDC_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CNDC; +} + +static inline void hri_xdmacchid_set_CUBC_UBLEN_bf(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC |= XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmacchid_get_CUBC_UBLEN_bf(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CUBC; + tmp = (tmp & XDMAC_CUBC_UBLEN(mask)) >> XDMAC_CUBC_UBLEN_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CUBC_UBLEN_bf(const void *const hw, hri_xdmac_cubc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CUBC; + tmp &= ~XDMAC_CUBC_UBLEN_Msk; + tmp |= XDMAC_CUBC_UBLEN(data); + ((XdmacChid *)hw)->XDMAC_CUBC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CUBC_UBLEN_bf(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC &= ~XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CUBC_UBLEN_bf(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC ^= XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmacchid_read_CUBC_UBLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CUBC; + tmp = (tmp & XDMAC_CUBC_UBLEN_Msk) >> XDMAC_CUBC_UBLEN_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CUBC_reg(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmacchid_get_CUBC_reg(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CUBC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CUBC_reg(const void *const hw, hri_xdmac_cubc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CUBC_reg(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CUBC_reg(const void *const hw, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CUBC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmacchid_read_CUBC_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CUBC; +} + +static inline void hri_xdmacchid_set_CBC_BLEN_bf(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC |= XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmacchid_get_CBC_BLEN_bf(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CBC; + tmp = (tmp & XDMAC_CBC_BLEN(mask)) >> XDMAC_CBC_BLEN_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CBC_BLEN_bf(const void *const hw, hri_xdmac_cbc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CBC; + tmp &= ~XDMAC_CBC_BLEN_Msk; + tmp |= XDMAC_CBC_BLEN(data); + ((XdmacChid *)hw)->XDMAC_CBC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CBC_BLEN_bf(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC &= ~XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CBC_BLEN_bf(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC ^= XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmacchid_read_CBC_BLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CBC; + tmp = (tmp & XDMAC_CBC_BLEN_Msk) >> XDMAC_CBC_BLEN_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CBC_reg(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmacchid_get_CBC_reg(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CBC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CBC_reg(const void *const hw, hri_xdmac_cbc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CBC_reg(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CBC_reg(const void *const hw, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CBC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmacchid_read_CBC_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CBC; +} + +static inline void hri_xdmacchid_set_CC_TYPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_TYPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_TYPE) >> XDMAC_CC_TYPE_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_TYPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_TYPE; + tmp |= value << XDMAC_CC_TYPE_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_TYPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_TYPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_DSYNC_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_DSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DSYNC) >> XDMAC_CC_DSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_DSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_DSYNC; + tmp |= value << XDMAC_CC_DSYNC_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_DSYNC_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_DSYNC_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_SWREQ_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_SWREQ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_SWREQ) >> XDMAC_CC_SWREQ_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_SWREQ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_SWREQ; + tmp |= value << XDMAC_CC_SWREQ_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_SWREQ_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_SWREQ_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_MEMSET_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_MEMSET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_MEMSET) >> XDMAC_CC_MEMSET_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_MEMSET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_MEMSET; + tmp |= value << XDMAC_CC_MEMSET_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_MEMSET_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_MEMSET_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_SIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_SIF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_SIF) >> XDMAC_CC_SIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_SIF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_SIF; + tmp |= value << XDMAC_CC_SIF_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_SIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_SIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_DIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_DIF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DIF) >> XDMAC_CC_DIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_DIF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_DIF; + tmp |= value << XDMAC_CC_DIF_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_DIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_DIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_INITD_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_INITD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_INITD) >> XDMAC_CC_INITD_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_INITD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_INITD; + tmp |= value << XDMAC_CC_INITD_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_INITD_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_INITD_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_RDIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_RDIP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_RDIP) >> XDMAC_CC_RDIP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_RDIP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_RDIP; + tmp |= value << XDMAC_CC_RDIP_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_RDIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_RDIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_WRIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmacchid_get_CC_WRIP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_WRIP) >> XDMAC_CC_WRIP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmacchid_write_CC_WRIP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_WRIP; + tmp |= value << XDMAC_CC_WRIP_Pos; + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_WRIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_WRIP_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_set_CC_MBSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_MBSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_MBSIZE(mask)) >> XDMAC_CC_MBSIZE_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_MBSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_MBSIZE_Msk; + tmp |= XDMAC_CC_MBSIZE(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_MBSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_MBSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_MBSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_MBSIZE_Msk) >> XDMAC_CC_MBSIZE_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_CSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_CSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_CSIZE(mask)) >> XDMAC_CC_CSIZE_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_CSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_CSIZE_Msk; + tmp |= XDMAC_CC_CSIZE(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_CSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_CSIZE_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_CSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_CSIZE_Msk) >> XDMAC_CC_CSIZE_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_DWIDTH_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_DWIDTH_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DWIDTH(mask)) >> XDMAC_CC_DWIDTH_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_DWIDTH_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_DWIDTH_Msk; + tmp |= XDMAC_CC_DWIDTH(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_DWIDTH_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_DWIDTH_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_DWIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DWIDTH_Msk) >> XDMAC_CC_DWIDTH_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_SAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_SAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_SAM(mask)) >> XDMAC_CC_SAM_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_SAM_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_SAM_Msk; + tmp |= XDMAC_CC_SAM(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_SAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_SAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_SAM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_SAM_Msk) >> XDMAC_CC_SAM_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_DAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_DAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DAM(mask)) >> XDMAC_CC_DAM_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_DAM_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_DAM_Msk; + tmp |= XDMAC_CC_DAM(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_DAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_DAM_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_DAM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_DAM_Msk) >> XDMAC_CC_DAM_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_PERID_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_PERID_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_PERID(mask)) >> XDMAC_CC_PERID_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_PERID_bf(const void *const hw, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= ~XDMAC_CC_PERID_Msk; + tmp |= XDMAC_CC_PERID(data); + ((XdmacChid *)hw)->XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_PERID_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_PERID_bf(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp = (tmp & XDMAC_CC_PERID_Msk) >> XDMAC_CC_PERID_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CC_reg(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_get_CC_reg(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CC_reg(const void *const hw, hri_xdmac_cc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CC_reg(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CC_reg(const void *const hw, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmacchid_read_CC_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CC; +} + +static inline void hri_xdmacchid_set_CDS_MSP_SDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP |= XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_get_CDS_MSP_SDS_MSP_bf(const void *const hw, + hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_SDS_MSP(mask)) >> XDMAC_CDS_MSP_SDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CDS_MSP_SDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp &= ~XDMAC_CDS_MSP_SDS_MSP_Msk; + tmp |= XDMAC_CDS_MSP_SDS_MSP(data); + ((XdmacChid *)hw)->XDMAC_CDS_MSP = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDS_MSP_SDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP &= ~XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDS_MSP_SDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP ^= XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_read_CDS_MSP_SDS_MSP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_SDS_MSP_Msk) >> XDMAC_CDS_MSP_SDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CDS_MSP_DDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP |= XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_get_CDS_MSP_DDS_MSP_bf(const void *const hw, + hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_DDS_MSP(mask)) >> XDMAC_CDS_MSP_DDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CDS_MSP_DDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp &= ~XDMAC_CDS_MSP_DDS_MSP_Msk; + tmp |= XDMAC_CDS_MSP_DDS_MSP(data); + ((XdmacChid *)hw)->XDMAC_CDS_MSP = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDS_MSP_DDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP &= ~XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDS_MSP_DDS_MSP_bf(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP ^= XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_read_CDS_MSP_DDS_MSP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_DDS_MSP_Msk) >> XDMAC_CDS_MSP_DDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CDS_MSP_reg(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_get_CDS_MSP_reg(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDS_MSP; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CDS_MSP_reg(const void *const hw, hri_xdmac_cds_msp_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDS_MSP_reg(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDS_MSP_reg(const void *const hw, hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDS_MSP ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmacchid_read_CDS_MSP_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CDS_MSP; +} + +static inline void hri_xdmacchid_set_CSUS_SUBS_bf(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS |= XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmacchid_get_CSUS_SUBS_bf(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSUS; + tmp = (tmp & XDMAC_CSUS_SUBS(mask)) >> XDMAC_CSUS_SUBS_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CSUS_SUBS_bf(const void *const hw, hri_xdmac_csus_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CSUS; + tmp &= ~XDMAC_CSUS_SUBS_Msk; + tmp |= XDMAC_CSUS_SUBS(data); + ((XdmacChid *)hw)->XDMAC_CSUS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CSUS_SUBS_bf(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS &= ~XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CSUS_SUBS_bf(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS ^= XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmacchid_read_CSUS_SUBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSUS; + tmp = (tmp & XDMAC_CSUS_SUBS_Msk) >> XDMAC_CSUS_SUBS_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CSUS_reg(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmacchid_get_CSUS_reg(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CSUS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CSUS_reg(const void *const hw, hri_xdmac_csus_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CSUS_reg(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CSUS_reg(const void *const hw, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CSUS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmacchid_read_CSUS_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CSUS; +} + +static inline void hri_xdmacchid_set_CDUS_DUBS_bf(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS |= XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmacchid_get_CDUS_DUBS_bf(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDUS; + tmp = (tmp & XDMAC_CDUS_DUBS(mask)) >> XDMAC_CDUS_DUBS_Pos; + return tmp; +} + +static inline void hri_xdmacchid_write_CDUS_DUBS_bf(const void *const hw, hri_xdmac_cdus_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((XdmacChid *)hw)->XDMAC_CDUS; + tmp &= ~XDMAC_CDUS_DUBS_Msk; + tmp |= XDMAC_CDUS_DUBS(data); + ((XdmacChid *)hw)->XDMAC_CDUS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDUS_DUBS_bf(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS &= ~XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDUS_DUBS_bf(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS ^= XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmacchid_read_CDUS_DUBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDUS; + tmp = (tmp & XDMAC_CDUS_DUBS_Msk) >> XDMAC_CDUS_DUBS_Pos; + return tmp; +} + +static inline void hri_xdmacchid_set_CDUS_reg(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmacchid_get_CDUS_reg(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + uint32_t tmp; + tmp = ((XdmacChid *)hw)->XDMAC_CDUS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmacchid_write_CDUS_reg(const void *const hw, hri_xdmac_cdus_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_clear_CDUS_reg(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmacchid_toggle_CDUS_reg(const void *const hw, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((XdmacChid *)hw)->XDMAC_CDUS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmacchid_read_CDUS_reg(const void *const hw) +{ + return ((XdmacChid *)hw)->XDMAC_CDUS; +} + +static inline void hri_xdmac_set_CIM_BIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_BIM; +} + +static inline bool hri_xdmac_get_CIM_BIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_BIM) >> XDMAC_CIM_BIM_Pos; +} + +static inline void hri_xdmac_write_CIM_BIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_BIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_BIM; + } +} + +static inline void hri_xdmac_clear_CIM_BIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_BIM; +} + +static inline void hri_xdmac_set_CIM_LIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_LIM; +} + +static inline bool hri_xdmac_get_CIM_LIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_LIM) >> XDMAC_CIM_LIM_Pos; +} + +static inline void hri_xdmac_write_CIM_LIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_LIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_LIM; + } +} + +static inline void hri_xdmac_clear_CIM_LIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_LIM; +} + +static inline void hri_xdmac_set_CIM_DIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_DIM; +} + +static inline bool hri_xdmac_get_CIM_DIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_DIM) >> XDMAC_CIM_DIM_Pos; +} + +static inline void hri_xdmac_write_CIM_DIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_DIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_DIM; + } +} + +static inline void hri_xdmac_clear_CIM_DIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_DIM; +} + +static inline void hri_xdmac_set_CIM_FIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_FIM; +} + +static inline bool hri_xdmac_get_CIM_FIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_FIM) >> XDMAC_CIM_FIM_Pos; +} + +static inline void hri_xdmac_write_CIM_FIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_FIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_FIM; + } +} + +static inline void hri_xdmac_clear_CIM_FIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_FIM; +} + +static inline void hri_xdmac_set_CIM_RBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_RBEIM; +} + +static inline bool hri_xdmac_get_CIM_RBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_RBEIM) >> XDMAC_CIM_RBEIM_Pos; +} + +static inline void hri_xdmac_write_CIM_RBEIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_RBEIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_RBEIM; + } +} + +static inline void hri_xdmac_clear_CIM_RBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_RBEIM; +} + +static inline void hri_xdmac_set_CIM_WBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_WBEIM; +} + +static inline bool hri_xdmac_get_CIM_WBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_WBEIM) >> XDMAC_CIM_WBEIM_Pos; +} + +static inline void hri_xdmac_write_CIM_WBEIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_WBEIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_WBEIM; + } +} + +static inline void hri_xdmac_clear_CIM_WBEIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_WBEIM; +} + +static inline void hri_xdmac_set_CIM_ROIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_ROIM; +} + +static inline bool hri_xdmac_get_CIM_ROIM_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM & XDMAC_CIM_ROIM) >> XDMAC_CIM_ROIM_Pos; +} + +static inline void hri_xdmac_write_CIM_ROIM_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_ROIM; + } else { + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = XDMAC_CIM_ROIM; + } +} + +static inline void hri_xdmac_clear_CIM_ROIM_bit(const void *const hw, uint8_t submodule_index) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = XDMAC_CIM_ROIM; +} + +static inline void hri_xdmac_set_CIM_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cim_reg_t mask) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = mask; +} + +static inline hri_xdmac_cim_reg_t hri_xdmac_get_CIM_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cim_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_cim_reg_t hri_xdmac_read_CIM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIM; +} + +static inline void hri_xdmac_write_CIM_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cim_reg_t data) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIE = data; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = ~data; +} + +static inline void hri_xdmac_clear_CIM_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cim_reg_t mask) +{ + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CID = mask; +} + +static inline bool hri_xdmac_get_CIS_BIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_BIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_LIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_LIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_DIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_DIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_FIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_FIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_RBEIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_RBEIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_WBEIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_WBEIS) > 0; +} + +static inline bool hri_xdmac_get_CIS_ROIS_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS & XDMAC_CIS_ROIS) > 0; +} + +static inline hri_xdmac_cis_reg_t hri_xdmac_get_CIS_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cis_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_cis_reg_t hri_xdmac_read_CIS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CIS; +} + +static inline void hri_xdmac_set_CSA_SA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA |= XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmac_get_CSA_SA_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_csa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA; + tmp = (tmp & XDMAC_CSA_SA(mask)) >> XDMAC_CSA_SA_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CSA_SA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA; + tmp &= ~XDMAC_CSA_SA_Msk; + tmp |= XDMAC_CSA_SA(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CSA_SA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA &= ~XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CSA_SA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA ^= XDMAC_CSA_SA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmac_read_CSA_SA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA; + tmp = (tmp & XDMAC_CSA_SA_Msk) >> XDMAC_CSA_SA_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CSA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmac_get_CSA_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_csa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CSA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CSA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CSA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csa_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csa_reg_t hri_xdmac_read_CSA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSA; +} + +static inline void hri_xdmac_set_CDA_DA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA |= XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmac_get_CDA_DA_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cda_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA; + tmp = (tmp & XDMAC_CDA_DA(mask)) >> XDMAC_CDA_DA_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CDA_DA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA; + tmp &= ~XDMAC_CDA_DA_Msk; + tmp |= XDMAC_CDA_DA(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDA_DA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA &= ~XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDA_DA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA ^= XDMAC_CDA_DA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmac_read_CDA_DA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA; + tmp = (tmp & XDMAC_CDA_DA_Msk) >> XDMAC_CDA_DA_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmac_get_CDA_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cda_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cda_reg_t hri_xdmac_read_CDA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDA; +} + +static inline void hri_xdmac_set_CNDA_NDAIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA |= XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CNDA_NDAIF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDAIF) >> XDMAC_CNDA_NDAIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CNDA_NDAIF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp &= ~XDMAC_CNDA_NDAIF; + tmp |= value << XDMAC_CNDA_NDAIF_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDA_NDAIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA &= ~XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDA_NDAIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA ^= XDMAC_CNDA_NDAIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA |= XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmac_get_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cnda_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDA(mask)) >> XDMAC_CNDA_NDA_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp &= ~XDMAC_CNDA_NDA_Msk; + tmp |= XDMAC_CNDA_NDA(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA &= ~XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA ^= XDMAC_CNDA_NDA(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmac_read_CNDA_NDA_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp = (tmp & XDMAC_CNDA_NDA_Msk) >> XDMAC_CNDA_NDA_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CNDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmac_get_CNDA_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cnda_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CNDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDA_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cnda_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cnda_reg_t hri_xdmac_read_CNDA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDA; +} + +static inline void hri_xdmac_set_CNDC_NDE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC |= XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CNDC_NDE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDE) >> XDMAC_CNDC_NDE_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CNDC_NDE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDE; + tmp |= value << XDMAC_CNDC_NDE_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDC_NDE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC &= ~XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDC_NDE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC ^= XDMAC_CNDC_NDE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CNDC_NDSUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC |= XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CNDC_NDSUP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDSUP) >> XDMAC_CNDC_NDSUP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CNDC_NDSUP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDSUP; + tmp |= value << XDMAC_CNDC_NDSUP_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDC_NDSUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC &= ~XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDC_NDSUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC ^= XDMAC_CNDC_NDSUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CNDC_NDDUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC |= XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CNDC_NDDUP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDDUP) >> XDMAC_CNDC_NDDUP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CNDC_NDDUP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDDUP; + tmp |= value << XDMAC_CNDC_NDDUP_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDC_NDDUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC &= ~XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDC_NDDUP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC ^= XDMAC_CNDC_NDDUP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC |= XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmac_get_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDVIEW(mask)) >> XDMAC_CNDC_NDVIEW_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp &= ~XDMAC_CNDC_NDVIEW_Msk; + tmp |= XDMAC_CNDC_NDVIEW(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC &= ~XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC ^= XDMAC_CNDC_NDVIEW(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmac_read_CNDC_NDVIEW_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp = (tmp & XDMAC_CNDC_NDVIEW_Msk) >> XDMAC_CNDC_NDVIEW_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CNDC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmac_get_CNDC_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cndc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CNDC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cndc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CNDC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CNDC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cndc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cndc_reg_t hri_xdmac_read_CNDC_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CNDC; +} + +static inline void hri_xdmac_set_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC |= XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmac_get_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cubc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC; + tmp = (tmp & XDMAC_CUBC_UBLEN(mask)) >> XDMAC_CUBC_UBLEN_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cubc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC; + tmp &= ~XDMAC_CUBC_UBLEN_Msk; + tmp |= XDMAC_CUBC_UBLEN(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC &= ~XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC ^= XDMAC_CUBC_UBLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmac_read_CUBC_UBLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC; + tmp = (tmp & XDMAC_CUBC_UBLEN_Msk) >> XDMAC_CUBC_UBLEN_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CUBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmac_get_CUBC_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cubc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CUBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cubc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CUBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CUBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cubc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cubc_reg_t hri_xdmac_read_CUBC_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CUBC; +} + +static inline void hri_xdmac_set_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC |= XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmac_get_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC; + tmp = (tmp & XDMAC_CBC_BLEN(mask)) >> XDMAC_CBC_BLEN_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC; + tmp &= ~XDMAC_CBC_BLEN_Msk; + tmp |= XDMAC_CBC_BLEN(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC &= ~XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC ^= XDMAC_CBC_BLEN(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmac_read_CBC_BLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC; + tmp = (tmp & XDMAC_CBC_BLEN_Msk) >> XDMAC_CBC_BLEN_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmac_get_CBC_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CBC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cbc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cbc_reg_t hri_xdmac_read_CBC_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CBC; +} + +static inline void hri_xdmac_set_CC_TYPE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_TYPE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_TYPE) >> XDMAC_CC_TYPE_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_TYPE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_TYPE; + tmp |= value << XDMAC_CC_TYPE_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_TYPE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_TYPE_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_TYPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_DSYNC_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_DSYNC_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DSYNC) >> XDMAC_CC_DSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_DSYNC_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_DSYNC; + tmp |= value << XDMAC_CC_DSYNC_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_DSYNC_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_DSYNC_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_DSYNC; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_SWREQ_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_SWREQ_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_SWREQ) >> XDMAC_CC_SWREQ_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_SWREQ_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_SWREQ; + tmp |= value << XDMAC_CC_SWREQ_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_SWREQ_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_SWREQ_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_SWREQ; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_MEMSET_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_MEMSET_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_MEMSET) >> XDMAC_CC_MEMSET_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_MEMSET_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_MEMSET; + tmp |= value << XDMAC_CC_MEMSET_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_MEMSET_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_MEMSET_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_MEMSET; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_SIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_SIF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_SIF) >> XDMAC_CC_SIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_SIF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_SIF; + tmp |= value << XDMAC_CC_SIF_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_SIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_SIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_SIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_DIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_DIF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DIF) >> XDMAC_CC_DIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_DIF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_DIF; + tmp |= value << XDMAC_CC_DIF_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_DIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_DIF_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_DIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_INITD_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_INITD_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_INITD) >> XDMAC_CC_INITD_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_INITD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_INITD; + tmp |= value << XDMAC_CC_INITD_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_INITD_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_INITD_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_INITD; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_RDIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_RDIP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_RDIP) >> XDMAC_CC_RDIP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_RDIP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_RDIP; + tmp |= value << XDMAC_CC_RDIP_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_RDIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_RDIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_RDIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_WRIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_CC_WRIP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_WRIP) >> XDMAC_CC_WRIP_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_CC_WRIP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_WRIP; + tmp |= value << XDMAC_CC_WRIP_Pos; + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_WRIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_WRIP_bit(const void *const hw, uint8_t submodule_index) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_WRIP; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_MBSIZE(mask)) >> XDMAC_CC_MBSIZE_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_MBSIZE_Msk; + tmp |= XDMAC_CC_MBSIZE(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_MBSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_MBSIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_MBSIZE_Msk) >> XDMAC_CC_MBSIZE_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_CSIZE(mask)) >> XDMAC_CC_CSIZE_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_CSIZE_Msk; + tmp |= XDMAC_CC_CSIZE(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_CSIZE(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_CSIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_CSIZE_Msk) >> XDMAC_CC_CSIZE_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DWIDTH(mask)) >> XDMAC_CC_DWIDTH_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_DWIDTH_Msk; + tmp |= XDMAC_CC_DWIDTH(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_DWIDTH(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_DWIDTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DWIDTH_Msk) >> XDMAC_CC_DWIDTH_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_SAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_SAM_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_SAM(mask)) >> XDMAC_CC_SAM_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_SAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_SAM_Msk; + tmp |= XDMAC_CC_SAM(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_SAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_SAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_SAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_SAM_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_SAM_Msk) >> XDMAC_CC_SAM_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_DAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_DAM_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DAM(mask)) >> XDMAC_CC_DAM_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_DAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_DAM_Msk; + tmp |= XDMAC_CC_DAM(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_DAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_DAM_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_DAM(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_DAM_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_DAM_Msk) >> XDMAC_CC_DAM_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_PERID_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_PERID_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_PERID(mask)) >> XDMAC_CC_PERID_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CC_PERID_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= ~XDMAC_CC_PERID_Msk; + tmp |= XDMAC_CC_PERID(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_PERID_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_PERID_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= XDMAC_CC_PERID(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_PERID_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp = (tmp & XDMAC_CC_PERID_Msk) >> XDMAC_CC_PERID_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_get_CC_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CC_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cc_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cc_reg_t hri_xdmac_read_CC_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CC; +} + +static inline void hri_xdmac_set_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP |= XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_get_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_SDS_MSP(mask)) >> XDMAC_CDS_MSP_SDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp &= ~XDMAC_CDS_MSP_SDS_MSP_Msk; + tmp |= XDMAC_CDS_MSP_SDS_MSP(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP &= ~XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP ^= XDMAC_CDS_MSP_SDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_read_CDS_MSP_SDS_MSP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_SDS_MSP_Msk) >> XDMAC_CDS_MSP_SDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP |= XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_get_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_DDS_MSP(mask)) >> XDMAC_CDS_MSP_DDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp &= ~XDMAC_CDS_MSP_DDS_MSP_Msk; + tmp |= XDMAC_CDS_MSP_DDS_MSP(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP &= ~XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP ^= XDMAC_CDS_MSP_DDS_MSP(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_read_CDS_MSP_DDS_MSP_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp = (tmp & XDMAC_CDS_MSP_DDS_MSP_Msk) >> XDMAC_CDS_MSP_DDS_MSP_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CDS_MSP_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_get_CDS_MSP_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CDS_MSP_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDS_MSP_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDS_MSP_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cds_msp_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cds_msp_reg_t hri_xdmac_read_CDS_MSP_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDS_MSP; +} + +static inline void hri_xdmac_set_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS |= XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmac_get_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_csus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS; + tmp = (tmp & XDMAC_CSUS_SUBS(mask)) >> XDMAC_CSUS_SUBS_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_csus_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS; + tmp &= ~XDMAC_CSUS_SUBS_Msk; + tmp |= XDMAC_CSUS_SUBS(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS &= ~XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS ^= XDMAC_CSUS_SUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmac_read_CSUS_SUBS_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS; + tmp = (tmp & XDMAC_CSUS_SUBS_Msk) >> XDMAC_CSUS_SUBS_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CSUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmac_get_CSUS_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_csus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CSUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csus_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CSUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CSUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_csus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_csus_reg_t hri_xdmac_read_CSUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CSUS; +} + +static inline void hri_xdmac_set_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS |= XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmac_get_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cdus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS; + tmp = (tmp & XDMAC_CDUS_DUBS(mask)) >> XDMAC_CDUS_DUBS_Pos; + return tmp; +} + +static inline void hri_xdmac_write_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cdus_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS; + tmp &= ~XDMAC_CDUS_DUBS_Msk; + tmp |= XDMAC_CDUS_DUBS(data); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS &= ~XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index, + hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS ^= XDMAC_CDUS_DUBS(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmac_read_CDUS_DUBS_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS; + tmp = (tmp & XDMAC_CDUS_DUBS_Msk) >> XDMAC_CDUS_DUBS_Pos; + return tmp; +} + +static inline void hri_xdmac_set_CDUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmac_get_CDUS_reg(const void *const hw, uint8_t submodule_index, + hri_xdmac_cdus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_CDUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cdus_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_CDUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_CDUS_reg(const void *const hw, uint8_t submodule_index, hri_xdmac_cdus_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_cdus_reg_t hri_xdmac_read_CDUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Xdmac *)hw)->XdmacChid[submodule_index].XDMAC_CDUS; +} + +static inline void hri_xdmac_set_GIM_IM0_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM0; +} + +static inline bool hri_xdmac_get_GIM_IM0_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM0) >> XDMAC_GIM_IM0_Pos; +} + +static inline void hri_xdmac_write_GIM_IM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM0; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM0; + } +} + +static inline void hri_xdmac_clear_GIM_IM0_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM0; +} + +static inline void hri_xdmac_set_GIM_IM1_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM1; +} + +static inline bool hri_xdmac_get_GIM_IM1_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM1) >> XDMAC_GIM_IM1_Pos; +} + +static inline void hri_xdmac_write_GIM_IM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM1; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM1; + } +} + +static inline void hri_xdmac_clear_GIM_IM1_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM1; +} + +static inline void hri_xdmac_set_GIM_IM2_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM2; +} + +static inline bool hri_xdmac_get_GIM_IM2_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM2) >> XDMAC_GIM_IM2_Pos; +} + +static inline void hri_xdmac_write_GIM_IM2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM2; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM2; + } +} + +static inline void hri_xdmac_clear_GIM_IM2_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM2; +} + +static inline void hri_xdmac_set_GIM_IM3_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM3; +} + +static inline bool hri_xdmac_get_GIM_IM3_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM3) >> XDMAC_GIM_IM3_Pos; +} + +static inline void hri_xdmac_write_GIM_IM3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM3; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM3; + } +} + +static inline void hri_xdmac_clear_GIM_IM3_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM3; +} + +static inline void hri_xdmac_set_GIM_IM4_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM4; +} + +static inline bool hri_xdmac_get_GIM_IM4_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM4) >> XDMAC_GIM_IM4_Pos; +} + +static inline void hri_xdmac_write_GIM_IM4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM4; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM4; + } +} + +static inline void hri_xdmac_clear_GIM_IM4_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM4; +} + +static inline void hri_xdmac_set_GIM_IM5_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM5; +} + +static inline bool hri_xdmac_get_GIM_IM5_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM5) >> XDMAC_GIM_IM5_Pos; +} + +static inline void hri_xdmac_write_GIM_IM5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM5; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM5; + } +} + +static inline void hri_xdmac_clear_GIM_IM5_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM5; +} + +static inline void hri_xdmac_set_GIM_IM6_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM6; +} + +static inline bool hri_xdmac_get_GIM_IM6_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM6) >> XDMAC_GIM_IM6_Pos; +} + +static inline void hri_xdmac_write_GIM_IM6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM6; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM6; + } +} + +static inline void hri_xdmac_clear_GIM_IM6_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM6; +} + +static inline void hri_xdmac_set_GIM_IM7_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM7; +} + +static inline bool hri_xdmac_get_GIM_IM7_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM7) >> XDMAC_GIM_IM7_Pos; +} + +static inline void hri_xdmac_write_GIM_IM7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM7; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM7; + } +} + +static inline void hri_xdmac_clear_GIM_IM7_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM7; +} + +static inline void hri_xdmac_set_GIM_IM8_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM8; +} + +static inline bool hri_xdmac_get_GIM_IM8_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM8) >> XDMAC_GIM_IM8_Pos; +} + +static inline void hri_xdmac_write_GIM_IM8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM8; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM8; + } +} + +static inline void hri_xdmac_clear_GIM_IM8_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM8; +} + +static inline void hri_xdmac_set_GIM_IM9_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM9; +} + +static inline bool hri_xdmac_get_GIM_IM9_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM9) >> XDMAC_GIM_IM9_Pos; +} + +static inline void hri_xdmac_write_GIM_IM9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM9; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM9; + } +} + +static inline void hri_xdmac_clear_GIM_IM9_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM9; +} + +static inline void hri_xdmac_set_GIM_IM10_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM10; +} + +static inline bool hri_xdmac_get_GIM_IM10_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM10) >> XDMAC_GIM_IM10_Pos; +} + +static inline void hri_xdmac_write_GIM_IM10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM10; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM10; + } +} + +static inline void hri_xdmac_clear_GIM_IM10_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM10; +} + +static inline void hri_xdmac_set_GIM_IM11_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM11; +} + +static inline bool hri_xdmac_get_GIM_IM11_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM11) >> XDMAC_GIM_IM11_Pos; +} + +static inline void hri_xdmac_write_GIM_IM11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM11; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM11; + } +} + +static inline void hri_xdmac_clear_GIM_IM11_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM11; +} + +static inline void hri_xdmac_set_GIM_IM12_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM12; +} + +static inline bool hri_xdmac_get_GIM_IM12_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM12) >> XDMAC_GIM_IM12_Pos; +} + +static inline void hri_xdmac_write_GIM_IM12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM12; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM12; + } +} + +static inline void hri_xdmac_clear_GIM_IM12_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM12; +} + +static inline void hri_xdmac_set_GIM_IM13_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM13; +} + +static inline bool hri_xdmac_get_GIM_IM13_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM13) >> XDMAC_GIM_IM13_Pos; +} + +static inline void hri_xdmac_write_GIM_IM13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM13; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM13; + } +} + +static inline void hri_xdmac_clear_GIM_IM13_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM13; +} + +static inline void hri_xdmac_set_GIM_IM14_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM14; +} + +static inline bool hri_xdmac_get_GIM_IM14_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM14) >> XDMAC_GIM_IM14_Pos; +} + +static inline void hri_xdmac_write_GIM_IM14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM14; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM14; + } +} + +static inline void hri_xdmac_clear_GIM_IM14_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM14; +} + +static inline void hri_xdmac_set_GIM_IM15_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM15; +} + +static inline bool hri_xdmac_get_GIM_IM15_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM15) >> XDMAC_GIM_IM15_Pos; +} + +static inline void hri_xdmac_write_GIM_IM15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM15; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM15; + } +} + +static inline void hri_xdmac_clear_GIM_IM15_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM15; +} + +static inline void hri_xdmac_set_GIM_IM16_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM16; +} + +static inline bool hri_xdmac_get_GIM_IM16_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM16) >> XDMAC_GIM_IM16_Pos; +} + +static inline void hri_xdmac_write_GIM_IM16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM16; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM16; + } +} + +static inline void hri_xdmac_clear_GIM_IM16_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM16; +} + +static inline void hri_xdmac_set_GIM_IM17_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM17; +} + +static inline bool hri_xdmac_get_GIM_IM17_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM17) >> XDMAC_GIM_IM17_Pos; +} + +static inline void hri_xdmac_write_GIM_IM17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM17; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM17; + } +} + +static inline void hri_xdmac_clear_GIM_IM17_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM17; +} + +static inline void hri_xdmac_set_GIM_IM18_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM18; +} + +static inline bool hri_xdmac_get_GIM_IM18_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM18) >> XDMAC_GIM_IM18_Pos; +} + +static inline void hri_xdmac_write_GIM_IM18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM18; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM18; + } +} + +static inline void hri_xdmac_clear_GIM_IM18_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM18; +} + +static inline void hri_xdmac_set_GIM_IM19_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM19; +} + +static inline bool hri_xdmac_get_GIM_IM19_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM19) >> XDMAC_GIM_IM19_Pos; +} + +static inline void hri_xdmac_write_GIM_IM19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM19; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM19; + } +} + +static inline void hri_xdmac_clear_GIM_IM19_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM19; +} + +static inline void hri_xdmac_set_GIM_IM20_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM20; +} + +static inline bool hri_xdmac_get_GIM_IM20_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM20) >> XDMAC_GIM_IM20_Pos; +} + +static inline void hri_xdmac_write_GIM_IM20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM20; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM20; + } +} + +static inline void hri_xdmac_clear_GIM_IM20_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM20; +} + +static inline void hri_xdmac_set_GIM_IM21_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM21; +} + +static inline bool hri_xdmac_get_GIM_IM21_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM21) >> XDMAC_GIM_IM21_Pos; +} + +static inline void hri_xdmac_write_GIM_IM21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM21; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM21; + } +} + +static inline void hri_xdmac_clear_GIM_IM21_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM21; +} + +static inline void hri_xdmac_set_GIM_IM22_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM22; +} + +static inline bool hri_xdmac_get_GIM_IM22_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM22) >> XDMAC_GIM_IM22_Pos; +} + +static inline void hri_xdmac_write_GIM_IM22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM22; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM22; + } +} + +static inline void hri_xdmac_clear_GIM_IM22_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM22; +} + +static inline void hri_xdmac_set_GIM_IM23_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM23; +} + +static inline bool hri_xdmac_get_GIM_IM23_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIM & XDMAC_GIM_IM23) >> XDMAC_GIM_IM23_Pos; +} + +static inline void hri_xdmac_write_GIM_IM23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM23; + } else { + ((Xdmac *)hw)->XDMAC_GIE = XDMAC_GIM_IM23; + } +} + +static inline void hri_xdmac_clear_GIM_IM23_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GID = XDMAC_GIM_IM23; +} + +static inline void hri_xdmac_set_GIM_reg(const void *const hw, hri_xdmac_gim_reg_t mask) +{ + ((Xdmac *)hw)->XDMAC_GIE = mask; +} + +static inline hri_xdmac_gim_reg_t hri_xdmac_get_GIM_reg(const void *const hw, hri_xdmac_gim_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GIM; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_gim_reg_t hri_xdmac_read_GIM_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GIM; +} + +static inline void hri_xdmac_write_GIM_reg(const void *const hw, hri_xdmac_gim_reg_t data) +{ + ((Xdmac *)hw)->XDMAC_GIE = data; + ((Xdmac *)hw)->XDMAC_GID = ~data; +} + +static inline void hri_xdmac_clear_GIM_reg(const void *const hw, hri_xdmac_gim_reg_t mask) +{ + ((Xdmac *)hw)->XDMAC_GID = mask; +} + +static inline void hri_xdmac_set_GS_ST0_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST0; +} + +static inline bool hri_xdmac_get_GS_ST0_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST0) >> XDMAC_GS_ST0_Pos; +} + +static inline void hri_xdmac_write_GS_ST0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST0; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST0; + } +} + +static inline void hri_xdmac_clear_GS_ST0_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST0; +} + +static inline void hri_xdmac_set_GS_ST1_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST1; +} + +static inline bool hri_xdmac_get_GS_ST1_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST1) >> XDMAC_GS_ST1_Pos; +} + +static inline void hri_xdmac_write_GS_ST1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST1; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST1; + } +} + +static inline void hri_xdmac_clear_GS_ST1_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST1; +} + +static inline void hri_xdmac_set_GS_ST2_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST2; +} + +static inline bool hri_xdmac_get_GS_ST2_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST2) >> XDMAC_GS_ST2_Pos; +} + +static inline void hri_xdmac_write_GS_ST2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST2; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST2; + } +} + +static inline void hri_xdmac_clear_GS_ST2_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST2; +} + +static inline void hri_xdmac_set_GS_ST3_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST3; +} + +static inline bool hri_xdmac_get_GS_ST3_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST3) >> XDMAC_GS_ST3_Pos; +} + +static inline void hri_xdmac_write_GS_ST3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST3; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST3; + } +} + +static inline void hri_xdmac_clear_GS_ST3_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST3; +} + +static inline void hri_xdmac_set_GS_ST4_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST4; +} + +static inline bool hri_xdmac_get_GS_ST4_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST4) >> XDMAC_GS_ST4_Pos; +} + +static inline void hri_xdmac_write_GS_ST4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST4; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST4; + } +} + +static inline void hri_xdmac_clear_GS_ST4_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST4; +} + +static inline void hri_xdmac_set_GS_ST5_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST5; +} + +static inline bool hri_xdmac_get_GS_ST5_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST5) >> XDMAC_GS_ST5_Pos; +} + +static inline void hri_xdmac_write_GS_ST5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST5; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST5; + } +} + +static inline void hri_xdmac_clear_GS_ST5_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST5; +} + +static inline void hri_xdmac_set_GS_ST6_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST6; +} + +static inline bool hri_xdmac_get_GS_ST6_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST6) >> XDMAC_GS_ST6_Pos; +} + +static inline void hri_xdmac_write_GS_ST6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST6; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST6; + } +} + +static inline void hri_xdmac_clear_GS_ST6_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST6; +} + +static inline void hri_xdmac_set_GS_ST7_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST7; +} + +static inline bool hri_xdmac_get_GS_ST7_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST7) >> XDMAC_GS_ST7_Pos; +} + +static inline void hri_xdmac_write_GS_ST7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST7; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST7; + } +} + +static inline void hri_xdmac_clear_GS_ST7_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST7; +} + +static inline void hri_xdmac_set_GS_ST8_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST8; +} + +static inline bool hri_xdmac_get_GS_ST8_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST8) >> XDMAC_GS_ST8_Pos; +} + +static inline void hri_xdmac_write_GS_ST8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST8; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST8; + } +} + +static inline void hri_xdmac_clear_GS_ST8_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST8; +} + +static inline void hri_xdmac_set_GS_ST9_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST9; +} + +static inline bool hri_xdmac_get_GS_ST9_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST9) >> XDMAC_GS_ST9_Pos; +} + +static inline void hri_xdmac_write_GS_ST9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST9; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST9; + } +} + +static inline void hri_xdmac_clear_GS_ST9_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST9; +} + +static inline void hri_xdmac_set_GS_ST10_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST10; +} + +static inline bool hri_xdmac_get_GS_ST10_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST10) >> XDMAC_GS_ST10_Pos; +} + +static inline void hri_xdmac_write_GS_ST10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST10; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST10; + } +} + +static inline void hri_xdmac_clear_GS_ST10_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST10; +} + +static inline void hri_xdmac_set_GS_ST11_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST11; +} + +static inline bool hri_xdmac_get_GS_ST11_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST11) >> XDMAC_GS_ST11_Pos; +} + +static inline void hri_xdmac_write_GS_ST11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST11; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST11; + } +} + +static inline void hri_xdmac_clear_GS_ST11_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST11; +} + +static inline void hri_xdmac_set_GS_ST12_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST12; +} + +static inline bool hri_xdmac_get_GS_ST12_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST12) >> XDMAC_GS_ST12_Pos; +} + +static inline void hri_xdmac_write_GS_ST12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST12; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST12; + } +} + +static inline void hri_xdmac_clear_GS_ST12_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST12; +} + +static inline void hri_xdmac_set_GS_ST13_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST13; +} + +static inline bool hri_xdmac_get_GS_ST13_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST13) >> XDMAC_GS_ST13_Pos; +} + +static inline void hri_xdmac_write_GS_ST13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST13; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST13; + } +} + +static inline void hri_xdmac_clear_GS_ST13_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST13; +} + +static inline void hri_xdmac_set_GS_ST14_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST14; +} + +static inline bool hri_xdmac_get_GS_ST14_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST14) >> XDMAC_GS_ST14_Pos; +} + +static inline void hri_xdmac_write_GS_ST14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST14; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST14; + } +} + +static inline void hri_xdmac_clear_GS_ST14_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST14; +} + +static inline void hri_xdmac_set_GS_ST15_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST15; +} + +static inline bool hri_xdmac_get_GS_ST15_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST15) >> XDMAC_GS_ST15_Pos; +} + +static inline void hri_xdmac_write_GS_ST15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST15; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST15; + } +} + +static inline void hri_xdmac_clear_GS_ST15_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST15; +} + +static inline void hri_xdmac_set_GS_ST16_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST16; +} + +static inline bool hri_xdmac_get_GS_ST16_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST16) >> XDMAC_GS_ST16_Pos; +} + +static inline void hri_xdmac_write_GS_ST16_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST16; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST16; + } +} + +static inline void hri_xdmac_clear_GS_ST16_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST16; +} + +static inline void hri_xdmac_set_GS_ST17_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST17; +} + +static inline bool hri_xdmac_get_GS_ST17_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST17) >> XDMAC_GS_ST17_Pos; +} + +static inline void hri_xdmac_write_GS_ST17_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST17; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST17; + } +} + +static inline void hri_xdmac_clear_GS_ST17_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST17; +} + +static inline void hri_xdmac_set_GS_ST18_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST18; +} + +static inline bool hri_xdmac_get_GS_ST18_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST18) >> XDMAC_GS_ST18_Pos; +} + +static inline void hri_xdmac_write_GS_ST18_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST18; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST18; + } +} + +static inline void hri_xdmac_clear_GS_ST18_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST18; +} + +static inline void hri_xdmac_set_GS_ST19_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST19; +} + +static inline bool hri_xdmac_get_GS_ST19_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST19) >> XDMAC_GS_ST19_Pos; +} + +static inline void hri_xdmac_write_GS_ST19_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST19; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST19; + } +} + +static inline void hri_xdmac_clear_GS_ST19_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST19; +} + +static inline void hri_xdmac_set_GS_ST20_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST20; +} + +static inline bool hri_xdmac_get_GS_ST20_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST20) >> XDMAC_GS_ST20_Pos; +} + +static inline void hri_xdmac_write_GS_ST20_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST20; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST20; + } +} + +static inline void hri_xdmac_clear_GS_ST20_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST20; +} + +static inline void hri_xdmac_set_GS_ST21_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST21; +} + +static inline bool hri_xdmac_get_GS_ST21_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST21) >> XDMAC_GS_ST21_Pos; +} + +static inline void hri_xdmac_write_GS_ST21_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST21; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST21; + } +} + +static inline void hri_xdmac_clear_GS_ST21_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST21; +} + +static inline void hri_xdmac_set_GS_ST22_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST22; +} + +static inline bool hri_xdmac_get_GS_ST22_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST22) >> XDMAC_GS_ST22_Pos; +} + +static inline void hri_xdmac_write_GS_ST22_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST22; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST22; + } +} + +static inline void hri_xdmac_clear_GS_ST22_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST22; +} + +static inline void hri_xdmac_set_GS_ST23_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST23; +} + +static inline bool hri_xdmac_get_GS_ST23_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GS & XDMAC_GS_ST23) >> XDMAC_GS_ST23_Pos; +} + +static inline void hri_xdmac_write_GS_ST23_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST23; + } else { + ((Xdmac *)hw)->XDMAC_GE = XDMAC_GS_ST23; + } +} + +static inline void hri_xdmac_clear_GS_ST23_bit(const void *const hw) +{ + ((Xdmac *)hw)->XDMAC_GD = XDMAC_GS_ST23; +} + +static inline void hri_xdmac_set_GS_reg(const void *const hw, hri_xdmac_gs_reg_t mask) +{ + ((Xdmac *)hw)->XDMAC_GE = mask; +} + +static inline hri_xdmac_gs_reg_t hri_xdmac_get_GS_reg(const void *const hw, hri_xdmac_gs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GS; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_gs_reg_t hri_xdmac_read_GS_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GS; +} + +static inline void hri_xdmac_write_GS_reg(const void *const hw, hri_xdmac_gs_reg_t data) +{ + ((Xdmac *)hw)->XDMAC_GE = data; + ((Xdmac *)hw)->XDMAC_GD = ~data; +} + +static inline void hri_xdmac_clear_GS_reg(const void *const hw, hri_xdmac_gs_reg_t mask) +{ + ((Xdmac *)hw)->XDMAC_GD = mask; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_get_GTYPE_NB_CH_bf(const void *const hw, hri_xdmac_gtype_reg_t mask) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_NB_CH(mask)) >> XDMAC_GTYPE_NB_CH_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_read_GTYPE_NB_CH_bf(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_NB_CH_Msk) >> XDMAC_GTYPE_NB_CH_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_get_GTYPE_FIFO_SZ_bf(const void *const hw, hri_xdmac_gtype_reg_t mask) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_FIFO_SZ(mask)) >> XDMAC_GTYPE_FIFO_SZ_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_read_GTYPE_FIFO_SZ_bf(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_FIFO_SZ_Msk) >> XDMAC_GTYPE_FIFO_SZ_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_get_GTYPE_NB_REQ_bf(const void *const hw, hri_xdmac_gtype_reg_t mask) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_NB_REQ(mask)) >> XDMAC_GTYPE_NB_REQ_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_read_GTYPE_NB_REQ_bf(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GTYPE & XDMAC_GTYPE_NB_REQ_Msk) >> XDMAC_GTYPE_NB_REQ_Pos; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_get_GTYPE_reg(const void *const hw, hri_xdmac_gtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GTYPE; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_gtype_reg_t hri_xdmac_read_GTYPE_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GTYPE; +} + +static inline bool hri_xdmac_get_GIS_IS0_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS0) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS1_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS1) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS2_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS2) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS3_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS3) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS4_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS4) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS5_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS5) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS6_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS6) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS7_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS7) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS8_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS8) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS9_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS9) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS10_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS10) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS11_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS11) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS12_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS12) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS13_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS13) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS14_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS14) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS15_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS15) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS16_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS16) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS17_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS17) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS18_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS18) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS19_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS19) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS20_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS20) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS21_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS21) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS22_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS22) > 0; +} + +static inline bool hri_xdmac_get_GIS_IS23_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GIS & XDMAC_GIS_IS23) > 0; +} + +static inline hri_xdmac_gis_reg_t hri_xdmac_get_GIS_reg(const void *const hw, hri_xdmac_gis_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GIS; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_gis_reg_t hri_xdmac_read_GIS_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GIS; +} + +static inline bool hri_xdmac_get_GSWS_SWRS0_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS0) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS1_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS1) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS2_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS2) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS3_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS3) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS4_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS4) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS5_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS5) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS6_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS6) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS7_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS7) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS8_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS8) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS9_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS9) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS10_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS10) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS11_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS11) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS12_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS12) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS13_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS13) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS14_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS14) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS15_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS15) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS16_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS16) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS17_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS17) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS18_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS18) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS19_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS19) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS20_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS20) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS21_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS21) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS22_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS22) > 0; +} + +static inline bool hri_xdmac_get_GSWS_SWRS23_bit(const void *const hw) +{ + return (((Xdmac *)hw)->XDMAC_GSWS & XDMAC_GSWS_SWRS23) > 0; +} + +static inline hri_xdmac_gsws_reg_t hri_xdmac_get_GSWS_reg(const void *const hw, hri_xdmac_gsws_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GSWS; + tmp &= mask; + return tmp; +} + +static inline hri_xdmac_gsws_reg_t hri_xdmac_read_GSWS_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GSWS; +} + +static inline void hri_xdmac_set_GCFG_CGDISREG_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= XDMAC_GCFG_CGDISREG; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GCFG_CGDISREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp = (tmp & XDMAC_GCFG_CGDISREG) >> XDMAC_GCFG_CGDISREG_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GCFG_CGDISREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= ~XDMAC_GCFG_CGDISREG; + tmp |= value << XDMAC_GCFG_CGDISREG_Pos; + ((Xdmac *)hw)->XDMAC_GCFG = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_CGDISREG_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~XDMAC_GCFG_CGDISREG; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_CGDISREG_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= XDMAC_GCFG_CGDISREG; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GCFG_CGDISPIPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= XDMAC_GCFG_CGDISPIPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GCFG_CGDISPIPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp = (tmp & XDMAC_GCFG_CGDISPIPE) >> XDMAC_GCFG_CGDISPIPE_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GCFG_CGDISPIPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= ~XDMAC_GCFG_CGDISPIPE; + tmp |= value << XDMAC_GCFG_CGDISPIPE_Pos; + ((Xdmac *)hw)->XDMAC_GCFG = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_CGDISPIPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~XDMAC_GCFG_CGDISPIPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_CGDISPIPE_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= XDMAC_GCFG_CGDISPIPE; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GCFG_CGDISFIFO_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= XDMAC_GCFG_CGDISFIFO; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GCFG_CGDISFIFO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp = (tmp & XDMAC_GCFG_CGDISFIFO) >> XDMAC_GCFG_CGDISFIFO_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GCFG_CGDISFIFO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= ~XDMAC_GCFG_CGDISFIFO; + tmp |= value << XDMAC_GCFG_CGDISFIFO_Pos; + ((Xdmac *)hw)->XDMAC_GCFG = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_CGDISFIFO_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~XDMAC_GCFG_CGDISFIFO; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_CGDISFIFO_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= XDMAC_GCFG_CGDISFIFO; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GCFG_CGDISIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= XDMAC_GCFG_CGDISIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GCFG_CGDISIF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp = (tmp & XDMAC_GCFG_CGDISIF) >> XDMAC_GCFG_CGDISIF_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GCFG_CGDISIF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= ~XDMAC_GCFG_CGDISIF; + tmp |= value << XDMAC_GCFG_CGDISIF_Pos; + ((Xdmac *)hw)->XDMAC_GCFG = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_CGDISIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~XDMAC_GCFG_CGDISIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_CGDISIF_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= XDMAC_GCFG_CGDISIF; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GCFG_BXKBEN_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= XDMAC_GCFG_BXKBEN; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GCFG_BXKBEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp = (tmp & XDMAC_GCFG_BXKBEN) >> XDMAC_GCFG_BXKBEN_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GCFG_BXKBEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= ~XDMAC_GCFG_BXKBEN; + tmp |= value << XDMAC_GCFG_BXKBEN_Pos; + ((Xdmac *)hw)->XDMAC_GCFG = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_BXKBEN_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~XDMAC_GCFG_BXKBEN; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_BXKBEN_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= XDMAC_GCFG_BXKBEN; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GCFG_reg(const void *const hw, hri_xdmac_gcfg_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gcfg_reg_t hri_xdmac_get_GCFG_reg(const void *const hw, hri_xdmac_gcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GCFG; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_GCFG_reg(const void *const hw, hri_xdmac_gcfg_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GCFG_reg(const void *const hw, hri_xdmac_gcfg_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GCFG_reg(const void *const hw, hri_xdmac_gcfg_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GCFG ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gcfg_reg_t hri_xdmac_read_GCFG_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GCFG; +} + +static inline void hri_xdmac_set_GWAC_PW0_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC |= XDMAC_GWAC_PW0(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_get_GWAC_PW0_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW0(mask)) >> XDMAC_GWAC_PW0_Pos; + return tmp; +} + +static inline void hri_xdmac_write_GWAC_PW0_bf(const void *const hw, hri_xdmac_gwac_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp &= ~XDMAC_GWAC_PW0_Msk; + tmp |= XDMAC_GWAC_PW0(data); + ((Xdmac *)hw)->XDMAC_GWAC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWAC_PW0_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC &= ~XDMAC_GWAC_PW0(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWAC_PW0_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC ^= XDMAC_GWAC_PW0(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_read_GWAC_PW0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW0_Msk) >> XDMAC_GWAC_PW0_Pos; + return tmp; +} + +static inline void hri_xdmac_set_GWAC_PW1_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC |= XDMAC_GWAC_PW1(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_get_GWAC_PW1_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW1(mask)) >> XDMAC_GWAC_PW1_Pos; + return tmp; +} + +static inline void hri_xdmac_write_GWAC_PW1_bf(const void *const hw, hri_xdmac_gwac_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp &= ~XDMAC_GWAC_PW1_Msk; + tmp |= XDMAC_GWAC_PW1(data); + ((Xdmac *)hw)->XDMAC_GWAC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWAC_PW1_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC &= ~XDMAC_GWAC_PW1(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWAC_PW1_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC ^= XDMAC_GWAC_PW1(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_read_GWAC_PW1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW1_Msk) >> XDMAC_GWAC_PW1_Pos; + return tmp; +} + +static inline void hri_xdmac_set_GWAC_PW2_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC |= XDMAC_GWAC_PW2(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_get_GWAC_PW2_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW2(mask)) >> XDMAC_GWAC_PW2_Pos; + return tmp; +} + +static inline void hri_xdmac_write_GWAC_PW2_bf(const void *const hw, hri_xdmac_gwac_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp &= ~XDMAC_GWAC_PW2_Msk; + tmp |= XDMAC_GWAC_PW2(data); + ((Xdmac *)hw)->XDMAC_GWAC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWAC_PW2_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC &= ~XDMAC_GWAC_PW2(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWAC_PW2_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC ^= XDMAC_GWAC_PW2(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_read_GWAC_PW2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW2_Msk) >> XDMAC_GWAC_PW2_Pos; + return tmp; +} + +static inline void hri_xdmac_set_GWAC_PW3_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC |= XDMAC_GWAC_PW3(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_get_GWAC_PW3_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW3(mask)) >> XDMAC_GWAC_PW3_Pos; + return tmp; +} + +static inline void hri_xdmac_write_GWAC_PW3_bf(const void *const hw, hri_xdmac_gwac_reg_t data) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp &= ~XDMAC_GWAC_PW3_Msk; + tmp |= XDMAC_GWAC_PW3(data); + ((Xdmac *)hw)->XDMAC_GWAC = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWAC_PW3_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC &= ~XDMAC_GWAC_PW3(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWAC_PW3_bf(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC ^= XDMAC_GWAC_PW3(mask); + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_read_GWAC_PW3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp = (tmp & XDMAC_GWAC_PW3_Msk) >> XDMAC_GWAC_PW3_Pos; + return tmp; +} + +static inline void hri_xdmac_set_GWAC_reg(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_get_GWAC_reg(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWAC; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_GWAC_reg(const void *const hw, hri_xdmac_gwac_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWAC_reg(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWAC_reg(const void *const hw, hri_xdmac_gwac_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWAC ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gwac_reg_t hri_xdmac_read_GWAC_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GWAC; +} + +static inline void hri_xdmac_set_GRS_RS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS0) >> XDMAC_GRS_RS0_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS0; + tmp |= value << XDMAC_GRS_RS0_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS1) >> XDMAC_GRS_RS1_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS1; + tmp |= value << XDMAC_GRS_RS1_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS2) >> XDMAC_GRS_RS2_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS2; + tmp |= value << XDMAC_GRS_RS2_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS3) >> XDMAC_GRS_RS3_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS3; + tmp |= value << XDMAC_GRS_RS3_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS4) >> XDMAC_GRS_RS4_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS4; + tmp |= value << XDMAC_GRS_RS4_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS5) >> XDMAC_GRS_RS5_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS5; + tmp |= value << XDMAC_GRS_RS5_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS6) >> XDMAC_GRS_RS6_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS6; + tmp |= value << XDMAC_GRS_RS6_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS7) >> XDMAC_GRS_RS7_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS7; + tmp |= value << XDMAC_GRS_RS7_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS8) >> XDMAC_GRS_RS8_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS8; + tmp |= value << XDMAC_GRS_RS8_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS9) >> XDMAC_GRS_RS9_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS9; + tmp |= value << XDMAC_GRS_RS9_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS10) >> XDMAC_GRS_RS10_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS10; + tmp |= value << XDMAC_GRS_RS10_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS11) >> XDMAC_GRS_RS11_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS11; + tmp |= value << XDMAC_GRS_RS11_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS12) >> XDMAC_GRS_RS12_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS12; + tmp |= value << XDMAC_GRS_RS12_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS13) >> XDMAC_GRS_RS13_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS13; + tmp |= value << XDMAC_GRS_RS13_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS14) >> XDMAC_GRS_RS14_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS14; + tmp |= value << XDMAC_GRS_RS14_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS15) >> XDMAC_GRS_RS15_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS15; + tmp |= value << XDMAC_GRS_RS15_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS16) >> XDMAC_GRS_RS16_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS16; + tmp |= value << XDMAC_GRS_RS16_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS17) >> XDMAC_GRS_RS17_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS17; + tmp |= value << XDMAC_GRS_RS17_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS18) >> XDMAC_GRS_RS18_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS18; + tmp |= value << XDMAC_GRS_RS18_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS19) >> XDMAC_GRS_RS19_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS19; + tmp |= value << XDMAC_GRS_RS19_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS20) >> XDMAC_GRS_RS20_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS20; + tmp |= value << XDMAC_GRS_RS20_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS21) >> XDMAC_GRS_RS21_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS21; + tmp |= value << XDMAC_GRS_RS21_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS22) >> XDMAC_GRS_RS22_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS22; + tmp |= value << XDMAC_GRS_RS22_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_RS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= XDMAC_GRS_RS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GRS_RS23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp = (tmp & XDMAC_GRS_RS23) >> XDMAC_GRS_RS23_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GRS_RS23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= ~XDMAC_GRS_RS23; + tmp |= value << XDMAC_GRS_RS23_Pos; + ((Xdmac *)hw)->XDMAC_GRS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_RS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~XDMAC_GRS_RS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_RS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= XDMAC_GRS_RS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GRS_reg(const void *const hw, hri_xdmac_grs_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_grs_reg_t hri_xdmac_get_GRS_reg(const void *const hw, hri_xdmac_grs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GRS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_GRS_reg(const void *const hw, hri_xdmac_grs_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GRS_reg(const void *const hw, hri_xdmac_grs_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GRS_reg(const void *const hw, hri_xdmac_grs_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_grs_reg_t hri_xdmac_read_GRS_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GRS; +} + +static inline void hri_xdmac_set_GWS_WS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS0) >> XDMAC_GWS_WS0_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS0; + tmp |= value << XDMAC_GWS_WS0_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS0_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS0; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS1) >> XDMAC_GWS_WS1_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS1; + tmp |= value << XDMAC_GWS_WS1_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS1_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS1; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS2) >> XDMAC_GWS_WS2_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS2; + tmp |= value << XDMAC_GWS_WS2_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS2_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS2; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS3) >> XDMAC_GWS_WS3_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS3; + tmp |= value << XDMAC_GWS_WS3_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS3_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS3; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS4) >> XDMAC_GWS_WS4_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS4; + tmp |= value << XDMAC_GWS_WS4_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS4_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS4; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS5) >> XDMAC_GWS_WS5_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS5; + tmp |= value << XDMAC_GWS_WS5_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS5_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS5; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS6) >> XDMAC_GWS_WS6_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS6; + tmp |= value << XDMAC_GWS_WS6_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS6_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS6; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS7) >> XDMAC_GWS_WS7_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS7; + tmp |= value << XDMAC_GWS_WS7_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS7_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS7; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS8) >> XDMAC_GWS_WS8_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS8; + tmp |= value << XDMAC_GWS_WS8_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS8_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS8; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS9) >> XDMAC_GWS_WS9_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS9; + tmp |= value << XDMAC_GWS_WS9_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS9_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS9; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS10) >> XDMAC_GWS_WS10_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS10; + tmp |= value << XDMAC_GWS_WS10_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS10_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS10; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS11) >> XDMAC_GWS_WS11_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS11; + tmp |= value << XDMAC_GWS_WS11_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS11_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS11; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS12) >> XDMAC_GWS_WS12_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS12; + tmp |= value << XDMAC_GWS_WS12_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS12_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS12; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS13) >> XDMAC_GWS_WS13_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS13; + tmp |= value << XDMAC_GWS_WS13_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS13_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS13; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS14) >> XDMAC_GWS_WS14_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS14; + tmp |= value << XDMAC_GWS_WS14_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS14_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS14; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS15) >> XDMAC_GWS_WS15_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS15; + tmp |= value << XDMAC_GWS_WS15_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS15_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS15; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS16) >> XDMAC_GWS_WS16_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS16; + tmp |= value << XDMAC_GWS_WS16_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS16_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS16; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS17) >> XDMAC_GWS_WS17_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS17; + tmp |= value << XDMAC_GWS_WS17_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS17_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS17; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS18) >> XDMAC_GWS_WS18_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS18; + tmp |= value << XDMAC_GWS_WS18_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS18_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS18; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS19) >> XDMAC_GWS_WS19_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS19; + tmp |= value << XDMAC_GWS_WS19_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS19_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS19; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS20) >> XDMAC_GWS_WS20_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS20; + tmp |= value << XDMAC_GWS_WS20_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS20_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS20; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS21) >> XDMAC_GWS_WS21_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS21; + tmp |= value << XDMAC_GWS_WS21_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS21_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS21; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS22) >> XDMAC_GWS_WS22_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS22; + tmp |= value << XDMAC_GWS_WS22_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS22_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS22; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_WS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= XDMAC_GWS_WS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_xdmac_get_GWS_WS23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp = (tmp & XDMAC_GWS_WS23) >> XDMAC_GWS_WS23_Pos; + return (bool)tmp; +} + +static inline void hri_xdmac_write_GWS_WS23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + XDMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= ~XDMAC_GWS_WS23; + tmp |= value << XDMAC_GWS_WS23_Pos; + ((Xdmac *)hw)->XDMAC_GWS = tmp; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_WS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~XDMAC_GWS_WS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_WS23_bit(const void *const hw) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= XDMAC_GWS_WS23; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_set_GWS_reg(const void *const hw, hri_xdmac_gws_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS |= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gws_reg_t hri_xdmac_get_GWS_reg(const void *const hw, hri_xdmac_gws_reg_t mask) +{ + uint32_t tmp; + tmp = ((Xdmac *)hw)->XDMAC_GWS; + tmp &= mask; + return tmp; +} + +static inline void hri_xdmac_write_GWS_reg(const void *const hw, hri_xdmac_gws_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_clear_GWS_reg(const void *const hw, hri_xdmac_gws_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS &= ~mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_toggle_GWS_reg(const void *const hw, hri_xdmac_gws_reg_t mask) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GWS ^= mask; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_xdmac_gws_reg_t hri_xdmac_read_GWS_reg(const void *const hw) +{ + return ((Xdmac *)hw)->XDMAC_GWS; +} + +static inline void hri_xdmac_write_GRWS_reg(const void *const hw, hri_xdmac_grws_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRWS = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_write_GRWR_reg(const void *const hw, hri_xdmac_grwr_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GRWR = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_write_GSWR_reg(const void *const hw, hri_xdmac_gswr_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GSWR = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_xdmac_write_GSWF_reg(const void *const hw, hri_xdmac_gswf_reg_t data) +{ + XDMAC_CRITICAL_SECTION_ENTER(); + ((Xdmac *)hw)->XDMAC_GSWF = data; + XDMAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_XDMAC_E70B_H_INCLUDED */ +#endif /* _SAME70_XDMAC_COMPONENT_ */ diff --git a/bsp/microchip/same70/bsp/iar-project-connection.ipcf b/bsp/microchip/same70/bsp/iar-project-connection.ipcf new file mode 100644 index 0000000000..05099d8482 --- /dev/null +++ b/bsp/microchip/same70/bsp/iar-project-connection.ipcf @@ -0,0 +1,383 @@ + + + + ATSAME70Q21B + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\mcan + $PROJ_DIR$\hpl\pio + $PROJ_DIR$\hpl\pmc + $PROJ_DIR$\hpl\systick + $PROJ_DIR$\hpl\usart + $PROJ_DIR$\hpl\xdmac + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\same70b\include + + + + $PROJ_DIR$\ + $PROJ_DIR$\config + $PROJ_DIR$\examples + $PROJ_DIR$\hal\include + $PROJ_DIR$\hal\utils\include + $PROJ_DIR$\hpl\core + $PROJ_DIR$\hpl\mcan + $PROJ_DIR$\hpl\pio + $PROJ_DIR$\hpl\pmc + $PROJ_DIR$\hpl\systick + $PROJ_DIR$\hpl\usart + $PROJ_DIR$\hpl\xdmac + $PROJ_DIR$\hri + $PROJ_DIR$\ + $PROJ_DIR$\CMSIS\Core\Include + $PROJ_DIR$\same70b\include + + + + __SAME70Q21B__ + F_CPU=300000000 + + + + __SAME70Q21B__ + + + + True + $PROJ_DIR$\same70b\iar\config\linker\Microchip\atsame70q21b\sram.icf + + + + + atmel_start.c + atmel_start.h + atmel_start_pins.h + driver_init.c + driver_init.h + led_switcher_main.c + + + + CMSIS/Core/Include/cmsis_armcc.h + CMSIS/Core/Include/cmsis_armclang.h + CMSIS/Core/Include/cmsis_compiler.h + CMSIS/Core/Include/cmsis_gcc.h + CMSIS/Core/Include/cmsis_iccarm.h + CMSIS/Core/Include/cmsis_version.h + CMSIS/Core/Include/core_armv8mbl.h + CMSIS/Core/Include/core_armv8mml.h + CMSIS/Core/Include/core_cm0.h + CMSIS/Core/Include/core_cm0plus.h + CMSIS/Core/Include/core_cm1.h + CMSIS/Core/Include/core_cm23.h + CMSIS/Core/Include/core_cm3.h + CMSIS/Core/Include/core_cm33.h + CMSIS/Core/Include/core_cm4.h + CMSIS/Core/Include/core_cm7.h + CMSIS/Core/Include/core_sc000.h + CMSIS/Core/Include/core_sc300.h + CMSIS/Core/Include/mpu_armv7.h + CMSIS/Core/Include/mpu_armv8.h + CMSIS/Core/Include/tz_context.h + + + + config/hpl_mcan_config.h + config/hpl_pmc_config.h + config/hpl_systick_ARMv7_config.h + config/hpl_usart_config.h + config/hpl_xdmac_config.h + config/peripheral_clk_config.h + + + + examples/driver_examples.c + examples/driver_examples.h + + + + hal/include/hal_atomic.h + hal/include/hal_can_async.h + hal/include/hal_delay.h + hal/include/hal_gpio.h + hal/include/hal_init.h + hal/include/hal_io.h + hal/include/hal_sleep.h + hal/include/hal_usart_sync.h + hal/include/hpl_can.h + hal/include/hpl_can_async.h + hal/include/hpl_core.h + hal/include/hpl_delay.h + hal/include/hpl_dma.h + hal/include/hpl_ext_irq.h + hal/include/hpl_gpio.h + hal/include/hpl_init.h + hal/include/hpl_irq.h + hal/include/hpl_missing_features.h + hal/include/hpl_reset.h + hal/include/hpl_sleep.h + hal/include/hpl_time_measure.h + hal/include/hpl_usart.h + hal/include/hpl_usart_async.h + hal/include/hpl_usart_dma.h + hal/include/hpl_usart_sync.h + + + + hal/src/hal_atomic.c + hal/src/hal_can_async.c + hal/src/hal_delay.c + hal/src/hal_gpio.c + hal/src/hal_init.c + hal/src/hal_io.c + hal/src/hal_sleep.c + hal/src/hal_usart_sync.c + + + + hal/utils/include/compiler.h + hal/utils/include/err_codes.h + hal/utils/include/events.h + hal/utils/include/parts.h + hal/utils/include/utils.h + hal/utils/include/utils_assert.h + hal/utils/include/utils_event.h + hal/utils/include/utils_increment_macro.h + hal/utils/include/utils_list.h + hal/utils/include/utils_repeat_macro.h + hal/utils/include/utils_ringbuffer.h + + + + hal/utils/src/utils_assert.c + hal/utils/src/utils_event.c + hal/utils/src/utils_list.c + hal/utils/src/utils_ringbuffer.c + + + + hpl/core/hpl_core_m7_base.c + hpl/core/hpl_core_port.h + hpl/core/hpl_init.c + + + + hpl/mcan/hpl_mcan.c + hpl/mcan/hpl_mcan.h + + + + hpl/pio/hpl_gpio_base.h + + + + hpl/pmc/hpl_pmc.c + hpl/pmc/hpl_pmc.h + hpl/pmc/hpl_sleep.c + + + + hpl/systick/hpl_systick_ARMv7_base.c + + + + hpl/usart/hpl_usart.c + hpl/usart/hpl_usart_base.h + + + + hpl/xdmac/hpl_xdmac.c + + + + hri/hri_acc_e70b.h + hri/hri_aes_e70b.h + hri/hri_afec_e70b.h + hri/hri_chipid_e70b.h + hri/hri_dacc_e70b.h + hri/hri_e70b.h + hri/hri_efc_e70b.h + hri/hri_gmac_e70b.h + hri/hri_gpbr_e70b.h + hri/hri_hsmci_e70b.h + hri/hri_i2sc_e70b.h + hri/hri_icm_e70b.h + hri/hri_isi_e70b.h + hri/hri_lockbit_e70b.h + hri/hri_matrix_e70b.h + hri/hri_mcan_e70b.h + hri/hri_pio_e70b.h + hri/hri_pmc_e70b.h + hri/hri_pwm_e70b.h + hri/hri_qspi_e70b.h + hri/hri_rstc_e70b.h + hri/hri_rswdt_e70b.h + hri/hri_rtc_e70b.h + hri/hri_rtt_e70b.h + hri/hri_sdramc_e70b.h + hri/hri_smc_e70b.h + hri/hri_spi_e70b.h + hri/hri_ssc_e70b.h + hri/hri_supc_e70b.h + hri/hri_tc_e70b.h + hri/hri_trng_e70b.h + hri/hri_twihs_e70b.h + hri/hri_uart_e70b.h + hri/hri_usart_e70b.h + hri/hri_usbhs_e70b.h + hri/hri_utmi_e70b.h + hri/hri_wdt_e70b.h + hri/hri_xdmac_e70b.h + + + + same70b/iar/system_same70q21b.c + + + + same70b/iar/iar/startup_same70q21b.c + + + + same70b/include/component-version.h + same70b/include/sam.h + same70b/include/sam.h + same70b/include/same70j19b.h + same70b/include/same70j20b.h + same70b/include/same70j21b.h + same70b/include/same70n19b.h + same70b/include/same70n20b.h + same70b/include/same70n21b.h + same70b/include/same70q19b.h + same70b/include/same70q20b.h + same70b/include/same70q21b.h + same70b/include/system_same70.h + + + + same70b/include/component/acc.h + same70b/include/component/aes.h + same70b/include/component/afec.h + same70b/include/component/chipid.h + same70b/include/component/dacc.h + same70b/include/component/efc.h + same70b/include/component/gmac.h + same70b/include/component/gpbr.h + same70b/include/component/hsmci.h + same70b/include/component/i2sc.h + same70b/include/component/icm.h + same70b/include/component/isi.h + same70b/include/component/matrix.h + same70b/include/component/mcan.h + same70b/include/component/pio.h + same70b/include/component/pmc.h + same70b/include/component/pwm.h + same70b/include/component/qspi.h + same70b/include/component/rstc.h + same70b/include/component/rswdt.h + same70b/include/component/rtc.h + same70b/include/component/rtt.h + same70b/include/component/sdramc.h + same70b/include/component/smc.h + same70b/include/component/spi.h + same70b/include/component/ssc.h + same70b/include/component/supc.h + same70b/include/component/tc.h + same70b/include/component/trng.h + same70b/include/component/twihs.h + same70b/include/component/uart.h + same70b/include/component/usart.h + same70b/include/component/usbhs.h + same70b/include/component/utmi.h + same70b/include/component/wdt.h + same70b/include/component/xdmac.h + + + + same70b/include/component/deprecated/tc.h + same70b/include/component/deprecated/template.h + same70b/include/component/deprecated/usart.h + same70b/include/component/deprecated/usbhs.h + + + + same70b/include/instance/acc.h + same70b/include/instance/aes.h + same70b/include/instance/afec0.h + same70b/include/instance/afec1.h + same70b/include/instance/chipid.h + same70b/include/instance/dacc.h + same70b/include/instance/efc.h + same70b/include/instance/gmac.h + same70b/include/instance/gpbr.h + same70b/include/instance/hsmci.h + same70b/include/instance/i2sc0.h + same70b/include/instance/i2sc1.h + same70b/include/instance/icm.h + same70b/include/instance/isi.h + same70b/include/instance/matrix.h + same70b/include/instance/mcan0.h + same70b/include/instance/mcan1.h + same70b/include/instance/pioa.h + same70b/include/instance/piob.h + same70b/include/instance/pioc.h + same70b/include/instance/piod.h + same70b/include/instance/pioe.h + same70b/include/instance/pmc.h + same70b/include/instance/pwm0.h + same70b/include/instance/pwm1.h + same70b/include/instance/qspi.h + same70b/include/instance/rstc.h + same70b/include/instance/rswdt.h + same70b/include/instance/rtc.h + same70b/include/instance/rtt.h + same70b/include/instance/sdramc.h + same70b/include/instance/smc.h + same70b/include/instance/spi0.h + same70b/include/instance/spi1.h + same70b/include/instance/ssc.h + same70b/include/instance/supc.h + same70b/include/instance/tc0.h + same70b/include/instance/tc1.h + same70b/include/instance/tc2.h + same70b/include/instance/tc3.h + same70b/include/instance/trng.h + same70b/include/instance/twihs0.h + same70b/include/instance/twihs1.h + same70b/include/instance/twihs2.h + same70b/include/instance/uart0.h + same70b/include/instance/uart1.h + same70b/include/instance/uart2.h + same70b/include/instance/uart3.h + same70b/include/instance/uart4.h + same70b/include/instance/usart0.h + same70b/include/instance/usart1.h + same70b/include/instance/usart2.h + same70b/include/instance/usbhs.h + same70b/include/instance/utmi.h + same70b/include/instance/wdt.h + same70b/include/instance/xdmac.h + + + + same70b/include/pio/same70j19b.h + same70b/include/pio/same70j20b.h + same70b/include/pio/same70j21b.h + same70b/include/pio/same70n19b.h + same70b/include/pio/same70n20b.h + same70b/include/pio/same70n21b.h + same70b/include/pio/same70q19b.h + same70b/include/pio/same70q20b.h + same70b/include/pio/same70q21b.h + + + \ No newline at end of file diff --git a/bsp/microchip/same70/bsp/led_switcher_main.c b/bsp/microchip/same70/bsp/led_switcher_main.c new file mode 100644 index 0000000000..f8da027d77 --- /dev/null +++ b/bsp/microchip/same70/bsp/led_switcher_main.c @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief Application implement + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include "atmel_start.h" +#include +#include + +int main(void) +{ + atmel_start_init(); + + gpio_set_pin_pull_mode(SW0, GPIO_PULL_UP); + + while (true) { + do { + delay_ms(100); + } while (gpio_get_pin_level(SW0)); + + gpio_toggle_pin_level(LED0); + + do { + delay_ms(100); + } while (!gpio_get_pin_level(SW0)); + } +} diff --git a/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/ARM/startup_SAME70.s b/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/ARM/startup_SAME70.s new file mode 100644 index 0000000000..2095c1db7a --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/ARM/startup_SAME70.s @@ -0,0 +1,372 @@ +;/**************************************************************************//** +; * @file startup_SAME70.s +; * @brief CMSIS Core Device Startup File for +; * Atmel SAME70 Device Series +; * @version V1.00 +; * @date 19. January 2015 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2015 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD SUPC_Handler ; 0 Supply Controller + DCD RSTC_Handler ; 1 Reset Controller + DCD RTC_Handler ; 2 Real Time Clock + DCD RTT_Handler ; 3 Real Time Timer + DCD WDT_Handler ; 4 Watchdog Timer + DCD PMC_Handler ; 5 Power Management Controller + DCD EFC_Handler ; 6 Enhanced Embedded Flash Controller + DCD UART0_Handler ; 7 UART 0 + DCD UART1_Handler ; 8 UART 1 + DCD 0 ; 9 Reserved + DCD PIOA_Handler ; 10 Parallel I/O Controller A + DCD PIOB_Handler ; 11 Parallel I/O Controller B + DCD PIOC_Handler ; 12 Parallel I/O Controller C + DCD USART0_Handler ; 13 USART 0 + DCD USART1_Handler ; 14 USART 1 + DCD USART2_Handler ; 15 USART 2 + DCD PIOD_Handler ; 16 Parallel I/O Controller D + DCD PIOE_Handler ; 17 Parallel I/O Controller E + DCD HSMCI_Handler ; 18 Multimedia Card Interface + DCD TWIHS0_Handler ; 19 Two Wire Interface 0 HS + DCD TWIHS1_Handler ; 20 Two Wire Interface 1 HS + DCD SPI0_Handler ; 21 Serial Peripheral Interface 0 + DCD SSC_Handler ; 22 Synchronous Serial Controller + DCD TC0_Handler ; 23 Timer/Counter 0 + DCD TC1_Handler ; 24 Timer/Counter 1 + DCD TC2_Handler ; 25 Timer/Counter 2 + DCD TC3_Handler ; 26 Timer/Counter 3 + DCD TC4_Handler ; 27 Timer/Counter 4 + DCD TC5_Handler ; 28 Timer/Counter 5 + DCD AFEC0_Handler ; 29 Analog Front End 0 + DCD DACC_Handler ; 30 Digital To Analog Converter + DCD PWM0_Handler ; 31 Pulse Width Modulation 0 + DCD ICM_Handler ; 32 Integrity Check Monitor + DCD ACC_Handler ; 33 Analog Comparator + DCD USBHS_Handler ; 34 USB Host / Device Controller + DCD MCAN0_Handler ; 35 MCAN Controller 0 + DCD 0 ; 36 Reserved + DCD MCAN1_Handler ; 37 MCAN Controller 1 + DCD 0 ; 38 Reserved + DCD GMAC_Handler ; 39 Ethernet MAC + DCD AFEC1_Handler ; 40 Analog Front End 1 + DCD TWIHS2_Handler ; 41 Two Wire Interface 2 HS + DCD SPI1_Handler ; 42 Serial Peripheral Interface 1 + DCD QSPI_Handler ; 43 Quad I/O Serial Peripheral Interface + DCD UART2_Handler ; 44 UART 2 + DCD UART3_Handler ; 45 UART 3 + DCD UART4_Handler ; 46 UART 4 + DCD TC6_Handler ; 47 Timer/Counter 6 + DCD TC7_Handler ; 48 Timer/Counter 7 + DCD TC8_Handler ; 49 Timer/Counter 8 + DCD TC9_Handler ; 50 Timer/Counter 9 + DCD TC10_Handler ; 51 Timer/Counter 10 + DCD TC11_Handler ; 52 Timer/Counter 11 + DCD 0 ; 53 Reserved + DCD 0 ; 54 Reserved + DCD 0 ; 55 Reserved + DCD AES_Handler ; 56 AES + DCD TRNG_Handler ; 57 True Random Generator + DCD XDMAC_Handler ; 58 DMA + DCD ISI_Handler ; 59 Camera Interface + DCD PWM1_Handler ; 60 Pulse Width Modulation 1 + DCD 0 ; 61 Reserved + DCD SDRAMC_Handler ; 62 SDRAM Controller + DCD RSWDT_Handler ; 63 Reinforced Secure Watchdog Timer +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SUPC_Handler [WEAK] + EXPORT RSTC_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT RTT_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT PMC_Handler [WEAK] + EXPORT EFC_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT PIOA_Handler [WEAK] + EXPORT PIOB_Handler [WEAK] + EXPORT PIOC_Handler [WEAK] + EXPORT USART0_Handler [WEAK] + EXPORT USART1_Handler [WEAK] + EXPORT USART2_Handler [WEAK] + EXPORT PIOD_Handler [WEAK] + EXPORT PIOE_Handler [WEAK] + EXPORT HSMCI_Handler [WEAK] + EXPORT TWIHS0_Handler [WEAK] + EXPORT TWIHS1_Handler [WEAK] + EXPORT SPI0_Handler [WEAK] + EXPORT SSC_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT AFEC0_Handler [WEAK] + EXPORT DACC_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT ICM_Handler [WEAK] + EXPORT ACC_Handler [WEAK] + EXPORT USBHS_Handler [WEAK] + EXPORT MCAN0_Handler [WEAK] + EXPORT MCAN1_Handler [WEAK] + EXPORT GMAC_Handler [WEAK] + EXPORT AFEC1_Handler [WEAK] + EXPORT TWIHS2_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT UART3_Handler [WEAK] + EXPORT UART4_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT TC8_Handler [WEAK] + EXPORT TC9_Handler [WEAK] + EXPORT TC10_Handler [WEAK] + EXPORT TC11_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT XDMAC_Handler [WEAK] + EXPORT ISI_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT SDRAMC_Handler [WEAK] + EXPORT RSWDT_Handler [WEAK] + +SUPC_Handler +RSTC_Handler +RTC_Handler +RTT_Handler +WDT_Handler +PMC_Handler +EFC_Handler +UART0_Handler +UART1_Handler +PIOA_Handler +PIOB_Handler +PIOC_Handler +USART0_Handler +USART1_Handler +USART2_Handler +PIOD_Handler +PIOE_Handler +HSMCI_Handler +TWIHS0_Handler +TWIHS1_Handler +SPI0_Handler +SSC_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +AFEC0_Handler +DACC_Handler +PWM0_Handler +ICM_Handler +ACC_Handler +USBHS_Handler +MCAN0_Handler +MCAN1_Handler +GMAC_Handler +AFEC1_Handler +TWIHS2_Handler +SPI1_Handler +QSPI_Handler +UART2_Handler +UART3_Handler +UART4_Handler +TC6_Handler +TC7_Handler +TC8_Handler +TC9_Handler +TC10_Handler +TC11_Handler +AES_Handler +TRNG_Handler +XDMAC_Handler +ISI_Handler +PWM1_Handler +SDRAMC_Handler +RSWDT_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/system_same70q21b.c b/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/system_same70q21b.c new file mode 100644 index 0000000000..35645b74b5 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/armcc/Device/Source/system_same70q21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q21B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_flash.ld b/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_flash.ld new file mode 100644 index 0000000000..f09a9ebda1 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_flash.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + __bss_end = _end; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_sram.ld b/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_sram.ld new file mode 100644 index 0000000000..5fa18af699 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/gcc/gcc/same70q21b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/bsp/microchip/same70/bsp/same70b/gcc/gcc/startup_same70q21b.c b/bsp/microchip/same70/bsp/same70b/gcc/gcc/startup_same70q21b.c new file mode 100644 index 0000000000..1133402860 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/gcc/gcc/startup_same70q21b.c @@ -0,0 +1,284 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RSTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PMC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EFC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UART0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UART1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PIOA_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PIOB_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PIOC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void USART0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void USART1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void USART2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PIOD_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PIOE_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HSMCI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SPI0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SSC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void AFEC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DACC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PWM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void ACC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void USBHS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void AFEC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SPI1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UART2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UART3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UART4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void XDMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void ISI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PWM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void FPU_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RSWDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void CCW_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void CCF_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void IXC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void I2SC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void I2SC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__((section(".vectors"))) const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pfnMemoryManagement_Handler = (void *)MemoryManagement_Handler, + .pfnBusFault_Handler = (void *)BusFault_Handler, + .pfnUsageFault_Handler = (void *)UsageFault_Handler, + .pvReservedC9 = (void *)(0UL), /* Reserved */ + .pvReservedC8 = (void *)(0UL), /* Reserved */ + .pvReservedC7 = (void *)(0UL), /* Reserved */ + .pvReservedC6 = (void *)(0UL), /* Reserved */ + .pfnSVCall_Handler = (void *)SVCall_Handler, + .pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler, + .pvReservedC3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void *)SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void *)RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void *)RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void *)PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void *)EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void *)UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void *)UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void *)(0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void *)PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void *)PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void *)PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void *)USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void *)USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void *)USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void *)PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void *)PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void *)HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void *)TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void *)TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void *)SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void *)SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void *)TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void *)TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void *)TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void *)TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void *)TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void *)AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void *)DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void *)PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void *)ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void *)ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void *)USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void *)MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void *)MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void *)MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void *)MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void *)GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void *)AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void *)TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void *)SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void *)QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void *)UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void *)UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void *)UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void *)TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void *)TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void *)TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void *)TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void *)TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void *)TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void *)(0UL), /* 53 Reserved */ + .pvReserved54 = (void *)(0UL), /* 54 Reserved */ + .pvReserved55 = (void *)(0UL), /* 55 Reserved */ + .pfnAES_Handler = (void *)AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void *)TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void *)XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void *)ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void *)PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void *)FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void *)SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void *)RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void *)CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void *)CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void *)GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void *)GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void *)IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void *)I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pfnI2SC1_Handler = (void *)I2SC1_Handler, /* 70 Inter-IC Sound Controller */ + .pfnGMAC_Q3_Handler = (void *)GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void *)GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void *)GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +int rtthread_startup(void); + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to rtthread_startup function */ + rtthread_startup(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/same70/bsp/same70b/gcc/system_same70q21b.c b/bsp/microchip/same70/bsp/same70b/gcc/system_same70q21b.c new file mode 100644 index 0000000000..1fae07c1cb --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/gcc/system_same70q21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf b/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf new file mode 100644 index 0000000000..cc0b751620 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/flash.icf @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief IAR linker script (flash) for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00400000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20400000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2045FFFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x00400000; +define symbol __ICFEDIT_region_ROM_end__ = 0x005FFFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x0400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0200; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; +place in RAM_region { readwrite, block HEAP }; +place at end of RAM_region { block CSTACK }; diff --git a/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/sram.icf b/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/sram.icf new file mode 100644 index 0000000000..3b2342b016 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/iar/config/linker/Microchip/atsame70q21b/sram.icf @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief IAR linker script (sram) for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20400000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20400000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2045FFFF; +/*-Sizes-*/ +if (!isdefinedsymbol(__ICFEDIT_size_cstack__)) { + define symbol __ICFEDIT_size_cstack__ = 0x0400; +} +if (!isdefinedsymbol(__ICFEDIT_size_heap__)) { + define symbol __ICFEDIT_size_heap__ = 0x0200; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place in RAM_region { readonly }; +place in RAM_region { readwrite, block HEAP }; +place at end of RAM_region { block CSTACK }; diff --git a/bsp/microchip/same70/bsp/same70b/iar/iar/startup_same70q21b.c b/bsp/microchip/same70/bsp/same70b/iar/iar/startup_same70q21b.c new file mode 100644 index 0000000000..efac3e9caf --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/iar/iar/startup_same70q21b.c @@ -0,0 +1,265 @@ +/** + * \file + * + * \brief IAR startup file for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +typedef void (*intfunc)(void); +typedef union { + intfunc __fun; + void * __ptr; +} intvec_elem; + +void __iar_program_start(void); +int __low_level_init(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +#pragma weak NonMaskableInt_Handler = Dummy_Handler +#pragma weak HardFault_Handler = Dummy_Handler +#pragma weak MemoryManagement_Handler = Dummy_Handler +#pragma weak BusFault_Handler = Dummy_Handler +#pragma weak UsageFault_Handler = Dummy_Handler +#pragma weak SVCall_Handler = Dummy_Handler +#pragma weak DebugMonitor_Handler = Dummy_Handler +#pragma weak PendSV_Handler = Dummy_Handler +#pragma weak SysTick_Handler = Dummy_Handler + +/* Peripherals handlers */ +#pragma weak SUPC_Handler = Dummy_Handler +#pragma weak RSTC_Handler = Dummy_Handler +#pragma weak RTC_Handler = Dummy_Handler +#pragma weak RTT_Handler = Dummy_Handler +#pragma weak WDT_Handler = Dummy_Handler +#pragma weak PMC_Handler = Dummy_Handler +#pragma weak EFC_Handler = Dummy_Handler +#pragma weak UART0_Handler = Dummy_Handler +#pragma weak UART1_Handler = Dummy_Handler +#pragma weak PIOA_Handler = Dummy_Handler +#pragma weak PIOB_Handler = Dummy_Handler +#pragma weak PIOC_Handler = Dummy_Handler +#pragma weak USART0_Handler = Dummy_Handler +#pragma weak USART1_Handler = Dummy_Handler +#pragma weak USART2_Handler = Dummy_Handler +#pragma weak PIOD_Handler = Dummy_Handler +#pragma weak PIOE_Handler = Dummy_Handler +#pragma weak HSMCI_Handler = Dummy_Handler +#pragma weak TWIHS0_Handler = Dummy_Handler +#pragma weak TWIHS1_Handler = Dummy_Handler +#pragma weak SPI0_Handler = Dummy_Handler +#pragma weak SSC_Handler = Dummy_Handler +#pragma weak TC0_Handler = Dummy_Handler +#pragma weak TC1_Handler = Dummy_Handler +#pragma weak TC2_Handler = Dummy_Handler +#pragma weak TC3_Handler = Dummy_Handler +#pragma weak TC4_Handler = Dummy_Handler +#pragma weak TC5_Handler = Dummy_Handler +#pragma weak AFEC0_Handler = Dummy_Handler +#pragma weak DACC_Handler = Dummy_Handler +#pragma weak PWM0_Handler = Dummy_Handler +#pragma weak ICM_Handler = Dummy_Handler +#pragma weak ACC_Handler = Dummy_Handler +#pragma weak USBHS_Handler = Dummy_Handler +#pragma weak MCAN0_INT0_Handler = Dummy_Handler +#pragma weak MCAN0_INT1_Handler = Dummy_Handler +#pragma weak MCAN1_INT0_Handler = Dummy_Handler +#pragma weak MCAN1_INT1_Handler = Dummy_Handler +#pragma weak GMAC_Handler = Dummy_Handler +#pragma weak AFEC1_Handler = Dummy_Handler +#pragma weak TWIHS2_Handler = Dummy_Handler +#pragma weak SPI1_Handler = Dummy_Handler +#pragma weak QSPI_Handler = Dummy_Handler +#pragma weak UART2_Handler = Dummy_Handler +#pragma weak UART3_Handler = Dummy_Handler +#pragma weak UART4_Handler = Dummy_Handler +#pragma weak TC6_Handler = Dummy_Handler +#pragma weak TC7_Handler = Dummy_Handler +#pragma weak TC8_Handler = Dummy_Handler +#pragma weak TC9_Handler = Dummy_Handler +#pragma weak TC10_Handler = Dummy_Handler +#pragma weak TC11_Handler = Dummy_Handler +#pragma weak AES_Handler = Dummy_Handler +#pragma weak TRNG_Handler = Dummy_Handler +#pragma weak XDMAC_Handler = Dummy_Handler +#pragma weak ISI_Handler = Dummy_Handler +#pragma weak PWM1_Handler = Dummy_Handler +#pragma weak FPU_Handler = Dummy_Handler +#pragma weak SDRAMC_Handler = Dummy_Handler +#pragma weak RSWDT_Handler = Dummy_Handler +#pragma weak CCW_Handler = Dummy_Handler +#pragma weak CCF_Handler = Dummy_Handler +#pragma weak GMAC_Q1_Handler = Dummy_Handler +#pragma weak GMAC_Q2_Handler = Dummy_Handler +#pragma weak IXC_Handler = Dummy_Handler +#pragma weak I2SC0_Handler = Dummy_Handler +#pragma weak I2SC1_Handler = Dummy_Handler +#pragma weak GMAC_Q3_Handler = Dummy_Handler +#pragma weak GMAC_Q4_Handler = Dummy_Handler +#pragma weak GMAC_Q5_Handler = Dummy_Handler + +/* Exception Table */ +#pragma language = extended +#pragma segment = "CSTACK" + +/* The name "__vector_table" has special meaning for C-SPY: */ +/* it is where the SP start value is found, and the NVIC vector */ +/* table register (VTOR) is initialized to this address if != 0 */ + +#pragma section = ".intvec" +#pragma location = ".intvec" +const DeviceVectors __vector_table = { + (void *)__sfe("CSTACK"), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pfnMemoryManagement_Handler = (void *)MemoryManagement_Handler, + .pfnBusFault_Handler = (void *)BusFault_Handler, + .pfnUsageFault_Handler = (void *)UsageFault_Handler, + .pvReservedC9 = (void *)(0UL), /* Reserved */ + .pvReservedC8 = (void *)(0UL), /* Reserved */ + .pvReservedC7 = (void *)(0UL), /* Reserved */ + .pvReservedC6 = (void *)(0UL), /* Reserved */ + .pfnSVCall_Handler = (void *)SVCall_Handler, + .pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler, + .pvReservedC3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void *)SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void *)RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void *)RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void *)PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void *)EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void *)UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void *)UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void *)(0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void *)PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void *)PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void *)PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void *)USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void *)USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void *)USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void *)PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void *)PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void *)HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void *)TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void *)TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void *)SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void *)SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void *)TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void *)TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void *)TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void *)TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void *)TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void *)AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void *)DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void *)PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void *)ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void *)ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void *)USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void *)MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void *)MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void *)MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void *)MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void *)GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void *)AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void *)TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void *)SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void *)QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void *)UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void *)UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void *)UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void *)TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void *)TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void *)TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void *)TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void *)TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void *)TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void *)(0UL), /* 53 Reserved */ + .pvReserved54 = (void *)(0UL), /* 54 Reserved */ + .pvReserved55 = (void *)(0UL), /* 55 Reserved */ + .pfnAES_Handler = (void *)AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void *)TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void *)XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void *)ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void *)PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void *)FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void *)SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void *)RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void *)CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void *)CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void *)GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void *)GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void *)IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void *)I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pfnI2SC1_Handler = (void *)I2SC1_Handler, /* 70 Inter-IC Sound Controller */ + .pfnGMAC_Q3_Handler = (void *)GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void *)GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void *)GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +int __low_level_init(void) +{ + uint32_t *pSrc = __section_begin(".intvec"); + + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + return 1; /* if return 0, the data sections will not be initialized */ +} + +/**------------------------------------------------------------------------------ + * This is the code that gets called on processor reset. To initialize the + * device. + *------------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __iar_program_start(); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/bsp/microchip/same70/bsp/same70b/iar/system_same70q21b.c b/bsp/microchip/same70/bsp/same70b/iar/system_same70q21b.c new file mode 100644 index 0000000000..1fae07c1cb --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/iar/system_same70q21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component-version.h b/bsp/microchip/same70/bsp/same70b/include/component-version.h new file mode 100644 index 0000000000..ea269d46bb --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 2 +#define COMPONENT_VERSION_MINOR 4 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 20004 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 166 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "2.4" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2019-02-18 11:43:38" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/bsp/microchip/same70/bsp/same70b/include/component/acc.h b/bsp/microchip/same70/bsp/same70b/include/component/acc.h new file mode 100644 index 0000000000..e8606d42eb --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/acc.h @@ -0,0 +1,390 @@ +/** + * \file + * + * \brief Component description for ACC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ACC_COMPONENT_H_ +#define _SAME70_ACC_COMPONENT_H_ +#define _SAME70_ACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Analog Comparator Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ACC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define ACC_6490 /**< (ACC) Module ID */ +#define REV_ACC J /**< (ACC) Module revision */ + +/* -------- ACC_CR : (ACC Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWRST:1; /**< bit: 0 Software Reset */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_CR_OFFSET (0x00) /**< (ACC_CR) Control Register Offset */ + +#define ACC_CR_SWRST_Pos 0 /**< (ACC_CR) Software Reset Position */ +#define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */ +#define ACC_CR_SWRST ACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_CR_SWRST_Msk instead */ +#define ACC_CR_MASK _U_(0x01) /**< \deprecated (ACC_CR) Register MASK (Use ACC_CR_Msk instead) */ +#define ACC_CR_Msk _U_(0x01) /**< (ACC_CR) Register Mask */ + + +/* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SELMINUS:3; /**< bit: 0..2 Selection for Minus Comparator Input */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t SELPLUS:3; /**< bit: 4..6 Selection For Plus Comparator Input */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t ACEN:1; /**< bit: 8 Analog Comparator Enable */ + uint32_t EDGETYP:2; /**< bit: 9..10 Edge Type */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t INV:1; /**< bit: 12 Invert Comparator Output */ + uint32_t SELFS:1; /**< bit: 13 Selection Of Fault Source */ + uint32_t FE:1; /**< bit: 14 Fault Enable */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_MR_OFFSET (0x04) /**< (ACC_MR) Mode Register Offset */ + +#define ACC_MR_SELMINUS_Pos 0 /**< (ACC_MR) Selection for Minus Comparator Input Position */ +#define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */ +#define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)) +#define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */ +#define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */ +#define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */ +#define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_Pos 4 /**< (ACC_MR) Selection For Plus Comparator Input Position */ +#define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */ +#define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)) +#define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */ +#define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */ +#define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */ +#define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */ +#define ACC_MR_ACEN_Pos 8 /**< (ACC_MR) Analog Comparator Enable Position */ +#define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */ +#define ACC_MR_ACEN ACC_MR_ACEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_ACEN_Msk instead */ +#define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */ +#define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */ +#define ACC_MR_EDGETYP_Pos 9 /**< (ACC_MR) Edge Type Position */ +#define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */ +#define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)) +#define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */ +#define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */ +#define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */ +#define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */ +#define ACC_MR_INV_Pos 12 /**< (ACC_MR) Invert Comparator Output Position */ +#define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */ +#define ACC_MR_INV ACC_MR_INV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_INV_Msk instead */ +#define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */ +#define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */ +#define ACC_MR_SELFS_Pos 13 /**< (ACC_MR) Selection Of Fault Source Position */ +#define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */ +#define ACC_MR_SELFS ACC_MR_SELFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_SELFS_Msk instead */ +#define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */ +#define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */ +#define ACC_MR_FE_Pos 14 /**< (ACC_MR) Fault Enable Position */ +#define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */ +#define ACC_MR_FE ACC_MR_FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_FE_Msk instead */ +#define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +#define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */ +#define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */ +#define ACC_MR_MASK _U_(0x7777) /**< \deprecated (ACC_MR) Register MASK (Use ACC_MR_Msk instead) */ +#define ACC_MR_Msk _U_(0x7777) /**< (ACC_MR) Register Mask */ + + +/* -------- ACC_IER : (ACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CE:1; /**< bit: 0 Comparison Edge */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_IER_OFFSET (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */ + +#define ACC_IER_CE_Pos 0 /**< (ACC_IER) Comparison Edge Position */ +#define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */ +#define ACC_IER_CE ACC_IER_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IER_CE_Msk instead */ +#define ACC_IER_MASK _U_(0x01) /**< \deprecated (ACC_IER) Register MASK (Use ACC_IER_Msk instead) */ +#define ACC_IER_Msk _U_(0x01) /**< (ACC_IER) Register Mask */ + + +/* -------- ACC_IDR : (ACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CE:1; /**< bit: 0 Comparison Edge */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_IDR_OFFSET (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */ + +#define ACC_IDR_CE_Pos 0 /**< (ACC_IDR) Comparison Edge Position */ +#define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */ +#define ACC_IDR_CE ACC_IDR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IDR_CE_Msk instead */ +#define ACC_IDR_MASK _U_(0x01) /**< \deprecated (ACC_IDR) Register MASK (Use ACC_IDR_Msk instead) */ +#define ACC_IDR_Msk _U_(0x01) /**< (ACC_IDR) Register Mask */ + + +/* -------- ACC_IMR : (ACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CE:1; /**< bit: 0 Comparison Edge */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_IMR_OFFSET (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */ + +#define ACC_IMR_CE_Pos 0 /**< (ACC_IMR) Comparison Edge Position */ +#define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */ +#define ACC_IMR_CE ACC_IMR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IMR_CE_Msk instead */ +#define ACC_IMR_MASK _U_(0x01) /**< \deprecated (ACC_IMR) Register MASK (Use ACC_IMR_Msk instead) */ +#define ACC_IMR_Msk _U_(0x01) /**< (ACC_IMR) Register Mask */ + + +/* -------- ACC_ISR : (ACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CE:1; /**< bit: 0 Comparison Edge (cleared on read) */ + uint32_t SCO:1; /**< bit: 1 Synchronized Comparator Output */ + uint32_t :29; /**< bit: 2..30 Reserved */ + uint32_t MASK:1; /**< bit: 31 Flag Mask */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_ISR_OFFSET (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */ + +#define ACC_ISR_CE_Pos 0 /**< (ACC_ISR) Comparison Edge (cleared on read) Position */ +#define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */ +#define ACC_ISR_CE ACC_ISR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_CE_Msk instead */ +#define ACC_ISR_SCO_Pos 1 /**< (ACC_ISR) Synchronized Comparator Output Position */ +#define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */ +#define ACC_ISR_SCO ACC_ISR_SCO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_SCO_Msk instead */ +#define ACC_ISR_MASK_Pos 31 /**< (ACC_ISR) Flag Mask Position */ +#define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */ +#define ACC_ISR_MASK ACC_ISR_MASK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_MASK_Msk instead */ +#define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */ + + +/* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ISEL:1; /**< bit: 0 Current Selection */ + uint32_t HYST:2; /**< bit: 1..2 Hysteresis Selection */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_ACR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_ACR_OFFSET (0x94) /**< (ACC_ACR) Analog Control Register Offset */ + +#define ACC_ACR_ISEL_Pos 0 /**< (ACC_ACR) Current Selection Position */ +#define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */ +#define ACC_ACR_ISEL ACC_ACR_ISEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ACR_ISEL_Msk instead */ +#define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */ +#define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */ +#define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */ +#define ACC_ACR_HYST_Pos 1 /**< (ACC_ACR) Hysteresis Selection Position */ +#define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */ +#define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)) +#define ACC_ACR_MASK _U_(0x07) /**< \deprecated (ACC_ACR) Register MASK (Use ACC_ACR_Msk instead) */ +#define ACC_ACR_Msk _U_(0x07) /**< (ACC_ACR) Register Mask */ + + +/* -------- ACC_WPMR : (ACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_WPMR_OFFSET (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */ + +#define ACC_WPMR_WPEN_Pos 0 /**< (ACC_WPMR) Write Protection Enable Position */ +#define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */ +#define ACC_WPMR_WPEN ACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPMR_WPEN_Msk instead */ +#define ACC_WPMR_WPKEY_Pos 8 /**< (ACC_WPMR) Write Protection Key Position */ +#define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */ +#define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)) +#define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (ACC_WPMR) Register MASK (Use ACC_WPMR_Msk instead) */ +#define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */ + + +/* -------- ACC_WPSR : (ACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ACC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ACC_WPSR_OFFSET (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */ + +#define ACC_WPSR_WPVS_Pos 0 /**< (ACC_WPSR) Write Protection Violation Status Position */ +#define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */ +#define ACC_WPSR_WPVS ACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPSR_WPVS_Msk instead */ +#define ACC_WPSR_MASK _U_(0x01) /**< \deprecated (ACC_WPSR) Register MASK (Use ACC_WPSR_Msk instead) */ +#define ACC_WPSR_Msk _U_(0x01) /**< (ACC_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief ACC hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< (ACC Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< (ACC Offset: 0x04) Mode Register */ + __I uint8_t Reserved1[28]; + __O uint32_t ACC_IER; /**< (ACC Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< (ACC Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< (ACC Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< (ACC Offset: 0x30) Interrupt Status Register */ + __I uint8_t Reserved2[96]; + __IO uint32_t ACC_ACR; /**< (ACC Offset: 0x94) Analog Control Register */ + __I uint8_t Reserved3[76]; + __IO uint32_t ACC_WPMR; /**< (ACC Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< (ACC Offset: 0xE8) Write Protection Status Register */ +} Acc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief ACC hardware registers */ +typedef struct { + __O ACC_CR_Type ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO ACC_MR_Type ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[28]; + __O ACC_IER_Type ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O ACC_IDR_Type ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I ACC_IMR_Type ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I ACC_ISR_Type ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[96]; + __IO ACC_ACR_Type ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */ + __I uint8_t Reserved3[76]; + __IO ACC_WPMR_Type ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I ACC_WPSR_Type ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Acc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Analog Comparator Controller */ + +#endif /* _SAME70_ACC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/aes.h b/bsp/microchip/same70/bsp/same70b/include/component/aes.h new file mode 100644 index 0000000000..35fdb1b5f3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/aes.h @@ -0,0 +1,586 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_AES_COMPONENT_H_ +#define _SAME70_AES_COMPONENT_H_ +#define _SAME70_AES_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Advanced Encryption Standard + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define AES_6149 /**< (AES) Module ID */ +#define REV_AES W /**< (AES) Module revision */ + +/* -------- AES_CR : (AES Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t START:1; /**< bit: 0 Start Processing */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t SWRST:1; /**< bit: 8 Software Reset */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t LOADSEED:1; /**< bit: 16 Random Number Generator Seed Loading */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CR_OFFSET (0x00) /**< (AES_CR) Control Register Offset */ + +#define AES_CR_START_Pos 0 /**< (AES_CR) Start Processing Position */ +#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */ +#define AES_CR_START AES_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_START_Msk instead */ +#define AES_CR_SWRST_Pos 8 /**< (AES_CR) Software Reset Position */ +#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */ +#define AES_CR_SWRST AES_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_SWRST_Msk instead */ +#define AES_CR_LOADSEED_Pos 16 /**< (AES_CR) Random Number Generator Seed Loading Position */ +#define AES_CR_LOADSEED_Msk (_U_(0x1) << AES_CR_LOADSEED_Pos) /**< (AES_CR) Random Number Generator Seed Loading Mask */ +#define AES_CR_LOADSEED AES_CR_LOADSEED_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_LOADSEED_Msk instead */ +#define AES_CR_MASK _U_(0x10101) /**< \deprecated (AES_CR) Register MASK (Use AES_CR_Msk instead) */ +#define AES_CR_Msk _U_(0x10101) /**< (AES_CR) Register Mask */ + + +/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CIPHER:1; /**< bit: 0 Processing Mode */ + uint32_t GTAGEN:1; /**< bit: 1 GCM Automatic Tag Generation Enable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t DUALBUFF:1; /**< bit: 3 Dual Input Buffer */ + uint32_t PROCDLY:4; /**< bit: 4..7 Processing Delay */ + uint32_t SMOD:2; /**< bit: 8..9 Start Mode */ + uint32_t KEYSIZE:2; /**< bit: 10..11 Key Size */ + uint32_t OPMOD:3; /**< bit: 12..14 Operating Mode */ + uint32_t LOD:1; /**< bit: 15 Last Output Data Mode */ + uint32_t CFBS:3; /**< bit: 16..18 Cipher Feedback Data Size */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t CKEY:4; /**< bit: 20..23 Countermeasure Key */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_MR_OFFSET (0x04) /**< (AES_MR) Mode Register Offset */ + +#define AES_MR_CIPHER_Pos 0 /**< (AES_MR) Processing Mode Position */ +#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */ +#define AES_MR_CIPHER AES_MR_CIPHER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CIPHER_Msk instead */ +#define AES_MR_GTAGEN_Pos 1 /**< (AES_MR) GCM Automatic Tag Generation Enable Position */ +#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */ +#define AES_MR_GTAGEN AES_MR_GTAGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_GTAGEN_Msk instead */ +#define AES_MR_DUALBUFF_Pos 3 /**< (AES_MR) Dual Input Buffer Position */ +#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */ +#define AES_MR_DUALBUFF AES_MR_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_DUALBUFF_Msk instead */ +#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */ +#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */ +#define AES_MR_PROCDLY_Pos 4 /**< (AES_MR) Processing Delay Position */ +#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */ +#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)) +#define AES_MR_SMOD_Pos 8 /**< (AES_MR) Start Mode Position */ +#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */ +#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)) +#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */ +#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */ +#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */ +#define AES_MR_KEYSIZE_Pos 10 /**< (AES_MR) Key Size Position */ +#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */ +#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)) +#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */ +#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */ +#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */ +#define AES_MR_OPMOD_Pos 12 /**< (AES_MR) Operating Mode Position */ +#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */ +#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)) +#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */ +#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */ +#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */ +#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */ +#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */ +#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */ +#define AES_MR_LOD_Pos 15 /**< (AES_MR) Last Output Data Mode Position */ +#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */ +#define AES_MR_LOD AES_MR_LOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_LOD_Msk instead */ +#define AES_MR_CFBS_Pos 16 /**< (AES_MR) Cipher Feedback Data Size Position */ +#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */ +#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)) +#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */ +#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */ +#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */ +#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */ +#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */ +#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */ +#define AES_MR_CKEY_Pos 20 /**< (AES_MR) Countermeasure Key Position */ +#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */ +#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)) +#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */ +#define AES_MR_MASK _U_(0xF7FFFB) /**< \deprecated (AES_MR) Register MASK (Use AES_MR_Msk instead) */ +#define AES_MR_Msk _U_(0xF7FFFB) /**< (AES_MR) Register Mask */ + + +/* -------- AES_IER : (AES Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Enable */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Enable */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_IER_OFFSET (0x10) /**< (AES_IER) Interrupt Enable Register Offset */ + +#define AES_IER_DATRDY_Pos 0 /**< (AES_IER) Data Ready Interrupt Enable Position */ +#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */ +#define AES_IER_DATRDY AES_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_DATRDY_Msk instead */ +#define AES_IER_URAD_Pos 8 /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */ +#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */ +#define AES_IER_URAD AES_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_URAD_Msk instead */ +#define AES_IER_TAGRDY_Pos 16 /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */ +#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */ +#define AES_IER_TAGRDY AES_IER_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_TAGRDY_Msk instead */ +#define AES_IER_MASK _U_(0x10101) /**< \deprecated (AES_IER) Register MASK (Use AES_IER_Msk instead) */ +#define AES_IER_Msk _U_(0x10101) /**< (AES_IER) Register Mask */ + + +/* -------- AES_IDR : (AES Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Disable */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Disable */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_IDR_OFFSET (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */ + +#define AES_IDR_DATRDY_Pos 0 /**< (AES_IDR) Data Ready Interrupt Disable Position */ +#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */ +#define AES_IDR_DATRDY AES_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_DATRDY_Msk instead */ +#define AES_IDR_URAD_Pos 8 /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */ +#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */ +#define AES_IDR_URAD AES_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_URAD_Msk instead */ +#define AES_IDR_TAGRDY_Pos 16 /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */ +#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */ +#define AES_IDR_TAGRDY AES_IDR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_TAGRDY_Msk instead */ +#define AES_IDR_MASK _U_(0x10101) /**< \deprecated (AES_IDR) Register MASK (Use AES_IDR_Msk instead) */ +#define AES_IDR_Msk _U_(0x10101) /**< (AES_IDR) Register Mask */ + + +/* -------- AES_IMR : (AES Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Mask */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Mask */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_IMR_OFFSET (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */ + +#define AES_IMR_DATRDY_Pos 0 /**< (AES_IMR) Data Ready Interrupt Mask Position */ +#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */ +#define AES_IMR_DATRDY AES_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_DATRDY_Msk instead */ +#define AES_IMR_URAD_Pos 8 /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */ +#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */ +#define AES_IMR_URAD AES_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_URAD_Msk instead */ +#define AES_IMR_TAGRDY_Pos 16 /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */ +#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */ +#define AES_IMR_TAGRDY AES_IMR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_TAGRDY_Msk instead */ +#define AES_IMR_MASK _U_(0x10101) /**< \deprecated (AES_IMR) Register MASK (Use AES_IMR_Msk instead) */ +#define AES_IMR_Msk _U_(0x10101) /**< (AES_IMR) Register Mask */ + + +/* -------- AES_ISR : (AES Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t URAT:4; /**< bit: 12..15 Unspecified Register Access (cleared by writing SWRST in AES_CR) */ + uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_ISR_OFFSET (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */ + +#define AES_ISR_DATRDY_Pos 0 /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */ +#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */ +#define AES_ISR_DATRDY AES_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_DATRDY_Msk instead */ +#define AES_ISR_URAD_Pos 8 /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAD AES_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_URAD_Msk instead */ +#define AES_ISR_URAT_Pos 12 /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos)) +#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */ +#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */ +#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */ +#define AES_ISR_TAGRDY_Pos 16 /**< (AES_ISR) GCM Tag Ready Position */ +#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */ +#define AES_ISR_TAGRDY AES_ISR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_TAGRDY_Msk instead */ +#define AES_ISR_MASK _U_(0x1F101) /**< \deprecated (AES_ISR) Register MASK (Use AES_ISR_Msk instead) */ +#define AES_ISR_Msk _U_(0x1F101) /**< (AES_ISR) Register Mask */ + + +/* -------- AES_KEYWR : (AES Offset: 0x20) (/W 32) Key Word Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t KEYW:32; /**< bit: 0..31 Key Word */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_KEYWR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWR_OFFSET (0x20) /**< (AES_KEYWR) Key Word Register Offset */ + +#define AES_KEYWR_KEYW_Pos 0 /**< (AES_KEYWR) Key Word Position */ +#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */ +#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)) +#define AES_KEYWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_KEYWR) Register MASK (Use AES_KEYWR_Msk instead) */ +#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */ + + +/* -------- AES_IDATAR : (AES Offset: 0x40) (/W 32) Input Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDATA:32; /**< bit: 0..31 Input Data Word */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_IDATAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_IDATAR_OFFSET (0x40) /**< (AES_IDATAR) Input Data Register Offset */ + +#define AES_IDATAR_IDATA_Pos 0 /**< (AES_IDATAR) Input Data Word Position */ +#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */ +#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)) +#define AES_IDATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IDATAR) Register MASK (Use AES_IDATAR_Msk instead) */ +#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */ + + +/* -------- AES_ODATAR : (AES Offset: 0x50) (R/ 32) Output Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ODATA:32; /**< bit: 0..31 Output Data */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_ODATAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_ODATAR_OFFSET (0x50) /**< (AES_ODATAR) Output Data Register Offset */ + +#define AES_ODATAR_ODATA_Pos 0 /**< (AES_ODATAR) Output Data Position */ +#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */ +#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos)) +#define AES_ODATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_ODATAR) Register MASK (Use AES_ODATAR_Msk instead) */ +#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */ + + +/* -------- AES_IVR : (AES Offset: 0x60) (/W 32) Initialization Vector Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IV:32; /**< bit: 0..31 Initialization Vector */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_IVR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_IVR_OFFSET (0x60) /**< (AES_IVR) Initialization Vector Register Offset */ + +#define AES_IVR_IV_Pos 0 /**< (AES_IVR) Initialization Vector Position */ +#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */ +#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)) +#define AES_IVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IVR) Register MASK (Use AES_IVR_Msk instead) */ +#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */ + + +/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t AADLEN:32; /**< bit: 0..31 Additional Authenticated Data Length */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_AADLENR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_AADLENR_OFFSET (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */ + +#define AES_AADLENR_AADLEN_Pos 0 /**< (AES_AADLENR) Additional Authenticated Data Length Position */ +#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */ +#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)) +#define AES_AADLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_AADLENR) Register MASK (Use AES_AADLENR_Msk instead) */ +#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */ + + +/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CLEN:32; /**< bit: 0..31 Plaintext/Ciphertext Length */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_CLENR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CLENR_OFFSET (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */ + +#define AES_CLENR_CLEN_Pos 0 /**< (AES_CLENR) Plaintext/Ciphertext Length Position */ +#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */ +#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)) +#define AES_CLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CLENR) Register MASK (Use AES_CLENR_Msk instead) */ +#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */ + + +/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t GHASH:32; /**< bit: 0..31 Intermediate GCM Hash Word x */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_GHASHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASHR_OFFSET (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register Offset */ + +#define AES_GHASHR_GHASH_Pos 0 /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */ +#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */ +#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)) +#define AES_GHASHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GHASHR) Register MASK (Use AES_GHASHR_Msk instead) */ +#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */ + + +/* -------- AES_TAGR : (AES Offset: 0x88) (R/ 32) GCM Authentication Tag Word Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TAG:32; /**< bit: 0..31 GCM Authentication Tag x */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_TAGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_TAGR_OFFSET (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register Offset */ + +#define AES_TAGR_TAG_Pos 0 /**< (AES_TAGR) GCM Authentication Tag x Position */ +#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */ +#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos)) +#define AES_TAGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_TAGR) Register MASK (Use AES_TAGR_Msk instead) */ +#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */ + + +/* -------- AES_CTRR : (AES Offset: 0x98) (R/ 32) GCM Encryption Counter Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CTR:32; /**< bit: 0..31 GCM Encryption Counter */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_CTRR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRR_OFFSET (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */ + +#define AES_CTRR_CTR_Pos 0 /**< (AES_CTRR) GCM Encryption Counter Position */ +#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */ +#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos)) +#define AES_CTRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CTRR) Register MASK (Use AES_CTRR_Msk instead) */ +#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */ + + +/* -------- AES_GCMHR : (AES Offset: 0x9c) (R/W 32) GCM H Word Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t H:32; /**< bit: 0..31 GCM H Word x */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AES_GCMHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GCMHR_OFFSET (0x9C) /**< (AES_GCMHR) GCM H Word Register Offset */ + +#define AES_GCMHR_H_Pos 0 /**< (AES_GCMHR) GCM H Word x Position */ +#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */ +#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)) +#define AES_GCMHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GCMHR) Register MASK (Use AES_GCMHR_Msk instead) */ +#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief AES hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< (AES Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< (AES Offset: 0x04) Mode Register */ + __I uint8_t Reserved1[8]; + __O uint32_t AES_IER; /**< (AES Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< (AES Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< (AES Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< (AES Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< (AES Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< (AES Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< (AES Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< (AES Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< (AES Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< (AES Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< (AES Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< (AES Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< (AES Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< (AES Offset: 0x9C) GCM H Word Register */ +} Aes; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief AES hardware registers */ +typedef struct { + __O AES_CR_Type AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO AES_MR_Type AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[8]; + __O AES_IER_Type AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O AES_IDR_Type AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I AES_IMR_Type AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I AES_ISR_Type AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __O AES_KEYWR_Type AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register */ + __O AES_IDATAR_Type AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register */ + __I AES_ODATAR_Type AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register */ + __O AES_IVR_Type AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register */ + __IO AES_AADLENR_Type AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */ + __IO AES_CLENR_Type AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */ + __IO AES_GHASHR_Type AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register */ + __I AES_TAGR_Type AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register */ + __I AES_CTRR_Type AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */ + __IO AES_GCMHR_Type AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register */ +} Aes; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Advanced Encryption Standard */ + +#endif /* _SAME70_AES_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/afec.h b/bsp/microchip/same70/bsp/same70b/include/component/afec.h new file mode 100644 index 0000000000..366c16aeb3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/afec.h @@ -0,0 +1,1710 @@ +/** + * \file + * + * \brief Component description for AFEC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_AFEC_COMPONENT_H_ +#define _SAME70_AFEC_COMPONENT_H_ +#define _SAME70_AFEC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Analog Front-End Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AFEC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define AFEC_11147 /**< (AFEC) Module ID */ +#define REV_AFEC S /**< (AFEC) Module revision */ + +/* -------- AFEC_CR : (AFEC Offset: 0x00) (/W 32) AFEC Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWRST:1; /**< bit: 0 Software Reset */ + uint32_t START:1; /**< bit: 1 Start Conversion */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CR_OFFSET (0x00) /**< (AFEC_CR) AFEC Control Register Offset */ + +#define AFEC_CR_SWRST_Pos 0 /**< (AFEC_CR) Software Reset Position */ +#define AFEC_CR_SWRST_Msk (_U_(0x1) << AFEC_CR_SWRST_Pos) /**< (AFEC_CR) Software Reset Mask */ +#define AFEC_CR_SWRST AFEC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CR_SWRST_Msk instead */ +#define AFEC_CR_START_Pos 1 /**< (AFEC_CR) Start Conversion Position */ +#define AFEC_CR_START_Msk (_U_(0x1) << AFEC_CR_START_Pos) /**< (AFEC_CR) Start Conversion Mask */ +#define AFEC_CR_START AFEC_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CR_START_Msk instead */ +#define AFEC_CR_MASK _U_(0x03) /**< \deprecated (AFEC_CR) Register MASK (Use AFEC_CR_Msk instead) */ +#define AFEC_CR_Msk _U_(0x03) /**< (AFEC_CR) Register Mask */ + + +/* -------- AFEC_MR : (AFEC Offset: 0x04) (R/W 32) AFEC Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TRGEN:1; /**< bit: 0 Trigger Enable */ + uint32_t TRGSEL:3; /**< bit: 1..3 Trigger Selection */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t SLEEP:1; /**< bit: 5 Sleep Mode */ + uint32_t FWUP:1; /**< bit: 6 Fast Wake-up */ + uint32_t FREERUN:1; /**< bit: 7 Free Run Mode */ + uint32_t PRESCAL:8; /**< bit: 8..15 Prescaler Rate Selection */ + uint32_t STARTUP:4; /**< bit: 16..19 Start-up Time */ + uint32_t :3; /**< bit: 20..22 Reserved */ + uint32_t ONE:1; /**< bit: 23 One */ + uint32_t TRACKTIM:4; /**< bit: 24..27 Tracking Time */ + uint32_t TRANSFER:2; /**< bit: 28..29 Transfer Period */ + uint32_t :1; /**< bit: 30 Reserved */ + uint32_t USEQ:1; /**< bit: 31 User Sequence Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_MR_OFFSET (0x04) /**< (AFEC_MR) AFEC Mode Register Offset */ + +#define AFEC_MR_TRGEN_Pos 0 /**< (AFEC_MR) Trigger Enable Position */ +#define AFEC_MR_TRGEN_Msk (_U_(0x1) << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Trigger Enable Mask */ +#define AFEC_MR_TRGEN AFEC_MR_TRGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_TRGEN_Msk instead */ +#define AFEC_MR_TRGEN_DIS_Val _U_(0x0) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN_Val _U_(0x1) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGEN_DIS (AFEC_MR_TRGEN_DIS_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. Position */ +#define AFEC_MR_TRGEN_EN (AFEC_MR_TRGEN_EN_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. Position */ +#define AFEC_MR_TRGSEL_Pos 1 /**< (AFEC_MR) Trigger Selection Position */ +#define AFEC_MR_TRGSEL_Msk (_U_(0x7) << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Trigger Selection Mask */ +#define AFEC_MR_TRGSEL(value) (AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)) +#define AFEC_MR_TRGSEL_AFEC_TRIG0_Val _U_(0x0) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1_Val _U_(0x1) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2_Val _U_(0x2) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3_Val _U_(0x3) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4_Val _U_(0x4) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5_Val _U_(0x5) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6_Val _U_(0x6) /**< (AFEC_MR) Analog Comparator */ +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (AFEC_MR_TRGSEL_AFEC_TRIG0_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (AFEC_MR_TRGSEL_AFEC_TRIG1_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (AFEC_MR_TRGSEL_AFEC_TRIG2_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (AFEC_MR_TRGSEL_AFEC_TRIG3_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (AFEC_MR_TRGSEL_AFEC_TRIG4_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (AFEC_MR_TRGSEL_AFEC_TRIG5_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (AFEC_MR_TRGSEL_AFEC_TRIG6_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Analog Comparator Position */ +#define AFEC_MR_SLEEP_Pos 5 /**< (AFEC_MR) Sleep Mode Position */ +#define AFEC_MR_SLEEP_Msk (_U_(0x1) << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep Mode Mask */ +#define AFEC_MR_SLEEP AFEC_MR_SLEEP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_SLEEP_Msk instead */ +#define AFEC_MR_SLEEP_NORMAL_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP_Val _U_(0x1) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_SLEEP_NORMAL (AFEC_MR_SLEEP_NORMAL_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. Position */ +#define AFEC_MR_SLEEP_SLEEP (AFEC_MR_SLEEP_SLEEP_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. Position */ +#define AFEC_MR_FWUP_Pos 6 /**< (AFEC_MR) Fast Wake-up Position */ +#define AFEC_MR_FWUP_Msk (_U_(0x1) << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast Wake-up Mask */ +#define AFEC_MR_FWUP AFEC_MR_FWUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_FWUP_Msk instead */ +#define AFEC_MR_FWUP_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON_Val _U_(0x1) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FWUP_OFF (AFEC_MR_FWUP_OFF_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. Position */ +#define AFEC_MR_FWUP_ON (AFEC_MR_FWUP_ON_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. Position */ +#define AFEC_MR_FREERUN_Pos 7 /**< (AFEC_MR) Free Run Mode Position */ +#define AFEC_MR_FREERUN_Msk (_U_(0x1) << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run Mode Mask */ +#define AFEC_MR_FREERUN AFEC_MR_FREERUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_FREERUN_Msk instead */ +#define AFEC_MR_FREERUN_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON_Val _U_(0x1) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_FREERUN_OFF (AFEC_MR_FREERUN_OFF_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Normal mode Position */ +#define AFEC_MR_FREERUN_ON (AFEC_MR_FREERUN_ON_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. Position */ +#define AFEC_MR_PRESCAL_Pos 8 /**< (AFEC_MR) Prescaler Rate Selection Position */ +#define AFEC_MR_PRESCAL_Msk (_U_(0xFF) << AFEC_MR_PRESCAL_Pos) /**< (AFEC_MR) Prescaler Rate Selection Mask */ +#define AFEC_MR_PRESCAL(value) (AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)) +#define AFEC_MR_STARTUP_Pos 16 /**< (AFEC_MR) Start-up Time Position */ +#define AFEC_MR_STARTUP_Msk (_U_(0xF) << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) Start-up Time Mask */ +#define AFEC_MR_STARTUP(value) (AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)) +#define AFEC_MR_STARTUP_SUT0_Val _U_(0x0) /**< (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8_Val _U_(0x1) /**< (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16_Val _U_(0x2) /**< (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24_Val _U_(0x3) /**< (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64_Val _U_(0x4) /**< (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80_Val _U_(0x5) /**< (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96_Val _U_(0x6) /**< (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112_Val _U_(0x7) /**< (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512_Val _U_(0x8) /**< (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576_Val _U_(0x9) /**< (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640_Val _U_(0xA) /**< (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704_Val _U_(0xB) /**< (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768_Val _U_(0xC) /**< (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832_Val _U_(0xD) /**< (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896_Val _U_(0xE) /**< (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960_Val _U_(0xF) /**< (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT0 (AFEC_MR_STARTUP_SUT0_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 0 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT8 (AFEC_MR_STARTUP_SUT8_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 8 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT16 (AFEC_MR_STARTUP_SUT16_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 16 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT24 (AFEC_MR_STARTUP_SUT24_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 24 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT64 (AFEC_MR_STARTUP_SUT64_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 64 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT80 (AFEC_MR_STARTUP_SUT80_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 80 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT96 (AFEC_MR_STARTUP_SUT96_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 96 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT112 (AFEC_MR_STARTUP_SUT112_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 112 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT512 (AFEC_MR_STARTUP_SUT512_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 512 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT576 (AFEC_MR_STARTUP_SUT576_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 576 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT640 (AFEC_MR_STARTUP_SUT640_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 640 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT704 (AFEC_MR_STARTUP_SUT704_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 704 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT768 (AFEC_MR_STARTUP_SUT768_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 768 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT832 (AFEC_MR_STARTUP_SUT832_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 832 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT896 (AFEC_MR_STARTUP_SUT896_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 896 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT960 (AFEC_MR_STARTUP_SUT960_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 960 periods of AFE clock Position */ +#define AFEC_MR_ONE_Pos 23 /**< (AFEC_MR) One Position */ +#define AFEC_MR_ONE_Msk (_U_(0x1) << AFEC_MR_ONE_Pos) /**< (AFEC_MR) One Mask */ +#define AFEC_MR_ONE AFEC_MR_ONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_ONE_Msk instead */ +#define AFEC_MR_TRACKTIM_Pos 24 /**< (AFEC_MR) Tracking Time Position */ +#define AFEC_MR_TRACKTIM_Msk (_U_(0xF) << AFEC_MR_TRACKTIM_Pos) /**< (AFEC_MR) Tracking Time Mask */ +#define AFEC_MR_TRACKTIM(value) (AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)) +#define AFEC_MR_TRANSFER_Pos 28 /**< (AFEC_MR) Transfer Period Position */ +#define AFEC_MR_TRANSFER_Msk (_U_(0x3) << AFEC_MR_TRANSFER_Pos) /**< (AFEC_MR) Transfer Period Mask */ +#define AFEC_MR_TRANSFER(value) (AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)) +#define AFEC_MR_USEQ_Pos 31 /**< (AFEC_MR) User Sequence Enable Position */ +#define AFEC_MR_USEQ_Msk (_U_(0x1) << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence Enable Mask */ +#define AFEC_MR_USEQ AFEC_MR_USEQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_USEQ_Msk instead */ +#define AFEC_MR_USEQ_NUM_ORDER_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER_Val _U_(0x1) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +#define AFEC_MR_USEQ_NUM_ORDER (AFEC_MR_USEQ_NUM_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. Position */ +#define AFEC_MR_USEQ_REG_ORDER (AFEC_MR_USEQ_REG_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. Position */ +#define AFEC_MR_MASK _U_(0xBF8FFFEF) /**< \deprecated (AFEC_MR) Register MASK (Use AFEC_MR_Msk instead) */ +#define AFEC_MR_Msk _U_(0xBF8FFFEF) /**< (AFEC_MR) Register Mask */ + + +/* -------- AFEC_EMR : (AFEC Offset: 0x08) (R/W 32) AFEC Extended Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMPMODE:2; /**< bit: 0..1 Comparison Mode */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t CMPSEL:5; /**< bit: 3..7 Comparison Selected Channel */ + uint32_t :1; /**< bit: 8 Reserved */ + uint32_t CMPALL:1; /**< bit: 9 Compare All Channels */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t CMPFILTER:2; /**< bit: 12..13 Compare Event Filtering */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RES:3; /**< bit: 16..18 Resolution */ + uint32_t :5; /**< bit: 19..23 Reserved */ + uint32_t TAG:1; /**< bit: 24 TAG of the AFEC_LDCR */ + uint32_t STM:1; /**< bit: 25 Single Trigger Mode */ + uint32_t :2; /**< bit: 26..27 Reserved */ + uint32_t SIGNMODE:2; /**< bit: 28..29 Sign Mode */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_EMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_EMR_OFFSET (0x08) /**< (AFEC_EMR) AFEC Extended Mode Register Offset */ + +#define AFEC_EMR_CMPMODE_Pos 0 /**< (AFEC_EMR) Comparison Mode Position */ +#define AFEC_EMR_CMPMODE_Msk (_U_(0x3) << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Comparison Mode Mask */ +#define AFEC_EMR_CMPMODE(value) (AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)) +#define AFEC_EMR_CMPMODE_LOW_Val _U_(0x0) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH_Val _U_(0x1) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN_Val _U_(0x2) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT_Val _U_(0x3) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPMODE_LOW (AFEC_EMR_CMPMODE_LOW_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_HIGH (AFEC_EMR_CMPMODE_HIGH_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_IN (AFEC_EMR_CMPMODE_IN_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_EMR_CMPMODE_OUT (AFEC_EMR_CMPMODE_OUT_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_EMR_CMPSEL_Pos 3 /**< (AFEC_EMR) Comparison Selected Channel Position */ +#define AFEC_EMR_CMPSEL_Msk (_U_(0x1F) << AFEC_EMR_CMPSEL_Pos) /**< (AFEC_EMR) Comparison Selected Channel Mask */ +#define AFEC_EMR_CMPSEL(value) (AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)) +#define AFEC_EMR_CMPALL_Pos 9 /**< (AFEC_EMR) Compare All Channels Position */ +#define AFEC_EMR_CMPALL_Msk (_U_(0x1) << AFEC_EMR_CMPALL_Pos) /**< (AFEC_EMR) Compare All Channels Mask */ +#define AFEC_EMR_CMPALL AFEC_EMR_CMPALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_CMPALL_Msk instead */ +#define AFEC_EMR_CMPFILTER_Pos 12 /**< (AFEC_EMR) Compare Event Filtering Position */ +#define AFEC_EMR_CMPFILTER_Msk (_U_(0x3) << AFEC_EMR_CMPFILTER_Pos) /**< (AFEC_EMR) Compare Event Filtering Mask */ +#define AFEC_EMR_CMPFILTER(value) (AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)) +#define AFEC_EMR_RES_Pos 16 /**< (AFEC_EMR) Resolution Position */ +#define AFEC_EMR_RES_Msk (_U_(0x7) << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) Resolution Mask */ +#define AFEC_EMR_RES(value) (AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)) +#define AFEC_EMR_RES_NO_AVERAGE_Val _U_(0x0) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4_Val _U_(0x2) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16_Val _U_(0x3) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64_Val _U_(0x4) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256_Val _U_(0x5) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_RES_NO_AVERAGE (AFEC_EMR_RES_NO_AVERAGE_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). Position */ +#define AFEC_EMR_RES_OSR4 (AFEC_EMR_RES_OSR4_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). Position */ +#define AFEC_EMR_RES_OSR16 (AFEC_EMR_RES_OSR16_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). Position */ +#define AFEC_EMR_RES_OSR64 (AFEC_EMR_RES_OSR64_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). Position */ +#define AFEC_EMR_RES_OSR256 (AFEC_EMR_RES_OSR256_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). Position */ +#define AFEC_EMR_TAG_Pos 24 /**< (AFEC_EMR) TAG of the AFEC_LDCR Position */ +#define AFEC_EMR_TAG_Msk (_U_(0x1) << AFEC_EMR_TAG_Pos) /**< (AFEC_EMR) TAG of the AFEC_LDCR Mask */ +#define AFEC_EMR_TAG AFEC_EMR_TAG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_TAG_Msk instead */ +#define AFEC_EMR_STM_Pos 25 /**< (AFEC_EMR) Single Trigger Mode Position */ +#define AFEC_EMR_STM_Msk (_U_(0x1) << AFEC_EMR_STM_Pos) /**< (AFEC_EMR) Single Trigger Mode Mask */ +#define AFEC_EMR_STM AFEC_EMR_STM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_STM_Msk instead */ +#define AFEC_EMR_SIGNMODE_Pos 28 /**< (AFEC_EMR) Sign Mode Position */ +#define AFEC_EMR_SIGNMODE_Msk (_U_(0x3) << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Sign Mode Mask */ +#define AFEC_EMR_SIGNMODE(value) (AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val _U_(0x0) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val _U_(0x1) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val _U_(0x2) /**< (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED_Val _U_(0x3) /**< (AFEC_EMR) All channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. Position */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (AFEC_EMR_SIGNMODE_ALL_SIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Signed conversions. Position */ +#define AFEC_EMR_MASK _U_(0x330732FB) /**< \deprecated (AFEC_EMR) Register MASK (Use AFEC_EMR_Msk instead) */ +#define AFEC_EMR_Msk _U_(0x330732FB) /**< (AFEC_EMR) Register Mask */ + + +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0c) (R/W 32) AFEC Channel Sequence 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t USCH0:4; /**< bit: 0..3 User Sequence Number 0 */ + uint32_t USCH1:4; /**< bit: 4..7 User Sequence Number 1 */ + uint32_t USCH2:4; /**< bit: 8..11 User Sequence Number 2 */ + uint32_t USCH3:4; /**< bit: 12..15 User Sequence Number 3 */ + uint32_t USCH4:4; /**< bit: 16..19 User Sequence Number 4 */ + uint32_t USCH5:4; /**< bit: 20..23 User Sequence Number 5 */ + uint32_t USCH6:4; /**< bit: 24..27 User Sequence Number 6 */ + uint32_t USCH7:4; /**< bit: 28..31 User Sequence Number 7 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_SEQ1R_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_SEQ1R_OFFSET (0x0C) /**< (AFEC_SEQ1R) AFEC Channel Sequence 1 Register Offset */ + +#define AFEC_SEQ1R_USCH0_Pos 0 /**< (AFEC_SEQ1R) User Sequence Number 0 Position */ +#define AFEC_SEQ1R_USCH0_Msk (_U_(0xF) << AFEC_SEQ1R_USCH0_Pos) /**< (AFEC_SEQ1R) User Sequence Number 0 Mask */ +#define AFEC_SEQ1R_USCH0(value) (AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)) +#define AFEC_SEQ1R_USCH1_Pos 4 /**< (AFEC_SEQ1R) User Sequence Number 1 Position */ +#define AFEC_SEQ1R_USCH1_Msk (_U_(0xF) << AFEC_SEQ1R_USCH1_Pos) /**< (AFEC_SEQ1R) User Sequence Number 1 Mask */ +#define AFEC_SEQ1R_USCH1(value) (AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)) +#define AFEC_SEQ1R_USCH2_Pos 8 /**< (AFEC_SEQ1R) User Sequence Number 2 Position */ +#define AFEC_SEQ1R_USCH2_Msk (_U_(0xF) << AFEC_SEQ1R_USCH2_Pos) /**< (AFEC_SEQ1R) User Sequence Number 2 Mask */ +#define AFEC_SEQ1R_USCH2(value) (AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)) +#define AFEC_SEQ1R_USCH3_Pos 12 /**< (AFEC_SEQ1R) User Sequence Number 3 Position */ +#define AFEC_SEQ1R_USCH3_Msk (_U_(0xF) << AFEC_SEQ1R_USCH3_Pos) /**< (AFEC_SEQ1R) User Sequence Number 3 Mask */ +#define AFEC_SEQ1R_USCH3(value) (AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)) +#define AFEC_SEQ1R_USCH4_Pos 16 /**< (AFEC_SEQ1R) User Sequence Number 4 Position */ +#define AFEC_SEQ1R_USCH4_Msk (_U_(0xF) << AFEC_SEQ1R_USCH4_Pos) /**< (AFEC_SEQ1R) User Sequence Number 4 Mask */ +#define AFEC_SEQ1R_USCH4(value) (AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)) +#define AFEC_SEQ1R_USCH5_Pos 20 /**< (AFEC_SEQ1R) User Sequence Number 5 Position */ +#define AFEC_SEQ1R_USCH5_Msk (_U_(0xF) << AFEC_SEQ1R_USCH5_Pos) /**< (AFEC_SEQ1R) User Sequence Number 5 Mask */ +#define AFEC_SEQ1R_USCH5(value) (AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)) +#define AFEC_SEQ1R_USCH6_Pos 24 /**< (AFEC_SEQ1R) User Sequence Number 6 Position */ +#define AFEC_SEQ1R_USCH6_Msk (_U_(0xF) << AFEC_SEQ1R_USCH6_Pos) /**< (AFEC_SEQ1R) User Sequence Number 6 Mask */ +#define AFEC_SEQ1R_USCH6(value) (AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)) +#define AFEC_SEQ1R_USCH7_Pos 28 /**< (AFEC_SEQ1R) User Sequence Number 7 Position */ +#define AFEC_SEQ1R_USCH7_Msk (_U_(0xF) << AFEC_SEQ1R_USCH7_Pos) /**< (AFEC_SEQ1R) User Sequence Number 7 Mask */ +#define AFEC_SEQ1R_USCH7(value) (AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)) +#define AFEC_SEQ1R_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_SEQ1R) Register MASK (Use AFEC_SEQ1R_Msk instead) */ +#define AFEC_SEQ1R_Msk _U_(0xFFFFFFFF) /**< (AFEC_SEQ1R) Register Mask */ + + +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) (R/W 32) AFEC Channel Sequence 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t USCH8:4; /**< bit: 0..3 User Sequence Number 8 */ + uint32_t USCH9:4; /**< bit: 4..7 User Sequence Number 9 */ + uint32_t USCH10:4; /**< bit: 8..11 User Sequence Number 10 */ + uint32_t USCH11:4; /**< bit: 12..15 User Sequence Number 11 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_SEQ2R_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_SEQ2R_OFFSET (0x10) /**< (AFEC_SEQ2R) AFEC Channel Sequence 2 Register Offset */ + +#define AFEC_SEQ2R_USCH8_Pos 0 /**< (AFEC_SEQ2R) User Sequence Number 8 Position */ +#define AFEC_SEQ2R_USCH8_Msk (_U_(0xF) << AFEC_SEQ2R_USCH8_Pos) /**< (AFEC_SEQ2R) User Sequence Number 8 Mask */ +#define AFEC_SEQ2R_USCH8(value) (AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)) +#define AFEC_SEQ2R_USCH9_Pos 4 /**< (AFEC_SEQ2R) User Sequence Number 9 Position */ +#define AFEC_SEQ2R_USCH9_Msk (_U_(0xF) << AFEC_SEQ2R_USCH9_Pos) /**< (AFEC_SEQ2R) User Sequence Number 9 Mask */ +#define AFEC_SEQ2R_USCH9(value) (AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)) +#define AFEC_SEQ2R_USCH10_Pos 8 /**< (AFEC_SEQ2R) User Sequence Number 10 Position */ +#define AFEC_SEQ2R_USCH10_Msk (_U_(0xF) << AFEC_SEQ2R_USCH10_Pos) /**< (AFEC_SEQ2R) User Sequence Number 10 Mask */ +#define AFEC_SEQ2R_USCH10(value) (AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)) +#define AFEC_SEQ2R_USCH11_Pos 12 /**< (AFEC_SEQ2R) User Sequence Number 11 Position */ +#define AFEC_SEQ2R_USCH11_Msk (_U_(0xF) << AFEC_SEQ2R_USCH11_Pos) /**< (AFEC_SEQ2R) User Sequence Number 11 Mask */ +#define AFEC_SEQ2R_USCH11(value) (AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)) +#define AFEC_SEQ2R_MASK _U_(0xFFFF) /**< \deprecated (AFEC_SEQ2R) Register MASK (Use AFEC_SEQ2R_Msk instead) */ +#define AFEC_SEQ2R_Msk _U_(0xFFFF) /**< (AFEC_SEQ2R) Register Mask */ + + +/* -------- AFEC_CHER : (AFEC Offset: 0x14) (/W 32) AFEC Channel Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Enable */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Enable */ + uint32_t CH2:1; /**< bit: 2 Channel 2 Enable */ + uint32_t CH3:1; /**< bit: 3 Channel 3 Enable */ + uint32_t CH4:1; /**< bit: 4 Channel 4 Enable */ + uint32_t CH5:1; /**< bit: 5 Channel 5 Enable */ + uint32_t CH6:1; /**< bit: 6 Channel 6 Enable */ + uint32_t CH7:1; /**< bit: 7 Channel 7 Enable */ + uint32_t CH8:1; /**< bit: 8 Channel 8 Enable */ + uint32_t CH9:1; /**< bit: 9 Channel 9 Enable */ + uint32_t CH10:1; /**< bit: 10 Channel 10 Enable */ + uint32_t CH11:1; /**< bit: 11 Channel 11 Enable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:12; /**< bit: 0..11 Channel xx Enable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CHER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CHER_OFFSET (0x14) /**< (AFEC_CHER) AFEC Channel Enable Register Offset */ + +#define AFEC_CHER_CH0_Pos 0 /**< (AFEC_CHER) Channel 0 Enable Position */ +#define AFEC_CHER_CH0_Msk (_U_(0x1) << AFEC_CHER_CH0_Pos) /**< (AFEC_CHER) Channel 0 Enable Mask */ +#define AFEC_CHER_CH0 AFEC_CHER_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH0_Msk instead */ +#define AFEC_CHER_CH1_Pos 1 /**< (AFEC_CHER) Channel 1 Enable Position */ +#define AFEC_CHER_CH1_Msk (_U_(0x1) << AFEC_CHER_CH1_Pos) /**< (AFEC_CHER) Channel 1 Enable Mask */ +#define AFEC_CHER_CH1 AFEC_CHER_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH1_Msk instead */ +#define AFEC_CHER_CH2_Pos 2 /**< (AFEC_CHER) Channel 2 Enable Position */ +#define AFEC_CHER_CH2_Msk (_U_(0x1) << AFEC_CHER_CH2_Pos) /**< (AFEC_CHER) Channel 2 Enable Mask */ +#define AFEC_CHER_CH2 AFEC_CHER_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH2_Msk instead */ +#define AFEC_CHER_CH3_Pos 3 /**< (AFEC_CHER) Channel 3 Enable Position */ +#define AFEC_CHER_CH3_Msk (_U_(0x1) << AFEC_CHER_CH3_Pos) /**< (AFEC_CHER) Channel 3 Enable Mask */ +#define AFEC_CHER_CH3 AFEC_CHER_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH3_Msk instead */ +#define AFEC_CHER_CH4_Pos 4 /**< (AFEC_CHER) Channel 4 Enable Position */ +#define AFEC_CHER_CH4_Msk (_U_(0x1) << AFEC_CHER_CH4_Pos) /**< (AFEC_CHER) Channel 4 Enable Mask */ +#define AFEC_CHER_CH4 AFEC_CHER_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH4_Msk instead */ +#define AFEC_CHER_CH5_Pos 5 /**< (AFEC_CHER) Channel 5 Enable Position */ +#define AFEC_CHER_CH5_Msk (_U_(0x1) << AFEC_CHER_CH5_Pos) /**< (AFEC_CHER) Channel 5 Enable Mask */ +#define AFEC_CHER_CH5 AFEC_CHER_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH5_Msk instead */ +#define AFEC_CHER_CH6_Pos 6 /**< (AFEC_CHER) Channel 6 Enable Position */ +#define AFEC_CHER_CH6_Msk (_U_(0x1) << AFEC_CHER_CH6_Pos) /**< (AFEC_CHER) Channel 6 Enable Mask */ +#define AFEC_CHER_CH6 AFEC_CHER_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH6_Msk instead */ +#define AFEC_CHER_CH7_Pos 7 /**< (AFEC_CHER) Channel 7 Enable Position */ +#define AFEC_CHER_CH7_Msk (_U_(0x1) << AFEC_CHER_CH7_Pos) /**< (AFEC_CHER) Channel 7 Enable Mask */ +#define AFEC_CHER_CH7 AFEC_CHER_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH7_Msk instead */ +#define AFEC_CHER_CH8_Pos 8 /**< (AFEC_CHER) Channel 8 Enable Position */ +#define AFEC_CHER_CH8_Msk (_U_(0x1) << AFEC_CHER_CH8_Pos) /**< (AFEC_CHER) Channel 8 Enable Mask */ +#define AFEC_CHER_CH8 AFEC_CHER_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH8_Msk instead */ +#define AFEC_CHER_CH9_Pos 9 /**< (AFEC_CHER) Channel 9 Enable Position */ +#define AFEC_CHER_CH9_Msk (_U_(0x1) << AFEC_CHER_CH9_Pos) /**< (AFEC_CHER) Channel 9 Enable Mask */ +#define AFEC_CHER_CH9 AFEC_CHER_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH9_Msk instead */ +#define AFEC_CHER_CH10_Pos 10 /**< (AFEC_CHER) Channel 10 Enable Position */ +#define AFEC_CHER_CH10_Msk (_U_(0x1) << AFEC_CHER_CH10_Pos) /**< (AFEC_CHER) Channel 10 Enable Mask */ +#define AFEC_CHER_CH10 AFEC_CHER_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH10_Msk instead */ +#define AFEC_CHER_CH11_Pos 11 /**< (AFEC_CHER) Channel 11 Enable Position */ +#define AFEC_CHER_CH11_Msk (_U_(0x1) << AFEC_CHER_CH11_Pos) /**< (AFEC_CHER) Channel 11 Enable Mask */ +#define AFEC_CHER_CH11 AFEC_CHER_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH11_Msk instead */ +#define AFEC_CHER_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHER) Register MASK (Use AFEC_CHER_Msk instead) */ +#define AFEC_CHER_Msk _U_(0xFFF) /**< (AFEC_CHER) Register Mask */ + +#define AFEC_CHER_CH_Pos 0 /**< (AFEC_CHER Position) Channel xx Enable */ +#define AFEC_CHER_CH_Msk (_U_(0xFFF) << AFEC_CHER_CH_Pos) /**< (AFEC_CHER Mask) CH */ +#define AFEC_CHER_CH(value) (AFEC_CHER_CH_Msk & ((value) << AFEC_CHER_CH_Pos)) + +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) (/W 32) AFEC Channel Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Disable */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Disable */ + uint32_t CH2:1; /**< bit: 2 Channel 2 Disable */ + uint32_t CH3:1; /**< bit: 3 Channel 3 Disable */ + uint32_t CH4:1; /**< bit: 4 Channel 4 Disable */ + uint32_t CH5:1; /**< bit: 5 Channel 5 Disable */ + uint32_t CH6:1; /**< bit: 6 Channel 6 Disable */ + uint32_t CH7:1; /**< bit: 7 Channel 7 Disable */ + uint32_t CH8:1; /**< bit: 8 Channel 8 Disable */ + uint32_t CH9:1; /**< bit: 9 Channel 9 Disable */ + uint32_t CH10:1; /**< bit: 10 Channel 10 Disable */ + uint32_t CH11:1; /**< bit: 11 Channel 11 Disable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:12; /**< bit: 0..11 Channel xx Disable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CHDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CHDR_OFFSET (0x18) /**< (AFEC_CHDR) AFEC Channel Disable Register Offset */ + +#define AFEC_CHDR_CH0_Pos 0 /**< (AFEC_CHDR) Channel 0 Disable Position */ +#define AFEC_CHDR_CH0_Msk (_U_(0x1) << AFEC_CHDR_CH0_Pos) /**< (AFEC_CHDR) Channel 0 Disable Mask */ +#define AFEC_CHDR_CH0 AFEC_CHDR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH0_Msk instead */ +#define AFEC_CHDR_CH1_Pos 1 /**< (AFEC_CHDR) Channel 1 Disable Position */ +#define AFEC_CHDR_CH1_Msk (_U_(0x1) << AFEC_CHDR_CH1_Pos) /**< (AFEC_CHDR) Channel 1 Disable Mask */ +#define AFEC_CHDR_CH1 AFEC_CHDR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH1_Msk instead */ +#define AFEC_CHDR_CH2_Pos 2 /**< (AFEC_CHDR) Channel 2 Disable Position */ +#define AFEC_CHDR_CH2_Msk (_U_(0x1) << AFEC_CHDR_CH2_Pos) /**< (AFEC_CHDR) Channel 2 Disable Mask */ +#define AFEC_CHDR_CH2 AFEC_CHDR_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH2_Msk instead */ +#define AFEC_CHDR_CH3_Pos 3 /**< (AFEC_CHDR) Channel 3 Disable Position */ +#define AFEC_CHDR_CH3_Msk (_U_(0x1) << AFEC_CHDR_CH3_Pos) /**< (AFEC_CHDR) Channel 3 Disable Mask */ +#define AFEC_CHDR_CH3 AFEC_CHDR_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH3_Msk instead */ +#define AFEC_CHDR_CH4_Pos 4 /**< (AFEC_CHDR) Channel 4 Disable Position */ +#define AFEC_CHDR_CH4_Msk (_U_(0x1) << AFEC_CHDR_CH4_Pos) /**< (AFEC_CHDR) Channel 4 Disable Mask */ +#define AFEC_CHDR_CH4 AFEC_CHDR_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH4_Msk instead */ +#define AFEC_CHDR_CH5_Pos 5 /**< (AFEC_CHDR) Channel 5 Disable Position */ +#define AFEC_CHDR_CH5_Msk (_U_(0x1) << AFEC_CHDR_CH5_Pos) /**< (AFEC_CHDR) Channel 5 Disable Mask */ +#define AFEC_CHDR_CH5 AFEC_CHDR_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH5_Msk instead */ +#define AFEC_CHDR_CH6_Pos 6 /**< (AFEC_CHDR) Channel 6 Disable Position */ +#define AFEC_CHDR_CH6_Msk (_U_(0x1) << AFEC_CHDR_CH6_Pos) /**< (AFEC_CHDR) Channel 6 Disable Mask */ +#define AFEC_CHDR_CH6 AFEC_CHDR_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH6_Msk instead */ +#define AFEC_CHDR_CH7_Pos 7 /**< (AFEC_CHDR) Channel 7 Disable Position */ +#define AFEC_CHDR_CH7_Msk (_U_(0x1) << AFEC_CHDR_CH7_Pos) /**< (AFEC_CHDR) Channel 7 Disable Mask */ +#define AFEC_CHDR_CH7 AFEC_CHDR_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH7_Msk instead */ +#define AFEC_CHDR_CH8_Pos 8 /**< (AFEC_CHDR) Channel 8 Disable Position */ +#define AFEC_CHDR_CH8_Msk (_U_(0x1) << AFEC_CHDR_CH8_Pos) /**< (AFEC_CHDR) Channel 8 Disable Mask */ +#define AFEC_CHDR_CH8 AFEC_CHDR_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH8_Msk instead */ +#define AFEC_CHDR_CH9_Pos 9 /**< (AFEC_CHDR) Channel 9 Disable Position */ +#define AFEC_CHDR_CH9_Msk (_U_(0x1) << AFEC_CHDR_CH9_Pos) /**< (AFEC_CHDR) Channel 9 Disable Mask */ +#define AFEC_CHDR_CH9 AFEC_CHDR_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH9_Msk instead */ +#define AFEC_CHDR_CH10_Pos 10 /**< (AFEC_CHDR) Channel 10 Disable Position */ +#define AFEC_CHDR_CH10_Msk (_U_(0x1) << AFEC_CHDR_CH10_Pos) /**< (AFEC_CHDR) Channel 10 Disable Mask */ +#define AFEC_CHDR_CH10 AFEC_CHDR_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH10_Msk instead */ +#define AFEC_CHDR_CH11_Pos 11 /**< (AFEC_CHDR) Channel 11 Disable Position */ +#define AFEC_CHDR_CH11_Msk (_U_(0x1) << AFEC_CHDR_CH11_Pos) /**< (AFEC_CHDR) Channel 11 Disable Mask */ +#define AFEC_CHDR_CH11 AFEC_CHDR_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH11_Msk instead */ +#define AFEC_CHDR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHDR) Register MASK (Use AFEC_CHDR_Msk instead) */ +#define AFEC_CHDR_Msk _U_(0xFFF) /**< (AFEC_CHDR) Register Mask */ + +#define AFEC_CHDR_CH_Pos 0 /**< (AFEC_CHDR Position) Channel xx Disable */ +#define AFEC_CHDR_CH_Msk (_U_(0xFFF) << AFEC_CHDR_CH_Pos) /**< (AFEC_CHDR Mask) CH */ +#define AFEC_CHDR_CH(value) (AFEC_CHDR_CH_Msk & ((value) << AFEC_CHDR_CH_Pos)) + +/* -------- AFEC_CHSR : (AFEC Offset: 0x1c) (R/ 32) AFEC Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Status */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Status */ + uint32_t CH2:1; /**< bit: 2 Channel 2 Status */ + uint32_t CH3:1; /**< bit: 3 Channel 3 Status */ + uint32_t CH4:1; /**< bit: 4 Channel 4 Status */ + uint32_t CH5:1; /**< bit: 5 Channel 5 Status */ + uint32_t CH6:1; /**< bit: 6 Channel 6 Status */ + uint32_t CH7:1; /**< bit: 7 Channel 7 Status */ + uint32_t CH8:1; /**< bit: 8 Channel 8 Status */ + uint32_t CH9:1; /**< bit: 9 Channel 9 Status */ + uint32_t CH10:1; /**< bit: 10 Channel 10 Status */ + uint32_t CH11:1; /**< bit: 11 Channel 11 Status */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:12; /**< bit: 0..11 Channel xx Status */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CHSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CHSR_OFFSET (0x1C) /**< (AFEC_CHSR) AFEC Channel Status Register Offset */ + +#define AFEC_CHSR_CH0_Pos 0 /**< (AFEC_CHSR) Channel 0 Status Position */ +#define AFEC_CHSR_CH0_Msk (_U_(0x1) << AFEC_CHSR_CH0_Pos) /**< (AFEC_CHSR) Channel 0 Status Mask */ +#define AFEC_CHSR_CH0 AFEC_CHSR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH0_Msk instead */ +#define AFEC_CHSR_CH1_Pos 1 /**< (AFEC_CHSR) Channel 1 Status Position */ +#define AFEC_CHSR_CH1_Msk (_U_(0x1) << AFEC_CHSR_CH1_Pos) /**< (AFEC_CHSR) Channel 1 Status Mask */ +#define AFEC_CHSR_CH1 AFEC_CHSR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH1_Msk instead */ +#define AFEC_CHSR_CH2_Pos 2 /**< (AFEC_CHSR) Channel 2 Status Position */ +#define AFEC_CHSR_CH2_Msk (_U_(0x1) << AFEC_CHSR_CH2_Pos) /**< (AFEC_CHSR) Channel 2 Status Mask */ +#define AFEC_CHSR_CH2 AFEC_CHSR_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH2_Msk instead */ +#define AFEC_CHSR_CH3_Pos 3 /**< (AFEC_CHSR) Channel 3 Status Position */ +#define AFEC_CHSR_CH3_Msk (_U_(0x1) << AFEC_CHSR_CH3_Pos) /**< (AFEC_CHSR) Channel 3 Status Mask */ +#define AFEC_CHSR_CH3 AFEC_CHSR_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH3_Msk instead */ +#define AFEC_CHSR_CH4_Pos 4 /**< (AFEC_CHSR) Channel 4 Status Position */ +#define AFEC_CHSR_CH4_Msk (_U_(0x1) << AFEC_CHSR_CH4_Pos) /**< (AFEC_CHSR) Channel 4 Status Mask */ +#define AFEC_CHSR_CH4 AFEC_CHSR_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH4_Msk instead */ +#define AFEC_CHSR_CH5_Pos 5 /**< (AFEC_CHSR) Channel 5 Status Position */ +#define AFEC_CHSR_CH5_Msk (_U_(0x1) << AFEC_CHSR_CH5_Pos) /**< (AFEC_CHSR) Channel 5 Status Mask */ +#define AFEC_CHSR_CH5 AFEC_CHSR_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH5_Msk instead */ +#define AFEC_CHSR_CH6_Pos 6 /**< (AFEC_CHSR) Channel 6 Status Position */ +#define AFEC_CHSR_CH6_Msk (_U_(0x1) << AFEC_CHSR_CH6_Pos) /**< (AFEC_CHSR) Channel 6 Status Mask */ +#define AFEC_CHSR_CH6 AFEC_CHSR_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH6_Msk instead */ +#define AFEC_CHSR_CH7_Pos 7 /**< (AFEC_CHSR) Channel 7 Status Position */ +#define AFEC_CHSR_CH7_Msk (_U_(0x1) << AFEC_CHSR_CH7_Pos) /**< (AFEC_CHSR) Channel 7 Status Mask */ +#define AFEC_CHSR_CH7 AFEC_CHSR_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH7_Msk instead */ +#define AFEC_CHSR_CH8_Pos 8 /**< (AFEC_CHSR) Channel 8 Status Position */ +#define AFEC_CHSR_CH8_Msk (_U_(0x1) << AFEC_CHSR_CH8_Pos) /**< (AFEC_CHSR) Channel 8 Status Mask */ +#define AFEC_CHSR_CH8 AFEC_CHSR_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH8_Msk instead */ +#define AFEC_CHSR_CH9_Pos 9 /**< (AFEC_CHSR) Channel 9 Status Position */ +#define AFEC_CHSR_CH9_Msk (_U_(0x1) << AFEC_CHSR_CH9_Pos) /**< (AFEC_CHSR) Channel 9 Status Mask */ +#define AFEC_CHSR_CH9 AFEC_CHSR_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH9_Msk instead */ +#define AFEC_CHSR_CH10_Pos 10 /**< (AFEC_CHSR) Channel 10 Status Position */ +#define AFEC_CHSR_CH10_Msk (_U_(0x1) << AFEC_CHSR_CH10_Pos) /**< (AFEC_CHSR) Channel 10 Status Mask */ +#define AFEC_CHSR_CH10 AFEC_CHSR_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH10_Msk instead */ +#define AFEC_CHSR_CH11_Pos 11 /**< (AFEC_CHSR) Channel 11 Status Position */ +#define AFEC_CHSR_CH11_Msk (_U_(0x1) << AFEC_CHSR_CH11_Pos) /**< (AFEC_CHSR) Channel 11 Status Mask */ +#define AFEC_CHSR_CH11 AFEC_CHSR_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH11_Msk instead */ +#define AFEC_CHSR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHSR) Register MASK (Use AFEC_CHSR_Msk instead) */ +#define AFEC_CHSR_Msk _U_(0xFFF) /**< (AFEC_CHSR) Register Mask */ + +#define AFEC_CHSR_CH_Pos 0 /**< (AFEC_CHSR Position) Channel xx Status */ +#define AFEC_CHSR_CH_Msk (_U_(0xFFF) << AFEC_CHSR_CH_Pos) /**< (AFEC_CHSR Mask) CH */ +#define AFEC_CHSR_CH(value) (AFEC_CHSR_CH_Msk & ((value) << AFEC_CHSR_CH_Pos)) + +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) (R/ 32) AFEC Last Converted Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LDATA:16; /**< bit: 0..15 Last Data Converted */ + uint32_t :8; /**< bit: 16..23 Reserved */ + uint32_t CHNB:4; /**< bit: 24..27 Channel Number */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_LCDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_LCDR_OFFSET (0x20) /**< (AFEC_LCDR) AFEC Last Converted Data Register Offset */ + +#define AFEC_LCDR_LDATA_Pos 0 /**< (AFEC_LCDR) Last Data Converted Position */ +#define AFEC_LCDR_LDATA_Msk (_U_(0xFFFF) << AFEC_LCDR_LDATA_Pos) /**< (AFEC_LCDR) Last Data Converted Mask */ +#define AFEC_LCDR_LDATA(value) (AFEC_LCDR_LDATA_Msk & ((value) << AFEC_LCDR_LDATA_Pos)) +#define AFEC_LCDR_CHNB_Pos 24 /**< (AFEC_LCDR) Channel Number Position */ +#define AFEC_LCDR_CHNB_Msk (_U_(0xF) << AFEC_LCDR_CHNB_Pos) /**< (AFEC_LCDR) Channel Number Mask */ +#define AFEC_LCDR_CHNB(value) (AFEC_LCDR_CHNB_Msk & ((value) << AFEC_LCDR_CHNB_Pos)) +#define AFEC_LCDR_MASK _U_(0xF00FFFF) /**< \deprecated (AFEC_LCDR) Register MASK (Use AFEC_LCDR_Msk instead) */ +#define AFEC_LCDR_Msk _U_(0xF00FFFF) /**< (AFEC_LCDR) Register Mask */ + + +/* -------- AFEC_IER : (AFEC Offset: 0x24) (/W 32) AFEC Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Enable 0 */ + uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Enable 1 */ + uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Enable 2 */ + uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Enable 3 */ + uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Enable 4 */ + uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Enable 5 */ + uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Enable 6 */ + uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Enable 7 */ + uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Enable 8 */ + uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Enable 9 */ + uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Enable 10 */ + uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Enable 11 */ + uint32_t :12; /**< bit: 12..23 Reserved */ + uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Enable */ + uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Enable */ + uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Enable */ + uint32_t :3; /**< bit: 27..29 Reserved */ + uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Enable */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Enable x */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_IER_OFFSET (0x24) /**< (AFEC_IER) AFEC Interrupt Enable Register Offset */ + +#define AFEC_IER_EOC0_Pos 0 /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Position */ +#define AFEC_IER_EOC0_Msk (_U_(0x1) << AFEC_IER_EOC0_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Mask */ +#define AFEC_IER_EOC0 AFEC_IER_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC0_Msk instead */ +#define AFEC_IER_EOC1_Pos 1 /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Position */ +#define AFEC_IER_EOC1_Msk (_U_(0x1) << AFEC_IER_EOC1_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Mask */ +#define AFEC_IER_EOC1 AFEC_IER_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC1_Msk instead */ +#define AFEC_IER_EOC2_Pos 2 /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Position */ +#define AFEC_IER_EOC2_Msk (_U_(0x1) << AFEC_IER_EOC2_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Mask */ +#define AFEC_IER_EOC2 AFEC_IER_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC2_Msk instead */ +#define AFEC_IER_EOC3_Pos 3 /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Position */ +#define AFEC_IER_EOC3_Msk (_U_(0x1) << AFEC_IER_EOC3_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Mask */ +#define AFEC_IER_EOC3 AFEC_IER_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC3_Msk instead */ +#define AFEC_IER_EOC4_Pos 4 /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Position */ +#define AFEC_IER_EOC4_Msk (_U_(0x1) << AFEC_IER_EOC4_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Mask */ +#define AFEC_IER_EOC4 AFEC_IER_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC4_Msk instead */ +#define AFEC_IER_EOC5_Pos 5 /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Position */ +#define AFEC_IER_EOC5_Msk (_U_(0x1) << AFEC_IER_EOC5_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Mask */ +#define AFEC_IER_EOC5 AFEC_IER_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC5_Msk instead */ +#define AFEC_IER_EOC6_Pos 6 /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Position */ +#define AFEC_IER_EOC6_Msk (_U_(0x1) << AFEC_IER_EOC6_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Mask */ +#define AFEC_IER_EOC6 AFEC_IER_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC6_Msk instead */ +#define AFEC_IER_EOC7_Pos 7 /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Position */ +#define AFEC_IER_EOC7_Msk (_U_(0x1) << AFEC_IER_EOC7_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Mask */ +#define AFEC_IER_EOC7 AFEC_IER_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC7_Msk instead */ +#define AFEC_IER_EOC8_Pos 8 /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Position */ +#define AFEC_IER_EOC8_Msk (_U_(0x1) << AFEC_IER_EOC8_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Mask */ +#define AFEC_IER_EOC8 AFEC_IER_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC8_Msk instead */ +#define AFEC_IER_EOC9_Pos 9 /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Position */ +#define AFEC_IER_EOC9_Msk (_U_(0x1) << AFEC_IER_EOC9_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Mask */ +#define AFEC_IER_EOC9 AFEC_IER_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC9_Msk instead */ +#define AFEC_IER_EOC10_Pos 10 /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Position */ +#define AFEC_IER_EOC10_Msk (_U_(0x1) << AFEC_IER_EOC10_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Mask */ +#define AFEC_IER_EOC10 AFEC_IER_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC10_Msk instead */ +#define AFEC_IER_EOC11_Pos 11 /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Position */ +#define AFEC_IER_EOC11_Msk (_U_(0x1) << AFEC_IER_EOC11_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Mask */ +#define AFEC_IER_EOC11 AFEC_IER_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC11_Msk instead */ +#define AFEC_IER_DRDY_Pos 24 /**< (AFEC_IER) Data Ready Interrupt Enable Position */ +#define AFEC_IER_DRDY_Msk (_U_(0x1) << AFEC_IER_DRDY_Pos) /**< (AFEC_IER) Data Ready Interrupt Enable Mask */ +#define AFEC_IER_DRDY AFEC_IER_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_DRDY_Msk instead */ +#define AFEC_IER_GOVRE_Pos 25 /**< (AFEC_IER) General Overrun Error Interrupt Enable Position */ +#define AFEC_IER_GOVRE_Msk (_U_(0x1) << AFEC_IER_GOVRE_Pos) /**< (AFEC_IER) General Overrun Error Interrupt Enable Mask */ +#define AFEC_IER_GOVRE AFEC_IER_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_GOVRE_Msk instead */ +#define AFEC_IER_COMPE_Pos 26 /**< (AFEC_IER) Comparison Event Interrupt Enable Position */ +#define AFEC_IER_COMPE_Msk (_U_(0x1) << AFEC_IER_COMPE_Pos) /**< (AFEC_IER) Comparison Event Interrupt Enable Mask */ +#define AFEC_IER_COMPE AFEC_IER_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_COMPE_Msk instead */ +#define AFEC_IER_TEMPCHG_Pos 30 /**< (AFEC_IER) Temperature Change Interrupt Enable Position */ +#define AFEC_IER_TEMPCHG_Msk (_U_(0x1) << AFEC_IER_TEMPCHG_Pos) /**< (AFEC_IER) Temperature Change Interrupt Enable Mask */ +#define AFEC_IER_TEMPCHG AFEC_IER_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_TEMPCHG_Msk instead */ +#define AFEC_IER_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IER) Register MASK (Use AFEC_IER_Msk instead) */ +#define AFEC_IER_Msk _U_(0x47000FFF) /**< (AFEC_IER) Register Mask */ + +#define AFEC_IER_EOC_Pos 0 /**< (AFEC_IER Position) End of Conversion Interrupt Enable x */ +#define AFEC_IER_EOC_Msk (_U_(0xFFF) << AFEC_IER_EOC_Pos) /**< (AFEC_IER Mask) EOC */ +#define AFEC_IER_EOC(value) (AFEC_IER_EOC_Msk & ((value) << AFEC_IER_EOC_Pos)) + +/* -------- AFEC_IDR : (AFEC Offset: 0x28) (/W 32) AFEC Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Disable 0 */ + uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Disable 1 */ + uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Disable 2 */ + uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Disable 3 */ + uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Disable 4 */ + uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Disable 5 */ + uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Disable 6 */ + uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Disable 7 */ + uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Disable 8 */ + uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Disable 9 */ + uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Disable 10 */ + uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Disable 11 */ + uint32_t :12; /**< bit: 12..23 Reserved */ + uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Disable */ + uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Disable */ + uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Disable */ + uint32_t :3; /**< bit: 27..29 Reserved */ + uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Disable */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Disable x */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_IDR_OFFSET (0x28) /**< (AFEC_IDR) AFEC Interrupt Disable Register Offset */ + +#define AFEC_IDR_EOC0_Pos 0 /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Position */ +#define AFEC_IDR_EOC0_Msk (_U_(0x1) << AFEC_IDR_EOC0_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Mask */ +#define AFEC_IDR_EOC0 AFEC_IDR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC0_Msk instead */ +#define AFEC_IDR_EOC1_Pos 1 /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Position */ +#define AFEC_IDR_EOC1_Msk (_U_(0x1) << AFEC_IDR_EOC1_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Mask */ +#define AFEC_IDR_EOC1 AFEC_IDR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC1_Msk instead */ +#define AFEC_IDR_EOC2_Pos 2 /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Position */ +#define AFEC_IDR_EOC2_Msk (_U_(0x1) << AFEC_IDR_EOC2_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Mask */ +#define AFEC_IDR_EOC2 AFEC_IDR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC2_Msk instead */ +#define AFEC_IDR_EOC3_Pos 3 /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Position */ +#define AFEC_IDR_EOC3_Msk (_U_(0x1) << AFEC_IDR_EOC3_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Mask */ +#define AFEC_IDR_EOC3 AFEC_IDR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC3_Msk instead */ +#define AFEC_IDR_EOC4_Pos 4 /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Position */ +#define AFEC_IDR_EOC4_Msk (_U_(0x1) << AFEC_IDR_EOC4_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Mask */ +#define AFEC_IDR_EOC4 AFEC_IDR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC4_Msk instead */ +#define AFEC_IDR_EOC5_Pos 5 /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Position */ +#define AFEC_IDR_EOC5_Msk (_U_(0x1) << AFEC_IDR_EOC5_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Mask */ +#define AFEC_IDR_EOC5 AFEC_IDR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC5_Msk instead */ +#define AFEC_IDR_EOC6_Pos 6 /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Position */ +#define AFEC_IDR_EOC6_Msk (_U_(0x1) << AFEC_IDR_EOC6_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Mask */ +#define AFEC_IDR_EOC6 AFEC_IDR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC6_Msk instead */ +#define AFEC_IDR_EOC7_Pos 7 /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Position */ +#define AFEC_IDR_EOC7_Msk (_U_(0x1) << AFEC_IDR_EOC7_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Mask */ +#define AFEC_IDR_EOC7 AFEC_IDR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC7_Msk instead */ +#define AFEC_IDR_EOC8_Pos 8 /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Position */ +#define AFEC_IDR_EOC8_Msk (_U_(0x1) << AFEC_IDR_EOC8_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Mask */ +#define AFEC_IDR_EOC8 AFEC_IDR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC8_Msk instead */ +#define AFEC_IDR_EOC9_Pos 9 /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Position */ +#define AFEC_IDR_EOC9_Msk (_U_(0x1) << AFEC_IDR_EOC9_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Mask */ +#define AFEC_IDR_EOC9 AFEC_IDR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC9_Msk instead */ +#define AFEC_IDR_EOC10_Pos 10 /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Position */ +#define AFEC_IDR_EOC10_Msk (_U_(0x1) << AFEC_IDR_EOC10_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Mask */ +#define AFEC_IDR_EOC10 AFEC_IDR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC10_Msk instead */ +#define AFEC_IDR_EOC11_Pos 11 /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Position */ +#define AFEC_IDR_EOC11_Msk (_U_(0x1) << AFEC_IDR_EOC11_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Mask */ +#define AFEC_IDR_EOC11 AFEC_IDR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC11_Msk instead */ +#define AFEC_IDR_DRDY_Pos 24 /**< (AFEC_IDR) Data Ready Interrupt Disable Position */ +#define AFEC_IDR_DRDY_Msk (_U_(0x1) << AFEC_IDR_DRDY_Pos) /**< (AFEC_IDR) Data Ready Interrupt Disable Mask */ +#define AFEC_IDR_DRDY AFEC_IDR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_DRDY_Msk instead */ +#define AFEC_IDR_GOVRE_Pos 25 /**< (AFEC_IDR) General Overrun Error Interrupt Disable Position */ +#define AFEC_IDR_GOVRE_Msk (_U_(0x1) << AFEC_IDR_GOVRE_Pos) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Mask */ +#define AFEC_IDR_GOVRE AFEC_IDR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_GOVRE_Msk instead */ +#define AFEC_IDR_COMPE_Pos 26 /**< (AFEC_IDR) Comparison Event Interrupt Disable Position */ +#define AFEC_IDR_COMPE_Msk (_U_(0x1) << AFEC_IDR_COMPE_Pos) /**< (AFEC_IDR) Comparison Event Interrupt Disable Mask */ +#define AFEC_IDR_COMPE AFEC_IDR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_COMPE_Msk instead */ +#define AFEC_IDR_TEMPCHG_Pos 30 /**< (AFEC_IDR) Temperature Change Interrupt Disable Position */ +#define AFEC_IDR_TEMPCHG_Msk (_U_(0x1) << AFEC_IDR_TEMPCHG_Pos) /**< (AFEC_IDR) Temperature Change Interrupt Disable Mask */ +#define AFEC_IDR_TEMPCHG AFEC_IDR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_TEMPCHG_Msk instead */ +#define AFEC_IDR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IDR) Register MASK (Use AFEC_IDR_Msk instead) */ +#define AFEC_IDR_Msk _U_(0x47000FFF) /**< (AFEC_IDR) Register Mask */ + +#define AFEC_IDR_EOC_Pos 0 /**< (AFEC_IDR Position) End of Conversion Interrupt Disable x */ +#define AFEC_IDR_EOC_Msk (_U_(0xFFF) << AFEC_IDR_EOC_Pos) /**< (AFEC_IDR Mask) EOC */ +#define AFEC_IDR_EOC(value) (AFEC_IDR_EOC_Msk & ((value) << AFEC_IDR_EOC_Pos)) + +/* -------- AFEC_IMR : (AFEC Offset: 0x2c) (R/ 32) AFEC Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Mask 0 */ + uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Mask 1 */ + uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Mask 2 */ + uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Mask 3 */ + uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Mask 4 */ + uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Mask 5 */ + uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Mask 6 */ + uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Mask 7 */ + uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Mask 8 */ + uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Mask 9 */ + uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Mask 10 */ + uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Mask 11 */ + uint32_t :12; /**< bit: 12..23 Reserved */ + uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Mask */ + uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Mask */ + uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Mask */ + uint32_t :3; /**< bit: 27..29 Reserved */ + uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Mask */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Mask x */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_IMR_OFFSET (0x2C) /**< (AFEC_IMR) AFEC Interrupt Mask Register Offset */ + +#define AFEC_IMR_EOC0_Pos 0 /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Position */ +#define AFEC_IMR_EOC0_Msk (_U_(0x1) << AFEC_IMR_EOC0_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Mask */ +#define AFEC_IMR_EOC0 AFEC_IMR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC0_Msk instead */ +#define AFEC_IMR_EOC1_Pos 1 /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Position */ +#define AFEC_IMR_EOC1_Msk (_U_(0x1) << AFEC_IMR_EOC1_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Mask */ +#define AFEC_IMR_EOC1 AFEC_IMR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC1_Msk instead */ +#define AFEC_IMR_EOC2_Pos 2 /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Position */ +#define AFEC_IMR_EOC2_Msk (_U_(0x1) << AFEC_IMR_EOC2_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Mask */ +#define AFEC_IMR_EOC2 AFEC_IMR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC2_Msk instead */ +#define AFEC_IMR_EOC3_Pos 3 /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Position */ +#define AFEC_IMR_EOC3_Msk (_U_(0x1) << AFEC_IMR_EOC3_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Mask */ +#define AFEC_IMR_EOC3 AFEC_IMR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC3_Msk instead */ +#define AFEC_IMR_EOC4_Pos 4 /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Position */ +#define AFEC_IMR_EOC4_Msk (_U_(0x1) << AFEC_IMR_EOC4_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Mask */ +#define AFEC_IMR_EOC4 AFEC_IMR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC4_Msk instead */ +#define AFEC_IMR_EOC5_Pos 5 /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Position */ +#define AFEC_IMR_EOC5_Msk (_U_(0x1) << AFEC_IMR_EOC5_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Mask */ +#define AFEC_IMR_EOC5 AFEC_IMR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC5_Msk instead */ +#define AFEC_IMR_EOC6_Pos 6 /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Position */ +#define AFEC_IMR_EOC6_Msk (_U_(0x1) << AFEC_IMR_EOC6_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Mask */ +#define AFEC_IMR_EOC6 AFEC_IMR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC6_Msk instead */ +#define AFEC_IMR_EOC7_Pos 7 /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Position */ +#define AFEC_IMR_EOC7_Msk (_U_(0x1) << AFEC_IMR_EOC7_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Mask */ +#define AFEC_IMR_EOC7 AFEC_IMR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC7_Msk instead */ +#define AFEC_IMR_EOC8_Pos 8 /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Position */ +#define AFEC_IMR_EOC8_Msk (_U_(0x1) << AFEC_IMR_EOC8_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Mask */ +#define AFEC_IMR_EOC8 AFEC_IMR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC8_Msk instead */ +#define AFEC_IMR_EOC9_Pos 9 /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Position */ +#define AFEC_IMR_EOC9_Msk (_U_(0x1) << AFEC_IMR_EOC9_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Mask */ +#define AFEC_IMR_EOC9 AFEC_IMR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC9_Msk instead */ +#define AFEC_IMR_EOC10_Pos 10 /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Position */ +#define AFEC_IMR_EOC10_Msk (_U_(0x1) << AFEC_IMR_EOC10_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Mask */ +#define AFEC_IMR_EOC10 AFEC_IMR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC10_Msk instead */ +#define AFEC_IMR_EOC11_Pos 11 /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Position */ +#define AFEC_IMR_EOC11_Msk (_U_(0x1) << AFEC_IMR_EOC11_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Mask */ +#define AFEC_IMR_EOC11 AFEC_IMR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC11_Msk instead */ +#define AFEC_IMR_DRDY_Pos 24 /**< (AFEC_IMR) Data Ready Interrupt Mask Position */ +#define AFEC_IMR_DRDY_Msk (_U_(0x1) << AFEC_IMR_DRDY_Pos) /**< (AFEC_IMR) Data Ready Interrupt Mask Mask */ +#define AFEC_IMR_DRDY AFEC_IMR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_DRDY_Msk instead */ +#define AFEC_IMR_GOVRE_Pos 25 /**< (AFEC_IMR) General Overrun Error Interrupt Mask Position */ +#define AFEC_IMR_GOVRE_Msk (_U_(0x1) << AFEC_IMR_GOVRE_Pos) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Mask */ +#define AFEC_IMR_GOVRE AFEC_IMR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_GOVRE_Msk instead */ +#define AFEC_IMR_COMPE_Pos 26 /**< (AFEC_IMR) Comparison Event Interrupt Mask Position */ +#define AFEC_IMR_COMPE_Msk (_U_(0x1) << AFEC_IMR_COMPE_Pos) /**< (AFEC_IMR) Comparison Event Interrupt Mask Mask */ +#define AFEC_IMR_COMPE AFEC_IMR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_COMPE_Msk instead */ +#define AFEC_IMR_TEMPCHG_Pos 30 /**< (AFEC_IMR) Temperature Change Interrupt Mask Position */ +#define AFEC_IMR_TEMPCHG_Msk (_U_(0x1) << AFEC_IMR_TEMPCHG_Pos) /**< (AFEC_IMR) Temperature Change Interrupt Mask Mask */ +#define AFEC_IMR_TEMPCHG AFEC_IMR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_TEMPCHG_Msk instead */ +#define AFEC_IMR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IMR) Register MASK (Use AFEC_IMR_Msk instead) */ +#define AFEC_IMR_Msk _U_(0x47000FFF) /**< (AFEC_IMR) Register Mask */ + +#define AFEC_IMR_EOC_Pos 0 /**< (AFEC_IMR Position) End of Conversion Interrupt Mask x */ +#define AFEC_IMR_EOC_Msk (_U_(0xFFF) << AFEC_IMR_EOC_Pos) /**< (AFEC_IMR Mask) EOC */ +#define AFEC_IMR_EOC(value) (AFEC_IMR_EOC_Msk & ((value) << AFEC_IMR_EOC_Pos)) + +/* -------- AFEC_ISR : (AFEC Offset: 0x30) (R/ 32) AFEC Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EOC0:1; /**< bit: 0 End of Conversion 0 (cleared by reading AFEC_CDRx) */ + uint32_t EOC1:1; /**< bit: 1 End of Conversion 1 (cleared by reading AFEC_CDRx) */ + uint32_t EOC2:1; /**< bit: 2 End of Conversion 2 (cleared by reading AFEC_CDRx) */ + uint32_t EOC3:1; /**< bit: 3 End of Conversion 3 (cleared by reading AFEC_CDRx) */ + uint32_t EOC4:1; /**< bit: 4 End of Conversion 4 (cleared by reading AFEC_CDRx) */ + uint32_t EOC5:1; /**< bit: 5 End of Conversion 5 (cleared by reading AFEC_CDRx) */ + uint32_t EOC6:1; /**< bit: 6 End of Conversion 6 (cleared by reading AFEC_CDRx) */ + uint32_t EOC7:1; /**< bit: 7 End of Conversion 7 (cleared by reading AFEC_CDRx) */ + uint32_t EOC8:1; /**< bit: 8 End of Conversion 8 (cleared by reading AFEC_CDRx) */ + uint32_t EOC9:1; /**< bit: 9 End of Conversion 9 (cleared by reading AFEC_CDRx) */ + uint32_t EOC10:1; /**< bit: 10 End of Conversion 10 (cleared by reading AFEC_CDRx) */ + uint32_t EOC11:1; /**< bit: 11 End of Conversion 11 (cleared by reading AFEC_CDRx) */ + uint32_t :12; /**< bit: 12..23 Reserved */ + uint32_t DRDY:1; /**< bit: 24 Data Ready (cleared by reading AFEC_LCDR) */ + uint32_t GOVRE:1; /**< bit: 25 General Overrun Error (cleared by reading AFEC_ISR) */ + uint32_t COMPE:1; /**< bit: 26 Comparison Error (cleared by reading AFEC_ISR) */ + uint32_t :3; /**< bit: 27..29 Reserved */ + uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change (cleared on read) */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EOC:12; /**< bit: 0..11 End of Conversion x (cleared by reading AFEC_CDRx) */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_ISR_OFFSET (0x30) /**< (AFEC_ISR) AFEC Interrupt Status Register Offset */ + +#define AFEC_ISR_EOC0_Pos 0 /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC0_Msk (_U_(0x1) << AFEC_ISR_EOC0_Pos) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC0 AFEC_ISR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC0_Msk instead */ +#define AFEC_ISR_EOC1_Pos 1 /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC1_Msk (_U_(0x1) << AFEC_ISR_EOC1_Pos) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC1 AFEC_ISR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC1_Msk instead */ +#define AFEC_ISR_EOC2_Pos 2 /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC2_Msk (_U_(0x1) << AFEC_ISR_EOC2_Pos) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC2 AFEC_ISR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC2_Msk instead */ +#define AFEC_ISR_EOC3_Pos 3 /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC3_Msk (_U_(0x1) << AFEC_ISR_EOC3_Pos) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC3 AFEC_ISR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC3_Msk instead */ +#define AFEC_ISR_EOC4_Pos 4 /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC4_Msk (_U_(0x1) << AFEC_ISR_EOC4_Pos) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC4 AFEC_ISR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC4_Msk instead */ +#define AFEC_ISR_EOC5_Pos 5 /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC5_Msk (_U_(0x1) << AFEC_ISR_EOC5_Pos) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC5 AFEC_ISR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC5_Msk instead */ +#define AFEC_ISR_EOC6_Pos 6 /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC6_Msk (_U_(0x1) << AFEC_ISR_EOC6_Pos) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC6 AFEC_ISR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC6_Msk instead */ +#define AFEC_ISR_EOC7_Pos 7 /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC7_Msk (_U_(0x1) << AFEC_ISR_EOC7_Pos) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC7 AFEC_ISR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC7_Msk instead */ +#define AFEC_ISR_EOC8_Pos 8 /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC8_Msk (_U_(0x1) << AFEC_ISR_EOC8_Pos) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC8 AFEC_ISR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC8_Msk instead */ +#define AFEC_ISR_EOC9_Pos 9 /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC9_Msk (_U_(0x1) << AFEC_ISR_EOC9_Pos) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC9 AFEC_ISR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC9_Msk instead */ +#define AFEC_ISR_EOC10_Pos 10 /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC10_Msk (_U_(0x1) << AFEC_ISR_EOC10_Pos) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC10 AFEC_ISR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC10_Msk instead */ +#define AFEC_ISR_EOC11_Pos 11 /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC11_Msk (_U_(0x1) << AFEC_ISR_EOC11_Pos) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC11 AFEC_ISR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC11_Msk instead */ +#define AFEC_ISR_DRDY_Pos 24 /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Position */ +#define AFEC_ISR_DRDY_Msk (_U_(0x1) << AFEC_ISR_DRDY_Pos) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Mask */ +#define AFEC_ISR_DRDY AFEC_ISR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_DRDY_Msk instead */ +#define AFEC_ISR_GOVRE_Pos 25 /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_GOVRE_Msk (_U_(0x1) << AFEC_ISR_GOVRE_Pos) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_GOVRE AFEC_ISR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_GOVRE_Msk instead */ +#define AFEC_ISR_COMPE_Pos 26 /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_COMPE_Msk (_U_(0x1) << AFEC_ISR_COMPE_Pos) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_COMPE AFEC_ISR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_COMPE_Msk instead */ +#define AFEC_ISR_TEMPCHG_Pos 30 /**< (AFEC_ISR) Temperature Change (cleared on read) Position */ +#define AFEC_ISR_TEMPCHG_Msk (_U_(0x1) << AFEC_ISR_TEMPCHG_Pos) /**< (AFEC_ISR) Temperature Change (cleared on read) Mask */ +#define AFEC_ISR_TEMPCHG AFEC_ISR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_TEMPCHG_Msk instead */ +#define AFEC_ISR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_ISR) Register MASK (Use AFEC_ISR_Msk instead) */ +#define AFEC_ISR_Msk _U_(0x47000FFF) /**< (AFEC_ISR) Register Mask */ + +#define AFEC_ISR_EOC_Pos 0 /**< (AFEC_ISR Position) End of Conversion x (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC_Msk (_U_(0xFFF) << AFEC_ISR_EOC_Pos) /**< (AFEC_ISR Mask) EOC */ +#define AFEC_ISR_EOC(value) (AFEC_ISR_EOC_Msk & ((value) << AFEC_ISR_EOC_Pos)) + +/* -------- AFEC_OVER : (AFEC Offset: 0x4c) (R/ 32) AFEC Overrun Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OVRE0:1; /**< bit: 0 Overrun Error 0 */ + uint32_t OVRE1:1; /**< bit: 1 Overrun Error 1 */ + uint32_t OVRE2:1; /**< bit: 2 Overrun Error 2 */ + uint32_t OVRE3:1; /**< bit: 3 Overrun Error 3 */ + uint32_t OVRE4:1; /**< bit: 4 Overrun Error 4 */ + uint32_t OVRE5:1; /**< bit: 5 Overrun Error 5 */ + uint32_t OVRE6:1; /**< bit: 6 Overrun Error 6 */ + uint32_t OVRE7:1; /**< bit: 7 Overrun Error 7 */ + uint32_t OVRE8:1; /**< bit: 8 Overrun Error 8 */ + uint32_t OVRE9:1; /**< bit: 9 Overrun Error 9 */ + uint32_t OVRE10:1; /**< bit: 10 Overrun Error 10 */ + uint32_t OVRE11:1; /**< bit: 11 Overrun Error 11 */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OVRE:12; /**< bit: 0..11 Overrun Error xx */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_OVER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_OVER_OFFSET (0x4C) /**< (AFEC_OVER) AFEC Overrun Status Register Offset */ + +#define AFEC_OVER_OVRE0_Pos 0 /**< (AFEC_OVER) Overrun Error 0 Position */ +#define AFEC_OVER_OVRE0_Msk (_U_(0x1) << AFEC_OVER_OVRE0_Pos) /**< (AFEC_OVER) Overrun Error 0 Mask */ +#define AFEC_OVER_OVRE0 AFEC_OVER_OVRE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE0_Msk instead */ +#define AFEC_OVER_OVRE1_Pos 1 /**< (AFEC_OVER) Overrun Error 1 Position */ +#define AFEC_OVER_OVRE1_Msk (_U_(0x1) << AFEC_OVER_OVRE1_Pos) /**< (AFEC_OVER) Overrun Error 1 Mask */ +#define AFEC_OVER_OVRE1 AFEC_OVER_OVRE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE1_Msk instead */ +#define AFEC_OVER_OVRE2_Pos 2 /**< (AFEC_OVER) Overrun Error 2 Position */ +#define AFEC_OVER_OVRE2_Msk (_U_(0x1) << AFEC_OVER_OVRE2_Pos) /**< (AFEC_OVER) Overrun Error 2 Mask */ +#define AFEC_OVER_OVRE2 AFEC_OVER_OVRE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE2_Msk instead */ +#define AFEC_OVER_OVRE3_Pos 3 /**< (AFEC_OVER) Overrun Error 3 Position */ +#define AFEC_OVER_OVRE3_Msk (_U_(0x1) << AFEC_OVER_OVRE3_Pos) /**< (AFEC_OVER) Overrun Error 3 Mask */ +#define AFEC_OVER_OVRE3 AFEC_OVER_OVRE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE3_Msk instead */ +#define AFEC_OVER_OVRE4_Pos 4 /**< (AFEC_OVER) Overrun Error 4 Position */ +#define AFEC_OVER_OVRE4_Msk (_U_(0x1) << AFEC_OVER_OVRE4_Pos) /**< (AFEC_OVER) Overrun Error 4 Mask */ +#define AFEC_OVER_OVRE4 AFEC_OVER_OVRE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE4_Msk instead */ +#define AFEC_OVER_OVRE5_Pos 5 /**< (AFEC_OVER) Overrun Error 5 Position */ +#define AFEC_OVER_OVRE5_Msk (_U_(0x1) << AFEC_OVER_OVRE5_Pos) /**< (AFEC_OVER) Overrun Error 5 Mask */ +#define AFEC_OVER_OVRE5 AFEC_OVER_OVRE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE5_Msk instead */ +#define AFEC_OVER_OVRE6_Pos 6 /**< (AFEC_OVER) Overrun Error 6 Position */ +#define AFEC_OVER_OVRE6_Msk (_U_(0x1) << AFEC_OVER_OVRE6_Pos) /**< (AFEC_OVER) Overrun Error 6 Mask */ +#define AFEC_OVER_OVRE6 AFEC_OVER_OVRE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE6_Msk instead */ +#define AFEC_OVER_OVRE7_Pos 7 /**< (AFEC_OVER) Overrun Error 7 Position */ +#define AFEC_OVER_OVRE7_Msk (_U_(0x1) << AFEC_OVER_OVRE7_Pos) /**< (AFEC_OVER) Overrun Error 7 Mask */ +#define AFEC_OVER_OVRE7 AFEC_OVER_OVRE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE7_Msk instead */ +#define AFEC_OVER_OVRE8_Pos 8 /**< (AFEC_OVER) Overrun Error 8 Position */ +#define AFEC_OVER_OVRE8_Msk (_U_(0x1) << AFEC_OVER_OVRE8_Pos) /**< (AFEC_OVER) Overrun Error 8 Mask */ +#define AFEC_OVER_OVRE8 AFEC_OVER_OVRE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE8_Msk instead */ +#define AFEC_OVER_OVRE9_Pos 9 /**< (AFEC_OVER) Overrun Error 9 Position */ +#define AFEC_OVER_OVRE9_Msk (_U_(0x1) << AFEC_OVER_OVRE9_Pos) /**< (AFEC_OVER) Overrun Error 9 Mask */ +#define AFEC_OVER_OVRE9 AFEC_OVER_OVRE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE9_Msk instead */ +#define AFEC_OVER_OVRE10_Pos 10 /**< (AFEC_OVER) Overrun Error 10 Position */ +#define AFEC_OVER_OVRE10_Msk (_U_(0x1) << AFEC_OVER_OVRE10_Pos) /**< (AFEC_OVER) Overrun Error 10 Mask */ +#define AFEC_OVER_OVRE10 AFEC_OVER_OVRE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE10_Msk instead */ +#define AFEC_OVER_OVRE11_Pos 11 /**< (AFEC_OVER) Overrun Error 11 Position */ +#define AFEC_OVER_OVRE11_Msk (_U_(0x1) << AFEC_OVER_OVRE11_Pos) /**< (AFEC_OVER) Overrun Error 11 Mask */ +#define AFEC_OVER_OVRE11 AFEC_OVER_OVRE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE11_Msk instead */ +#define AFEC_OVER_MASK _U_(0xFFF) /**< \deprecated (AFEC_OVER) Register MASK (Use AFEC_OVER_Msk instead) */ +#define AFEC_OVER_Msk _U_(0xFFF) /**< (AFEC_OVER) Register Mask */ + +#define AFEC_OVER_OVRE_Pos 0 /**< (AFEC_OVER Position) Overrun Error xx */ +#define AFEC_OVER_OVRE_Msk (_U_(0xFFF) << AFEC_OVER_OVRE_Pos) /**< (AFEC_OVER Mask) OVRE */ +#define AFEC_OVER_OVRE(value) (AFEC_OVER_OVRE_Msk & ((value) << AFEC_OVER_OVRE_Pos)) + +/* -------- AFEC_CWR : (AFEC Offset: 0x50) (R/W 32) AFEC Compare Window Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LOWTHRES:16; /**< bit: 0..15 Low Threshold */ + uint32_t HIGHTHRES:16; /**< bit: 16..31 High Threshold */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CWR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CWR_OFFSET (0x50) /**< (AFEC_CWR) AFEC Compare Window Register Offset */ + +#define AFEC_CWR_LOWTHRES_Pos 0 /**< (AFEC_CWR) Low Threshold Position */ +#define AFEC_CWR_LOWTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_LOWTHRES_Pos) /**< (AFEC_CWR) Low Threshold Mask */ +#define AFEC_CWR_LOWTHRES(value) (AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)) +#define AFEC_CWR_HIGHTHRES_Pos 16 /**< (AFEC_CWR) High Threshold Position */ +#define AFEC_CWR_HIGHTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_HIGHTHRES_Pos) /**< (AFEC_CWR) High Threshold Mask */ +#define AFEC_CWR_HIGHTHRES(value) (AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)) +#define AFEC_CWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_CWR) Register MASK (Use AFEC_CWR_Msk instead) */ +#define AFEC_CWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CWR) Register Mask */ + + +/* -------- AFEC_CGR : (AFEC Offset: 0x54) (R/W 32) AFEC Channel Gain Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t GAIN0:2; /**< bit: 0..1 Gain for Channel 0 */ + uint32_t GAIN1:2; /**< bit: 2..3 Gain for Channel 1 */ + uint32_t GAIN2:2; /**< bit: 4..5 Gain for Channel 2 */ + uint32_t GAIN3:2; /**< bit: 6..7 Gain for Channel 3 */ + uint32_t GAIN4:2; /**< bit: 8..9 Gain for Channel 4 */ + uint32_t GAIN5:2; /**< bit: 10..11 Gain for Channel 5 */ + uint32_t GAIN6:2; /**< bit: 12..13 Gain for Channel 6 */ + uint32_t GAIN7:2; /**< bit: 14..15 Gain for Channel 7 */ + uint32_t GAIN8:2; /**< bit: 16..17 Gain for Channel 8 */ + uint32_t GAIN9:2; /**< bit: 18..19 Gain for Channel 9 */ + uint32_t GAIN10:2; /**< bit: 20..21 Gain for Channel 10 */ + uint32_t GAIN11:2; /**< bit: 22..23 Gain for Channel 11 */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CGR_OFFSET (0x54) /**< (AFEC_CGR) AFEC Channel Gain Register Offset */ + +#define AFEC_CGR_GAIN0_Pos 0 /**< (AFEC_CGR) Gain for Channel 0 Position */ +#define AFEC_CGR_GAIN0_Msk (_U_(0x3) << AFEC_CGR_GAIN0_Pos) /**< (AFEC_CGR) Gain for Channel 0 Mask */ +#define AFEC_CGR_GAIN0(value) (AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)) +#define AFEC_CGR_GAIN1_Pos 2 /**< (AFEC_CGR) Gain for Channel 1 Position */ +#define AFEC_CGR_GAIN1_Msk (_U_(0x3) << AFEC_CGR_GAIN1_Pos) /**< (AFEC_CGR) Gain for Channel 1 Mask */ +#define AFEC_CGR_GAIN1(value) (AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)) +#define AFEC_CGR_GAIN2_Pos 4 /**< (AFEC_CGR) Gain for Channel 2 Position */ +#define AFEC_CGR_GAIN2_Msk (_U_(0x3) << AFEC_CGR_GAIN2_Pos) /**< (AFEC_CGR) Gain for Channel 2 Mask */ +#define AFEC_CGR_GAIN2(value) (AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)) +#define AFEC_CGR_GAIN3_Pos 6 /**< (AFEC_CGR) Gain for Channel 3 Position */ +#define AFEC_CGR_GAIN3_Msk (_U_(0x3) << AFEC_CGR_GAIN3_Pos) /**< (AFEC_CGR) Gain for Channel 3 Mask */ +#define AFEC_CGR_GAIN3(value) (AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)) +#define AFEC_CGR_GAIN4_Pos 8 /**< (AFEC_CGR) Gain for Channel 4 Position */ +#define AFEC_CGR_GAIN4_Msk (_U_(0x3) << AFEC_CGR_GAIN4_Pos) /**< (AFEC_CGR) Gain for Channel 4 Mask */ +#define AFEC_CGR_GAIN4(value) (AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)) +#define AFEC_CGR_GAIN5_Pos 10 /**< (AFEC_CGR) Gain for Channel 5 Position */ +#define AFEC_CGR_GAIN5_Msk (_U_(0x3) << AFEC_CGR_GAIN5_Pos) /**< (AFEC_CGR) Gain for Channel 5 Mask */ +#define AFEC_CGR_GAIN5(value) (AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)) +#define AFEC_CGR_GAIN6_Pos 12 /**< (AFEC_CGR) Gain for Channel 6 Position */ +#define AFEC_CGR_GAIN6_Msk (_U_(0x3) << AFEC_CGR_GAIN6_Pos) /**< (AFEC_CGR) Gain for Channel 6 Mask */ +#define AFEC_CGR_GAIN6(value) (AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)) +#define AFEC_CGR_GAIN7_Pos 14 /**< (AFEC_CGR) Gain for Channel 7 Position */ +#define AFEC_CGR_GAIN7_Msk (_U_(0x3) << AFEC_CGR_GAIN7_Pos) /**< (AFEC_CGR) Gain for Channel 7 Mask */ +#define AFEC_CGR_GAIN7(value) (AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)) +#define AFEC_CGR_GAIN8_Pos 16 /**< (AFEC_CGR) Gain for Channel 8 Position */ +#define AFEC_CGR_GAIN8_Msk (_U_(0x3) << AFEC_CGR_GAIN8_Pos) /**< (AFEC_CGR) Gain for Channel 8 Mask */ +#define AFEC_CGR_GAIN8(value) (AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)) +#define AFEC_CGR_GAIN9_Pos 18 /**< (AFEC_CGR) Gain for Channel 9 Position */ +#define AFEC_CGR_GAIN9_Msk (_U_(0x3) << AFEC_CGR_GAIN9_Pos) /**< (AFEC_CGR) Gain for Channel 9 Mask */ +#define AFEC_CGR_GAIN9(value) (AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)) +#define AFEC_CGR_GAIN10_Pos 20 /**< (AFEC_CGR) Gain for Channel 10 Position */ +#define AFEC_CGR_GAIN10_Msk (_U_(0x3) << AFEC_CGR_GAIN10_Pos) /**< (AFEC_CGR) Gain for Channel 10 Mask */ +#define AFEC_CGR_GAIN10(value) (AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)) +#define AFEC_CGR_GAIN11_Pos 22 /**< (AFEC_CGR) Gain for Channel 11 Position */ +#define AFEC_CGR_GAIN11_Msk (_U_(0x3) << AFEC_CGR_GAIN11_Pos) /**< (AFEC_CGR) Gain for Channel 11 Mask */ +#define AFEC_CGR_GAIN11(value) (AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)) +#define AFEC_CGR_MASK _U_(0xFFFFFF) /**< \deprecated (AFEC_CGR) Register MASK (Use AFEC_CGR_Msk instead) */ +#define AFEC_CGR_Msk _U_(0xFFFFFF) /**< (AFEC_CGR) Register Mask */ + + +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) (R/W 32) AFEC Channel Differential Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DIFF0:1; /**< bit: 0 Differential inputs for channel 0 */ + uint32_t DIFF1:1; /**< bit: 1 Differential inputs for channel 1 */ + uint32_t DIFF2:1; /**< bit: 2 Differential inputs for channel 2 */ + uint32_t DIFF3:1; /**< bit: 3 Differential inputs for channel 3 */ + uint32_t DIFF4:1; /**< bit: 4 Differential inputs for channel 4 */ + uint32_t DIFF5:1; /**< bit: 5 Differential inputs for channel 5 */ + uint32_t DIFF6:1; /**< bit: 6 Differential inputs for channel 6 */ + uint32_t DIFF7:1; /**< bit: 7 Differential inputs for channel 7 */ + uint32_t DIFF8:1; /**< bit: 8 Differential inputs for channel 8 */ + uint32_t DIFF9:1; /**< bit: 9 Differential inputs for channel 9 */ + uint32_t DIFF10:1; /**< bit: 10 Differential inputs for channel 10 */ + uint32_t DIFF11:1; /**< bit: 11 Differential inputs for channel 11 */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t DIFF:12; /**< bit: 0..11 Differential inputs for channel xx */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_DIFFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_DIFFR_OFFSET (0x60) /**< (AFEC_DIFFR) AFEC Channel Differential Register Offset */ + +#define AFEC_DIFFR_DIFF0_Pos 0 /**< (AFEC_DIFFR) Differential inputs for channel 0 Position */ +#define AFEC_DIFFR_DIFF0_Msk (_U_(0x1) << AFEC_DIFFR_DIFF0_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 0 Mask */ +#define AFEC_DIFFR_DIFF0 AFEC_DIFFR_DIFF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF0_Msk instead */ +#define AFEC_DIFFR_DIFF1_Pos 1 /**< (AFEC_DIFFR) Differential inputs for channel 1 Position */ +#define AFEC_DIFFR_DIFF1_Msk (_U_(0x1) << AFEC_DIFFR_DIFF1_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 1 Mask */ +#define AFEC_DIFFR_DIFF1 AFEC_DIFFR_DIFF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF1_Msk instead */ +#define AFEC_DIFFR_DIFF2_Pos 2 /**< (AFEC_DIFFR) Differential inputs for channel 2 Position */ +#define AFEC_DIFFR_DIFF2_Msk (_U_(0x1) << AFEC_DIFFR_DIFF2_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 2 Mask */ +#define AFEC_DIFFR_DIFF2 AFEC_DIFFR_DIFF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF2_Msk instead */ +#define AFEC_DIFFR_DIFF3_Pos 3 /**< (AFEC_DIFFR) Differential inputs for channel 3 Position */ +#define AFEC_DIFFR_DIFF3_Msk (_U_(0x1) << AFEC_DIFFR_DIFF3_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 3 Mask */ +#define AFEC_DIFFR_DIFF3 AFEC_DIFFR_DIFF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF3_Msk instead */ +#define AFEC_DIFFR_DIFF4_Pos 4 /**< (AFEC_DIFFR) Differential inputs for channel 4 Position */ +#define AFEC_DIFFR_DIFF4_Msk (_U_(0x1) << AFEC_DIFFR_DIFF4_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 4 Mask */ +#define AFEC_DIFFR_DIFF4 AFEC_DIFFR_DIFF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF4_Msk instead */ +#define AFEC_DIFFR_DIFF5_Pos 5 /**< (AFEC_DIFFR) Differential inputs for channel 5 Position */ +#define AFEC_DIFFR_DIFF5_Msk (_U_(0x1) << AFEC_DIFFR_DIFF5_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 5 Mask */ +#define AFEC_DIFFR_DIFF5 AFEC_DIFFR_DIFF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF5_Msk instead */ +#define AFEC_DIFFR_DIFF6_Pos 6 /**< (AFEC_DIFFR) Differential inputs for channel 6 Position */ +#define AFEC_DIFFR_DIFF6_Msk (_U_(0x1) << AFEC_DIFFR_DIFF6_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 6 Mask */ +#define AFEC_DIFFR_DIFF6 AFEC_DIFFR_DIFF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF6_Msk instead */ +#define AFEC_DIFFR_DIFF7_Pos 7 /**< (AFEC_DIFFR) Differential inputs for channel 7 Position */ +#define AFEC_DIFFR_DIFF7_Msk (_U_(0x1) << AFEC_DIFFR_DIFF7_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 7 Mask */ +#define AFEC_DIFFR_DIFF7 AFEC_DIFFR_DIFF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF7_Msk instead */ +#define AFEC_DIFFR_DIFF8_Pos 8 /**< (AFEC_DIFFR) Differential inputs for channel 8 Position */ +#define AFEC_DIFFR_DIFF8_Msk (_U_(0x1) << AFEC_DIFFR_DIFF8_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 8 Mask */ +#define AFEC_DIFFR_DIFF8 AFEC_DIFFR_DIFF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF8_Msk instead */ +#define AFEC_DIFFR_DIFF9_Pos 9 /**< (AFEC_DIFFR) Differential inputs for channel 9 Position */ +#define AFEC_DIFFR_DIFF9_Msk (_U_(0x1) << AFEC_DIFFR_DIFF9_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 9 Mask */ +#define AFEC_DIFFR_DIFF9 AFEC_DIFFR_DIFF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF9_Msk instead */ +#define AFEC_DIFFR_DIFF10_Pos 10 /**< (AFEC_DIFFR) Differential inputs for channel 10 Position */ +#define AFEC_DIFFR_DIFF10_Msk (_U_(0x1) << AFEC_DIFFR_DIFF10_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 10 Mask */ +#define AFEC_DIFFR_DIFF10 AFEC_DIFFR_DIFF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF10_Msk instead */ +#define AFEC_DIFFR_DIFF11_Pos 11 /**< (AFEC_DIFFR) Differential inputs for channel 11 Position */ +#define AFEC_DIFFR_DIFF11_Msk (_U_(0x1) << AFEC_DIFFR_DIFF11_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 11 Mask */ +#define AFEC_DIFFR_DIFF11 AFEC_DIFFR_DIFF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF11_Msk instead */ +#define AFEC_DIFFR_MASK _U_(0xFFF) /**< \deprecated (AFEC_DIFFR) Register MASK (Use AFEC_DIFFR_Msk instead) */ +#define AFEC_DIFFR_Msk _U_(0xFFF) /**< (AFEC_DIFFR) Register Mask */ + +#define AFEC_DIFFR_DIFF_Pos 0 /**< (AFEC_DIFFR Position) Differential inputs for channel xx */ +#define AFEC_DIFFR_DIFF_Msk (_U_(0xFFF) << AFEC_DIFFR_DIFF_Pos) /**< (AFEC_DIFFR Mask) DIFF */ +#define AFEC_DIFFR_DIFF(value) (AFEC_DIFFR_DIFF_Msk & ((value) << AFEC_DIFFR_DIFF_Pos)) + +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) (R/W 32) AFEC Channel Selection Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSEL:4; /**< bit: 0..3 Channel Selection */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CSELR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CSELR_OFFSET (0x64) /**< (AFEC_CSELR) AFEC Channel Selection Register Offset */ + +#define AFEC_CSELR_CSEL_Pos 0 /**< (AFEC_CSELR) Channel Selection Position */ +#define AFEC_CSELR_CSEL_Msk (_U_(0xF) << AFEC_CSELR_CSEL_Pos) /**< (AFEC_CSELR) Channel Selection Mask */ +#define AFEC_CSELR_CSEL(value) (AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)) +#define AFEC_CSELR_MASK _U_(0x0F) /**< \deprecated (AFEC_CSELR) Register MASK (Use AFEC_CSELR_Msk instead) */ +#define AFEC_CSELR_Msk _U_(0x0F) /**< (AFEC_CSELR) Register Mask */ + + +/* -------- AFEC_CDR : (AFEC Offset: 0x68) (R/ 32) AFEC Channel Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA:16; /**< bit: 0..15 Converted Data */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CDR_OFFSET (0x68) /**< (AFEC_CDR) AFEC Channel Data Register Offset */ + +#define AFEC_CDR_DATA_Pos 0 /**< (AFEC_CDR) Converted Data Position */ +#define AFEC_CDR_DATA_Msk (_U_(0xFFFF) << AFEC_CDR_DATA_Pos) /**< (AFEC_CDR) Converted Data Mask */ +#define AFEC_CDR_DATA(value) (AFEC_CDR_DATA_Msk & ((value) << AFEC_CDR_DATA_Pos)) +#define AFEC_CDR_MASK _U_(0xFFFF) /**< \deprecated (AFEC_CDR) Register MASK (Use AFEC_CDR_Msk instead) */ +#define AFEC_CDR_Msk _U_(0xFFFF) /**< (AFEC_CDR) Register Mask */ + + +/* -------- AFEC_COCR : (AFEC Offset: 0x6c) (R/W 32) AFEC Channel Offset Compensation Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t AOFF:10; /**< bit: 0..9 Analog Offset */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_COCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_COCR_OFFSET (0x6C) /**< (AFEC_COCR) AFEC Channel Offset Compensation Register Offset */ + +#define AFEC_COCR_AOFF_Pos 0 /**< (AFEC_COCR) Analog Offset Position */ +#define AFEC_COCR_AOFF_Msk (_U_(0x3FF) << AFEC_COCR_AOFF_Pos) /**< (AFEC_COCR) Analog Offset Mask */ +#define AFEC_COCR_AOFF(value) (AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)) +#define AFEC_COCR_MASK _U_(0x3FF) /**< \deprecated (AFEC_COCR) Register MASK (Use AFEC_COCR_Msk instead) */ +#define AFEC_COCR_Msk _U_(0x3FF) /**< (AFEC_COCR) Register Mask */ + + +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) (R/W 32) AFEC Temperature Sensor Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RTCT:1; /**< bit: 0 Temperature Sensor RTC Trigger Mode */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t TEMPCMPMOD:2; /**< bit: 4..5 Temperature Comparison Mode */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_TEMPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_TEMPMR_OFFSET (0x70) /**< (AFEC_TEMPMR) AFEC Temperature Sensor Mode Register Offset */ + +#define AFEC_TEMPMR_RTCT_Pos 0 /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Position */ +#define AFEC_TEMPMR_RTCT_Msk (_U_(0x1) << AFEC_TEMPMR_RTCT_Pos) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Mask */ +#define AFEC_TEMPMR_RTCT AFEC_TEMPMR_RTCT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_TEMPMR_RTCT_Msk instead */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 /**< (AFEC_TEMPMR) Temperature Comparison Mode Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (_U_(0x3) << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Temperature Comparison Mode Mask */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) (AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW_Val _U_(0x0) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val _U_(0x1) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN_Val _U_(0x2) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT_Val _U_(0x3) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (AFEC_TEMPMR_TEMPCMPMOD_LOW_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (AFEC_TEMPMR_TEMPCMPMOD_IN_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (AFEC_TEMPMR_TEMPCMPMOD_OUT_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_TEMPMR_MASK _U_(0x31) /**< \deprecated (AFEC_TEMPMR) Register MASK (Use AFEC_TEMPMR_Msk instead) */ +#define AFEC_TEMPMR_Msk _U_(0x31) /**< (AFEC_TEMPMR) Register Mask */ + + +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) (R/W 32) AFEC Temperature Compare Window Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TLOWTHRES:16; /**< bit: 0..15 Temperature Low Threshold */ + uint32_t THIGHTHRES:16; /**< bit: 16..31 Temperature High Threshold */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_TEMPCWR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_TEMPCWR_OFFSET (0x74) /**< (AFEC_TEMPCWR) AFEC Temperature Compare Window Register Offset */ + +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 /**< (AFEC_TEMPCWR) Temperature Low Threshold Position */ +#define AFEC_TEMPCWR_TLOWTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature Low Threshold Mask */ +#define AFEC_TEMPCWR_TLOWTHRES(value) (AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 /**< (AFEC_TEMPCWR) Temperature High Threshold Position */ +#define AFEC_TEMPCWR_THIGHTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature High Threshold Mask */ +#define AFEC_TEMPCWR_THIGHTHRES(value) (AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)) +#define AFEC_TEMPCWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_TEMPCWR) Register MASK (Use AFEC_TEMPCWR_Msk instead) */ +#define AFEC_TEMPCWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_TEMPCWR) Register Mask */ + + +/* -------- AFEC_ACR : (AFEC Offset: 0x94) (R/W 32) AFEC Analog Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t PGA0EN:1; /**< bit: 2 PGA0 Enable */ + uint32_t PGA1EN:1; /**< bit: 3 PGA1 Enable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t IBCTL:2; /**< bit: 8..9 AFE Bias Current Control */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_ACR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_ACR_OFFSET (0x94) /**< (AFEC_ACR) AFEC Analog Control Register Offset */ + +#define AFEC_ACR_PGA0EN_Pos 2 /**< (AFEC_ACR) PGA0 Enable Position */ +#define AFEC_ACR_PGA0EN_Msk (_U_(0x1) << AFEC_ACR_PGA0EN_Pos) /**< (AFEC_ACR) PGA0 Enable Mask */ +#define AFEC_ACR_PGA0EN AFEC_ACR_PGA0EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ACR_PGA0EN_Msk instead */ +#define AFEC_ACR_PGA1EN_Pos 3 /**< (AFEC_ACR) PGA1 Enable Position */ +#define AFEC_ACR_PGA1EN_Msk (_U_(0x1) << AFEC_ACR_PGA1EN_Pos) /**< (AFEC_ACR) PGA1 Enable Mask */ +#define AFEC_ACR_PGA1EN AFEC_ACR_PGA1EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ACR_PGA1EN_Msk instead */ +#define AFEC_ACR_IBCTL_Pos 8 /**< (AFEC_ACR) AFE Bias Current Control Position */ +#define AFEC_ACR_IBCTL_Msk (_U_(0x3) << AFEC_ACR_IBCTL_Pos) /**< (AFEC_ACR) AFE Bias Current Control Mask */ +#define AFEC_ACR_IBCTL(value) (AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)) +#define AFEC_ACR_MASK _U_(0x30C) /**< \deprecated (AFEC_ACR) Register MASK (Use AFEC_ACR_Msk instead) */ +#define AFEC_ACR_Msk _U_(0x30C) /**< (AFEC_ACR) Register Mask */ + + +/* -------- AFEC_SHMR : (AFEC Offset: 0xa0) (R/W 32) AFEC Sample & Hold Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DUAL0:1; /**< bit: 0 Dual Sample & Hold for channel 0 */ + uint32_t DUAL1:1; /**< bit: 1 Dual Sample & Hold for channel 1 */ + uint32_t DUAL2:1; /**< bit: 2 Dual Sample & Hold for channel 2 */ + uint32_t DUAL3:1; /**< bit: 3 Dual Sample & Hold for channel 3 */ + uint32_t DUAL4:1; /**< bit: 4 Dual Sample & Hold for channel 4 */ + uint32_t DUAL5:1; /**< bit: 5 Dual Sample & Hold for channel 5 */ + uint32_t DUAL6:1; /**< bit: 6 Dual Sample & Hold for channel 6 */ + uint32_t DUAL7:1; /**< bit: 7 Dual Sample & Hold for channel 7 */ + uint32_t DUAL8:1; /**< bit: 8 Dual Sample & Hold for channel 8 */ + uint32_t DUAL9:1; /**< bit: 9 Dual Sample & Hold for channel 9 */ + uint32_t DUAL10:1; /**< bit: 10 Dual Sample & Hold for channel 10 */ + uint32_t DUAL11:1; /**< bit: 11 Dual Sample & Hold for channel 11 */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t DUAL:12; /**< bit: 0..11 Dual Sample & Hold for channel xx */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_SHMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_SHMR_OFFSET (0xA0) /**< (AFEC_SHMR) AFEC Sample & Hold Mode Register Offset */ + +#define AFEC_SHMR_DUAL0_Pos 0 /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Position */ +#define AFEC_SHMR_DUAL0_Msk (_U_(0x1) << AFEC_SHMR_DUAL0_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Mask */ +#define AFEC_SHMR_DUAL0 AFEC_SHMR_DUAL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL0_Msk instead */ +#define AFEC_SHMR_DUAL1_Pos 1 /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Position */ +#define AFEC_SHMR_DUAL1_Msk (_U_(0x1) << AFEC_SHMR_DUAL1_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Mask */ +#define AFEC_SHMR_DUAL1 AFEC_SHMR_DUAL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL1_Msk instead */ +#define AFEC_SHMR_DUAL2_Pos 2 /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Position */ +#define AFEC_SHMR_DUAL2_Msk (_U_(0x1) << AFEC_SHMR_DUAL2_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Mask */ +#define AFEC_SHMR_DUAL2 AFEC_SHMR_DUAL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL2_Msk instead */ +#define AFEC_SHMR_DUAL3_Pos 3 /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Position */ +#define AFEC_SHMR_DUAL3_Msk (_U_(0x1) << AFEC_SHMR_DUAL3_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Mask */ +#define AFEC_SHMR_DUAL3 AFEC_SHMR_DUAL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL3_Msk instead */ +#define AFEC_SHMR_DUAL4_Pos 4 /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Position */ +#define AFEC_SHMR_DUAL4_Msk (_U_(0x1) << AFEC_SHMR_DUAL4_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Mask */ +#define AFEC_SHMR_DUAL4 AFEC_SHMR_DUAL4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL4_Msk instead */ +#define AFEC_SHMR_DUAL5_Pos 5 /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Position */ +#define AFEC_SHMR_DUAL5_Msk (_U_(0x1) << AFEC_SHMR_DUAL5_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Mask */ +#define AFEC_SHMR_DUAL5 AFEC_SHMR_DUAL5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL5_Msk instead */ +#define AFEC_SHMR_DUAL6_Pos 6 /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Position */ +#define AFEC_SHMR_DUAL6_Msk (_U_(0x1) << AFEC_SHMR_DUAL6_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Mask */ +#define AFEC_SHMR_DUAL6 AFEC_SHMR_DUAL6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL6_Msk instead */ +#define AFEC_SHMR_DUAL7_Pos 7 /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Position */ +#define AFEC_SHMR_DUAL7_Msk (_U_(0x1) << AFEC_SHMR_DUAL7_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Mask */ +#define AFEC_SHMR_DUAL7 AFEC_SHMR_DUAL7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL7_Msk instead */ +#define AFEC_SHMR_DUAL8_Pos 8 /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Position */ +#define AFEC_SHMR_DUAL8_Msk (_U_(0x1) << AFEC_SHMR_DUAL8_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Mask */ +#define AFEC_SHMR_DUAL8 AFEC_SHMR_DUAL8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL8_Msk instead */ +#define AFEC_SHMR_DUAL9_Pos 9 /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Position */ +#define AFEC_SHMR_DUAL9_Msk (_U_(0x1) << AFEC_SHMR_DUAL9_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Mask */ +#define AFEC_SHMR_DUAL9 AFEC_SHMR_DUAL9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL9_Msk instead */ +#define AFEC_SHMR_DUAL10_Pos 10 /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Position */ +#define AFEC_SHMR_DUAL10_Msk (_U_(0x1) << AFEC_SHMR_DUAL10_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Mask */ +#define AFEC_SHMR_DUAL10 AFEC_SHMR_DUAL10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL10_Msk instead */ +#define AFEC_SHMR_DUAL11_Pos 11 /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Position */ +#define AFEC_SHMR_DUAL11_Msk (_U_(0x1) << AFEC_SHMR_DUAL11_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Mask */ +#define AFEC_SHMR_DUAL11 AFEC_SHMR_DUAL11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL11_Msk instead */ +#define AFEC_SHMR_MASK _U_(0xFFF) /**< \deprecated (AFEC_SHMR) Register MASK (Use AFEC_SHMR_Msk instead) */ +#define AFEC_SHMR_Msk _U_(0xFFF) /**< (AFEC_SHMR) Register Mask */ + +#define AFEC_SHMR_DUAL_Pos 0 /**< (AFEC_SHMR Position) Dual Sample & Hold for channel xx */ +#define AFEC_SHMR_DUAL_Msk (_U_(0xFFF) << AFEC_SHMR_DUAL_Pos) /**< (AFEC_SHMR Mask) DUAL */ +#define AFEC_SHMR_DUAL(value) (AFEC_SHMR_DUAL_Msk & ((value) << AFEC_SHMR_DUAL_Pos)) + +/* -------- AFEC_COSR : (AFEC Offset: 0xd0) (R/W 32) AFEC Correction Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSEL:1; /**< bit: 0 Sample & Hold unit Correction Select */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_COSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_COSR_OFFSET (0xD0) /**< (AFEC_COSR) AFEC Correction Select Register Offset */ + +#define AFEC_COSR_CSEL_Pos 0 /**< (AFEC_COSR) Sample & Hold unit Correction Select Position */ +#define AFEC_COSR_CSEL_Msk (_U_(0x1) << AFEC_COSR_CSEL_Pos) /**< (AFEC_COSR) Sample & Hold unit Correction Select Mask */ +#define AFEC_COSR_CSEL AFEC_COSR_CSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_COSR_CSEL_Msk instead */ +#define AFEC_COSR_MASK _U_(0x01) /**< \deprecated (AFEC_COSR) Register MASK (Use AFEC_COSR_Msk instead) */ +#define AFEC_COSR_Msk _U_(0x01) /**< (AFEC_COSR) Register Mask */ + + +/* -------- AFEC_CVR : (AFEC Offset: 0xd4) (R/W 32) AFEC Correction Values Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OFFSETCORR:16; /**< bit: 0..15 Offset Correction */ + uint32_t GAINCORR:16; /**< bit: 16..31 Gain Correction */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CVR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CVR_OFFSET (0xD4) /**< (AFEC_CVR) AFEC Correction Values Register Offset */ + +#define AFEC_CVR_OFFSETCORR_Pos 0 /**< (AFEC_CVR) Offset Correction Position */ +#define AFEC_CVR_OFFSETCORR_Msk (_U_(0xFFFF) << AFEC_CVR_OFFSETCORR_Pos) /**< (AFEC_CVR) Offset Correction Mask */ +#define AFEC_CVR_OFFSETCORR(value) (AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)) +#define AFEC_CVR_GAINCORR_Pos 16 /**< (AFEC_CVR) Gain Correction Position */ +#define AFEC_CVR_GAINCORR_Msk (_U_(0xFFFF) << AFEC_CVR_GAINCORR_Pos) /**< (AFEC_CVR) Gain Correction Mask */ +#define AFEC_CVR_GAINCORR(value) (AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)) +#define AFEC_CVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_CVR) Register MASK (Use AFEC_CVR_Msk instead) */ +#define AFEC_CVR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CVR) Register Mask */ + + +/* -------- AFEC_CECR : (AFEC Offset: 0xd8) (R/W 32) AFEC Channel Error Correction Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ECORR0:1; /**< bit: 0 Error Correction Enable for channel 0 */ + uint32_t ECORR1:1; /**< bit: 1 Error Correction Enable for channel 1 */ + uint32_t ECORR2:1; /**< bit: 2 Error Correction Enable for channel 2 */ + uint32_t ECORR3:1; /**< bit: 3 Error Correction Enable for channel 3 */ + uint32_t ECORR4:1; /**< bit: 4 Error Correction Enable for channel 4 */ + uint32_t ECORR5:1; /**< bit: 5 Error Correction Enable for channel 5 */ + uint32_t ECORR6:1; /**< bit: 6 Error Correction Enable for channel 6 */ + uint32_t ECORR7:1; /**< bit: 7 Error Correction Enable for channel 7 */ + uint32_t ECORR8:1; /**< bit: 8 Error Correction Enable for channel 8 */ + uint32_t ECORR9:1; /**< bit: 9 Error Correction Enable for channel 9 */ + uint32_t ECORR10:1; /**< bit: 10 Error Correction Enable for channel 10 */ + uint32_t ECORR11:1; /**< bit: 11 Error Correction Enable for channel 11 */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ECORR:12; /**< bit: 0..11 Error Correction Enable for channel xx */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_CECR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_CECR_OFFSET (0xD8) /**< (AFEC_CECR) AFEC Channel Error Correction Register Offset */ + +#define AFEC_CECR_ECORR0_Pos 0 /**< (AFEC_CECR) Error Correction Enable for channel 0 Position */ +#define AFEC_CECR_ECORR0_Msk (_U_(0x1) << AFEC_CECR_ECORR0_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 0 Mask */ +#define AFEC_CECR_ECORR0 AFEC_CECR_ECORR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR0_Msk instead */ +#define AFEC_CECR_ECORR1_Pos 1 /**< (AFEC_CECR) Error Correction Enable for channel 1 Position */ +#define AFEC_CECR_ECORR1_Msk (_U_(0x1) << AFEC_CECR_ECORR1_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 1 Mask */ +#define AFEC_CECR_ECORR1 AFEC_CECR_ECORR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR1_Msk instead */ +#define AFEC_CECR_ECORR2_Pos 2 /**< (AFEC_CECR) Error Correction Enable for channel 2 Position */ +#define AFEC_CECR_ECORR2_Msk (_U_(0x1) << AFEC_CECR_ECORR2_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 2 Mask */ +#define AFEC_CECR_ECORR2 AFEC_CECR_ECORR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR2_Msk instead */ +#define AFEC_CECR_ECORR3_Pos 3 /**< (AFEC_CECR) Error Correction Enable for channel 3 Position */ +#define AFEC_CECR_ECORR3_Msk (_U_(0x1) << AFEC_CECR_ECORR3_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 3 Mask */ +#define AFEC_CECR_ECORR3 AFEC_CECR_ECORR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR3_Msk instead */ +#define AFEC_CECR_ECORR4_Pos 4 /**< (AFEC_CECR) Error Correction Enable for channel 4 Position */ +#define AFEC_CECR_ECORR4_Msk (_U_(0x1) << AFEC_CECR_ECORR4_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 4 Mask */ +#define AFEC_CECR_ECORR4 AFEC_CECR_ECORR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR4_Msk instead */ +#define AFEC_CECR_ECORR5_Pos 5 /**< (AFEC_CECR) Error Correction Enable for channel 5 Position */ +#define AFEC_CECR_ECORR5_Msk (_U_(0x1) << AFEC_CECR_ECORR5_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 5 Mask */ +#define AFEC_CECR_ECORR5 AFEC_CECR_ECORR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR5_Msk instead */ +#define AFEC_CECR_ECORR6_Pos 6 /**< (AFEC_CECR) Error Correction Enable for channel 6 Position */ +#define AFEC_CECR_ECORR6_Msk (_U_(0x1) << AFEC_CECR_ECORR6_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 6 Mask */ +#define AFEC_CECR_ECORR6 AFEC_CECR_ECORR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR6_Msk instead */ +#define AFEC_CECR_ECORR7_Pos 7 /**< (AFEC_CECR) Error Correction Enable for channel 7 Position */ +#define AFEC_CECR_ECORR7_Msk (_U_(0x1) << AFEC_CECR_ECORR7_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 7 Mask */ +#define AFEC_CECR_ECORR7 AFEC_CECR_ECORR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR7_Msk instead */ +#define AFEC_CECR_ECORR8_Pos 8 /**< (AFEC_CECR) Error Correction Enable for channel 8 Position */ +#define AFEC_CECR_ECORR8_Msk (_U_(0x1) << AFEC_CECR_ECORR8_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 8 Mask */ +#define AFEC_CECR_ECORR8 AFEC_CECR_ECORR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR8_Msk instead */ +#define AFEC_CECR_ECORR9_Pos 9 /**< (AFEC_CECR) Error Correction Enable for channel 9 Position */ +#define AFEC_CECR_ECORR9_Msk (_U_(0x1) << AFEC_CECR_ECORR9_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 9 Mask */ +#define AFEC_CECR_ECORR9 AFEC_CECR_ECORR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR9_Msk instead */ +#define AFEC_CECR_ECORR10_Pos 10 /**< (AFEC_CECR) Error Correction Enable for channel 10 Position */ +#define AFEC_CECR_ECORR10_Msk (_U_(0x1) << AFEC_CECR_ECORR10_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 10 Mask */ +#define AFEC_CECR_ECORR10 AFEC_CECR_ECORR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR10_Msk instead */ +#define AFEC_CECR_ECORR11_Pos 11 /**< (AFEC_CECR) Error Correction Enable for channel 11 Position */ +#define AFEC_CECR_ECORR11_Msk (_U_(0x1) << AFEC_CECR_ECORR11_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 11 Mask */ +#define AFEC_CECR_ECORR11 AFEC_CECR_ECORR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR11_Msk instead */ +#define AFEC_CECR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CECR) Register MASK (Use AFEC_CECR_Msk instead) */ +#define AFEC_CECR_Msk _U_(0xFFF) /**< (AFEC_CECR) Register Mask */ + +#define AFEC_CECR_ECORR_Pos 0 /**< (AFEC_CECR Position) Error Correction Enable for channel xx */ +#define AFEC_CECR_ECORR_Msk (_U_(0xFFF) << AFEC_CECR_ECORR_Pos) /**< (AFEC_CECR Mask) ECORR */ +#define AFEC_CECR_ECORR(value) (AFEC_CECR_ECORR_Msk & ((value) << AFEC_CECR_ECORR_Pos)) + +/* -------- AFEC_WPMR : (AFEC Offset: 0xe4) (R/W 32) AFEC Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protect KEY */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_WPMR_OFFSET (0xE4) /**< (AFEC_WPMR) AFEC Write Protection Mode Register Offset */ + +#define AFEC_WPMR_WPEN_Pos 0 /**< (AFEC_WPMR) Write Protection Enable Position */ +#define AFEC_WPMR_WPEN_Msk (_U_(0x1) << AFEC_WPMR_WPEN_Pos) /**< (AFEC_WPMR) Write Protection Enable Mask */ +#define AFEC_WPMR_WPEN AFEC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_WPMR_WPEN_Msk instead */ +#define AFEC_WPMR_WPKEY_Pos 8 /**< (AFEC_WPMR) Write Protect KEY Position */ +#define AFEC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Write Protect KEY Mask */ +#define AFEC_WPMR_WPKEY(value) (AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)) +#define AFEC_WPMR_WPKEY_PASSWD_Val _U_(0x414443) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define AFEC_WPMR_WPKEY_PASSWD (AFEC_WPMR_WPKEY_PASSWD_Val << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define AFEC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (AFEC_WPMR) Register MASK (Use AFEC_WPMR_Msk instead) */ +#define AFEC_WPMR_Msk _U_(0xFFFFFF01) /**< (AFEC_WPMR) Register Mask */ + + +/* -------- AFEC_WPSR : (AFEC Offset: 0xe8) (R/ 32) AFEC Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protect Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protect Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} AFEC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AFEC_WPSR_OFFSET (0xE8) /**< (AFEC_WPSR) AFEC Write Protection Status Register Offset */ + +#define AFEC_WPSR_WPVS_Pos 0 /**< (AFEC_WPSR) Write Protect Violation Status Position */ +#define AFEC_WPSR_WPVS_Msk (_U_(0x1) << AFEC_WPSR_WPVS_Pos) /**< (AFEC_WPSR) Write Protect Violation Status Mask */ +#define AFEC_WPSR_WPVS AFEC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_WPSR_WPVS_Msk instead */ +#define AFEC_WPSR_WPVSRC_Pos 8 /**< (AFEC_WPSR) Write Protect Violation Source Position */ +#define AFEC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << AFEC_WPSR_WPVSRC_Pos) /**< (AFEC_WPSR) Write Protect Violation Source Mask */ +#define AFEC_WPSR_WPVSRC(value) (AFEC_WPSR_WPVSRC_Msk & ((value) << AFEC_WPSR_WPVSRC_Pos)) +#define AFEC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (AFEC_WPSR) Register MASK (Use AFEC_WPSR_Msk instead) */ +#define AFEC_WPSR_Msk _U_(0xFFFF01) /**< (AFEC_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief AFEC hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< (AFEC Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< (AFEC Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< (AFEC Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< (AFEC Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< (AFEC Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< (AFEC Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< (AFEC Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< (AFEC Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< (AFEC Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< (AFEC Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< (AFEC Offset: 0x30) AFEC Interrupt Status Register */ + __I uint8_t Reserved1[24]; + __I uint32_t AFEC_OVER; /**< (AFEC Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< (AFEC Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< (AFEC Offset: 0x54) AFEC Channel Gain Register */ + __I uint8_t Reserved2[8]; + __IO uint32_t AFEC_DIFFR; /**< (AFEC Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< (AFEC Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< (AFEC Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< (AFEC Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint8_t Reserved3[28]; + __IO uint32_t AFEC_ACR; /**< (AFEC Offset: 0x94) AFEC Analog Control Register */ + __I uint8_t Reserved4[8]; + __IO uint32_t AFEC_SHMR; /**< (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint8_t Reserved5[44]; + __IO uint32_t AFEC_COSR; /**< (AFEC Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< (AFEC Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< (AFEC Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint8_t Reserved6[8]; + __IO uint32_t AFEC_WPMR; /**< (AFEC Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< (AFEC Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief AFEC hardware registers */ +typedef struct { + __O AFEC_CR_Type AFEC_CR; /**< Offset: 0x00 ( /W 32) AFEC Control Register */ + __IO AFEC_MR_Type AFEC_MR; /**< Offset: 0x04 (R/W 32) AFEC Mode Register */ + __IO AFEC_EMR_Type AFEC_EMR; /**< Offset: 0x08 (R/W 32) AFEC Extended Mode Register */ + __IO AFEC_SEQ1R_Type AFEC_SEQ1R; /**< Offset: 0x0C (R/W 32) AFEC Channel Sequence 1 Register */ + __IO AFEC_SEQ2R_Type AFEC_SEQ2R; /**< Offset: 0x10 (R/W 32) AFEC Channel Sequence 2 Register */ + __O AFEC_CHER_Type AFEC_CHER; /**< Offset: 0x14 ( /W 32) AFEC Channel Enable Register */ + __O AFEC_CHDR_Type AFEC_CHDR; /**< Offset: 0x18 ( /W 32) AFEC Channel Disable Register */ + __I AFEC_CHSR_Type AFEC_CHSR; /**< Offset: 0x1C (R/ 32) AFEC Channel Status Register */ + __I AFEC_LCDR_Type AFEC_LCDR; /**< Offset: 0x20 (R/ 32) AFEC Last Converted Data Register */ + __O AFEC_IER_Type AFEC_IER; /**< Offset: 0x24 ( /W 32) AFEC Interrupt Enable Register */ + __O AFEC_IDR_Type AFEC_IDR; /**< Offset: 0x28 ( /W 32) AFEC Interrupt Disable Register */ + __I AFEC_IMR_Type AFEC_IMR; /**< Offset: 0x2C (R/ 32) AFEC Interrupt Mask Register */ + __I AFEC_ISR_Type AFEC_ISR; /**< Offset: 0x30 (R/ 32) AFEC Interrupt Status Register */ + __I uint8_t Reserved1[24]; + __I AFEC_OVER_Type AFEC_OVER; /**< Offset: 0x4C (R/ 32) AFEC Overrun Status Register */ + __IO AFEC_CWR_Type AFEC_CWR; /**< Offset: 0x50 (R/W 32) AFEC Compare Window Register */ + __IO AFEC_CGR_Type AFEC_CGR; /**< Offset: 0x54 (R/W 32) AFEC Channel Gain Register */ + __I uint8_t Reserved2[8]; + __IO AFEC_DIFFR_Type AFEC_DIFFR; /**< Offset: 0x60 (R/W 32) AFEC Channel Differential Register */ + __IO AFEC_CSELR_Type AFEC_CSELR; /**< Offset: 0x64 (R/W 32) AFEC Channel Selection Register */ + __I AFEC_CDR_Type AFEC_CDR; /**< Offset: 0x68 (R/ 32) AFEC Channel Data Register */ + __IO AFEC_COCR_Type AFEC_COCR; /**< Offset: 0x6C (R/W 32) AFEC Channel Offset Compensation Register */ + __IO AFEC_TEMPMR_Type AFEC_TEMPMR; /**< Offset: 0x70 (R/W 32) AFEC Temperature Sensor Mode Register */ + __IO AFEC_TEMPCWR_Type AFEC_TEMPCWR; /**< Offset: 0x74 (R/W 32) AFEC Temperature Compare Window Register */ + __I uint8_t Reserved3[28]; + __IO AFEC_ACR_Type AFEC_ACR; /**< Offset: 0x94 (R/W 32) AFEC Analog Control Register */ + __I uint8_t Reserved4[8]; + __IO AFEC_SHMR_Type AFEC_SHMR; /**< Offset: 0xA0 (R/W 32) AFEC Sample & Hold Mode Register */ + __I uint8_t Reserved5[44]; + __IO AFEC_COSR_Type AFEC_COSR; /**< Offset: 0xD0 (R/W 32) AFEC Correction Select Register */ + __IO AFEC_CVR_Type AFEC_CVR; /**< Offset: 0xD4 (R/W 32) AFEC Correction Values Register */ + __IO AFEC_CECR_Type AFEC_CECR; /**< Offset: 0xD8 (R/W 32) AFEC Channel Error Correction Register */ + __I uint8_t Reserved6[8]; + __IO AFEC_WPMR_Type AFEC_WPMR; /**< Offset: 0xE4 (R/W 32) AFEC Write Protection Mode Register */ + __I AFEC_WPSR_Type AFEC_WPSR; /**< Offset: 0xE8 (R/ 32) AFEC Write Protection Status Register */ +} Afec; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Analog Front-End Controller */ + +#endif /* _SAME70_AFEC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/chipid.h b/bsp/microchip/same70/bsp/same70b/include/component/chipid.h new file mode 100644 index 0000000000..52cdeed985 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/chipid.h @@ -0,0 +1,248 @@ +/** + * \file + * + * \brief Component description for CHIPID + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_CHIPID_COMPONENT_H_ +#define _SAME70_CHIPID_COMPONENT_H_ +#define _SAME70_CHIPID_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Chip Identifier + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CHIPID */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define CHIPID_6417 /**< (CHIPID) Module ID */ +#define REV_CHIPID ZK /**< (CHIPID) Module revision */ + +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) (R/ 32) Chip ID Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t VERSION:5; /**< bit: 0..4 Version of the Device */ + uint32_t EPROC:3; /**< bit: 5..7 Embedded Processor */ + uint32_t NVPSIZ:4; /**< bit: 8..11 Nonvolatile Program Memory Size */ + uint32_t NVPSIZ2:4; /**< bit: 12..15 Second Nonvolatile Program Memory Size */ + uint32_t SRAMSIZ:4; /**< bit: 16..19 Internal SRAM Size */ + uint32_t ARCH:8; /**< bit: 20..27 Architecture Identifier */ + uint32_t NVPTYP:3; /**< bit: 28..30 Nonvolatile Program Memory Type */ + uint32_t EXT:1; /**< bit: 31 Extension Flag */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CHIPID_CIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CHIPID_CIDR_OFFSET (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */ + +#define CHIPID_CIDR_VERSION_Pos 0 /**< (CHIPID_CIDR) Version of the Device Position */ +#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */ +#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos)) +#define CHIPID_CIDR_EPROC_Pos 5 /**< (CHIPID_CIDR) Embedded Processor Position */ +#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */ +#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos)) +#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */ +#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */ +#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */ +#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */ +#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */ +#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */ +#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos)) +#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos)) +#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 /**< (CHIPID_CIDR) Internal SRAM Size Position */ +#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */ +#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos)) +#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_ARCH_Pos 20 /**< (CHIPID_CIDR) Architecture Identifier Position */ +#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */ +#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos)) +#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */ +#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */ +#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */ +#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */ +#define CHIPID_CIDR_NVPTYP_Pos 28 /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */ +#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */ +#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos)) +#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */ +#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */ +#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */ +#define CHIPID_CIDR_EXT_Pos 31 /**< (CHIPID_CIDR) Extension Flag Position */ +#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */ +#define CHIPID_CIDR_EXT CHIPID_CIDR_EXT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CHIPID_CIDR_EXT_Msk instead */ +#define CHIPID_CIDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_CIDR) Register MASK (Use CHIPID_CIDR_Msk instead) */ +#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */ + + +/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) (R/ 32) Chip ID Extension Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EXID:32; /**< bit: 0..31 Chip ID Extension */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CHIPID_EXID_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CHIPID_EXID_OFFSET (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */ + +#define CHIPID_EXID_EXID_Pos 0 /**< (CHIPID_EXID) Chip ID Extension Position */ +#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */ +#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos)) +#define CHIPID_EXID_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_EXID) Register MASK (Use CHIPID_EXID_Msk instead) */ +#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief CHIPID hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< (CHIPID Offset: 0x00) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< (CHIPID Offset: 0x04) Chip ID Extension Register */ +} Chipid; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief CHIPID hardware registers */ +typedef struct { + __I CHIPID_CIDR_Type CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */ + __I CHIPID_EXID_Type CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */ +} Chipid; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Chip Identifier */ + +#endif /* _SAME70_CHIPID_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/dacc.h b/bsp/microchip/same70/bsp/same70b/include/component/dacc.h new file mode 100644 index 0000000000..336f7bcc80 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/dacc.h @@ -0,0 +1,713 @@ +/** + * \file + * + * \brief Component description for DACC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_DACC_COMPONENT_H_ +#define _SAME70_DACC_COMPONENT_H_ +#define _SAME70_DACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Digital-to-Analog Converter Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DACC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define DACC_11246 /**< (DACC) Module ID */ +#define REV_DACC E /**< (DACC) Module revision */ + +/* -------- DACC_CR : (DACC Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWRST:1; /**< bit: 0 Software Reset */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} DACC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_CR_OFFSET (0x00) /**< (DACC_CR) Control Register Offset */ + +#define DACC_CR_SWRST_Pos 0 /**< (DACC_CR) Software Reset Position */ +#define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */ +#define DACC_CR_SWRST DACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CR_SWRST_Msk instead */ +#define DACC_CR_MASK _U_(0x01) /**< \deprecated (DACC_CR) Register MASK (Use DACC_CR_Msk instead) */ +#define DACC_CR_Msk _U_(0x01) /**< (DACC_CR) Register Mask */ + + +/* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MAXS0:1; /**< bit: 0 Max Speed Mode for Channel 0 */ + uint32_t MAXS1:1; /**< bit: 1 Max Speed Mode for Channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t WORD:1; /**< bit: 4 Word Transfer Mode */ + uint32_t ZERO:1; /**< bit: 5 Must always be written to 0. */ + uint32_t :17; /**< bit: 6..22 Reserved */ + uint32_t DIFF:1; /**< bit: 23 Differential Mode */ + uint32_t PRESCALER:4; /**< bit: 24..27 Peripheral Clock to DAC Clock Ratio */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t MAXS:2; /**< bit: 0..1 Max Speed Mode for Channel x */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_MR_OFFSET (0x04) /**< (DACC_MR) Mode Register Offset */ + +#define DACC_MR_MAXS0_Pos 0 /**< (DACC_MR) Max Speed Mode for Channel 0 Position */ +#define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */ +#define DACC_MR_MAXS0 DACC_MR_MAXS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS0_Msk instead */ +#define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_MAXS1_Pos 1 /**< (DACC_MR) Max Speed Mode for Channel 1 Position */ +#define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */ +#define DACC_MR_MAXS1 DACC_MR_MAXS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_MAXS1_Msk instead */ +#define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_WORD_Pos 4 /**< (DACC_MR) Word Transfer Mode Position */ +#define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */ +#define DACC_MR_WORD DACC_MR_WORD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_WORD_Msk instead */ +#define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */ +#define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */ +#define DACC_MR_ZERO_Pos 5 /**< (DACC_MR) Must always be written to 0. Position */ +#define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */ +#define DACC_MR_ZERO DACC_MR_ZERO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_ZERO_Msk instead */ +#define DACC_MR_DIFF_Pos 23 /**< (DACC_MR) Differential Mode Position */ +#define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */ +#define DACC_MR_DIFF DACC_MR_DIFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_MR_DIFF_Msk instead */ +#define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */ +#define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */ +#define DACC_MR_PRESCALER_Pos 24 /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */ +#define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */ +#define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)) +#define DACC_MR_MASK _U_(0xF800033) /**< \deprecated (DACC_MR) Register MASK (Use DACC_MR_Msk instead) */ +#define DACC_MR_Msk _U_(0xF800033) /**< (DACC_MR) Register Mask */ + +#define DACC_MR_MAXS_Pos 0 /**< (DACC_MR Position) Max Speed Mode for Channel x */ +#define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */ +#define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos)) + +/* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TRGEN0:1; /**< bit: 0 Trigger Enable of Channel 0 */ + uint32_t TRGEN1:1; /**< bit: 1 Trigger Enable of Channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t TRGSEL0:3; /**< bit: 4..6 Trigger Selection of Channel 0 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t TRGSEL1:3; /**< bit: 8..10 Trigger Selection of Channel 1 */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t OSR0:3; /**< bit: 16..18 Over Sampling Ratio of Channel 0 */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t OSR1:3; /**< bit: 20..22 Over Sampling Ratio of Channel 1 */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TRGEN:2; /**< bit: 0..1 Trigger Enable of Channel x */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_TRIGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_TRIGR_OFFSET (0x08) /**< (DACC_TRIGR) Trigger Register Offset */ + +#define DACC_TRIGR_TRGEN0_Pos 0 /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */ +#define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */ +#define DACC_TRIGR_TRGEN0 DACC_TRIGR_TRGEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN0_Msk instead */ +#define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGEN1_Pos 1 /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */ +#define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */ +#define DACC_TRIGR_TRGEN1 DACC_TRIGR_TRGEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_TRIGR_TRGEN1_Msk instead */ +#define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGSEL0_Pos 4 /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */ +#define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */ +#define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)) +#define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 Event Line 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 Event Line 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 Event Line 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 Event Line 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL1_Pos 8 /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */ +#define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */ +#define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)) +#define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 Event Line 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 Event Line 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 Event Line 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 Event Line 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 Event Line 1 Position */ +#define DACC_TRIGR_OSR0_Pos 16 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */ +#define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */ +#define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)) +#define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_OSR1_Pos 20 /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */ +#define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */ +#define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)) +#define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_MASK _U_(0x770773) /**< \deprecated (DACC_TRIGR) Register MASK (Use DACC_TRIGR_Msk instead) */ +#define DACC_TRIGR_Msk _U_(0x770773) /**< (DACC_TRIGR) Register Mask */ + +#define DACC_TRIGR_TRGEN_Pos 0 /**< (DACC_TRIGR Position) Trigger Enable of Channel x */ +#define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */ +#define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos)) + +/* -------- DACC_CHER : (DACC Offset: 0x10) (/W 32) Channel Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Enable */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Enable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:2; /**< bit: 0..1 Channel x Enable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_CHER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_CHER_OFFSET (0x10) /**< (DACC_CHER) Channel Enable Register Offset */ + +#define DACC_CHER_CH0_Pos 0 /**< (DACC_CHER) Channel 0 Enable Position */ +#define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */ +#define DACC_CHER_CH0 DACC_CHER_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH0_Msk instead */ +#define DACC_CHER_CH1_Pos 1 /**< (DACC_CHER) Channel 1 Enable Position */ +#define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */ +#define DACC_CHER_CH1 DACC_CHER_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHER_CH1_Msk instead */ +#define DACC_CHER_MASK _U_(0x03) /**< \deprecated (DACC_CHER) Register MASK (Use DACC_CHER_Msk instead) */ +#define DACC_CHER_Msk _U_(0x03) /**< (DACC_CHER) Register Mask */ + +#define DACC_CHER_CH_Pos 0 /**< (DACC_CHER Position) Channel x Enable */ +#define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */ +#define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos)) + +/* -------- DACC_CHDR : (DACC Offset: 0x14) (/W 32) Channel Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Disable */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Disable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:2; /**< bit: 0..1 Channel x Disable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_CHDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_CHDR_OFFSET (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */ + +#define DACC_CHDR_CH0_Pos 0 /**< (DACC_CHDR) Channel 0 Disable Position */ +#define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */ +#define DACC_CHDR_CH0 DACC_CHDR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH0_Msk instead */ +#define DACC_CHDR_CH1_Pos 1 /**< (DACC_CHDR) Channel 1 Disable Position */ +#define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */ +#define DACC_CHDR_CH1 DACC_CHDR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHDR_CH1_Msk instead */ +#define DACC_CHDR_MASK _U_(0x03) /**< \deprecated (DACC_CHDR) Register MASK (Use DACC_CHDR_Msk instead) */ +#define DACC_CHDR_Msk _U_(0x03) /**< (DACC_CHDR) Register Mask */ + +#define DACC_CHDR_CH_Pos 0 /**< (DACC_CHDR Position) Channel x Disable */ +#define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */ +#define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos)) + +/* -------- DACC_CHSR : (DACC Offset: 0x18) (R/ 32) Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CH0:1; /**< bit: 0 Channel 0 Status */ + uint32_t CH1:1; /**< bit: 1 Channel 1 Status */ + uint32_t :6; /**< bit: 2..7 Reserved */ + uint32_t DACRDY0:1; /**< bit: 8 DAC Ready Flag */ + uint32_t DACRDY1:1; /**< bit: 9 DAC Ready Flag */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CH:2; /**< bit: 0..1 Channel x Status */ + uint32_t :6; /**< bit: 2..7 Reserved */ + uint32_t DACRDY:2; /**< bit: 8..9 DAC Ready Flag */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_CHSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_CHSR_OFFSET (0x18) /**< (DACC_CHSR) Channel Status Register Offset */ + +#define DACC_CHSR_CH0_Pos 0 /**< (DACC_CHSR) Channel 0 Status Position */ +#define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */ +#define DACC_CHSR_CH0 DACC_CHSR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH0_Msk instead */ +#define DACC_CHSR_CH1_Pos 1 /**< (DACC_CHSR) Channel 1 Status Position */ +#define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */ +#define DACC_CHSR_CH1 DACC_CHSR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_CH1_Msk instead */ +#define DACC_CHSR_DACRDY0_Pos 8 /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY0 DACC_CHSR_DACRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY0_Msk instead */ +#define DACC_CHSR_DACRDY1_Pos 9 /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY1 DACC_CHSR_DACRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_CHSR_DACRDY1_Msk instead */ +#define DACC_CHSR_MASK _U_(0x303) /**< \deprecated (DACC_CHSR) Register MASK (Use DACC_CHSR_Msk instead) */ +#define DACC_CHSR_Msk _U_(0x303) /**< (DACC_CHSR) Register Mask */ + +#define DACC_CHSR_CH_Pos 0 /**< (DACC_CHSR Position) Channel x Status */ +#define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */ +#define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos)) +#define DACC_CHSR_DACRDY_Pos 8 /**< (DACC_CHSR Position) DAC Ready Flag */ +#define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */ +#define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos)) + +/* -------- DACC_CDR : (DACC Offset: 0x1c) (/W 32) Conversion Data Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA0:16; /**< bit: 0..15 Data to Convert for channel 0 */ + uint32_t DATA1:16; /**< bit: 16..31 Data to Convert for channel 1 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} DACC_CDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_CDR_OFFSET (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */ + +#define DACC_CDR_DATA0_Pos 0 /**< (DACC_CDR) Data to Convert for channel 0 Position */ +#define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */ +#define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)) +#define DACC_CDR_DATA1_Pos 16 /**< (DACC_CDR) Data to Convert for channel 1 Position */ +#define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */ +#define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)) +#define DACC_CDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (DACC_CDR) Register MASK (Use DACC_CDR_Msk instead) */ +#define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */ + + +/* -------- DACC_IER : (DACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Enable of channel 0 */ + uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Enable of channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Enable of channel 0 */ + uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Enable of channel 1 */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Enable of channel x */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Enable of channel x */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_IER_OFFSET (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */ + +#define DACC_IER_TXRDY0_Pos 0 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */ +#define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */ +#define DACC_IER_TXRDY0 DACC_IER_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY0_Msk instead */ +#define DACC_IER_TXRDY1_Pos 1 /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */ +#define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */ +#define DACC_IER_TXRDY1 DACC_IER_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_TXRDY1_Msk instead */ +#define DACC_IER_EOC0_Pos 4 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */ +#define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */ +#define DACC_IER_EOC0 DACC_IER_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC0_Msk instead */ +#define DACC_IER_EOC1_Pos 5 /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */ +#define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */ +#define DACC_IER_EOC1 DACC_IER_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IER_EOC1_Msk instead */ +#define DACC_IER_MASK _U_(0x33) /**< \deprecated (DACC_IER) Register MASK (Use DACC_IER_Msk instead) */ +#define DACC_IER_Msk _U_(0x33) /**< (DACC_IER) Register Mask */ + +#define DACC_IER_TXRDY_Pos 0 /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */ +#define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */ +#define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos)) +#define DACC_IER_EOC_Pos 4 /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */ +#define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */ +#define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos)) + +/* -------- DACC_IDR : (DACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Disable of channel 0 */ + uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Disable of channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Disable of channel 0 */ + uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Disable of channel 1 */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Disable of channel x */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Disable of channel x */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_IDR_OFFSET (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */ + +#define DACC_IDR_TXRDY0_Pos 0 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */ +#define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_TXRDY0 DACC_IDR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY0_Msk instead */ +#define DACC_IDR_TXRDY1_Pos 1 /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */ +#define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_TXRDY1 DACC_IDR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_TXRDY1_Msk instead */ +#define DACC_IDR_EOC0_Pos 4 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */ +#define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_EOC0 DACC_IDR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC0_Msk instead */ +#define DACC_IDR_EOC1_Pos 5 /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */ +#define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_EOC1 DACC_IDR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IDR_EOC1_Msk instead */ +#define DACC_IDR_MASK _U_(0x33) /**< \deprecated (DACC_IDR) Register MASK (Use DACC_IDR_Msk instead) */ +#define DACC_IDR_Msk _U_(0x33) /**< (DACC_IDR) Register Mask */ + +#define DACC_IDR_TXRDY_Pos 0 /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */ +#define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */ +#define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos)) +#define DACC_IDR_EOC_Pos 4 /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */ +#define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */ +#define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos)) + +/* -------- DACC_IMR : (DACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Mask of channel 0 */ + uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Mask of channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Mask of channel 0 */ + uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Mask of channel 1 */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Mask of channel x */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Mask of channel x */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_IMR_OFFSET (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */ + +#define DACC_IMR_TXRDY0_Pos 0 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */ +#define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_TXRDY0 DACC_IMR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY0_Msk instead */ +#define DACC_IMR_TXRDY1_Pos 1 /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */ +#define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_TXRDY1 DACC_IMR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_TXRDY1_Msk instead */ +#define DACC_IMR_EOC0_Pos 4 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */ +#define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_EOC0 DACC_IMR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC0_Msk instead */ +#define DACC_IMR_EOC1_Pos 5 /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */ +#define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_EOC1 DACC_IMR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_IMR_EOC1_Msk instead */ +#define DACC_IMR_MASK _U_(0x33) /**< \deprecated (DACC_IMR) Register MASK (Use DACC_IMR_Msk instead) */ +#define DACC_IMR_Msk _U_(0x33) /**< (DACC_IMR) Register Mask */ + +#define DACC_IMR_TXRDY_Pos 0 /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */ +#define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */ +#define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos)) +#define DACC_IMR_EOC_Pos 4 /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */ +#define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */ +#define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos)) + +/* -------- DACC_ISR : (DACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY0:1; /**< bit: 0 Transmit Ready Interrupt Flag of channel 0 */ + uint32_t TXRDY1:1; /**< bit: 1 Transmit Ready Interrupt Flag of channel 1 */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC0:1; /**< bit: 4 End of Conversion Interrupt Flag of channel 0 */ + uint32_t EOC1:1; /**< bit: 5 End of Conversion Interrupt Flag of channel 1 */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TXRDY:2; /**< bit: 0..1 Transmit Ready Interrupt Flag of channel x */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EOC:2; /**< bit: 4..5 End of Conversion Interrupt Flag of channel x */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} DACC_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_ISR_OFFSET (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */ + +#define DACC_ISR_TXRDY0_Pos 0 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */ +#define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_TXRDY0 DACC_ISR_TXRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY0_Msk instead */ +#define DACC_ISR_TXRDY1_Pos 1 /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */ +#define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_TXRDY1 DACC_ISR_TXRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_TXRDY1_Msk instead */ +#define DACC_ISR_EOC0_Pos 4 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */ +#define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_EOC0 DACC_ISR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC0_Msk instead */ +#define DACC_ISR_EOC1_Pos 5 /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */ +#define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_EOC1 DACC_ISR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_ISR_EOC1_Msk instead */ +#define DACC_ISR_MASK _U_(0x33) /**< \deprecated (DACC_ISR) Register MASK (Use DACC_ISR_Msk instead) */ +#define DACC_ISR_Msk _U_(0x33) /**< (DACC_ISR) Register Mask */ + +#define DACC_ISR_TXRDY_Pos 0 /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */ +#define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */ +#define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos)) +#define DACC_ISR_EOC_Pos 4 /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */ +#define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */ +#define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos)) + +/* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IBCTLCH0:2; /**< bit: 0..1 Analog Output Current Control */ + uint32_t IBCTLCH1:2; /**< bit: 2..3 Analog Output Current Control */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} DACC_ACR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_ACR_OFFSET (0x94) /**< (DACC_ACR) Analog Current Register Offset */ + +#define DACC_ACR_IBCTLCH0_Pos 0 /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)) +#define DACC_ACR_IBCTLCH1_Pos 2 /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)) +#define DACC_ACR_MASK _U_(0x0F) /**< \deprecated (DACC_ACR) Register MASK (Use DACC_ACR_Msk instead) */ +#define DACC_ACR_Msk _U_(0x0F) /**< (DACC_ACR) Register Mask */ + + +/* -------- DACC_WPMR : (DACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protect Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} DACC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_WPMR_OFFSET (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */ + +#define DACC_WPMR_WPEN_Pos 0 /**< (DACC_WPMR) Write Protection Enable Position */ +#define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */ +#define DACC_WPMR_WPEN DACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPMR_WPEN_Msk instead */ +#define DACC_WPMR_WPKEY_Pos 8 /**< (DACC_WPMR) Write Protect Key Position */ +#define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */ +#define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)) +#define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +#define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */ +#define DACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (DACC_WPMR) Register MASK (Use DACC_WPMR_Msk instead) */ +#define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */ + + +/* -------- DACC_WPSR : (DACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} DACC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DACC_WPSR_OFFSET (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */ + +#define DACC_WPSR_WPVS_Pos 0 /**< (DACC_WPSR) Write Protection Violation Status Position */ +#define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */ +#define DACC_WPSR_WPVS DACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use DACC_WPSR_WPVS_Msk instead */ +#define DACC_WPSR_WPVSRC_Pos 8 /**< (DACC_WPSR) Write Protection Violation Source Position */ +#define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */ +#define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos)) +#define DACC_WPSR_MASK _U_(0xFF01) /**< \deprecated (DACC_WPSR) Register MASK (Use DACC_WPSR_Msk instead) */ +#define DACC_WPSR_Msk _U_(0xFF01) /**< (DACC_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief DACC hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< (DACC Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< (DACC Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< (DACC Offset: 0x08) Trigger Register */ + __I uint8_t Reserved1[4]; + __O uint32_t DACC_CHER; /**< (DACC Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< (DACC Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< (DACC Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< (DACC Offset: 0x1C) Conversion Data Register 0 */ + __O uint32_t DACC_IER; /**< (DACC Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< (DACC Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< (DACC Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< (DACC Offset: 0x30) Interrupt Status Register */ + __I uint8_t Reserved2[96]; + __IO uint32_t DACC_ACR; /**< (DACC Offset: 0x94) Analog Current Register */ + __I uint8_t Reserved3[76]; + __IO uint32_t DACC_WPMR; /**< (DACC Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< (DACC Offset: 0xE8) Write Protection Status Register */ +} Dacc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief DACC hardware registers */ +typedef struct { + __O DACC_CR_Type DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO DACC_MR_Type DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO DACC_TRIGR_Type DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */ + __I uint8_t Reserved1[4]; + __O DACC_CHER_Type DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */ + __O DACC_CHDR_Type DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */ + __I DACC_CHSR_Type DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */ + __O DACC_CDR_Type DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */ + __O DACC_IER_Type DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O DACC_IDR_Type DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I DACC_IMR_Type DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I DACC_ISR_Type DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[96]; + __IO DACC_ACR_Type DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */ + __I uint8_t Reserved3[76]; + __IO DACC_WPMR_Type DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I DACC_WPSR_Type DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Dacc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Digital-to-Analog Converter Controller */ + +#endif /* _SAME70_DACC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/deprecated/tc.h b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/tc.h new file mode 100644 index 0000000000..8e781ccdba --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/tc.h @@ -0,0 +1,63 @@ +/** + * \file + * \brief This file is for deprecated macro constants + * + * Used to mark macro constants as deprecate. + * Uses a macro 'DEPRECTAED' to give warnings during compilation (GCC >= 4.8) + * + * \remark To use, add defines and put a DEPRECATED statement between the macro name and the value + * + * \note This file is manually maintained + */ + +#ifndef _SAME70_TC_COMPONENT_DEPRECATED_H_ +#define _SAME70_TC_COMPONENT_DEPRECATED_H_ + +#ifndef DEPRECATED +#define _DEP_STRING(X) #X + +/** \hideinitializer + * \brief Macro deprecation mark + * + * Putting this in a macro definition will emit deprecation warning when given + * macro is used (GCC 4.8) + * + * \code{.c} + * #define OLD_MACRO DEPRECATED(OLD_MACRO, "deprecated ") + * \endcode + * + * \warning Using these macros in #if statements will not work + */ +#if defined(__GNUC__) && __GNUC__*100 + __GNUC_MINOR__ >= 408 +#define DEPRECATED(macro, message) _Pragma (_DEP_STRING(GCC warning message)) +#else +#define DEPRECATED(macro, message) +#endif +#endif + +/* deprecated defines added below here */ +#define TC_CMR_ABETRG_Msk DEPRECATED(TC_CMR_ABETRG_Msk, "Using deprecated macro TC_CMR_ABETRG_Msk") (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ +#define TC_CMR_ABETRG_Pos DEPRECATED(TC_CMR_ABETRG_Pos, "Using deprecated macro TC_CMR_ABETRG_Pos") 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ +#define TC_CMR_ABETRG DEPRECATED(TC_CMR_ABETRG, "Using deprecated macro TC_CMR_ABETRG") TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */ +#define TC_CMR_CPCTRG_Msk DEPRECATED(TC_CMR_CPCTRG_Msk, "Using deprecated macro TC_CMR_CPCTRG_Msk") (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ +#define TC_CMR_CPCTRG_Pos DEPRECATED(TC_CMR_CPCTRG_Pos, "Using deprecated macro TC_CMR_CPCTRG_Pos") 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ +#define TC_CMR_CPCTRG DEPRECATED(TC_CMR_CPCTRG, "Using deprecated macro TC_CMR_CPCTRG") TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */ +#define TC_CMR_ETRGEDG_Msk DEPRECATED(TC_CMR_ETRGEDG_Msk, "Using deprecated macro TC_CMR_ETRGEDG_Msk") (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ +#define TC_CMR_ETRGEDG_Pos DEPRECATED(TC_CMR_ETRGEDG_Pos, "Using deprecated macro TC_CMR_ETRGEDG_Pos") 8 /**< (TC_CMR) External Trigger Edge Selection Position */ +#define TC_CMR_ETRGEDG(value) DEPRECATED(TC_CMR_ETRGEDG, "Using deprecated macro TC_CMR_ETRGEDG") (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) +#define TC_CMR_LDBDIS_Msk DEPRECATED(TC_CMR_LDBDIS_Msk, "Using deprecated macro TC_CMR_LDBDIS_Msk") (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ +#define TC_CMR_LDBDIS_Pos DEPRECATED(TC_CMR_LDBDIS_Pos, "Using deprecated macro TC_CMR_LDBDIS_Pos") 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ +#define TC_CMR_LDBDIS DEPRECATED(TC_CMR_LDBDIS, "Using deprecated macro TC_CMR_LDBDIS") TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */ +#define TC_CMR_LDBSTOP_Msk DEPRECATED(TC_CMR_LDBSTOP_Msk, "Using deprecated macro TC_CMR_LDBSTOP_Msk") (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ +#define TC_CMR_LDBSTOP_Pos DEPRECATED(TC_CMR_LDBSTOP_Pos, "Using deprecated macro TC_CMR_LDBSTOP_Pos") 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ +#define TC_CMR_LDBSTOP DEPRECATED(TC_CMR_LDBSTOP, "Using deprecated macro TC_CMR_LDBSTOP") TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */ +#define TC_CMR_LDRA_Msk DEPRECATED(TC_CMR_LDRA_Msk, "Using deprecated macro TC_CMR_LDRA_Msk") (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ +#define TC_CMR_LDRA_Pos DEPRECATED(TC_CMR_LDRA_Pos, "Using deprecated macro TC_CMR_LDRA_Pos") 16 /**< (TC_CMR) RA Loading Edge Selection Position */ +#define TC_CMR_LDRA(value) DEPRECATED(TC_CMR_LDRA, "Using deprecated macro TC_CMR_LDRA") (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)) +#define TC_CMR_LDRB_Msk DEPRECATED(TC_CMR_LDRB_Msk, "Using deprecated macro TC_CMR_LDRB_Msk") (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ +#define TC_CMR_LDRB_Pos DEPRECATED(TC_CMR_LDRB_Pos, "Using deprecated macro TC_CMR_LDRB_Pos") 18 /**< (TC_CMR) RB Loading Edge Selection Position */ +#define TC_CMR_LDRB(value) DEPRECATED(TC_CMR_LDRB, "Using deprecated macro TC_CMR_LDRB") (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)) +#define TC_CMR_SBSMPLR_Msk DEPRECATED(TC_CMR_SBSMPLR_Msk, "Using deprecated macro TC_CMR_SBSMPLR_Msk") (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ +#define TC_CMR_SBSMPLR_Pos DEPRECATED(TC_CMR_SBSMPLR_Pos, "Using deprecated macro TC_CMR_SBSMPLR_Pos") 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ +#define TC_CMR_SBSMPLR(value) DEPRECATED(TC_CMR_SBSMPLR, "Using deprecated macro TC_CMR_SBSMPLR") (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)) +#endif diff --git a/bsp/microchip/same70/bsp/same70b/include/component/deprecated/template.h b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/template.h new file mode 100644 index 0000000000..0fd033ca74 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/template.h @@ -0,0 +1,41 @@ +/** + * \file + * \brief This file is for deprecated macro constants + * + * Used to mark macro constants as deprecate. + * Uses a macro 'DEPRECTAED' to give warnings during compilation (GCC >= 4.8) + * + * \remark To use, add defines and put a DEPRECATED statement between the macro name and the value + * + * \note This file is manually maintained + */ + +#ifndef ___COMPONENT_DEPRECATED_H_ +#define ___COMPONENT_DEPRECATED_H_ + +#ifndef DEPRECATED +#define _DEP_STRING(X) #X + +/** \hideinitializer + * \brief Macro deprecation mark + * + * Putting this in a macro definition will emit deprecation warning when given + * macro is used (GCC 4.8) + * + * \code{.c} + * #define OLD_MACRO DEPRECATED(OLD_MACRO, "deprecated ") + * \endcode + * + * \warning Using these macros in #if statements will not work + */ +#if defined(__GNUC__) && __GNUC__*100 + __GNUC_MINOR__ >= 408 +#define DEPRECATED(macro, message) _Pragma (_DEP_STRING(GCC warning message)) +#else +#define DEPRECATED(macro, message) +#endif +#endif + +/* deprecated defines added below here */ +#define _OLD_MACRO DEPRECATED(_OLD_MACRO, "deprecated") + +#endif diff --git a/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usart.h b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usart.h new file mode 100644 index 0000000000..b94e5a714e --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usart.h @@ -0,0 +1,250 @@ +/** + * \file + * \brief This file is for deprecated macro constants + * + * Used to mark macro constants as deprecate. + * Uses a macro 'DEPRECTAED' to give warnings during compilation (GCC >= 4.8) + * + * \remark To use, add defines and put a DEPRECATED statement between the macro name and the value + * + * \note This file is manually maintained + */ + +#ifndef _SAME70_USART_COMPONENT_DEPRECATED_H_ +#define _SAME70_USART_COMPONENT_DEPRECATED_H_ + +#ifndef DEPRECATED +#define _DEP_STRING(X) #X + +/** \hideinitializer + * \brief Macro deprecation mark + * + * Putting this in a macro definition will emit deprecation warning when given + * macro is used (GCC 4.8) + * + * \code{.c} + * #define OLD_MACRO DEPRECATED(OLD_MACRO, "deprecated ") + * \endcode + * + * \warning Using these macros in #if statements will not work + */ +#if defined(__GNUC__) && __GNUC__*100 + __GNUC_MINOR__ >= 408 +#define DEPRECATED(macro, message) _Pragma (_DEP_STRING(GCC warning message)) +#else +#define DEPRECATED(macro, message) +#endif +#endif + +/* deprecated defines added below here */ +#define US_CR_DTRDIS_Msk DEPRECATED(US_CR_DTRDIS_Msk, "Using deprecated macro US_CR_DTRDIS_Msk") (_U_(0x1) << US_CR_DTRDIS_Pos) /**< (US_CR) Data Terminal Ready Disable Mask */ +#define US_CR_DTRDIS_Pos DEPRECATED(US_CR_DTRDIS_Pos, "Using deprecated macro US_CR_DTRDIS_Pos") 17 /**< (US_CR) Data Terminal Ready Disable Position */ +#define US_CR_DTRDIS DEPRECATED(US_CR_DTRDIS, "Using deprecated macro US_CR_DTRDIS") US_CR_DTRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_DTRDIS_Msk instead */ +#define US_CR_DTREN_Msk DEPRECATED(US_CR_DTREN_Msk, "Using deprecated macro US_CR_DTREN_Msk") (_U_(0x1) << US_CR_DTREN_Pos) /**< (US_CR) Data Terminal Ready Enable Mask */ +#define US_CR_DTREN_Pos DEPRECATED(US_CR_DTREN_Pos, "Using deprecated macro US_CR_DTREN_Pos") 16 /**< (US_CR) Data Terminal Ready Enable Position */ +#define US_CR_DTREN DEPRECATED(US_CR_DTREN, "Using deprecated macro US_CR_DTREN") US_CR_DTREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_DTREN_Msk instead */ +#define US_CR_LINABT_Msk DEPRECATED(US_CR_LINABT_Msk, "Using deprecated macro US_CR_LINABT_Msk") (_U_(0x1) << US_CR_LINABT_Pos) /**< (US_CR) Abort LIN Transmission Mask */ +#define US_CR_LINABT_Pos DEPRECATED(US_CR_LINABT_Pos, "Using deprecated macro US_CR_LINABT_Pos") 20 /**< (US_CR) Abort LIN Transmission Position */ +#define US_CR_LINABT DEPRECATED(US_CR_LINABT, "Using deprecated macro US_CR_LINABT") US_CR_LINABT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_LINABT_Msk instead */ +#define US_CR_LINWKUP_Msk DEPRECATED(US_CR_LINWKUP_Msk, "Using deprecated macro US_CR_LINWKUP_Msk") (_U_(0x1) << US_CR_LINWKUP_Pos) /**< (US_CR) Send LIN Wakeup Signal Mask */ +#define US_CR_LINWKUP_Pos DEPRECATED(US_CR_LINWKUP_Pos, "Using deprecated macro US_CR_LINWKUP_Pos") 21 /**< (US_CR) Send LIN Wakeup Signal Position */ +#define US_CR_LINWKUP DEPRECATED(US_CR_LINWKUP, "Using deprecated macro US_CR_LINWKUP") US_CR_LINWKUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_LINWKUP_Msk instead */ +#define US_CR_RETTO_Msk DEPRECATED(US_CR_RETTO_Msk, "Using deprecated macro US_CR_RETTO_Msk") (_U_(0x1) << US_CR_RETTO_Pos) /**< (US_CR) Start Time-out Immediately Mask */ +#define US_CR_RETTO_Pos DEPRECATED(US_CR_RETTO_Pos, "Using deprecated macro US_CR_RETTO_Pos") 15 /**< (US_CR) Start Time-out Immediately Position */ +#define US_CR_RETTO DEPRECATED(US_CR_RETTO, "Using deprecated macro US_CR_RETTO") US_CR_RETTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RETTO_Msk instead */ +#define US_CR_RSTIT_Msk DEPRECATED(US_CR_RSTIT_Msk, "Using deprecated macro US_CR_RSTIT_Msk") (_U_(0x1) << US_CR_RSTIT_Pos) /**< (US_CR) Reset Iterations Mask */ +#define US_CR_RSTIT_Pos DEPRECATED(US_CR_RSTIT_Pos, "Using deprecated macro US_CR_RSTIT_Pos") 13 /**< (US_CR) Reset Iterations Position */ +#define US_CR_RSTIT DEPRECATED(US_CR_RSTIT, "Using deprecated macro US_CR_RSTIT") US_CR_RSTIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RSTIT_Msk instead */ +#define US_CR_RSTNACK_Msk DEPRECATED(US_CR_RSTNACK_Msk, "Using deprecated macro US_CR_RSTNACK_Msk") (_U_(0x1) << US_CR_RSTNACK_Pos) /**< (US_CR) Reset Non Acknowledge Mask */ +#define US_CR_RSTNACK_Pos DEPRECATED(US_CR_RSTNACK_Pos, "Using deprecated macro US_CR_RSTNACK_Pos") 14 /**< (US_CR) Reset Non Acknowledge Position */ +#define US_CR_RSTNACK DEPRECATED(US_CR_RSTNACK, "Using deprecated macro US_CR_RSTNACK") US_CR_RSTNACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RSTNACK_Msk instead */ +#define US_CR_RTSDIS_Msk DEPRECATED(US_CR_RTSDIS_Msk, "Using deprecated macro US_CR_RTSDIS_Msk") (_U_(0x1) << US_CR_RTSDIS_Pos) /**< (US_CR) Request to Send Pin Control Mask */ +#define US_CR_RTSDIS_Pos DEPRECATED(US_CR_RTSDIS_Pos, "Using deprecated macro US_CR_RTSDIS_Pos") 19 /**< (US_CR) Request to Send Pin Control Position */ +#define US_CR_RTSDIS DEPRECATED(US_CR_RTSDIS, "Using deprecated macro US_CR_RTSDIS") US_CR_RTSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RTSDIS_Msk instead */ +#define US_CR_RTSEN_Msk DEPRECATED(US_CR_RTSEN_Msk, "Using deprecated macro US_CR_RTSEN_Msk") (_U_(0x1) << US_CR_RTSEN_Pos) /**< (US_CR) Request to Send Pin Control Mask */ +#define US_CR_RTSEN_Pos DEPRECATED(US_CR_RTSEN_Pos, "Using deprecated macro US_CR_RTSEN_Pos") 18 /**< (US_CR) Request to Send Pin Control Position */ +#define US_CR_RTSEN DEPRECATED(US_CR_RTSEN, "Using deprecated macro US_CR_RTSEN") US_CR_RTSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RTSEN_Msk instead */ +#define US_CR_SENDA_Msk DEPRECATED(US_CR_SENDA_Msk, "Using deprecated macro US_CR_SENDA_Msk") (_U_(0x1) << US_CR_SENDA_Pos) /**< (US_CR) Send Address Mask */ +#define US_CR_SENDA_Pos DEPRECATED(US_CR_SENDA_Pos, "Using deprecated macro US_CR_SENDA_Pos") 12 /**< (US_CR) Send Address Position */ +#define US_CR_SENDA DEPRECATED(US_CR_SENDA, "Using deprecated macro US_CR_SENDA") US_CR_SENDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_SENDA_Msk instead */ +#define US_CR_STPBRK_Msk DEPRECATED(US_CR_STPBRK_Msk, "Using deprecated macro US_CR_STPBRK_Msk") (_U_(0x1) << US_CR_STPBRK_Pos) /**< (US_CR) Stop Break Mask */ +#define US_CR_STPBRK_Pos DEPRECATED(US_CR_STPBRK_Pos, "Using deprecated macro US_CR_STPBRK_Pos") 10 /**< (US_CR) Stop Break Position */ +#define US_CR_STPBRK DEPRECATED(US_CR_STPBRK, "Using deprecated macro US_CR_STPBRK") US_CR_STPBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_STPBRK_Msk instead */ +#define US_CR_STTBRK_Msk DEPRECATED(US_CR_STTBRK_Msk, "Using deprecated macro US_CR_STTBRK_Msk") (_U_(0x1) << US_CR_STTBRK_Pos) /**< (US_CR) Start Break Mask */ +#define US_CR_STTBRK_Pos DEPRECATED(US_CR_STTBRK_Pos, "Using deprecated macro US_CR_STTBRK_Pos") 9 /**< (US_CR) Start Break Position */ +#define US_CR_STTBRK DEPRECATED(US_CR_STTBRK, "Using deprecated macro US_CR_STTBRK") US_CR_STTBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_STTBRK_Msk instead */ +#define US_CR_STTTO_Msk DEPRECATED(US_CR_STTTO_Msk, "Using deprecated macro US_CR_STTTO_Msk") (_U_(0x1) << US_CR_STTTO_Pos) /**< (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received Mask */ +#define US_CR_STTTO_Pos DEPRECATED(US_CR_STTTO_Pos, "Using deprecated macro US_CR_STTTO_Pos") 11 /**< (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received Position */ +#define US_CR_STTTO DEPRECATED(US_CR_STTTO, "Using deprecated macro US_CR_STTTO") US_CR_STTTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_STTTO_Msk instead */ +#define US_CSR_CTSIC_Msk DEPRECATED(US_CSR_CTSIC_Msk, "Using deprecated macro US_CSR_CTSIC_Msk") (_U_(0x1) << US_CSR_CTSIC_Pos) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Mask */ +#define US_CSR_CTSIC_Pos DEPRECATED(US_CSR_CTSIC_Pos, "Using deprecated macro US_CSR_CTSIC_Pos") 19 /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Position */ +#define US_CSR_CTSIC DEPRECATED(US_CSR_CTSIC, "Using deprecated macro US_CSR_CTSIC") US_CSR_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_CTSIC_Msk instead */ +#define US_CSR_CTS_Msk DEPRECATED(US_CSR_CTS_Msk, "Using deprecated macro US_CSR_CTS_Msk") (_U_(0x1) << US_CSR_CTS_Pos) /**< (US_CSR) Image of CTS Input Mask */ +#define US_CSR_CTS_Pos DEPRECATED(US_CSR_CTS_Pos, "Using deprecated macro US_CSR_CTS_Pos") 23 /**< (US_CSR) Image of CTS Input Position */ +#define US_CSR_CTS DEPRECATED(US_CSR_CTS, "Using deprecated macro US_CSR_CTS") US_CSR_CTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_CTS_Msk instead */ +#define US_CSR_DCD_Msk DEPRECATED(US_CSR_DCD_Msk, "Using deprecated macro US_CSR_DCD_Msk") (_U_(0x1) << US_CSR_DCD_Pos) /**< (US_CSR) Image of DCD Input Mask */ +#define US_CSR_DCD_Pos DEPRECATED(US_CSR_DCD_Pos, "Using deprecated macro US_CSR_DCD_Pos") 22 /**< (US_CSR) Image of DCD Input Position */ +#define US_CSR_DCD DEPRECATED(US_CSR_DCD, "Using deprecated macro US_CSR_DCD") US_CSR_DCD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_DCD_Msk instead */ +#define US_CSR_DSR_Msk DEPRECATED(US_CSR_DSR_Msk, "Using deprecated macro US_CSR_DSR_Msk") (_U_(0x1) << US_CSR_DSR_Pos) /**< (US_CSR) Image of DSR Input Mask */ +#define US_CSR_DSR_Pos DEPRECATED(US_CSR_DSR_Pos, "Using deprecated macro US_CSR_DSR_Pos") 21 /**< (US_CSR) Image of DSR Input Position */ +#define US_CSR_DSR DEPRECATED(US_CSR_DSR, "Using deprecated macro US_CSR_DSR") US_CSR_DSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_DSR_Msk instead */ +#define US_CSR_FRAME_Msk DEPRECATED(US_CSR_FRAME_Msk, "Using deprecated macro US_CSR_FRAME_Msk") (_U_(0x1) << US_CSR_FRAME_Pos) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_FRAME_Pos DEPRECATED(US_CSR_FRAME_Pos, "Using deprecated macro US_CSR_FRAME_Pos") 6 /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_FRAME DEPRECATED(US_CSR_FRAME, "Using deprecated macro US_CSR_FRAME") US_CSR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_FRAME_Msk instead */ +#define US_CSR_ITER_Msk DEPRECATED(US_CSR_ITER_Msk, "Using deprecated macro US_CSR_ITER_Msk") (_U_(0x1) << US_CSR_ITER_Pos) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Mask */ +#define US_CSR_ITER_Pos DEPRECATED(US_CSR_ITER_Pos, "Using deprecated macro US_CSR_ITER_Pos") 10 /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Position */ +#define US_CSR_ITER DEPRECATED(US_CSR_ITER, "Using deprecated macro US_CSR_ITER") US_CSR_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_ITER_Msk instead */ +#define US_CSR_MANERR_Msk DEPRECATED(US_CSR_MANERR_Msk, "Using deprecated macro US_CSR_MANERR_Msk") (_U_(0x1) << US_CSR_MANERR_Pos) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Mask */ +#define US_CSR_MANERR_Pos DEPRECATED(US_CSR_MANERR_Pos, "Using deprecated macro US_CSR_MANERR_Pos") 24 /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Position */ +#define US_CSR_MANERR DEPRECATED(US_CSR_MANERR, "Using deprecated macro US_CSR_MANERR") US_CSR_MANERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_MANERR_Msk instead */ +#define US_CSR_NACK_Msk DEPRECATED(US_CSR_NACK_Msk, "Using deprecated macro US_CSR_NACK_Msk") (_U_(0x1) << US_CSR_NACK_Pos) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Mask */ +#define US_CSR_NACK_Pos DEPRECATED(US_CSR_NACK_Pos, "Using deprecated macro US_CSR_NACK_Pos") 13 /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Position */ +#define US_CSR_NACK DEPRECATED(US_CSR_NACK, "Using deprecated macro US_CSR_NACK") US_CSR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_NACK_Msk instead */ +#define US_CSR_PARE_Msk DEPRECATED(US_CSR_PARE_Msk, "Using deprecated macro US_CSR_PARE_Msk") (_U_(0x1) << US_CSR_PARE_Pos) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_PARE_Pos DEPRECATED(US_CSR_PARE_Pos, "Using deprecated macro US_CSR_PARE_Pos") 7 /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_PARE DEPRECATED(US_CSR_PARE, "Using deprecated macro US_CSR_PARE") US_CSR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_PARE_Msk instead */ +#define US_CSR_RI_Msk DEPRECATED(US_CSR_RI_Msk, "Using deprecated macro US_CSR_RI_Msk") (_U_(0x1) << US_CSR_RI_Pos) /**< (US_CSR) Image of RI Input Mask */ +#define US_CSR_RI_Pos DEPRECATED(US_CSR_RI_Pos, "Using deprecated macro US_CSR_RI_Pos") 20 /**< (US_CSR) Image of RI Input Position */ +#define US_CSR_RI DEPRECATED(US_CSR_RI, "Using deprecated macro US_CSR_RI") US_CSR_RI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_RI_Msk instead */ +#define US_CSR_RXBRK_Msk DEPRECATED(US_CSR_RXBRK_Msk, "Using deprecated macro US_CSR_RXBRK_Msk") (_U_(0x1) << US_CSR_RXBRK_Pos) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_RXBRK_Pos DEPRECATED(US_CSR_RXBRK_Pos, "Using deprecated macro US_CSR_RXBRK_Pos") 2 /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_RXBRK DEPRECATED(US_CSR_RXBRK, "Using deprecated macro US_CSR_RXBRK") US_CSR_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_RXBRK_Msk instead */ +#define US_CSR_TIMEOUT_Msk DEPRECATED(US_CSR_TIMEOUT_Msk, "Using deprecated macro US_CSR_TIMEOUT_Msk") (_U_(0x1) << US_CSR_TIMEOUT_Pos) /**< (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) Mask */ +#define US_CSR_TIMEOUT_Pos DEPRECATED(US_CSR_TIMEOUT_Pos, "Using deprecated macro US_CSR_TIMEOUT_Pos") 8 /**< (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) Position */ +#define US_CSR_TIMEOUT DEPRECATED(US_CSR_TIMEOUT, "Using deprecated macro US_CSR_TIMEOUT") US_CSR_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_TIMEOUT_Msk instead */ +#define US_FIDI_FI_DI_RATIO_Msk DEPRECATED(US_FIDI_FI_DI_RATIO_Msk, "Using deprecated macro US_FIDI_FI_DI_RATIO_Msk") (_U_(0xFFFF) << US_FIDI_FI_DI_RATIO_Pos) /**< (US_FIDI) FI Over DI Ratio Value Mask */ +#define US_FIDI_FI_DI_RATIO_Pos DEPRECATED(US_FIDI_FI_DI_RATIO_Pos, "Using deprecated macro US_FIDI_FI_DI_RATIO_Pos") 0 /**< (US_FIDI) FI Over DI Ratio Value Position */ +#define US_FIDI_FI_DI_RATIO(value) DEPRECATED(US_FIDI_FI_DI_RATIO, "Using deprecated macro US_FIDI_FI_DI_RATIO") (US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)) +#define US_IDR_CTSIC_Msk DEPRECATED(US_IDR_CTSIC_Msk, "Using deprecated macro US_IDR_CTSIC_Msk") (_U_(0x1) << US_IDR_CTSIC_Pos) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Mask */ +#define US_IDR_CTSIC_Pos DEPRECATED(US_IDR_CTSIC_Pos, "Using deprecated macro US_IDR_CTSIC_Pos") 19 /**< (US_IDR) Clear to Send Input Change Interrupt Disable Position */ +#define US_IDR_CTSIC DEPRECATED(US_IDR_CTSIC, "Using deprecated macro US_IDR_CTSIC") US_IDR_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_CTSIC_Msk instead */ +#define US_IDR_FRAME_Msk DEPRECATED(US_IDR_FRAME_Msk, "Using deprecated macro US_IDR_FRAME_Msk") (_U_(0x1) << US_IDR_FRAME_Pos) /**< (US_IDR) Framing Error Interrupt Disable Mask */ +#define US_IDR_FRAME_Pos DEPRECATED(US_IDR_FRAME_Pos, "Using deprecated macro US_IDR_FRAME_Pos") 6 /**< (US_IDR) Framing Error Interrupt Disable Position */ +#define US_IDR_FRAME DEPRECATED(US_IDR_FRAME, "Using deprecated macro US_IDR_FRAME") US_IDR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_FRAME_Msk instead */ +#define US_IDR_ITER_Msk DEPRECATED(US_IDR_ITER_Msk, "Using deprecated macro US_IDR_ITER_Msk") (_U_(0x1) << US_IDR_ITER_Pos) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Mask */ +#define US_IDR_ITER_Pos DEPRECATED(US_IDR_ITER_Pos, "Using deprecated macro US_IDR_ITER_Pos") 10 /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Position */ +#define US_IDR_ITER DEPRECATED(US_IDR_ITER, "Using deprecated macro US_IDR_ITER") US_IDR_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_ITER_Msk instead */ +#define US_IDR_MANE_Msk DEPRECATED(US_IDR_MANE_Msk, "Using deprecated macro US_IDR_MANE_Msk") (_U_(0x1) << US_IDR_MANE_Pos) /**< (US_IDR) Manchester Error Interrupt Disable Mask */ +#define US_IDR_MANE_Pos DEPRECATED(US_IDR_MANE_Pos, "Using deprecated macro US_IDR_MANE_Pos") 24 /**< (US_IDR) Manchester Error Interrupt Disable Position */ +#define US_IDR_MANE DEPRECATED(US_IDR_MANE, "Using deprecated macro US_IDR_MANE") US_IDR_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_MANE_Msk instead */ +#define US_IDR_NACK_Msk DEPRECATED(US_IDR_NACK_Msk, "Using deprecated macro US_IDR_NACK_Msk") (_U_(0x1) << US_IDR_NACK_Pos) /**< (US_IDR) Non Acknowledge Interrupt Disable Mask */ +#define US_IDR_NACK_Pos DEPRECATED(US_IDR_NACK_Pos, "Using deprecated macro US_IDR_NACK_Pos") 13 /**< (US_IDR) Non Acknowledge Interrupt Disable Position */ +#define US_IDR_NACK DEPRECATED(US_IDR_NACK, "Using deprecated macro US_IDR_NACK") US_IDR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_NACK_Msk instead */ +#define US_IDR_PARE_Msk DEPRECATED(US_IDR_PARE_Msk, "Using deprecated macro US_IDR_PARE_Msk") (_U_(0x1) << US_IDR_PARE_Pos) /**< (US_IDR) Parity Error Interrupt Disable Mask */ +#define US_IDR_PARE_Pos DEPRECATED(US_IDR_PARE_Pos, "Using deprecated macro US_IDR_PARE_Pos") 7 /**< (US_IDR) Parity Error Interrupt Disable Position */ +#define US_IDR_PARE DEPRECATED(US_IDR_PARE, "Using deprecated macro US_IDR_PARE") US_IDR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_PARE_Msk instead */ +#define US_IDR_RXBRK_Msk DEPRECATED(US_IDR_RXBRK_Msk, "Using deprecated macro US_IDR_RXBRK_Msk") (_U_(0x1) << US_IDR_RXBRK_Pos) /**< (US_IDR) Receiver Break Interrupt Disable Mask */ +#define US_IDR_RXBRK_Pos DEPRECATED(US_IDR_RXBRK_Pos, "Using deprecated macro US_IDR_RXBRK_Pos") 2 /**< (US_IDR) Receiver Break Interrupt Disable Position */ +#define US_IDR_RXBRK DEPRECATED(US_IDR_RXBRK, "Using deprecated macro US_IDR_RXBRK") US_IDR_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_RXBRK_Msk instead */ +#define US_IDR_TIMEOUT_Msk DEPRECATED(US_IDR_TIMEOUT_Msk, "Using deprecated macro US_IDR_TIMEOUT_Msk") (_U_(0x1) << US_IDR_TIMEOUT_Pos) /**< (US_IDR) Time-out Interrupt Disable Mask */ +#define US_IDR_TIMEOUT_Pos DEPRECATED(US_IDR_TIMEOUT_Pos, "Using deprecated macro US_IDR_TIMEOUT_Pos") 8 /**< (US_IDR) Time-out Interrupt Disable Position */ +#define US_IDR_TIMEOUT DEPRECATED(US_IDR_TIMEOUT, "Using deprecated macro US_IDR_TIMEOUT") US_IDR_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_TIMEOUT_Msk instead */ +#define US_IER_CTSIC_Msk DEPRECATED(US_IER_CTSIC_Msk, "Using deprecated macro US_IER_CTSIC_Msk") (_U_(0x1) << US_IER_CTSIC_Pos) /**< (US_IER) Clear to Send Input Change Interrupt Enable Mask */ +#define US_IER_CTSIC_Pos DEPRECATED(US_IER_CTSIC_Pos, "Using deprecated macro US_IER_CTSIC_Pos") 19 /**< (US_IER) Clear to Send Input Change Interrupt Enable Position */ +#define US_IER_CTSIC DEPRECATED(US_IER_CTSIC, "Using deprecated macro US_IER_CTSIC") US_IER_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_CTSIC_Msk instead */ +#define US_IER_DCDIC_Msk DEPRECATED(US_IER_DCDIC_Msk, "Using deprecated macro US_IER_DCDIC_Msk") (_U_(0x1) << US_IER_DCDIC_Pos) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Mask */ +#define US_IER_DCDIC_Pos DEPRECATED(US_IER_DCDIC_Pos, "Using deprecated macro US_IER_DCDIC_Pos") 18 /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Position */ +#define US_IER_DCDIC DEPRECATED(US_IER_DCDIC, "Using deprecated macro US_IER_DCDIC") US_IER_DCDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_DCDIC_Msk instead */ +#define US_IER_DSRIC_Msk DEPRECATED(US_IER_DSRIC_Msk, "Using deprecated macro US_IER_DSRIC_Msk") (_U_(0x1) << US_IER_DSRIC_Pos) /**< (US_IER) Data Set Ready Input Change Enable Mask */ +#define US_IER_DSRIC_Pos DEPRECATED(US_IER_DSRIC_Pos, "Using deprecated macro US_IER_DSRIC_Pos") 17 /**< (US_IER) Data Set Ready Input Change Enable Position */ +#define US_IER_DSRIC DEPRECATED(US_IER_DSRIC, "Using deprecated macro US_IER_DSRIC") US_IER_DSRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_DSRIC_Msk instead */ +#define US_IER_FRAME_Msk DEPRECATED(US_IER_FRAME_Msk, "Using deprecated macro US_IER_FRAME_Msk") (_U_(0x1) << US_IER_FRAME_Pos) /**< (US_IER) Framing Error Interrupt Enable Mask */ +#define US_IER_FRAME_Pos DEPRECATED(US_IER_FRAME_Pos, "Using deprecated macro US_IER_FRAME_Pos") 6 /**< (US_IER) Framing Error Interrupt Enable Position */ +#define US_IER_FRAME DEPRECATED(US_IER_FRAME, "Using deprecated macro US_IER_FRAME") US_IER_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_FRAME_Msk instead */ +#define US_IER_ITER_Msk DEPRECATED(US_IER_ITER_Msk, "Using deprecated macro US_IER_ITER_Msk") (_U_(0x1) << US_IER_ITER_Pos) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Mask */ +#define US_IER_ITER_Pos DEPRECATED(US_IER_ITER_Pos, "Using deprecated macro US_IER_ITER_Pos") 10 /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Position */ +#define US_IER_ITER DEPRECATED(US_IER_ITER, "Using deprecated macro US_IER_ITER") US_IER_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_ITER_Msk instead */ +#define US_IER_MANE_Msk DEPRECATED(US_IER_MANE_Msk, "Using deprecated macro US_IER_MANE_Msk") (_U_(0x1) << US_IER_MANE_Pos) /**< (US_IER) Manchester Error Interrupt Enable Mask */ +#define US_IER_MANE_Pos DEPRECATED(US_IER_MANE_Pos, "Using deprecated macro US_IER_MANE_Po") 24 /**< (US_IER) Manchester Error Interrupt Enable Position */ +#define US_IER_MANE DEPRECATED(US_IER_MANE, "Using deprecated macro US_IER_MANE") US_IER_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_MANE_Msk instead */ +#define US_IER_NACK_Msk DEPRECATED(US_IER_NACK_Msk, "Using deprecated macro US_IER_NACK_Msk") (_U_(0x1) << US_IER_NACK_Pos) /**< (US_IER) Non Acknowledge Interrupt Enable Mask */ +#define US_IER_NACK_Pos DEPRECATED(US_IER_NACK_Pos, "Using deprecated macro US_IER_NACK_Pos") 13 /**< (US_IER) Non Acknowledge Interrupt Enable Position */ +#define US_IER_NACK DEPRECATED(US_IER_NACK, "Using deprecated macro US_IER_NAC") US_IER_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_NACK_Msk instead */ +#define US_IER_PARE_Msk DEPRECATED(US_IER_PARE_Msk, "Using deprecated macro US_IER_PARE_Msk") (_U_(0x1) << US_IER_PARE_Pos) /**< (US_IER) Parity Error Interrupt Enable Mask */ +#define US_IER_PARE_Pos DEPRECATED(US_IER_PARE_Pos, "Using deprecated macro US_IER_PARE_Pos") 7 /**< (US_IER) Parity Error Interrupt Enable Position */ +#define US_IER_PARE DEPRECATED(US_IER_PARE, "Using deprecated macro US_IER_PARE") US_IER_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_PARE_Msk instead */ +#define US_IER_RIIC_Msk DEPRECATED(US_IER_RIIC_Msk, "Using deprecated macro US_IER_RIIC_Msk") (_U_(0x1) << US_IER_RIIC_Pos) /**< (US_IER) Ring Indicator Input Change Enable Mask */ +#define US_IER_RIIC_Pos DEPRECATED(US_IER_RIIC_Pos, "Using deprecated macro US_IER_RIIC_Pos") 16 /**< (US_IER) Ring Indicator Input Change Enable Position */ +#define US_IER_RIIC DEPRECATED(US_IER_RIIC, "Using deprecated macro US_IER_RIIC") US_IER_RIIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_RIIC_Msk instead */ +#define US_IER_RXBRK_Msk DEPRECATED(US_IER_RXBRK_Msk, "Using deprecated macro US_IER_RXBRK_Msk") (_U_(0x1) << US_IER_RXBRK_Pos) /**< (US_IER) Receiver Break Interrupt Enable Mask */ +#define US_IER_RXBRK_Pos DEPRECATED(US_IER_RXBRK_Pos, "Using deprecated macro US_IER_RXBRK_Pos") 2 /**< (US_IER) Receiver Break Interrupt Enable Position */ +#define US_IER_RXBRK DEPRECATED(US_IER_RXBRK, "Using deprecated macro US_IER_RXBRK") US_IER_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_RXBRK_Msk instead */ +#define US_IER_TIMEOUT_Msk DEPRECATED(US_IER_TIMEOUT_Msk, "Using deprecated macro US_IER_TIMEOUT_Msk") (_U_(0x1) << US_IER_TIMEOUT_Pos) /**< (US_IER) Time-out Interrupt Enable Mask */ +#define US_IER_TIMEOUT_Pos DEPRECATED(US_IER_TIMEOUT_Pos, "Using deprecated macro US_IER_TIMEOUT_Pos") 8 /**< (US_IER) Time-out Interrupt Enable Position */ +#define US_IER_TIMEOUT DEPRECATED(US_IER_TIMEOUT, "Using deprecated macro US_IER_TIMEOUT") US_IER_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_TIMEOUT_Msk instead */ +#define US_IMR_CTSIC_Msk DEPRECATED(US_IMR_CTSIC_Msk, "Using deprecated macro US_IMR_CTSIC_Msk") (_U_(0x1) << US_IMR_CTSIC_Pos) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Mask */ +#define US_IMR_CTSIC_Pos DEPRECATED(US_IMR_CTSIC_Pos, "Using deprecated macro US_IMR_CTSIC_Pos") 19 /**< (US_IMR) Clear to Send Input Change Interrupt Mask Position */ +#define US_IMR_CTSIC DEPRECATED(US_IMR_CTSIC, "Using deprecated macro US_IMR_CTSIC") US_IMR_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_CTSIC_Msk instead */ +#define US_IMR_FRAME_Msk DEPRECATED(US_IMR_FRAME_Msk, "Using deprecated macro US_IMR_FRAME_Msk") (_U_(0x1) << US_IMR_FRAME_Pos) /**< (US_IMR) Framing Error Interrupt Mask Mask */ +#define US_IMR_FRAME_Pos DEPRECATED(US_IMR_FRAME_Pos, "Using deprecated macro US_IMR_FRAME_Pos") 6 /**< (US_IMR) Framing Error Interrupt Mask Position */ +#define US_IMR_FRAME DEPRECATED(US_IMR_FRAME, "Using deprecated macro US_IMR_FRAME") US_IMR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_FRAME_Msk instead */ +#define US_IMR_ITER_Msk DEPRECATED(US_IMR_ITER_Msk, "Using deprecated macro US_IMR_ITER_Msk") (_U_(0x1) << US_IMR_ITER_Pos) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Mask */ +#define US_IMR_ITER_Pos DEPRECATED(US_IMR_ITER_Pos, "Using deprecated macro US_IMR_ITER_Pos") 10 /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Position */ +#define US_IMR_ITER DEPRECATED(US_IMR_ITER, "Using deprecated macro US_IMR_ITER") US_IMR_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_ITER_Msk instead */ +#define US_IMR_MANE_Msk DEPRECATED(US_IMR_MANE_Msk, "Using deprecated macro US_IMR_MANE_Msk") (_U_(0x1) << US_IMR_MANE_Pos) /**< (US_IMR) Manchester Error Interrupt Mask Mask */ +#define US_IMR_MANE_Pos DEPRECATED(US_IMR_MANE_Pos, "Using deprecated macro US_IMR_MANE_Pos") 24 /**< (US_IMR) Manchester Error Interrupt Mask Position */ +#define US_IMR_MANE DEPRECATED(US_IMR_MANE, "Using deprecated macro US_IMR_MANE") US_IMR_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_MANE_Msk instead */ +#define US_IMR_NACK_Msk DEPRECATED(US_IMR_NACK_Msk, "Using deprecated macro US_IMR_NACK_Msk") (_U_(0x1) << US_IMR_NACK_Pos) /**< (US_IMR) Non Acknowledge Interrupt Mask Mask */ +#define US_IMR_NACK_Pos DEPRECATED(US_IMR_NACK_Pos, "Using deprecated macro US_IMR_NACK_Pos") 13 /**< (US_IMR) Non Acknowledge Interrupt Mask Position */ +#define US_IMR_NACK DEPRECATED(US_IMR_NACK, "Using deprecated macro US_IMR_NACK") US_IMR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_NACK_Msk instead */ +#define US_IMR_PARE_Msk DEPRECATED(US_IMR_PARE_Msk, "Using deprecated macro US_IMR_PARE_Msk") (_U_(0x1) << US_IMR_PARE_Pos) /**< (US_IMR) Parity Error Interrupt Mask Mask */ +#define US_IMR_PARE_Pos DEPRECATED(US_IMR_PARE_Pos, "Using deprecated macro US_IMR_PARE_Pos") 7 /**< (US_IMR) Parity Error Interrupt Mask Position */ +#define US_IMR_PARE DEPRECATED(US_IMR_PARE, "Using deprecated macro US_IMR_PARE") US_IMR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_PARE_Msk instead */ +#define US_IMR_RXBRK_Msk DEPRECATED(US_IMR_RXBRK_Msk, "Using deprecated macro US_IMR_RXBRK_Msk") (_U_(0x1) << US_IMR_RXBRK_Pos) /**< (US_IMR) Receiver Break Interrupt Mask Mask */ +#define US_IMR_RXBRK_Pos DEPRECATED(US_IMR_RXBRK_Pos, "Using deprecated macro US_IMR_RXBRK_Pos") 2 /**< (US_IMR) Receiver Break Interrupt Mask Position */ +#define US_IMR_RXBRK DEPRECATED(US_IMR_RXBRK, "Using deprecated macro US_IMR_RXBRK") US_IMR_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_RXBRK_Msk instead */ +#define US_IMR_TIMEOUT_Msk DEPRECATED(US_IMR_TIMEOUT_Msk, "Using deprecated macro US_IMR_TIMEOUT_Msk") (_U_(0x1) << US_IMR_TIMEOUT_Pos) /**< (US_IMR) Time-out Interrupt Mask Mask */ +#define US_IMR_TIMEOUT_Pos DEPRECATED(US_IMR_TIMEOUT_Pos, "Using deprecated macro US_IMR_TIMEOUT_Pos") 8 /**< (US_IMR) Time-out Interrupt Mask Position */ +#define US_IMR_TIMEOUT DEPRECATED(US_IMR_TIMEOUT, "Using deprecated macro US_IMR_TIMEOUT") US_IMR_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_TIMEOUT_Msk instead */ +#define US_MR_CHMODE_Msk DEPRECATED(US_MR_CHMODE_Msk, "Using deprecated macro US_MR_CHMODE_Msk") (_U_(0x3) << US_MR_CHMODE_Pos) /**< (US_MR) Channel Mode Mask */ +#define US_MR_CHMODE_Pos DEPRECATED(US_MR_CHMODE_Pos, "Using deprecated macro US_MR_CHMODE_Pos") 14 /**< (US_MR) Channel Mode Position */ +#define US_MR_CHMODE(value) DEPRECATED(US_MR_CHMODE, "Using deprecated macro US_MR_CHMODE") (US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)) +#define US_MR_DSNACK_Msk DEPRECATED(US_MR_DSNACK_Msk, "Using deprecated macro US_MR_DSNACK_Msk") (_U_(0x1) << US_MR_DSNACK_Pos) /**< (US_MR) Disable Successive NACK Mask */ +#define US_MR_DSNACK_Pos DEPRECATED(US_MR_DSNACK_Pos, "Using deprecated macro US_MR_DSNACK_Pos") 21 /**< (US_MR) Disable Successive NACK Position */ +#define US_MR_DSNACK DEPRECATED(US_MR_DSNACK, "Using deprecated macro US_MR_DSNACK") US_MR_DSNACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_DSNACK_Msk instead */ +#define US_MR_FILTER_Msk DEPRECATED(US_MR_FILTER_Msk, "Using deprecated macro US_MR_FILTER_Msk") (_U_(0x1) << US_MR_FILTER_Pos) /**< (US_MR) Receive Line Filter Mask */ +#define US_MR_FILTER_Pos DEPRECATED(US_MR_FILTER_Pos, "Using deprecated macro US_MR_FILTER_Pos") 28 /**< (US_MR) Receive Line Filter Position */ +#define US_MR_FILTER DEPRECATED(US_MR_FILTER, "Using deprecated macro US_MR_FILTER") US_MR_FILTER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_FILTER_Msk instead */ +#define US_MR_INACK_Msk DEPRECATED(US_MR_INACK_Msk, "Using deprecated macro US_MR_INACK_Msk") (_U_(0x1) << US_MR_INACK_Pos) /**< (US_MR) Inhibit Non Acknowledge Mask */ +#define US_MR_INACK_Pos DEPRECATED(US_MR_INACK_Pos, "Using deprecated macro US_MR_INACK_Pos") 20 /**< (US_MR) Inhibit Non Acknowledge Position */ +#define US_MR_INACK DEPRECATED(US_MR_INACK, "Using deprecated macro US_MR_INACK") US_MR_INACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_INACK_Msk instead */ +#define US_MR_INVDATA_Msk DEPRECATED(US_MR_INVDATA_Msk, "Using deprecated macro US_MR_INVDATA_Msk") (_U_(0x1) << US_MR_INVDATA_Pos) /**< (US_MR) Inverted Data Mask */ +#define US_MR_INVDATA_Pos DEPRECATED(US_MR_INVDATA_Pos, "Using deprecated macro US_MR_INVDATA_Pos") 23 /**< (US_MR) Inverted Data Position */ +#define US_MR_INVDATA DEPRECATED(US_MR_INVDATA, "Using deprecated macro US_MR_INVDATA") US_MR_INVDATA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_INVDATA_Msk instead */ +#define US_MR_MAN_Msk DEPRECATED(US_MR_MAN_Msk, "Using deprecated macro US_MR_MAN_Msk") (_U_(0x1) << US_MR_MAN_Pos) /**< (US_MR) Manchester Encoder/Decoder Enable Mask */ +#define US_MR_MAN_Pos DEPRECATED(US_MR_MAN_Pos, "Using deprecated macro US_MR_MAN_Pos") 29 /**< (US_MR) Manchester Encoder/Decoder Enable Position */ +#define US_MR_MAN DEPRECATED(US_MR_MAN, "Using deprecated macro US_MR_MAN") US_MR_MAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_MAN_Msk instead */ +#define US_MR_MAX_ITERATION_Msk DEPRECATED(US_MR_MAX_ITERATION_Msk, "Using deprecated macro US_MR_MAX_ITERATION_Msk") (_U_(0x7) << US_MR_MAX_ITERATION_Pos) /**< (US_MR) Maximum Number of Automatic Iteration Mask */ +#define US_MR_MAX_ITERATION_Pos DEPRECATED(US_MR_MAX_ITERATION_Pos, "Using deprecated macro US_MR_MAX_ITERATION_Pos") 24 /**< (US_MR) Maximum Number of Automatic Iteration Position */ +#define US_MR_MAX_ITERATION(value) DEPRECATED(US_MR_MAX_ITERATION, "Using deprecated macro US_MR_MAX_ITERATION") (US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)) +#define US_MR_MODE9_Msk DEPRECATED(US_MR_MODE9_Msk, "Using deprecated macro US_MR_MODE9_Msk") (_U_(0x1) << US_MR_MODE9_Pos) /**< (US_MR) 9-bit Character Length Mask */ +#define US_MR_MODE9_Pos DEPRECATED(US_MR_MODE9_Pos, "Using deprecated macro US_MR_MODE9_Pos") 17 /**< (US_MR) 9-bit Character Length Position */ +#define US_MR_MODE9 DEPRECATED(US_MR_MODE9, "Using deprecated macro US_MR_MODE9") US_MR_MODE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_MODE9_Msk instead */ +#define US_MR_MODSYNC_Msk DEPRECATED(US_MR_MODSYNC_Msk, "Using deprecated macro US_MR_MODSYNC_Msk") (_U_(0x1) << US_MR_MODSYNC_Pos) /**< (US_MR) Manchester Synchronization Mode Mask */ +#define US_MR_MODSYNC_Pos DEPRECATED(US_MR_MODSYNC_Pos, "Using deprecated macro US_MR_MODSYNC_Pos") 30 /**< (US_MR) Manchester Synchronization Mode Position */ +#define US_MR_MODSYNC DEPRECATED(US_MR_MODSYNC, "Using deprecated macro US_MR_MODSYNC") US_MR_MODSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_MODSYNC_Msk instead */ +#define US_MR_MSBF_Msk DEPRECATED(US_MR_MSBF_Msk, "Using deprecated macro US_MR_MSBF_Msk") (_U_(0x1) << US_MR_MSBF_Pos) /**< (US_MR) Bit Order Mask */ +#define US_MR_MSBF_Pos DEPRECATED(US_MR_MSBF_Pos, "Using deprecated macro US_MR_MSBF_Pos") 16 /**< (US_MR) Bit Order Position */ +#define US_MR_MSBF DEPRECATED(US_MR_MSBF, "Using deprecated macro US_MR_MSBF") US_MR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_MSBF_Msk instead */ +#define US_MR_NBSTOP_Msk DEPRECATED(US_MR_NBSTOP_Msk, "Using deprecated macro US_MR_NBSTOP_Msk") (_U_(0x3) << US_MR_NBSTOP_Pos) /**< (US_MR) Number of Stop Bits Mask */ +#define US_MR_NBSTOP_Pos DEPRECATED(US_MR_NBSTOP_Pos, "Using deprecated macro US_MR_NBSTOP_Pos") 12 /**< (US_MR) Number of Stop Bits Position */ +#define US_MR_NBSTOP(value) DEPRECATED(US_MR_NBSTOP, "Using deprecated macro US_MR_NBSTOP") (US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)) +#define US_MR_ONEBIT_Msk DEPRECATED(US_MR_ONEBIT_Msk, "Using deprecated macro US_MR_ONEBIT_Msk") (_U_(0x1) << US_MR_ONEBIT_Pos) /**< (US_MR) Start Frame Delimiter Selector Mask */ +#define US_MR_ONEBIT_Pos DEPRECATED(US_MR_ONEBIT_Pos, "Using deprecated macro US_MR_ONEBIT_Pos") 31 /**< (US_MR) Start Frame Delimiter Selector Position */ +#define US_MR_ONEBIT DEPRECATED(US_MR_ONEBIT, "Using deprecated macro US_MR_ONEBIT") US_MR_ONEBIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_ONEBIT_Msk instead */ +#define US_MR_OVER_Msk DEPRECATED(US_MR_OVER_Msk, "Using deprecated macro US_MR_OVER_Msk") (_U_(0x1) << US_MR_OVER_Pos) /**< (US_MR) Oversampling Mode Mask */ +#define US_MR_OVER_Pos DEPRECATED(US_MR_OVER_Pos, "Using deprecated macro US_MR_OVER_Pos") 19 /**< (US_MR) Oversampling Mode Position */ +#define US_MR_OVER DEPRECATED(US_MR_OVER, "Using deprecated macro US_MR_OVER") US_MR_OVER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_OVER_Msk instead */ +#define US_MR_PAR_Msk DEPRECATED(US_MR_PAR_Msk, "Using deprecated macro US_MR_PAR_Msk") (_U_(0x7) << US_MR_PAR_Pos) /**< (US_MR) Parity Type Mask */ +#define US_MR_PAR_Pos DEPRECATED(US_MR_PAR_Pos, "Using deprecated macro US_MR_PAR_Pos") 9 /**< (US_MR) Parity Type Position */ +#define US_MR_PAR(value) DEPRECATED(US_MR_PAR, "Using deprecated macro US_MR_PAR") (US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)) +#define US_MR_SYNC_Msk DEPRECATED(US_MR_SYNC_Msk, "Using deprecated macro US_MR_SYNC_Msk") (_U_(0x1) << US_MR_SYNC_Pos) /**< (US_MR) Synchronous Mode Select Mask */ +#define US_MR_SYNC_Pos DEPRECATED(US_MR_SYNC_Pos, "Using deprecated macro US_MR_SYNC_Pos") 8 /**< (US_MR) Synchronous Mode Select Position */ +#define US_MR_SYNC DEPRECATED(US_MR_SYNC, "Using deprecated macro US_MR_SYNC") US_MR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_SYNC_Msk instead */ +#define US_MR_VAR_SYNC_Msk DEPRECATED(US_MR_VAR_SYNC_Msk, "Using deprecated macro US_MR_VAR_SYNC_Msk") (_U_(0x1) << US_MR_VAR_SYNC_Pos) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Mask */ +#define US_MR_VAR_SYNC_Pos DEPRECATED(US_MR_VAR_SYNC_Pos, "Using deprecated macro US_MR_VAR_SYNC_Pos") 22 /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Position */ +#define US_MR_VAR_SYNC DEPRECATED(US_MR_VAR_SYNC, "Using deprecated macro US_MR_VAR_SYNC") US_MR_VAR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_VAR_SYNC_Msk instead */ +#define US_TTGR_TG_Msk DEPRECATED(US_TTGR_TG_Msk, "Using deprecated macro US_TTGR_TG_Msk") (_U_(0xFF) << US_TTGR_TG_Pos) /**< (US_TTGR) Timeguard Value Mask */ +#define US_TTGR_TG_Pos DEPRECATED(US_TTGR_TG_Pos, "Using deprecated macro US_TTGR_TG_Pos") 0 /**< (US_TTGR) Timeguard Value Position */ +#define US_TTGR_TG(value) DEPRECATED(US_TTGR_TG, "Using deprecated macro US_TTGR_TG") (US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)) + +#endif diff --git a/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usbhs.h b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usbhs.h new file mode 100644 index 0000000000..172c804506 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/deprecated/usbhs.h @@ -0,0 +1,184 @@ +/** + * \file + * \brief This file is for deprecated macro constants + * + * Used to mark macro constants as deprecate. + * Uses a macro 'DEPRECTAED' to give warnings during compilation (GCC >= 4.8) + * + * \remark To use, add defines and put a DEPRECATED statement between the macro name and the value + * + * \note This file is manually maintained + */ + +#ifndef _SAME70_USBHS_COMPONENT_DEPRECATED_H_ +#define _SAME70_USBHS_COMPONENT_DEPRECATED_H_ + +#ifndef DEPRECATED +#define _DEP_STRING(X) #X + +/** \hideinitializer + * \brief Macro deprecation mark + * + * Putting this in a macro definition will emit deprecation warning when given + * macro is used (GCC 4.8) + * + * \code{.c} + * #define OLD_MACRO DEPRECATED(OLD_MACRO, "deprecated ") + * \endcode + * + * \warning Using these macros in #if statements will not work + */ +#if defined(__GNUC__) && __GNUC__*100 + __GNUC_MINOR__ >= 408 +#define DEPRECATED(macro, message) _Pragma (_DEP_STRING(GCC warning message)) +#else +#define DEPRECATED(macro, message) +#endif +#endif + +/* deprecated defines added below here */ +#define USBHS_DEVEPTICR_NAKINIC_Msk DEPRECATED(USBHS_DEVEPTICR_NAKINIC_Msk, "Using deprecated macro USBHS_DEVEPTICR_NAKINIC_Msk") (_U_(0x1) << USBHS_DEVEPTICR_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_NAKINIC_Pos DEPRECATED(USBHS_DEVEPTICR_NAKINIC_Pos, "Using deprecated macro USBHS_DEVEPTICR_NAKINIC_Pos") 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_NAKINIC DEPRECATED(USBHS_DEVEPTICR_NAKINIC, "Using deprecated macro USBHS_DEVEPTICR_NAKINIC") USBHS_DEVEPTICR_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_NAKINIC_Msk instead */ +#define USBHS_DEVEPTICR_NAKOUTIC_Msk DEPRECATED(USBHS_DEVEPTICR_NAKOUTIC_Msk, "Using deprecated macro USBHS_DEVEPTICR_NAKOUTIC_Msk") (_U_(0x1) << USBHS_DEVEPTICR_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_NAKOUTIC_Pos DEPRECATED(USBHS_DEVEPTICR_NAKOUTIC_Pos, "Using deprecated macro USBHS_DEVEPTICR_NAKOUTIC_Pos") 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_NAKOUTIC DEPRECATED(USBHS_DEVEPTICR_NAKOUTIC, "Using deprecated macro USBHS_DEVEPTICR_NAKOUTIC") USBHS_DEVEPTICR_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_NAKOUTIC_Msk instead */ +#define USBHS_DEVEPTICR_RXSTPIC_Msk DEPRECATED(USBHS_DEVEPTICR_RXSTPIC_Msk, "Using deprecated macro USBHS_DEVEPTICR_RXSTPIC_Msk") (_U_(0x1) << USBHS_DEVEPTICR_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_RXSTPIC_Pos DEPRECATED(USBHS_DEVEPTICR_RXSTPIC_Pos, "Using deprecated macro USBHS_DEVEPTICR_RXSTPIC_Pos") 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_RXSTPIC DEPRECATED(USBHS_DEVEPTICR_RXSTPIC, "Using deprecated macro USBHS_DEVEPTICR_RXSTPIC") USBHS_DEVEPTICR_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_RXSTPIC_Msk instead */ +#define USBHS_DEVEPTICR_STALLEDIC_Msk DEPRECATED(USBHS_DEVEPTICR_STALLEDIC_Msk, "Using deprecated macro USBHS_DEVEPTICR_STALLEDIC_Msk") (_U_(0x1) << USBHS_DEVEPTICR_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_STALLEDIC_Pos DEPRECATED(USBHS_DEVEPTICR_STALLEDIC_Pos, "Using deprecated macro USBHS_DEVEPTICR_STALLEDIC_Pos") 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_STALLEDIC DEPRECATED(USBHS_DEVEPTICR_STALLEDIC, "Using deprecated macro USBHS_DEVEPTICR_STALLEDIC") USBHS_DEVEPTICR_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_STALLEDIC_Msk instead */ +#define USBHS_DEVEPTIDR_NAKINEC_Msk DEPRECATED(USBHS_DEVEPTIDR_NAKINEC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_NAKINEC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NAKINEC_Pos DEPRECATED(USBHS_DEVEPTIDR_NAKINEC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_NAKINEC_Pos") 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NAKINEC DEPRECATED(USBHS_DEVEPTIDR_NAKINEC, "Using deprecated macro USBHS_DEVEPTIDR_NAKINEC") USBHS_DEVEPTIDR_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_NAKINEC_Msk instead */ +#define USBHS_DEVEPTIDR_NAKOUTEC_Msk DEPRECATED(USBHS_DEVEPTIDR_NAKOUTEC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_NAKOUTEC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NAKOUTEC_Pos DEPRECATED(USBHS_DEVEPTIDR_NAKOUTEC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_NAKOUTEC_Pos") 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NAKOUTEC DEPRECATED(USBHS_DEVEPTIDR_NAKOUTEC, "Using deprecated macro USBHS_DEVEPTIDR_NAKOUTEC") USBHS_DEVEPTIDR_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_NAKOUTEC_Msk instead */ +#define USBHS_DEVEPTIDR_NYETDISC_Msk DEPRECATED(USBHS_DEVEPTIDR_NYETDISC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_NYETDISC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_NYETDISC_Pos DEPRECATED(USBHS_DEVEPTIDR_NYETDISC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_NYETDISC_Pos") 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_NYETDISC DEPRECATED(USBHS_DEVEPTIDR_NYETDISC, "Using deprecated macro USBHS_DEVEPTIDR_NYETDISC") USBHS_DEVEPTIDR_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_NYETDISC_Msk instead */ +#define USBHS_DEVEPTIDR_RXSTPEC_Msk DEPRECATED(USBHS_DEVEPTIDR_RXSTPEC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_RXSTPEC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_RXSTPEC_Pos DEPRECATED(USBHS_DEVEPTIDR_RXSTPEC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_RXSTPEC_Pos") 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_RXSTPEC DEPRECATED(USBHS_DEVEPTIDR_RXSTPEC, "Using deprecated macro USBHS_DEVEPTIDR_RXSTPEC") USBHS_DEVEPTIDR_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_RXSTPEC_Msk instead */ +#define USBHS_DEVEPTIDR_STALLEDEC_Msk DEPRECATED(USBHS_DEVEPTIDR_STALLEDEC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_STALLEDEC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_STALLEDEC_Pos DEPRECATED(USBHS_DEVEPTIDR_STALLEDEC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_STALLEDEC_Pos") 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_STALLEDEC DEPRECATED(USBHS_DEVEPTIDR_STALLEDEC, "Using deprecated macro USBHS_DEVEPTIDR_STALLEDEC") USBHS_DEVEPTIDR_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_STALLEDEC_Msk instead */ +#define USBHS_DEVEPTIDR_STALLRQC_Msk DEPRECATED(USBHS_DEVEPTIDR_STALLRQC_Msk, "Using deprecated macro USBHS_DEVEPTIDR_STALLRQC_Msk") (_U_(0x1) << USBHS_DEVEPTIDR_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_STALLRQC_Pos DEPRECATED(USBHS_DEVEPTIDR_STALLRQC_Pos, "Using deprecated macro USBHS_DEVEPTIDR_STALLRQC_Pos") 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_STALLRQC DEPRECATED(USBHS_DEVEPTIDR_STALLRQC, "Using deprecated macro USBHS_DEVEPTIDR_STALLRQC") USBHS_DEVEPTIDR_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_STALLRQC_Msk instead */ +#define USBHS_DEVEPTIER_NAKINES_Msk DEPRECATED(USBHS_DEVEPTIER_NAKINES_Msk, "Using deprecated macro USBHS_DEVEPTIER_NAKINES_Msk") (_U_(0x1) << USBHS_DEVEPTIER_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NAKINES_Pos DEPRECATED(USBHS_DEVEPTIER_NAKINES_Pos, "Using deprecated macro USBHS_DEVEPTIER_NAKINES_Pos") 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NAKINES DEPRECATED(USBHS_DEVEPTIER_NAKINES, "Using deprecated macro USBHS_DEVEPTIER_NAKINES") USBHS_DEVEPTIER_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_NAKINES_Msk instead */ +#define USBHS_DEVEPTIER_NAKOUTES_Msk DEPRECATED(USBHS_DEVEPTIER_NAKOUTES_Msk, "Using deprecated macro USBHS_DEVEPTIER_NAKOUTES_Msk") (_U_(0x1) << USBHS_DEVEPTIER_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NAKOUTES_Pos DEPRECATED(USBHS_DEVEPTIER_NAKOUTES_Pos, "Using deprecated macro USBHS_DEVEPTIER_NAKOUTES_Pos") 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NAKOUTES DEPRECATED(USBHS_DEVEPTIER_NAKOUTES, "Using deprecated macro USBHS_DEVEPTIER_NAKOUTES") USBHS_DEVEPTIER_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_NAKOUTES_Msk instead */ +#define USBHS_DEVEPTIER_NYETDISS_Msk DEPRECATED(USBHS_DEVEPTIER_NYETDISS_Msk, "Using deprecated macro USBHS_DEVEPTIER_NYETDISS_Msk") (_U_(0x1) << USBHS_DEVEPTIER_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_NYETDISS_Pos DEPRECATED(USBHS_DEVEPTIER_NYETDISS_Pos, "Using deprecated macro USBHS_DEVEPTIER_NYETDISS_Pos") 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_NYETDISS DEPRECATED(USBHS_DEVEPTIER_NYETDISS, "Using deprecated macro USBHS_DEVEPTIER_NYETDISS") USBHS_DEVEPTIER_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_NYETDISS_Msk instead */ +#define USBHS_DEVEPTIER_RXSTPES_Msk DEPRECATED(USBHS_DEVEPTIER_RXSTPES_Msk, "Using deprecated macro USBHS_DEVEPTIER_RXSTPES_Msk") (_U_(0x1) << USBHS_DEVEPTIER_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_RXSTPES_Pos DEPRECATED(USBHS_DEVEPTIER_RXSTPES_Pos, "Using deprecated macro USBHS_DEVEPTIER_RXSTPES_Pos") 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_RXSTPES DEPRECATED(USBHS_DEVEPTIER_RXSTPES, "Using deprecated macro USBHS_DEVEPTIER_RXSTPES") USBHS_DEVEPTIER_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_RXSTPES_Msk instead */ +#define USBHS_DEVEPTIER_STALLEDES_Msk DEPRECATED(USBHS_DEVEPTIER_STALLEDES_Msk, "Using deprecated macro USBHS_DEVEPTIER_STALLEDES_Msk") (_U_(0x1) << USBHS_DEVEPTIER_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_STALLEDES_Pos DEPRECATED(USBHS_DEVEPTIER_STALLEDES_Pos, "Using deprecated macro USBHS_DEVEPTIER_STALLEDES_Pos") 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_STALLEDES DEPRECATED(USBHS_DEVEPTIER_STALLEDES, "Using deprecated macro USBHS_DEVEPTIER_STALLEDES") USBHS_DEVEPTIER_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_STALLEDES_Msk instead */ +#define USBHS_DEVEPTIER_STALLRQS_Msk DEPRECATED(USBHS_DEVEPTIER_STALLRQS_Msk, "Using deprecated macro USBHS_DEVEPTIER_STALLRQS_Msk") (_U_(0x1) << USBHS_DEVEPTIER_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_STALLRQS_Pos DEPRECATED(USBHS_DEVEPTIER_STALLRQS_Pos, "Using deprecated macro USBHS_DEVEPTIER_STALLRQS_Pos") 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_STALLRQS DEPRECATED(USBHS_DEVEPTIER_STALLRQS, "Using deprecated macro USBHS_DEVEPTIER_STALLRQS") USBHS_DEVEPTIER_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_STALLRQS_Msk instead */ +#define USBHS_DEVEPTIFR_NAKINIS_Msk DEPRECATED(USBHS_DEVEPTIFR_NAKINIS_Msk, "Using deprecated macro USBHS_DEVEPTIFR_NAKINIS_Msk") (_U_(0x1) << USBHS_DEVEPTIFR_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NAKINIS_Pos DEPRECATED(USBHS_DEVEPTIFR_NAKINIS_Pos, "Using deprecated macro USBHS_DEVEPTIFR_NAKINIS_Pos") 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NAKINIS DEPRECATED(USBHS_DEVEPTIFR_NAKINIS, "Using deprecated macro USBHS_DEVEPTIFR_NAKINIS") USBHS_DEVEPTIFR_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_NAKINIS_Msk instead */ +#define USBHS_DEVEPTIFR_NAKOUTIS_Msk DEPRECATED(USBHS_DEVEPTIFR_NAKOUTIS_Msk, "Using deprecated macro USBHS_DEVEPTIFR_NAKOUTIS_Msk") (_U_(0x1) << USBHS_DEVEPTIFR_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NAKOUTIS_Pos DEPRECATED(USBHS_DEVEPTIFR_NAKOUTIS_Pos, "Using deprecated macro USBHS_DEVEPTIFR_NAKOUTIS_Pos") 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NAKOUTIS DEPRECATED(USBHS_DEVEPTIFR_NAKOUTIS, "Using deprecated macro USBHS_DEVEPTIFR_NAKOUTIS") USBHS_DEVEPTIFR_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_NAKOUTIS_Msk instead */ +#define USBHS_DEVEPTIFR_RXSTPIS_Msk DEPRECATED(USBHS_DEVEPTIFR_RXSTPIS_Msk, "Using deprecated macro USBHS_DEVEPTIFR_RXSTPIS_Msk") (_U_(0x1) << USBHS_DEVEPTIFR_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_RXSTPIS_Pos DEPRECATED(USBHS_DEVEPTIFR_RXSTPIS_Pos, "Using deprecated macro USBHS_DEVEPTIFR_RXSTPIS_Pos") 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_RXSTPIS DEPRECATED(USBHS_DEVEPTIFR_RXSTPIS, "Using deprecated macro USBHS_DEVEPTIFR_RXSTPIS") USBHS_DEVEPTIFR_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_RXSTPIS_Msk instead */ +#define USBHS_DEVEPTIFR_STALLEDIS_Msk DEPRECATED(USBHS_DEVEPTIFR_STALLEDIS_Msk, "Using deprecated macro USBHS_DEVEPTIFR_STALLEDIS_Msk") (_U_(0x1) << USBHS_DEVEPTIFR_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_STALLEDIS_Pos DEPRECATED(USBHS_DEVEPTIFR_STALLEDIS_Pos, "Using deprecated macro USBHS_DEVEPTIFR_STALLEDIS_Pos") 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_STALLEDIS DEPRECATED(USBHS_DEVEPTIFR_STALLEDIS, "Using deprecated macro USBHS_DEVEPTIFR_STALLEDIS") USBHS_DEVEPTIFR_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_STALLEDIS_Msk instead */ +#define USBHS_DEVEPTIMR_NAKINE_Msk DEPRECATED(USBHS_DEVEPTIMR_NAKINE_Msk, "Using deprecated macro USBHS_DEVEPTIMR_NAKINE_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_NAKINE_Pos DEPRECATED(USBHS_DEVEPTIMR_NAKINE_Pos, "Using deprecated macro USBHS_DEVEPTIMR_NAKINE_Pos") 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_NAKINE DEPRECATED(USBHS_DEVEPTIMR_NAKINE, "Using deprecated macro USBHS_DEVEPTIMR_NAKINE") USBHS_DEVEPTIMR_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_NAKINE_Msk instead */ +#define USBHS_DEVEPTIMR_NAKOUTE_Msk DEPRECATED(USBHS_DEVEPTIMR_NAKOUTE_Msk, "Using deprecated macro USBHS_DEVEPTIMR_NAKOUTE_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_NAKOUTE_Pos DEPRECATED(USBHS_DEVEPTIMR_NAKOUTE_Pos, "Using deprecated macro USBHS_DEVEPTIMR_NAKOUTE_Pos") 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_NAKOUTE DEPRECATED(USBHS_DEVEPTIMR_NAKOUTE, "Using deprecated macro USBHS_DEVEPTIMR_NAKOUTE") USBHS_DEVEPTIMR_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_NAKOUTE_Msk instead */ +#define USBHS_DEVEPTIMR_NYETDIS_Msk DEPRECATED(USBHS_DEVEPTIMR_NYETDIS_Msk, "Using deprecated macro USBHS_DEVEPTIMR_NYETDIS_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_NYETDIS_Pos DEPRECATED(USBHS_DEVEPTIMR_NYETDIS_Pos, "Using deprecated macro USBHS_DEVEPTIMR_NYETDIS_Pos") 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_NYETDIS DEPRECATED(USBHS_DEVEPTIMR_NYETDIS, "Using deprecated macro USBHS_DEVEPTIMR_NYETDIS") USBHS_DEVEPTIMR_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_NYETDIS_Msk instead */ +#define USBHS_DEVEPTIMR_RXSTPE_Msk DEPRECATED(USBHS_DEVEPTIMR_RXSTPE_Msk, "Using deprecated macro USBHS_DEVEPTIMR_RXSTPE_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_RXSTPE_Pos DEPRECATED(USBHS_DEVEPTIMR_RXSTPE_Pos, "Using deprecated macro USBHS_DEVEPTIMR_RXSTPE_Pos") 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_RXSTPE DEPRECATED(USBHS_DEVEPTIMR_RXSTPE, "Using deprecated macro USBHS_DEVEPTIMR_RXSTPE") USBHS_DEVEPTIMR_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_RXSTPE_Msk instead */ +#define USBHS_DEVEPTIMR_STALLEDE_Msk DEPRECATED(USBHS_DEVEPTIMR_STALLEDE_Msk, "Using deprecated macro USBHS_DEVEPTIMR_STALLEDE_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_STALLEDE_Pos DEPRECATED(USBHS_DEVEPTIMR_STALLEDE_Pos, "Using deprecated macro USBHS_DEVEPTIMR_STALLEDE_Pos") 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_STALLEDE DEPRECATED(USBHS_DEVEPTIMR_STALLEDE, "Using deprecated macro USBHS_DEVEPTIMR_STALLEDE") USBHS_DEVEPTIMR_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_STALLEDE_Msk instead */ +#define USBHS_DEVEPTIMR_STALLRQ_Msk DEPRECATED(USBHS_DEVEPTIMR_STALLRQ_Msk, "Using deprecated macro USBHS_DEVEPTIMR_STALLRQ_Msk") (_U_(0x1) << USBHS_DEVEPTIMR_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_STALLRQ_Pos DEPRECATED(USBHS_DEVEPTIMR_STALLRQ_Pos, "Using deprecated macro USBHS_DEVEPTIMR_STALLRQ_Pos") 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_STALLRQ DEPRECATED(USBHS_DEVEPTIMR_STALLRQ, "Using deprecated macro USBHS_DEVEPTIMR_STALLRQ") USBHS_DEVEPTIMR_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_STALLRQ_Msk instead */ +#define USBHS_DEVEPTISR_CTRLDIR_Msk DEPRECATED(USBHS_DEVEPTISR_CTRLDIR_Msk, "Using deprecated macro USBHS_DEVEPTISR_CTRLDIR_Msk") (_U_(0x1) << USBHS_DEVEPTISR_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_CTRLDIR_Pos DEPRECATED(USBHS_DEVEPTISR_CTRLDIR_Pos, "Using deprecated macro USBHS_DEVEPTISR_CTRLDIR_Pos") 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_CTRLDIR DEPRECATED(USBHS_DEVEPTISR_CTRLDIR, "Using deprecated macro USBHS_DEVEPTISR_CTRLDIR") USBHS_DEVEPTISR_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRLDIR_Msk instead */ +#define USBHS_DEVEPTISR_NAKINI_Msk DEPRECATED(USBHS_DEVEPTISR_NAKINI_Msk, "Using deprecated macro USBHS_DEVEPTISR_NAKINI_Msk") (_U_(0x1) << USBHS_DEVEPTISR_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_NAKINI_Pos DEPRECATED(USBHS_DEVEPTISR_NAKINI_Pos, "Using deprecated macro USBHS_DEVEPTISR_NAKINI_Pos") 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_NAKINI DEPRECATED(USBHS_DEVEPTISR_NAKINI, "Using deprecated macro USBHS_DEVEPTISR_NAKINI") USBHS_DEVEPTISR_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_NAKINI_Msk instead */ +#define USBHS_DEVEPTISR_NAKOUTI_Msk DEPRECATED(USBHS_DEVEPTISR_NAKOUTI_Msk, "Using deprecated macro USBHS_DEVEPTISR_NAKOUTI_Msk") (_U_(0x1) << USBHS_DEVEPTISR_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_NAKOUTI_Pos DEPRECATED(USBHS_DEVEPTISR_NAKOUTI_Pos, "Using deprecated macro USBHS_DEVEPTISR_NAKOUTI_Pos") 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_NAKOUTI DEPRECATED(USBHS_DEVEPTISR_NAKOUTI, "Using deprecated macro USBHS_DEVEPTISR_NAKOUTI") USBHS_DEVEPTISR_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_NAKOUTI_Msk instead */ +#define USBHS_DEVEPTISR_RXSTPI_Msk DEPRECATED(USBHS_DEVEPTISR_RXSTPI_Msk, "Using deprecated macro USBHS_DEVEPTISR_RXSTPI_Msk") (_U_(0x1) << USBHS_DEVEPTISR_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_RXSTPI_Pos DEPRECATED(USBHS_DEVEPTISR_RXSTPI_Pos, "Using deprecated macro USBHS_DEVEPTISR_RXSTPI_Pos") 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_RXSTPI DEPRECATED(USBHS_DEVEPTISR_RXSTPI, "Using deprecated macro USBHS_DEVEPTISR_RXSTPI") USBHS_DEVEPTISR_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_RXSTPI_Msk instead */ +#define USBHS_DEVEPTISR_STALLEDI_Msk DEPRECATED(USBHS_DEVEPTISR_STALLEDI_Msk, "Using deprecated macro USBHS_DEVEPTISR_STALLEDI_Msk") (_U_(0x1) << USBHS_DEVEPTISR_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_STALLEDI_Pos DEPRECATED(USBHS_DEVEPTISR_STALLEDI_Pos, "Using deprecated macro USBHS_DEVEPTISR_STALLEDI_Pos") 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_STALLEDI DEPRECATED(USBHS_DEVEPTISR_STALLEDI, "Using deprecated macro USBHS_DEVEPTISR_STALLEDI") USBHS_DEVEPTISR_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_STALLEDI_Msk instead */ +#define USBHS_HSTIDR_DMA_7_Msk DEPRECATED(USBHS_HSTIDR_DMA_7_Msk, "Using deprecated macro USBHS_HSTIDR_DMA_7_Msk") (_U_(0x1) << USBHS_HSTIDR_DMA_7_Pos) /**< (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_7_Pos DEPRECATED(USBHS_HSTIDR_DMA_7_Pos, "Using deprecated macro USBHS_HSTIDR_DMA_7_Pos") 31 /**< (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_7 DEPRECATED(USBHS_HSTIDR_DMA_7, "Using deprecated macro USBHS_HSTIDR_DMA_7") USBHS_HSTIDR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_7_Msk instead */ +#define USBHS_HSTIER_DMA_7_Msk DEPRECATED(USBHS_HSTIER_DMA_7_Msk, "Using deprecated macro USBHS_HSTIER_DMA_7_Msk") (_U_(0x1) << USBHS_HSTIER_DMA_7_Pos) /**< (USBHS_HSTIER) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_7_Pos DEPRECATED(USBHS_HSTIER_DMA_7_Pos, "Using deprecated macro USBHS_HSTIER_DMA_7_Pos") 31 /**< (USBHS_HSTIER) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_7 DEPRECATED(USBHS_HSTIER_DMA_7, "Using deprecated macro USBHS_HSTIER_DMA_7") USBHS_HSTIER_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_7_Msk instead */ +#define USBHS_HSTIFR_DMA_7_Msk DEPRECATED(USBHS_HSTIFR_DMA_7_Msk, "Using deprecated macro USBHS_HSTIFR_DMA_7_Msk") (_U_(0x1) << USBHS_HSTIFR_DMA_7_Pos) /**< (USBHS_HSTIFR) DMA Channel 7 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_7_Pos DEPRECATED(USBHS_HSTIFR_DMA_7_Pos, "Using deprecated macro USBHS_HSTIFR_DMA_7_Pos") 31 /**< (USBHS_HSTIFR) DMA Channel 7 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_7 DEPRECATED(USBHS_HSTIFR_DMA_7, "Using deprecated macro USBHS_HSTIFR_DMA_7") USBHS_HSTIFR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_7_Msk instead */ +#define USBHS_HSTIMR_DMA_7_Msk DEPRECATED(USBHS_HSTIMR_DMA_7_Msk, "Using deprecated macro USBHS_HSTIMR_DMA_7_Msk") (_U_(0x1) << USBHS_HSTIMR_DMA_7_Pos) /**< (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_7_Pos DEPRECATED(USBHS_HSTIMR_DMA_7_Pos, "Using deprecated macro USBHS_HSTIMR_DMA_7_Pos") 31 /**< (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_7 DEPRECATED(USBHS_HSTIMR_DMA_7, "Using deprecated macro USBHS_HSTIMR_DMA_7") USBHS_HSTIMR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_7_Msk instead */ +#define USBHS_HSTISR_DMA_7_Msk DEPRECATED(USBHS_HSTISR_DMA_7_Msk, "Using deprecated macro USBHS_HSTISR_DMA_7_Msk") (_U_(0x1) << USBHS_HSTISR_DMA_7_Pos) /**< (USBHS_HSTISR) DMA Channel 7 Interrupt Mask */ +#define USBHS_HSTISR_DMA_7_Pos DEPRECATED(USBHS_HSTISR_DMA_7_Pos, "Using deprecated macro USBHS_HSTISR_DMA_7_Pos") 31 /**< (USBHS_HSTISR) DMA Channel 7 Interrupt Position */ +#define USBHS_HSTISR_DMA_7 DEPRECATED(USBHS_HSTISR_DMA_7, "Using deprecated macro USBHS_HSTISR_DMA_7") USBHS_HSTISR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_7_Msk instead */ +#define USBHS_HSTPIPICR_RXSTALLDIC_Msk DEPRECATED(USBHS_HSTPIPICR_RXSTALLDIC_Msk, "Using deprecated macro USBHS_HSTPIPICR_RXSTALLDIC_Msk") (_U_(0x1) << USBHS_HSTPIPICR_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_RXSTALLDIC_Pos DEPRECATED(USBHS_HSTPIPICR_RXSTALLDIC_Pos, "Using deprecated macro USBHS_HSTPIPICR_RXSTALLDIC_Pos") 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_RXSTALLDIC DEPRECATED(USBHS_HSTPIPICR_RXSTALLDIC, "Using deprecated macro USBHS_HSTPIPICR_RXSTALLDIC") USBHS_HSTPIPICR_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_RXSTALLDIC_Msk instead */ +#define USBHS_HSTPIPICR_TXSTPIC_Msk DEPRECATED(USBHS_HSTPIPICR_TXSTPIC_Msk, "Using deprecated macro USBHS_HSTPIPICR_TXSTPIC_Msk") (_U_(0x1) << USBHS_HSTPIPICR_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_TXSTPIC_Pos DEPRECATED(USBHS_HSTPIPICR_TXSTPIC_Pos, "Using deprecated macro USBHS_HSTPIPICR_TXSTPIC_Pos") 2 /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_TXSTPIC DEPRECATED(USBHS_HSTPIPICR_TXSTPIC, "Using deprecated macro USBHS_HSTPIPICR_TXSTPIC") USBHS_HSTPIPICR_TXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_TXSTPIC_Msk instead */ +#define USBHS_HSTPIPIDR_RXSTALLDEC_Msk DEPRECATED(USBHS_HSTPIPIDR_RXSTALLDEC_Msk, "Using deprecated macro USBHS_HSTPIPIDR_RXSTALLDEC_Msk") (_U_(0x1) << USBHS_HSTPIPIDR_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_RXSTALLDEC_Pos DEPRECATED(USBHS_HSTPIPIDR_RXSTALLDEC_Pos, "Using deprecated macro USBHS_HSTPIPIDR_RXSTALLDEC_Pos") 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_RXSTALLDEC DEPRECATED(USBHS_HSTPIPIDR_RXSTALLDEC, "Using deprecated macro USBHS_HSTPIPIDR_RXSTALLDEC") USBHS_HSTPIPIDR_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_RXSTALLDEC_Msk instead */ +#define USBHS_HSTPIPIDR_TXSTPEC_Msk DEPRECATED(USBHS_HSTPIPIDR_TXSTPEC_Msk, "Using deprecated macro USBHS_HSTPIPIDR_TXSTPEC_Msk") (_U_(0x1) << USBHS_HSTPIPIDR_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_TXSTPEC_Pos DEPRECATED(USBHS_HSTPIPIDR_TXSTPEC_Pos, "Using deprecated macro USBHS_HSTPIPIDR_TXSTPEC_Pos") 2 /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_TXSTPEC DEPRECATED(USBHS_HSTPIPIDR_TXSTPEC, "Using deprecated macro USBHS_HSTPIPIDR_TXSTPEC") USBHS_HSTPIPIDR_TXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_TXSTPEC_Msk instead */ +#define USBHS_HSTPIPIER_RXSTALLDES_Msk DEPRECATED(USBHS_HSTPIPIER_RXSTALLDES_Msk, "Using deprecated macro USBHS_HSTPIPIER_RXSTALLDES_Msk") (_U_(0x1) << USBHS_HSTPIPIER_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_RXSTALLDES_Pos DEPRECATED(USBHS_HSTPIPIER_RXSTALLDES_Pos, "Using deprecated macro USBHS_HSTPIPIER_RXSTALLDES_Pos") 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_RXSTALLDES DEPRECATED(USBHS_HSTPIPIER_RXSTALLDES, "Using deprecated macro USBHS_HSTPIPIER_RXSTALLDES") USBHS_HSTPIPIER_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_RXSTALLDES_Msk instead */ +#define USBHS_HSTPIPIER_TXSTPES_Msk DEPRECATED(USBHS_HSTPIPIER_TXSTPES_Msk, "Using deprecated macro USBHS_HSTPIPIER_TXSTPES_Msk") (_U_(0x1) << USBHS_HSTPIPIER_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_TXSTPES_Pos DEPRECATED(USBHS_HSTPIPIER_TXSTPES_Pos, "Using deprecated macro USBHS_HSTPIPIER_TXSTPES_Pos") 2 /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_TXSTPES DEPRECATED(USBHS_HSTPIPIER_TXSTPES, "Using deprecated macro USBHS_HSTPIPIER_TXSTPES") USBHS_HSTPIPIER_TXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_TXSTPES_Msk instead */ +#define USBHS_HSTPIPIFR_RXSTALLDIS_Msk DEPRECATED(USBHS_HSTPIPIFR_RXSTALLDIS_Msk, "Using deprecated macro USBHS_HSTPIPIFR_RXSTALLDIS_Msk") (_U_(0x1) << USBHS_HSTPIPIFR_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_RXSTALLDIS_Pos DEPRECATED(USBHS_HSTPIPIFR_RXSTALLDIS_Pos, "Using deprecated macro USBHS_HSTPIPIFR_RXSTALLDIS_Pos") 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_RXSTALLDIS DEPRECATED(USBHS_HSTPIPIFR_RXSTALLDIS, "Using deprecated macro USBHS_HSTPIPIFR_RXSTALLDIS") USBHS_HSTPIPIFR_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_RXSTALLDIS_Msk instead */ +#define USBHS_HSTPIPIFR_TXSTPIS_Msk DEPRECATED(USBHS_HSTPIPIFR_TXSTPIS_Msk, "Using deprecated macro USBHS_HSTPIPIFR_TXSTPIS_Msk") (_U_(0x1) << USBHS_HSTPIPIFR_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_TXSTPIS_Pos DEPRECATED(USBHS_HSTPIPIFR_TXSTPIS_Pos, "Using deprecated macro USBHS_HSTPIPIFR_TXSTPIS_Pos") 2 /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_TXSTPIS DEPRECATED(USBHS_HSTPIPIFR_TXSTPIS, "Using deprecated macro USBHS_HSTPIPIFR_TXSTPIS") USBHS_HSTPIPIFR_TXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_TXSTPIS_Msk instead */ +#define USBHS_HSTPIPIMR_RXSTALLDE_Msk DEPRECATED(USBHS_HSTPIPIMR_RXSTALLDE_Msk, "Using deprecated macro USBHS_HSTPIPIMR_RXSTALLDE_Msk") (_U_(0x1) << USBHS_HSTPIPIMR_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_RXSTALLDE_Pos DEPRECATED(USBHS_HSTPIPIMR_RXSTALLDE_Pos, "Using deprecated macro USBHS_HSTPIPIMR_RXSTALLDE_Pos") 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_RXSTALLDE DEPRECATED(USBHS_HSTPIPIMR_RXSTALLDE, "Using deprecated macro USBHS_HSTPIPIMR_RXSTALLDE") USBHS_HSTPIPIMR_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_RXSTALLDE_Msk instead */ +#define USBHS_HSTPIPIMR_TXSTPE_Msk DEPRECATED(USBHS_HSTPIPIMR_TXSTPE_Msk, "Using deprecated macro USBHS_HSTPIPIMR_TXSTPE_Msk") (_U_(0x1) << USBHS_HSTPIPIMR_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_TXSTPE_Pos DEPRECATED(USBHS_HSTPIPIMR_TXSTPE_Pos, "Using deprecated macro USBHS_HSTPIPIMR_TXSTPE_Pos") 2 /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_TXSTPE DEPRECATED(USBHS_HSTPIPIMR_TXSTPE, "Using deprecated macro USBHS_HSTPIPIMR_TXSTPE") USBHS_HSTPIPIMR_TXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_TXSTPE_Msk instead */ +#define USBHS_HSTPIPISR_RXSTALLDI_Msk DEPRECATED(USBHS_HSTPIPISR_RXSTALLDI_Msk, "Using deprecated macro USBHS_HSTPIPISR_RXSTALLDI_Msk") (_U_(0x1) << USBHS_HSTPIPISR_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_RXSTALLDI_Pos DEPRECATED(USBHS_HSTPIPISR_RXSTALLDI_Pos, "Using deprecated macro USBHS_HSTPIPISR_RXSTALLDI_Pos") 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_RXSTALLDI DEPRECATED(USBHS_HSTPIPISR_RXSTALLDI, "Using deprecated macro USBHS_HSTPIPISR_RXSTALLDI") USBHS_HSTPIPISR_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_RXSTALLDI_Msk instead */ +#define USBHS_HSTPIPISR_TXSTPI_Msk DEPRECATED(USBHS_HSTPIPISR_TXSTPI_Msk, "Using deprecated macro USBHS_HSTPIPISR_TXSTPI_Msk") (_U_(0x1) << USBHS_HSTPIPISR_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_TXSTPI_Pos DEPRECATED(USBHS_HSTPIPISR_TXSTPI_Pos, "Using deprecated macro USBHS_HSTPIPISR_TXSTPI_Pos") 2 /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_TXSTPI DEPRECATED(USBHS_HSTPIPISR_TXSTPI, "Using deprecated macro USBHS_HSTPIPISR_TXSTPI") USBHS_HSTPIPISR_TXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_TXSTPI_Msk instead */ + +#endif diff --git a/bsp/microchip/same70/bsp/same70b/include/component/efc.h b/bsp/microchip/same70/bsp/same70b/include/component/efc.h new file mode 100644 index 0000000000..b8c0fc0927 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/efc.h @@ -0,0 +1,288 @@ +/** + * \file + * + * \brief Component description for EFC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_EFC_COMPONENT_H_ +#define _SAME70_EFC_COMPONENT_H_ +#define _SAME70_EFC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Embedded Flash Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR EFC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define EFC_6450 /**< (EFC) Module ID */ +#define REV_EFC Y /**< (EFC) Module revision */ + +/* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FRDY:1; /**< bit: 0 Flash Ready Interrupt Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t FWS:4; /**< bit: 8..11 Flash Wait State */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t SCOD:1; /**< bit: 16 Sequential Code Optimization Disable */ + uint32_t :9; /**< bit: 17..25 Reserved */ + uint32_t CLOE:1; /**< bit: 26 Code Loop Optimization Enable */ + uint32_t :5; /**< bit: 27..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} EEFC_FMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EEFC_FMR_OFFSET (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */ + +#define EEFC_FMR_FRDY_Pos 0 /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */ +#define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */ +#define EEFC_FMR_FRDY EEFC_FMR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_FRDY_Msk instead */ +#define EEFC_FMR_FWS_Pos 8 /**< (EEFC_FMR) Flash Wait State Position */ +#define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */ +#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)) +#define EEFC_FMR_SCOD_Pos 16 /**< (EEFC_FMR) Sequential Code Optimization Disable Position */ +#define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */ +#define EEFC_FMR_SCOD EEFC_FMR_SCOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_SCOD_Msk instead */ +#define EEFC_FMR_CLOE_Pos 26 /**< (EEFC_FMR) Code Loop Optimization Enable Position */ +#define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */ +#define EEFC_FMR_CLOE EEFC_FMR_CLOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_CLOE_Msk instead */ +#define EEFC_FMR_MASK _U_(0x4010F01) /**< \deprecated (EEFC_FMR) Register MASK (Use EEFC_FMR_Msk instead) */ +#define EEFC_FMR_Msk _U_(0x4010F01) /**< (EEFC_FMR) Register Mask */ + + +/* -------- EEFC_FCR : (EFC Offset: 0x04) (/W 32) EEFC Flash Command Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FCMD:8; /**< bit: 0..7 Flash Command */ + uint32_t FARG:16; /**< bit: 8..23 Flash Command Argument */ + uint32_t FKEY:8; /**< bit: 24..31 Flash Writing Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} EEFC_FCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EEFC_FCR_OFFSET (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */ + +#define EEFC_FCR_FCMD_Pos 0 /**< (EEFC_FCR) Flash Command Position */ +#define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */ +#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)) +#define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */ +#define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */ +#define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */ +#define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */ +#define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */ +#define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */ +#define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */ +#define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */ +#define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */ +#define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */ +#define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */ +#define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */ +#define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */ +#define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */ +#define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */ +#define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */ +#define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */ +#define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */ +#define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */ +#define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */ +#define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */ +#define EEFC_FCR_FARG_Pos 8 /**< (EEFC_FCR) Flash Command Argument Position */ +#define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */ +#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)) +#define EEFC_FCR_FKEY_Pos 24 /**< (EEFC_FCR) Flash Writing Protection Key Position */ +#define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */ +#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)) +#define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +#define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */ +#define EEFC_FCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FCR) Register MASK (Use EEFC_FCR_Msk instead) */ +#define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */ + + +/* -------- EEFC_FSR : (EFC Offset: 0x08) (R/ 32) EEFC Flash Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FRDY:1; /**< bit: 0 Flash Ready Status (cleared when Flash is busy) */ + uint32_t FCMDE:1; /**< bit: 1 Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ + uint32_t FLOCKE:1; /**< bit: 2 Flash Lock Error Status (cleared on read) */ + uint32_t FLERR:1; /**< bit: 3 Flash Error Status (cleared when a programming operation starts) */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t UECCELSB:1; /**< bit: 16 Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ + uint32_t MECCELSB:1; /**< bit: 17 Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ + uint32_t UECCEMSB:1; /**< bit: 18 Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ + uint32_t MECCEMSB:1; /**< bit: 19 Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} EEFC_FSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EEFC_FSR_OFFSET (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */ + +#define EEFC_FSR_FRDY_Pos 0 /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */ +#define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */ +#define EEFC_FSR_FRDY EEFC_FSR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FRDY_Msk instead */ +#define EEFC_FSR_FCMDE_Pos 1 /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */ +#define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */ +#define EEFC_FSR_FCMDE EEFC_FSR_FCMDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FCMDE_Msk instead */ +#define EEFC_FSR_FLOCKE_Pos 2 /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */ +#define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */ +#define EEFC_FSR_FLOCKE EEFC_FSR_FLOCKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLOCKE_Msk instead */ +#define EEFC_FSR_FLERR_Pos 3 /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */ +#define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */ +#define EEFC_FSR_FLERR EEFC_FSR_FLERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLERR_Msk instead */ +#define EEFC_FSR_UECCELSB_Pos 16 /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCELSB EEFC_FSR_UECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCELSB_Msk instead */ +#define EEFC_FSR_MECCELSB_Pos 17 /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCELSB EEFC_FSR_MECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCELSB_Msk instead */ +#define EEFC_FSR_UECCEMSB_Pos 18 /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCEMSB EEFC_FSR_UECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCEMSB_Msk instead */ +#define EEFC_FSR_MECCEMSB_Pos 19 /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCEMSB EEFC_FSR_MECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCEMSB_Msk instead */ +#define EEFC_FSR_MASK _U_(0xF000F) /**< \deprecated (EEFC_FSR) Register MASK (Use EEFC_FSR_Msk instead) */ +#define EEFC_FSR_Msk _U_(0xF000F) /**< (EEFC_FSR) Register Mask */ + + +/* -------- EEFC_FRR : (EFC Offset: 0x0c) (R/ 32) EEFC Flash Result Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FVALUE:32; /**< bit: 0..31 Flash Result Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} EEFC_FRR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EEFC_FRR_OFFSET (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */ + +#define EEFC_FRR_FVALUE_Pos 0 /**< (EEFC_FRR) Flash Result Value Position */ +#define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */ +#define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos)) +#define EEFC_FRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FRR) Register MASK (Use EEFC_FRR_Msk instead) */ +#define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */ + + +/* -------- EEFC_WPMR : (EFC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} EEFC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define EEFC_WPMR_OFFSET (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */ + +#define EEFC_WPMR_WPEN_Pos 0 /**< (EEFC_WPMR) Write Protection Enable Position */ +#define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */ +#define EEFC_WPMR_WPEN EEFC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_WPMR_WPEN_Msk instead */ +#define EEFC_WPMR_WPKEY_Pos 8 /**< (EEFC_WPMR) Write Protection Key Position */ +#define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */ +#define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)) +#define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define EEFC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (EEFC_WPMR) Register MASK (Use EEFC_WPMR_Msk instead) */ +#define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief EFC hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< (EFC Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< (EFC Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< (EFC Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< (EFC Offset: 0x0C) EEFC Flash Result Register */ + __I uint8_t Reserved1[212]; + __IO uint32_t EEFC_WPMR; /**< (EFC Offset: 0xE4) Write Protection Mode Register */ +} Efc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief EFC hardware registers */ +typedef struct { + __IO EEFC_FMR_Type EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */ + __O EEFC_FCR_Type EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */ + __I EEFC_FSR_Type EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */ + __I EEFC_FRR_Type EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */ + __I uint8_t Reserved1[212]; + __IO EEFC_WPMR_Type EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} Efc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Embedded Flash Controller */ + +#endif /* _SAME70_EFC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/gmac.h b/bsp/microchip/same70/bsp/same70b/include/component/gmac.h new file mode 100644 index 0000000000..382d64c716 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/gmac.h @@ -0,0 +1,3891 @@ +/** + * \file + * + * \brief Component description for GMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_GMAC_COMPONENT_H_ +#define _SAME70_GMAC_COMPONENT_H_ +#define _SAME70_GMAC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Gigabit Ethernet MAC + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR GMAC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define GMAC_11046 /**< (GMAC) Module ID */ +#define REV_GMAC S /**< (GMAC) Module revision */ + +/* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address 1 Bottom Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SAB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SAB_OFFSET (0x00) /**< (GMAC_SAB) Specific Address 1 Bottom Register Offset */ + +#define GMAC_SAB_ADDR_Pos 0 /**< (GMAC_SAB) Specific Address 1 Position */ +#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /**< (GMAC_SAB) Specific Address 1 Mask */ +#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)) +#define GMAC_SAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAB) Register MASK (Use GMAC_SAB_Msk instead) */ +#define GMAC_SAB_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAB) Register Mask */ + + +/* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address 1 Top Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SAT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SAT_OFFSET (0x04) /**< (GMAC_SAT) Specific Address 1 Top Register Offset */ + +#define GMAC_SAT_ADDR_Pos 0 /**< (GMAC_SAT) Specific Address 1 Position */ +#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos) /**< (GMAC_SAT) Specific Address 1 Mask */ +#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)) +#define GMAC_SAT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAT) Register MASK (Use GMAC_SAT_Msk instead) */ +#define GMAC_SAT_Msk _U_(0xFFFF) /**< (GMAC_SAT) Register Mask */ + + +/* -------- GMAC_ST2CW0 : (GMAC Offset: 0x00) (R/W 32) Screening Type 2 Compare Word 0 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MASKVAL:16; /**< bit: 0..15 Mask Value */ + uint32_t COMPVAL:16; /**< bit: 16..31 Compare Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ST2CW0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ST2CW0_OFFSET (0x00) /**< (GMAC_ST2CW0) Screening Type 2 Compare Word 0 Register Offset */ + +#define GMAC_ST2CW0_MASKVAL_Pos 0 /**< (GMAC_ST2CW0) Mask Value Position */ +#define GMAC_ST2CW0_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_MASKVAL_Pos) /**< (GMAC_ST2CW0) Mask Value Mask */ +#define GMAC_ST2CW0_MASKVAL(value) (GMAC_ST2CW0_MASKVAL_Msk & ((value) << GMAC_ST2CW0_MASKVAL_Pos)) +#define GMAC_ST2CW0_COMPVAL_Pos 16 /**< (GMAC_ST2CW0) Compare Value Position */ +#define GMAC_ST2CW0_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_COMPVAL_Pos) /**< (GMAC_ST2CW0) Compare Value Mask */ +#define GMAC_ST2CW0_COMPVAL(value) (GMAC_ST2CW0_COMPVAL_Msk & ((value) << GMAC_ST2CW0_COMPVAL_Pos)) +#define GMAC_ST2CW0_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW0) Register Mask */ + + +/* -------- GMAC_ST2CW1 : (GMAC Offset: 0x04) (R/W 32) Screening Type 2 Compare Word 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OFFSVAL:7; /**< bit: 0..6 Offset Value in Bytes */ + uint32_t OFFSSTRT:2; /**< bit: 7..8 Ethernet Frame Offset Start */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ST2CW1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ST2CW1_OFFSET (0x04) /**< (GMAC_ST2CW1) Screening Type 2 Compare Word 1 Register Offset */ + +#define GMAC_ST2CW1_OFFSVAL_Pos 0 /**< (GMAC_ST2CW1) Offset Value in Bytes Position */ +#define GMAC_ST2CW1_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW1_OFFSVAL_Pos) /**< (GMAC_ST2CW1) Offset Value in Bytes Mask */ +#define GMAC_ST2CW1_OFFSVAL(value) (GMAC_ST2CW1_OFFSVAL_Msk & ((value) << GMAC_ST2CW1_OFFSVAL_Pos)) +#define GMAC_ST2CW1_OFFSSTRT_Pos 7 /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW1_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW1_OFFSSTRT(value) (GMAC_ST2CW1_OFFSSTRT_Msk & ((value) << GMAC_ST2CW1_OFFSSTRT_Pos)) +#define GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW1) Offset from the start of the frame */ +#define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW1_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field */ +#define GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW1_OFFSSTRT_FRAMESTART (GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the start of the frame Position */ +#define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE (GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW1_OFFSSTRT_IP (GMAC_ST2CW1_OFFSSTRT_IP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW1_OFFSSTRT_TCP_UDP (GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW1_MASK _U_(0x1FF) /**< \deprecated (GMAC_ST2CW1) Register MASK (Use GMAC_ST2CW1_Msk instead) */ +#define GMAC_ST2CW1_Msk _U_(0x1FF) /**< (GMAC_ST2CW1) Register Mask */ + + +/* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t LBL:1; /**< bit: 1 Loop Back Local */ + uint32_t RXEN:1; /**< bit: 2 Receive Enable */ + uint32_t TXEN:1; /**< bit: 3 Transmit Enable */ + uint32_t MPE:1; /**< bit: 4 Management Port Enable */ + uint32_t CLRSTAT:1; /**< bit: 5 Clear Statistics Registers */ + uint32_t INCSTAT:1; /**< bit: 6 Increment Statistics Registers */ + uint32_t WESTAT:1; /**< bit: 7 Write Enable for Statistics Registers */ + uint32_t BP:1; /**< bit: 8 Back pressure */ + uint32_t TSTART:1; /**< bit: 9 Start Transmission */ + uint32_t THALT:1; /**< bit: 10 Transmit Halt */ + uint32_t TXPF:1; /**< bit: 11 Transmit Pause Frame */ + uint32_t TXZQPF:1; /**< bit: 12 Transmit Zero Quantum Pause Frame */ + uint32_t :2; /**< bit: 13..14 Reserved */ + uint32_t SRTSM:1; /**< bit: 15 Store Receive Time Stamp to Memory */ + uint32_t ENPBPR:1; /**< bit: 16 Enable PFC Priority-based Pause Reception */ + uint32_t TXPBPF:1; /**< bit: 17 Transmit PFC Priority-based Pause Frame */ + uint32_t FNP:1; /**< bit: 18 Flush Next Packet */ + uint32_t TXLPIEN:1; /**< bit: 19 Enable LPI Transmission */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_NCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_NCR_OFFSET (0x00) /**< (GMAC_NCR) Network Control Register Offset */ + +#define GMAC_NCR_LBL_Pos 1 /**< (GMAC_NCR) Loop Back Local Position */ +#define GMAC_NCR_LBL_Msk (_U_(0x1) << GMAC_NCR_LBL_Pos) /**< (GMAC_NCR) Loop Back Local Mask */ +#define GMAC_NCR_LBL GMAC_NCR_LBL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_LBL_Msk instead */ +#define GMAC_NCR_RXEN_Pos 2 /**< (GMAC_NCR) Receive Enable Position */ +#define GMAC_NCR_RXEN_Msk (_U_(0x1) << GMAC_NCR_RXEN_Pos) /**< (GMAC_NCR) Receive Enable Mask */ +#define GMAC_NCR_RXEN GMAC_NCR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_RXEN_Msk instead */ +#define GMAC_NCR_TXEN_Pos 3 /**< (GMAC_NCR) Transmit Enable Position */ +#define GMAC_NCR_TXEN_Msk (_U_(0x1) << GMAC_NCR_TXEN_Pos) /**< (GMAC_NCR) Transmit Enable Mask */ +#define GMAC_NCR_TXEN GMAC_NCR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXEN_Msk instead */ +#define GMAC_NCR_MPE_Pos 4 /**< (GMAC_NCR) Management Port Enable Position */ +#define GMAC_NCR_MPE_Msk (_U_(0x1) << GMAC_NCR_MPE_Pos) /**< (GMAC_NCR) Management Port Enable Mask */ +#define GMAC_NCR_MPE GMAC_NCR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_MPE_Msk instead */ +#define GMAC_NCR_CLRSTAT_Pos 5 /**< (GMAC_NCR) Clear Statistics Registers Position */ +#define GMAC_NCR_CLRSTAT_Msk (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos) /**< (GMAC_NCR) Clear Statistics Registers Mask */ +#define GMAC_NCR_CLRSTAT GMAC_NCR_CLRSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_CLRSTAT_Msk instead */ +#define GMAC_NCR_INCSTAT_Pos 6 /**< (GMAC_NCR) Increment Statistics Registers Position */ +#define GMAC_NCR_INCSTAT_Msk (_U_(0x1) << GMAC_NCR_INCSTAT_Pos) /**< (GMAC_NCR) Increment Statistics Registers Mask */ +#define GMAC_NCR_INCSTAT GMAC_NCR_INCSTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_INCSTAT_Msk instead */ +#define GMAC_NCR_WESTAT_Pos 7 /**< (GMAC_NCR) Write Enable for Statistics Registers Position */ +#define GMAC_NCR_WESTAT_Msk (_U_(0x1) << GMAC_NCR_WESTAT_Pos) /**< (GMAC_NCR) Write Enable for Statistics Registers Mask */ +#define GMAC_NCR_WESTAT GMAC_NCR_WESTAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_WESTAT_Msk instead */ +#define GMAC_NCR_BP_Pos 8 /**< (GMAC_NCR) Back pressure Position */ +#define GMAC_NCR_BP_Msk (_U_(0x1) << GMAC_NCR_BP_Pos) /**< (GMAC_NCR) Back pressure Mask */ +#define GMAC_NCR_BP GMAC_NCR_BP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_BP_Msk instead */ +#define GMAC_NCR_TSTART_Pos 9 /**< (GMAC_NCR) Start Transmission Position */ +#define GMAC_NCR_TSTART_Msk (_U_(0x1) << GMAC_NCR_TSTART_Pos) /**< (GMAC_NCR) Start Transmission Mask */ +#define GMAC_NCR_TSTART GMAC_NCR_TSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TSTART_Msk instead */ +#define GMAC_NCR_THALT_Pos 10 /**< (GMAC_NCR) Transmit Halt Position */ +#define GMAC_NCR_THALT_Msk (_U_(0x1) << GMAC_NCR_THALT_Pos) /**< (GMAC_NCR) Transmit Halt Mask */ +#define GMAC_NCR_THALT GMAC_NCR_THALT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_THALT_Msk instead */ +#define GMAC_NCR_TXPF_Pos 11 /**< (GMAC_NCR) Transmit Pause Frame Position */ +#define GMAC_NCR_TXPF_Msk (_U_(0x1) << GMAC_NCR_TXPF_Pos) /**< (GMAC_NCR) Transmit Pause Frame Mask */ +#define GMAC_NCR_TXPF GMAC_NCR_TXPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPF_Msk instead */ +#define GMAC_NCR_TXZQPF_Pos 12 /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ +#define GMAC_NCR_TXZQPF_Msk (_U_(0x1) << GMAC_NCR_TXZQPF_Pos) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ +#define GMAC_NCR_TXZQPF GMAC_NCR_TXZQPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXZQPF_Msk instead */ +#define GMAC_NCR_SRTSM_Pos 15 /**< (GMAC_NCR) Store Receive Time Stamp to Memory Position */ +#define GMAC_NCR_SRTSM_Msk (_U_(0x1) << GMAC_NCR_SRTSM_Pos) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ +#define GMAC_NCR_SRTSM GMAC_NCR_SRTSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_SRTSM_Msk instead */ +#define GMAC_NCR_ENPBPR_Pos 16 /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ +#define GMAC_NCR_ENPBPR_Msk (_U_(0x1) << GMAC_NCR_ENPBPR_Pos) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ +#define GMAC_NCR_ENPBPR GMAC_NCR_ENPBPR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_ENPBPR_Msk instead */ +#define GMAC_NCR_TXPBPF_Pos 17 /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ +#define GMAC_NCR_TXPBPF_Msk (_U_(0x1) << GMAC_NCR_TXPBPF_Pos) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ +#define GMAC_NCR_TXPBPF GMAC_NCR_TXPBPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXPBPF_Msk instead */ +#define GMAC_NCR_FNP_Pos 18 /**< (GMAC_NCR) Flush Next Packet Position */ +#define GMAC_NCR_FNP_Msk (_U_(0x1) << GMAC_NCR_FNP_Pos) /**< (GMAC_NCR) Flush Next Packet Mask */ +#define GMAC_NCR_FNP GMAC_NCR_FNP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_FNP_Msk instead */ +#define GMAC_NCR_TXLPIEN_Pos 19 /**< (GMAC_NCR) Enable LPI Transmission Position */ +#define GMAC_NCR_TXLPIEN_Msk (_U_(0x1) << GMAC_NCR_TXLPIEN_Pos) /**< (GMAC_NCR) Enable LPI Transmission Mask */ +#define GMAC_NCR_TXLPIEN GMAC_NCR_TXLPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCR_TXLPIEN_Msk instead */ +#define GMAC_NCR_MASK _U_(0xF9FFE) /**< \deprecated (GMAC_NCR) Register MASK (Use GMAC_NCR_Msk instead) */ +#define GMAC_NCR_Msk _U_(0xF9FFE) /**< (GMAC_NCR) Register Mask */ + + +/* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SPD:1; /**< bit: 0 Speed */ + uint32_t FD:1; /**< bit: 1 Full Duplex */ + uint32_t DNVLAN:1; /**< bit: 2 Discard Non-VLAN FRAMES */ + uint32_t JFRAME:1; /**< bit: 3 Jumbo Frame Size */ + uint32_t CAF:1; /**< bit: 4 Copy All Frames */ + uint32_t NBC:1; /**< bit: 5 No Broadcast */ + uint32_t MTIHEN:1; /**< bit: 6 Multicast Hash Enable */ + uint32_t UNIHEN:1; /**< bit: 7 Unicast Hash Enable */ + uint32_t MAXFS:1; /**< bit: 8 1536 Maximum Frame Size */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t RTY:1; /**< bit: 12 Retry Test */ + uint32_t PEN:1; /**< bit: 13 Pause Enable */ + uint32_t RXBUFO:2; /**< bit: 14..15 Receive Buffer Offset */ + uint32_t LFERD:1; /**< bit: 16 Length Field Error Frame Discard */ + uint32_t RFCS:1; /**< bit: 17 Remove FCS */ + uint32_t CLK:3; /**< bit: 18..20 MDC CLock Division */ + uint32_t DBW:2; /**< bit: 21..22 Data Bus Width */ + uint32_t DCPF:1; /**< bit: 23 Disable Copy of Pause Frames */ + uint32_t RXCOEN:1; /**< bit: 24 Receive Checksum Offload Enable */ + uint32_t EFRHD:1; /**< bit: 25 Enable Frames Received in Half Duplex */ + uint32_t IRXFCS:1; /**< bit: 26 Ignore RX FCS */ + uint32_t :1; /**< bit: 27 Reserved */ + uint32_t IPGSEN:1; /**< bit: 28 IP Stretch Enable */ + uint32_t RXBP:1; /**< bit: 29 Receive Bad Preamble */ + uint32_t IRXER:1; /**< bit: 30 Ignore IPG GRXER */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_NCFGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_NCFGR_OFFSET (0x04) /**< (GMAC_NCFGR) Network Configuration Register Offset */ + +#define GMAC_NCFGR_SPD_Pos 0 /**< (GMAC_NCFGR) Speed Position */ +#define GMAC_NCFGR_SPD_Msk (_U_(0x1) << GMAC_NCFGR_SPD_Pos) /**< (GMAC_NCFGR) Speed Mask */ +#define GMAC_NCFGR_SPD GMAC_NCFGR_SPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_SPD_Msk instead */ +#define GMAC_NCFGR_FD_Pos 1 /**< (GMAC_NCFGR) Full Duplex Position */ +#define GMAC_NCFGR_FD_Msk (_U_(0x1) << GMAC_NCFGR_FD_Pos) /**< (GMAC_NCFGR) Full Duplex Mask */ +#define GMAC_NCFGR_FD GMAC_NCFGR_FD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_FD_Msk instead */ +#define GMAC_NCFGR_DNVLAN_Pos 2 /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ +#define GMAC_NCFGR_DNVLAN_Msk (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ +#define GMAC_NCFGR_DNVLAN GMAC_NCFGR_DNVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DNVLAN_Msk instead */ +#define GMAC_NCFGR_JFRAME_Pos 3 /**< (GMAC_NCFGR) Jumbo Frame Size Position */ +#define GMAC_NCFGR_JFRAME_Msk (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos) /**< (GMAC_NCFGR) Jumbo Frame Size Mask */ +#define GMAC_NCFGR_JFRAME GMAC_NCFGR_JFRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_JFRAME_Msk instead */ +#define GMAC_NCFGR_CAF_Pos 4 /**< (GMAC_NCFGR) Copy All Frames Position */ +#define GMAC_NCFGR_CAF_Msk (_U_(0x1) << GMAC_NCFGR_CAF_Pos) /**< (GMAC_NCFGR) Copy All Frames Mask */ +#define GMAC_NCFGR_CAF GMAC_NCFGR_CAF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_CAF_Msk instead */ +#define GMAC_NCFGR_NBC_Pos 5 /**< (GMAC_NCFGR) No Broadcast Position */ +#define GMAC_NCFGR_NBC_Msk (_U_(0x1) << GMAC_NCFGR_NBC_Pos) /**< (GMAC_NCFGR) No Broadcast Mask */ +#define GMAC_NCFGR_NBC GMAC_NCFGR_NBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_NBC_Msk instead */ +#define GMAC_NCFGR_MTIHEN_Pos 6 /**< (GMAC_NCFGR) Multicast Hash Enable Position */ +#define GMAC_NCFGR_MTIHEN_Msk (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /**< (GMAC_NCFGR) Multicast Hash Enable Mask */ +#define GMAC_NCFGR_MTIHEN GMAC_NCFGR_MTIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MTIHEN_Msk instead */ +#define GMAC_NCFGR_UNIHEN_Pos 7 /**< (GMAC_NCFGR) Unicast Hash Enable Position */ +#define GMAC_NCFGR_UNIHEN_Msk (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /**< (GMAC_NCFGR) Unicast Hash Enable Mask */ +#define GMAC_NCFGR_UNIHEN GMAC_NCFGR_UNIHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_UNIHEN_Msk instead */ +#define GMAC_NCFGR_MAXFS_Pos 8 /**< (GMAC_NCFGR) 1536 Maximum Frame Size Position */ +#define GMAC_NCFGR_MAXFS_Msk (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ +#define GMAC_NCFGR_MAXFS GMAC_NCFGR_MAXFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_MAXFS_Msk instead */ +#define GMAC_NCFGR_RTY_Pos 12 /**< (GMAC_NCFGR) Retry Test Position */ +#define GMAC_NCFGR_RTY_Msk (_U_(0x1) << GMAC_NCFGR_RTY_Pos) /**< (GMAC_NCFGR) Retry Test Mask */ +#define GMAC_NCFGR_RTY GMAC_NCFGR_RTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RTY_Msk instead */ +#define GMAC_NCFGR_PEN_Pos 13 /**< (GMAC_NCFGR) Pause Enable Position */ +#define GMAC_NCFGR_PEN_Msk (_U_(0x1) << GMAC_NCFGR_PEN_Pos) /**< (GMAC_NCFGR) Pause Enable Mask */ +#define GMAC_NCFGR_PEN GMAC_NCFGR_PEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_PEN_Msk instead */ +#define GMAC_NCFGR_RXBUFO_Pos 14 /**< (GMAC_NCFGR) Receive Buffer Offset Position */ +#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /**< (GMAC_NCFGR) Receive Buffer Offset Mask */ +#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)) +#define GMAC_NCFGR_LFERD_Pos 16 /**< (GMAC_NCFGR) Length Field Error Frame Discard Position */ +#define GMAC_NCFGR_LFERD_Msk (_U_(0x1) << GMAC_NCFGR_LFERD_Pos) /**< (GMAC_NCFGR) Length Field Error Frame Discard Mask */ +#define GMAC_NCFGR_LFERD GMAC_NCFGR_LFERD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_LFERD_Msk instead */ +#define GMAC_NCFGR_RFCS_Pos 17 /**< (GMAC_NCFGR) Remove FCS Position */ +#define GMAC_NCFGR_RFCS_Msk (_U_(0x1) << GMAC_NCFGR_RFCS_Pos) /**< (GMAC_NCFGR) Remove FCS Mask */ +#define GMAC_NCFGR_RFCS GMAC_NCFGR_RFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RFCS_Msk instead */ +#define GMAC_NCFGR_CLK_Pos 18 /**< (GMAC_NCFGR) MDC CLock Division Position */ +#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MDC CLock Division Mask */ +#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)) +#define GMAC_NCFGR_CLK_MCK_8_Val _U_(0x0) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16_Val _U_(0x1) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32_Val _U_(0x2) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48_Val _U_(0x3) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64_Val _U_(0x4) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96_Val _U_(0x5) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_CLK_MCK_8 (GMAC_NCFGR_CLK_MCK_8_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_16 (GMAC_NCFGR_CLK_MCK_16_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_32 (GMAC_NCFGR_CLK_MCK_32_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_48 (GMAC_NCFGR_CLK_MCK_48_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_64 (GMAC_NCFGR_CLK_MCK_64_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_96 (GMAC_NCFGR_CLK_MCK_96_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) Position */ +#define GMAC_NCFGR_DBW_Pos 21 /**< (GMAC_NCFGR) Data Bus Width Position */ +#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos) /**< (GMAC_NCFGR) Data Bus Width Mask */ +#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)) +#define GMAC_NCFGR_DCPF_Pos 23 /**< (GMAC_NCFGR) Disable Copy of Pause Frames Position */ +#define GMAC_NCFGR_DCPF_Msk (_U_(0x1) << GMAC_NCFGR_DCPF_Pos) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ +#define GMAC_NCFGR_DCPF GMAC_NCFGR_DCPF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_DCPF_Msk instead */ +#define GMAC_NCFGR_RXCOEN_Pos 24 /**< (GMAC_NCFGR) Receive Checksum Offload Enable Position */ +#define GMAC_NCFGR_RXCOEN_Msk (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ +#define GMAC_NCFGR_RXCOEN GMAC_NCFGR_RXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXCOEN_Msk instead */ +#define GMAC_NCFGR_EFRHD_Pos 25 /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ +#define GMAC_NCFGR_EFRHD_Msk (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ +#define GMAC_NCFGR_EFRHD GMAC_NCFGR_EFRHD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_EFRHD_Msk instead */ +#define GMAC_NCFGR_IRXFCS_Pos 26 /**< (GMAC_NCFGR) Ignore RX FCS Position */ +#define GMAC_NCFGR_IRXFCS_Msk (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /**< (GMAC_NCFGR) Ignore RX FCS Mask */ +#define GMAC_NCFGR_IRXFCS GMAC_NCFGR_IRXFCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXFCS_Msk instead */ +#define GMAC_NCFGR_IPGSEN_Pos 28 /**< (GMAC_NCFGR) IP Stretch Enable Position */ +#define GMAC_NCFGR_IPGSEN_Msk (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /**< (GMAC_NCFGR) IP Stretch Enable Mask */ +#define GMAC_NCFGR_IPGSEN GMAC_NCFGR_IPGSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IPGSEN_Msk instead */ +#define GMAC_NCFGR_RXBP_Pos 29 /**< (GMAC_NCFGR) Receive Bad Preamble Position */ +#define GMAC_NCFGR_RXBP_Msk (_U_(0x1) << GMAC_NCFGR_RXBP_Pos) /**< (GMAC_NCFGR) Receive Bad Preamble Mask */ +#define GMAC_NCFGR_RXBP GMAC_NCFGR_RXBP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_RXBP_Msk instead */ +#define GMAC_NCFGR_IRXER_Pos 30 /**< (GMAC_NCFGR) Ignore IPG GRXER Position */ +#define GMAC_NCFGR_IRXER_Msk (_U_(0x1) << GMAC_NCFGR_IRXER_Pos) /**< (GMAC_NCFGR) Ignore IPG GRXER Mask */ +#define GMAC_NCFGR_IRXER GMAC_NCFGR_IRXER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NCFGR_IRXER_Msk instead */ +#define GMAC_NCFGR_MASK _U_(0x77FFF1FF) /**< \deprecated (GMAC_NCFGR) Register MASK (Use GMAC_NCFGR_Msk instead) */ +#define GMAC_NCFGR_Msk _U_(0x77FFF1FF) /**< (GMAC_NCFGR) Register Mask */ + + +/* -------- GMAC_NSR : (GMAC Offset: 0x08) (R/ 32) Network Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t MDIO:1; /**< bit: 1 MDIO Input Status */ + uint32_t IDLE:1; /**< bit: 2 PHY Management Logic Idle */ + uint32_t :4; /**< bit: 3..6 Reserved */ + uint32_t RXLPIS:1; /**< bit: 7 LPI Indication */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_NSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_NSR_OFFSET (0x08) /**< (GMAC_NSR) Network Status Register Offset */ + +#define GMAC_NSR_MDIO_Pos 1 /**< (GMAC_NSR) MDIO Input Status Position */ +#define GMAC_NSR_MDIO_Msk (_U_(0x1) << GMAC_NSR_MDIO_Pos) /**< (GMAC_NSR) MDIO Input Status Mask */ +#define GMAC_NSR_MDIO GMAC_NSR_MDIO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_MDIO_Msk instead */ +#define GMAC_NSR_IDLE_Pos 2 /**< (GMAC_NSR) PHY Management Logic Idle Position */ +#define GMAC_NSR_IDLE_Msk (_U_(0x1) << GMAC_NSR_IDLE_Pos) /**< (GMAC_NSR) PHY Management Logic Idle Mask */ +#define GMAC_NSR_IDLE GMAC_NSR_IDLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_IDLE_Msk instead */ +#define GMAC_NSR_RXLPIS_Pos 7 /**< (GMAC_NSR) LPI Indication Position */ +#define GMAC_NSR_RXLPIS_Msk (_U_(0x1) << GMAC_NSR_RXLPIS_Pos) /**< (GMAC_NSR) LPI Indication Mask */ +#define GMAC_NSR_RXLPIS GMAC_NSR_RXLPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_NSR_RXLPIS_Msk instead */ +#define GMAC_NSR_MASK _U_(0x86) /**< \deprecated (GMAC_NSR) Register MASK (Use GMAC_NSR_Msk instead) */ +#define GMAC_NSR_Msk _U_(0x86) /**< (GMAC_NSR) Register Mask */ + + +/* -------- GMAC_UR : (GMAC Offset: 0x0c) (R/W 32) User Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RMII:1; /**< bit: 0 Reduced MII Mode */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_UR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_UR_OFFSET (0x0C) /**< (GMAC_UR) User Register Offset */ + +#define GMAC_UR_RMII_Pos 0 /**< (GMAC_UR) Reduced MII Mode Position */ +#define GMAC_UR_RMII_Msk (_U_(0x1) << GMAC_UR_RMII_Pos) /**< (GMAC_UR) Reduced MII Mode Mask */ +#define GMAC_UR_RMII GMAC_UR_RMII_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_UR_RMII_Msk instead */ +#define GMAC_UR_MASK _U_(0x01) /**< \deprecated (GMAC_UR) Register MASK (Use GMAC_UR_Msk instead) */ +#define GMAC_UR_Msk _U_(0x01) /**< (GMAC_UR) Register Mask */ + + +/* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FBLDO:5; /**< bit: 0..4 Fixed Burst Length for DMA Data Operations: */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t ESMA:1; /**< bit: 6 Endian Swap Mode Enable for Management Descriptor Accesses */ + uint32_t ESPA:1; /**< bit: 7 Endian Swap Mode Enable for Packet Data Accesses */ + uint32_t RXBMS:2; /**< bit: 8..9 Receiver Packet Buffer Memory Size Select */ + uint32_t TXPBMS:1; /**< bit: 10 Transmitter Packet Buffer Memory Size Select */ + uint32_t TXCOEN:1; /**< bit: 11 Transmitter Checksum Generation Offload Enable */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t DRBS:8; /**< bit: 16..23 DMA Receive Buffer Size */ + uint32_t DDRP:1; /**< bit: 24 DMA Discard Receive Packets */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_DCFGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_DCFGR_OFFSET (0x10) /**< (GMAC_DCFGR) DMA Configuration Register Offset */ + +#define GMAC_DCFGR_FBLDO_Pos 0 /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ +#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ +#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)) +#define GMAC_DCFGR_FBLDO_SINGLE_Val _U_(0x1) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4_Val _U_(0x4) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8_Val _U_(0x8) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16_Val _U_(0x10) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ +#define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ +#define GMAC_DCFGR_ESMA_Pos 6 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ +#define GMAC_DCFGR_ESMA_Msk (_U_(0x1) << GMAC_DCFGR_ESMA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ +#define GMAC_DCFGR_ESMA GMAC_DCFGR_ESMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESMA_Msk instead */ +#define GMAC_DCFGR_ESPA_Pos 7 /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ +#define GMAC_DCFGR_ESPA_Msk (_U_(0x1) << GMAC_DCFGR_ESPA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ +#define GMAC_DCFGR_ESPA GMAC_DCFGR_ESPA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_ESPA_Msk instead */ +#define GMAC_DCFGR_RXBMS_Pos 8 /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)) +#define GMAC_DCFGR_RXBMS_EIGHTH_Val _U_(0x0) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER_Val _U_(0x1) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF_Val _U_(0x2) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL_Val _U_(0x3) /**< (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size Position */ +#define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_TXPBMS_Pos 10 /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_TXPBMS_Msk (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_TXPBMS GMAC_DCFGR_TXPBMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXPBMS_Msk instead */ +#define GMAC_DCFGR_TXCOEN_Pos 11 /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ +#define GMAC_DCFGR_TXCOEN_Msk (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ +#define GMAC_DCFGR_TXCOEN GMAC_DCFGR_TXCOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_TXCOEN_Msk instead */ +#define GMAC_DCFGR_DRBS_Pos 16 /**< (GMAC_DCFGR) DMA Receive Buffer Size Position */ +#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos) /**< (GMAC_DCFGR) DMA Receive Buffer Size Mask */ +#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)) +#define GMAC_DCFGR_DDRP_Pos 24 /**< (GMAC_DCFGR) DMA Discard Receive Packets Position */ +#define GMAC_DCFGR_DDRP_Msk (_U_(0x1) << GMAC_DCFGR_DDRP_Pos) /**< (GMAC_DCFGR) DMA Discard Receive Packets Mask */ +#define GMAC_DCFGR_DDRP GMAC_DCFGR_DDRP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_DCFGR_DDRP_Msk instead */ +#define GMAC_DCFGR_MASK _U_(0x1FF0FDF) /**< \deprecated (GMAC_DCFGR) Register MASK (Use GMAC_DCFGR_Msk instead) */ +#define GMAC_DCFGR_Msk _U_(0x1FF0FDF) /**< (GMAC_DCFGR) Register Mask */ + + +/* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UBR:1; /**< bit: 0 Used Bit Read */ + uint32_t COL:1; /**< bit: 1 Collision Occurred */ + uint32_t RLE:1; /**< bit: 2 Retry Limit Exceeded */ + uint32_t TXGO:1; /**< bit: 3 Transmit Go */ + uint32_t TFC:1; /**< bit: 4 Transmit Frame Corruption Due to AHB Error */ + uint32_t TXCOMP:1; /**< bit: 5 Transmit Complete */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t HRESP:1; /**< bit: 8 HRESP Not OK */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TSR_OFFSET (0x14) /**< (GMAC_TSR) Transmit Status Register Offset */ + +#define GMAC_TSR_UBR_Pos 0 /**< (GMAC_TSR) Used Bit Read Position */ +#define GMAC_TSR_UBR_Msk (_U_(0x1) << GMAC_TSR_UBR_Pos) /**< (GMAC_TSR) Used Bit Read Mask */ +#define GMAC_TSR_UBR GMAC_TSR_UBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_UBR_Msk instead */ +#define GMAC_TSR_COL_Pos 1 /**< (GMAC_TSR) Collision Occurred Position */ +#define GMAC_TSR_COL_Msk (_U_(0x1) << GMAC_TSR_COL_Pos) /**< (GMAC_TSR) Collision Occurred Mask */ +#define GMAC_TSR_COL GMAC_TSR_COL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_COL_Msk instead */ +#define GMAC_TSR_RLE_Pos 2 /**< (GMAC_TSR) Retry Limit Exceeded Position */ +#define GMAC_TSR_RLE_Msk (_U_(0x1) << GMAC_TSR_RLE_Pos) /**< (GMAC_TSR) Retry Limit Exceeded Mask */ +#define GMAC_TSR_RLE GMAC_TSR_RLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_RLE_Msk instead */ +#define GMAC_TSR_TXGO_Pos 3 /**< (GMAC_TSR) Transmit Go Position */ +#define GMAC_TSR_TXGO_Msk (_U_(0x1) << GMAC_TSR_TXGO_Pos) /**< (GMAC_TSR) Transmit Go Mask */ +#define GMAC_TSR_TXGO GMAC_TSR_TXGO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXGO_Msk instead */ +#define GMAC_TSR_TFC_Pos 4 /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_TSR_TFC_Msk (_U_(0x1) << GMAC_TSR_TFC_Pos) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_TSR_TFC GMAC_TSR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TFC_Msk instead */ +#define GMAC_TSR_TXCOMP_Pos 5 /**< (GMAC_TSR) Transmit Complete Position */ +#define GMAC_TSR_TXCOMP_Msk (_U_(0x1) << GMAC_TSR_TXCOMP_Pos) /**< (GMAC_TSR) Transmit Complete Mask */ +#define GMAC_TSR_TXCOMP GMAC_TSR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_TXCOMP_Msk instead */ +#define GMAC_TSR_HRESP_Pos 8 /**< (GMAC_TSR) HRESP Not OK Position */ +#define GMAC_TSR_HRESP_Msk (_U_(0x1) << GMAC_TSR_HRESP_Pos) /**< (GMAC_TSR) HRESP Not OK Mask */ +#define GMAC_TSR_HRESP GMAC_TSR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TSR_HRESP_Msk instead */ +#define GMAC_TSR_MASK _U_(0x13F) /**< \deprecated (GMAC_TSR) Register MASK (Use GMAC_TSR_Msk instead) */ +#define GMAC_TSR_Msk _U_(0x13F) /**< (GMAC_TSR) Register Mask */ + + +/* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t ADDR:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RBQB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RBQB_OFFSET (0x18) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Register Offset */ + +#define GMAC_RBQB_ADDR_Pos 2 /**< (GMAC_RBQB) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)) +#define GMAC_RBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQB) Register MASK (Use GMAC_RBQB_Msk instead) */ +#define GMAC_RBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQB) Register Mask */ + + +/* -------- GMAC_TBQB : (GMAC Offset: 0x1c) (R/W 32) Transmit Buffer Queue Base Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t ADDR:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBQB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBQB_OFFSET (0x1C) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Register Offset */ + +#define GMAC_TBQB_ADDR_Pos 2 /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)) +#define GMAC_TBQB_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQB) Register MASK (Use GMAC_TBQB_Msk instead) */ +#define GMAC_TBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQB) Register Mask */ + + +/* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BNA:1; /**< bit: 0 Buffer Not Available */ + uint32_t REC:1; /**< bit: 1 Frame Received */ + uint32_t RXOVR:1; /**< bit: 2 Receive Overrun */ + uint32_t HNO:1; /**< bit: 3 HRESP Not OK */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RSR_OFFSET (0x20) /**< (GMAC_RSR) Receive Status Register Offset */ + +#define GMAC_RSR_BNA_Pos 0 /**< (GMAC_RSR) Buffer Not Available Position */ +#define GMAC_RSR_BNA_Msk (_U_(0x1) << GMAC_RSR_BNA_Pos) /**< (GMAC_RSR) Buffer Not Available Mask */ +#define GMAC_RSR_BNA GMAC_RSR_BNA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_BNA_Msk instead */ +#define GMAC_RSR_REC_Pos 1 /**< (GMAC_RSR) Frame Received Position */ +#define GMAC_RSR_REC_Msk (_U_(0x1) << GMAC_RSR_REC_Pos) /**< (GMAC_RSR) Frame Received Mask */ +#define GMAC_RSR_REC GMAC_RSR_REC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_REC_Msk instead */ +#define GMAC_RSR_RXOVR_Pos 2 /**< (GMAC_RSR) Receive Overrun Position */ +#define GMAC_RSR_RXOVR_Msk (_U_(0x1) << GMAC_RSR_RXOVR_Pos) /**< (GMAC_RSR) Receive Overrun Mask */ +#define GMAC_RSR_RXOVR GMAC_RSR_RXOVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_RXOVR_Msk instead */ +#define GMAC_RSR_HNO_Pos 3 /**< (GMAC_RSR) HRESP Not OK Position */ +#define GMAC_RSR_HNO_Msk (_U_(0x1) << GMAC_RSR_HNO_Pos) /**< (GMAC_RSR) HRESP Not OK Mask */ +#define GMAC_RSR_HNO GMAC_RSR_HNO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RSR_HNO_Msk instead */ +#define GMAC_RSR_MASK _U_(0x0F) /**< \deprecated (GMAC_RSR) Register MASK (Use GMAC_RSR_Msk instead) */ +#define GMAC_RSR_Msk _U_(0x0F) /**< (GMAC_RSR) Register Mask */ + + +/* -------- GMAC_ISR : (GMAC Offset: 0x24) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ + uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ + uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ + uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ + uint32_t :3; /**< bit: 15..17 Reserved */ + uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ + uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ + uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ + uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ + uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ + uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ + uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ + uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ + uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ + uint32_t RXLPISBC:1; /**< bit: 27 Receive LPI indication Status Bit Change */ + uint32_t WOL:1; /**< bit: 28 Wake On LAN */ + uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ISR_OFFSET (0x24) /**< (GMAC_ISR) Interrupt Status Register Offset */ + +#define GMAC_ISR_MFS_Pos 0 /**< (GMAC_ISR) Management Frame Sent Position */ +#define GMAC_ISR_MFS_Msk (_U_(0x1) << GMAC_ISR_MFS_Pos) /**< (GMAC_ISR) Management Frame Sent Mask */ +#define GMAC_ISR_MFS GMAC_ISR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_MFS_Msk instead */ +#define GMAC_ISR_RCOMP_Pos 1 /**< (GMAC_ISR) Receive Complete Position */ +#define GMAC_ISR_RCOMP_Msk (_U_(0x1) << GMAC_ISR_RCOMP_Pos) /**< (GMAC_ISR) Receive Complete Mask */ +#define GMAC_ISR_RCOMP GMAC_ISR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RCOMP_Msk instead */ +#define GMAC_ISR_RXUBR_Pos 2 /**< (GMAC_ISR) RX Used Bit Read Position */ +#define GMAC_ISR_RXUBR_Msk (_U_(0x1) << GMAC_ISR_RXUBR_Pos) /**< (GMAC_ISR) RX Used Bit Read Mask */ +#define GMAC_ISR_RXUBR GMAC_ISR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RXUBR_Msk instead */ +#define GMAC_ISR_TXUBR_Pos 3 /**< (GMAC_ISR) TX Used Bit Read Position */ +#define GMAC_ISR_TXUBR_Msk (_U_(0x1) << GMAC_ISR_TXUBR_Pos) /**< (GMAC_ISR) TX Used Bit Read Mask */ +#define GMAC_ISR_TXUBR GMAC_ISR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TXUBR_Msk instead */ +#define GMAC_ISR_TUR_Pos 4 /**< (GMAC_ISR) Transmit Underrun Position */ +#define GMAC_ISR_TUR_Msk (_U_(0x1) << GMAC_ISR_TUR_Pos) /**< (GMAC_ISR) Transmit Underrun Mask */ +#define GMAC_ISR_TUR GMAC_ISR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TUR_Msk instead */ +#define GMAC_ISR_RLEX_Pos 5 /**< (GMAC_ISR) Retry Limit Exceeded Position */ +#define GMAC_ISR_RLEX_Msk (_U_(0x1) << GMAC_ISR_RLEX_Pos) /**< (GMAC_ISR) Retry Limit Exceeded Mask */ +#define GMAC_ISR_RLEX GMAC_ISR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RLEX_Msk instead */ +#define GMAC_ISR_TFC_Pos 6 /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISR_TFC_Msk (_U_(0x1) << GMAC_ISR_TFC_Pos) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISR_TFC GMAC_ISR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TFC_Msk instead */ +#define GMAC_ISR_TCOMP_Pos 7 /**< (GMAC_ISR) Transmit Complete Position */ +#define GMAC_ISR_TCOMP_Msk (_U_(0x1) << GMAC_ISR_TCOMP_Pos) /**< (GMAC_ISR) Transmit Complete Mask */ +#define GMAC_ISR_TCOMP GMAC_ISR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TCOMP_Msk instead */ +#define GMAC_ISR_ROVR_Pos 10 /**< (GMAC_ISR) Receive Overrun Position */ +#define GMAC_ISR_ROVR_Msk (_U_(0x1) << GMAC_ISR_ROVR_Pos) /**< (GMAC_ISR) Receive Overrun Mask */ +#define GMAC_ISR_ROVR GMAC_ISR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_ROVR_Msk instead */ +#define GMAC_ISR_HRESP_Pos 11 /**< (GMAC_ISR) HRESP Not OK Position */ +#define GMAC_ISR_HRESP_Msk (_U_(0x1) << GMAC_ISR_HRESP_Pos) /**< (GMAC_ISR) HRESP Not OK Mask */ +#define GMAC_ISR_HRESP GMAC_ISR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_HRESP_Msk instead */ +#define GMAC_ISR_PFNZ_Pos 12 /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_ISR_PFNZ_Msk (_U_(0x1) << GMAC_ISR_PFNZ_Pos) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_ISR_PFNZ GMAC_ISR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFNZ_Msk instead */ +#define GMAC_ISR_PTZ_Pos 13 /**< (GMAC_ISR) Pause Time Zero Position */ +#define GMAC_ISR_PTZ_Msk (_U_(0x1) << GMAC_ISR_PTZ_Pos) /**< (GMAC_ISR) Pause Time Zero Mask */ +#define GMAC_ISR_PTZ GMAC_ISR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PTZ_Msk instead */ +#define GMAC_ISR_PFTR_Pos 14 /**< (GMAC_ISR) Pause Frame Transmitted Position */ +#define GMAC_ISR_PFTR_Msk (_U_(0x1) << GMAC_ISR_PFTR_Pos) /**< (GMAC_ISR) Pause Frame Transmitted Mask */ +#define GMAC_ISR_PFTR GMAC_ISR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PFTR_Msk instead */ +#define GMAC_ISR_DRQFR_Pos 18 /**< (GMAC_ISR) PTP Delay Request Frame Received Position */ +#define GMAC_ISR_DRQFR_Msk (_U_(0x1) << GMAC_ISR_DRQFR_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Received Mask */ +#define GMAC_ISR_DRQFR GMAC_ISR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFR_Msk instead */ +#define GMAC_ISR_SFR_Pos 19 /**< (GMAC_ISR) PTP Sync Frame Received Position */ +#define GMAC_ISR_SFR_Msk (_U_(0x1) << GMAC_ISR_SFR_Pos) /**< (GMAC_ISR) PTP Sync Frame Received Mask */ +#define GMAC_ISR_SFR GMAC_ISR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFR_Msk instead */ +#define GMAC_ISR_DRQFT_Pos 20 /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_ISR_DRQFT_Msk (_U_(0x1) << GMAC_ISR_DRQFT_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_ISR_DRQFT GMAC_ISR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_DRQFT_Msk instead */ +#define GMAC_ISR_SFT_Pos 21 /**< (GMAC_ISR) PTP Sync Frame Transmitted Position */ +#define GMAC_ISR_SFT_Msk (_U_(0x1) << GMAC_ISR_SFT_Pos) /**< (GMAC_ISR) PTP Sync Frame Transmitted Mask */ +#define GMAC_ISR_SFT GMAC_ISR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SFT_Msk instead */ +#define GMAC_ISR_PDRQFR_Pos 22 /**< (GMAC_ISR) PDelay Request Frame Received Position */ +#define GMAC_ISR_PDRQFR_Msk (_U_(0x1) << GMAC_ISR_PDRQFR_Pos) /**< (GMAC_ISR) PDelay Request Frame Received Mask */ +#define GMAC_ISR_PDRQFR GMAC_ISR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFR_Msk instead */ +#define GMAC_ISR_PDRSFR_Pos 23 /**< (GMAC_ISR) PDelay Response Frame Received Position */ +#define GMAC_ISR_PDRSFR_Msk (_U_(0x1) << GMAC_ISR_PDRSFR_Pos) /**< (GMAC_ISR) PDelay Response Frame Received Mask */ +#define GMAC_ISR_PDRSFR GMAC_ISR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFR_Msk instead */ +#define GMAC_ISR_PDRQFT_Pos 24 /**< (GMAC_ISR) PDelay Request Frame Transmitted Position */ +#define GMAC_ISR_PDRQFT_Msk (_U_(0x1) << GMAC_ISR_PDRQFT_Pos) /**< (GMAC_ISR) PDelay Request Frame Transmitted Mask */ +#define GMAC_ISR_PDRQFT GMAC_ISR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRQFT_Msk instead */ +#define GMAC_ISR_PDRSFT_Pos 25 /**< (GMAC_ISR) PDelay Response Frame Transmitted Position */ +#define GMAC_ISR_PDRSFT_Msk (_U_(0x1) << GMAC_ISR_PDRSFT_Pos) /**< (GMAC_ISR) PDelay Response Frame Transmitted Mask */ +#define GMAC_ISR_PDRSFT GMAC_ISR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_PDRSFT_Msk instead */ +#define GMAC_ISR_SRI_Pos 26 /**< (GMAC_ISR) TSU Seconds Register Increment Position */ +#define GMAC_ISR_SRI_Msk (_U_(0x1) << GMAC_ISR_SRI_Pos) /**< (GMAC_ISR) TSU Seconds Register Increment Mask */ +#define GMAC_ISR_SRI GMAC_ISR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_SRI_Msk instead */ +#define GMAC_ISR_RXLPISBC_Pos 27 /**< (GMAC_ISR) Receive LPI indication Status Bit Change Position */ +#define GMAC_ISR_RXLPISBC_Msk (_U_(0x1) << GMAC_ISR_RXLPISBC_Pos) /**< (GMAC_ISR) Receive LPI indication Status Bit Change Mask */ +#define GMAC_ISR_RXLPISBC GMAC_ISR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_RXLPISBC_Msk instead */ +#define GMAC_ISR_WOL_Pos 28 /**< (GMAC_ISR) Wake On LAN Position */ +#define GMAC_ISR_WOL_Msk (_U_(0x1) << GMAC_ISR_WOL_Pos) /**< (GMAC_ISR) Wake On LAN Mask */ +#define GMAC_ISR_WOL GMAC_ISR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_WOL_Msk instead */ +#define GMAC_ISR_TSUTIMCOMP_Pos 29 /**< (GMAC_ISR) TSU Timer Comparison Position */ +#define GMAC_ISR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_ISR_TSUTIMCOMP_Pos) /**< (GMAC_ISR) TSU Timer Comparison Mask */ +#define GMAC_ISR_TSUTIMCOMP GMAC_ISR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISR_TSUTIMCOMP_Msk instead */ +#define GMAC_ISR_MASK _U_(0x3FFC7CFF) /**< \deprecated (GMAC_ISR) Register MASK (Use GMAC_ISR_Msk instead) */ +#define GMAC_ISR_Msk _U_(0x3FFC7CFF) /**< (GMAC_ISR) Register Mask */ + + +/* -------- GMAC_IER : (GMAC Offset: 0x28) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ + uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ + uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ + uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ + uint32_t EXINT:1; /**< bit: 15 External Interrupt */ + uint32_t :2; /**< bit: 16..17 Reserved */ + uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ + uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ + uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ + uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ + uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ + uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ + uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ + uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ + uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ + uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ + uint32_t WOL:1; /**< bit: 28 Wake On LAN */ + uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IER_OFFSET (0x28) /**< (GMAC_IER) Interrupt Enable Register Offset */ + +#define GMAC_IER_MFS_Pos 0 /**< (GMAC_IER) Management Frame Sent Position */ +#define GMAC_IER_MFS_Msk (_U_(0x1) << GMAC_IER_MFS_Pos) /**< (GMAC_IER) Management Frame Sent Mask */ +#define GMAC_IER_MFS GMAC_IER_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_MFS_Msk instead */ +#define GMAC_IER_RCOMP_Pos 1 /**< (GMAC_IER) Receive Complete Position */ +#define GMAC_IER_RCOMP_Msk (_U_(0x1) << GMAC_IER_RCOMP_Pos) /**< (GMAC_IER) Receive Complete Mask */ +#define GMAC_IER_RCOMP GMAC_IER_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RCOMP_Msk instead */ +#define GMAC_IER_RXUBR_Pos 2 /**< (GMAC_IER) RX Used Bit Read Position */ +#define GMAC_IER_RXUBR_Msk (_U_(0x1) << GMAC_IER_RXUBR_Pos) /**< (GMAC_IER) RX Used Bit Read Mask */ +#define GMAC_IER_RXUBR GMAC_IER_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXUBR_Msk instead */ +#define GMAC_IER_TXUBR_Pos 3 /**< (GMAC_IER) TX Used Bit Read Position */ +#define GMAC_IER_TXUBR_Msk (_U_(0x1) << GMAC_IER_TXUBR_Pos) /**< (GMAC_IER) TX Used Bit Read Mask */ +#define GMAC_IER_TXUBR GMAC_IER_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TXUBR_Msk instead */ +#define GMAC_IER_TUR_Pos 4 /**< (GMAC_IER) Transmit Underrun Position */ +#define GMAC_IER_TUR_Msk (_U_(0x1) << GMAC_IER_TUR_Pos) /**< (GMAC_IER) Transmit Underrun Mask */ +#define GMAC_IER_TUR GMAC_IER_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TUR_Msk instead */ +#define GMAC_IER_RLEX_Pos 5 /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IER_RLEX_Msk (_U_(0x1) << GMAC_IER_RLEX_Pos) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IER_RLEX GMAC_IER_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RLEX_Msk instead */ +#define GMAC_IER_TFC_Pos 6 /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IER_TFC_Msk (_U_(0x1) << GMAC_IER_TFC_Pos) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IER_TFC GMAC_IER_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TFC_Msk instead */ +#define GMAC_IER_TCOMP_Pos 7 /**< (GMAC_IER) Transmit Complete Position */ +#define GMAC_IER_TCOMP_Msk (_U_(0x1) << GMAC_IER_TCOMP_Pos) /**< (GMAC_IER) Transmit Complete Mask */ +#define GMAC_IER_TCOMP GMAC_IER_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TCOMP_Msk instead */ +#define GMAC_IER_ROVR_Pos 10 /**< (GMAC_IER) Receive Overrun Position */ +#define GMAC_IER_ROVR_Msk (_U_(0x1) << GMAC_IER_ROVR_Pos) /**< (GMAC_IER) Receive Overrun Mask */ +#define GMAC_IER_ROVR GMAC_IER_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_ROVR_Msk instead */ +#define GMAC_IER_HRESP_Pos 11 /**< (GMAC_IER) HRESP Not OK Position */ +#define GMAC_IER_HRESP_Msk (_U_(0x1) << GMAC_IER_HRESP_Pos) /**< (GMAC_IER) HRESP Not OK Mask */ +#define GMAC_IER_HRESP GMAC_IER_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_HRESP_Msk instead */ +#define GMAC_IER_PFNZ_Pos 12 /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IER_PFNZ_Msk (_U_(0x1) << GMAC_IER_PFNZ_Pos) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IER_PFNZ GMAC_IER_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFNZ_Msk instead */ +#define GMAC_IER_PTZ_Pos 13 /**< (GMAC_IER) Pause Time Zero Position */ +#define GMAC_IER_PTZ_Msk (_U_(0x1) << GMAC_IER_PTZ_Pos) /**< (GMAC_IER) Pause Time Zero Mask */ +#define GMAC_IER_PTZ GMAC_IER_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PTZ_Msk instead */ +#define GMAC_IER_PFTR_Pos 14 /**< (GMAC_IER) Pause Frame Transmitted Position */ +#define GMAC_IER_PFTR_Msk (_U_(0x1) << GMAC_IER_PFTR_Pos) /**< (GMAC_IER) Pause Frame Transmitted Mask */ +#define GMAC_IER_PFTR GMAC_IER_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PFTR_Msk instead */ +#define GMAC_IER_EXINT_Pos 15 /**< (GMAC_IER) External Interrupt Position */ +#define GMAC_IER_EXINT_Msk (_U_(0x1) << GMAC_IER_EXINT_Pos) /**< (GMAC_IER) External Interrupt Mask */ +#define GMAC_IER_EXINT GMAC_IER_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_EXINT_Msk instead */ +#define GMAC_IER_DRQFR_Pos 18 /**< (GMAC_IER) PTP Delay Request Frame Received Position */ +#define GMAC_IER_DRQFR_Msk (_U_(0x1) << GMAC_IER_DRQFR_Pos) /**< (GMAC_IER) PTP Delay Request Frame Received Mask */ +#define GMAC_IER_DRQFR GMAC_IER_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFR_Msk instead */ +#define GMAC_IER_SFR_Pos 19 /**< (GMAC_IER) PTP Sync Frame Received Position */ +#define GMAC_IER_SFR_Msk (_U_(0x1) << GMAC_IER_SFR_Pos) /**< (GMAC_IER) PTP Sync Frame Received Mask */ +#define GMAC_IER_SFR GMAC_IER_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFR_Msk instead */ +#define GMAC_IER_DRQFT_Pos 20 /**< (GMAC_IER) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IER_DRQFT_Msk (_U_(0x1) << GMAC_IER_DRQFT_Pos) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IER_DRQFT GMAC_IER_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_DRQFT_Msk instead */ +#define GMAC_IER_SFT_Pos 21 /**< (GMAC_IER) PTP Sync Frame Transmitted Position */ +#define GMAC_IER_SFT_Msk (_U_(0x1) << GMAC_IER_SFT_Pos) /**< (GMAC_IER) PTP Sync Frame Transmitted Mask */ +#define GMAC_IER_SFT GMAC_IER_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SFT_Msk instead */ +#define GMAC_IER_PDRQFR_Pos 22 /**< (GMAC_IER) PDelay Request Frame Received Position */ +#define GMAC_IER_PDRQFR_Msk (_U_(0x1) << GMAC_IER_PDRQFR_Pos) /**< (GMAC_IER) PDelay Request Frame Received Mask */ +#define GMAC_IER_PDRQFR GMAC_IER_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFR_Msk instead */ +#define GMAC_IER_PDRSFR_Pos 23 /**< (GMAC_IER) PDelay Response Frame Received Position */ +#define GMAC_IER_PDRSFR_Msk (_U_(0x1) << GMAC_IER_PDRSFR_Pos) /**< (GMAC_IER) PDelay Response Frame Received Mask */ +#define GMAC_IER_PDRSFR GMAC_IER_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFR_Msk instead */ +#define GMAC_IER_PDRQFT_Pos 24 /**< (GMAC_IER) PDelay Request Frame Transmitted Position */ +#define GMAC_IER_PDRQFT_Msk (_U_(0x1) << GMAC_IER_PDRQFT_Pos) /**< (GMAC_IER) PDelay Request Frame Transmitted Mask */ +#define GMAC_IER_PDRQFT GMAC_IER_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRQFT_Msk instead */ +#define GMAC_IER_PDRSFT_Pos 25 /**< (GMAC_IER) PDelay Response Frame Transmitted Position */ +#define GMAC_IER_PDRSFT_Msk (_U_(0x1) << GMAC_IER_PDRSFT_Pos) /**< (GMAC_IER) PDelay Response Frame Transmitted Mask */ +#define GMAC_IER_PDRSFT GMAC_IER_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_PDRSFT_Msk instead */ +#define GMAC_IER_SRI_Pos 26 /**< (GMAC_IER) TSU Seconds Register Increment Position */ +#define GMAC_IER_SRI_Msk (_U_(0x1) << GMAC_IER_SRI_Pos) /**< (GMAC_IER) TSU Seconds Register Increment Mask */ +#define GMAC_IER_SRI GMAC_IER_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_SRI_Msk instead */ +#define GMAC_IER_RXLPISBC_Pos 27 /**< (GMAC_IER) Enable RX LPI Indication Position */ +#define GMAC_IER_RXLPISBC_Msk (_U_(0x1) << GMAC_IER_RXLPISBC_Pos) /**< (GMAC_IER) Enable RX LPI Indication Mask */ +#define GMAC_IER_RXLPISBC GMAC_IER_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_RXLPISBC_Msk instead */ +#define GMAC_IER_WOL_Pos 28 /**< (GMAC_IER) Wake On LAN Position */ +#define GMAC_IER_WOL_Msk (_U_(0x1) << GMAC_IER_WOL_Pos) /**< (GMAC_IER) Wake On LAN Mask */ +#define GMAC_IER_WOL GMAC_IER_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_WOL_Msk instead */ +#define GMAC_IER_TSUTIMCOMP_Pos 29 /**< (GMAC_IER) TSU Timer Comparison Position */ +#define GMAC_IER_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IER_TSUTIMCOMP_Pos) /**< (GMAC_IER) TSU Timer Comparison Mask */ +#define GMAC_IER_TSUTIMCOMP GMAC_IER_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IER_TSUTIMCOMP_Msk instead */ +#define GMAC_IER_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IER) Register MASK (Use GMAC_IER_Msk instead) */ +#define GMAC_IER_Msk _U_(0x3FFCFCFF) /**< (GMAC_IER) Register Mask */ + + +/* -------- GMAC_IDR : (GMAC Offset: 0x2c) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ + uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ + uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ + uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ + uint32_t EXINT:1; /**< bit: 15 External Interrupt */ + uint32_t :2; /**< bit: 16..17 Reserved */ + uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ + uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ + uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ + uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ + uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ + uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ + uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ + uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ + uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ + uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ + uint32_t WOL:1; /**< bit: 28 Wake On LAN */ + uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IDR_OFFSET (0x2C) /**< (GMAC_IDR) Interrupt Disable Register Offset */ + +#define GMAC_IDR_MFS_Pos 0 /**< (GMAC_IDR) Management Frame Sent Position */ +#define GMAC_IDR_MFS_Msk (_U_(0x1) << GMAC_IDR_MFS_Pos) /**< (GMAC_IDR) Management Frame Sent Mask */ +#define GMAC_IDR_MFS GMAC_IDR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_MFS_Msk instead */ +#define GMAC_IDR_RCOMP_Pos 1 /**< (GMAC_IDR) Receive Complete Position */ +#define GMAC_IDR_RCOMP_Msk (_U_(0x1) << GMAC_IDR_RCOMP_Pos) /**< (GMAC_IDR) Receive Complete Mask */ +#define GMAC_IDR_RCOMP GMAC_IDR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RCOMP_Msk instead */ +#define GMAC_IDR_RXUBR_Pos 2 /**< (GMAC_IDR) RX Used Bit Read Position */ +#define GMAC_IDR_RXUBR_Msk (_U_(0x1) << GMAC_IDR_RXUBR_Pos) /**< (GMAC_IDR) RX Used Bit Read Mask */ +#define GMAC_IDR_RXUBR GMAC_IDR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXUBR_Msk instead */ +#define GMAC_IDR_TXUBR_Pos 3 /**< (GMAC_IDR) TX Used Bit Read Position */ +#define GMAC_IDR_TXUBR_Msk (_U_(0x1) << GMAC_IDR_TXUBR_Pos) /**< (GMAC_IDR) TX Used Bit Read Mask */ +#define GMAC_IDR_TXUBR GMAC_IDR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TXUBR_Msk instead */ +#define GMAC_IDR_TUR_Pos 4 /**< (GMAC_IDR) Transmit Underrun Position */ +#define GMAC_IDR_TUR_Msk (_U_(0x1) << GMAC_IDR_TUR_Pos) /**< (GMAC_IDR) Transmit Underrun Mask */ +#define GMAC_IDR_TUR GMAC_IDR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TUR_Msk instead */ +#define GMAC_IDR_RLEX_Pos 5 /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDR_RLEX_Msk (_U_(0x1) << GMAC_IDR_RLEX_Pos) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDR_RLEX GMAC_IDR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RLEX_Msk instead */ +#define GMAC_IDR_TFC_Pos 6 /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDR_TFC_Msk (_U_(0x1) << GMAC_IDR_TFC_Pos) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDR_TFC GMAC_IDR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TFC_Msk instead */ +#define GMAC_IDR_TCOMP_Pos 7 /**< (GMAC_IDR) Transmit Complete Position */ +#define GMAC_IDR_TCOMP_Msk (_U_(0x1) << GMAC_IDR_TCOMP_Pos) /**< (GMAC_IDR) Transmit Complete Mask */ +#define GMAC_IDR_TCOMP GMAC_IDR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TCOMP_Msk instead */ +#define GMAC_IDR_ROVR_Pos 10 /**< (GMAC_IDR) Receive Overrun Position */ +#define GMAC_IDR_ROVR_Msk (_U_(0x1) << GMAC_IDR_ROVR_Pos) /**< (GMAC_IDR) Receive Overrun Mask */ +#define GMAC_IDR_ROVR GMAC_IDR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_ROVR_Msk instead */ +#define GMAC_IDR_HRESP_Pos 11 /**< (GMAC_IDR) HRESP Not OK Position */ +#define GMAC_IDR_HRESP_Msk (_U_(0x1) << GMAC_IDR_HRESP_Pos) /**< (GMAC_IDR) HRESP Not OK Mask */ +#define GMAC_IDR_HRESP GMAC_IDR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_HRESP_Msk instead */ +#define GMAC_IDR_PFNZ_Pos 12 /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IDR_PFNZ_Msk (_U_(0x1) << GMAC_IDR_PFNZ_Pos) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IDR_PFNZ GMAC_IDR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFNZ_Msk instead */ +#define GMAC_IDR_PTZ_Pos 13 /**< (GMAC_IDR) Pause Time Zero Position */ +#define GMAC_IDR_PTZ_Msk (_U_(0x1) << GMAC_IDR_PTZ_Pos) /**< (GMAC_IDR) Pause Time Zero Mask */ +#define GMAC_IDR_PTZ GMAC_IDR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PTZ_Msk instead */ +#define GMAC_IDR_PFTR_Pos 14 /**< (GMAC_IDR) Pause Frame Transmitted Position */ +#define GMAC_IDR_PFTR_Msk (_U_(0x1) << GMAC_IDR_PFTR_Pos) /**< (GMAC_IDR) Pause Frame Transmitted Mask */ +#define GMAC_IDR_PFTR GMAC_IDR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PFTR_Msk instead */ +#define GMAC_IDR_EXINT_Pos 15 /**< (GMAC_IDR) External Interrupt Position */ +#define GMAC_IDR_EXINT_Msk (_U_(0x1) << GMAC_IDR_EXINT_Pos) /**< (GMAC_IDR) External Interrupt Mask */ +#define GMAC_IDR_EXINT GMAC_IDR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_EXINT_Msk instead */ +#define GMAC_IDR_DRQFR_Pos 18 /**< (GMAC_IDR) PTP Delay Request Frame Received Position */ +#define GMAC_IDR_DRQFR_Msk (_U_(0x1) << GMAC_IDR_DRQFR_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Received Mask */ +#define GMAC_IDR_DRQFR GMAC_IDR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFR_Msk instead */ +#define GMAC_IDR_SFR_Pos 19 /**< (GMAC_IDR) PTP Sync Frame Received Position */ +#define GMAC_IDR_SFR_Msk (_U_(0x1) << GMAC_IDR_SFR_Pos) /**< (GMAC_IDR) PTP Sync Frame Received Mask */ +#define GMAC_IDR_SFR GMAC_IDR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFR_Msk instead */ +#define GMAC_IDR_DRQFT_Pos 20 /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IDR_DRQFT_Msk (_U_(0x1) << GMAC_IDR_DRQFT_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IDR_DRQFT GMAC_IDR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_DRQFT_Msk instead */ +#define GMAC_IDR_SFT_Pos 21 /**< (GMAC_IDR) PTP Sync Frame Transmitted Position */ +#define GMAC_IDR_SFT_Msk (_U_(0x1) << GMAC_IDR_SFT_Pos) /**< (GMAC_IDR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IDR_SFT GMAC_IDR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SFT_Msk instead */ +#define GMAC_IDR_PDRQFR_Pos 22 /**< (GMAC_IDR) PDelay Request Frame Received Position */ +#define GMAC_IDR_PDRQFR_Msk (_U_(0x1) << GMAC_IDR_PDRQFR_Pos) /**< (GMAC_IDR) PDelay Request Frame Received Mask */ +#define GMAC_IDR_PDRQFR GMAC_IDR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFR_Msk instead */ +#define GMAC_IDR_PDRSFR_Pos 23 /**< (GMAC_IDR) PDelay Response Frame Received Position */ +#define GMAC_IDR_PDRSFR_Msk (_U_(0x1) << GMAC_IDR_PDRSFR_Pos) /**< (GMAC_IDR) PDelay Response Frame Received Mask */ +#define GMAC_IDR_PDRSFR GMAC_IDR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFR_Msk instead */ +#define GMAC_IDR_PDRQFT_Pos 24 /**< (GMAC_IDR) PDelay Request Frame Transmitted Position */ +#define GMAC_IDR_PDRQFT_Msk (_U_(0x1) << GMAC_IDR_PDRQFT_Pos) /**< (GMAC_IDR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IDR_PDRQFT GMAC_IDR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRQFT_Msk instead */ +#define GMAC_IDR_PDRSFT_Pos 25 /**< (GMAC_IDR) PDelay Response Frame Transmitted Position */ +#define GMAC_IDR_PDRSFT_Msk (_U_(0x1) << GMAC_IDR_PDRSFT_Pos) /**< (GMAC_IDR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IDR_PDRSFT GMAC_IDR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_PDRSFT_Msk instead */ +#define GMAC_IDR_SRI_Pos 26 /**< (GMAC_IDR) TSU Seconds Register Increment Position */ +#define GMAC_IDR_SRI_Msk (_U_(0x1) << GMAC_IDR_SRI_Pos) /**< (GMAC_IDR) TSU Seconds Register Increment Mask */ +#define GMAC_IDR_SRI GMAC_IDR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_SRI_Msk instead */ +#define GMAC_IDR_RXLPISBC_Pos 27 /**< (GMAC_IDR) Enable RX LPI Indication Position */ +#define GMAC_IDR_RXLPISBC_Msk (_U_(0x1) << GMAC_IDR_RXLPISBC_Pos) /**< (GMAC_IDR) Enable RX LPI Indication Mask */ +#define GMAC_IDR_RXLPISBC GMAC_IDR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_RXLPISBC_Msk instead */ +#define GMAC_IDR_WOL_Pos 28 /**< (GMAC_IDR) Wake On LAN Position */ +#define GMAC_IDR_WOL_Msk (_U_(0x1) << GMAC_IDR_WOL_Pos) /**< (GMAC_IDR) Wake On LAN Mask */ +#define GMAC_IDR_WOL GMAC_IDR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_WOL_Msk instead */ +#define GMAC_IDR_TSUTIMCOMP_Pos 29 /**< (GMAC_IDR) TSU Timer Comparison Position */ +#define GMAC_IDR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IDR_TSUTIMCOMP_Pos) /**< (GMAC_IDR) TSU Timer Comparison Mask */ +#define GMAC_IDR_TSUTIMCOMP GMAC_IDR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDR_TSUTIMCOMP_Msk instead */ +#define GMAC_IDR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IDR) Register MASK (Use GMAC_IDR_Msk instead) */ +#define GMAC_IDR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IDR) Register Mask */ + + +/* -------- GMAC_IMR : (GMAC Offset: 0x30) (R/W 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFS:1; /**< bit: 0 Management Frame Sent */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t TXUBR:1; /**< bit: 3 TX Used Bit Read */ + uint32_t TUR:1; /**< bit: 4 Transmit Underrun */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t PFNZ:1; /**< bit: 12 Pause Frame with Non-zero Pause Quantum Received */ + uint32_t PTZ:1; /**< bit: 13 Pause Time Zero */ + uint32_t PFTR:1; /**< bit: 14 Pause Frame Transmitted */ + uint32_t EXINT:1; /**< bit: 15 External Interrupt */ + uint32_t :2; /**< bit: 16..17 Reserved */ + uint32_t DRQFR:1; /**< bit: 18 PTP Delay Request Frame Received */ + uint32_t SFR:1; /**< bit: 19 PTP Sync Frame Received */ + uint32_t DRQFT:1; /**< bit: 20 PTP Delay Request Frame Transmitted */ + uint32_t SFT:1; /**< bit: 21 PTP Sync Frame Transmitted */ + uint32_t PDRQFR:1; /**< bit: 22 PDelay Request Frame Received */ + uint32_t PDRSFR:1; /**< bit: 23 PDelay Response Frame Received */ + uint32_t PDRQFT:1; /**< bit: 24 PDelay Request Frame Transmitted */ + uint32_t PDRSFT:1; /**< bit: 25 PDelay Response Frame Transmitted */ + uint32_t SRI:1; /**< bit: 26 TSU Seconds Register Increment */ + uint32_t RXLPISBC:1; /**< bit: 27 Enable RX LPI Indication */ + uint32_t WOL:1; /**< bit: 28 Wake On LAN */ + uint32_t TSUTIMCOMP:1; /**< bit: 29 TSU Timer Comparison */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IMR_OFFSET (0x30) /**< (GMAC_IMR) Interrupt Mask Register Offset */ + +#define GMAC_IMR_MFS_Pos 0 /**< (GMAC_IMR) Management Frame Sent Position */ +#define GMAC_IMR_MFS_Msk (_U_(0x1) << GMAC_IMR_MFS_Pos) /**< (GMAC_IMR) Management Frame Sent Mask */ +#define GMAC_IMR_MFS GMAC_IMR_MFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_MFS_Msk instead */ +#define GMAC_IMR_RCOMP_Pos 1 /**< (GMAC_IMR) Receive Complete Position */ +#define GMAC_IMR_RCOMP_Msk (_U_(0x1) << GMAC_IMR_RCOMP_Pos) /**< (GMAC_IMR) Receive Complete Mask */ +#define GMAC_IMR_RCOMP GMAC_IMR_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RCOMP_Msk instead */ +#define GMAC_IMR_RXUBR_Pos 2 /**< (GMAC_IMR) RX Used Bit Read Position */ +#define GMAC_IMR_RXUBR_Msk (_U_(0x1) << GMAC_IMR_RXUBR_Pos) /**< (GMAC_IMR) RX Used Bit Read Mask */ +#define GMAC_IMR_RXUBR GMAC_IMR_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXUBR_Msk instead */ +#define GMAC_IMR_TXUBR_Pos 3 /**< (GMAC_IMR) TX Used Bit Read Position */ +#define GMAC_IMR_TXUBR_Msk (_U_(0x1) << GMAC_IMR_TXUBR_Pos) /**< (GMAC_IMR) TX Used Bit Read Mask */ +#define GMAC_IMR_TXUBR GMAC_IMR_TXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TXUBR_Msk instead */ +#define GMAC_IMR_TUR_Pos 4 /**< (GMAC_IMR) Transmit Underrun Position */ +#define GMAC_IMR_TUR_Msk (_U_(0x1) << GMAC_IMR_TUR_Pos) /**< (GMAC_IMR) Transmit Underrun Mask */ +#define GMAC_IMR_TUR GMAC_IMR_TUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TUR_Msk instead */ +#define GMAC_IMR_RLEX_Pos 5 /**< (GMAC_IMR) Retry Limit Exceeded Position */ +#define GMAC_IMR_RLEX_Msk (_U_(0x1) << GMAC_IMR_RLEX_Pos) /**< (GMAC_IMR) Retry Limit Exceeded Mask */ +#define GMAC_IMR_RLEX GMAC_IMR_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RLEX_Msk instead */ +#define GMAC_IMR_TFC_Pos 6 /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IMR_TFC_Msk (_U_(0x1) << GMAC_IMR_TFC_Pos) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IMR_TFC GMAC_IMR_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TFC_Msk instead */ +#define GMAC_IMR_TCOMP_Pos 7 /**< (GMAC_IMR) Transmit Complete Position */ +#define GMAC_IMR_TCOMP_Msk (_U_(0x1) << GMAC_IMR_TCOMP_Pos) /**< (GMAC_IMR) Transmit Complete Mask */ +#define GMAC_IMR_TCOMP GMAC_IMR_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TCOMP_Msk instead */ +#define GMAC_IMR_ROVR_Pos 10 /**< (GMAC_IMR) Receive Overrun Position */ +#define GMAC_IMR_ROVR_Msk (_U_(0x1) << GMAC_IMR_ROVR_Pos) /**< (GMAC_IMR) Receive Overrun Mask */ +#define GMAC_IMR_ROVR GMAC_IMR_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_ROVR_Msk instead */ +#define GMAC_IMR_HRESP_Pos 11 /**< (GMAC_IMR) HRESP Not OK Position */ +#define GMAC_IMR_HRESP_Msk (_U_(0x1) << GMAC_IMR_HRESP_Pos) /**< (GMAC_IMR) HRESP Not OK Mask */ +#define GMAC_IMR_HRESP GMAC_IMR_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_HRESP_Msk instead */ +#define GMAC_IMR_PFNZ_Pos 12 /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IMR_PFNZ_Msk (_U_(0x1) << GMAC_IMR_PFNZ_Pos) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IMR_PFNZ GMAC_IMR_PFNZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFNZ_Msk instead */ +#define GMAC_IMR_PTZ_Pos 13 /**< (GMAC_IMR) Pause Time Zero Position */ +#define GMAC_IMR_PTZ_Msk (_U_(0x1) << GMAC_IMR_PTZ_Pos) /**< (GMAC_IMR) Pause Time Zero Mask */ +#define GMAC_IMR_PTZ GMAC_IMR_PTZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PTZ_Msk instead */ +#define GMAC_IMR_PFTR_Pos 14 /**< (GMAC_IMR) Pause Frame Transmitted Position */ +#define GMAC_IMR_PFTR_Msk (_U_(0x1) << GMAC_IMR_PFTR_Pos) /**< (GMAC_IMR) Pause Frame Transmitted Mask */ +#define GMAC_IMR_PFTR GMAC_IMR_PFTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PFTR_Msk instead */ +#define GMAC_IMR_EXINT_Pos 15 /**< (GMAC_IMR) External Interrupt Position */ +#define GMAC_IMR_EXINT_Msk (_U_(0x1) << GMAC_IMR_EXINT_Pos) /**< (GMAC_IMR) External Interrupt Mask */ +#define GMAC_IMR_EXINT GMAC_IMR_EXINT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_EXINT_Msk instead */ +#define GMAC_IMR_DRQFR_Pos 18 /**< (GMAC_IMR) PTP Delay Request Frame Received Position */ +#define GMAC_IMR_DRQFR_Msk (_U_(0x1) << GMAC_IMR_DRQFR_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Received Mask */ +#define GMAC_IMR_DRQFR GMAC_IMR_DRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFR_Msk instead */ +#define GMAC_IMR_SFR_Pos 19 /**< (GMAC_IMR) PTP Sync Frame Received Position */ +#define GMAC_IMR_SFR_Msk (_U_(0x1) << GMAC_IMR_SFR_Pos) /**< (GMAC_IMR) PTP Sync Frame Received Mask */ +#define GMAC_IMR_SFR GMAC_IMR_SFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFR_Msk instead */ +#define GMAC_IMR_DRQFT_Pos 20 /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IMR_DRQFT_Msk (_U_(0x1) << GMAC_IMR_DRQFT_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IMR_DRQFT GMAC_IMR_DRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_DRQFT_Msk instead */ +#define GMAC_IMR_SFT_Pos 21 /**< (GMAC_IMR) PTP Sync Frame Transmitted Position */ +#define GMAC_IMR_SFT_Msk (_U_(0x1) << GMAC_IMR_SFT_Pos) /**< (GMAC_IMR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IMR_SFT GMAC_IMR_SFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SFT_Msk instead */ +#define GMAC_IMR_PDRQFR_Pos 22 /**< (GMAC_IMR) PDelay Request Frame Received Position */ +#define GMAC_IMR_PDRQFR_Msk (_U_(0x1) << GMAC_IMR_PDRQFR_Pos) /**< (GMAC_IMR) PDelay Request Frame Received Mask */ +#define GMAC_IMR_PDRQFR GMAC_IMR_PDRQFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFR_Msk instead */ +#define GMAC_IMR_PDRSFR_Pos 23 /**< (GMAC_IMR) PDelay Response Frame Received Position */ +#define GMAC_IMR_PDRSFR_Msk (_U_(0x1) << GMAC_IMR_PDRSFR_Pos) /**< (GMAC_IMR) PDelay Response Frame Received Mask */ +#define GMAC_IMR_PDRSFR GMAC_IMR_PDRSFR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFR_Msk instead */ +#define GMAC_IMR_PDRQFT_Pos 24 /**< (GMAC_IMR) PDelay Request Frame Transmitted Position */ +#define GMAC_IMR_PDRQFT_Msk (_U_(0x1) << GMAC_IMR_PDRQFT_Pos) /**< (GMAC_IMR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IMR_PDRQFT GMAC_IMR_PDRQFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRQFT_Msk instead */ +#define GMAC_IMR_PDRSFT_Pos 25 /**< (GMAC_IMR) PDelay Response Frame Transmitted Position */ +#define GMAC_IMR_PDRSFT_Msk (_U_(0x1) << GMAC_IMR_PDRSFT_Pos) /**< (GMAC_IMR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IMR_PDRSFT GMAC_IMR_PDRSFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_PDRSFT_Msk instead */ +#define GMAC_IMR_SRI_Pos 26 /**< (GMAC_IMR) TSU Seconds Register Increment Position */ +#define GMAC_IMR_SRI_Msk (_U_(0x1) << GMAC_IMR_SRI_Pos) /**< (GMAC_IMR) TSU Seconds Register Increment Mask */ +#define GMAC_IMR_SRI GMAC_IMR_SRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_SRI_Msk instead */ +#define GMAC_IMR_RXLPISBC_Pos 27 /**< (GMAC_IMR) Enable RX LPI Indication Position */ +#define GMAC_IMR_RXLPISBC_Msk (_U_(0x1) << GMAC_IMR_RXLPISBC_Pos) /**< (GMAC_IMR) Enable RX LPI Indication Mask */ +#define GMAC_IMR_RXLPISBC GMAC_IMR_RXLPISBC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_RXLPISBC_Msk instead */ +#define GMAC_IMR_WOL_Pos 28 /**< (GMAC_IMR) Wake On LAN Position */ +#define GMAC_IMR_WOL_Msk (_U_(0x1) << GMAC_IMR_WOL_Pos) /**< (GMAC_IMR) Wake On LAN Mask */ +#define GMAC_IMR_WOL GMAC_IMR_WOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_WOL_Msk instead */ +#define GMAC_IMR_TSUTIMCOMP_Pos 29 /**< (GMAC_IMR) TSU Timer Comparison Position */ +#define GMAC_IMR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IMR_TSUTIMCOMP_Pos) /**< (GMAC_IMR) TSU Timer Comparison Mask */ +#define GMAC_IMR_TSUTIMCOMP GMAC_IMR_TSUTIMCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMR_TSUTIMCOMP_Msk instead */ +#define GMAC_IMR_MASK _U_(0x3FFCFCFF) /**< \deprecated (GMAC_IMR) Register MASK (Use GMAC_IMR_Msk instead) */ +#define GMAC_IMR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IMR) Register Mask */ + + +/* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA:16; /**< bit: 0..15 PHY Data */ + uint32_t WTN:2; /**< bit: 16..17 Write Ten */ + uint32_t REGA:5; /**< bit: 18..22 Register Address */ + uint32_t PHYA:5; /**< bit: 23..27 PHY Address */ + uint32_t OP:2; /**< bit: 28..29 Operation */ + uint32_t CLTTO:1; /**< bit: 30 Clause 22 Operation */ + uint32_t WZO:1; /**< bit: 31 Write ZERO */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_MAN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_MAN_OFFSET (0x34) /**< (GMAC_MAN) PHY Maintenance Register Offset */ + +#define GMAC_MAN_DATA_Pos 0 /**< (GMAC_MAN) PHY Data Position */ +#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos) /**< (GMAC_MAN) PHY Data Mask */ +#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)) +#define GMAC_MAN_WTN_Pos 16 /**< (GMAC_MAN) Write Ten Position */ +#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos) /**< (GMAC_MAN) Write Ten Mask */ +#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)) +#define GMAC_MAN_REGA_Pos 18 /**< (GMAC_MAN) Register Address Position */ +#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos) /**< (GMAC_MAN) Register Address Mask */ +#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)) +#define GMAC_MAN_PHYA_Pos 23 /**< (GMAC_MAN) PHY Address Position */ +#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos) /**< (GMAC_MAN) PHY Address Mask */ +#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)) +#define GMAC_MAN_OP_Pos 28 /**< (GMAC_MAN) Operation Position */ +#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos) /**< (GMAC_MAN) Operation Mask */ +#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)) +#define GMAC_MAN_CLTTO_Pos 30 /**< (GMAC_MAN) Clause 22 Operation Position */ +#define GMAC_MAN_CLTTO_Msk (_U_(0x1) << GMAC_MAN_CLTTO_Pos) /**< (GMAC_MAN) Clause 22 Operation Mask */ +#define GMAC_MAN_CLTTO GMAC_MAN_CLTTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_CLTTO_Msk instead */ +#define GMAC_MAN_WZO_Pos 31 /**< (GMAC_MAN) Write ZERO Position */ +#define GMAC_MAN_WZO_Msk (_U_(0x1) << GMAC_MAN_WZO_Pos) /**< (GMAC_MAN) Write ZERO Mask */ +#define GMAC_MAN_WZO GMAC_MAN_WZO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_MAN_WZO_Msk instead */ +#define GMAC_MAN_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MAN) Register MASK (Use GMAC_MAN_Msk instead) */ +#define GMAC_MAN_Msk _U_(0xFFFFFFFF) /**< (GMAC_MAN) Register Mask */ + + +/* -------- GMAC_RPQ : (GMAC Offset: 0x38) (R/ 32) Received Pause Quantum Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RPQ:16; /**< bit: 0..15 Received Pause Quantum */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RPQ_OFFSET (0x38) /**< (GMAC_RPQ) Received Pause Quantum Register Offset */ + +#define GMAC_RPQ_RPQ_Pos 0 /**< (GMAC_RPQ) Received Pause Quantum Position */ +#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /**< (GMAC_RPQ) Received Pause Quantum Mask */ +#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos)) +#define GMAC_RPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RPQ) Register MASK (Use GMAC_RPQ_Msk instead) */ +#define GMAC_RPQ_Msk _U_(0xFFFF) /**< (GMAC_RPQ) Register Mask */ + + +/* -------- GMAC_TPQ : (GMAC Offset: 0x3c) (R/W 32) Transmit Pause Quantum Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TPQ:16; /**< bit: 0..15 Transmit Pause Quantum */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TPQ_OFFSET (0x3C) /**< (GMAC_TPQ) Transmit Pause Quantum Register Offset */ + +#define GMAC_TPQ_TPQ_Pos 0 /**< (GMAC_TPQ) Transmit Pause Quantum Position */ +#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /**< (GMAC_TPQ) Transmit Pause Quantum Mask */ +#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)) +#define GMAC_TPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPQ) Register MASK (Use GMAC_TPQ_Msk instead) */ +#define GMAC_TPQ_Msk _U_(0xFFFF) /**< (GMAC_TPQ) Register Mask */ + + +/* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX Partial Store and Forward Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TPB1ADR:12; /**< bit: 0..11 Transmit Partial Store and Forward Address */ + uint32_t :19; /**< bit: 12..30 Reserved */ + uint32_t ENTXP:1; /**< bit: 31 Enable TX Partial Store and Forward Operation */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TPSF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TPSF_OFFSET (0x40) /**< (GMAC_TPSF) TX Partial Store and Forward Register Offset */ + +#define GMAC_TPSF_TPB1ADR_Pos 0 /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Position */ +#define GMAC_TPSF_TPB1ADR_Msk (_U_(0xFFF) << GMAC_TPSF_TPB1ADR_Pos) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Mask */ +#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)) +#define GMAC_TPSF_ENTXP_Pos 31 /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Position */ +#define GMAC_TPSF_ENTXP_Msk (_U_(0x1) << GMAC_TPSF_ENTXP_Pos) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Mask */ +#define GMAC_TPSF_ENTXP GMAC_TPSF_ENTXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TPSF_ENTXP_Msk instead */ +#define GMAC_TPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_TPSF) Register MASK (Use GMAC_TPSF_Msk instead) */ +#define GMAC_TPSF_Msk _U_(0x80000FFF) /**< (GMAC_TPSF) Register Mask */ + + +/* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX Partial Store and Forward Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RPB1ADR:12; /**< bit: 0..11 Receive Partial Store and Forward Address */ + uint32_t :19; /**< bit: 12..30 Reserved */ + uint32_t ENRXP:1; /**< bit: 31 Enable RX Partial Store and Forward Operation */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RPSF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RPSF_OFFSET (0x44) /**< (GMAC_RPSF) RX Partial Store and Forward Register Offset */ + +#define GMAC_RPSF_RPB1ADR_Pos 0 /**< (GMAC_RPSF) Receive Partial Store and Forward Address Position */ +#define GMAC_RPSF_RPB1ADR_Msk (_U_(0xFFF) << GMAC_RPSF_RPB1ADR_Pos) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Mask */ +#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)) +#define GMAC_RPSF_ENRXP_Pos 31 /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Position */ +#define GMAC_RPSF_ENRXP_Msk (_U_(0x1) << GMAC_RPSF_ENRXP_Pos) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Mask */ +#define GMAC_RPSF_ENRXP GMAC_RPSF_ENRXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_RPSF_ENRXP_Msk instead */ +#define GMAC_RPSF_MASK _U_(0x80000FFF) /**< \deprecated (GMAC_RPSF) Register MASK (Use GMAC_RPSF_Msk instead) */ +#define GMAC_RPSF_Msk _U_(0x80000FFF) /**< (GMAC_RPSF) Register Mask */ + + +/* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FML:14; /**< bit: 0..13 Frame Max Length */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RJFML_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RJFML_OFFSET (0x48) /**< (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ + +#define GMAC_RJFML_FML_Pos 0 /**< (GMAC_RJFML) Frame Max Length Position */ +#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos) /**< (GMAC_RJFML) Frame Max Length Mask */ +#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)) +#define GMAC_RJFML_MASK _U_(0x3FFF) /**< \deprecated (GMAC_RJFML) Register MASK (Use GMAC_RJFML_Msk instead) */ +#define GMAC_RJFML_Msk _U_(0x3FFF) /**< (GMAC_RJFML) Register Mask */ + + +/* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_HRB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_HRB_OFFSET (0x80) /**< (GMAC_HRB) Hash Register Bottom Offset */ + +#define GMAC_HRB_ADDR_Pos 0 /**< (GMAC_HRB) Hash Address Position */ +#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /**< (GMAC_HRB) Hash Address Mask */ +#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)) +#define GMAC_HRB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRB) Register MASK (Use GMAC_HRB_Msk instead) */ +#define GMAC_HRB_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRB) Register Mask */ + + +/* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:32; /**< bit: 0..31 Hash Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_HRT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_HRT_OFFSET (0x84) /**< (GMAC_HRT) Hash Register Top Offset */ + +#define GMAC_HRT_ADDR_Pos 0 /**< (GMAC_HRT) Hash Address Position */ +#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /**< (GMAC_HRT) Hash Address Mask */ +#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)) +#define GMAC_HRT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_HRT) Register MASK (Use GMAC_HRT_Msk instead) */ +#define GMAC_HRT_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRT) Register Mask */ + + +/* -------- GMAC_TIDM1 : (GMAC Offset: 0xa8) (R/W 32) Type ID Match 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TID:16; /**< bit: 0..15 Type ID Match 1 */ + uint32_t :15; /**< bit: 16..30 Reserved */ + uint32_t ENID1:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :31; /**< bit: 0..30 Reserved */ + uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TIDM1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TIDM1_OFFSET (0xA8) /**< (GMAC_TIDM1) Type ID Match 1 Register Offset */ + +#define GMAC_TIDM1_TID_Pos 0 /**< (GMAC_TIDM1) Type ID Match 1 Position */ +#define GMAC_TIDM1_TID_Msk (_U_(0xFFFF) << GMAC_TIDM1_TID_Pos) /**< (GMAC_TIDM1) Type ID Match 1 Mask */ +#define GMAC_TIDM1_TID(value) (GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)) +#define GMAC_TIDM1_ENID1_Pos 31 /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM1_ENID1_Msk (_U_(0x1) << GMAC_TIDM1_ENID1_Pos) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM1_ENID1 GMAC_TIDM1_ENID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM1_ENID1_Msk instead */ +#define GMAC_TIDM1_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM1) Register MASK (Use GMAC_TIDM1_Msk instead) */ +#define GMAC_TIDM1_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM1) Register Mask */ + +#define GMAC_TIDM1_ENID_Pos 31 /**< (GMAC_TIDM1 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM1_ENID_Msk (_U_(0x1) << GMAC_TIDM1_ENID_Pos) /**< (GMAC_TIDM1 Mask) ENID */ +#define GMAC_TIDM1_ENID(value) (GMAC_TIDM1_ENID_Msk & ((value) << GMAC_TIDM1_ENID_Pos)) + +/* -------- GMAC_TIDM2 : (GMAC Offset: 0xac) (R/W 32) Type ID Match 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TID:16; /**< bit: 0..15 Type ID Match 2 */ + uint32_t :15; /**< bit: 16..30 Reserved */ + uint32_t ENID2:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :31; /**< bit: 0..30 Reserved */ + uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TIDM2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TIDM2_OFFSET (0xAC) /**< (GMAC_TIDM2) Type ID Match 2 Register Offset */ + +#define GMAC_TIDM2_TID_Pos 0 /**< (GMAC_TIDM2) Type ID Match 2 Position */ +#define GMAC_TIDM2_TID_Msk (_U_(0xFFFF) << GMAC_TIDM2_TID_Pos) /**< (GMAC_TIDM2) Type ID Match 2 Mask */ +#define GMAC_TIDM2_TID(value) (GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)) +#define GMAC_TIDM2_ENID2_Pos 31 /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM2_ENID2_Msk (_U_(0x1) << GMAC_TIDM2_ENID2_Pos) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM2_ENID2 GMAC_TIDM2_ENID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM2_ENID2_Msk instead */ +#define GMAC_TIDM2_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM2) Register MASK (Use GMAC_TIDM2_Msk instead) */ +#define GMAC_TIDM2_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM2) Register Mask */ + +#define GMAC_TIDM2_ENID_Pos 31 /**< (GMAC_TIDM2 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM2_ENID_Msk (_U_(0x1) << GMAC_TIDM2_ENID_Pos) /**< (GMAC_TIDM2 Mask) ENID */ +#define GMAC_TIDM2_ENID(value) (GMAC_TIDM2_ENID_Msk & ((value) << GMAC_TIDM2_ENID_Pos)) + +/* -------- GMAC_TIDM3 : (GMAC Offset: 0xb0) (R/W 32) Type ID Match 3 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TID:16; /**< bit: 0..15 Type ID Match 3 */ + uint32_t :15; /**< bit: 16..30 Reserved */ + uint32_t ENID3:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :31; /**< bit: 0..30 Reserved */ + uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TIDM3_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TIDM3_OFFSET (0xB0) /**< (GMAC_TIDM3) Type ID Match 3 Register Offset */ + +#define GMAC_TIDM3_TID_Pos 0 /**< (GMAC_TIDM3) Type ID Match 3 Position */ +#define GMAC_TIDM3_TID_Msk (_U_(0xFFFF) << GMAC_TIDM3_TID_Pos) /**< (GMAC_TIDM3) Type ID Match 3 Mask */ +#define GMAC_TIDM3_TID(value) (GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)) +#define GMAC_TIDM3_ENID3_Pos 31 /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM3_ENID3_Msk (_U_(0x1) << GMAC_TIDM3_ENID3_Pos) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM3_ENID3 GMAC_TIDM3_ENID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM3_ENID3_Msk instead */ +#define GMAC_TIDM3_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM3) Register MASK (Use GMAC_TIDM3_Msk instead) */ +#define GMAC_TIDM3_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM3) Register Mask */ + +#define GMAC_TIDM3_ENID_Pos 31 /**< (GMAC_TIDM3 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM3_ENID_Msk (_U_(0x1) << GMAC_TIDM3_ENID_Pos) /**< (GMAC_TIDM3 Mask) ENID */ +#define GMAC_TIDM3_ENID(value) (GMAC_TIDM3_ENID_Msk & ((value) << GMAC_TIDM3_ENID_Pos)) + +/* -------- GMAC_TIDM4 : (GMAC Offset: 0xb4) (R/W 32) Type ID Match 4 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TID:16; /**< bit: 0..15 Type ID Match 4 */ + uint32_t :15; /**< bit: 16..30 Reserved */ + uint32_t ENID4:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :31; /**< bit: 0..30 Reserved */ + uint32_t ENID:1; /**< bit: 31 Enable Copying of TID Matched Frames */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TIDM4_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TIDM4_OFFSET (0xB4) /**< (GMAC_TIDM4) Type ID Match 4 Register Offset */ + +#define GMAC_TIDM4_TID_Pos 0 /**< (GMAC_TIDM4) Type ID Match 4 Position */ +#define GMAC_TIDM4_TID_Msk (_U_(0xFFFF) << GMAC_TIDM4_TID_Pos) /**< (GMAC_TIDM4) Type ID Match 4 Mask */ +#define GMAC_TIDM4_TID(value) (GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)) +#define GMAC_TIDM4_ENID4_Pos 31 /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM4_ENID4_Msk (_U_(0x1) << GMAC_TIDM4_ENID4_Pos) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM4_ENID4 GMAC_TIDM4_ENID4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TIDM4_ENID4_Msk instead */ +#define GMAC_TIDM4_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_TIDM4) Register MASK (Use GMAC_TIDM4_Msk instead) */ +#define GMAC_TIDM4_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM4) Register Mask */ + +#define GMAC_TIDM4_ENID_Pos 31 /**< (GMAC_TIDM4 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM4_ENID_Msk (_U_(0x1) << GMAC_TIDM4_ENID_Pos) /**< (GMAC_TIDM4 Mask) ENID */ +#define GMAC_TIDM4_ENID(value) (GMAC_TIDM4_ENID_Msk & ((value) << GMAC_TIDM4_ENID_Pos)) + +/* -------- GMAC_WOL : (GMAC Offset: 0xb8) (R/W 32) Wake on LAN Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IP:16; /**< bit: 0..15 ARP Request IP Address */ + uint32_t MAG:1; /**< bit: 16 Magic Packet Event Enable */ + uint32_t ARP:1; /**< bit: 17 ARP Request IP Address */ + uint32_t SA1:1; /**< bit: 18 Specific Address Register 1 Event Enable */ + uint32_t MTI:1; /**< bit: 19 Multicast Hash Event Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :18; /**< bit: 0..17 Reserved */ + uint32_t SA:1; /**< bit: 18 Specific Address Register x Event Enable */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_WOL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_WOL_OFFSET (0xB8) /**< (GMAC_WOL) Wake on LAN Register Offset */ + +#define GMAC_WOL_IP_Pos 0 /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)) +#define GMAC_WOL_MAG_Pos 16 /**< (GMAC_WOL) Magic Packet Event Enable Position */ +#define GMAC_WOL_MAG_Msk (_U_(0x1) << GMAC_WOL_MAG_Pos) /**< (GMAC_WOL) Magic Packet Event Enable Mask */ +#define GMAC_WOL_MAG GMAC_WOL_MAG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MAG_Msk instead */ +#define GMAC_WOL_ARP_Pos 17 /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_ARP_Msk (_U_(0x1) << GMAC_WOL_ARP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_ARP GMAC_WOL_ARP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_ARP_Msk instead */ +#define GMAC_WOL_SA1_Pos 18 /**< (GMAC_WOL) Specific Address Register 1 Event Enable Position */ +#define GMAC_WOL_SA1_Msk (_U_(0x1) << GMAC_WOL_SA1_Pos) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Mask */ +#define GMAC_WOL_SA1 GMAC_WOL_SA1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_SA1_Msk instead */ +#define GMAC_WOL_MTI_Pos 19 /**< (GMAC_WOL) Multicast Hash Event Enable Position */ +#define GMAC_WOL_MTI_Msk (_U_(0x1) << GMAC_WOL_MTI_Pos) /**< (GMAC_WOL) Multicast Hash Event Enable Mask */ +#define GMAC_WOL_MTI GMAC_WOL_MTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_WOL_MTI_Msk instead */ +#define GMAC_WOL_MASK _U_(0xFFFFF) /**< \deprecated (GMAC_WOL) Register MASK (Use GMAC_WOL_Msk instead) */ +#define GMAC_WOL_Msk _U_(0xFFFFF) /**< (GMAC_WOL) Register Mask */ + +#define GMAC_WOL_SA_Pos 18 /**< (GMAC_WOL Position) Specific Address Register x Event Enable */ +#define GMAC_WOL_SA_Msk (_U_(0x1) << GMAC_WOL_SA_Pos) /**< (GMAC_WOL Mask) SA */ +#define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & ((value) << GMAC_WOL_SA_Pos)) + +/* -------- GMAC_IPGS : (GMAC Offset: 0xbc) (R/W 32) IPG Stretch Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FL:16; /**< bit: 0..15 Frame Length */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IPGS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IPGS_OFFSET (0xBC) /**< (GMAC_IPGS) IPG Stretch Register Offset */ + +#define GMAC_IPGS_FL_Pos 0 /**< (GMAC_IPGS) Frame Length Position */ +#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos) /**< (GMAC_IPGS) Frame Length Mask */ +#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)) +#define GMAC_IPGS_MASK _U_(0xFFFF) /**< \deprecated (GMAC_IPGS) Register MASK (Use GMAC_IPGS_Msk instead) */ +#define GMAC_IPGS_Msk _U_(0xFFFF) /**< (GMAC_IPGS) Register Mask */ + + +/* -------- GMAC_SVLAN : (GMAC Offset: 0xc0) (R/W 32) Stacked VLAN Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t VLAN_TYPE:16; /**< bit: 0..15 User Defined VLAN_TYPE Field */ + uint32_t :15; /**< bit: 16..30 Reserved */ + uint32_t ESVLAN:1; /**< bit: 31 Enable Stacked VLAN Processing Mode */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SVLAN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SVLAN_OFFSET (0xC0) /**< (GMAC_SVLAN) Stacked VLAN Register Offset */ + +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ +#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ +#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)) +#define GMAC_SVLAN_ESVLAN_Pos 31 /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ +#define GMAC_SVLAN_ESVLAN_Msk (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ +#define GMAC_SVLAN_ESVLAN GMAC_SVLAN_ESVLAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_SVLAN_ESVLAN_Msk instead */ +#define GMAC_SVLAN_MASK _U_(0x8000FFFF) /**< \deprecated (GMAC_SVLAN) Register MASK (Use GMAC_SVLAN_Msk instead) */ +#define GMAC_SVLAN_Msk _U_(0x8000FFFF) /**< (GMAC_SVLAN) Register Mask */ + + +/* -------- GMAC_TPFCP : (GMAC Offset: 0xc4) (R/W 32) Transmit PFC Pause Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PEV:8; /**< bit: 0..7 Priority Enable Vector */ + uint32_t PQ:8; /**< bit: 8..15 Pause Quantum */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TPFCP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TPFCP_OFFSET (0xC4) /**< (GMAC_TPFCP) Transmit PFC Pause Register Offset */ + +#define GMAC_TPFCP_PEV_Pos 0 /**< (GMAC_TPFCP) Priority Enable Vector Position */ +#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos) /**< (GMAC_TPFCP) Priority Enable Vector Mask */ +#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)) +#define GMAC_TPFCP_PQ_Pos 8 /**< (GMAC_TPFCP) Pause Quantum Position */ +#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos) /**< (GMAC_TPFCP) Pause Quantum Mask */ +#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)) +#define GMAC_TPFCP_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TPFCP) Register MASK (Use GMAC_TPFCP_Msk instead) */ +#define GMAC_TPFCP_Msk _U_(0xFFFF) /**< (GMAC_TPFCP) Register Mask */ + + +/* -------- GMAC_SAMB1 : (GMAC Offset: 0xc8) (R/W 32) Specific Address 1 Mask Bottom Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:32; /**< bit: 0..31 Specific Address 1 Mask */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SAMB1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SAMB1_OFFSET (0xC8) /**< (GMAC_SAMB1) Specific Address 1 Mask Bottom Register Offset */ + +#define GMAC_SAMB1_ADDR_Pos 0 /**< (GMAC_SAMB1) Specific Address 1 Mask Position */ +#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /**< (GMAC_SAMB1) Specific Address 1 Mask Mask */ +#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)) +#define GMAC_SAMB1_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SAMB1) Register MASK (Use GMAC_SAMB1_Msk instead) */ +#define GMAC_SAMB1_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAMB1) Register Mask */ + + +/* -------- GMAC_SAMT1 : (GMAC Offset: 0xcc) (R/W 32) Specific Address 1 Mask Top Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:16; /**< bit: 0..15 Specific Address 1 Mask */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SAMT1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SAMT1_OFFSET (0xCC) /**< (GMAC_SAMT1) Specific Address 1 Mask Top Register Offset */ + +#define GMAC_SAMT1_ADDR_Pos 0 /**< (GMAC_SAMT1) Specific Address 1 Mask Position */ +#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /**< (GMAC_SAMT1) Specific Address 1 Mask Mask */ +#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)) +#define GMAC_SAMT1_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SAMT1) Register MASK (Use GMAC_SAMT1_Msk instead) */ +#define GMAC_SAMT1_Msk _U_(0xFFFF) /**< (GMAC_SAMT1) Register Mask */ + + +/* -------- GMAC_NSC : (GMAC Offset: 0xdc) (R/W 32) 1588 Timer Nanosecond Comparison Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NANOSEC:22; /**< bit: 0..21 1588 Timer Nanosecond Comparison Value */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_NSC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_NSC_OFFSET (0xDC) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Register Offset */ + +#define GMAC_NSC_NANOSEC_Pos 0 /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Position */ +#define GMAC_NSC_NANOSEC_Msk (_U_(0x3FFFFF) << GMAC_NSC_NANOSEC_Pos) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Mask */ +#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)) +#define GMAC_NSC_MASK _U_(0x3FFFFF) /**< \deprecated (GMAC_NSC) Register MASK (Use GMAC_NSC_Msk instead) */ +#define GMAC_NSC_Msk _U_(0x3FFFFF) /**< (GMAC_NSC) Register Mask */ + + +/* -------- GMAC_SCL : (GMAC Offset: 0xe0) (R/W 32) 1588 Timer Second Comparison Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SEC:32; /**< bit: 0..31 1588 Timer Second Comparison Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SCL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SCL_OFFSET (0xE0) /**< (GMAC_SCL) 1588 Timer Second Comparison Low Register Offset */ + +#define GMAC_SCL_SEC_Pos 0 /**< (GMAC_SCL) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)) +#define GMAC_SCL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_SCL) Register MASK (Use GMAC_SCL_Msk instead) */ +#define GMAC_SCL_Msk _U_(0xFFFFFFFF) /**< (GMAC_SCL) Register Mask */ + + +/* -------- GMAC_SCH : (GMAC Offset: 0xe4) (R/W 32) 1588 Timer Second Comparison High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SEC:16; /**< bit: 0..15 1588 Timer Second Comparison Value */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SCH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SCH_OFFSET (0xE4) /**< (GMAC_SCH) 1588 Timer Second Comparison High Register Offset */ + +#define GMAC_SCH_SEC_Pos 0 /**< (GMAC_SCH) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)) +#define GMAC_SCH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_SCH) Register MASK (Use GMAC_SCH_Msk instead) */ +#define GMAC_SCH_Msk _U_(0xFFFF) /**< (GMAC_SCH) Register Mask */ + + +/* -------- GMAC_EFTSH : (GMAC Offset: 0xe8) (R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:16; /**< bit: 0..15 Register Update */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFTSH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFTSH_OFFSET (0xE8) /**< (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ + +#define GMAC_EFTSH_RUD_Pos 0 /**< (GMAC_EFTSH) Register Update Position */ +#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /**< (GMAC_EFTSH) Register Update Mask */ +#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos)) +#define GMAC_EFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFTSH) Register MASK (Use GMAC_EFTSH_Msk instead) */ +#define GMAC_EFTSH_Msk _U_(0xFFFF) /**< (GMAC_EFTSH) Register Mask */ + + +/* -------- GMAC_EFRSH : (GMAC Offset: 0xec) (R/ 32) PTP Event Frame Received Seconds High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:16; /**< bit: 0..15 Register Update */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFRSH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFRSH_OFFSET (0xEC) /**< (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ + +#define GMAC_EFRSH_RUD_Pos 0 /**< (GMAC_EFRSH) Register Update Position */ +#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /**< (GMAC_EFRSH) Register Update Mask */ +#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos)) +#define GMAC_EFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_EFRSH) Register MASK (Use GMAC_EFRSH_Msk instead) */ +#define GMAC_EFRSH_Msk _U_(0xFFFF) /**< (GMAC_EFRSH) Register Mask */ + + +/* -------- GMAC_PEFTSH : (GMAC Offset: 0xf0) (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:16; /**< bit: 0..15 Register Update */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFTSH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFTSH_OFFSET (0xF0) /**< (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ + +#define GMAC_PEFTSH_RUD_Pos 0 /**< (GMAC_PEFTSH) Register Update Position */ +#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /**< (GMAC_PEFTSH) Register Update Mask */ +#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos)) +#define GMAC_PEFTSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFTSH) Register MASK (Use GMAC_PEFTSH_Msk instead) */ +#define GMAC_PEFTSH_Msk _U_(0xFFFF) /**< (GMAC_PEFTSH) Register Mask */ + + +/* -------- GMAC_PEFRSH : (GMAC Offset: 0xf4) (R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:16; /**< bit: 0..15 Register Update */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFRSH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFRSH_OFFSET (0xF4) /**< (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ + +#define GMAC_PEFRSH_RUD_Pos 0 /**< (GMAC_PEFRSH) Register Update Position */ +#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /**< (GMAC_PEFRSH) Register Update Mask */ +#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos)) +#define GMAC_PEFRSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PEFRSH) Register MASK (Use GMAC_PEFRSH_Msk instead) */ +#define GMAC_PEFRSH_Msk _U_(0xFFFF) /**< (GMAC_PEFRSH) Register Mask */ + + +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) (R/ 32) Octets Transmitted Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXO:32; /**< bit: 0..31 Transmitted Octets */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_OTLO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_OTLO_OFFSET (0x100) /**< (GMAC_OTLO) Octets Transmitted Low Register Offset */ + +#define GMAC_OTLO_TXO_Pos 0 /**< (GMAC_OTLO) Transmitted Octets Position */ +#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /**< (GMAC_OTLO) Transmitted Octets Mask */ +#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos)) +#define GMAC_OTLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_OTLO) Register MASK (Use GMAC_OTLO_Msk instead) */ +#define GMAC_OTLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_OTLO) Register Mask */ + + +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) (R/ 32) Octets Transmitted High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXO:16; /**< bit: 0..15 Transmitted Octets */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_OTHI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_OTHI_OFFSET (0x104) /**< (GMAC_OTHI) Octets Transmitted High Register Offset */ + +#define GMAC_OTHI_TXO_Pos 0 /**< (GMAC_OTHI) Transmitted Octets Position */ +#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos) /**< (GMAC_OTHI) Transmitted Octets Mask */ +#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos)) +#define GMAC_OTHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_OTHI) Register MASK (Use GMAC_OTHI_Msk instead) */ +#define GMAC_OTHI_Msk _U_(0xFFFF) /**< (GMAC_OTHI) Register Mask */ + + +/* -------- GMAC_FT : (GMAC Offset: 0x108) (R/ 32) Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FTX:32; /**< bit: 0..31 Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_FT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_FT_OFFSET (0x108) /**< (GMAC_FT) Frames Transmitted Register Offset */ + +#define GMAC_FT_FTX_Pos 0 /**< (GMAC_FT) Frames Transmitted without Error Position */ +#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /**< (GMAC_FT) Frames Transmitted without Error Mask */ +#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos)) +#define GMAC_FT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FT) Register MASK (Use GMAC_FT_Msk instead) */ +#define GMAC_FT_Msk _U_(0xFFFFFFFF) /**< (GMAC_FT) Register Mask */ + + +/* -------- GMAC_BCFT : (GMAC Offset: 0x10c) (R/ 32) Broadcast Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BFTX:32; /**< bit: 0..31 Broadcast Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_BCFT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_BCFT_OFFSET (0x10C) /**< (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ + +#define GMAC_BCFT_BFTX_Pos 0 /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ +#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ +#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos)) +#define GMAC_BCFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFT) Register MASK (Use GMAC_BCFT_Msk instead) */ +#define GMAC_BCFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFT) Register Mask */ + + +/* -------- GMAC_MFT : (GMAC Offset: 0x110) (R/ 32) Multicast Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFTX:32; /**< bit: 0..31 Multicast Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_MFT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_MFT_OFFSET (0x110) /**< (GMAC_MFT) Multicast Frames Transmitted Register Offset */ + +#define GMAC_MFT_MFTX_Pos 0 /**< (GMAC_MFT) Multicast Frames Transmitted without Error Position */ +#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ +#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos)) +#define GMAC_MFT_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFT) Register MASK (Use GMAC_MFT_Msk instead) */ +#define GMAC_MFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFT) Register Mask */ + + +/* -------- GMAC_PFT : (GMAC Offset: 0x114) (R/ 32) Pause Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PFTX:16; /**< bit: 0..15 Pause Frames Transmitted Register */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PFT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PFT_OFFSET (0x114) /**< (GMAC_PFT) Pause Frames Transmitted Register Offset */ + +#define GMAC_PFT_PFTX_Pos 0 /**< (GMAC_PFT) Pause Frames Transmitted Register Position */ +#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos) /**< (GMAC_PFT) Pause Frames Transmitted Register Mask */ +#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos)) +#define GMAC_PFT_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFT) Register MASK (Use GMAC_PFT_Msk instead) */ +#define GMAC_PFT_Msk _U_(0xFFFF) /**< (GMAC_PFT) Register Mask */ + + +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) (R/ 32) 64 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 64 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_BFT64_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_BFT64_OFFSET (0x118) /**< (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ + +#define GMAC_BFT64_NFTX_Pos 0 /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ +#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ +#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos)) +#define GMAC_BFT64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFT64) Register MASK (Use GMAC_BFT64_Msk instead) */ +#define GMAC_BFT64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFT64) Register Mask */ + + +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11c) (R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 65 to 127 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFT127_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFT127_OFFSET (0x11C) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ + +#define GMAC_TBFT127_NFTX_Pos 0 /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos)) +#define GMAC_TBFT127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT127) Register MASK (Use GMAC_TBFT127_Msk instead) */ +#define GMAC_TBFT127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT127) Register Mask */ + + +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) (R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 128 to 255 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFT255_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFT255_OFFSET (0x120) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ + +#define GMAC_TBFT255_NFTX_Pos 0 /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos)) +#define GMAC_TBFT255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT255) Register MASK (Use GMAC_TBFT255_Msk instead) */ +#define GMAC_TBFT255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT255) Register Mask */ + + +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) (R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 256 to 511 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFT511_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFT511_OFFSET (0x124) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ + +#define GMAC_TBFT511_NFTX_Pos 0 /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos)) +#define GMAC_TBFT511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT511) Register MASK (Use GMAC_TBFT511_Msk instead) */ +#define GMAC_TBFT511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT511) Register Mask */ + + +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) (R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 512 to 1023 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFT1023_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFT1023_OFFSET (0x128) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ + +#define GMAC_TBFT1023_NFTX_Pos 0 /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos)) +#define GMAC_TBFT1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1023) Register MASK (Use GMAC_TBFT1023_Msk instead) */ +#define GMAC_TBFT1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1023) Register Mask */ + + +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12c) (R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFT1518_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFT1518_OFFSET (0x12C) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ + +#define GMAC_TBFT1518_NFTX_Pos 0 /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos)) +#define GMAC_TBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFT1518) Register MASK (Use GMAC_TBFT1518_Msk instead) */ +#define GMAC_TBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1518) Register Mask */ + + +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) (R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFTX:32; /**< bit: 0..31 Greater than 1518 Byte Frames Transmitted without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_GTBFT1518_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_GTBFT1518_OFFSET (0x130) /**< (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ + +#define GMAC_GTBFT1518_NFTX_Pos 0 /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos)) +#define GMAC_GTBFT1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_GTBFT1518) Register MASK (Use GMAC_GTBFT1518_Msk instead) */ +#define GMAC_GTBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_GTBFT1518) Register Mask */ + + +/* -------- GMAC_TUR : (GMAC Offset: 0x134) (R/ 32) Transmit Underruns Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXUNR:10; /**< bit: 0..9 Transmit Underruns */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TUR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TUR_OFFSET (0x134) /**< (GMAC_TUR) Transmit Underruns Register Offset */ + +#define GMAC_TUR_TXUNR_Pos 0 /**< (GMAC_TUR) Transmit Underruns Position */ +#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos) /**< (GMAC_TUR) Transmit Underruns Mask */ +#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos)) +#define GMAC_TUR_MASK _U_(0x3FF) /**< \deprecated (GMAC_TUR) Register MASK (Use GMAC_TUR_Msk instead) */ +#define GMAC_TUR_Msk _U_(0x3FF) /**< (GMAC_TUR) Register Mask */ + + +/* -------- GMAC_SCF : (GMAC Offset: 0x138) (R/ 32) Single Collision Frames Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SCOL:18; /**< bit: 0..17 Single Collision */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_SCF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_SCF_OFFSET (0x138) /**< (GMAC_SCF) Single Collision Frames Register Offset */ + +#define GMAC_SCF_SCOL_Pos 0 /**< (GMAC_SCF) Single Collision Position */ +#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /**< (GMAC_SCF) Single Collision Mask */ +#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos)) +#define GMAC_SCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_SCF) Register MASK (Use GMAC_SCF_Msk instead) */ +#define GMAC_SCF_Msk _U_(0x3FFFF) /**< (GMAC_SCF) Register Mask */ + + +/* -------- GMAC_MCF : (GMAC Offset: 0x13c) (R/ 32) Multiple Collision Frames Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MCOL:18; /**< bit: 0..17 Multiple Collision */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_MCF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_MCF_OFFSET (0x13C) /**< (GMAC_MCF) Multiple Collision Frames Register Offset */ + +#define GMAC_MCF_MCOL_Pos 0 /**< (GMAC_MCF) Multiple Collision Position */ +#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /**< (GMAC_MCF) Multiple Collision Mask */ +#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos)) +#define GMAC_MCF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_MCF) Register MASK (Use GMAC_MCF_Msk instead) */ +#define GMAC_MCF_Msk _U_(0x3FFFF) /**< (GMAC_MCF) Register Mask */ + + +/* -------- GMAC_EC : (GMAC Offset: 0x140) (R/ 32) Excessive Collisions Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t XCOL:10; /**< bit: 0..9 Excessive Collisions */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EC_OFFSET (0x140) /**< (GMAC_EC) Excessive Collisions Register Offset */ + +#define GMAC_EC_XCOL_Pos 0 /**< (GMAC_EC) Excessive Collisions Position */ +#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos) /**< (GMAC_EC) Excessive Collisions Mask */ +#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos)) +#define GMAC_EC_MASK _U_(0x3FF) /**< \deprecated (GMAC_EC) Register MASK (Use GMAC_EC_Msk instead) */ +#define GMAC_EC_Msk _U_(0x3FF) /**< (GMAC_EC) Register Mask */ + + +/* -------- GMAC_LC : (GMAC Offset: 0x144) (R/ 32) Late Collisions Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LCOL:10; /**< bit: 0..9 Late Collisions */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_LC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_LC_OFFSET (0x144) /**< (GMAC_LC) Late Collisions Register Offset */ + +#define GMAC_LC_LCOL_Pos 0 /**< (GMAC_LC) Late Collisions Position */ +#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos) /**< (GMAC_LC) Late Collisions Mask */ +#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos)) +#define GMAC_LC_MASK _U_(0x3FF) /**< \deprecated (GMAC_LC) Register MASK (Use GMAC_LC_Msk instead) */ +#define GMAC_LC_Msk _U_(0x3FF) /**< (GMAC_LC) Register Mask */ + + +/* -------- GMAC_DTF : (GMAC Offset: 0x148) (R/ 32) Deferred Transmission Frames Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DEFT:18; /**< bit: 0..17 Deferred Transmission */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_DTF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_DTF_OFFSET (0x148) /**< (GMAC_DTF) Deferred Transmission Frames Register Offset */ + +#define GMAC_DTF_DEFT_Pos 0 /**< (GMAC_DTF) Deferred Transmission Position */ +#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /**< (GMAC_DTF) Deferred Transmission Mask */ +#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos)) +#define GMAC_DTF_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_DTF) Register MASK (Use GMAC_DTF_Msk instead) */ +#define GMAC_DTF_Msk _U_(0x3FFFF) /**< (GMAC_DTF) Register Mask */ + + +/* -------- GMAC_CSE : (GMAC Offset: 0x14c) (R/ 32) Carrier Sense Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSR:10; /**< bit: 0..9 Carrier Sense Error */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_CSE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_CSE_OFFSET (0x14C) /**< (GMAC_CSE) Carrier Sense Errors Register Offset */ + +#define GMAC_CSE_CSR_Pos 0 /**< (GMAC_CSE) Carrier Sense Error Position */ +#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos) /**< (GMAC_CSE) Carrier Sense Error Mask */ +#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos)) +#define GMAC_CSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_CSE) Register MASK (Use GMAC_CSE_Msk instead) */ +#define GMAC_CSE_Msk _U_(0x3FF) /**< (GMAC_CSE) Register Mask */ + + +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) (R/ 32) Octets Received Low Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXO:32; /**< bit: 0..31 Received Octets */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ORLO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ORLO_OFFSET (0x150) /**< (GMAC_ORLO) Octets Received Low Received Register Offset */ + +#define GMAC_ORLO_RXO_Pos 0 /**< (GMAC_ORLO) Received Octets Position */ +#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /**< (GMAC_ORLO) Received Octets Mask */ +#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos)) +#define GMAC_ORLO_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_ORLO) Register MASK (Use GMAC_ORLO_Msk instead) */ +#define GMAC_ORLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_ORLO) Register Mask */ + + +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) (R/ 32) Octets Received High Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXO:16; /**< bit: 0..15 Received Octets */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ORHI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ORHI_OFFSET (0x154) /**< (GMAC_ORHI) Octets Received High Received Register Offset */ + +#define GMAC_ORHI_RXO_Pos 0 /**< (GMAC_ORHI) Received Octets Position */ +#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos) /**< (GMAC_ORHI) Received Octets Mask */ +#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos)) +#define GMAC_ORHI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ORHI) Register MASK (Use GMAC_ORHI_Msk instead) */ +#define GMAC_ORHI_Msk _U_(0xFFFF) /**< (GMAC_ORHI) Register Mask */ + + +/* -------- GMAC_FR : (GMAC Offset: 0x158) (R/ 32) Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FRX:32; /**< bit: 0..31 Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_FR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_FR_OFFSET (0x158) /**< (GMAC_FR) Frames Received Register Offset */ + +#define GMAC_FR_FRX_Pos 0 /**< (GMAC_FR) Frames Received without Error Position */ +#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /**< (GMAC_FR) Frames Received without Error Mask */ +#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos)) +#define GMAC_FR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_FR) Register MASK (Use GMAC_FR_Msk instead) */ +#define GMAC_FR_Msk _U_(0xFFFFFFFF) /**< (GMAC_FR) Register Mask */ + + +/* -------- GMAC_BCFR : (GMAC Offset: 0x15c) (R/ 32) Broadcast Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BFRX:32; /**< bit: 0..31 Broadcast Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_BCFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_BCFR_OFFSET (0x15C) /**< (GMAC_BCFR) Broadcast Frames Received Register Offset */ + +#define GMAC_BCFR_BFRX_Pos 0 /**< (GMAC_BCFR) Broadcast Frames Received without Error Position */ +#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /**< (GMAC_BCFR) Broadcast Frames Received without Error Mask */ +#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos)) +#define GMAC_BCFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BCFR) Register MASK (Use GMAC_BCFR_Msk instead) */ +#define GMAC_BCFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFR) Register Mask */ + + +/* -------- GMAC_MFR : (GMAC Offset: 0x160) (R/ 32) Multicast Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFRX:32; /**< bit: 0..31 Multicast Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_MFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_MFR_OFFSET (0x160) /**< (GMAC_MFR) Multicast Frames Received Register Offset */ + +#define GMAC_MFR_MFRX_Pos 0 /**< (GMAC_MFR) Multicast Frames Received without Error Position */ +#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /**< (GMAC_MFR) Multicast Frames Received without Error Mask */ +#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos)) +#define GMAC_MFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_MFR) Register MASK (Use GMAC_MFR_Msk instead) */ +#define GMAC_MFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFR) Register Mask */ + + +/* -------- GMAC_PFR : (GMAC Offset: 0x164) (R/ 32) Pause Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PFRX:16; /**< bit: 0..15 Pause Frames Received Register */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PFR_OFFSET (0x164) /**< (GMAC_PFR) Pause Frames Received Register Offset */ + +#define GMAC_PFR_PFRX_Pos 0 /**< (GMAC_PFR) Pause Frames Received Register Position */ +#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos) /**< (GMAC_PFR) Pause Frames Received Register Mask */ +#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos)) +#define GMAC_PFR_MASK _U_(0xFFFF) /**< \deprecated (GMAC_PFR) Register MASK (Use GMAC_PFR_Msk instead) */ +#define GMAC_PFR_Msk _U_(0xFFFF) /**< (GMAC_PFR) Register Mask */ + + +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) (R/ 32) 64 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 64 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_BFR64_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_BFR64_OFFSET (0x168) /**< (GMAC_BFR64) 64 Byte Frames Received Register Offset */ + +#define GMAC_BFR64_NFRX_Pos 0 /**< (GMAC_BFR64) 64 Byte Frames Received without Error Position */ +#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ +#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos)) +#define GMAC_BFR64_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_BFR64) Register MASK (Use GMAC_BFR64_Msk instead) */ +#define GMAC_BFR64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFR64) Register Mask */ + + +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16c) (R/ 32) 65 to 127 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 65 to 127 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFR127_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFR127_OFFSET (0x16C) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ + +#define GMAC_TBFR127_NFRX_Pos 0 /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ +#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ +#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos)) +#define GMAC_TBFR127_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR127) Register MASK (Use GMAC_TBFR127_Msk instead) */ +#define GMAC_TBFR127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR127) Register Mask */ + + +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) (R/ 32) 128 to 255 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 128 to 255 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFR255_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFR255_OFFSET (0x170) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ + +#define GMAC_TBFR255_NFRX_Pos 0 /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ +#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ +#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos)) +#define GMAC_TBFR255_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR255) Register MASK (Use GMAC_TBFR255_Msk instead) */ +#define GMAC_TBFR255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR255) Register Mask */ + + +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) (R/ 32) 256 to 511 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 256 to 511 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFR511_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFR511_OFFSET (0x174) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received Register Offset */ + +#define GMAC_TBFR511_NFRX_Pos 0 /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ +#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ +#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos)) +#define GMAC_TBFR511_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR511) Register MASK (Use GMAC_TBFR511_Msk instead) */ +#define GMAC_TBFR511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR511) Register Mask */ + + +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) (R/ 32) 512 to 1023 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 512 to 1023 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFR1023_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFR1023_OFFSET (0x178) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ + +#define GMAC_TBFR1023_NFRX_Pos 0 /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ +#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos)) +#define GMAC_TBFR1023_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1023) Register MASK (Use GMAC_TBFR1023_Msk instead) */ +#define GMAC_TBFR1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1023) Register Mask */ + + +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17c) (R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 1024 to 1518 Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBFR1518_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBFR1518_OFFSET (0x17C) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ + +#define GMAC_TBFR1518_NFRX_Pos 0 /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ +#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos)) +#define GMAC_TBFR1518_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TBFR1518) Register MASK (Use GMAC_TBFR1518_Msk instead) */ +#define GMAC_TBFR1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1518) Register Mask */ + + +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) (R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NFRX:32; /**< bit: 0..31 1519 to Maximum Byte Frames Received without Error */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TMXBFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TMXBFR_OFFSET (0x180) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ + +#define GMAC_TMXBFR_NFRX_Pos 0 /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ +#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ +#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos)) +#define GMAC_TMXBFR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TMXBFR) Register MASK (Use GMAC_TMXBFR_Msk instead) */ +#define GMAC_TMXBFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_TMXBFR) Register Mask */ + + +/* -------- GMAC_UFR : (GMAC Offset: 0x184) (R/ 32) Undersize Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UFRX:10; /**< bit: 0..9 Undersize Frames Received */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_UFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_UFR_OFFSET (0x184) /**< (GMAC_UFR) Undersize Frames Received Register Offset */ + +#define GMAC_UFR_UFRX_Pos 0 /**< (GMAC_UFR) Undersize Frames Received Position */ +#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos) /**< (GMAC_UFR) Undersize Frames Received Mask */ +#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos)) +#define GMAC_UFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_UFR) Register MASK (Use GMAC_UFR_Msk instead) */ +#define GMAC_UFR_Msk _U_(0x3FF) /**< (GMAC_UFR) Register Mask */ + + +/* -------- GMAC_OFR : (GMAC Offset: 0x188) (R/ 32) Oversize Frames Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OFRX:10; /**< bit: 0..9 Oversized Frames Received */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_OFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_OFR_OFFSET (0x188) /**< (GMAC_OFR) Oversize Frames Received Register Offset */ + +#define GMAC_OFR_OFRX_Pos 0 /**< (GMAC_OFR) Oversized Frames Received Position */ +#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos) /**< (GMAC_OFR) Oversized Frames Received Mask */ +#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos)) +#define GMAC_OFR_MASK _U_(0x3FF) /**< \deprecated (GMAC_OFR) Register MASK (Use GMAC_OFR_Msk instead) */ +#define GMAC_OFR_Msk _U_(0x3FF) /**< (GMAC_OFR) Register Mask */ + + +/* -------- GMAC_JR : (GMAC Offset: 0x18c) (R/ 32) Jabbers Received Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t JRX:10; /**< bit: 0..9 Jabbers Received */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_JR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_JR_OFFSET (0x18C) /**< (GMAC_JR) Jabbers Received Register Offset */ + +#define GMAC_JR_JRX_Pos 0 /**< (GMAC_JR) Jabbers Received Position */ +#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos) /**< (GMAC_JR) Jabbers Received Mask */ +#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos)) +#define GMAC_JR_MASK _U_(0x3FF) /**< \deprecated (GMAC_JR) Register MASK (Use GMAC_JR_Msk instead) */ +#define GMAC_JR_Msk _U_(0x3FF) /**< (GMAC_JR) Register Mask */ + + +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) (R/ 32) Frame Check Sequence Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FCKR:10; /**< bit: 0..9 Frame Check Sequence Errors */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_FCSE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_FCSE_OFFSET (0x190) /**< (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ + +#define GMAC_FCSE_FCKR_Pos 0 /**< (GMAC_FCSE) Frame Check Sequence Errors Position */ +#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos) /**< (GMAC_FCSE) Frame Check Sequence Errors Mask */ +#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos)) +#define GMAC_FCSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_FCSE) Register MASK (Use GMAC_FCSE_Msk instead) */ +#define GMAC_FCSE_Msk _U_(0x3FF) /**< (GMAC_FCSE) Register Mask */ + + +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) (R/ 32) Length Field Frame Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LFER:10; /**< bit: 0..9 Length Field Frame Errors */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_LFFE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_LFFE_OFFSET (0x194) /**< (GMAC_LFFE) Length Field Frame Errors Register Offset */ + +#define GMAC_LFFE_LFER_Pos 0 /**< (GMAC_LFFE) Length Field Frame Errors Position */ +#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos) /**< (GMAC_LFFE) Length Field Frame Errors Mask */ +#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos)) +#define GMAC_LFFE_MASK _U_(0x3FF) /**< \deprecated (GMAC_LFFE) Register MASK (Use GMAC_LFFE_Msk instead) */ +#define GMAC_LFFE_Msk _U_(0x3FF) /**< (GMAC_LFFE) Register Mask */ + + +/* -------- GMAC_RSE : (GMAC Offset: 0x198) (R/ 32) Receive Symbol Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXSE:10; /**< bit: 0..9 Receive Symbol Errors */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RSE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RSE_OFFSET (0x198) /**< (GMAC_RSE) Receive Symbol Errors Register Offset */ + +#define GMAC_RSE_RXSE_Pos 0 /**< (GMAC_RSE) Receive Symbol Errors Position */ +#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos) /**< (GMAC_RSE) Receive Symbol Errors Mask */ +#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos)) +#define GMAC_RSE_MASK _U_(0x3FF) /**< \deprecated (GMAC_RSE) Register MASK (Use GMAC_RSE_Msk instead) */ +#define GMAC_RSE_Msk _U_(0x3FF) /**< (GMAC_RSE) Register Mask */ + + +/* -------- GMAC_AE : (GMAC Offset: 0x19c) (R/ 32) Alignment Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t AER:10; /**< bit: 0..9 Alignment Errors */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_AE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_AE_OFFSET (0x19C) /**< (GMAC_AE) Alignment Errors Register Offset */ + +#define GMAC_AE_AER_Pos 0 /**< (GMAC_AE) Alignment Errors Position */ +#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos) /**< (GMAC_AE) Alignment Errors Mask */ +#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos)) +#define GMAC_AE_MASK _U_(0x3FF) /**< \deprecated (GMAC_AE) Register MASK (Use GMAC_AE_Msk instead) */ +#define GMAC_AE_Msk _U_(0x3FF) /**< (GMAC_AE) Register Mask */ + + +/* -------- GMAC_RRE : (GMAC Offset: 0x1a0) (R/ 32) Receive Resource Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRER:18; /**< bit: 0..17 Receive Resource Errors */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RRE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RRE_OFFSET (0x1A0) /**< (GMAC_RRE) Receive Resource Errors Register Offset */ + +#define GMAC_RRE_RXRER_Pos 0 /**< (GMAC_RRE) Receive Resource Errors Position */ +#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /**< (GMAC_RRE) Receive Resource Errors Mask */ +#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos)) +#define GMAC_RRE_MASK _U_(0x3FFFF) /**< \deprecated (GMAC_RRE) Register MASK (Use GMAC_RRE_Msk instead) */ +#define GMAC_RRE_Msk _U_(0x3FFFF) /**< (GMAC_RRE) Register Mask */ + + +/* -------- GMAC_ROE : (GMAC Offset: 0x1a4) (R/ 32) Receive Overrun Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXOVR:10; /**< bit: 0..9 Receive Overruns */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ROE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ROE_OFFSET (0x1A4) /**< (GMAC_ROE) Receive Overrun Register Offset */ + +#define GMAC_ROE_RXOVR_Pos 0 /**< (GMAC_ROE) Receive Overruns Position */ +#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos) /**< (GMAC_ROE) Receive Overruns Mask */ +#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos)) +#define GMAC_ROE_MASK _U_(0x3FF) /**< \deprecated (GMAC_ROE) Register MASK (Use GMAC_ROE_Msk instead) */ +#define GMAC_ROE_Msk _U_(0x3FF) /**< (GMAC_ROE) Register Mask */ + + +/* -------- GMAC_IHCE : (GMAC Offset: 0x1a8) (R/ 32) IP Header Checksum Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HCKER:8; /**< bit: 0..7 IP Header Checksum Errors */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IHCE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IHCE_OFFSET (0x1A8) /**< (GMAC_IHCE) IP Header Checksum Errors Register Offset */ + +#define GMAC_IHCE_HCKER_Pos 0 /**< (GMAC_IHCE) IP Header Checksum Errors Position */ +#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos) /**< (GMAC_IHCE) IP Header Checksum Errors Mask */ +#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos)) +#define GMAC_IHCE_MASK _U_(0xFF) /**< \deprecated (GMAC_IHCE) Register MASK (Use GMAC_IHCE_Msk instead) */ +#define GMAC_IHCE_Msk _U_(0xFF) /**< (GMAC_IHCE) Register Mask */ + + +/* -------- GMAC_TCE : (GMAC Offset: 0x1ac) (R/ 32) TCP Checksum Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TCKER:8; /**< bit: 0..7 TCP Checksum Errors */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TCE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TCE_OFFSET (0x1AC) /**< (GMAC_TCE) TCP Checksum Errors Register Offset */ + +#define GMAC_TCE_TCKER_Pos 0 /**< (GMAC_TCE) TCP Checksum Errors Position */ +#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos) /**< (GMAC_TCE) TCP Checksum Errors Mask */ +#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos)) +#define GMAC_TCE_MASK _U_(0xFF) /**< \deprecated (GMAC_TCE) Register MASK (Use GMAC_TCE_Msk instead) */ +#define GMAC_TCE_Msk _U_(0xFF) /**< (GMAC_TCE) Register Mask */ + + +/* -------- GMAC_UCE : (GMAC Offset: 0x1b0) (R/ 32) UDP Checksum Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UCKER:8; /**< bit: 0..7 UDP Checksum Errors */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_UCE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_UCE_OFFSET (0x1B0) /**< (GMAC_UCE) UDP Checksum Errors Register Offset */ + +#define GMAC_UCE_UCKER_Pos 0 /**< (GMAC_UCE) UDP Checksum Errors Position */ +#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos) /**< (GMAC_UCE) UDP Checksum Errors Mask */ +#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos)) +#define GMAC_UCE_MASK _U_(0xFF) /**< \deprecated (GMAC_UCE) Register MASK (Use GMAC_UCE_Msk instead) */ +#define GMAC_UCE_Msk _U_(0xFF) /**< (GMAC_UCE) Register Mask */ + + +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1bc) (R/W 32) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LSBTIR:16; /**< bit: 0..15 Lower Significant Bits of Timer Increment Register */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TISUBN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TISUBN_OFFSET (0x1BC) /**< (GMAC_TISUBN) 1588 Timer Increment Sub-nanoseconds Register Offset */ + +#define GMAC_TISUBN_LSBTIR_Pos 0 /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Position */ +#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Mask */ +#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)) +#define GMAC_TISUBN_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TISUBN) Register MASK (Use GMAC_TISUBN_Msk instead) */ +#define GMAC_TISUBN_Msk _U_(0xFFFF) /**< (GMAC_TISUBN) Register Mask */ + + +/* -------- GMAC_TSH : (GMAC Offset: 0x1c0) (R/W 32) 1588 Timer Seconds High Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TCS:16; /**< bit: 0..15 Timer Count in Seconds */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TSH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TSH_OFFSET (0x1C0) /**< (GMAC_TSH) 1588 Timer Seconds High Register Offset */ + +#define GMAC_TSH_TCS_Pos 0 /**< (GMAC_TSH) Timer Count in Seconds Position */ +#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos) /**< (GMAC_TSH) Timer Count in Seconds Mask */ +#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)) +#define GMAC_TSH_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TSH) Register MASK (Use GMAC_TSH_Msk instead) */ +#define GMAC_TSH_Msk _U_(0xFFFF) /**< (GMAC_TSH) Register Mask */ + + +/* -------- GMAC_TSL : (GMAC Offset: 0x1d0) (R/W 32) 1588 Timer Seconds Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TCS:32; /**< bit: 0..31 Timer Count in Seconds */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TSL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TSL_OFFSET (0x1D0) /**< (GMAC_TSL) 1588 Timer Seconds Low Register Offset */ + +#define GMAC_TSL_TCS_Pos 0 /**< (GMAC_TSL) Timer Count in Seconds Position */ +#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /**< (GMAC_TSL) Timer Count in Seconds Mask */ +#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)) +#define GMAC_TSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_TSL) Register MASK (Use GMAC_TSL_Msk instead) */ +#define GMAC_TSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_TSL) Register Mask */ + + +/* -------- GMAC_TN : (GMAC Offset: 0x1d4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TNS:30; /**< bit: 0..29 Timer Count in Nanoseconds */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TN_OFFSET (0x1D4) /**< (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ + +#define GMAC_TN_TNS_Pos 0 /**< (GMAC_TN) Timer Count in Nanoseconds Position */ +#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /**< (GMAC_TN) Timer Count in Nanoseconds Mask */ +#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)) +#define GMAC_TN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_TN) Register MASK (Use GMAC_TN_Msk instead) */ +#define GMAC_TN_Msk _U_(0x3FFFFFFF) /**< (GMAC_TN) Register Mask */ + + +/* -------- GMAC_TA : (GMAC Offset: 0x1d8) (/W 32) 1588 Timer Adjust Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ITDT:30; /**< bit: 0..29 Increment/Decrement */ + uint32_t :1; /**< bit: 30 Reserved */ + uint32_t ADJ:1; /**< bit: 31 Adjust 1588 Timer */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TA_OFFSET (0x1D8) /**< (GMAC_TA) 1588 Timer Adjust Register Offset */ + +#define GMAC_TA_ITDT_Pos 0 /**< (GMAC_TA) Increment/Decrement Position */ +#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /**< (GMAC_TA) Increment/Decrement Mask */ +#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)) +#define GMAC_TA_ADJ_Pos 31 /**< (GMAC_TA) Adjust 1588 Timer Position */ +#define GMAC_TA_ADJ_Msk (_U_(0x1) << GMAC_TA_ADJ_Pos) /**< (GMAC_TA) Adjust 1588 Timer Mask */ +#define GMAC_TA_ADJ GMAC_TA_ADJ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_TA_ADJ_Msk instead */ +#define GMAC_TA_MASK _U_(0xBFFFFFFF) /**< \deprecated (GMAC_TA) Register MASK (Use GMAC_TA_Msk instead) */ +#define GMAC_TA_Msk _U_(0xBFFFFFFF) /**< (GMAC_TA) Register Mask */ + + +/* -------- GMAC_TI : (GMAC Offset: 0x1dc) (R/W 32) 1588 Timer Increment Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CNS:8; /**< bit: 0..7 Count Nanoseconds */ + uint32_t ACNS:8; /**< bit: 8..15 Alternative Count Nanoseconds */ + uint32_t NIT:8; /**< bit: 16..23 Number of Increments */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TI_OFFSET (0x1DC) /**< (GMAC_TI) 1588 Timer Increment Register Offset */ + +#define GMAC_TI_CNS_Pos 0 /**< (GMAC_TI) Count Nanoseconds Position */ +#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos) /**< (GMAC_TI) Count Nanoseconds Mask */ +#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)) +#define GMAC_TI_ACNS_Pos 8 /**< (GMAC_TI) Alternative Count Nanoseconds Position */ +#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos) /**< (GMAC_TI) Alternative Count Nanoseconds Mask */ +#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)) +#define GMAC_TI_NIT_Pos 16 /**< (GMAC_TI) Number of Increments Position */ +#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos) /**< (GMAC_TI) Number of Increments Mask */ +#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)) +#define GMAC_TI_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_TI) Register MASK (Use GMAC_TI_Msk instead) */ +#define GMAC_TI_Msk _U_(0xFFFFFF) /**< (GMAC_TI) Register Mask */ + + +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1e0) (R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:32; /**< bit: 0..31 Register Update */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFTSL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFTSL_OFFSET (0x1E0) /**< (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ + +#define GMAC_EFTSL_RUD_Pos 0 /**< (GMAC_EFTSL) Register Update Position */ +#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /**< (GMAC_EFTSL) Register Update Mask */ +#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos)) +#define GMAC_EFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFTSL) Register MASK (Use GMAC_EFTSL_Msk instead) */ +#define GMAC_EFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFTSL) Register Mask */ + + +/* -------- GMAC_EFTN : (GMAC Offset: 0x1e4) (R/ 32) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:30; /**< bit: 0..29 Register Update */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFTN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFTN_OFFSET (0x1E4) /**< (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Register Offset */ + +#define GMAC_EFTN_RUD_Pos 0 /**< (GMAC_EFTN) Register Update Position */ +#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /**< (GMAC_EFTN) Register Update Mask */ +#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos)) +#define GMAC_EFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFTN) Register MASK (Use GMAC_EFTN_Msk instead) */ +#define GMAC_EFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFTN) Register Mask */ + + +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1e8) (R/ 32) PTP Event Frame Received Seconds Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:32; /**< bit: 0..31 Register Update */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFRSL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFRSL_OFFSET (0x1E8) /**< (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ + +#define GMAC_EFRSL_RUD_Pos 0 /**< (GMAC_EFRSL) Register Update Position */ +#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /**< (GMAC_EFRSL) Register Update Mask */ +#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos)) +#define GMAC_EFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_EFRSL) Register MASK (Use GMAC_EFRSL_Msk instead) */ +#define GMAC_EFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFRSL) Register Mask */ + + +/* -------- GMAC_EFRN : (GMAC Offset: 0x1ec) (R/ 32) PTP Event Frame Received Nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:30; /**< bit: 0..29 Register Update */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_EFRN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_EFRN_OFFSET (0x1EC) /**< (GMAC_EFRN) PTP Event Frame Received Nanoseconds Register Offset */ + +#define GMAC_EFRN_RUD_Pos 0 /**< (GMAC_EFRN) Register Update Position */ +#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /**< (GMAC_EFRN) Register Update Mask */ +#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos)) +#define GMAC_EFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_EFRN) Register MASK (Use GMAC_EFRN_Msk instead) */ +#define GMAC_EFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFRN) Register Mask */ + + +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1f0) (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:32; /**< bit: 0..31 Register Update */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFTSL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFTSL_OFFSET (0x1F0) /**< (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ + +#define GMAC_PEFTSL_RUD_Pos 0 /**< (GMAC_PEFTSL) Register Update Position */ +#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /**< (GMAC_PEFTSL) Register Update Mask */ +#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos)) +#define GMAC_PEFTSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFTSL) Register MASK (Use GMAC_PEFTSL_Msk instead) */ +#define GMAC_PEFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFTSL) Register Mask */ + + +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1f4) (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:30; /**< bit: 0..29 Register Update */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFTN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFTN_OFFSET (0x1F4) /**< (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Register Offset */ + +#define GMAC_PEFTN_RUD_Pos 0 /**< (GMAC_PEFTN) Register Update Position */ +#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /**< (GMAC_PEFTN) Register Update Mask */ +#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos)) +#define GMAC_PEFTN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFTN) Register MASK (Use GMAC_PEFTN_Msk instead) */ +#define GMAC_PEFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFTN) Register Mask */ + + +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1f8) (R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:32; /**< bit: 0..31 Register Update */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFRSL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFRSL_OFFSET (0x1F8) /**< (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ + +#define GMAC_PEFRSL_RUD_Pos 0 /**< (GMAC_PEFRSL) Register Update Position */ +#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /**< (GMAC_PEFRSL) Register Update Mask */ +#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos)) +#define GMAC_PEFRSL_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_PEFRSL) Register MASK (Use GMAC_PEFRSL_Msk instead) */ +#define GMAC_PEFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFRSL) Register Mask */ + + +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1fc) (R/ 32) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RUD:30; /**< bit: 0..29 Register Update */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_PEFRN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_PEFRN_OFFSET (0x1FC) /**< (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Register Offset */ + +#define GMAC_PEFRN_RUD_Pos 0 /**< (GMAC_PEFRN) Register Update Position */ +#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /**< (GMAC_PEFRN) Register Update Mask */ +#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos)) +#define GMAC_PEFRN_MASK _U_(0x3FFFFFFF) /**< \deprecated (GMAC_PEFRN) Register MASK (Use GMAC_PEFRN_Msk instead) */ +#define GMAC_PEFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFRN) Register Mask */ + + +/* -------- GMAC_RXLPI : (GMAC Offset: 0x270) (R/ 32) Received LPI Transitions -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COUNT:16; /**< bit: 0..15 Count of RX LPI transitions (cleared on read) */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RXLPI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RXLPI_OFFSET (0x270) /**< (GMAC_RXLPI) Received LPI Transitions Offset */ + +#define GMAC_RXLPI_COUNT_Pos 0 /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Position */ +#define GMAC_RXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_RXLPI_COUNT_Pos) /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Mask */ +#define GMAC_RXLPI_COUNT(value) (GMAC_RXLPI_COUNT_Msk & ((value) << GMAC_RXLPI_COUNT_Pos)) +#define GMAC_RXLPI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RXLPI) Register MASK (Use GMAC_RXLPI_Msk instead) */ +#define GMAC_RXLPI_Msk _U_(0xFFFF) /**< (GMAC_RXLPI) Register Mask */ + + +/* -------- GMAC_RXLPITIME : (GMAC Offset: 0x274) (R/ 32) Received LPI Time -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LPITIME:24; /**< bit: 0..23 Time in LPI (cleared on read) */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RXLPITIME_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RXLPITIME_OFFSET (0x274) /**< (GMAC_RXLPITIME) Received LPI Time Offset */ + +#define GMAC_RXLPITIME_LPITIME_Pos 0 /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Position */ +#define GMAC_RXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_RXLPITIME_LPITIME_Pos) /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Mask */ +#define GMAC_RXLPITIME_LPITIME(value) (GMAC_RXLPITIME_LPITIME_Msk & ((value) << GMAC_RXLPITIME_LPITIME_Pos)) +#define GMAC_RXLPITIME_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_RXLPITIME) Register MASK (Use GMAC_RXLPITIME_Msk instead) */ +#define GMAC_RXLPITIME_Msk _U_(0xFFFFFF) /**< (GMAC_RXLPITIME) Register Mask */ + + +/* -------- GMAC_TXLPI : (GMAC Offset: 0x278) (R/ 32) Transmit LPI Transitions -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COUNT:16; /**< bit: 0..15 Count of LPI transitions (cleared on read) */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TXLPI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TXLPI_OFFSET (0x278) /**< (GMAC_TXLPI) Transmit LPI Transitions Offset */ + +#define GMAC_TXLPI_COUNT_Pos 0 /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Position */ +#define GMAC_TXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_TXLPI_COUNT_Pos) /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Mask */ +#define GMAC_TXLPI_COUNT(value) (GMAC_TXLPI_COUNT_Msk & ((value) << GMAC_TXLPI_COUNT_Pos)) +#define GMAC_TXLPI_MASK _U_(0xFFFF) /**< \deprecated (GMAC_TXLPI) Register MASK (Use GMAC_TXLPI_Msk instead) */ +#define GMAC_TXLPI_Msk _U_(0xFFFF) /**< (GMAC_TXLPI) Register Mask */ + + +/* -------- GMAC_TXLPITIME : (GMAC Offset: 0x27c) (R/ 32) Transmit LPI Time -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LPITIME:24; /**< bit: 0..23 Time in LPI (cleared on read) */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TXLPITIME_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TXLPITIME_OFFSET (0x27C) /**< (GMAC_TXLPITIME) Transmit LPI Time Offset */ + +#define GMAC_TXLPITIME_LPITIME_Pos 0 /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Position */ +#define GMAC_TXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_TXLPITIME_LPITIME_Pos) /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Mask */ +#define GMAC_TXLPITIME_LPITIME(value) (GMAC_TXLPITIME_LPITIME_Msk & ((value) << GMAC_TXLPITIME_LPITIME_Pos)) +#define GMAC_TXLPITIME_MASK _U_(0xFFFFFF) /**< \deprecated (GMAC_TXLPITIME) Register MASK (Use GMAC_TXLPITIME_Msk instead) */ +#define GMAC_TXLPITIME_Msk _U_(0xFFFFFF) /**< (GMAC_TXLPITIME) Register Mask */ + + +/* -------- GMAC_ISRPQ : (GMAC Offset: 0x400) (R/ 32) Interrupt Status Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ISRPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ISRPQ_OFFSET (0x400) /**< (GMAC_ISRPQ) Interrupt Status Register Priority Queue (1..5) Offset */ + +#define GMAC_ISRPQ_RCOMP_Pos 1 /**< (GMAC_ISRPQ) Receive Complete Position */ +#define GMAC_ISRPQ_RCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_RCOMP_Pos) /**< (GMAC_ISRPQ) Receive Complete Mask */ +#define GMAC_ISRPQ_RCOMP GMAC_ISRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RCOMP_Msk instead */ +#define GMAC_ISRPQ_RXUBR_Pos 2 /**< (GMAC_ISRPQ) RX Used Bit Read Position */ +#define GMAC_ISRPQ_RXUBR_Msk (_U_(0x1) << GMAC_ISRPQ_RXUBR_Pos) /**< (GMAC_ISRPQ) RX Used Bit Read Mask */ +#define GMAC_ISRPQ_RXUBR GMAC_ISRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RXUBR_Msk instead */ +#define GMAC_ISRPQ_RLEX_Pos 5 /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_ISRPQ_RLEX_Msk (_U_(0x1) << GMAC_ISRPQ_RLEX_Pos) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_ISRPQ_RLEX GMAC_ISRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_RLEX_Msk instead */ +#define GMAC_ISRPQ_TFC_Pos 6 /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISRPQ_TFC_Msk (_U_(0x1) << GMAC_ISRPQ_TFC_Pos) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISRPQ_TFC GMAC_ISRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TFC_Msk instead */ +#define GMAC_ISRPQ_TCOMP_Pos 7 /**< (GMAC_ISRPQ) Transmit Complete Position */ +#define GMAC_ISRPQ_TCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_TCOMP_Pos) /**< (GMAC_ISRPQ) Transmit Complete Mask */ +#define GMAC_ISRPQ_TCOMP GMAC_ISRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_TCOMP_Msk instead */ +#define GMAC_ISRPQ_ROVR_Pos 10 /**< (GMAC_ISRPQ) Receive Overrun Position */ +#define GMAC_ISRPQ_ROVR_Msk (_U_(0x1) << GMAC_ISRPQ_ROVR_Pos) /**< (GMAC_ISRPQ) Receive Overrun Mask */ +#define GMAC_ISRPQ_ROVR GMAC_ISRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_ROVR_Msk instead */ +#define GMAC_ISRPQ_HRESP_Pos 11 /**< (GMAC_ISRPQ) HRESP Not OK Position */ +#define GMAC_ISRPQ_HRESP_Msk (_U_(0x1) << GMAC_ISRPQ_HRESP_Pos) /**< (GMAC_ISRPQ) HRESP Not OK Mask */ +#define GMAC_ISRPQ_HRESP GMAC_ISRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ISRPQ_HRESP_Msk instead */ +#define GMAC_ISRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_ISRPQ) Register MASK (Use GMAC_ISRPQ_Msk instead) */ +#define GMAC_ISRPQ_Msk _U_(0xCE6) /**< (GMAC_ISRPQ) Register Mask */ + + +/* -------- GMAC_TBQBAPQ : (GMAC Offset: 0x440) (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXBQBA:30; /**< bit: 2..31 Transmit Buffer Queue Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_TBQBAPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_TBQBAPQ_OFFSET (0x440) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Register Priority Queue (1..5) Offset */ + +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQBAPQ_TXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_TBQBAPQ_TXBQBA_Pos) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQBAPQ_TXBQBA(value) (GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)) +#define GMAC_TBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_TBQBAPQ) Register MASK (Use GMAC_TBQBAPQ_Msk instead) */ +#define GMAC_TBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBQBAPQ : (GMAC Offset: 0x480) (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXBQBA:30; /**< bit: 2..31 Receive Buffer Queue Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RBQBAPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RBQBAPQ_OFFSET (0x480) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Register Priority Queue (1..5) Offset */ + +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQBAPQ_RXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_RBQBAPQ_RXBQBA_Pos) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQBAPQ_RXBQBA(value) (GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)) +#define GMAC_RBQBAPQ_MASK _U_(0xFFFFFFFC) /**< \deprecated (GMAC_RBQBAPQ) Register MASK (Use GMAC_RBQBAPQ_Msk instead) */ +#define GMAC_RBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBSRPQ : (GMAC Offset: 0x4a0) (R/W 32) Receive Buffer Size Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RBS:16; /**< bit: 0..15 Receive Buffer Size */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_RBSRPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_RBSRPQ_OFFSET (0x4A0) /**< (GMAC_RBSRPQ) Receive Buffer Size Register Priority Queue (1..5) Offset */ + +#define GMAC_RBSRPQ_RBS_Pos 0 /**< (GMAC_RBSRPQ) Receive Buffer Size Position */ +#define GMAC_RBSRPQ_RBS_Msk (_U_(0xFFFF) << GMAC_RBSRPQ_RBS_Pos) /**< (GMAC_RBSRPQ) Receive Buffer Size Mask */ +#define GMAC_RBSRPQ_RBS(value) (GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)) +#define GMAC_RBSRPQ_MASK _U_(0xFFFF) /**< \deprecated (GMAC_RBSRPQ) Register MASK (Use GMAC_RBSRPQ_Msk instead) */ +#define GMAC_RBSRPQ_Msk _U_(0xFFFF) /**< (GMAC_RBSRPQ) Register Mask */ + + +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4bc) (R/W 32) Credit-Based Shaping Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t QBE:1; /**< bit: 0 Queue B CBS Enable */ + uint32_t QAE:1; /**< bit: 1 Queue A CBS Enable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_CBSCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_CBSCR_OFFSET (0x4BC) /**< (GMAC_CBSCR) Credit-Based Shaping Control Register Offset */ + +#define GMAC_CBSCR_QBE_Pos 0 /**< (GMAC_CBSCR) Queue B CBS Enable Position */ +#define GMAC_CBSCR_QBE_Msk (_U_(0x1) << GMAC_CBSCR_QBE_Pos) /**< (GMAC_CBSCR) Queue B CBS Enable Mask */ +#define GMAC_CBSCR_QBE GMAC_CBSCR_QBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QBE_Msk instead */ +#define GMAC_CBSCR_QAE_Pos 1 /**< (GMAC_CBSCR) Queue A CBS Enable Position */ +#define GMAC_CBSCR_QAE_Msk (_U_(0x1) << GMAC_CBSCR_QAE_Pos) /**< (GMAC_CBSCR) Queue A CBS Enable Mask */ +#define GMAC_CBSCR_QAE GMAC_CBSCR_QAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_CBSCR_QAE_Msk instead */ +#define GMAC_CBSCR_MASK _U_(0x03) /**< \deprecated (GMAC_CBSCR) Register MASK (Use GMAC_CBSCR_Msk instead) */ +#define GMAC_CBSCR_Msk _U_(0x03) /**< (GMAC_CBSCR) Register Mask */ + + +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4c0) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IS:32; /**< bit: 0..31 IdleSlope */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_CBSISQA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_CBSISQA_OFFSET (0x4C0) /**< (GMAC_CBSISQA) Credit-Based Shaping IdleSlope Register for Queue A Offset */ + +#define GMAC_CBSISQA_IS_Pos 0 /**< (GMAC_CBSISQA) IdleSlope Position */ +#define GMAC_CBSISQA_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQA_IS_Pos) /**< (GMAC_CBSISQA) IdleSlope Mask */ +#define GMAC_CBSISQA_IS(value) (GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)) +#define GMAC_CBSISQA_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQA) Register MASK (Use GMAC_CBSISQA_Msk instead) */ +#define GMAC_CBSISQA_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQA) Register Mask */ + + +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4c4) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IS:32; /**< bit: 0..31 IdleSlope */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_CBSISQB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_CBSISQB_OFFSET (0x4C4) /**< (GMAC_CBSISQB) Credit-Based Shaping IdleSlope Register for Queue B Offset */ + +#define GMAC_CBSISQB_IS_Pos 0 /**< (GMAC_CBSISQB) IdleSlope Position */ +#define GMAC_CBSISQB_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQB_IS_Pos) /**< (GMAC_CBSISQB) IdleSlope Mask */ +#define GMAC_CBSISQB_IS(value) (GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)) +#define GMAC_CBSISQB_MASK _U_(0xFFFFFFFF) /**< \deprecated (GMAC_CBSISQB) Register MASK (Use GMAC_CBSISQB_Msk instead) */ +#define GMAC_CBSISQB_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQB) Register Mask */ + + +/* -------- GMAC_ST1RPQ : (GMAC Offset: 0x500) (R/W 32) Screening Type 1 Register Priority Queue -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-5) */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t DSTCM:8; /**< bit: 4..11 Differentiated Services or Traffic Class Match */ + uint32_t UDPM:16; /**< bit: 12..27 UDP Port Match */ + uint32_t DSTCE:1; /**< bit: 28 Differentiated Services or Traffic Class Match Enable */ + uint32_t UDPE:1; /**< bit: 29 UDP Port Match Enable */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ST1RPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ST1RPQ_OFFSET (0x500) /**< (GMAC_ST1RPQ) Screening Type 1 Register Priority Queue Offset */ + +#define GMAC_ST1RPQ_QNB_Pos 0 /**< (GMAC_ST1RPQ) Queue Number (0-5) Position */ +#define GMAC_ST1RPQ_QNB_Msk (_U_(0x7) << GMAC_ST1RPQ_QNB_Pos) /**< (GMAC_ST1RPQ) Queue Number (0-5) Mask */ +#define GMAC_ST1RPQ_QNB(value) (GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)) +#define GMAC_ST1RPQ_DSTCM_Pos 4 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Position */ +#define GMAC_ST1RPQ_DSTCM_Msk (_U_(0xFF) << GMAC_ST1RPQ_DSTCM_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Mask */ +#define GMAC_ST1RPQ_DSTCM(value) (GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)) +#define GMAC_ST1RPQ_UDPM_Pos 12 /**< (GMAC_ST1RPQ) UDP Port Match Position */ +#define GMAC_ST1RPQ_UDPM_Msk (_U_(0xFFFF) << GMAC_ST1RPQ_UDPM_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Mask */ +#define GMAC_ST1RPQ_UDPM(value) (GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)) +#define GMAC_ST1RPQ_DSTCE_Pos 28 /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Position */ +#define GMAC_ST1RPQ_DSTCE_Msk (_U_(0x1) << GMAC_ST1RPQ_DSTCE_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Mask */ +#define GMAC_ST1RPQ_DSTCE GMAC_ST1RPQ_DSTCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_DSTCE_Msk instead */ +#define GMAC_ST1RPQ_UDPE_Pos 29 /**< (GMAC_ST1RPQ) UDP Port Match Enable Position */ +#define GMAC_ST1RPQ_UDPE_Msk (_U_(0x1) << GMAC_ST1RPQ_UDPE_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Enable Mask */ +#define GMAC_ST1RPQ_UDPE GMAC_ST1RPQ_UDPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST1RPQ_UDPE_Msk instead */ +#define GMAC_ST1RPQ_MASK _U_(0x3FFFFFF7) /**< \deprecated (GMAC_ST1RPQ) Register MASK (Use GMAC_ST1RPQ_Msk instead) */ +#define GMAC_ST1RPQ_Msk _U_(0x3FFFFFF7) /**< (GMAC_ST1RPQ) Register Mask */ + + +/* -------- GMAC_ST2RPQ : (GMAC Offset: 0x540) (R/W 32) Screening Type 2 Register Priority Queue -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t QNB:3; /**< bit: 0..2 Queue Number (0-5) */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t VLANP:3; /**< bit: 4..6 VLAN Priority */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t VLANE:1; /**< bit: 8 VLAN Enable */ + uint32_t I2ETH:3; /**< bit: 9..11 Index of Screening Type 2 EtherType register x */ + uint32_t ETHE:1; /**< bit: 12 EtherType Enable */ + uint32_t COMPA:5; /**< bit: 13..17 Index of Screening Type 2 Compare Word 0/Word 1 register x */ + uint32_t COMPAE:1; /**< bit: 18 Compare A Enable */ + uint32_t COMPB:5; /**< bit: 19..23 Index of Screening Type 2 Compare Word 0/Word 1 register x */ + uint32_t COMPBE:1; /**< bit: 24 Compare B Enable */ + uint32_t COMPC:5; /**< bit: 25..29 Index of Screening Type 2 Compare Word 0/Word 1 register x */ + uint32_t COMPCE:1; /**< bit: 30 Compare C Enable */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ST2RPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ST2RPQ_OFFSET (0x540) /**< (GMAC_ST2RPQ) Screening Type 2 Register Priority Queue Offset */ + +#define GMAC_ST2RPQ_QNB_Pos 0 /**< (GMAC_ST2RPQ) Queue Number (0-5) Position */ +#define GMAC_ST2RPQ_QNB_Msk (_U_(0x7) << GMAC_ST2RPQ_QNB_Pos) /**< (GMAC_ST2RPQ) Queue Number (0-5) Mask */ +#define GMAC_ST2RPQ_QNB(value) (GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)) +#define GMAC_ST2RPQ_VLANP_Pos 4 /**< (GMAC_ST2RPQ) VLAN Priority Position */ +#define GMAC_ST2RPQ_VLANP_Msk (_U_(0x7) << GMAC_ST2RPQ_VLANP_Pos) /**< (GMAC_ST2RPQ) VLAN Priority Mask */ +#define GMAC_ST2RPQ_VLANP(value) (GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)) +#define GMAC_ST2RPQ_VLANE_Pos 8 /**< (GMAC_ST2RPQ) VLAN Enable Position */ +#define GMAC_ST2RPQ_VLANE_Msk (_U_(0x1) << GMAC_ST2RPQ_VLANE_Pos) /**< (GMAC_ST2RPQ) VLAN Enable Mask */ +#define GMAC_ST2RPQ_VLANE GMAC_ST2RPQ_VLANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_VLANE_Msk instead */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Position */ +#define GMAC_ST2RPQ_I2ETH_Msk (_U_(0x7) << GMAC_ST2RPQ_I2ETH_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Mask */ +#define GMAC_ST2RPQ_I2ETH(value) (GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)) +#define GMAC_ST2RPQ_ETHE_Pos 12 /**< (GMAC_ST2RPQ) EtherType Enable Position */ +#define GMAC_ST2RPQ_ETHE_Msk (_U_(0x1) << GMAC_ST2RPQ_ETHE_Pos) /**< (GMAC_ST2RPQ) EtherType Enable Mask */ +#define GMAC_ST2RPQ_ETHE GMAC_ST2RPQ_ETHE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_ETHE_Msk instead */ +#define GMAC_ST2RPQ_COMPA_Pos 13 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPA_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPA_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPA(value) (GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)) +#define GMAC_ST2RPQ_COMPAE_Pos 18 /**< (GMAC_ST2RPQ) Compare A Enable Position */ +#define GMAC_ST2RPQ_COMPAE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPAE_Pos) /**< (GMAC_ST2RPQ) Compare A Enable Mask */ +#define GMAC_ST2RPQ_COMPAE GMAC_ST2RPQ_COMPAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPAE_Msk instead */ +#define GMAC_ST2RPQ_COMPB_Pos 19 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPB_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPB_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPB(value) (GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)) +#define GMAC_ST2RPQ_COMPBE_Pos 24 /**< (GMAC_ST2RPQ) Compare B Enable Position */ +#define GMAC_ST2RPQ_COMPBE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPBE_Pos) /**< (GMAC_ST2RPQ) Compare B Enable Mask */ +#define GMAC_ST2RPQ_COMPBE GMAC_ST2RPQ_COMPBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPBE_Msk instead */ +#define GMAC_ST2RPQ_COMPC_Pos 25 /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPC_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPC_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPC(value) (GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)) +#define GMAC_ST2RPQ_COMPCE_Pos 30 /**< (GMAC_ST2RPQ) Compare C Enable Position */ +#define GMAC_ST2RPQ_COMPCE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPCE_Pos) /**< (GMAC_ST2RPQ) Compare C Enable Mask */ +#define GMAC_ST2RPQ_COMPCE GMAC_ST2RPQ_COMPCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_ST2RPQ_COMPCE_Msk instead */ +#define GMAC_ST2RPQ_MASK _U_(0x7FFFFF77) /**< \deprecated (GMAC_ST2RPQ) Register MASK (Use GMAC_ST2RPQ_Msk instead) */ +#define GMAC_ST2RPQ_Msk _U_(0x7FFFFF77) /**< (GMAC_ST2RPQ) Register Mask */ + + +/* -------- GMAC_IERPQ : (GMAC Offset: 0x600) (/W 32) Interrupt Enable Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IERPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IERPQ_OFFSET (0x600) /**< (GMAC_IERPQ) Interrupt Enable Register Priority Queue (1..5) Offset */ + +#define GMAC_IERPQ_RCOMP_Pos 1 /**< (GMAC_IERPQ) Receive Complete Position */ +#define GMAC_IERPQ_RCOMP_Msk (_U_(0x1) << GMAC_IERPQ_RCOMP_Pos) /**< (GMAC_IERPQ) Receive Complete Mask */ +#define GMAC_IERPQ_RCOMP GMAC_IERPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RCOMP_Msk instead */ +#define GMAC_IERPQ_RXUBR_Pos 2 /**< (GMAC_IERPQ) RX Used Bit Read Position */ +#define GMAC_IERPQ_RXUBR_Msk (_U_(0x1) << GMAC_IERPQ_RXUBR_Pos) /**< (GMAC_IERPQ) RX Used Bit Read Mask */ +#define GMAC_IERPQ_RXUBR GMAC_IERPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RXUBR_Msk instead */ +#define GMAC_IERPQ_RLEX_Pos 5 /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IERPQ_RLEX_Msk (_U_(0x1) << GMAC_IERPQ_RLEX_Pos) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IERPQ_RLEX GMAC_IERPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_RLEX_Msk instead */ +#define GMAC_IERPQ_TFC_Pos 6 /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IERPQ_TFC_Msk (_U_(0x1) << GMAC_IERPQ_TFC_Pos) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IERPQ_TFC GMAC_IERPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TFC_Msk instead */ +#define GMAC_IERPQ_TCOMP_Pos 7 /**< (GMAC_IERPQ) Transmit Complete Position */ +#define GMAC_IERPQ_TCOMP_Msk (_U_(0x1) << GMAC_IERPQ_TCOMP_Pos) /**< (GMAC_IERPQ) Transmit Complete Mask */ +#define GMAC_IERPQ_TCOMP GMAC_IERPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_TCOMP_Msk instead */ +#define GMAC_IERPQ_ROVR_Pos 10 /**< (GMAC_IERPQ) Receive Overrun Position */ +#define GMAC_IERPQ_ROVR_Msk (_U_(0x1) << GMAC_IERPQ_ROVR_Pos) /**< (GMAC_IERPQ) Receive Overrun Mask */ +#define GMAC_IERPQ_ROVR GMAC_IERPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_ROVR_Msk instead */ +#define GMAC_IERPQ_HRESP_Pos 11 /**< (GMAC_IERPQ) HRESP Not OK Position */ +#define GMAC_IERPQ_HRESP_Msk (_U_(0x1) << GMAC_IERPQ_HRESP_Pos) /**< (GMAC_IERPQ) HRESP Not OK Mask */ +#define GMAC_IERPQ_HRESP GMAC_IERPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IERPQ_HRESP_Msk instead */ +#define GMAC_IERPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IERPQ) Register MASK (Use GMAC_IERPQ_Msk instead) */ +#define GMAC_IERPQ_Msk _U_(0xCE6) /**< (GMAC_IERPQ) Register Mask */ + + +/* -------- GMAC_IDRPQ : (GMAC Offset: 0x620) (/W 32) Interrupt Disable Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t TFC:1; /**< bit: 6 Transmit Frame Corruption Due to AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IDRPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IDRPQ_OFFSET (0x620) /**< (GMAC_IDRPQ) Interrupt Disable Register Priority Queue (1..5) Offset */ + +#define GMAC_IDRPQ_RCOMP_Pos 1 /**< (GMAC_IDRPQ) Receive Complete Position */ +#define GMAC_IDRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_RCOMP_Pos) /**< (GMAC_IDRPQ) Receive Complete Mask */ +#define GMAC_IDRPQ_RCOMP GMAC_IDRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RCOMP_Msk instead */ +#define GMAC_IDRPQ_RXUBR_Pos 2 /**< (GMAC_IDRPQ) RX Used Bit Read Position */ +#define GMAC_IDRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IDRPQ_RXUBR_Pos) /**< (GMAC_IDRPQ) RX Used Bit Read Mask */ +#define GMAC_IDRPQ_RXUBR GMAC_IDRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RXUBR_Msk instead */ +#define GMAC_IDRPQ_RLEX_Pos 5 /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDRPQ_RLEX_Msk (_U_(0x1) << GMAC_IDRPQ_RLEX_Pos) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDRPQ_RLEX GMAC_IDRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_RLEX_Msk instead */ +#define GMAC_IDRPQ_TFC_Pos 6 /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDRPQ_TFC_Msk (_U_(0x1) << GMAC_IDRPQ_TFC_Pos) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDRPQ_TFC GMAC_IDRPQ_TFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TFC_Msk instead */ +#define GMAC_IDRPQ_TCOMP_Pos 7 /**< (GMAC_IDRPQ) Transmit Complete Position */ +#define GMAC_IDRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_TCOMP_Pos) /**< (GMAC_IDRPQ) Transmit Complete Mask */ +#define GMAC_IDRPQ_TCOMP GMAC_IDRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_TCOMP_Msk instead */ +#define GMAC_IDRPQ_ROVR_Pos 10 /**< (GMAC_IDRPQ) Receive Overrun Position */ +#define GMAC_IDRPQ_ROVR_Msk (_U_(0x1) << GMAC_IDRPQ_ROVR_Pos) /**< (GMAC_IDRPQ) Receive Overrun Mask */ +#define GMAC_IDRPQ_ROVR GMAC_IDRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_ROVR_Msk instead */ +#define GMAC_IDRPQ_HRESP_Pos 11 /**< (GMAC_IDRPQ) HRESP Not OK Position */ +#define GMAC_IDRPQ_HRESP_Msk (_U_(0x1) << GMAC_IDRPQ_HRESP_Pos) /**< (GMAC_IDRPQ) HRESP Not OK Mask */ +#define GMAC_IDRPQ_HRESP GMAC_IDRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IDRPQ_HRESP_Msk instead */ +#define GMAC_IDRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IDRPQ) Register MASK (Use GMAC_IDRPQ_Msk instead) */ +#define GMAC_IDRPQ_Msk _U_(0xCE6) /**< (GMAC_IDRPQ) Register Mask */ + + +/* -------- GMAC_IMRPQ : (GMAC Offset: 0x640) (R/W 32) Interrupt Mask Register Priority Queue (1..5) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RCOMP:1; /**< bit: 1 Receive Complete */ + uint32_t RXUBR:1; /**< bit: 2 RX Used Bit Read */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t RLEX:1; /**< bit: 5 Retry Limit Exceeded or Late Collision */ + uint32_t AHB:1; /**< bit: 6 AHB Error */ + uint32_t TCOMP:1; /**< bit: 7 Transmit Complete */ + uint32_t :2; /**< bit: 8..9 Reserved */ + uint32_t ROVR:1; /**< bit: 10 Receive Overrun */ + uint32_t HRESP:1; /**< bit: 11 HRESP Not OK */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_IMRPQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_IMRPQ_OFFSET (0x640) /**< (GMAC_IMRPQ) Interrupt Mask Register Priority Queue (1..5) Offset */ + +#define GMAC_IMRPQ_RCOMP_Pos 1 /**< (GMAC_IMRPQ) Receive Complete Position */ +#define GMAC_IMRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_RCOMP_Pos) /**< (GMAC_IMRPQ) Receive Complete Mask */ +#define GMAC_IMRPQ_RCOMP GMAC_IMRPQ_RCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RCOMP_Msk instead */ +#define GMAC_IMRPQ_RXUBR_Pos 2 /**< (GMAC_IMRPQ) RX Used Bit Read Position */ +#define GMAC_IMRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IMRPQ_RXUBR_Pos) /**< (GMAC_IMRPQ) RX Used Bit Read Mask */ +#define GMAC_IMRPQ_RXUBR GMAC_IMRPQ_RXUBR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RXUBR_Msk instead */ +#define GMAC_IMRPQ_RLEX_Pos 5 /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IMRPQ_RLEX_Msk (_U_(0x1) << GMAC_IMRPQ_RLEX_Pos) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IMRPQ_RLEX GMAC_IMRPQ_RLEX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_RLEX_Msk instead */ +#define GMAC_IMRPQ_AHB_Pos 6 /**< (GMAC_IMRPQ) AHB Error Position */ +#define GMAC_IMRPQ_AHB_Msk (_U_(0x1) << GMAC_IMRPQ_AHB_Pos) /**< (GMAC_IMRPQ) AHB Error Mask */ +#define GMAC_IMRPQ_AHB GMAC_IMRPQ_AHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_AHB_Msk instead */ +#define GMAC_IMRPQ_TCOMP_Pos 7 /**< (GMAC_IMRPQ) Transmit Complete Position */ +#define GMAC_IMRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_TCOMP_Pos) /**< (GMAC_IMRPQ) Transmit Complete Mask */ +#define GMAC_IMRPQ_TCOMP GMAC_IMRPQ_TCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_TCOMP_Msk instead */ +#define GMAC_IMRPQ_ROVR_Pos 10 /**< (GMAC_IMRPQ) Receive Overrun Position */ +#define GMAC_IMRPQ_ROVR_Msk (_U_(0x1) << GMAC_IMRPQ_ROVR_Pos) /**< (GMAC_IMRPQ) Receive Overrun Mask */ +#define GMAC_IMRPQ_ROVR GMAC_IMRPQ_ROVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_ROVR_Msk instead */ +#define GMAC_IMRPQ_HRESP_Pos 11 /**< (GMAC_IMRPQ) HRESP Not OK Position */ +#define GMAC_IMRPQ_HRESP_Msk (_U_(0x1) << GMAC_IMRPQ_HRESP_Pos) /**< (GMAC_IMRPQ) HRESP Not OK Mask */ +#define GMAC_IMRPQ_HRESP GMAC_IMRPQ_HRESP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use GMAC_IMRPQ_HRESP_Msk instead */ +#define GMAC_IMRPQ_MASK _U_(0xCE6) /**< \deprecated (GMAC_IMRPQ) Register MASK (Use GMAC_IMRPQ_Msk instead) */ +#define GMAC_IMRPQ_Msk _U_(0xCE6) /**< (GMAC_IMRPQ) Register Mask */ + + +/* -------- GMAC_ST2ER : (GMAC Offset: 0x6e0) (R/W 32) Screening Type 2 Ethertype Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COMPVAL:16; /**< bit: 0..15 Ethertype Compare Value */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GMAC_ST2ER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GMAC_ST2ER_OFFSET (0x6E0) /**< (GMAC_ST2ER) Screening Type 2 Ethertype Register Offset */ + +#define GMAC_ST2ER_COMPVAL_Pos 0 /**< (GMAC_ST2ER) Ethertype Compare Value Position */ +#define GMAC_ST2ER_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2ER_COMPVAL_Pos) /**< (GMAC_ST2ER) Ethertype Compare Value Mask */ +#define GMAC_ST2ER_COMPVAL(value) (GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)) +#define GMAC_ST2ER_MASK _U_(0xFFFF) /**< \deprecated (GMAC_ST2ER) Register MASK (Use GMAC_ST2ER_Msk instead) */ +#define GMAC_ST2ER_Msk _U_(0xFFFF) /**< (GMAC_ST2ER) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief GMAC_SA hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< (GMAC_SA Offset: 0x00) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< (GMAC_SA Offset: 0x04) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GMAC_ST2CW hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2CW0; /**< (GMAC_ST2CW Offset: 0x00) Screening Type 2 Compare Word 0 Register */ + __IO uint32_t GMAC_ST2CW1; /**< (GMAC_ST2CW Offset: 0x04) Screening Type 2 Compare Word 1 Register */ +} GmacSt2cw; + +#define GMACSA_NUMBER 4 +#define GMACST2CW_NUMBER 24 +/** \brief GMAC hardware registers */ +typedef struct { + __IO uint32_t GMAC_NCR; /**< (GMAC Offset: 0x00) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< (GMAC Offset: 0x04) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< (GMAC Offset: 0x08) Network Status Register */ + __IO uint32_t GMAC_UR; /**< (GMAC Offset: 0x0C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< (GMAC Offset: 0x10) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< (GMAC Offset: 0x14) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< (GMAC Offset: 0x18) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< (GMAC Offset: 0x1C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< (GMAC Offset: 0x20) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< (GMAC Offset: 0x24) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< (GMAC Offset: 0x28) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< (GMAC Offset: 0x2C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< (GMAC Offset: 0x30) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< (GMAC Offset: 0x34) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< (GMAC Offset: 0x38) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< (GMAC Offset: 0x3C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< (GMAC Offset: 0x40) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< (GMAC Offset: 0x44) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< (GMAC Offset: 0x48) RX Jumbo Frame Max Length Register */ + __I uint8_t Reserved1[52]; + __IO uint32_t GMAC_HRB; /**< (GMAC Offset: 0x80) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< (GMAC Offset: 0x84) Hash Register Top */ + GmacSa GmacSa[GMACSA_NUMBER]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_TIDM1; /**< (GMAC Offset: 0xA8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< (GMAC Offset: 0xAC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< (GMAC Offset: 0xB0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< (GMAC Offset: 0xB4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< (GMAC Offset: 0xB8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< (GMAC Offset: 0xBC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< (GMAC Offset: 0xC0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< (GMAC Offset: 0xC4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< (GMAC Offset: 0xC8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< (GMAC Offset: 0xCC) Specific Address 1 Mask Top Register */ + __I uint8_t Reserved2[12]; + __IO uint32_t GMAC_NSC; /**< (GMAC Offset: 0xDC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< (GMAC Offset: 0xE0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< (GMAC Offset: 0xE4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< (GMAC Offset: 0xE8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< (GMAC Offset: 0xEC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< (GMAC Offset: 0xF0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< (GMAC Offset: 0xF4) PTP Peer Event Frame Received Seconds High Register */ + __I uint8_t Reserved3[8]; + __I uint32_t GMAC_OTLO; /**< (GMAC Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< (GMAC Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< (GMAC Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< (GMAC Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< (GMAC Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< (GMAC Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< (GMAC Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< (GMAC Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< (GMAC Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< (GMAC Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< (GMAC Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< (GMAC Offset: 0x14C) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< (GMAC Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< (GMAC Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< (GMAC Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< (GMAC Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< (GMAC Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< (GMAC Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< (GMAC Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< (GMAC Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< (GMAC Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< (GMAC Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< (GMAC Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< (GMAC Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< (GMAC Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< (GMAC Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< (GMAC Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< (GMAC Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< (GMAC Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< (GMAC Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< (GMAC Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint8_t Reserved4[8]; + __IO uint32_t GMAC_TISUBN; /**< (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint8_t Reserved5[12]; + __IO uint32_t GMAC_TSL; /**< (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< (GMAC Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< (GMAC Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint8_t Reserved6[112]; + __I uint32_t GMAC_RXLPI; /**< (GMAC Offset: 0x270) Received LPI Transitions */ + __I uint32_t GMAC_RXLPITIME; /**< (GMAC Offset: 0x274) Received LPI Time */ + __I uint32_t GMAC_TXLPI; /**< (GMAC Offset: 0x278) Transmit LPI Transitions */ + __I uint32_t GMAC_TXLPITIME; /**< (GMAC Offset: 0x27C) Transmit LPI Time */ + __I uint8_t Reserved7[384]; + __I uint32_t GMAC_ISRPQ[5]; /**< (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (1..5) */ + __I uint8_t Reserved8[44]; + __IO uint32_t GMAC_TBQBAPQ[5]; /**< (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved9[44]; + __IO uint32_t GMAC_RBQBAPQ[5]; /**< (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved10[12]; + __IO uint32_t GMAC_RBSRPQ[5]; /**< (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (1..5) */ + __I uint8_t Reserved11[8]; + __IO uint32_t GMAC_CBSCR; /**< (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint8_t Reserved12[56]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue */ + __I uint8_t Reserved13[48]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue */ + __I uint8_t Reserved14[160]; + __O uint32_t GMAC_IERPQ[5]; /**< (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (1..5) */ + __I uint8_t Reserved15[12]; + __O uint32_t GMAC_IDRPQ[5]; /**< (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (1..5) */ + __I uint8_t Reserved16[12]; + __IO uint32_t GMAC_IMRPQ[5]; /**< (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (1..5) */ + __I uint8_t Reserved17[140]; + __IO uint32_t GMAC_ST2ER[4]; /**< (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register */ + __I uint8_t Reserved18[16]; + GmacSt2cw GmacSt2cw[GMACST2CW_NUMBER]; /**< Offset: 0x700 Screening Type 2 Compare Word 0 Register */ +} Gmac; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief GMAC_SA hardware registers */ +typedef struct { + __IO GMAC_SAB_Type GMAC_SAB; /**< Offset: 0x00 (R/W 32) Specific Address 1 Bottom Register */ + __IO GMAC_SAT_Type GMAC_SAT; /**< Offset: 0x04 (R/W 32) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GMAC_ST2CW hardware registers */ +typedef struct { + __IO GMAC_ST2CW0_Type GMAC_ST2CW0; /**< Offset: 0x00 (R/W 32) Screening Type 2 Compare Word 0 Register */ + __IO GMAC_ST2CW1_Type GMAC_ST2CW1; /**< Offset: 0x04 (R/W 32) Screening Type 2 Compare Word 1 Register */ +} GmacSt2cw; + +/** \brief GMAC hardware registers */ +typedef struct { + __IO GMAC_NCR_Type GMAC_NCR; /**< Offset: 0x00 (R/W 32) Network Control Register */ + __IO GMAC_NCFGR_Type GMAC_NCFGR; /**< Offset: 0x04 (R/W 32) Network Configuration Register */ + __I GMAC_NSR_Type GMAC_NSR; /**< Offset: 0x08 (R/ 32) Network Status Register */ + __IO GMAC_UR_Type GMAC_UR; /**< Offset: 0x0C (R/W 32) User Register */ + __IO GMAC_DCFGR_Type GMAC_DCFGR; /**< Offset: 0x10 (R/W 32) DMA Configuration Register */ + __IO GMAC_TSR_Type GMAC_TSR; /**< Offset: 0x14 (R/W 32) Transmit Status Register */ + __IO GMAC_RBQB_Type GMAC_RBQB; /**< Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address Register */ + __IO GMAC_TBQB_Type GMAC_TBQB; /**< Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address Register */ + __IO GMAC_RSR_Type GMAC_RSR; /**< Offset: 0x20 (R/W 32) Receive Status Register */ + __I GMAC_ISR_Type GMAC_ISR; /**< Offset: 0x24 (R/ 32) Interrupt Status Register */ + __O GMAC_IER_Type GMAC_IER; /**< Offset: 0x28 ( /W 32) Interrupt Enable Register */ + __O GMAC_IDR_Type GMAC_IDR; /**< Offset: 0x2C ( /W 32) Interrupt Disable Register */ + __IO GMAC_IMR_Type GMAC_IMR; /**< Offset: 0x30 (R/W 32) Interrupt Mask Register */ + __IO GMAC_MAN_Type GMAC_MAN; /**< Offset: 0x34 (R/W 32) PHY Maintenance Register */ + __I GMAC_RPQ_Type GMAC_RPQ; /**< Offset: 0x38 (R/ 32) Received Pause Quantum Register */ + __IO GMAC_TPQ_Type GMAC_TPQ; /**< Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ + __IO GMAC_TPSF_Type GMAC_TPSF; /**< Offset: 0x40 (R/W 32) TX Partial Store and Forward Register */ + __IO GMAC_RPSF_Type GMAC_RPSF; /**< Offset: 0x44 (R/W 32) RX Partial Store and Forward Register */ + __IO GMAC_RJFML_Type GMAC_RJFML; /**< Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ + __I uint8_t Reserved1[52]; + __IO GMAC_HRB_Type GMAC_HRB; /**< Offset: 0x80 (R/W 32) Hash Register Bottom */ + __IO GMAC_HRT_Type GMAC_HRT; /**< Offset: 0x84 (R/W 32) Hash Register Top */ + GmacSa GmacSa[4]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ + __IO GMAC_TIDM1_Type GMAC_TIDM1; /**< Offset: 0xA8 (R/W 32) Type ID Match 1 Register */ + __IO GMAC_TIDM2_Type GMAC_TIDM2; /**< Offset: 0xAC (R/W 32) Type ID Match 2 Register */ + __IO GMAC_TIDM3_Type GMAC_TIDM3; /**< Offset: 0xB0 (R/W 32) Type ID Match 3 Register */ + __IO GMAC_TIDM4_Type GMAC_TIDM4; /**< Offset: 0xB4 (R/W 32) Type ID Match 4 Register */ + __IO GMAC_WOL_Type GMAC_WOL; /**< Offset: 0xB8 (R/W 32) Wake on LAN Register */ + __IO GMAC_IPGS_Type GMAC_IPGS; /**< Offset: 0xBC (R/W 32) IPG Stretch Register */ + __IO GMAC_SVLAN_Type GMAC_SVLAN; /**< Offset: 0xC0 (R/W 32) Stacked VLAN Register */ + __IO GMAC_TPFCP_Type GMAC_TPFCP; /**< Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ + __IO GMAC_SAMB1_Type GMAC_SAMB1; /**< Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom Register */ + __IO GMAC_SAMT1_Type GMAC_SAMT1; /**< Offset: 0xCC (R/W 32) Specific Address 1 Mask Top Register */ + __I uint8_t Reserved2[12]; + __IO GMAC_NSC_Type GMAC_NSC; /**< Offset: 0xDC (R/W 32) 1588 Timer Nanosecond Comparison Register */ + __IO GMAC_SCL_Type GMAC_SCL; /**< Offset: 0xE0 (R/W 32) 1588 Timer Second Comparison Low Register */ + __IO GMAC_SCH_Type GMAC_SCH; /**< Offset: 0xE4 (R/W 32) 1588 Timer Second Comparison High Register */ + __I GMAC_EFTSH_Type GMAC_EFTSH; /**< Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ + __I GMAC_EFRSH_Type GMAC_EFRSH; /**< Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ + __I GMAC_PEFTSH_Type GMAC_PEFTSH; /**< Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ + __I GMAC_PEFRSH_Type GMAC_PEFRSH; /**< Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ + __I uint8_t Reserved3[8]; + __I GMAC_OTLO_Type GMAC_OTLO; /**< Offset: 0x100 (R/ 32) Octets Transmitted Low Register */ + __I GMAC_OTHI_Type GMAC_OTHI; /**< Offset: 0x104 (R/ 32) Octets Transmitted High Register */ + __I GMAC_FT_Type GMAC_FT; /**< Offset: 0x108 (R/ 32) Frames Transmitted Register */ + __I GMAC_BCFT_Type GMAC_BCFT; /**< Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ + __I GMAC_MFT_Type GMAC_MFT; /**< Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ + __I GMAC_PFT_Type GMAC_PFT; /**< Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ + __I GMAC_BFT64_Type GMAC_BFT64; /**< Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ + __I GMAC_TBFT127_Type GMAC_TBFT127; /**< Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ + __I GMAC_TBFT255_Type GMAC_TBFT255; /**< Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ + __I GMAC_TBFT511_Type GMAC_TBFT511; /**< Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ + __I GMAC_TBFT1023_Type GMAC_TBFT1023; /**< Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ + __I GMAC_TBFT1518_Type GMAC_TBFT1518; /**< Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ + __I GMAC_GTBFT1518_Type GMAC_GTBFT1518; /**< Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ + __I GMAC_TUR_Type GMAC_TUR; /**< Offset: 0x134 (R/ 32) Transmit Underruns Register */ + __I GMAC_SCF_Type GMAC_SCF; /**< Offset: 0x138 (R/ 32) Single Collision Frames Register */ + __I GMAC_MCF_Type GMAC_MCF; /**< Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ + __I GMAC_EC_Type GMAC_EC; /**< Offset: 0x140 (R/ 32) Excessive Collisions Register */ + __I GMAC_LC_Type GMAC_LC; /**< Offset: 0x144 (R/ 32) Late Collisions Register */ + __I GMAC_DTF_Type GMAC_DTF; /**< Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ + __I GMAC_CSE_Type GMAC_CSE; /**< Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ + __I GMAC_ORLO_Type GMAC_ORLO; /**< Offset: 0x150 (R/ 32) Octets Received Low Received Register */ + __I GMAC_ORHI_Type GMAC_ORHI; /**< Offset: 0x154 (R/ 32) Octets Received High Received Register */ + __I GMAC_FR_Type GMAC_FR; /**< Offset: 0x158 (R/ 32) Frames Received Register */ + __I GMAC_BCFR_Type GMAC_BCFR; /**< Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ + __I GMAC_MFR_Type GMAC_MFR; /**< Offset: 0x160 (R/ 32) Multicast Frames Received Register */ + __I GMAC_PFR_Type GMAC_PFR; /**< Offset: 0x164 (R/ 32) Pause Frames Received Register */ + __I GMAC_BFR64_Type GMAC_BFR64; /**< Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ + __I GMAC_TBFR127_Type GMAC_TBFR127; /**< Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ + __I GMAC_TBFR255_Type GMAC_TBFR255; /**< Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ + __I GMAC_TBFR511_Type GMAC_TBFR511; /**< Offset: 0x174 (R/ 32) 256 to 511 Byte Frames Received Register */ + __I GMAC_TBFR1023_Type GMAC_TBFR1023; /**< Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ + __I GMAC_TBFR1518_Type GMAC_TBFR1518; /**< Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ + __I GMAC_TMXBFR_Type GMAC_TMXBFR; /**< Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ + __I GMAC_UFR_Type GMAC_UFR; /**< Offset: 0x184 (R/ 32) Undersize Frames Received Register */ + __I GMAC_OFR_Type GMAC_OFR; /**< Offset: 0x188 (R/ 32) Oversize Frames Received Register */ + __I GMAC_JR_Type GMAC_JR; /**< Offset: 0x18C (R/ 32) Jabbers Received Register */ + __I GMAC_FCSE_Type GMAC_FCSE; /**< Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ + __I GMAC_LFFE_Type GMAC_LFFE; /**< Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ + __I GMAC_RSE_Type GMAC_RSE; /**< Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ + __I GMAC_AE_Type GMAC_AE; /**< Offset: 0x19C (R/ 32) Alignment Errors Register */ + __I GMAC_RRE_Type GMAC_RRE; /**< Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ + __I GMAC_ROE_Type GMAC_ROE; /**< Offset: 0x1A4 (R/ 32) Receive Overrun Register */ + __I GMAC_IHCE_Type GMAC_IHCE; /**< Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ + __I GMAC_TCE_Type GMAC_TCE; /**< Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ + __I GMAC_UCE_Type GMAC_UCE; /**< Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ + __I uint8_t Reserved4[8]; + __IO GMAC_TISUBN_Type GMAC_TISUBN; /**< Offset: 0x1BC (R/W 32) 1588 Timer Increment Sub-nanoseconds Register */ + __IO GMAC_TSH_Type GMAC_TSH; /**< Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High Register */ + __I uint8_t Reserved5[12]; + __IO GMAC_TSL_Type GMAC_TSL; /**< Offset: 0x1D0 (R/W 32) 1588 Timer Seconds Low Register */ + __IO GMAC_TN_Type GMAC_TN; /**< Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ + __O GMAC_TA_Type GMAC_TA; /**< Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ + __IO GMAC_TI_Type GMAC_TI; /**< Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ + __I GMAC_EFTSL_Type GMAC_EFTSL; /**< Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ + __I GMAC_EFTN_Type GMAC_EFTN; /**< Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds Register */ + __I GMAC_EFRSL_Type GMAC_EFRSL; /**< Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ + __I GMAC_EFRN_Type GMAC_EFRN; /**< Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds Register */ + __I GMAC_PEFTSL_Type GMAC_PEFTSL; /**< Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I GMAC_PEFTN_Type GMAC_PEFTN; /**< Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I GMAC_PEFRSL_Type GMAC_PEFRSL; /**< Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ + __I GMAC_PEFRN_Type GMAC_PEFRN; /**< Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint8_t Reserved6[112]; + __I GMAC_RXLPI_Type GMAC_RXLPI; /**< Offset: 0x270 (R/ 32) Received LPI Transitions */ + __I GMAC_RXLPITIME_Type GMAC_RXLPITIME; /**< Offset: 0x274 (R/ 32) Received LPI Time */ + __I GMAC_TXLPI_Type GMAC_TXLPI; /**< Offset: 0x278 (R/ 32) Transmit LPI Transitions */ + __I GMAC_TXLPITIME_Type GMAC_TXLPITIME; /**< Offset: 0x27C (R/ 32) Transmit LPI Time */ + __I uint8_t Reserved7[384]; + __I GMAC_ISRPQ_Type GMAC_ISRPQ[5]; /**< Offset: 0x400 (R/ 32) Interrupt Status Register Priority Queue (1..5) */ + __I uint8_t Reserved8[44]; + __IO GMAC_TBQBAPQ_Type GMAC_TBQBAPQ[5]; /**< Offset: 0x440 (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved9[44]; + __IO GMAC_RBQBAPQ_Type GMAC_RBQBAPQ[5]; /**< Offset: 0x480 (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved10[12]; + __IO GMAC_RBSRPQ_Type GMAC_RBSRPQ[5]; /**< Offset: 0x4A0 (R/W 32) Receive Buffer Size Register Priority Queue (1..5) */ + __I uint8_t Reserved11[8]; + __IO GMAC_CBSCR_Type GMAC_CBSCR; /**< Offset: 0x4BC (R/W 32) Credit-Based Shaping Control Register */ + __IO GMAC_CBSISQA_Type GMAC_CBSISQA; /**< Offset: 0x4C0 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO GMAC_CBSISQB_Type GMAC_CBSISQB; /**< Offset: 0x4C4 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint8_t Reserved12[56]; + __IO GMAC_ST1RPQ_Type GMAC_ST1RPQ[4]; /**< Offset: 0x500 (R/W 32) Screening Type 1 Register Priority Queue */ + __I uint8_t Reserved13[48]; + __IO GMAC_ST2RPQ_Type GMAC_ST2RPQ[8]; /**< Offset: 0x540 (R/W 32) Screening Type 2 Register Priority Queue */ + __I uint8_t Reserved14[160]; + __O GMAC_IERPQ_Type GMAC_IERPQ[5]; /**< Offset: 0x600 ( /W 32) Interrupt Enable Register Priority Queue (1..5) */ + __I uint8_t Reserved15[12]; + __O GMAC_IDRPQ_Type GMAC_IDRPQ[5]; /**< Offset: 0x620 ( /W 32) Interrupt Disable Register Priority Queue (1..5) */ + __I uint8_t Reserved16[12]; + __IO GMAC_IMRPQ_Type GMAC_IMRPQ[5]; /**< Offset: 0x640 (R/W 32) Interrupt Mask Register Priority Queue (1..5) */ + __I uint8_t Reserved17[140]; + __IO GMAC_ST2ER_Type GMAC_ST2ER[4]; /**< Offset: 0x6E0 (R/W 32) Screening Type 2 Ethertype Register */ + __I uint8_t Reserved18[16]; + GmacSt2cw GmacSt2cw[24]; /**< Offset: 0x700 Screening Type 2 Compare Word 0 Register */ +} Gmac; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Gigabit Ethernet MAC */ + +#endif /* _SAME70_GMAC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/gpbr.h b/bsp/microchip/same70/bsp/same70b/include/component/gpbr.h new file mode 100644 index 0000000000..ab6e948a92 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/gpbr.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief Component description for GPBR + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_GPBR_COMPONENT_H_ +#define _SAME70_GPBR_COMPONENT_H_ +#define _SAME70_GPBR_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 General Purpose Backup Registers + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR GPBR */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define GPBR_6378 /**< (GPBR) Module ID */ +#define REV_GPBR J /**< (GPBR) Module revision */ + +/* -------- GPBR_SYS_GPBR : (GPBR Offset: 0x00) (R/W 32) General Purpose Backup Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t GPBR_VALUE:32; /**< bit: 0..31 Value of GPBR x */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} GPBR_SYS_GPBR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define GPBR_SYS_GPBR_OFFSET (0x00) /**< (GPBR_SYS_GPBR) General Purpose Backup Register 0 Offset */ + +#define GPBR_SYS_GPBR_GPBR_VALUE_Pos 0 /**< (GPBR_SYS_GPBR) Value of GPBR x Position */ +#define GPBR_SYS_GPBR_GPBR_VALUE_Msk (_U_(0xFFFFFFFF) << GPBR_SYS_GPBR_GPBR_VALUE_Pos) /**< (GPBR_SYS_GPBR) Value of GPBR x Mask */ +#define GPBR_SYS_GPBR_GPBR_VALUE(value) (GPBR_SYS_GPBR_GPBR_VALUE_Msk & ((value) << GPBR_SYS_GPBR_GPBR_VALUE_Pos)) +#define GPBR_SYS_GPBR_MASK _U_(0xFFFFFFFF) /**< \deprecated (GPBR_SYS_GPBR) Register MASK (Use GPBR_SYS_GPBR_Msk instead) */ +#define GPBR_SYS_GPBR_Msk _U_(0xFFFFFFFF) /**< (GPBR_SYS_GPBR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief GPBR hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< (GPBR Offset: 0x00) General Purpose Backup Register 0 */ +} Gpbr; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief GPBR hardware registers */ +typedef struct { + __IO GPBR_SYS_GPBR_Type SYS_GPBR[8]; /**< Offset: 0x00 (R/W 32) General Purpose Backup Register 0 */ +} Gpbr; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of General Purpose Backup Registers */ + +#endif /* _SAME70_GPBR_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/hsmci.h b/bsp/microchip/same70/bsp/same70b/include/component/hsmci.h new file mode 100644 index 0000000000..23f51b3b98 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/hsmci.h @@ -0,0 +1,1171 @@ +/** + * \file + * + * \brief Component description for HSMCI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_HSMCI_COMPONENT_H_ +#define _SAME70_HSMCI_COMPONENT_H_ +#define _SAME70_HSMCI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 High Speed MultiMedia Card Interface + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR HSMCI */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define HSMCI_6449 /**< (HSMCI) Module ID */ +#define REV_HSMCI R /**< (HSMCI) Module revision */ + +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MCIEN:1; /**< bit: 0 Multi-Media Interface Enable */ + uint32_t MCIDIS:1; /**< bit: 1 Multi-Media Interface Disable */ + uint32_t PWSEN:1; /**< bit: 2 Power Save Mode Enable */ + uint32_t PWSDIS:1; /**< bit: 3 Power Save Mode Disable */ + uint32_t :3; /**< bit: 4..6 Reserved */ + uint32_t SWRST:1; /**< bit: 7 Software Reset */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_CR_OFFSET (0x00) /**< (HSMCI_CR) Control Register Offset */ + +#define HSMCI_CR_MCIEN_Pos 0 /**< (HSMCI_CR) Multi-Media Interface Enable Position */ +#define HSMCI_CR_MCIEN_Msk (_U_(0x1) << HSMCI_CR_MCIEN_Pos) /**< (HSMCI_CR) Multi-Media Interface Enable Mask */ +#define HSMCI_CR_MCIEN HSMCI_CR_MCIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_MCIEN_Msk instead */ +#define HSMCI_CR_MCIDIS_Pos 1 /**< (HSMCI_CR) Multi-Media Interface Disable Position */ +#define HSMCI_CR_MCIDIS_Msk (_U_(0x1) << HSMCI_CR_MCIDIS_Pos) /**< (HSMCI_CR) Multi-Media Interface Disable Mask */ +#define HSMCI_CR_MCIDIS HSMCI_CR_MCIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_MCIDIS_Msk instead */ +#define HSMCI_CR_PWSEN_Pos 2 /**< (HSMCI_CR) Power Save Mode Enable Position */ +#define HSMCI_CR_PWSEN_Msk (_U_(0x1) << HSMCI_CR_PWSEN_Pos) /**< (HSMCI_CR) Power Save Mode Enable Mask */ +#define HSMCI_CR_PWSEN HSMCI_CR_PWSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_PWSEN_Msk instead */ +#define HSMCI_CR_PWSDIS_Pos 3 /**< (HSMCI_CR) Power Save Mode Disable Position */ +#define HSMCI_CR_PWSDIS_Msk (_U_(0x1) << HSMCI_CR_PWSDIS_Pos) /**< (HSMCI_CR) Power Save Mode Disable Mask */ +#define HSMCI_CR_PWSDIS HSMCI_CR_PWSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_PWSDIS_Msk instead */ +#define HSMCI_CR_SWRST_Pos 7 /**< (HSMCI_CR) Software Reset Position */ +#define HSMCI_CR_SWRST_Msk (_U_(0x1) << HSMCI_CR_SWRST_Pos) /**< (HSMCI_CR) Software Reset Mask */ +#define HSMCI_CR_SWRST HSMCI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_SWRST_Msk instead */ +#define HSMCI_CR_MASK _U_(0x8F) /**< \deprecated (HSMCI_CR) Register MASK (Use HSMCI_CR_Msk instead) */ +#define HSMCI_CR_Msk _U_(0x8F) /**< (HSMCI_CR) Register Mask */ + + +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CLKDIV:8; /**< bit: 0..7 Clock Divider */ + uint32_t PWSDIV:3; /**< bit: 8..10 Power Saving Divider */ + uint32_t RDPROOF:1; /**< bit: 11 Read Proof Enable */ + uint32_t WRPROOF:1; /**< bit: 12 Write Proof Enable */ + uint32_t FBYTE:1; /**< bit: 13 Force Byte Transfer */ + uint32_t PADV:1; /**< bit: 14 Padding Value */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t CLKODD:1; /**< bit: 16 Clock divider is odd */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_MR_OFFSET (0x04) /**< (HSMCI_MR) Mode Register Offset */ + +#define HSMCI_MR_CLKDIV_Pos 0 /**< (HSMCI_MR) Clock Divider Position */ +#define HSMCI_MR_CLKDIV_Msk (_U_(0xFF) << HSMCI_MR_CLKDIV_Pos) /**< (HSMCI_MR) Clock Divider Mask */ +#define HSMCI_MR_CLKDIV(value) (HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)) +#define HSMCI_MR_PWSDIV_Pos 8 /**< (HSMCI_MR) Power Saving Divider Position */ +#define HSMCI_MR_PWSDIV_Msk (_U_(0x7) << HSMCI_MR_PWSDIV_Pos) /**< (HSMCI_MR) Power Saving Divider Mask */ +#define HSMCI_MR_PWSDIV(value) (HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)) +#define HSMCI_MR_RDPROOF_Pos 11 /**< (HSMCI_MR) Read Proof Enable Position */ +#define HSMCI_MR_RDPROOF_Msk (_U_(0x1) << HSMCI_MR_RDPROOF_Pos) /**< (HSMCI_MR) Read Proof Enable Mask */ +#define HSMCI_MR_RDPROOF HSMCI_MR_RDPROOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_RDPROOF_Msk instead */ +#define HSMCI_MR_WRPROOF_Pos 12 /**< (HSMCI_MR) Write Proof Enable Position */ +#define HSMCI_MR_WRPROOF_Msk (_U_(0x1) << HSMCI_MR_WRPROOF_Pos) /**< (HSMCI_MR) Write Proof Enable Mask */ +#define HSMCI_MR_WRPROOF HSMCI_MR_WRPROOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_WRPROOF_Msk instead */ +#define HSMCI_MR_FBYTE_Pos 13 /**< (HSMCI_MR) Force Byte Transfer Position */ +#define HSMCI_MR_FBYTE_Msk (_U_(0x1) << HSMCI_MR_FBYTE_Pos) /**< (HSMCI_MR) Force Byte Transfer Mask */ +#define HSMCI_MR_FBYTE HSMCI_MR_FBYTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_FBYTE_Msk instead */ +#define HSMCI_MR_PADV_Pos 14 /**< (HSMCI_MR) Padding Value Position */ +#define HSMCI_MR_PADV_Msk (_U_(0x1) << HSMCI_MR_PADV_Pos) /**< (HSMCI_MR) Padding Value Mask */ +#define HSMCI_MR_PADV HSMCI_MR_PADV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_PADV_Msk instead */ +#define HSMCI_MR_CLKODD_Pos 16 /**< (HSMCI_MR) Clock divider is odd Position */ +#define HSMCI_MR_CLKODD_Msk (_U_(0x1) << HSMCI_MR_CLKODD_Pos) /**< (HSMCI_MR) Clock divider is odd Mask */ +#define HSMCI_MR_CLKODD HSMCI_MR_CLKODD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_CLKODD_Msk instead */ +#define HSMCI_MR_MASK _U_(0x17FFF) /**< \deprecated (HSMCI_MR) Register MASK (Use HSMCI_MR_Msk instead) */ +#define HSMCI_MR_Msk _U_(0x17FFF) /**< (HSMCI_MR) Register Mask */ + + +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) (R/W 32) Data Timeout Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DTOCYC:4; /**< bit: 0..3 Data Timeout Cycle Number */ + uint32_t DTOMUL:3; /**< bit: 4..6 Data Timeout Multiplier */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_DTOR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_DTOR_OFFSET (0x08) /**< (HSMCI_DTOR) Data Timeout Register Offset */ + +#define HSMCI_DTOR_DTOCYC_Pos 0 /**< (HSMCI_DTOR) Data Timeout Cycle Number Position */ +#define HSMCI_DTOR_DTOCYC_Msk (_U_(0xF) << HSMCI_DTOR_DTOCYC_Pos) /**< (HSMCI_DTOR) Data Timeout Cycle Number Mask */ +#define HSMCI_DTOR_DTOCYC(value) (HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)) +#define HSMCI_DTOR_DTOMUL_Pos 4 /**< (HSMCI_DTOR) Data Timeout Multiplier Position */ +#define HSMCI_DTOR_DTOMUL_Msk (_U_(0x7) << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) Data Timeout Multiplier Mask */ +#define HSMCI_DTOR_DTOMUL(value) (HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)) +#define HSMCI_DTOR_DTOMUL_1_Val _U_(0x0) /**< (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16_Val _U_(0x1) /**< (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128_Val _U_(0x2) /**< (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256_Val _U_(0x3) /**< (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024_Val _U_(0x4) /**< (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096_Val _U_(0x5) /**< (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536_Val _U_(0x6) /**< (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_DTOR) DTOCYC x 1048576 */ +#define HSMCI_DTOR_DTOMUL_1 (HSMCI_DTOR_DTOMUL_1_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC Position */ +#define HSMCI_DTOR_DTOMUL_16 (HSMCI_DTOR_DTOMUL_16_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 16 Position */ +#define HSMCI_DTOR_DTOMUL_128 (HSMCI_DTOR_DTOMUL_128_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 128 Position */ +#define HSMCI_DTOR_DTOMUL_256 (HSMCI_DTOR_DTOMUL_256_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 256 Position */ +#define HSMCI_DTOR_DTOMUL_1024 (HSMCI_DTOR_DTOMUL_1024_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1024 Position */ +#define HSMCI_DTOR_DTOMUL_4096 (HSMCI_DTOR_DTOMUL_4096_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 4096 Position */ +#define HSMCI_DTOR_DTOMUL_65536 (HSMCI_DTOR_DTOMUL_65536_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 65536 Position */ +#define HSMCI_DTOR_DTOMUL_1048576 (HSMCI_DTOR_DTOMUL_1048576_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1048576 Position */ +#define HSMCI_DTOR_MASK _U_(0x7F) /**< \deprecated (HSMCI_DTOR) Register MASK (Use HSMCI_DTOR_Msk instead) */ +#define HSMCI_DTOR_Msk _U_(0x7F) /**< (HSMCI_DTOR) Register Mask */ + + +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0c) (R/W 32) SD/SDIO Card Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SDCSEL:2; /**< bit: 0..1 SDCard/SDIO Slot */ + uint32_t :4; /**< bit: 2..5 Reserved */ + uint32_t SDCBUS:2; /**< bit: 6..7 SDCard/SDIO Bus Width */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_SDCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_SDCR_OFFSET (0x0C) /**< (HSMCI_SDCR) SD/SDIO Card Register Offset */ + +#define HSMCI_SDCR_SDCSEL_Pos 0 /**< (HSMCI_SDCR) SDCard/SDIO Slot Position */ +#define HSMCI_SDCR_SDCSEL_Msk (_U_(0x3) << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Slot Mask */ +#define HSMCI_SDCR_SDCSEL(value) (HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)) +#define HSMCI_SDCR_SDCSEL_SLOTA_Val _U_(0x0) /**< (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTA (HSMCI_SDCR_SDCSEL_SLOTA_Val << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) Slot A is selected. Position */ +#define HSMCI_SDCR_SDCBUS_Pos 6 /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Position */ +#define HSMCI_SDCR_SDCBUS_Msk (_U_(0x3) << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Mask */ +#define HSMCI_SDCR_SDCBUS(value) (HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)) +#define HSMCI_SDCR_SDCBUS_1_Val _U_(0x0) /**< (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4_Val _U_(0x2) /**< (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8_Val _U_(0x3) /**< (HSMCI_SDCR) 8 bits */ +#define HSMCI_SDCR_SDCBUS_1 (HSMCI_SDCR_SDCBUS_1_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 1 bit Position */ +#define HSMCI_SDCR_SDCBUS_4 (HSMCI_SDCR_SDCBUS_4_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 4 bits Position */ +#define HSMCI_SDCR_SDCBUS_8 (HSMCI_SDCR_SDCBUS_8_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 8 bits Position */ +#define HSMCI_SDCR_MASK _U_(0xC3) /**< \deprecated (HSMCI_SDCR) Register MASK (Use HSMCI_SDCR_Msk instead) */ +#define HSMCI_SDCR_Msk _U_(0xC3) /**< (HSMCI_SDCR) Register Mask */ + + +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) (R/W 32) Argument Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ARG:32; /**< bit: 0..31 Command Argument */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_ARGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_ARGR_OFFSET (0x10) /**< (HSMCI_ARGR) Argument Register Offset */ + +#define HSMCI_ARGR_ARG_Pos 0 /**< (HSMCI_ARGR) Command Argument Position */ +#define HSMCI_ARGR_ARG_Msk (_U_(0xFFFFFFFF) << HSMCI_ARGR_ARG_Pos) /**< (HSMCI_ARGR) Command Argument Mask */ +#define HSMCI_ARGR_ARG(value) (HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)) +#define HSMCI_ARGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_ARGR) Register MASK (Use HSMCI_ARGR_Msk instead) */ +#define HSMCI_ARGR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_ARGR) Register Mask */ + + +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) (/W 32) Command Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMDNB:6; /**< bit: 0..5 Command Number */ + uint32_t RSPTYP:2; /**< bit: 6..7 Response Type */ + uint32_t SPCMD:3; /**< bit: 8..10 Special Command */ + uint32_t OPDCMD:1; /**< bit: 11 Open Drain Command */ + uint32_t MAXLAT:1; /**< bit: 12 Max Latency for Command to Response */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t TRCMD:2; /**< bit: 16..17 Transfer Command */ + uint32_t TRDIR:1; /**< bit: 18 Transfer Direction */ + uint32_t TRTYP:3; /**< bit: 19..21 Transfer Type */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t IOSPCMD:2; /**< bit: 24..25 SDIO Special Command */ + uint32_t ATACS:1; /**< bit: 26 ATA with Command Completion Signal */ + uint32_t BOOT_ACK:1; /**< bit: 27 Boot Operation Acknowledge */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_CMDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_CMDR_OFFSET (0x14) /**< (HSMCI_CMDR) Command Register Offset */ + +#define HSMCI_CMDR_CMDNB_Pos 0 /**< (HSMCI_CMDR) Command Number Position */ +#define HSMCI_CMDR_CMDNB_Msk (_U_(0x3F) << HSMCI_CMDR_CMDNB_Pos) /**< (HSMCI_CMDR) Command Number Mask */ +#define HSMCI_CMDR_CMDNB(value) (HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)) +#define HSMCI_CMDR_RSPTYP_Pos 6 /**< (HSMCI_CMDR) Response Type Position */ +#define HSMCI_CMDR_RSPTYP_Msk (_U_(0x3) << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) Response Type Mask */ +#define HSMCI_CMDR_RSPTYP(value) (HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)) +#define HSMCI_CMDR_RSPTYP_NORESP_Val _U_(0x0) /**< (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT_Val _U_(0x1) /**< (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT_Val _U_(0x2) /**< (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B_Val _U_(0x3) /**< (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_RSPTYP_NORESP (HSMCI_CMDR_RSPTYP_NORESP_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) No response Position */ +#define HSMCI_CMDR_RSPTYP_48_BIT (HSMCI_CMDR_RSPTYP_48_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 48-bit response Position */ +#define HSMCI_CMDR_RSPTYP_136_BIT (HSMCI_CMDR_RSPTYP_136_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 136-bit response Position */ +#define HSMCI_CMDR_RSPTYP_R1B (HSMCI_CMDR_RSPTYP_R1B_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) R1b response type Position */ +#define HSMCI_CMDR_SPCMD_Pos 8 /**< (HSMCI_CMDR) Special Command Position */ +#define HSMCI_CMDR_SPCMD_Msk (_U_(0x7) << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Special Command Mask */ +#define HSMCI_CMDR_SPCMD(value) (HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)) +#define HSMCI_CMDR_SPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT_Val _U_(0x1) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC_Val _U_(0x2) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA_Val _U_(0x3) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD_Val _U_(0x4) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP_Val _U_(0x5) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR_Val _U_(0x6) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO_Val _U_(0x7) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_SPCMD_STD (HSMCI_CMDR_SPCMD_STD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Not a special CMD. Position */ +#define HSMCI_CMDR_SPCMD_INIT (HSMCI_CMDR_SPCMD_INIT_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. Position */ +#define HSMCI_CMDR_SPCMD_SYNC (HSMCI_CMDR_SPCMD_SYNC_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Position */ +#define HSMCI_CMDR_SPCMD_CE_ATA (HSMCI_CMDR_SPCMD_CE_ATA_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Position */ +#define HSMCI_CMDR_SPCMD_IT_CMD (HSMCI_CMDR_SPCMD_IT_CMD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_IT_RESP (HSMCI_CMDR_SPCMD_IT_RESP_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_BOR (HSMCI_CMDR_SPCMD_BOR_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. Position */ +#define HSMCI_CMDR_SPCMD_EBO (HSMCI_CMDR_SPCMD_EBO_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. Position */ +#define HSMCI_CMDR_OPDCMD_Pos 11 /**< (HSMCI_CMDR) Open Drain Command Position */ +#define HSMCI_CMDR_OPDCMD_Msk (_U_(0x1) << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open Drain Command Mask */ +#define HSMCI_CMDR_OPDCMD HSMCI_CMDR_OPDCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_OPDCMD_Msk instead */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL_Val _U_(0x0) /**< (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN_Val _U_(0x1) /**< (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (HSMCI_CMDR_OPDCMD_PUSHPULL_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Push pull command. Position */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (HSMCI_CMDR_OPDCMD_OPENDRAIN_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open drain command. Position */ +#define HSMCI_CMDR_MAXLAT_Pos 12 /**< (HSMCI_CMDR) Max Latency for Command to Response Position */ +#define HSMCI_CMDR_MAXLAT_Msk (_U_(0x1) << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) Max Latency for Command to Response Mask */ +#define HSMCI_CMDR_MAXLAT HSMCI_CMDR_MAXLAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_MAXLAT_Msk instead */ +#define HSMCI_CMDR_MAXLAT_5_Val _U_(0x0) /**< (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64_Val _U_(0x1) /**< (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_5 (HSMCI_CMDR_MAXLAT_5_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 5-cycle max latency. Position */ +#define HSMCI_CMDR_MAXLAT_64 (HSMCI_CMDR_MAXLAT_64_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 64-cycle max latency. Position */ +#define HSMCI_CMDR_TRCMD_Pos 16 /**< (HSMCI_CMDR) Transfer Command Position */ +#define HSMCI_CMDR_TRCMD_Msk (_U_(0x3) << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Transfer Command Mask */ +#define HSMCI_CMDR_TRCMD(value) (HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)) +#define HSMCI_CMDR_TRCMD_NO_DATA_Val _U_(0x0) /**< (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA_Val _U_(0x1) /**< (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA_Val _U_(0x2) /**< (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRCMD_NO_DATA (HSMCI_CMDR_TRCMD_NO_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) No data transfer Position */ +#define HSMCI_CMDR_TRCMD_START_DATA (HSMCI_CMDR_TRCMD_START_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Start data transfer Position */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (HSMCI_CMDR_TRCMD_STOP_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Stop data transfer Position */ +#define HSMCI_CMDR_TRDIR_Pos 18 /**< (HSMCI_CMDR) Transfer Direction Position */ +#define HSMCI_CMDR_TRDIR_Msk (_U_(0x1) << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Transfer Direction Mask */ +#define HSMCI_CMDR_TRDIR HSMCI_CMDR_TRDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_TRDIR_Msk instead */ +#define HSMCI_CMDR_TRDIR_WRITE_Val _U_(0x0) /**< (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ_Val _U_(0x1) /**< (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRDIR_WRITE (HSMCI_CMDR_TRDIR_WRITE_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Write. Position */ +#define HSMCI_CMDR_TRDIR_READ (HSMCI_CMDR_TRDIR_READ_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Read. Position */ +#define HSMCI_CMDR_TRTYP_Pos 19 /**< (HSMCI_CMDR) Transfer Type Position */ +#define HSMCI_CMDR_TRTYP_Msk (_U_(0x7) << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) Transfer Type Mask */ +#define HSMCI_CMDR_TRTYP(value) (HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)) +#define HSMCI_CMDR_TRTYP_SINGLE_Val _U_(0x0) /**< (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE_Val _U_(0x1) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM_Val _U_(0x2) /**< (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE_Val _U_(0x4) /**< (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK_Val _U_(0x5) /**< (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_TRTYP_SINGLE (HSMCI_CMDR_TRTYP_SINGLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Single Block Position */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (HSMCI_CMDR_TRTYP_MULTIPLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block Position */ +#define HSMCI_CMDR_TRTYP_STREAM (HSMCI_CMDR_TRTYP_STREAM_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC Stream Position */ +#define HSMCI_CMDR_TRTYP_BYTE (HSMCI_CMDR_TRTYP_BYTE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Byte Position */ +#define HSMCI_CMDR_TRTYP_BLOCK (HSMCI_CMDR_TRTYP_BLOCK_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Block Position */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 /**< (HSMCI_CMDR) SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_Msk (_U_(0x3) << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Special Command Mask */ +#define HSMCI_CMDR_IOSPCMD(value) (HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)) +#define HSMCI_CMDR_IOSPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND_Val _U_(0x1) /**< (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME_Val _U_(0x2) /**< (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_IOSPCMD_STD (HSMCI_CMDR_IOSPCMD_STD_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) Not an SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (HSMCI_CMDR_IOSPCMD_SUSPEND_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Suspend Command Position */ +#define HSMCI_CMDR_IOSPCMD_RESUME (HSMCI_CMDR_IOSPCMD_RESUME_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Resume Command Position */ +#define HSMCI_CMDR_ATACS_Pos 26 /**< (HSMCI_CMDR) ATA with Command Completion Signal Position */ +#define HSMCI_CMDR_ATACS_Msk (_U_(0x1) << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) ATA with Command Completion Signal Mask */ +#define HSMCI_CMDR_ATACS HSMCI_CMDR_ATACS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_ATACS_Msk instead */ +#define HSMCI_CMDR_ATACS_NORMAL_Val _U_(0x0) /**< (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION_Val _U_(0x1) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_ATACS_NORMAL (HSMCI_CMDR_ATACS_NORMAL_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) Normal operation mode. Position */ +#define HSMCI_CMDR_ATACS_COMPLETION (HSMCI_CMDR_ATACS_COMPLETION_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). Position */ +#define HSMCI_CMDR_BOOT_ACK_Pos 27 /**< (HSMCI_CMDR) Boot Operation Acknowledge Position */ +#define HSMCI_CMDR_BOOT_ACK_Msk (_U_(0x1) << HSMCI_CMDR_BOOT_ACK_Pos) /**< (HSMCI_CMDR) Boot Operation Acknowledge Mask */ +#define HSMCI_CMDR_BOOT_ACK HSMCI_CMDR_BOOT_ACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_BOOT_ACK_Msk instead */ +#define HSMCI_CMDR_MASK _U_(0xF3F1FFF) /**< \deprecated (HSMCI_CMDR) Register MASK (Use HSMCI_CMDR_Msk instead) */ +#define HSMCI_CMDR_Msk _U_(0xF3F1FFF) /**< (HSMCI_CMDR) Register Mask */ + + +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) (R/W 32) Block Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BCNT:16; /**< bit: 0..15 MMC/SDIO Block Count - SDIO Byte Count */ + uint32_t BLKLEN:16; /**< bit: 16..31 Data Block Length */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_BLKR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_BLKR_OFFSET (0x18) /**< (HSMCI_BLKR) Block Register Offset */ + +#define HSMCI_BLKR_BCNT_Pos 0 /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Position */ +#define HSMCI_BLKR_BCNT_Msk (_U_(0xFFFF) << HSMCI_BLKR_BCNT_Pos) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Mask */ +#define HSMCI_BLKR_BCNT(value) (HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)) +#define HSMCI_BLKR_BLKLEN_Pos 16 /**< (HSMCI_BLKR) Data Block Length Position */ +#define HSMCI_BLKR_BLKLEN_Msk (_U_(0xFFFF) << HSMCI_BLKR_BLKLEN_Pos) /**< (HSMCI_BLKR) Data Block Length Mask */ +#define HSMCI_BLKR_BLKLEN(value) (HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)) +#define HSMCI_BLKR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_BLKR) Register MASK (Use HSMCI_BLKR_Msk instead) */ +#define HSMCI_BLKR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_BLKR) Register Mask */ + + +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1c) (R/W 32) Completion Signal Timeout Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSTOCYC:4; /**< bit: 0..3 Completion Signal Timeout Cycle Number */ + uint32_t CSTOMUL:3; /**< bit: 4..6 Completion Signal Timeout Multiplier */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_CSTOR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_CSTOR_OFFSET (0x1C) /**< (HSMCI_CSTOR) Completion Signal Timeout Register Offset */ + +#define HSMCI_CSTOR_CSTOCYC_Pos 0 /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Position */ +#define HSMCI_CSTOR_CSTOCYC_Msk (_U_(0xF) << HSMCI_CSTOR_CSTOCYC_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Mask */ +#define HSMCI_CSTOR_CSTOCYC(value) (HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Position */ +#define HSMCI_CSTOR_CSTOMUL_Msk (_U_(0x7) << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Mask */ +#define HSMCI_CSTOR_CSTOMUL(value) (HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)) +#define HSMCI_CSTOR_CSTOMUL_1_Val _U_(0x0) /**< (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16_Val _U_(0x1) /**< (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128_Val _U_(0x2) /**< (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256_Val _U_(0x3) /**< (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024_Val _U_(0x4) /**< (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096_Val _U_(0x5) /**< (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536_Val _U_(0x6) /**< (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 */ +#define HSMCI_CSTOR_CSTOMUL_1 (HSMCI_CSTOR_CSTOMUL_1_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1 Position */ +#define HSMCI_CSTOR_CSTOMUL_16 (HSMCI_CSTOR_CSTOMUL_16_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 16 Position */ +#define HSMCI_CSTOR_CSTOMUL_128 (HSMCI_CSTOR_CSTOMUL_128_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 128 Position */ +#define HSMCI_CSTOR_CSTOMUL_256 (HSMCI_CSTOR_CSTOMUL_256_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 256 Position */ +#define HSMCI_CSTOR_CSTOMUL_1024 (HSMCI_CSTOR_CSTOMUL_1024_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1024 Position */ +#define HSMCI_CSTOR_CSTOMUL_4096 (HSMCI_CSTOR_CSTOMUL_4096_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 4096 Position */ +#define HSMCI_CSTOR_CSTOMUL_65536 (HSMCI_CSTOR_CSTOMUL_65536_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 65536 Position */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (HSMCI_CSTOR_CSTOMUL_1048576_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 Position */ +#define HSMCI_CSTOR_MASK _U_(0x7F) /**< \deprecated (HSMCI_CSTOR) Register MASK (Use HSMCI_CSTOR_Msk instead) */ +#define HSMCI_CSTOR_Msk _U_(0x7F) /**< (HSMCI_CSTOR) Register Mask */ + + +/* -------- HSMCI_RSPR : (HSMCI Offset: 0x20) (R/ 32) Response Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RSP:32; /**< bit: 0..31 Response */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_RSPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_RSPR_OFFSET (0x20) /**< (HSMCI_RSPR) Response Register 0 Offset */ + +#define HSMCI_RSPR_RSP_Pos 0 /**< (HSMCI_RSPR) Response Position */ +#define HSMCI_RSPR_RSP_Msk (_U_(0xFFFFFFFF) << HSMCI_RSPR_RSP_Pos) /**< (HSMCI_RSPR) Response Mask */ +#define HSMCI_RSPR_RSP(value) (HSMCI_RSPR_RSP_Msk & ((value) << HSMCI_RSPR_RSP_Pos)) +#define HSMCI_RSPR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_RSPR) Register MASK (Use HSMCI_RSPR_Msk instead) */ +#define HSMCI_RSPR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RSPR) Register Mask */ + + +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) (R/ 32) Receive Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA:32; /**< bit: 0..31 Data to Read */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_RDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_RDR_OFFSET (0x30) /**< (HSMCI_RDR) Receive Data Register Offset */ + +#define HSMCI_RDR_DATA_Pos 0 /**< (HSMCI_RDR) Data to Read Position */ +#define HSMCI_RDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_RDR_DATA_Pos) /**< (HSMCI_RDR) Data to Read Mask */ +#define HSMCI_RDR_DATA(value) (HSMCI_RDR_DATA_Msk & ((value) << HSMCI_RDR_DATA_Pos)) +#define HSMCI_RDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_RDR) Register MASK (Use HSMCI_RDR_Msk instead) */ +#define HSMCI_RDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RDR) Register Mask */ + + +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) (/W 32) Transmit Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA:32; /**< bit: 0..31 Data to Write */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_TDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_TDR_OFFSET (0x34) /**< (HSMCI_TDR) Transmit Data Register Offset */ + +#define HSMCI_TDR_DATA_Pos 0 /**< (HSMCI_TDR) Data to Write Position */ +#define HSMCI_TDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_TDR_DATA_Pos) /**< (HSMCI_TDR) Data to Write Mask */ +#define HSMCI_TDR_DATA(value) (HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)) +#define HSMCI_TDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_TDR) Register MASK (Use HSMCI_TDR_Msk instead) */ +#define HSMCI_TDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_TDR) Register Mask */ + + +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMDRDY:1; /**< bit: 0 Command Ready (cleared by writing in HSMCI_CMDR) */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready (cleared by reading HSMCI_RDR) */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Ready (cleared by writing in HSMCI_TDR) */ + uint32_t BLKE:1; /**< bit: 3 Data Block Ended (cleared on read) */ + uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress (cleared at the end of CRC16 calculation) */ + uint32_t NOTBUSY:1; /**< bit: 5 HSMCI Not Busy */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A (cleared on read) */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status */ + uint32_t CSRCV:1; /**< bit: 13 CE-ATA Completion Signal Received (cleared on read) */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RINDE:1; /**< bit: 16 Response Index Error (cleared by writing in HSMCI_CMDR) */ + uint32_t RDIRE:1; /**< bit: 17 Response Direction Error (cleared by writing in HSMCI_CMDR) */ + uint32_t RCRCE:1; /**< bit: 18 Response CRC Error (cleared by writing in HSMCI_CMDR) */ + uint32_t RENDE:1; /**< bit: 19 Response End Bit Error (cleared by writing in HSMCI_CMDR) */ + uint32_t RTOE:1; /**< bit: 20 Response Time-out Error (cleared by writing in HSMCI_CMDR) */ + uint32_t DCRCE:1; /**< bit: 21 Data CRC Error (cleared on read) */ + uint32_t DTOE:1; /**< bit: 22 Data Time-out Error (cleared on read) */ + uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time-out Error (cleared on read) */ + uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error (cleared on read) */ + uint32_t :1; /**< bit: 25 Reserved */ + uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty flag */ + uint32_t XFRDONE:1; /**< bit: 27 Transfer Done flag */ + uint32_t ACKRCV:1; /**< bit: 28 Boot Operation Acknowledge Received (cleared on read) */ + uint32_t ACKRCVE:1; /**< bit: 29 Boot Operation Acknowledge Error (cleared on read) */ + uint32_t OVRE:1; /**< bit: 30 Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ + uint32_t UNRE:1; /**< bit: 31 Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_SR_OFFSET (0x40) /**< (HSMCI_SR) Status Register Offset */ + +#define HSMCI_SR_CMDRDY_Pos 0 /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_CMDRDY_Msk (_U_(0x1) << HSMCI_SR_CMDRDY_Pos) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_CMDRDY HSMCI_SR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CMDRDY_Msk instead */ +#define HSMCI_SR_RXRDY_Pos 1 /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Position */ +#define HSMCI_SR_RXRDY_Msk (_U_(0x1) << HSMCI_SR_RXRDY_Pos) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Mask */ +#define HSMCI_SR_RXRDY HSMCI_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RXRDY_Msk instead */ +#define HSMCI_SR_TXRDY_Pos 2 /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Position */ +#define HSMCI_SR_TXRDY_Msk (_U_(0x1) << HSMCI_SR_TXRDY_Pos) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Mask */ +#define HSMCI_SR_TXRDY HSMCI_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_TXRDY_Msk instead */ +#define HSMCI_SR_BLKE_Pos 3 /**< (HSMCI_SR) Data Block Ended (cleared on read) Position */ +#define HSMCI_SR_BLKE_Msk (_U_(0x1) << HSMCI_SR_BLKE_Pos) /**< (HSMCI_SR) Data Block Ended (cleared on read) Mask */ +#define HSMCI_SR_BLKE HSMCI_SR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_BLKE_Msk instead */ +#define HSMCI_SR_DTIP_Pos 4 /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Position */ +#define HSMCI_SR_DTIP_Msk (_U_(0x1) << HSMCI_SR_DTIP_Pos) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Mask */ +#define HSMCI_SR_DTIP HSMCI_SR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DTIP_Msk instead */ +#define HSMCI_SR_NOTBUSY_Pos 5 /**< (HSMCI_SR) HSMCI Not Busy Position */ +#define HSMCI_SR_NOTBUSY_Msk (_U_(0x1) << HSMCI_SR_NOTBUSY_Pos) /**< (HSMCI_SR) HSMCI Not Busy Mask */ +#define HSMCI_SR_NOTBUSY HSMCI_SR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_NOTBUSY_Msk instead */ +#define HSMCI_SR_SDIOIRQA_Pos 8 /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Position */ +#define HSMCI_SR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_SR_SDIOIRQA_Pos) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Mask */ +#define HSMCI_SR_SDIOIRQA HSMCI_SR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_SDIOIRQA_Msk instead */ +#define HSMCI_SR_SDIOWAIT_Pos 12 /**< (HSMCI_SR) SDIO Read Wait Operation Status Position */ +#define HSMCI_SR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_SR_SDIOWAIT_Pos) /**< (HSMCI_SR) SDIO Read Wait Operation Status Mask */ +#define HSMCI_SR_SDIOWAIT HSMCI_SR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_SDIOWAIT_Msk instead */ +#define HSMCI_SR_CSRCV_Pos 13 /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Position */ +#define HSMCI_SR_CSRCV_Msk (_U_(0x1) << HSMCI_SR_CSRCV_Pos) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Mask */ +#define HSMCI_SR_CSRCV HSMCI_SR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CSRCV_Msk instead */ +#define HSMCI_SR_RINDE_Pos 16 /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RINDE_Msk (_U_(0x1) << HSMCI_SR_RINDE_Pos) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RINDE HSMCI_SR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RINDE_Msk instead */ +#define HSMCI_SR_RDIRE_Pos 17 /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RDIRE_Msk (_U_(0x1) << HSMCI_SR_RDIRE_Pos) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RDIRE HSMCI_SR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RDIRE_Msk instead */ +#define HSMCI_SR_RCRCE_Pos 18 /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RCRCE_Msk (_U_(0x1) << HSMCI_SR_RCRCE_Pos) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RCRCE HSMCI_SR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RCRCE_Msk instead */ +#define HSMCI_SR_RENDE_Pos 19 /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RENDE_Msk (_U_(0x1) << HSMCI_SR_RENDE_Pos) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RENDE HSMCI_SR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RENDE_Msk instead */ +#define HSMCI_SR_RTOE_Pos 20 /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RTOE_Msk (_U_(0x1) << HSMCI_SR_RTOE_Pos) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RTOE HSMCI_SR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RTOE_Msk instead */ +#define HSMCI_SR_DCRCE_Pos 21 /**< (HSMCI_SR) Data CRC Error (cleared on read) Position */ +#define HSMCI_SR_DCRCE_Msk (_U_(0x1) << HSMCI_SR_DCRCE_Pos) /**< (HSMCI_SR) Data CRC Error (cleared on read) Mask */ +#define HSMCI_SR_DCRCE HSMCI_SR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DCRCE_Msk instead */ +#define HSMCI_SR_DTOE_Pos 22 /**< (HSMCI_SR) Data Time-out Error (cleared on read) Position */ +#define HSMCI_SR_DTOE_Msk (_U_(0x1) << HSMCI_SR_DTOE_Pos) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_DTOE HSMCI_SR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DTOE_Msk instead */ +#define HSMCI_SR_CSTOE_Pos 23 /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Position */ +#define HSMCI_SR_CSTOE_Msk (_U_(0x1) << HSMCI_SR_CSTOE_Pos) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_CSTOE HSMCI_SR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CSTOE_Msk instead */ +#define HSMCI_SR_BLKOVRE_Pos 24 /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Position */ +#define HSMCI_SR_BLKOVRE_Msk (_U_(0x1) << HSMCI_SR_BLKOVRE_Pos) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Mask */ +#define HSMCI_SR_BLKOVRE HSMCI_SR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_BLKOVRE_Msk instead */ +#define HSMCI_SR_FIFOEMPTY_Pos 26 /**< (HSMCI_SR) FIFO empty flag Position */ +#define HSMCI_SR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_SR_FIFOEMPTY_Pos) /**< (HSMCI_SR) FIFO empty flag Mask */ +#define HSMCI_SR_FIFOEMPTY HSMCI_SR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_FIFOEMPTY_Msk instead */ +#define HSMCI_SR_XFRDONE_Pos 27 /**< (HSMCI_SR) Transfer Done flag Position */ +#define HSMCI_SR_XFRDONE_Msk (_U_(0x1) << HSMCI_SR_XFRDONE_Pos) /**< (HSMCI_SR) Transfer Done flag Mask */ +#define HSMCI_SR_XFRDONE HSMCI_SR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_XFRDONE_Msk instead */ +#define HSMCI_SR_ACKRCV_Pos 28 /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Position */ +#define HSMCI_SR_ACKRCV_Msk (_U_(0x1) << HSMCI_SR_ACKRCV_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Mask */ +#define HSMCI_SR_ACKRCV HSMCI_SR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_ACKRCV_Msk instead */ +#define HSMCI_SR_ACKRCVE_Pos 29 /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Position */ +#define HSMCI_SR_ACKRCVE_Msk (_U_(0x1) << HSMCI_SR_ACKRCVE_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Mask */ +#define HSMCI_SR_ACKRCVE HSMCI_SR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_ACKRCVE_Msk instead */ +#define HSMCI_SR_OVRE_Pos 30 /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_OVRE_Msk (_U_(0x1) << HSMCI_SR_OVRE_Pos) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_OVRE HSMCI_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_OVRE_Msk instead */ +#define HSMCI_SR_UNRE_Pos 31 /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_UNRE_Msk (_U_(0x1) << HSMCI_SR_UNRE_Pos) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_UNRE HSMCI_SR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_UNRE_Msk instead */ +#define HSMCI_SR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_SR) Register MASK (Use HSMCI_SR_Msk instead) */ +#define HSMCI_SR_Msk _U_(0xFDFF313F) /**< (HSMCI_SR) Register Mask */ + + +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Enable */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Enable */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Enable */ + uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Enable */ + uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Enable */ + uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Enable */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Enable */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Enable */ + uint32_t CSRCV:1; /**< bit: 13 Completion Signal Received Interrupt Enable */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Enable */ + uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Enable */ + uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Enable */ + uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Enable */ + uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Enable */ + uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Enable */ + uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Enable */ + uint32_t CSTOE:1; /**< bit: 23 Completion Signal Timeout Error Interrupt Enable */ + uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Enable */ + uint32_t :1; /**< bit: 25 Reserved */ + uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty Interrupt enable */ + uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt enable */ + uint32_t ACKRCV:1; /**< bit: 28 Boot Acknowledge Interrupt Enable */ + uint32_t ACKRCVE:1; /**< bit: 29 Boot Acknowledge Error Interrupt Enable */ + uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Enable */ + uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_IER_OFFSET (0x44) /**< (HSMCI_IER) Interrupt Enable Register Offset */ + +#define HSMCI_IER_CMDRDY_Pos 0 /**< (HSMCI_IER) Command Ready Interrupt Enable Position */ +#define HSMCI_IER_CMDRDY_Msk (_U_(0x1) << HSMCI_IER_CMDRDY_Pos) /**< (HSMCI_IER) Command Ready Interrupt Enable Mask */ +#define HSMCI_IER_CMDRDY HSMCI_IER_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CMDRDY_Msk instead */ +#define HSMCI_IER_RXRDY_Pos 1 /**< (HSMCI_IER) Receiver Ready Interrupt Enable Position */ +#define HSMCI_IER_RXRDY_Msk (_U_(0x1) << HSMCI_IER_RXRDY_Pos) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Mask */ +#define HSMCI_IER_RXRDY HSMCI_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RXRDY_Msk instead */ +#define HSMCI_IER_TXRDY_Pos 2 /**< (HSMCI_IER) Transmit Ready Interrupt Enable Position */ +#define HSMCI_IER_TXRDY_Msk (_U_(0x1) << HSMCI_IER_TXRDY_Pos) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Mask */ +#define HSMCI_IER_TXRDY HSMCI_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_TXRDY_Msk instead */ +#define HSMCI_IER_BLKE_Pos 3 /**< (HSMCI_IER) Data Block Ended Interrupt Enable Position */ +#define HSMCI_IER_BLKE_Msk (_U_(0x1) << HSMCI_IER_BLKE_Pos) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Mask */ +#define HSMCI_IER_BLKE HSMCI_IER_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_BLKE_Msk instead */ +#define HSMCI_IER_DTIP_Pos 4 /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Position */ +#define HSMCI_IER_DTIP_Msk (_U_(0x1) << HSMCI_IER_DTIP_Pos) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Mask */ +#define HSMCI_IER_DTIP HSMCI_IER_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DTIP_Msk instead */ +#define HSMCI_IER_NOTBUSY_Pos 5 /**< (HSMCI_IER) Data Not Busy Interrupt Enable Position */ +#define HSMCI_IER_NOTBUSY_Msk (_U_(0x1) << HSMCI_IER_NOTBUSY_Pos) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Mask */ +#define HSMCI_IER_NOTBUSY HSMCI_IER_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_NOTBUSY_Msk instead */ +#define HSMCI_IER_SDIOIRQA_Pos 8 /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Position */ +#define HSMCI_IER_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IER_SDIOIRQA_Pos) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Mask */ +#define HSMCI_IER_SDIOIRQA HSMCI_IER_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_SDIOIRQA_Msk instead */ +#define HSMCI_IER_SDIOWAIT_Pos 12 /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Position */ +#define HSMCI_IER_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IER_SDIOWAIT_Pos) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Mask */ +#define HSMCI_IER_SDIOWAIT HSMCI_IER_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_SDIOWAIT_Msk instead */ +#define HSMCI_IER_CSRCV_Pos 13 /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Position */ +#define HSMCI_IER_CSRCV_Msk (_U_(0x1) << HSMCI_IER_CSRCV_Pos) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Mask */ +#define HSMCI_IER_CSRCV HSMCI_IER_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CSRCV_Msk instead */ +#define HSMCI_IER_RINDE_Pos 16 /**< (HSMCI_IER) Response Index Error Interrupt Enable Position */ +#define HSMCI_IER_RINDE_Msk (_U_(0x1) << HSMCI_IER_RINDE_Pos) /**< (HSMCI_IER) Response Index Error Interrupt Enable Mask */ +#define HSMCI_IER_RINDE HSMCI_IER_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RINDE_Msk instead */ +#define HSMCI_IER_RDIRE_Pos 17 /**< (HSMCI_IER) Response Direction Error Interrupt Enable Position */ +#define HSMCI_IER_RDIRE_Msk (_U_(0x1) << HSMCI_IER_RDIRE_Pos) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Mask */ +#define HSMCI_IER_RDIRE HSMCI_IER_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RDIRE_Msk instead */ +#define HSMCI_IER_RCRCE_Pos 18 /**< (HSMCI_IER) Response CRC Error Interrupt Enable Position */ +#define HSMCI_IER_RCRCE_Msk (_U_(0x1) << HSMCI_IER_RCRCE_Pos) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_RCRCE HSMCI_IER_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RCRCE_Msk instead */ +#define HSMCI_IER_RENDE_Pos 19 /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Position */ +#define HSMCI_IER_RENDE_Msk (_U_(0x1) << HSMCI_IER_RENDE_Pos) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Mask */ +#define HSMCI_IER_RENDE HSMCI_IER_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RENDE_Msk instead */ +#define HSMCI_IER_RTOE_Pos 20 /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_RTOE_Msk (_U_(0x1) << HSMCI_IER_RTOE_Pos) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_RTOE HSMCI_IER_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RTOE_Msk instead */ +#define HSMCI_IER_DCRCE_Pos 21 /**< (HSMCI_IER) Data CRC Error Interrupt Enable Position */ +#define HSMCI_IER_DCRCE_Msk (_U_(0x1) << HSMCI_IER_DCRCE_Pos) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_DCRCE HSMCI_IER_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DCRCE_Msk instead */ +#define HSMCI_IER_DTOE_Pos 22 /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_DTOE_Msk (_U_(0x1) << HSMCI_IER_DTOE_Pos) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_DTOE HSMCI_IER_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DTOE_Msk instead */ +#define HSMCI_IER_CSTOE_Pos 23 /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Position */ +#define HSMCI_IER_CSTOE_Msk (_U_(0x1) << HSMCI_IER_CSTOE_Pos) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Mask */ +#define HSMCI_IER_CSTOE HSMCI_IER_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CSTOE_Msk instead */ +#define HSMCI_IER_BLKOVRE_Pos 24 /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Position */ +#define HSMCI_IER_BLKOVRE_Msk (_U_(0x1) << HSMCI_IER_BLKOVRE_Pos) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Mask */ +#define HSMCI_IER_BLKOVRE HSMCI_IER_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_BLKOVRE_Msk instead */ +#define HSMCI_IER_FIFOEMPTY_Pos 26 /**< (HSMCI_IER) FIFO empty Interrupt enable Position */ +#define HSMCI_IER_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IER_FIFOEMPTY_Pos) /**< (HSMCI_IER) FIFO empty Interrupt enable Mask */ +#define HSMCI_IER_FIFOEMPTY HSMCI_IER_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_FIFOEMPTY_Msk instead */ +#define HSMCI_IER_XFRDONE_Pos 27 /**< (HSMCI_IER) Transfer Done Interrupt enable Position */ +#define HSMCI_IER_XFRDONE_Msk (_U_(0x1) << HSMCI_IER_XFRDONE_Pos) /**< (HSMCI_IER) Transfer Done Interrupt enable Mask */ +#define HSMCI_IER_XFRDONE HSMCI_IER_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_XFRDONE_Msk instead */ +#define HSMCI_IER_ACKRCV_Pos 28 /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Position */ +#define HSMCI_IER_ACKRCV_Msk (_U_(0x1) << HSMCI_IER_ACKRCV_Pos) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCV HSMCI_IER_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_ACKRCV_Msk instead */ +#define HSMCI_IER_ACKRCVE_Pos 29 /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Position */ +#define HSMCI_IER_ACKRCVE_Msk (_U_(0x1) << HSMCI_IER_ACKRCVE_Pos) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCVE HSMCI_IER_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_ACKRCVE_Msk instead */ +#define HSMCI_IER_OVRE_Pos 30 /**< (HSMCI_IER) Overrun Interrupt Enable Position */ +#define HSMCI_IER_OVRE_Msk (_U_(0x1) << HSMCI_IER_OVRE_Pos) /**< (HSMCI_IER) Overrun Interrupt Enable Mask */ +#define HSMCI_IER_OVRE HSMCI_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_OVRE_Msk instead */ +#define HSMCI_IER_UNRE_Pos 31 /**< (HSMCI_IER) Underrun Interrupt Enable Position */ +#define HSMCI_IER_UNRE_Msk (_U_(0x1) << HSMCI_IER_UNRE_Pos) /**< (HSMCI_IER) Underrun Interrupt Enable Mask */ +#define HSMCI_IER_UNRE HSMCI_IER_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_UNRE_Msk instead */ +#define HSMCI_IER_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IER) Register MASK (Use HSMCI_IER_Msk instead) */ +#define HSMCI_IER_Msk _U_(0xFDFF313F) /**< (HSMCI_IER) Register Mask */ + + +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Disable */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Disable */ + uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Disable */ + uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Disable */ + uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Disable */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Disable */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Disable */ + uint32_t CSRCV:1; /**< bit: 13 Completion Signal received interrupt Disable */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Disable */ + uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Disable */ + uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Disable */ + uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Disable */ + uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Disable */ + uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Disable */ + uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Disable */ + uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time out Error Interrupt Disable */ + uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Disable */ + uint32_t :1; /**< bit: 25 Reserved */ + uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty Interrupt Disable */ + uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt Disable */ + uint32_t ACKRCV:1; /**< bit: 28 Boot Acknowledge Interrupt Disable */ + uint32_t ACKRCVE:1; /**< bit: 29 Boot Acknowledge Error Interrupt Disable */ + uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Disable */ + uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Disable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_IDR_OFFSET (0x48) /**< (HSMCI_IDR) Interrupt Disable Register Offset */ + +#define HSMCI_IDR_CMDRDY_Pos 0 /**< (HSMCI_IDR) Command Ready Interrupt Disable Position */ +#define HSMCI_IDR_CMDRDY_Msk (_U_(0x1) << HSMCI_IDR_CMDRDY_Pos) /**< (HSMCI_IDR) Command Ready Interrupt Disable Mask */ +#define HSMCI_IDR_CMDRDY HSMCI_IDR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CMDRDY_Msk instead */ +#define HSMCI_IDR_RXRDY_Pos 1 /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Position */ +#define HSMCI_IDR_RXRDY_Msk (_U_(0x1) << HSMCI_IDR_RXRDY_Pos) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Mask */ +#define HSMCI_IDR_RXRDY HSMCI_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RXRDY_Msk instead */ +#define HSMCI_IDR_TXRDY_Pos 2 /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Position */ +#define HSMCI_IDR_TXRDY_Msk (_U_(0x1) << HSMCI_IDR_TXRDY_Pos) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Mask */ +#define HSMCI_IDR_TXRDY HSMCI_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_TXRDY_Msk instead */ +#define HSMCI_IDR_BLKE_Pos 3 /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Position */ +#define HSMCI_IDR_BLKE_Msk (_U_(0x1) << HSMCI_IDR_BLKE_Pos) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Mask */ +#define HSMCI_IDR_BLKE HSMCI_IDR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_BLKE_Msk instead */ +#define HSMCI_IDR_DTIP_Pos 4 /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Position */ +#define HSMCI_IDR_DTIP_Msk (_U_(0x1) << HSMCI_IDR_DTIP_Pos) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Mask */ +#define HSMCI_IDR_DTIP HSMCI_IDR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DTIP_Msk instead */ +#define HSMCI_IDR_NOTBUSY_Pos 5 /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Position */ +#define HSMCI_IDR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IDR_NOTBUSY_Pos) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Mask */ +#define HSMCI_IDR_NOTBUSY HSMCI_IDR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_NOTBUSY_Msk instead */ +#define HSMCI_IDR_SDIOIRQA_Pos 8 /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Position */ +#define HSMCI_IDR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IDR_SDIOIRQA_Pos) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOIRQA HSMCI_IDR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_SDIOIRQA_Msk instead */ +#define HSMCI_IDR_SDIOWAIT_Pos 12 /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Position */ +#define HSMCI_IDR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IDR_SDIOWAIT_Pos) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOWAIT HSMCI_IDR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_SDIOWAIT_Msk instead */ +#define HSMCI_IDR_CSRCV_Pos 13 /**< (HSMCI_IDR) Completion Signal received interrupt Disable Position */ +#define HSMCI_IDR_CSRCV_Msk (_U_(0x1) << HSMCI_IDR_CSRCV_Pos) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Mask */ +#define HSMCI_IDR_CSRCV HSMCI_IDR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CSRCV_Msk instead */ +#define HSMCI_IDR_RINDE_Pos 16 /**< (HSMCI_IDR) Response Index Error Interrupt Disable Position */ +#define HSMCI_IDR_RINDE_Msk (_U_(0x1) << HSMCI_IDR_RINDE_Pos) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Mask */ +#define HSMCI_IDR_RINDE HSMCI_IDR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RINDE_Msk instead */ +#define HSMCI_IDR_RDIRE_Pos 17 /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Position */ +#define HSMCI_IDR_RDIRE_Msk (_U_(0x1) << HSMCI_IDR_RDIRE_Pos) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Mask */ +#define HSMCI_IDR_RDIRE HSMCI_IDR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RDIRE_Msk instead */ +#define HSMCI_IDR_RCRCE_Pos 18 /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_RCRCE_Msk (_U_(0x1) << HSMCI_IDR_RCRCE_Pos) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_RCRCE HSMCI_IDR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RCRCE_Msk instead */ +#define HSMCI_IDR_RENDE_Pos 19 /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Position */ +#define HSMCI_IDR_RENDE_Msk (_U_(0x1) << HSMCI_IDR_RENDE_Pos) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Mask */ +#define HSMCI_IDR_RENDE HSMCI_IDR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RENDE_Msk instead */ +#define HSMCI_IDR_RTOE_Pos 20 /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_RTOE_Msk (_U_(0x1) << HSMCI_IDR_RTOE_Pos) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_RTOE HSMCI_IDR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RTOE_Msk instead */ +#define HSMCI_IDR_DCRCE_Pos 21 /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_DCRCE_Msk (_U_(0x1) << HSMCI_IDR_DCRCE_Pos) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_DCRCE HSMCI_IDR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DCRCE_Msk instead */ +#define HSMCI_IDR_DTOE_Pos 22 /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_DTOE_Msk (_U_(0x1) << HSMCI_IDR_DTOE_Pos) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_DTOE HSMCI_IDR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DTOE_Msk instead */ +#define HSMCI_IDR_CSTOE_Pos 23 /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Position */ +#define HSMCI_IDR_CSTOE_Msk (_U_(0x1) << HSMCI_IDR_CSTOE_Pos) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Mask */ +#define HSMCI_IDR_CSTOE HSMCI_IDR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CSTOE_Msk instead */ +#define HSMCI_IDR_BLKOVRE_Pos 24 /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Position */ +#define HSMCI_IDR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IDR_BLKOVRE_Pos) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Mask */ +#define HSMCI_IDR_BLKOVRE HSMCI_IDR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_BLKOVRE_Msk instead */ +#define HSMCI_IDR_FIFOEMPTY_Pos 26 /**< (HSMCI_IDR) FIFO empty Interrupt Disable Position */ +#define HSMCI_IDR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IDR_FIFOEMPTY_Pos) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Mask */ +#define HSMCI_IDR_FIFOEMPTY HSMCI_IDR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_FIFOEMPTY_Msk instead */ +#define HSMCI_IDR_XFRDONE_Pos 27 /**< (HSMCI_IDR) Transfer Done Interrupt Disable Position */ +#define HSMCI_IDR_XFRDONE_Msk (_U_(0x1) << HSMCI_IDR_XFRDONE_Pos) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Mask */ +#define HSMCI_IDR_XFRDONE HSMCI_IDR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_XFRDONE_Msk instead */ +#define HSMCI_IDR_ACKRCV_Pos 28 /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCV_Msk (_U_(0x1) << HSMCI_IDR_ACKRCV_Pos) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCV HSMCI_IDR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_ACKRCV_Msk instead */ +#define HSMCI_IDR_ACKRCVE_Pos 29 /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IDR_ACKRCVE_Pos) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCVE HSMCI_IDR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_ACKRCVE_Msk instead */ +#define HSMCI_IDR_OVRE_Pos 30 /**< (HSMCI_IDR) Overrun Interrupt Disable Position */ +#define HSMCI_IDR_OVRE_Msk (_U_(0x1) << HSMCI_IDR_OVRE_Pos) /**< (HSMCI_IDR) Overrun Interrupt Disable Mask */ +#define HSMCI_IDR_OVRE HSMCI_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_OVRE_Msk instead */ +#define HSMCI_IDR_UNRE_Pos 31 /**< (HSMCI_IDR) Underrun Interrupt Disable Position */ +#define HSMCI_IDR_UNRE_Msk (_U_(0x1) << HSMCI_IDR_UNRE_Pos) /**< (HSMCI_IDR) Underrun Interrupt Disable Mask */ +#define HSMCI_IDR_UNRE HSMCI_IDR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_UNRE_Msk instead */ +#define HSMCI_IDR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IDR) Register MASK (Use HSMCI_IDR_Msk instead) */ +#define HSMCI_IDR_Msk _U_(0xFDFF313F) /**< (HSMCI_IDR) Register Mask */ + + +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Mask */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Mask */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Mask */ + uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Mask */ + uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Mask */ + uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Mask */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Mask */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Mask */ + uint32_t CSRCV:1; /**< bit: 13 Completion Signal Received Interrupt Mask */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Mask */ + uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Mask */ + uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Mask */ + uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Mask */ + uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Mask */ + uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Mask */ + uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Mask */ + uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time-out Error Interrupt Mask */ + uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Mask */ + uint32_t :1; /**< bit: 25 Reserved */ + uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO Empty Interrupt Mask */ + uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt Mask */ + uint32_t ACKRCV:1; /**< bit: 28 Boot Operation Acknowledge Received Interrupt Mask */ + uint32_t ACKRCVE:1; /**< bit: 29 Boot Operation Acknowledge Error Interrupt Mask */ + uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Mask */ + uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Mask */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_IMR_OFFSET (0x4C) /**< (HSMCI_IMR) Interrupt Mask Register Offset */ + +#define HSMCI_IMR_CMDRDY_Pos 0 /**< (HSMCI_IMR) Command Ready Interrupt Mask Position */ +#define HSMCI_IMR_CMDRDY_Msk (_U_(0x1) << HSMCI_IMR_CMDRDY_Pos) /**< (HSMCI_IMR) Command Ready Interrupt Mask Mask */ +#define HSMCI_IMR_CMDRDY HSMCI_IMR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CMDRDY_Msk instead */ +#define HSMCI_IMR_RXRDY_Pos 1 /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Position */ +#define HSMCI_IMR_RXRDY_Msk (_U_(0x1) << HSMCI_IMR_RXRDY_Pos) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Mask */ +#define HSMCI_IMR_RXRDY HSMCI_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RXRDY_Msk instead */ +#define HSMCI_IMR_TXRDY_Pos 2 /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Position */ +#define HSMCI_IMR_TXRDY_Msk (_U_(0x1) << HSMCI_IMR_TXRDY_Pos) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Mask */ +#define HSMCI_IMR_TXRDY HSMCI_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_TXRDY_Msk instead */ +#define HSMCI_IMR_BLKE_Pos 3 /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Position */ +#define HSMCI_IMR_BLKE_Msk (_U_(0x1) << HSMCI_IMR_BLKE_Pos) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Mask */ +#define HSMCI_IMR_BLKE HSMCI_IMR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_BLKE_Msk instead */ +#define HSMCI_IMR_DTIP_Pos 4 /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Position */ +#define HSMCI_IMR_DTIP_Msk (_U_(0x1) << HSMCI_IMR_DTIP_Pos) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Mask */ +#define HSMCI_IMR_DTIP HSMCI_IMR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DTIP_Msk instead */ +#define HSMCI_IMR_NOTBUSY_Pos 5 /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Position */ +#define HSMCI_IMR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IMR_NOTBUSY_Pos) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Mask */ +#define HSMCI_IMR_NOTBUSY HSMCI_IMR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_NOTBUSY_Msk instead */ +#define HSMCI_IMR_SDIOIRQA_Pos 8 /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Position */ +#define HSMCI_IMR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IMR_SDIOIRQA_Pos) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOIRQA HSMCI_IMR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_SDIOIRQA_Msk instead */ +#define HSMCI_IMR_SDIOWAIT_Pos 12 /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Position */ +#define HSMCI_IMR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IMR_SDIOWAIT_Pos) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOWAIT HSMCI_IMR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_SDIOWAIT_Msk instead */ +#define HSMCI_IMR_CSRCV_Pos 13 /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Position */ +#define HSMCI_IMR_CSRCV_Msk (_U_(0x1) << HSMCI_IMR_CSRCV_Pos) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Mask */ +#define HSMCI_IMR_CSRCV HSMCI_IMR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CSRCV_Msk instead */ +#define HSMCI_IMR_RINDE_Pos 16 /**< (HSMCI_IMR) Response Index Error Interrupt Mask Position */ +#define HSMCI_IMR_RINDE_Msk (_U_(0x1) << HSMCI_IMR_RINDE_Pos) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Mask */ +#define HSMCI_IMR_RINDE HSMCI_IMR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RINDE_Msk instead */ +#define HSMCI_IMR_RDIRE_Pos 17 /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Position */ +#define HSMCI_IMR_RDIRE_Msk (_U_(0x1) << HSMCI_IMR_RDIRE_Pos) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Mask */ +#define HSMCI_IMR_RDIRE HSMCI_IMR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RDIRE_Msk instead */ +#define HSMCI_IMR_RCRCE_Pos 18 /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_RCRCE_Msk (_U_(0x1) << HSMCI_IMR_RCRCE_Pos) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_RCRCE HSMCI_IMR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RCRCE_Msk instead */ +#define HSMCI_IMR_RENDE_Pos 19 /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Position */ +#define HSMCI_IMR_RENDE_Msk (_U_(0x1) << HSMCI_IMR_RENDE_Pos) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Mask */ +#define HSMCI_IMR_RENDE HSMCI_IMR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RENDE_Msk instead */ +#define HSMCI_IMR_RTOE_Pos 20 /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_RTOE_Msk (_U_(0x1) << HSMCI_IMR_RTOE_Pos) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_RTOE HSMCI_IMR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RTOE_Msk instead */ +#define HSMCI_IMR_DCRCE_Pos 21 /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_DCRCE_Msk (_U_(0x1) << HSMCI_IMR_DCRCE_Pos) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_DCRCE HSMCI_IMR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DCRCE_Msk instead */ +#define HSMCI_IMR_DTOE_Pos 22 /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_DTOE_Msk (_U_(0x1) << HSMCI_IMR_DTOE_Pos) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_DTOE HSMCI_IMR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DTOE_Msk instead */ +#define HSMCI_IMR_CSTOE_Pos 23 /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_CSTOE_Msk (_U_(0x1) << HSMCI_IMR_CSTOE_Pos) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_CSTOE HSMCI_IMR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CSTOE_Msk instead */ +#define HSMCI_IMR_BLKOVRE_Pos 24 /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Position */ +#define HSMCI_IMR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IMR_BLKOVRE_Pos) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Mask */ +#define HSMCI_IMR_BLKOVRE HSMCI_IMR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_BLKOVRE_Msk instead */ +#define HSMCI_IMR_FIFOEMPTY_Pos 26 /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Position */ +#define HSMCI_IMR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IMR_FIFOEMPTY_Pos) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Mask */ +#define HSMCI_IMR_FIFOEMPTY HSMCI_IMR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_FIFOEMPTY_Msk instead */ +#define HSMCI_IMR_XFRDONE_Pos 27 /**< (HSMCI_IMR) Transfer Done Interrupt Mask Position */ +#define HSMCI_IMR_XFRDONE_Msk (_U_(0x1) << HSMCI_IMR_XFRDONE_Pos) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Mask */ +#define HSMCI_IMR_XFRDONE HSMCI_IMR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_XFRDONE_Msk instead */ +#define HSMCI_IMR_ACKRCV_Pos 28 /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCV_Msk (_U_(0x1) << HSMCI_IMR_ACKRCV_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCV HSMCI_IMR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_ACKRCV_Msk instead */ +#define HSMCI_IMR_ACKRCVE_Pos 29 /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IMR_ACKRCVE_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCVE HSMCI_IMR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_ACKRCVE_Msk instead */ +#define HSMCI_IMR_OVRE_Pos 30 /**< (HSMCI_IMR) Overrun Interrupt Mask Position */ +#define HSMCI_IMR_OVRE_Msk (_U_(0x1) << HSMCI_IMR_OVRE_Pos) /**< (HSMCI_IMR) Overrun Interrupt Mask Mask */ +#define HSMCI_IMR_OVRE HSMCI_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_OVRE_Msk instead */ +#define HSMCI_IMR_UNRE_Pos 31 /**< (HSMCI_IMR) Underrun Interrupt Mask Position */ +#define HSMCI_IMR_UNRE_Msk (_U_(0x1) << HSMCI_IMR_UNRE_Pos) /**< (HSMCI_IMR) Underrun Interrupt Mask Mask */ +#define HSMCI_IMR_UNRE HSMCI_IMR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_UNRE_Msk instead */ +#define HSMCI_IMR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IMR) Register MASK (Use HSMCI_IMR_Msk instead) */ +#define HSMCI_IMR_Msk _U_(0xFDFF313F) /**< (HSMCI_IMR) Register Mask */ + + +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) (R/W 32) DMA Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t CHKSIZE:3; /**< bit: 4..6 DMA Channel Read and Write Chunk Size */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t DMAEN:1; /**< bit: 8 DMA Hardware Handshaking Enable */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_DMA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_DMA_OFFSET (0x50) /**< (HSMCI_DMA) DMA Configuration Register Offset */ + +#define HSMCI_DMA_CHKSIZE_Pos 4 /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Position */ +#define HSMCI_DMA_CHKSIZE_Msk (_U_(0x7) << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Mask */ +#define HSMCI_DMA_CHKSIZE(value) (HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)) +#define HSMCI_DMA_CHKSIZE_1_Val _U_(0x0) /**< (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2_Val _U_(0x1) /**< (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4_Val _U_(0x2) /**< (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8_Val _U_(0x3) /**< (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16_Val _U_(0x4) /**< (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_CHKSIZE_1 (HSMCI_DMA_CHKSIZE_1_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 1 data available Position */ +#define HSMCI_DMA_CHKSIZE_2 (HSMCI_DMA_CHKSIZE_2_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 2 data available Position */ +#define HSMCI_DMA_CHKSIZE_4 (HSMCI_DMA_CHKSIZE_4_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 4 data available Position */ +#define HSMCI_DMA_CHKSIZE_8 (HSMCI_DMA_CHKSIZE_8_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 8 data available Position */ +#define HSMCI_DMA_CHKSIZE_16 (HSMCI_DMA_CHKSIZE_16_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 16 data available Position */ +#define HSMCI_DMA_DMAEN_Pos 8 /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Position */ +#define HSMCI_DMA_DMAEN_Msk (_U_(0x1) << HSMCI_DMA_DMAEN_Pos) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Mask */ +#define HSMCI_DMA_DMAEN HSMCI_DMA_DMAEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_DMA_DMAEN_Msk instead */ +#define HSMCI_DMA_MASK _U_(0x170) /**< \deprecated (HSMCI_DMA) Register MASK (Use HSMCI_DMA_Msk instead) */ +#define HSMCI_DMA_Msk _U_(0x170) /**< (HSMCI_DMA) Register Mask */ + + +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) (R/W 32) Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FIFOMODE:1; /**< bit: 0 HSMCI Internal FIFO control mode */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t FERRCTRL:1; /**< bit: 4 Flow Error flag reset control mode */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t HSMODE:1; /**< bit: 8 High Speed Mode */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t LSYNC:1; /**< bit: 12 Synchronize on the last block */ + uint32_t :19; /**< bit: 13..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_CFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_CFG_OFFSET (0x54) /**< (HSMCI_CFG) Configuration Register Offset */ + +#define HSMCI_CFG_FIFOMODE_Pos 0 /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Position */ +#define HSMCI_CFG_FIFOMODE_Msk (_U_(0x1) << HSMCI_CFG_FIFOMODE_Pos) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Mask */ +#define HSMCI_CFG_FIFOMODE HSMCI_CFG_FIFOMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_FIFOMODE_Msk instead */ +#define HSMCI_CFG_FERRCTRL_Pos 4 /**< (HSMCI_CFG) Flow Error flag reset control mode Position */ +#define HSMCI_CFG_FERRCTRL_Msk (_U_(0x1) << HSMCI_CFG_FERRCTRL_Pos) /**< (HSMCI_CFG) Flow Error flag reset control mode Mask */ +#define HSMCI_CFG_FERRCTRL HSMCI_CFG_FERRCTRL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_FERRCTRL_Msk instead */ +#define HSMCI_CFG_HSMODE_Pos 8 /**< (HSMCI_CFG) High Speed Mode Position */ +#define HSMCI_CFG_HSMODE_Msk (_U_(0x1) << HSMCI_CFG_HSMODE_Pos) /**< (HSMCI_CFG) High Speed Mode Mask */ +#define HSMCI_CFG_HSMODE HSMCI_CFG_HSMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_HSMODE_Msk instead */ +#define HSMCI_CFG_LSYNC_Pos 12 /**< (HSMCI_CFG) Synchronize on the last block Position */ +#define HSMCI_CFG_LSYNC_Msk (_U_(0x1) << HSMCI_CFG_LSYNC_Pos) /**< (HSMCI_CFG) Synchronize on the last block Mask */ +#define HSMCI_CFG_LSYNC HSMCI_CFG_LSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_LSYNC_Msk instead */ +#define HSMCI_CFG_MASK _U_(0x1111) /**< \deprecated (HSMCI_CFG) Register MASK (Use HSMCI_CFG_Msk instead) */ +#define HSMCI_CFG_Msk _U_(0x1111) /**< (HSMCI_CFG) Register Mask */ + + +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protect Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protect Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_WPMR_OFFSET (0xE4) /**< (HSMCI_WPMR) Write Protection Mode Register Offset */ + +#define HSMCI_WPMR_WPEN_Pos 0 /**< (HSMCI_WPMR) Write Protect Enable Position */ +#define HSMCI_WPMR_WPEN_Msk (_U_(0x1) << HSMCI_WPMR_WPEN_Pos) /**< (HSMCI_WPMR) Write Protect Enable Mask */ +#define HSMCI_WPMR_WPEN HSMCI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_WPMR_WPEN_Msk instead */ +#define HSMCI_WPMR_WPKEY_Pos 8 /**< (HSMCI_WPMR) Write Protect Key Position */ +#define HSMCI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Write Protect Key Mask */ +#define HSMCI_WPMR_WPKEY(value) (HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)) +#define HSMCI_WPMR_WPKEY_PASSWD_Val _U_(0x4D4349) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define HSMCI_WPMR_WPKEY_PASSWD (HSMCI_WPMR_WPKEY_PASSWD_Val << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define HSMCI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (HSMCI_WPMR) Register MASK (Use HSMCI_WPMR_Msk instead) */ +#define HSMCI_WPMR_Msk _U_(0xFFFFFF01) /**< (HSMCI_WPMR) Register Mask */ + + +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_WPSR_OFFSET (0xE8) /**< (HSMCI_WPSR) Write Protection Status Register Offset */ + +#define HSMCI_WPSR_WPVS_Pos 0 /**< (HSMCI_WPSR) Write Protection Violation Status Position */ +#define HSMCI_WPSR_WPVS_Msk (_U_(0x1) << HSMCI_WPSR_WPVS_Pos) /**< (HSMCI_WPSR) Write Protection Violation Status Mask */ +#define HSMCI_WPSR_WPVS HSMCI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_WPSR_WPVS_Msk instead */ +#define HSMCI_WPSR_WPVSRC_Pos 8 /**< (HSMCI_WPSR) Write Protection Violation Source Position */ +#define HSMCI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << HSMCI_WPSR_WPVSRC_Pos) /**< (HSMCI_WPSR) Write Protection Violation Source Mask */ +#define HSMCI_WPSR_WPVSRC(value) (HSMCI_WPSR_WPVSRC_Msk & ((value) << HSMCI_WPSR_WPVSRC_Pos)) +#define HSMCI_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (HSMCI_WPSR) Register MASK (Use HSMCI_WPSR_Msk instead) */ +#define HSMCI_WPSR_Msk _U_(0xFFFF01) /**< (HSMCI_WPSR) Register Mask */ + + +/* -------- HSMCI_FIFO : (HSMCI Offset: 0x200) (R/W 32) FIFO Memory Aperture0 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATA:32; /**< bit: 0..31 Data to Read or Data to Write */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} HSMCI_FIFO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define HSMCI_FIFO_OFFSET (0x200) /**< (HSMCI_FIFO) FIFO Memory Aperture0 0 Offset */ + +#define HSMCI_FIFO_DATA_Pos 0 /**< (HSMCI_FIFO) Data to Read or Data to Write Position */ +#define HSMCI_FIFO_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_FIFO_DATA_Pos) /**< (HSMCI_FIFO) Data to Read or Data to Write Mask */ +#define HSMCI_FIFO_DATA(value) (HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)) +#define HSMCI_FIFO_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_FIFO) Register MASK (Use HSMCI_FIFO_Msk instead) */ +#define HSMCI_FIFO_Msk _U_(0xFFFFFFFF) /**< (HSMCI_FIFO) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief HSMCI hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< (HSMCI Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< (HSMCI Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< (HSMCI Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< (HSMCI Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< (HSMCI Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< (HSMCI Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< (HSMCI Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< (HSMCI Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< (HSMCI Offset: 0x20) Response Register 0 */ + __I uint32_t HSMCI_RDR; /**< (HSMCI Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< (HSMCI Offset: 0x34) Transmit Data Register */ + __I uint8_t Reserved1[8]; + __I uint32_t HSMCI_SR; /**< (HSMCI Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< (HSMCI Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< (HSMCI Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< (HSMCI Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< (HSMCI Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< (HSMCI Offset: 0x54) Configuration Register */ + __I uint8_t Reserved2[140]; + __IO uint32_t HSMCI_WPMR; /**< (HSMCI Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< (HSMCI Offset: 0xE8) Write Protection Status Register */ + __I uint8_t Reserved3[276]; + __IO uint32_t HSMCI_FIFO[256]; /**< (HSMCI Offset: 0x200) FIFO Memory Aperture0 0 */ +} Hsmci; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief HSMCI hardware registers */ +typedef struct { + __O HSMCI_CR_Type HSMCI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO HSMCI_MR_Type HSMCI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO HSMCI_DTOR_Type HSMCI_DTOR; /**< Offset: 0x08 (R/W 32) Data Timeout Register */ + __IO HSMCI_SDCR_Type HSMCI_SDCR; /**< Offset: 0x0C (R/W 32) SD/SDIO Card Register */ + __IO HSMCI_ARGR_Type HSMCI_ARGR; /**< Offset: 0x10 (R/W 32) Argument Register */ + __O HSMCI_CMDR_Type HSMCI_CMDR; /**< Offset: 0x14 ( /W 32) Command Register */ + __IO HSMCI_BLKR_Type HSMCI_BLKR; /**< Offset: 0x18 (R/W 32) Block Register */ + __IO HSMCI_CSTOR_Type HSMCI_CSTOR; /**< Offset: 0x1C (R/W 32) Completion Signal Timeout Register */ + __I HSMCI_RSPR_Type HSMCI_RSPR[4]; /**< Offset: 0x20 (R/ 32) Response Register 0 */ + __I HSMCI_RDR_Type HSMCI_RDR; /**< Offset: 0x30 (R/ 32) Receive Data Register */ + __O HSMCI_TDR_Type HSMCI_TDR; /**< Offset: 0x34 ( /W 32) Transmit Data Register */ + __I uint8_t Reserved1[8]; + __I HSMCI_SR_Type HSMCI_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O HSMCI_IER_Type HSMCI_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O HSMCI_IDR_Type HSMCI_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I HSMCI_IMR_Type HSMCI_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __IO HSMCI_DMA_Type HSMCI_DMA; /**< Offset: 0x50 (R/W 32) DMA Configuration Register */ + __IO HSMCI_CFG_Type HSMCI_CFG; /**< Offset: 0x54 (R/W 32) Configuration Register */ + __I uint8_t Reserved2[140]; + __IO HSMCI_WPMR_Type HSMCI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I HSMCI_WPSR_Type HSMCI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved3[276]; + __IO HSMCI_FIFO_Type HSMCI_FIFO[256]; /**< Offset: 0x200 (R/W 32) FIFO Memory Aperture0 0 */ +} Hsmci; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of High Speed MultiMedia Card Interface */ + +#endif /* _SAME70_HSMCI_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/i2sc.h b/bsp/microchip/same70/bsp/same70b/include/component/i2sc.h new file mode 100644 index 0000000000..65d126f186 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/i2sc.h @@ -0,0 +1,526 @@ +/** + * \file + * + * \brief Component description for I2SC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_I2SC_COMPONENT_H_ +#define _SAME70_I2SC_COMPONENT_H_ +#define _SAME70_I2SC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Inter-IC Sound Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR I2SC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define I2SC_11241 /**< (I2SC) Module ID */ +#define REV_I2SC N /**< (I2SC) Module revision */ + +/* -------- I2SC_CR : (I2SC Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXEN:1; /**< bit: 0 Receiver Enable */ + uint32_t RXDIS:1; /**< bit: 1 Receiver Disable */ + uint32_t CKEN:1; /**< bit: 2 Clocks Enable */ + uint32_t CKDIS:1; /**< bit: 3 Clocks Disable */ + uint32_t TXEN:1; /**< bit: 4 Transmitter Enable */ + uint32_t TXDIS:1; /**< bit: 5 Transmitter Disable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SWRST:1; /**< bit: 7 Software Reset */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_CR_OFFSET (0x00) /**< (I2SC_CR) Control Register Offset */ + +#define I2SC_CR_RXEN_Pos 0 /**< (I2SC_CR) Receiver Enable Position */ +#define I2SC_CR_RXEN_Msk (_U_(0x1) << I2SC_CR_RXEN_Pos) /**< (I2SC_CR) Receiver Enable Mask */ +#define I2SC_CR_RXEN I2SC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXEN_Msk instead */ +#define I2SC_CR_RXDIS_Pos 1 /**< (I2SC_CR) Receiver Disable Position */ +#define I2SC_CR_RXDIS_Msk (_U_(0x1) << I2SC_CR_RXDIS_Pos) /**< (I2SC_CR) Receiver Disable Mask */ +#define I2SC_CR_RXDIS I2SC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_RXDIS_Msk instead */ +#define I2SC_CR_CKEN_Pos 2 /**< (I2SC_CR) Clocks Enable Position */ +#define I2SC_CR_CKEN_Msk (_U_(0x1) << I2SC_CR_CKEN_Pos) /**< (I2SC_CR) Clocks Enable Mask */ +#define I2SC_CR_CKEN I2SC_CR_CKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKEN_Msk instead */ +#define I2SC_CR_CKDIS_Pos 3 /**< (I2SC_CR) Clocks Disable Position */ +#define I2SC_CR_CKDIS_Msk (_U_(0x1) << I2SC_CR_CKDIS_Pos) /**< (I2SC_CR) Clocks Disable Mask */ +#define I2SC_CR_CKDIS I2SC_CR_CKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_CKDIS_Msk instead */ +#define I2SC_CR_TXEN_Pos 4 /**< (I2SC_CR) Transmitter Enable Position */ +#define I2SC_CR_TXEN_Msk (_U_(0x1) << I2SC_CR_TXEN_Pos) /**< (I2SC_CR) Transmitter Enable Mask */ +#define I2SC_CR_TXEN I2SC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXEN_Msk instead */ +#define I2SC_CR_TXDIS_Pos 5 /**< (I2SC_CR) Transmitter Disable Position */ +#define I2SC_CR_TXDIS_Msk (_U_(0x1) << I2SC_CR_TXDIS_Pos) /**< (I2SC_CR) Transmitter Disable Mask */ +#define I2SC_CR_TXDIS I2SC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_TXDIS_Msk instead */ +#define I2SC_CR_SWRST_Pos 7 /**< (I2SC_CR) Software Reset Position */ +#define I2SC_CR_SWRST_Msk (_U_(0x1) << I2SC_CR_SWRST_Pos) /**< (I2SC_CR) Software Reset Mask */ +#define I2SC_CR_SWRST I2SC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_CR_SWRST_Msk instead */ +#define I2SC_CR_MASK _U_(0xBF) /**< \deprecated (I2SC_CR) Register MASK (Use I2SC_CR_Msk instead) */ +#define I2SC_CR_Msk _U_(0xBF) /**< (I2SC_CR) Register Mask */ + + +/* -------- I2SC_MR : (I2SC Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MODE:1; /**< bit: 0 Inter-IC Sound Controller Mode */ + uint32_t :1; /**< bit: 1 Reserved */ + uint32_t DATALENGTH:3; /**< bit: 2..4 Data Word Length */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t RXMONO:1; /**< bit: 8 Receive Mono */ + uint32_t RXDMA:1; /**< bit: 9 Single or Multiple DMA Controller Channels for Receiver */ + uint32_t RXLOOP:1; /**< bit: 10 Loopback Test Mode */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t TXMONO:1; /**< bit: 12 Transmit Mono */ + uint32_t TXDMA:1; /**< bit: 13 Single or Multiple DMA Controller Channels for Transmitter */ + uint32_t TXSAME:1; /**< bit: 14 Transmit Data when Underrun */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t IMCKDIV:6; /**< bit: 16..21 Selected Clock to I2SC Master Clock Ratio */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t IMCKFS:6; /**< bit: 24..29 Master Clock to fs Ratio */ + uint32_t IMCKMODE:1; /**< bit: 30 Master Clock Mode */ + uint32_t IWS:1; /**< bit: 31 I2SC_WS Slot Width */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_MR_OFFSET (0x04) /**< (I2SC_MR) Mode Register Offset */ + +#define I2SC_MR_MODE_Pos 0 /**< (I2SC_MR) Inter-IC Sound Controller Mode Position */ +#define I2SC_MR_MODE_Msk (_U_(0x1) << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Inter-IC Sound Controller Mode Mask */ +#define I2SC_MR_MODE I2SC_MR_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_MODE_Msk instead */ +#define I2SC_MR_MODE_SLAVE_Val _U_(0x0) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. */ +#define I2SC_MR_MODE_MASTER_Val _U_(0x1) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. */ +#define I2SC_MR_MODE_SLAVE (I2SC_MR_MODE_SLAVE_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. Position */ +#define I2SC_MR_MODE_MASTER (I2SC_MR_MODE_MASTER_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. Position */ +#define I2SC_MR_DATALENGTH_Pos 2 /**< (I2SC_MR) Data Word Length Position */ +#define I2SC_MR_DATALENGTH_Msk (_U_(0x7) << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data Word Length Mask */ +#define I2SC_MR_DATALENGTH(value) (I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)) +#define I2SC_MR_DATALENGTH_32_BITS_Val _U_(0x0) /**< (I2SC_MR) Data length is set to 32 bits */ +#define I2SC_MR_DATALENGTH_24_BITS_Val _U_(0x1) /**< (I2SC_MR) Data length is set to 24 bits */ +#define I2SC_MR_DATALENGTH_20_BITS_Val _U_(0x2) /**< (I2SC_MR) Data length is set to 20 bits */ +#define I2SC_MR_DATALENGTH_18_BITS_Val _U_(0x3) /**< (I2SC_MR) Data length is set to 18 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_Val _U_(0x4) /**< (I2SC_MR) Data length is set to 16 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val _U_(0x5) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ +#define I2SC_MR_DATALENGTH_8_BITS_Val _U_(0x6) /**< (I2SC_MR) Data length is set to 8 bits */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val _U_(0x7) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ +#define I2SC_MR_DATALENGTH_32_BITS (I2SC_MR_DATALENGTH_32_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 32 bits Position */ +#define I2SC_MR_DATALENGTH_24_BITS (I2SC_MR_DATALENGTH_24_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 24 bits Position */ +#define I2SC_MR_DATALENGTH_20_BITS (I2SC_MR_DATALENGTH_20_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 20 bits Position */ +#define I2SC_MR_DATALENGTH_18_BITS (I2SC_MR_DATALENGTH_18_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 18 bits Position */ +#define I2SC_MR_DATALENGTH_16_BITS (I2SC_MR_DATALENGTH_16_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16 bits Position */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. Position */ +#define I2SC_MR_DATALENGTH_8_BITS (I2SC_MR_DATALENGTH_8_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8 bits Position */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. Position */ +#define I2SC_MR_RXMONO_Pos 8 /**< (I2SC_MR) Receive Mono Position */ +#define I2SC_MR_RXMONO_Msk (_U_(0x1) << I2SC_MR_RXMONO_Pos) /**< (I2SC_MR) Receive Mono Mask */ +#define I2SC_MR_RXMONO I2SC_MR_RXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXMONO_Msk instead */ +#define I2SC_MR_RXDMA_Pos 9 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Position */ +#define I2SC_MR_RXDMA_Msk (_U_(0x1) << I2SC_MR_RXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Mask */ +#define I2SC_MR_RXDMA I2SC_MR_RXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXDMA_Msk instead */ +#define I2SC_MR_RXLOOP_Pos 10 /**< (I2SC_MR) Loopback Test Mode Position */ +#define I2SC_MR_RXLOOP_Msk (_U_(0x1) << I2SC_MR_RXLOOP_Pos) /**< (I2SC_MR) Loopback Test Mode Mask */ +#define I2SC_MR_RXLOOP I2SC_MR_RXLOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_RXLOOP_Msk instead */ +#define I2SC_MR_TXMONO_Pos 12 /**< (I2SC_MR) Transmit Mono Position */ +#define I2SC_MR_TXMONO_Msk (_U_(0x1) << I2SC_MR_TXMONO_Pos) /**< (I2SC_MR) Transmit Mono Mask */ +#define I2SC_MR_TXMONO I2SC_MR_TXMONO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXMONO_Msk instead */ +#define I2SC_MR_TXDMA_Pos 13 /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Position */ +#define I2SC_MR_TXDMA_Msk (_U_(0x1) << I2SC_MR_TXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Mask */ +#define I2SC_MR_TXDMA I2SC_MR_TXDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXDMA_Msk instead */ +#define I2SC_MR_TXSAME_Pos 14 /**< (I2SC_MR) Transmit Data when Underrun Position */ +#define I2SC_MR_TXSAME_Msk (_U_(0x1) << I2SC_MR_TXSAME_Pos) /**< (I2SC_MR) Transmit Data when Underrun Mask */ +#define I2SC_MR_TXSAME I2SC_MR_TXSAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_TXSAME_Msk instead */ +#define I2SC_MR_IMCKDIV_Pos 16 /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Position */ +#define I2SC_MR_IMCKDIV_Msk (_U_(0x3F) << I2SC_MR_IMCKDIV_Pos) /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Mask */ +#define I2SC_MR_IMCKDIV(value) (I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)) +#define I2SC_MR_IMCKFS_Pos 24 /**< (I2SC_MR) Master Clock to fs Ratio Position */ +#define I2SC_MR_IMCKFS_Msk (_U_(0x3F) << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Master Clock to fs Ratio Mask */ +#define I2SC_MR_IMCKFS(value) (I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)) +#define I2SC_MR_IMCKFS_M2SF32_Val _U_(0x0) /**< (I2SC_MR) Sample frequency ratio set to 32 */ +#define I2SC_MR_IMCKFS_M2SF64_Val _U_(0x1) /**< (I2SC_MR) Sample frequency ratio set to 64 */ +#define I2SC_MR_IMCKFS_M2SF96_Val _U_(0x2) /**< (I2SC_MR) Sample frequency ratio set to 96 */ +#define I2SC_MR_IMCKFS_M2SF128_Val _U_(0x3) /**< (I2SC_MR) Sample frequency ratio set to 128 */ +#define I2SC_MR_IMCKFS_M2SF192_Val _U_(0x5) /**< (I2SC_MR) Sample frequency ratio set to 192 */ +#define I2SC_MR_IMCKFS_M2SF256_Val _U_(0x7) /**< (I2SC_MR) Sample frequency ratio set to 256 */ +#define I2SC_MR_IMCKFS_M2SF384_Val _U_(0xB) /**< (I2SC_MR) Sample frequency ratio set to 384 */ +#define I2SC_MR_IMCKFS_M2SF512_Val _U_(0xF) /**< (I2SC_MR) Sample frequency ratio set to 512 */ +#define I2SC_MR_IMCKFS_M2SF768_Val _U_(0x17) /**< (I2SC_MR) Sample frequency ratio set to 768 */ +#define I2SC_MR_IMCKFS_M2SF1024_Val _U_(0x1F) /**< (I2SC_MR) Sample frequency ratio set to 1024 */ +#define I2SC_MR_IMCKFS_M2SF1536_Val _U_(0x2F) /**< (I2SC_MR) Sample frequency ratio set to 1536 */ +#define I2SC_MR_IMCKFS_M2SF2048_Val _U_(0x3F) /**< (I2SC_MR) Sample frequency ratio set to 2048 */ +#define I2SC_MR_IMCKFS_M2SF32 (I2SC_MR_IMCKFS_M2SF32_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 32 Position */ +#define I2SC_MR_IMCKFS_M2SF64 (I2SC_MR_IMCKFS_M2SF64_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 64 Position */ +#define I2SC_MR_IMCKFS_M2SF96 (I2SC_MR_IMCKFS_M2SF96_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 96 Position */ +#define I2SC_MR_IMCKFS_M2SF128 (I2SC_MR_IMCKFS_M2SF128_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 128 Position */ +#define I2SC_MR_IMCKFS_M2SF192 (I2SC_MR_IMCKFS_M2SF192_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 192 Position */ +#define I2SC_MR_IMCKFS_M2SF256 (I2SC_MR_IMCKFS_M2SF256_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 256 Position */ +#define I2SC_MR_IMCKFS_M2SF384 (I2SC_MR_IMCKFS_M2SF384_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 384 Position */ +#define I2SC_MR_IMCKFS_M2SF512 (I2SC_MR_IMCKFS_M2SF512_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 512 Position */ +#define I2SC_MR_IMCKFS_M2SF768 (I2SC_MR_IMCKFS_M2SF768_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 768 Position */ +#define I2SC_MR_IMCKFS_M2SF1024 (I2SC_MR_IMCKFS_M2SF1024_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1024 Position */ +#define I2SC_MR_IMCKFS_M2SF1536 (I2SC_MR_IMCKFS_M2SF1536_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1536 Position */ +#define I2SC_MR_IMCKFS_M2SF2048 (I2SC_MR_IMCKFS_M2SF2048_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 2048 Position */ +#define I2SC_MR_IMCKMODE_Pos 30 /**< (I2SC_MR) Master Clock Mode Position */ +#define I2SC_MR_IMCKMODE_Msk (_U_(0x1) << I2SC_MR_IMCKMODE_Pos) /**< (I2SC_MR) Master Clock Mode Mask */ +#define I2SC_MR_IMCKMODE I2SC_MR_IMCKMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IMCKMODE_Msk instead */ +#define I2SC_MR_IWS_Pos 31 /**< (I2SC_MR) I2SC_WS Slot Width Position */ +#define I2SC_MR_IWS_Msk (_U_(0x1) << I2SC_MR_IWS_Pos) /**< (I2SC_MR) I2SC_WS Slot Width Mask */ +#define I2SC_MR_IWS I2SC_MR_IWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_MR_IWS_Msk instead */ +#define I2SC_MR_MASK _U_(0xFF3F771D) /**< \deprecated (I2SC_MR) Register MASK (Use I2SC_MR_Msk instead) */ +#define I2SC_MR_Msk _U_(0xFF3F771D) /**< (I2SC_MR) Register Mask */ + + +/* -------- I2SC_SR : (I2SC Offset: 0x08) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXEN:1; /**< bit: 0 Receiver Enabled */ + uint32_t RXRDY:1; /**< bit: 1 Receive Ready */ + uint32_t RXOR:1; /**< bit: 2 Receive Overrun */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t TXEN:1; /**< bit: 4 Transmitter Enabled */ + uint32_t TXRDY:1; /**< bit: 5 Transmit Ready */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underrun */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Channel */ + uint32_t :10; /**< bit: 10..19 Reserved */ + uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Channel */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_SR_OFFSET (0x08) /**< (I2SC_SR) Status Register Offset */ + +#define I2SC_SR_RXEN_Pos 0 /**< (I2SC_SR) Receiver Enabled Position */ +#define I2SC_SR_RXEN_Msk (_U_(0x1) << I2SC_SR_RXEN_Pos) /**< (I2SC_SR) Receiver Enabled Mask */ +#define I2SC_SR_RXEN I2SC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXEN_Msk instead */ +#define I2SC_SR_RXRDY_Pos 1 /**< (I2SC_SR) Receive Ready Position */ +#define I2SC_SR_RXRDY_Msk (_U_(0x1) << I2SC_SR_RXRDY_Pos) /**< (I2SC_SR) Receive Ready Mask */ +#define I2SC_SR_RXRDY I2SC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXRDY_Msk instead */ +#define I2SC_SR_RXOR_Pos 2 /**< (I2SC_SR) Receive Overrun Position */ +#define I2SC_SR_RXOR_Msk (_U_(0x1) << I2SC_SR_RXOR_Pos) /**< (I2SC_SR) Receive Overrun Mask */ +#define I2SC_SR_RXOR I2SC_SR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_RXOR_Msk instead */ +#define I2SC_SR_TXEN_Pos 4 /**< (I2SC_SR) Transmitter Enabled Position */ +#define I2SC_SR_TXEN_Msk (_U_(0x1) << I2SC_SR_TXEN_Pos) /**< (I2SC_SR) Transmitter Enabled Mask */ +#define I2SC_SR_TXEN I2SC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXEN_Msk instead */ +#define I2SC_SR_TXRDY_Pos 5 /**< (I2SC_SR) Transmit Ready Position */ +#define I2SC_SR_TXRDY_Msk (_U_(0x1) << I2SC_SR_TXRDY_Pos) /**< (I2SC_SR) Transmit Ready Mask */ +#define I2SC_SR_TXRDY I2SC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXRDY_Msk instead */ +#define I2SC_SR_TXUR_Pos 6 /**< (I2SC_SR) Transmit Underrun Position */ +#define I2SC_SR_TXUR_Msk (_U_(0x1) << I2SC_SR_TXUR_Pos) /**< (I2SC_SR) Transmit Underrun Mask */ +#define I2SC_SR_TXUR I2SC_SR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SR_TXUR_Msk instead */ +#define I2SC_SR_RXORCH_Pos 8 /**< (I2SC_SR) Receive Overrun Channel Position */ +#define I2SC_SR_RXORCH_Msk (_U_(0x3) << I2SC_SR_RXORCH_Pos) /**< (I2SC_SR) Receive Overrun Channel Mask */ +#define I2SC_SR_RXORCH(value) (I2SC_SR_RXORCH_Msk & ((value) << I2SC_SR_RXORCH_Pos)) +#define I2SC_SR_TXURCH_Pos 20 /**< (I2SC_SR) Transmit Underrun Channel Position */ +#define I2SC_SR_TXURCH_Msk (_U_(0x3) << I2SC_SR_TXURCH_Pos) /**< (I2SC_SR) Transmit Underrun Channel Mask */ +#define I2SC_SR_TXURCH(value) (I2SC_SR_TXURCH_Msk & ((value) << I2SC_SR_TXURCH_Pos)) +#define I2SC_SR_MASK _U_(0x300377) /**< \deprecated (I2SC_SR) Register MASK (Use I2SC_SR_Msk instead) */ +#define I2SC_SR_Msk _U_(0x300377) /**< (I2SC_SR) Register Mask */ + + +/* -------- I2SC_SCR : (I2SC Offset: 0x0c) (/W 32) Status Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Clear */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Clear */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Clear */ + uint32_t :10; /**< bit: 10..19 Reserved */ + uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Clear */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_SCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_SCR_OFFSET (0x0C) /**< (I2SC_SCR) Status Clear Register Offset */ + +#define I2SC_SCR_RXOR_Pos 2 /**< (I2SC_SCR) Receive Overrun Status Clear Position */ +#define I2SC_SCR_RXOR_Msk (_U_(0x1) << I2SC_SCR_RXOR_Pos) /**< (I2SC_SCR) Receive Overrun Status Clear Mask */ +#define I2SC_SCR_RXOR I2SC_SCR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_RXOR_Msk instead */ +#define I2SC_SCR_TXUR_Pos 6 /**< (I2SC_SCR) Transmit Underrun Status Clear Position */ +#define I2SC_SCR_TXUR_Msk (_U_(0x1) << I2SC_SCR_TXUR_Pos) /**< (I2SC_SCR) Transmit Underrun Status Clear Mask */ +#define I2SC_SCR_TXUR I2SC_SCR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SCR_TXUR_Msk instead */ +#define I2SC_SCR_RXORCH_Pos 8 /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Position */ +#define I2SC_SCR_RXORCH_Msk (_U_(0x3) << I2SC_SCR_RXORCH_Pos) /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Mask */ +#define I2SC_SCR_RXORCH(value) (I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)) +#define I2SC_SCR_TXURCH_Pos 20 /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Position */ +#define I2SC_SCR_TXURCH_Msk (_U_(0x3) << I2SC_SCR_TXURCH_Pos) /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Mask */ +#define I2SC_SCR_TXURCH(value) (I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)) +#define I2SC_SCR_MASK _U_(0x300344) /**< \deprecated (I2SC_SCR) Register MASK (Use I2SC_SCR_Msk instead) */ +#define I2SC_SCR_Msk _U_(0x300344) /**< (I2SC_SCR) Register Mask */ + + +/* -------- I2SC_SSR : (I2SC Offset: 0x10) (/W 32) Status Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXOR:1; /**< bit: 2 Receive Overrun Status Set */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underrun Status Set */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t RXORCH:2; /**< bit: 8..9 Receive Overrun Per Channel Status Set */ + uint32_t :10; /**< bit: 10..19 Reserved */ + uint32_t TXURCH:2; /**< bit: 20..21 Transmit Underrun Per Channel Status Set */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_SSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_SSR_OFFSET (0x10) /**< (I2SC_SSR) Status Set Register Offset */ + +#define I2SC_SSR_RXOR_Pos 2 /**< (I2SC_SSR) Receive Overrun Status Set Position */ +#define I2SC_SSR_RXOR_Msk (_U_(0x1) << I2SC_SSR_RXOR_Pos) /**< (I2SC_SSR) Receive Overrun Status Set Mask */ +#define I2SC_SSR_RXOR I2SC_SSR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_RXOR_Msk instead */ +#define I2SC_SSR_TXUR_Pos 6 /**< (I2SC_SSR) Transmit Underrun Status Set Position */ +#define I2SC_SSR_TXUR_Msk (_U_(0x1) << I2SC_SSR_TXUR_Pos) /**< (I2SC_SSR) Transmit Underrun Status Set Mask */ +#define I2SC_SSR_TXUR I2SC_SSR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_SSR_TXUR_Msk instead */ +#define I2SC_SSR_RXORCH_Pos 8 /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Position */ +#define I2SC_SSR_RXORCH_Msk (_U_(0x3) << I2SC_SSR_RXORCH_Pos) /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Mask */ +#define I2SC_SSR_RXORCH(value) (I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)) +#define I2SC_SSR_TXURCH_Pos 20 /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Position */ +#define I2SC_SSR_TXURCH_Msk (_U_(0x3) << I2SC_SSR_TXURCH_Pos) /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Mask */ +#define I2SC_SSR_TXURCH(value) (I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)) +#define I2SC_SSR_MASK _U_(0x300344) /**< \deprecated (I2SC_SSR) Register MASK (Use I2SC_SSR_Msk instead) */ +#define I2SC_SSR_Msk _U_(0x300344) /**< (I2SC_SSR) Register Mask */ + + +/* -------- I2SC_IER : (I2SC Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Enable */ + uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Enable */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Enable */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_IER_OFFSET (0x14) /**< (I2SC_IER) Interrupt Enable Register Offset */ + +#define I2SC_IER_RXRDY_Pos 1 /**< (I2SC_IER) Receiver Ready Interrupt Enable Position */ +#define I2SC_IER_RXRDY_Msk (_U_(0x1) << I2SC_IER_RXRDY_Pos) /**< (I2SC_IER) Receiver Ready Interrupt Enable Mask */ +#define I2SC_IER_RXRDY I2SC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXRDY_Msk instead */ +#define I2SC_IER_RXOR_Pos 2 /**< (I2SC_IER) Receiver Overrun Interrupt Enable Position */ +#define I2SC_IER_RXOR_Msk (_U_(0x1) << I2SC_IER_RXOR_Pos) /**< (I2SC_IER) Receiver Overrun Interrupt Enable Mask */ +#define I2SC_IER_RXOR I2SC_IER_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_RXOR_Msk instead */ +#define I2SC_IER_TXRDY_Pos 5 /**< (I2SC_IER) Transmit Ready Interrupt Enable Position */ +#define I2SC_IER_TXRDY_Msk (_U_(0x1) << I2SC_IER_TXRDY_Pos) /**< (I2SC_IER) Transmit Ready Interrupt Enable Mask */ +#define I2SC_IER_TXRDY I2SC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXRDY_Msk instead */ +#define I2SC_IER_TXUR_Pos 6 /**< (I2SC_IER) Transmit Underflow Interrupt Enable Position */ +#define I2SC_IER_TXUR_Msk (_U_(0x1) << I2SC_IER_TXUR_Pos) /**< (I2SC_IER) Transmit Underflow Interrupt Enable Mask */ +#define I2SC_IER_TXUR I2SC_IER_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IER_TXUR_Msk instead */ +#define I2SC_IER_MASK _U_(0x66) /**< \deprecated (I2SC_IER) Register MASK (Use I2SC_IER_Msk instead) */ +#define I2SC_IER_Msk _U_(0x66) /**< (I2SC_IER) Register Mask */ + + +/* -------- I2SC_IDR : (I2SC Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ + uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_IDR_OFFSET (0x18) /**< (I2SC_IDR) Interrupt Disable Register Offset */ + +#define I2SC_IDR_RXRDY_Pos 1 /**< (I2SC_IDR) Receiver Ready Interrupt Disable Position */ +#define I2SC_IDR_RXRDY_Msk (_U_(0x1) << I2SC_IDR_RXRDY_Pos) /**< (I2SC_IDR) Receiver Ready Interrupt Disable Mask */ +#define I2SC_IDR_RXRDY I2SC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXRDY_Msk instead */ +#define I2SC_IDR_RXOR_Pos 2 /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Position */ +#define I2SC_IDR_RXOR_Msk (_U_(0x1) << I2SC_IDR_RXOR_Pos) /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Mask */ +#define I2SC_IDR_RXOR I2SC_IDR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_RXOR_Msk instead */ +#define I2SC_IDR_TXRDY_Pos 5 /**< (I2SC_IDR) Transmit Ready Interrupt Disable Position */ +#define I2SC_IDR_TXRDY_Msk (_U_(0x1) << I2SC_IDR_TXRDY_Pos) /**< (I2SC_IDR) Transmit Ready Interrupt Disable Mask */ +#define I2SC_IDR_TXRDY I2SC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXRDY_Msk instead */ +#define I2SC_IDR_TXUR_Pos 6 /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Position */ +#define I2SC_IDR_TXUR_Msk (_U_(0x1) << I2SC_IDR_TXUR_Pos) /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Mask */ +#define I2SC_IDR_TXUR I2SC_IDR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IDR_TXUR_Msk instead */ +#define I2SC_IDR_MASK _U_(0x66) /**< \deprecated (I2SC_IDR) Register MASK (Use I2SC_IDR_Msk instead) */ +#define I2SC_IDR_Msk _U_(0x66) /**< (I2SC_IDR) Register Mask */ + + +/* -------- I2SC_IMR : (I2SC Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ + uint32_t RXOR:1; /**< bit: 2 Receiver Overrun Interrupt Disable */ + uint32_t :2; /**< bit: 3..4 Reserved */ + uint32_t TXRDY:1; /**< bit: 5 Transmit Ready Interrupt Disable */ + uint32_t TXUR:1; /**< bit: 6 Transmit Underflow Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_IMR_OFFSET (0x1C) /**< (I2SC_IMR) Interrupt Mask Register Offset */ + +#define I2SC_IMR_RXRDY_Pos 1 /**< (I2SC_IMR) Receiver Ready Interrupt Disable Position */ +#define I2SC_IMR_RXRDY_Msk (_U_(0x1) << I2SC_IMR_RXRDY_Pos) /**< (I2SC_IMR) Receiver Ready Interrupt Disable Mask */ +#define I2SC_IMR_RXRDY I2SC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXRDY_Msk instead */ +#define I2SC_IMR_RXOR_Pos 2 /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Position */ +#define I2SC_IMR_RXOR_Msk (_U_(0x1) << I2SC_IMR_RXOR_Pos) /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Mask */ +#define I2SC_IMR_RXOR I2SC_IMR_RXOR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_RXOR_Msk instead */ +#define I2SC_IMR_TXRDY_Pos 5 /**< (I2SC_IMR) Transmit Ready Interrupt Disable Position */ +#define I2SC_IMR_TXRDY_Msk (_U_(0x1) << I2SC_IMR_TXRDY_Pos) /**< (I2SC_IMR) Transmit Ready Interrupt Disable Mask */ +#define I2SC_IMR_TXRDY I2SC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXRDY_Msk instead */ +#define I2SC_IMR_TXUR_Pos 6 /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Position */ +#define I2SC_IMR_TXUR_Msk (_U_(0x1) << I2SC_IMR_TXUR_Pos) /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Mask */ +#define I2SC_IMR_TXUR I2SC_IMR_TXUR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use I2SC_IMR_TXUR_Msk instead */ +#define I2SC_IMR_MASK _U_(0x66) /**< \deprecated (I2SC_IMR) Register MASK (Use I2SC_IMR_Msk instead) */ +#define I2SC_IMR_Msk _U_(0x66) /**< (I2SC_IMR) Register Mask */ + + +/* -------- I2SC_RHR : (I2SC Offset: 0x20) (R/ 32) Receiver Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RHR:32; /**< bit: 0..31 Receiver Holding Register */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_RHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_RHR_OFFSET (0x20) /**< (I2SC_RHR) Receiver Holding Register Offset */ + +#define I2SC_RHR_RHR_Pos 0 /**< (I2SC_RHR) Receiver Holding Register Position */ +#define I2SC_RHR_RHR_Msk (_U_(0xFFFFFFFF) << I2SC_RHR_RHR_Pos) /**< (I2SC_RHR) Receiver Holding Register Mask */ +#define I2SC_RHR_RHR(value) (I2SC_RHR_RHR_Msk & ((value) << I2SC_RHR_RHR_Pos)) +#define I2SC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_RHR) Register MASK (Use I2SC_RHR_Msk instead) */ +#define I2SC_RHR_Msk _U_(0xFFFFFFFF) /**< (I2SC_RHR) Register Mask */ + + +/* -------- I2SC_THR : (I2SC Offset: 0x24) (/W 32) Transmitter Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t THR:32; /**< bit: 0..31 Transmitter Holding Register */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} I2SC_THR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define I2SC_THR_OFFSET (0x24) /**< (I2SC_THR) Transmitter Holding Register Offset */ + +#define I2SC_THR_THR_Pos 0 /**< (I2SC_THR) Transmitter Holding Register Position */ +#define I2SC_THR_THR_Msk (_U_(0xFFFFFFFF) << I2SC_THR_THR_Pos) /**< (I2SC_THR) Transmitter Holding Register Mask */ +#define I2SC_THR_THR(value) (I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)) +#define I2SC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (I2SC_THR) Register MASK (Use I2SC_THR_Msk instead) */ +#define I2SC_THR_Msk _U_(0xFFFFFFFF) /**< (I2SC_THR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief I2SC hardware registers */ +typedef struct { + __O uint32_t I2SC_CR; /**< (I2SC Offset: 0x00) Control Register */ + __IO uint32_t I2SC_MR; /**< (I2SC Offset: 0x04) Mode Register */ + __I uint32_t I2SC_SR; /**< (I2SC Offset: 0x08) Status Register */ + __O uint32_t I2SC_SCR; /**< (I2SC Offset: 0x0C) Status Clear Register */ + __O uint32_t I2SC_SSR; /**< (I2SC Offset: 0x10) Status Set Register */ + __O uint32_t I2SC_IER; /**< (I2SC Offset: 0x14) Interrupt Enable Register */ + __O uint32_t I2SC_IDR; /**< (I2SC Offset: 0x18) Interrupt Disable Register */ + __I uint32_t I2SC_IMR; /**< (I2SC Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t I2SC_RHR; /**< (I2SC Offset: 0x20) Receiver Holding Register */ + __O uint32_t I2SC_THR; /**< (I2SC Offset: 0x24) Transmitter Holding Register */ +} I2sc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief I2SC hardware registers */ +typedef struct { + __O I2SC_CR_Type I2SC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO I2SC_MR_Type I2SC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I I2SC_SR_Type I2SC_SR; /**< Offset: 0x08 (R/ 32) Status Register */ + __O I2SC_SCR_Type I2SC_SCR; /**< Offset: 0x0C ( /W 32) Status Clear Register */ + __O I2SC_SSR_Type I2SC_SSR; /**< Offset: 0x10 ( /W 32) Status Set Register */ + __O I2SC_IER_Type I2SC_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O I2SC_IDR_Type I2SC_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I I2SC_IMR_Type I2SC_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __I I2SC_RHR_Type I2SC_RHR; /**< Offset: 0x20 (R/ 32) Receiver Holding Register */ + __O I2SC_THR_Type I2SC_THR; /**< Offset: 0x24 ( /W 32) Transmitter Holding Register */ +} I2sc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Inter-IC Sound Controller */ + +#endif /* _SAME70_I2SC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/icm.h b/bsp/microchip/same70/bsp/same70b/include/component/icm.h new file mode 100644 index 0000000000..d62785e6f6 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/icm.h @@ -0,0 +1,505 @@ +/** + * \file + * + * \brief Component description for ICM + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ICM_COMPONENT_H_ +#define _SAME70_ICM_COMPONENT_H_ +#define _SAME70_ICM_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Integrity Check Monitor + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ICM */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define ICM_11105 /**< (ICM) Module ID */ +#define REV_ICM H /**< (ICM) Module revision */ + +/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WBDIS:1; /**< bit: 0 Write Back Disable */ + uint32_t EOMDIS:1; /**< bit: 1 End of Monitoring Disable */ + uint32_t SLBDIS:1; /**< bit: 2 Secondary List Branching Disable */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t BBC:4; /**< bit: 4..7 Bus Burden Control */ + uint32_t ASCD:1; /**< bit: 8 Automatic Switch To Compare Digest */ + uint32_t DUALBUFF:1; /**< bit: 9 Dual Input Buffer */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t UIHASH:1; /**< bit: 12 User Initial Hash Value */ + uint32_t UALGO:3; /**< bit: 13..15 User SHA Algorithm */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_CFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_CFG_OFFSET (0x00) /**< (ICM_CFG) Configuration Register Offset */ + +#define ICM_CFG_WBDIS_Pos 0 /**< (ICM_CFG) Write Back Disable Position */ +#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */ +#define ICM_CFG_WBDIS ICM_CFG_WBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_WBDIS_Msk instead */ +#define ICM_CFG_EOMDIS_Pos 1 /**< (ICM_CFG) End of Monitoring Disable Position */ +#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */ +#define ICM_CFG_EOMDIS ICM_CFG_EOMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_EOMDIS_Msk instead */ +#define ICM_CFG_SLBDIS_Pos 2 /**< (ICM_CFG) Secondary List Branching Disable Position */ +#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */ +#define ICM_CFG_SLBDIS ICM_CFG_SLBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_SLBDIS_Msk instead */ +#define ICM_CFG_BBC_Pos 4 /**< (ICM_CFG) Bus Burden Control Position */ +#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */ +#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) +#define ICM_CFG_ASCD_Pos 8 /**< (ICM_CFG) Automatic Switch To Compare Digest Position */ +#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */ +#define ICM_CFG_ASCD ICM_CFG_ASCD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_ASCD_Msk instead */ +#define ICM_CFG_DUALBUFF_Pos 9 /**< (ICM_CFG) Dual Input Buffer Position */ +#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */ +#define ICM_CFG_DUALBUFF ICM_CFG_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_DUALBUFF_Msk instead */ +#define ICM_CFG_UIHASH_Pos 12 /**< (ICM_CFG) User Initial Hash Value Position */ +#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */ +#define ICM_CFG_UIHASH ICM_CFG_UIHASH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_UIHASH_Msk instead */ +#define ICM_CFG_UALGO_Pos 13 /**< (ICM_CFG) User SHA Algorithm Position */ +#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */ +#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) +#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */ +#define ICM_CFG_MASK _U_(0xF3F7) /**< \deprecated (ICM_CFG) Register MASK (Use ICM_CFG_Msk instead) */ +#define ICM_CFG_Msk _U_(0xF3F7) /**< (ICM_CFG) Register Mask */ + + +/* -------- ICM_CTRL : (ICM Offset: 0x04) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ENABLE:1; /**< bit: 0 ICM Enable */ + uint32_t DISABLE:1; /**< bit: 1 ICM Disable Register */ + uint32_t SWRST:1; /**< bit: 2 Software Reset */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t REHASH:4; /**< bit: 4..7 Recompute Internal Hash */ + uint32_t RMDIS:4; /**< bit: 8..11 Region Monitoring Disable */ + uint32_t RMEN:4; /**< bit: 12..15 Region Monitoring Enable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_CTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_CTRL_OFFSET (0x04) /**< (ICM_CTRL) Control Register Offset */ + +#define ICM_CTRL_ENABLE_Pos 0 /**< (ICM_CTRL) ICM Enable Position */ +#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */ +#define ICM_CTRL_ENABLE ICM_CTRL_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_ENABLE_Msk instead */ +#define ICM_CTRL_DISABLE_Pos 1 /**< (ICM_CTRL) ICM Disable Register Position */ +#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */ +#define ICM_CTRL_DISABLE ICM_CTRL_DISABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_DISABLE_Msk instead */ +#define ICM_CTRL_SWRST_Pos 2 /**< (ICM_CTRL) Software Reset Position */ +#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */ +#define ICM_CTRL_SWRST ICM_CTRL_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_SWRST_Msk instead */ +#define ICM_CTRL_REHASH_Pos 4 /**< (ICM_CTRL) Recompute Internal Hash Position */ +#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */ +#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)) +#define ICM_CTRL_RMDIS_Pos 8 /**< (ICM_CTRL) Region Monitoring Disable Position */ +#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */ +#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)) +#define ICM_CTRL_RMEN_Pos 12 /**< (ICM_CTRL) Region Monitoring Enable Position */ +#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */ +#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)) +#define ICM_CTRL_MASK _U_(0xFFF7) /**< \deprecated (ICM_CTRL) Register MASK (Use ICM_CTRL_Msk instead) */ +#define ICM_CTRL_Msk _U_(0xFFF7) /**< (ICM_CTRL) Register Mask */ + + +/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ENABLE:1; /**< bit: 0 ICM Controller Enable Register */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t RAWRMDIS:4; /**< bit: 8..11 Region Monitoring Disabled Raw Status */ + uint32_t RMDIS:4; /**< bit: 12..15 Region Monitoring Disabled Status */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_SR_OFFSET (0x08) /**< (ICM_SR) Status Register Offset */ + +#define ICM_SR_ENABLE_Pos 0 /**< (ICM_SR) ICM Controller Enable Register Position */ +#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */ +#define ICM_SR_ENABLE ICM_SR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_SR_ENABLE_Msk instead */ +#define ICM_SR_RAWRMDIS_Pos 8 /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */ +#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */ +#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)) +#define ICM_SR_RMDIS_Pos 12 /**< (ICM_SR) Region Monitoring Disabled Status Position */ +#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */ +#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)) +#define ICM_SR_MASK _U_(0xFF01) /**< \deprecated (ICM_SR) Register MASK (Use ICM_SR_Msk instead) */ +#define ICM_SR_Msk _U_(0xFF01) /**< (ICM_SR) Register Mask */ + + +/* -------- ICM_IER : (ICM Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Enable */ + uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Enable */ + uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Enable */ + uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition detected Interrupt Enable */ + uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Enable */ + uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */ + uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Enable */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_IER_OFFSET (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */ + +#define ICM_IER_RHC_Pos 0 /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */ +#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */ +#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) +#define ICM_IER_RDM_Pos 4 /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */ +#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */ +#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) +#define ICM_IER_RBE_Pos 8 /**< (ICM_IER) Region Bus Error Interrupt Enable Position */ +#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */ +#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) +#define ICM_IER_RWC_Pos 12 /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */ +#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */ +#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) +#define ICM_IER_REC_Pos 16 /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */ +#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */ +#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) +#define ICM_IER_RSU_Pos 20 /**< (ICM_IER) Region Status Updated Interrupt Disable Position */ +#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */ +#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) +#define ICM_IER_URAD_Pos 24 /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */ +#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */ +#define ICM_IER_URAD ICM_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IER_URAD_Msk instead */ +#define ICM_IER_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IER) Register MASK (Use ICM_IER_Msk instead) */ +#define ICM_IER_Msk _U_(0x1FFFFFF) /**< (ICM_IER) Register Mask */ + + +/* -------- ICM_IDR : (ICM Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Disable */ + uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Disable */ + uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Disable */ + uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */ + uint32_t REC:4; /**< bit: 16..19 Region End bit Condition detected Interrupt Disable */ + uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */ + uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Disable */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_IDR_OFFSET (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */ + +#define ICM_IDR_RHC_Pos 0 /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */ +#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */ +#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) +#define ICM_IDR_RDM_Pos 4 /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */ +#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */ +#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) +#define ICM_IDR_RBE_Pos 8 /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */ +#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */ +#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) +#define ICM_IDR_RWC_Pos 12 /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */ +#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */ +#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)) +#define ICM_IDR_REC_Pos 16 /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */ +#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */ +#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)) +#define ICM_IDR_RSU_Pos 20 /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */ +#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */ +#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)) +#define ICM_IDR_URAD_Pos 24 /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */ +#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */ +#define ICM_IDR_URAD ICM_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IDR_URAD_Msk instead */ +#define ICM_IDR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IDR) Register MASK (Use ICM_IDR_Msk instead) */ +#define ICM_IDR_Msk _U_(0x1FFFFFF) /**< (ICM_IDR) Register Mask */ + + +/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Mask */ + uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Mask */ + uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Mask */ + uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */ + uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Mask */ + uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Mask */ + uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Mask */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_IMR_OFFSET (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */ + +#define ICM_IMR_RHC_Pos 0 /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */ +#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */ +#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos)) +#define ICM_IMR_RDM_Pos 4 /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */ +#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */ +#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos)) +#define ICM_IMR_RBE_Pos 8 /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */ +#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */ +#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos)) +#define ICM_IMR_RWC_Pos 12 /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */ +#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos)) +#define ICM_IMR_REC_Pos 16 /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */ +#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos)) +#define ICM_IMR_RSU_Pos 20 /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */ +#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */ +#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos)) +#define ICM_IMR_URAD_Pos 24 /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */ +#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */ +#define ICM_IMR_URAD ICM_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IMR_URAD_Msk instead */ +#define ICM_IMR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IMR) Register MASK (Use ICM_IMR_Msk instead) */ +#define ICM_IMR_Msk _U_(0x1FFFFFF) /**< (ICM_IMR) Register Mask */ + + +/* -------- ICM_ISR : (ICM Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed */ + uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch */ + uint32_t RBE:4; /**< bit: 8..11 Region Bus Error */ + uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected */ + uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected */ + uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Detected */ + uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Status */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_ISR_OFFSET (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */ + +#define ICM_ISR_RHC_Pos 0 /**< (ICM_ISR) Region Hash Completed Position */ +#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */ +#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos)) +#define ICM_ISR_RDM_Pos 4 /**< (ICM_ISR) Region Digest Mismatch Position */ +#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */ +#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos)) +#define ICM_ISR_RBE_Pos 8 /**< (ICM_ISR) Region Bus Error Position */ +#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */ +#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos)) +#define ICM_ISR_RWC_Pos 12 /**< (ICM_ISR) Region Wrap Condition Detected Position */ +#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */ +#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos)) +#define ICM_ISR_REC_Pos 16 /**< (ICM_ISR) Region End bit Condition Detected Position */ +#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */ +#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos)) +#define ICM_ISR_RSU_Pos 20 /**< (ICM_ISR) Region Status Updated Detected Position */ +#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */ +#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos)) +#define ICM_ISR_URAD_Pos 24 /**< (ICM_ISR) Undefined Register Access Detection Status Position */ +#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */ +#define ICM_ISR_URAD ICM_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_ISR_URAD_Msk instead */ +#define ICM_ISR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_ISR) Register MASK (Use ICM_ISR_Msk instead) */ +#define ICM_ISR_Msk _U_(0x1FFFFFF) /**< (ICM_ISR) Register Mask */ + + +/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t URAT:3; /**< bit: 0..2 Undefined Register Access Trace */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_UASR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_UASR_OFFSET (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */ + +#define ICM_UASR_URAT_Pos 0 /**< (ICM_UASR) Undefined Register Access Trace Position */ +#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */ +#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos)) +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */ +#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */ +#define ICM_UASR_MASK _U_(0x07) /**< \deprecated (ICM_UASR) Register MASK (Use ICM_UASR_Msk instead) */ +#define ICM_UASR_Msk _U_(0x07) /**< (ICM_UASR) Register Mask */ + + +/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t DASA:26; /**< bit: 6..31 Descriptor Area Start Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_DSCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_DSCR_OFFSET (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */ + +#define ICM_DSCR_DASA_Pos 6 /**< (ICM_DSCR) Descriptor Area Start Address Position */ +#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */ +#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)) +#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \deprecated (ICM_DSCR) Register MASK (Use ICM_DSCR_Msk instead) */ +#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */ + + +/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t HASA:25; /**< bit: 7..31 Hash Area Start Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_HASH_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_HASH_OFFSET (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */ + +#define ICM_HASH_HASA_Pos 7 /**< (ICM_HASH) Hash Area Start Address Position */ +#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */ +#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)) +#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \deprecated (ICM_HASH) Register MASK (Use ICM_HASH_Msk instead) */ +#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */ + + +/* -------- ICM_UIHVAL : (ICM Offset: 0x38) (/W 32) User Initial Hash Value 0 Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t VAL:32; /**< bit: 0..31 Initial Hash Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ICM_UIHVAL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ICM_UIHVAL_OFFSET (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */ + +#define ICM_UIHVAL_VAL_Pos 0 /**< (ICM_UIHVAL) Initial Hash Value Position */ +#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */ +#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)) +#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \deprecated (ICM_UIHVAL) Register MASK (Use ICM_UIHVAL_Msk instead) */ +#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief ICM hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< (ICM Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< (ICM Offset: 0x04) Control Register */ + __I uint32_t ICM_SR; /**< (ICM Offset: 0x08) Status Register */ + __I uint8_t Reserved1[4]; + __O uint32_t ICM_IER; /**< (ICM Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< (ICM Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< (ICM Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< (ICM Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< (ICM Offset: 0x20) Undefined Access Status Register */ + __I uint8_t Reserved2[12]; + __IO uint32_t ICM_DSCR; /**< (ICM Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< (ICM Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< (ICM Offset: 0x38) User Initial Hash Value 0 Register 0 */ +} Icm; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief ICM hardware registers */ +typedef struct { + __IO ICM_CFG_Type ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */ + __O ICM_CTRL_Type ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */ + __I ICM_SR_Type ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */ + __I uint8_t Reserved1[4]; + __O ICM_IER_Type ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O ICM_IDR_Type ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I ICM_IMR_Type ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I ICM_ISR_Type ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I ICM_UASR_Type ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */ + __I uint8_t Reserved2[12]; + __IO ICM_DSCR_Type ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */ + __IO ICM_HASH_Type ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */ + __O ICM_UIHVAL_Type ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */ +} Icm; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Integrity Check Monitor */ + +#endif /* _SAME70_ICM_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/isi.h b/bsp/microchip/same70/bsp/same70b/include/component/isi.h new file mode 100644 index 0000000000..a04979588a --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/isi.h @@ -0,0 +1,1057 @@ +/** + * \file + * + * \brief Component description for ISI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ISI_COMPONENT_H_ +#define _SAME70_ISI_COMPONENT_H_ +#define _SAME70_ISI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Image Sensor Interface + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ISI */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define ISI_6350 /**< (ISI) Module ID */ +#define REV_ISI K /**< (ISI) Module revision */ + +/* -------- ISI_CFG1 : (ISI Offset: 0x00) (R/W 32) ISI Configuration 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t HSYNC_POL:1; /**< bit: 2 Horizontal Synchronization Polarity */ + uint32_t VSYNC_POL:1; /**< bit: 3 Vertical Synchronization Polarity */ + uint32_t PIXCLK_POL:1; /**< bit: 4 Pixel Clock Polarity */ + uint32_t GRAYLE:1; /**< bit: 5 Grayscale Little Endian */ + uint32_t EMB_SYNC:1; /**< bit: 6 Embedded Synchronization */ + uint32_t CRC_SYNC:1; /**< bit: 7 Embedded Synchronization Correction */ + uint32_t FRATE:3; /**< bit: 8..10 Frame Rate [0..7] */ + uint32_t DISCR:1; /**< bit: 11 Disable Codec Request */ + uint32_t FULL:1; /**< bit: 12 Full Mode is Allowed */ + uint32_t THMASK:2; /**< bit: 13..14 Threshold Mask */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t SLD:8; /**< bit: 16..23 Start of Line Delay */ + uint32_t SFD:8; /**< bit: 24..31 Start of Frame Delay */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_CFG1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_CFG1_OFFSET (0x00) /**< (ISI_CFG1) ISI Configuration 1 Register Offset */ + +#define ISI_CFG1_HSYNC_POL_Pos 2 /**< (ISI_CFG1) Horizontal Synchronization Polarity Position */ +#define ISI_CFG1_HSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_HSYNC_POL_Pos) /**< (ISI_CFG1) Horizontal Synchronization Polarity Mask */ +#define ISI_CFG1_HSYNC_POL ISI_CFG1_HSYNC_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_HSYNC_POL_Msk instead */ +#define ISI_CFG1_VSYNC_POL_Pos 3 /**< (ISI_CFG1) Vertical Synchronization Polarity Position */ +#define ISI_CFG1_VSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_VSYNC_POL_Pos) /**< (ISI_CFG1) Vertical Synchronization Polarity Mask */ +#define ISI_CFG1_VSYNC_POL ISI_CFG1_VSYNC_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_VSYNC_POL_Msk instead */ +#define ISI_CFG1_PIXCLK_POL_Pos 4 /**< (ISI_CFG1) Pixel Clock Polarity Position */ +#define ISI_CFG1_PIXCLK_POL_Msk (_U_(0x1) << ISI_CFG1_PIXCLK_POL_Pos) /**< (ISI_CFG1) Pixel Clock Polarity Mask */ +#define ISI_CFG1_PIXCLK_POL ISI_CFG1_PIXCLK_POL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_PIXCLK_POL_Msk instead */ +#define ISI_CFG1_GRAYLE_Pos 5 /**< (ISI_CFG1) Grayscale Little Endian Position */ +#define ISI_CFG1_GRAYLE_Msk (_U_(0x1) << ISI_CFG1_GRAYLE_Pos) /**< (ISI_CFG1) Grayscale Little Endian Mask */ +#define ISI_CFG1_GRAYLE ISI_CFG1_GRAYLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_GRAYLE_Msk instead */ +#define ISI_CFG1_EMB_SYNC_Pos 6 /**< (ISI_CFG1) Embedded Synchronization Position */ +#define ISI_CFG1_EMB_SYNC_Msk (_U_(0x1) << ISI_CFG1_EMB_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Mask */ +#define ISI_CFG1_EMB_SYNC ISI_CFG1_EMB_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_EMB_SYNC_Msk instead */ +#define ISI_CFG1_CRC_SYNC_Pos 7 /**< (ISI_CFG1) Embedded Synchronization Correction Position */ +#define ISI_CFG1_CRC_SYNC_Msk (_U_(0x1) << ISI_CFG1_CRC_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Correction Mask */ +#define ISI_CFG1_CRC_SYNC ISI_CFG1_CRC_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_CRC_SYNC_Msk instead */ +#define ISI_CFG1_FRATE_Pos 8 /**< (ISI_CFG1) Frame Rate [0..7] Position */ +#define ISI_CFG1_FRATE_Msk (_U_(0x7) << ISI_CFG1_FRATE_Pos) /**< (ISI_CFG1) Frame Rate [0..7] Mask */ +#define ISI_CFG1_FRATE(value) (ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)) +#define ISI_CFG1_DISCR_Pos 11 /**< (ISI_CFG1) Disable Codec Request Position */ +#define ISI_CFG1_DISCR_Msk (_U_(0x1) << ISI_CFG1_DISCR_Pos) /**< (ISI_CFG1) Disable Codec Request Mask */ +#define ISI_CFG1_DISCR ISI_CFG1_DISCR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_DISCR_Msk instead */ +#define ISI_CFG1_FULL_Pos 12 /**< (ISI_CFG1) Full Mode is Allowed Position */ +#define ISI_CFG1_FULL_Msk (_U_(0x1) << ISI_CFG1_FULL_Pos) /**< (ISI_CFG1) Full Mode is Allowed Mask */ +#define ISI_CFG1_FULL ISI_CFG1_FULL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG1_FULL_Msk instead */ +#define ISI_CFG1_THMASK_Pos 13 /**< (ISI_CFG1) Threshold Mask Position */ +#define ISI_CFG1_THMASK_Msk (_U_(0x3) << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Threshold Mask Mask */ +#define ISI_CFG1_THMASK(value) (ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)) +#define ISI_CFG1_THMASK_BEATS_4_Val _U_(0x0) /**< (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8_Val _U_(0x1) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16_Val _U_(0x2) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_4 (ISI_CFG1_THMASK_BEATS_4_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_8 (ISI_CFG1_THMASK_BEATS_8_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_16 (ISI_CFG1_THMASK_BEATS_16_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed Position */ +#define ISI_CFG1_SLD_Pos 16 /**< (ISI_CFG1) Start of Line Delay Position */ +#define ISI_CFG1_SLD_Msk (_U_(0xFF) << ISI_CFG1_SLD_Pos) /**< (ISI_CFG1) Start of Line Delay Mask */ +#define ISI_CFG1_SLD(value) (ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)) +#define ISI_CFG1_SFD_Pos 24 /**< (ISI_CFG1) Start of Frame Delay Position */ +#define ISI_CFG1_SFD_Msk (_U_(0xFF) << ISI_CFG1_SFD_Pos) /**< (ISI_CFG1) Start of Frame Delay Mask */ +#define ISI_CFG1_SFD(value) (ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)) +#define ISI_CFG1_Msk _U_(0xFFFF7FFC) /**< (ISI_CFG1) Register Mask */ + + +/* -------- ISI_CFG2 : (ISI Offset: 0x04) (R/W 32) ISI Configuration 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IM_VSIZE:11; /**< bit: 0..10 Vertical Size of the Image Sensor [0..2047] */ + uint32_t GS_MODE:1; /**< bit: 11 Grayscale Pixel Format Mode */ + uint32_t RGB_MODE:1; /**< bit: 12 RGB Input Mode */ + uint32_t GRAYSCALE:1; /**< bit: 13 Grayscale Mode Format Enable */ + uint32_t RGB_SWAP:1; /**< bit: 14 RGB Format Swap Mode */ + uint32_t COL_SPACE:1; /**< bit: 15 Color Space for the Image Data */ + uint32_t IM_HSIZE:11; /**< bit: 16..26 Horizontal Size of the Image Sensor [0..2047] */ + uint32_t :1; /**< bit: 27 Reserved */ + uint32_t YCC_SWAP:2; /**< bit: 28..29 YCrCb Format Swap Mode */ + uint32_t RGB_CFG:2; /**< bit: 30..31 RGB Pixel Mapping Configuration */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_CFG2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_CFG2_OFFSET (0x04) /**< (ISI_CFG2) ISI Configuration 2 Register Offset */ + +#define ISI_CFG2_IM_VSIZE_Pos 0 /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_VSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_VSIZE_Pos) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_VSIZE(value) (ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)) +#define ISI_CFG2_GS_MODE_Pos 11 /**< (ISI_CFG2) Grayscale Pixel Format Mode Position */ +#define ISI_CFG2_GS_MODE_Msk (_U_(0x1) << ISI_CFG2_GS_MODE_Pos) /**< (ISI_CFG2) Grayscale Pixel Format Mode Mask */ +#define ISI_CFG2_GS_MODE ISI_CFG2_GS_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_GS_MODE_Msk instead */ +#define ISI_CFG2_RGB_MODE_Pos 12 /**< (ISI_CFG2) RGB Input Mode Position */ +#define ISI_CFG2_RGB_MODE_Msk (_U_(0x1) << ISI_CFG2_RGB_MODE_Pos) /**< (ISI_CFG2) RGB Input Mode Mask */ +#define ISI_CFG2_RGB_MODE ISI_CFG2_RGB_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_RGB_MODE_Msk instead */ +#define ISI_CFG2_GRAYSCALE_Pos 13 /**< (ISI_CFG2) Grayscale Mode Format Enable Position */ +#define ISI_CFG2_GRAYSCALE_Msk (_U_(0x1) << ISI_CFG2_GRAYSCALE_Pos) /**< (ISI_CFG2) Grayscale Mode Format Enable Mask */ +#define ISI_CFG2_GRAYSCALE ISI_CFG2_GRAYSCALE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_GRAYSCALE_Msk instead */ +#define ISI_CFG2_RGB_SWAP_Pos 14 /**< (ISI_CFG2) RGB Format Swap Mode Position */ +#define ISI_CFG2_RGB_SWAP_Msk (_U_(0x1) << ISI_CFG2_RGB_SWAP_Pos) /**< (ISI_CFG2) RGB Format Swap Mode Mask */ +#define ISI_CFG2_RGB_SWAP ISI_CFG2_RGB_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_RGB_SWAP_Msk instead */ +#define ISI_CFG2_COL_SPACE_Pos 15 /**< (ISI_CFG2) Color Space for the Image Data Position */ +#define ISI_CFG2_COL_SPACE_Msk (_U_(0x1) << ISI_CFG2_COL_SPACE_Pos) /**< (ISI_CFG2) Color Space for the Image Data Mask */ +#define ISI_CFG2_COL_SPACE ISI_CFG2_COL_SPACE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CFG2_COL_SPACE_Msk instead */ +#define ISI_CFG2_IM_HSIZE_Pos 16 /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_HSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_HSIZE_Pos) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_HSIZE(value) (ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)) +#define ISI_CFG2_YCC_SWAP_Pos 28 /**< (ISI_CFG2) YCrCb Format Swap Mode Position */ +#define ISI_CFG2_YCC_SWAP_Msk (_U_(0x3) << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) YCrCb Format Swap Mode Mask */ +#define ISI_CFG2_YCC_SWAP(value) (ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)) +#define ISI_CFG2_YCC_SWAP_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_YCC_SWAP_DEFAULT (ISI_CFG2_YCC_SWAP_DEFAULT_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE1 (ISI_CFG2_YCC_SWAP_MODE1_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE2 (ISI_CFG2_YCC_SWAP_MODE2_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) Position */ +#define ISI_CFG2_YCC_SWAP_MODE3 (ISI_CFG2_YCC_SWAP_MODE3_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) Position */ +#define ISI_CFG2_RGB_CFG_Pos 30 /**< (ISI_CFG2) RGB Pixel Mapping Configuration Position */ +#define ISI_CFG2_RGB_CFG_Msk (_U_(0x3) << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Mask */ +#define ISI_CFG2_RGB_CFG(value) (ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)) +#define ISI_CFG2_RGB_CFG_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +#define ISI_CFG2_RGB_CFG_DEFAULT (ISI_CFG2_RGB_CFG_DEFAULT_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B Position */ +#define ISI_CFG2_RGB_CFG_MODE1 (ISI_CFG2_RGB_CFG_MODE1_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R Position */ +#define ISI_CFG2_RGB_CFG_MODE2 (ISI_CFG2_RGB_CFG_MODE2_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) Position */ +#define ISI_CFG2_RGB_CFG_MODE3 (ISI_CFG2_RGB_CFG_MODE3_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) Position */ +#define ISI_CFG2_MASK _U_(0xF7FFFFFF) /**< \deprecated (ISI_CFG2) Register MASK (Use ISI_CFG2_Msk instead) */ +#define ISI_CFG2_Msk _U_(0xF7FFFFFF) /**< (ISI_CFG2) Register Mask */ + + +/* -------- ISI_PSIZE : (ISI Offset: 0x08) (R/W 32) ISI Preview Size Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PREV_VSIZE:10; /**< bit: 0..9 Vertical Size for the Preview Path */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t PREV_HSIZE:10; /**< bit: 16..25 Horizontal Size for the Preview Path */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_PSIZE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_PSIZE_OFFSET (0x08) /**< (ISI_PSIZE) ISI Preview Size Register Offset */ + +#define ISI_PSIZE_PREV_VSIZE_Pos 0 /**< (ISI_PSIZE) Vertical Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_VSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_VSIZE_Pos) /**< (ISI_PSIZE) Vertical Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_VSIZE(value) (ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 /**< (ISI_PSIZE) Horizontal Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_HSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_HSIZE_Pos) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_HSIZE(value) (ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)) +#define ISI_PSIZE_MASK _U_(0x3FF03FF) /**< \deprecated (ISI_PSIZE) Register MASK (Use ISI_PSIZE_Msk instead) */ +#define ISI_PSIZE_Msk _U_(0x3FF03FF) /**< (ISI_PSIZE) Register Mask */ + + +/* -------- ISI_PDECF : (ISI Offset: 0x0c) (R/W 32) ISI Preview Decimation Factor Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DEC_FACTOR:8; /**< bit: 0..7 Decimation Factor */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_PDECF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_PDECF_OFFSET (0x0C) /**< (ISI_PDECF) ISI Preview Decimation Factor Register Offset */ + +#define ISI_PDECF_DEC_FACTOR_Pos 0 /**< (ISI_PDECF) Decimation Factor Position */ +#define ISI_PDECF_DEC_FACTOR_Msk (_U_(0xFF) << ISI_PDECF_DEC_FACTOR_Pos) /**< (ISI_PDECF) Decimation Factor Mask */ +#define ISI_PDECF_DEC_FACTOR(value) (ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)) +#define ISI_PDECF_MASK _U_(0xFF) /**< \deprecated (ISI_PDECF) Register MASK (Use ISI_PDECF_Msk instead) */ +#define ISI_PDECF_Msk _U_(0xFF) /**< (ISI_PDECF) Register Mask */ + + +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C0:8; /**< bit: 0..7 Color Space Conversion Matrix Coefficient C0 */ + uint32_t C1:8; /**< bit: 8..15 Color Space Conversion Matrix Coefficient C1 */ + uint32_t C2:8; /**< bit: 16..23 Color Space Conversion Matrix Coefficient C2 */ + uint32_t C3:8; /**< bit: 24..31 Color Space Conversion Matrix Coefficient C3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_Y2R_SET0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_Y2R_SET0_OFFSET (0x10) /**< (ISI_Y2R_SET0) ISI Color Space Conversion YCrCb To RGB Set 0 Register Offset */ + +#define ISI_Y2R_SET0_C0_Pos 0 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_Y2R_SET0_C0_Msk (_U_(0xFF) << ISI_Y2R_SET0_C0_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_Y2R_SET0_C0(value) (ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)) +#define ISI_Y2R_SET0_C1_Pos 8 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_Y2R_SET0_C1_Msk (_U_(0xFF) << ISI_Y2R_SET0_C1_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_Y2R_SET0_C1(value) (ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)) +#define ISI_Y2R_SET0_C2_Pos 16 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_Y2R_SET0_C2_Msk (_U_(0xFF) << ISI_Y2R_SET0_C2_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_Y2R_SET0_C2(value) (ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)) +#define ISI_Y2R_SET0_C3_Pos 24 /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_Y2R_SET0_C3_Msk (_U_(0xFF) << ISI_Y2R_SET0_C3_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_Y2R_SET0_C3(value) (ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)) +#define ISI_Y2R_SET0_MASK _U_(0xFFFFFFFF) /**< \deprecated (ISI_Y2R_SET0) Register MASK (Use ISI_Y2R_SET0_Msk instead) */ +#define ISI_Y2R_SET0_Msk _U_(0xFFFFFFFF) /**< (ISI_Y2R_SET0) Register Mask */ + + +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C4:9; /**< bit: 0..8 Color Space Conversion Matrix Coefficient C4 */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t Yoff:1; /**< bit: 12 Color Space Conversion Luminance Default Offset */ + uint32_t Croff:1; /**< bit: 13 Color Space Conversion Red Chrominance Default Offset */ + uint32_t Cboff:1; /**< bit: 14 Color Space Conversion Blue Chrominance Default Offset */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_Y2R_SET1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_Y2R_SET1_OFFSET (0x14) /**< (ISI_Y2R_SET1) ISI Color Space Conversion YCrCb To RGB Set 1 Register Offset */ + +#define ISI_Y2R_SET1_C4_Pos 0 /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_Y2R_SET1_C4_Msk (_U_(0x1FF) << ISI_Y2R_SET1_C4_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_Y2R_SET1_C4(value) (ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)) +#define ISI_Y2R_SET1_Yoff_Pos 12 /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Position */ +#define ISI_Y2R_SET1_Yoff_Msk (_U_(0x1) << ISI_Y2R_SET1_Yoff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Mask */ +#define ISI_Y2R_SET1_Yoff ISI_Y2R_SET1_Yoff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Yoff_Msk instead */ +#define ISI_Y2R_SET1_Croff_Pos 13 /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Croff_Msk (_U_(0x1) << ISI_Y2R_SET1_Croff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Croff ISI_Y2R_SET1_Croff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Croff_Msk instead */ +#define ISI_Y2R_SET1_Cboff_Pos 14 /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Cboff_Msk (_U_(0x1) << ISI_Y2R_SET1_Cboff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Cboff ISI_Y2R_SET1_Cboff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_Y2R_SET1_Cboff_Msk instead */ +#define ISI_Y2R_SET1_MASK _U_(0x71FF) /**< \deprecated (ISI_Y2R_SET1) Register MASK (Use ISI_Y2R_SET1_Msk instead) */ +#define ISI_Y2R_SET1_Msk _U_(0x71FF) /**< (ISI_Y2R_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C0:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C0 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t C1:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C1 */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t C2:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C2 */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t Roff:1; /**< bit: 24 Color Space Conversion Red Component Offset */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_R2Y_SET0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_R2Y_SET0_OFFSET (0x18) /**< (ISI_R2Y_SET0) ISI Color Space Conversion RGB To YCrCb Set 0 Register Offset */ + +#define ISI_R2Y_SET0_C0_Pos 0 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_R2Y_SET0_C0_Msk (_U_(0x7F) << ISI_R2Y_SET0_C0_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_R2Y_SET0_C0(value) (ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)) +#define ISI_R2Y_SET0_C1_Pos 8 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_R2Y_SET0_C1_Msk (_U_(0x7F) << ISI_R2Y_SET0_C1_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_R2Y_SET0_C1(value) (ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)) +#define ISI_R2Y_SET0_C2_Pos 16 /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_R2Y_SET0_C2_Msk (_U_(0x7F) << ISI_R2Y_SET0_C2_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_R2Y_SET0_C2(value) (ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)) +#define ISI_R2Y_SET0_Roff_Pos 24 /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Position */ +#define ISI_R2Y_SET0_Roff_Msk (_U_(0x1) << ISI_R2Y_SET0_Roff_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Mask */ +#define ISI_R2Y_SET0_Roff ISI_R2Y_SET0_Roff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET0_Roff_Msk instead */ +#define ISI_R2Y_SET0_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET0) Register MASK (Use ISI_R2Y_SET0_Msk instead) */ +#define ISI_R2Y_SET0_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET0) Register Mask */ + + +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1c) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C3:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C3 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t C4:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C4 */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t C5:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C5 */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t Goff:1; /**< bit: 24 Color Space Conversion Green Component Offset */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_R2Y_SET1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_R2Y_SET1_OFFSET (0x1C) /**< (ISI_R2Y_SET1) ISI Color Space Conversion RGB To YCrCb Set 1 Register Offset */ + +#define ISI_R2Y_SET1_C3_Pos 0 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_R2Y_SET1_C3_Msk (_U_(0x7F) << ISI_R2Y_SET1_C3_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_R2Y_SET1_C3(value) (ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)) +#define ISI_R2Y_SET1_C4_Pos 8 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_R2Y_SET1_C4_Msk (_U_(0x7F) << ISI_R2Y_SET1_C4_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_R2Y_SET1_C4(value) (ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)) +#define ISI_R2Y_SET1_C5_Pos 16 /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Position */ +#define ISI_R2Y_SET1_C5_Msk (_U_(0x7F) << ISI_R2Y_SET1_C5_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Mask */ +#define ISI_R2Y_SET1_C5(value) (ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)) +#define ISI_R2Y_SET1_Goff_Pos 24 /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Position */ +#define ISI_R2Y_SET1_Goff_Msk (_U_(0x1) << ISI_R2Y_SET1_Goff_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Mask */ +#define ISI_R2Y_SET1_Goff ISI_R2Y_SET1_Goff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET1_Goff_Msk instead */ +#define ISI_R2Y_SET1_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET1) Register MASK (Use ISI_R2Y_SET1_Msk instead) */ +#define ISI_R2Y_SET1_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C6:7; /**< bit: 0..6 Color Space Conversion Matrix Coefficient C6 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t C7:7; /**< bit: 8..14 Color Space Conversion Matrix Coefficient C7 */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t C8:7; /**< bit: 16..22 Color Space Conversion Matrix Coefficient C8 */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t Boff:1; /**< bit: 24 Color Space Conversion Blue Component Offset */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_R2Y_SET2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_R2Y_SET2_OFFSET (0x20) /**< (ISI_R2Y_SET2) ISI Color Space Conversion RGB To YCrCb Set 2 Register Offset */ + +#define ISI_R2Y_SET2_C6_Pos 0 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Position */ +#define ISI_R2Y_SET2_C6_Msk (_U_(0x7F) << ISI_R2Y_SET2_C6_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Mask */ +#define ISI_R2Y_SET2_C6(value) (ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)) +#define ISI_R2Y_SET2_C7_Pos 8 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Position */ +#define ISI_R2Y_SET2_C7_Msk (_U_(0x7F) << ISI_R2Y_SET2_C7_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Mask */ +#define ISI_R2Y_SET2_C7(value) (ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)) +#define ISI_R2Y_SET2_C8_Pos 16 /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Position */ +#define ISI_R2Y_SET2_C8_Msk (_U_(0x7F) << ISI_R2Y_SET2_C8_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Mask */ +#define ISI_R2Y_SET2_C8(value) (ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)) +#define ISI_R2Y_SET2_Boff_Pos 24 /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Position */ +#define ISI_R2Y_SET2_Boff_Msk (_U_(0x1) << ISI_R2Y_SET2_Boff_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Mask */ +#define ISI_R2Y_SET2_Boff ISI_R2Y_SET2_Boff_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_R2Y_SET2_Boff_Msk instead */ +#define ISI_R2Y_SET2_MASK _U_(0x17F7F7F) /**< \deprecated (ISI_R2Y_SET2) Register MASK (Use ISI_R2Y_SET2_Msk instead) */ +#define ISI_R2Y_SET2_Msk _U_(0x17F7F7F) /**< (ISI_R2Y_SET2) Register Mask */ + + +/* -------- ISI_CR : (ISI Offset: 0x24) (/W 32) ISI Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ISI_EN:1; /**< bit: 0 ISI Module Enable Request */ + uint32_t ISI_DIS:1; /**< bit: 1 ISI Module Disable Request */ + uint32_t ISI_SRST:1; /**< bit: 2 ISI Software Reset Request */ + uint32_t :5; /**< bit: 3..7 Reserved */ + uint32_t ISI_CDC:1; /**< bit: 8 ISI Codec Request */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_CR_OFFSET (0x24) /**< (ISI_CR) ISI Control Register Offset */ + +#define ISI_CR_ISI_EN_Pos 0 /**< (ISI_CR) ISI Module Enable Request Position */ +#define ISI_CR_ISI_EN_Msk (_U_(0x1) << ISI_CR_ISI_EN_Pos) /**< (ISI_CR) ISI Module Enable Request Mask */ +#define ISI_CR_ISI_EN ISI_CR_ISI_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_EN_Msk instead */ +#define ISI_CR_ISI_DIS_Pos 1 /**< (ISI_CR) ISI Module Disable Request Position */ +#define ISI_CR_ISI_DIS_Msk (_U_(0x1) << ISI_CR_ISI_DIS_Pos) /**< (ISI_CR) ISI Module Disable Request Mask */ +#define ISI_CR_ISI_DIS ISI_CR_ISI_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_DIS_Msk instead */ +#define ISI_CR_ISI_SRST_Pos 2 /**< (ISI_CR) ISI Software Reset Request Position */ +#define ISI_CR_ISI_SRST_Msk (_U_(0x1) << ISI_CR_ISI_SRST_Pos) /**< (ISI_CR) ISI Software Reset Request Mask */ +#define ISI_CR_ISI_SRST ISI_CR_ISI_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_SRST_Msk instead */ +#define ISI_CR_ISI_CDC_Pos 8 /**< (ISI_CR) ISI Codec Request Position */ +#define ISI_CR_ISI_CDC_Msk (_U_(0x1) << ISI_CR_ISI_CDC_Pos) /**< (ISI_CR) ISI Codec Request Mask */ +#define ISI_CR_ISI_CDC ISI_CR_ISI_CDC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_CR_ISI_CDC_Msk instead */ +#define ISI_CR_MASK _U_(0x107) /**< \deprecated (ISI_CR) Register MASK (Use ISI_CR_Msk instead) */ +#define ISI_CR_Msk _U_(0x107) /**< (ISI_CR) Register Mask */ + + +/* -------- ISI_SR : (ISI Offset: 0x28) (R/ 32) ISI Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ENABLE:1; /**< bit: 0 Module Enable */ + uint32_t DIS_DONE:1; /**< bit: 1 Module Disable Request has Terminated (cleared on read) */ + uint32_t SRST:1; /**< bit: 2 Module Software Reset Request has Terminated (cleared on read) */ + uint32_t :5; /**< bit: 3..7 Reserved */ + uint32_t CDC_PND:1; /**< bit: 8 Pending Codec Request */ + uint32_t :1; /**< bit: 9 Reserved */ + uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization (cleared on read) */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer has Terminated (cleared on read) */ + uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer has Terminated (cleared on read) */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t SIP:1; /**< bit: 19 Synchronization in Progress */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow (cleared on read) */ + uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow (cleared on read) */ + uint32_t CRC_ERR:1; /**< bit: 26 CRC Synchronization Error (cleared on read) */ + uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overrun (cleared on read) */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_SR_OFFSET (0x28) /**< (ISI_SR) ISI Status Register Offset */ + +#define ISI_SR_ENABLE_Pos 0 /**< (ISI_SR) Module Enable Position */ +#define ISI_SR_ENABLE_Msk (_U_(0x1) << ISI_SR_ENABLE_Pos) /**< (ISI_SR) Module Enable Mask */ +#define ISI_SR_ENABLE ISI_SR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_ENABLE_Msk instead */ +#define ISI_SR_DIS_DONE_Pos 1 /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Position */ +#define ISI_SR_DIS_DONE_Msk (_U_(0x1) << ISI_SR_DIS_DONE_Pos) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Mask */ +#define ISI_SR_DIS_DONE ISI_SR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_DIS_DONE_Msk instead */ +#define ISI_SR_SRST_Pos 2 /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Position */ +#define ISI_SR_SRST_Msk (_U_(0x1) << ISI_SR_SRST_Pos) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Mask */ +#define ISI_SR_SRST ISI_SR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_SRST_Msk instead */ +#define ISI_SR_CDC_PND_Pos 8 /**< (ISI_SR) Pending Codec Request Position */ +#define ISI_SR_CDC_PND_Msk (_U_(0x1) << ISI_SR_CDC_PND_Pos) /**< (ISI_SR) Pending Codec Request Mask */ +#define ISI_SR_CDC_PND ISI_SR_CDC_PND_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CDC_PND_Msk instead */ +#define ISI_SR_VSYNC_Pos 10 /**< (ISI_SR) Vertical Synchronization (cleared on read) Position */ +#define ISI_SR_VSYNC_Msk (_U_(0x1) << ISI_SR_VSYNC_Pos) /**< (ISI_SR) Vertical Synchronization (cleared on read) Mask */ +#define ISI_SR_VSYNC ISI_SR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_VSYNC_Msk instead */ +#define ISI_SR_PXFR_DONE_Pos 16 /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_PXFR_DONE_Msk (_U_(0x1) << ISI_SR_PXFR_DONE_Pos) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_PXFR_DONE ISI_SR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_PXFR_DONE_Msk instead */ +#define ISI_SR_CXFR_DONE_Pos 17 /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_CXFR_DONE_Msk (_U_(0x1) << ISI_SR_CXFR_DONE_Pos) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_CXFR_DONE ISI_SR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CXFR_DONE_Msk instead */ +#define ISI_SR_SIP_Pos 19 /**< (ISI_SR) Synchronization in Progress Position */ +#define ISI_SR_SIP_Msk (_U_(0x1) << ISI_SR_SIP_Pos) /**< (ISI_SR) Synchronization in Progress Mask */ +#define ISI_SR_SIP ISI_SR_SIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_SIP_Msk instead */ +#define ISI_SR_P_OVR_Pos 24 /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Position */ +#define ISI_SR_P_OVR_Msk (_U_(0x1) << ISI_SR_P_OVR_Pos) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_P_OVR ISI_SR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_P_OVR_Msk instead */ +#define ISI_SR_C_OVR_Pos 25 /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Position */ +#define ISI_SR_C_OVR_Msk (_U_(0x1) << ISI_SR_C_OVR_Pos) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_C_OVR ISI_SR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_C_OVR_Msk instead */ +#define ISI_SR_CRC_ERR_Pos 26 /**< (ISI_SR) CRC Synchronization Error (cleared on read) Position */ +#define ISI_SR_CRC_ERR_Msk (_U_(0x1) << ISI_SR_CRC_ERR_Pos) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Mask */ +#define ISI_SR_CRC_ERR ISI_SR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_CRC_ERR_Msk instead */ +#define ISI_SR_FR_OVR_Pos 27 /**< (ISI_SR) Frame Rate Overrun (cleared on read) Position */ +#define ISI_SR_FR_OVR_Msk (_U_(0x1) << ISI_SR_FR_OVR_Pos) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Mask */ +#define ISI_SR_FR_OVR ISI_SR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_SR_FR_OVR_Msk instead */ +#define ISI_SR_MASK _U_(0xF0B0507) /**< \deprecated (ISI_SR) Register MASK (Use ISI_SR_Msk instead) */ +#define ISI_SR_Msk _U_(0xF0B0507) /**< (ISI_SR) Register Mask */ + + +/* -------- ISI_IER : (ISI Offset: 0x2c) (/W 32) ISI Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t DIS_DONE:1; /**< bit: 1 Disable Done Interrupt Enable */ + uint32_t SRST:1; /**< bit: 2 Software Reset Interrupt Enable */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization Interrupt Enable */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Done Interrupt Enable */ + uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Done Interrupt Enable */ + uint32_t :6; /**< bit: 18..23 Reserved */ + uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow Interrupt Enable */ + uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow Interrupt Enable */ + uint32_t CRC_ERR:1; /**< bit: 26 Embedded Synchronization CRC Error Interrupt Enable */ + uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overflow Interrupt Enable */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_IER_OFFSET (0x2C) /**< (ISI_IER) ISI Interrupt Enable Register Offset */ + +#define ISI_IER_DIS_DONE_Pos 1 /**< (ISI_IER) Disable Done Interrupt Enable Position */ +#define ISI_IER_DIS_DONE_Msk (_U_(0x1) << ISI_IER_DIS_DONE_Pos) /**< (ISI_IER) Disable Done Interrupt Enable Mask */ +#define ISI_IER_DIS_DONE ISI_IER_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_DIS_DONE_Msk instead */ +#define ISI_IER_SRST_Pos 2 /**< (ISI_IER) Software Reset Interrupt Enable Position */ +#define ISI_IER_SRST_Msk (_U_(0x1) << ISI_IER_SRST_Pos) /**< (ISI_IER) Software Reset Interrupt Enable Mask */ +#define ISI_IER_SRST ISI_IER_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_SRST_Msk instead */ +#define ISI_IER_VSYNC_Pos 10 /**< (ISI_IER) Vertical Synchronization Interrupt Enable Position */ +#define ISI_IER_VSYNC_Msk (_U_(0x1) << ISI_IER_VSYNC_Pos) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Mask */ +#define ISI_IER_VSYNC ISI_IER_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_VSYNC_Msk instead */ +#define ISI_IER_PXFR_DONE_Pos 16 /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_PXFR_DONE_Msk (_U_(0x1) << ISI_IER_PXFR_DONE_Pos) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_PXFR_DONE ISI_IER_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_PXFR_DONE_Msk instead */ +#define ISI_IER_CXFR_DONE_Pos 17 /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_CXFR_DONE_Msk (_U_(0x1) << ISI_IER_CXFR_DONE_Pos) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_CXFR_DONE ISI_IER_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_CXFR_DONE_Msk instead */ +#define ISI_IER_P_OVR_Pos 24 /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_P_OVR_Msk (_U_(0x1) << ISI_IER_P_OVR_Pos) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_P_OVR ISI_IER_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_P_OVR_Msk instead */ +#define ISI_IER_C_OVR_Pos 25 /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_C_OVR_Msk (_U_(0x1) << ISI_IER_C_OVR_Pos) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_C_OVR ISI_IER_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_C_OVR_Msk instead */ +#define ISI_IER_CRC_ERR_Pos 26 /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Position */ +#define ISI_IER_CRC_ERR_Msk (_U_(0x1) << ISI_IER_CRC_ERR_Pos) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Mask */ +#define ISI_IER_CRC_ERR ISI_IER_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_CRC_ERR_Msk instead */ +#define ISI_IER_FR_OVR_Pos 27 /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Position */ +#define ISI_IER_FR_OVR_Msk (_U_(0x1) << ISI_IER_FR_OVR_Pos) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Mask */ +#define ISI_IER_FR_OVR ISI_IER_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IER_FR_OVR_Msk instead */ +#define ISI_IER_MASK _U_(0xF030406) /**< \deprecated (ISI_IER) Register MASK (Use ISI_IER_Msk instead) */ +#define ISI_IER_Msk _U_(0xF030406) /**< (ISI_IER) Register Mask */ + + +/* -------- ISI_IDR : (ISI Offset: 0x30) (/W 32) ISI Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t DIS_DONE:1; /**< bit: 1 Disable Done Interrupt Disable */ + uint32_t SRST:1; /**< bit: 2 Software Reset Interrupt Disable */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization Interrupt Disable */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Done Interrupt Disable */ + uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Done Interrupt Disable */ + uint32_t :6; /**< bit: 18..23 Reserved */ + uint32_t P_OVR:1; /**< bit: 24 Preview Datapath Overflow Interrupt Disable */ + uint32_t C_OVR:1; /**< bit: 25 Codec Datapath Overflow Interrupt Disable */ + uint32_t CRC_ERR:1; /**< bit: 26 Embedded Synchronization CRC Error Interrupt Disable */ + uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overflow Interrupt Disable */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_IDR_OFFSET (0x30) /**< (ISI_IDR) ISI Interrupt Disable Register Offset */ + +#define ISI_IDR_DIS_DONE_Pos 1 /**< (ISI_IDR) Disable Done Interrupt Disable Position */ +#define ISI_IDR_DIS_DONE_Msk (_U_(0x1) << ISI_IDR_DIS_DONE_Pos) /**< (ISI_IDR) Disable Done Interrupt Disable Mask */ +#define ISI_IDR_DIS_DONE ISI_IDR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_DIS_DONE_Msk instead */ +#define ISI_IDR_SRST_Pos 2 /**< (ISI_IDR) Software Reset Interrupt Disable Position */ +#define ISI_IDR_SRST_Msk (_U_(0x1) << ISI_IDR_SRST_Pos) /**< (ISI_IDR) Software Reset Interrupt Disable Mask */ +#define ISI_IDR_SRST ISI_IDR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_SRST_Msk instead */ +#define ISI_IDR_VSYNC_Pos 10 /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Position */ +#define ISI_IDR_VSYNC_Msk (_U_(0x1) << ISI_IDR_VSYNC_Pos) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Mask */ +#define ISI_IDR_VSYNC ISI_IDR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_VSYNC_Msk instead */ +#define ISI_IDR_PXFR_DONE_Pos 16 /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_PXFR_DONE_Msk (_U_(0x1) << ISI_IDR_PXFR_DONE_Pos) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_PXFR_DONE ISI_IDR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_PXFR_DONE_Msk instead */ +#define ISI_IDR_CXFR_DONE_Pos 17 /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_CXFR_DONE_Msk (_U_(0x1) << ISI_IDR_CXFR_DONE_Pos) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_CXFR_DONE ISI_IDR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_CXFR_DONE_Msk instead */ +#define ISI_IDR_P_OVR_Pos 24 /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_P_OVR_Msk (_U_(0x1) << ISI_IDR_P_OVR_Pos) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_P_OVR ISI_IDR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_P_OVR_Msk instead */ +#define ISI_IDR_C_OVR_Pos 25 /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_C_OVR_Msk (_U_(0x1) << ISI_IDR_C_OVR_Pos) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_C_OVR ISI_IDR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_C_OVR_Msk instead */ +#define ISI_IDR_CRC_ERR_Pos 26 /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Position */ +#define ISI_IDR_CRC_ERR_Msk (_U_(0x1) << ISI_IDR_CRC_ERR_Pos) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Mask */ +#define ISI_IDR_CRC_ERR ISI_IDR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_CRC_ERR_Msk instead */ +#define ISI_IDR_FR_OVR_Pos 27 /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Position */ +#define ISI_IDR_FR_OVR_Msk (_U_(0x1) << ISI_IDR_FR_OVR_Pos) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Mask */ +#define ISI_IDR_FR_OVR ISI_IDR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IDR_FR_OVR_Msk instead */ +#define ISI_IDR_MASK _U_(0xF030406) /**< \deprecated (ISI_IDR) Register MASK (Use ISI_IDR_Msk instead) */ +#define ISI_IDR_Msk _U_(0xF030406) /**< (ISI_IDR) Register Mask */ + + +/* -------- ISI_IMR : (ISI Offset: 0x34) (R/ 32) ISI Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t DIS_DONE:1; /**< bit: 1 Module Disable Operation Completed */ + uint32_t SRST:1; /**< bit: 2 Software Reset Completed */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t VSYNC:1; /**< bit: 10 Vertical Synchronization */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t PXFR_DONE:1; /**< bit: 16 Preview DMA Transfer Completed */ + uint32_t CXFR_DONE:1; /**< bit: 17 Codec DMA Transfer Completed */ + uint32_t :6; /**< bit: 18..23 Reserved */ + uint32_t P_OVR:1; /**< bit: 24 Preview FIFO Overflow */ + uint32_t C_OVR:1; /**< bit: 25 Codec FIFO Overflow */ + uint32_t CRC_ERR:1; /**< bit: 26 CRC Synchronization Error */ + uint32_t FR_OVR:1; /**< bit: 27 Frame Rate Overrun */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_IMR_OFFSET (0x34) /**< (ISI_IMR) ISI Interrupt Mask Register Offset */ + +#define ISI_IMR_DIS_DONE_Pos 1 /**< (ISI_IMR) Module Disable Operation Completed Position */ +#define ISI_IMR_DIS_DONE_Msk (_U_(0x1) << ISI_IMR_DIS_DONE_Pos) /**< (ISI_IMR) Module Disable Operation Completed Mask */ +#define ISI_IMR_DIS_DONE ISI_IMR_DIS_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_DIS_DONE_Msk instead */ +#define ISI_IMR_SRST_Pos 2 /**< (ISI_IMR) Software Reset Completed Position */ +#define ISI_IMR_SRST_Msk (_U_(0x1) << ISI_IMR_SRST_Pos) /**< (ISI_IMR) Software Reset Completed Mask */ +#define ISI_IMR_SRST ISI_IMR_SRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_SRST_Msk instead */ +#define ISI_IMR_VSYNC_Pos 10 /**< (ISI_IMR) Vertical Synchronization Position */ +#define ISI_IMR_VSYNC_Msk (_U_(0x1) << ISI_IMR_VSYNC_Pos) /**< (ISI_IMR) Vertical Synchronization Mask */ +#define ISI_IMR_VSYNC ISI_IMR_VSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_VSYNC_Msk instead */ +#define ISI_IMR_PXFR_DONE_Pos 16 /**< (ISI_IMR) Preview DMA Transfer Completed Position */ +#define ISI_IMR_PXFR_DONE_Msk (_U_(0x1) << ISI_IMR_PXFR_DONE_Pos) /**< (ISI_IMR) Preview DMA Transfer Completed Mask */ +#define ISI_IMR_PXFR_DONE ISI_IMR_PXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_PXFR_DONE_Msk instead */ +#define ISI_IMR_CXFR_DONE_Pos 17 /**< (ISI_IMR) Codec DMA Transfer Completed Position */ +#define ISI_IMR_CXFR_DONE_Msk (_U_(0x1) << ISI_IMR_CXFR_DONE_Pos) /**< (ISI_IMR) Codec DMA Transfer Completed Mask */ +#define ISI_IMR_CXFR_DONE ISI_IMR_CXFR_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_CXFR_DONE_Msk instead */ +#define ISI_IMR_P_OVR_Pos 24 /**< (ISI_IMR) Preview FIFO Overflow Position */ +#define ISI_IMR_P_OVR_Msk (_U_(0x1) << ISI_IMR_P_OVR_Pos) /**< (ISI_IMR) Preview FIFO Overflow Mask */ +#define ISI_IMR_P_OVR ISI_IMR_P_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_P_OVR_Msk instead */ +#define ISI_IMR_C_OVR_Pos 25 /**< (ISI_IMR) Codec FIFO Overflow Position */ +#define ISI_IMR_C_OVR_Msk (_U_(0x1) << ISI_IMR_C_OVR_Pos) /**< (ISI_IMR) Codec FIFO Overflow Mask */ +#define ISI_IMR_C_OVR ISI_IMR_C_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_C_OVR_Msk instead */ +#define ISI_IMR_CRC_ERR_Pos 26 /**< (ISI_IMR) CRC Synchronization Error Position */ +#define ISI_IMR_CRC_ERR_Msk (_U_(0x1) << ISI_IMR_CRC_ERR_Pos) /**< (ISI_IMR) CRC Synchronization Error Mask */ +#define ISI_IMR_CRC_ERR ISI_IMR_CRC_ERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_CRC_ERR_Msk instead */ +#define ISI_IMR_FR_OVR_Pos 27 /**< (ISI_IMR) Frame Rate Overrun Position */ +#define ISI_IMR_FR_OVR_Msk (_U_(0x1) << ISI_IMR_FR_OVR_Pos) /**< (ISI_IMR) Frame Rate Overrun Mask */ +#define ISI_IMR_FR_OVR ISI_IMR_FR_OVR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_IMR_FR_OVR_Msk instead */ +#define ISI_IMR_MASK _U_(0xF030406) /**< \deprecated (ISI_IMR) Register MASK (Use ISI_IMR_Msk instead) */ +#define ISI_IMR_Msk _U_(0xF030406) /**< (ISI_IMR) Register Mask */ + + +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) (/W 32) DMA Channel Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P_CH_EN:1; /**< bit: 0 Preview Channel Enable */ + uint32_t C_CH_EN:1; /**< bit: 1 Codec Channel Enable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_CHER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_CHER_OFFSET (0x38) /**< (ISI_DMA_CHER) DMA Channel Enable Register Offset */ + +#define ISI_DMA_CHER_P_CH_EN_Pos 0 /**< (ISI_DMA_CHER) Preview Channel Enable Position */ +#define ISI_DMA_CHER_P_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_P_CH_EN_Pos) /**< (ISI_DMA_CHER) Preview Channel Enable Mask */ +#define ISI_DMA_CHER_P_CH_EN ISI_DMA_CHER_P_CH_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHER_P_CH_EN_Msk instead */ +#define ISI_DMA_CHER_C_CH_EN_Pos 1 /**< (ISI_DMA_CHER) Codec Channel Enable Position */ +#define ISI_DMA_CHER_C_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_C_CH_EN_Pos) /**< (ISI_DMA_CHER) Codec Channel Enable Mask */ +#define ISI_DMA_CHER_C_CH_EN ISI_DMA_CHER_C_CH_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHER_C_CH_EN_Msk instead */ +#define ISI_DMA_CHER_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHER) Register MASK (Use ISI_DMA_CHER_Msk instead) */ +#define ISI_DMA_CHER_Msk _U_(0x03) /**< (ISI_DMA_CHER) Register Mask */ + + +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3c) (/W 32) DMA Channel Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P_CH_DIS:1; /**< bit: 0 Preview Channel Disable Request */ + uint32_t C_CH_DIS:1; /**< bit: 1 Codec Channel Disable Request */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_CHDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_CHDR_OFFSET (0x3C) /**< (ISI_DMA_CHDR) DMA Channel Disable Register Offset */ + +#define ISI_DMA_CHDR_P_CH_DIS_Pos 0 /**< (ISI_DMA_CHDR) Preview Channel Disable Request Position */ +#define ISI_DMA_CHDR_P_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_P_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Mask */ +#define ISI_DMA_CHDR_P_CH_DIS ISI_DMA_CHDR_P_CH_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHDR_P_CH_DIS_Msk instead */ +#define ISI_DMA_CHDR_C_CH_DIS_Pos 1 /**< (ISI_DMA_CHDR) Codec Channel Disable Request Position */ +#define ISI_DMA_CHDR_C_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_C_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Mask */ +#define ISI_DMA_CHDR_C_CH_DIS ISI_DMA_CHDR_C_CH_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHDR_C_CH_DIS_Msk instead */ +#define ISI_DMA_CHDR_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHDR) Register MASK (Use ISI_DMA_CHDR_Msk instead) */ +#define ISI_DMA_CHDR_Msk _U_(0x03) /**< (ISI_DMA_CHDR) Register Mask */ + + +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) (R/ 32) DMA Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P_CH_S:1; /**< bit: 0 Preview DMA Channel Status */ + uint32_t C_CH_S:1; /**< bit: 1 Code DMA Channel Status */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_CHSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_CHSR_OFFSET (0x40) /**< (ISI_DMA_CHSR) DMA Channel Status Register Offset */ + +#define ISI_DMA_CHSR_P_CH_S_Pos 0 /**< (ISI_DMA_CHSR) Preview DMA Channel Status Position */ +#define ISI_DMA_CHSR_P_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_P_CH_S_Pos) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Mask */ +#define ISI_DMA_CHSR_P_CH_S ISI_DMA_CHSR_P_CH_S_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHSR_P_CH_S_Msk instead */ +#define ISI_DMA_CHSR_C_CH_S_Pos 1 /**< (ISI_DMA_CHSR) Code DMA Channel Status Position */ +#define ISI_DMA_CHSR_C_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_C_CH_S_Pos) /**< (ISI_DMA_CHSR) Code DMA Channel Status Mask */ +#define ISI_DMA_CHSR_C_CH_S ISI_DMA_CHSR_C_CH_S_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_CHSR_C_CH_S_Msk instead */ +#define ISI_DMA_CHSR_MASK _U_(0x03) /**< \deprecated (ISI_DMA_CHSR) Register MASK (Use ISI_DMA_CHSR_Msk instead) */ +#define ISI_DMA_CHSR_Msk _U_(0x03) /**< (ISI_DMA_CHSR) Register Mask */ + + +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) (R/W 32) DMA Preview Base Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t P_ADDR:30; /**< bit: 2..31 Preview Image Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_P_ADDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_P_ADDR_OFFSET (0x44) /**< (ISI_DMA_P_ADDR) DMA Preview Base Address Register Offset */ + +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 /**< (ISI_DMA_P_ADDR) Preview Image Base Address Position */ +#define ISI_DMA_P_ADDR_P_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Mask */ +#define ISI_DMA_P_ADDR_P_ADDR(value) (ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)) +#define ISI_DMA_P_ADDR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_P_ADDR) Register MASK (Use ISI_DMA_P_ADDR_Msk instead) */ +#define ISI_DMA_P_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_ADDR) Register Mask */ + + +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) (R/W 32) DMA Preview Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P_FETCH:1; /**< bit: 0 Descriptor Fetch Control Bit */ + uint32_t P_WB:1; /**< bit: 1 Descriptor Writeback Control Bit */ + uint32_t P_IEN:1; /**< bit: 2 Transfer Done Flag Control */ + uint32_t P_DONE:1; /**< bit: 3 Preview Transfer Done */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_P_CTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_P_CTRL_OFFSET (0x48) /**< (ISI_DMA_P_CTRL) DMA Preview Control Register Offset */ + +#define ISI_DMA_P_CTRL_P_FETCH_Pos 0 /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_P_CTRL_P_FETCH_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_FETCH_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_FETCH ISI_DMA_P_CTRL_P_FETCH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_FETCH_Msk instead */ +#define ISI_DMA_P_CTRL_P_WB_Pos 1 /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_P_CTRL_P_WB_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_WB_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_WB ISI_DMA_P_CTRL_P_WB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_WB_Msk instead */ +#define ISI_DMA_P_CTRL_P_IEN_Pos 2 /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_P_CTRL_P_IEN_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_IEN_Pos) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_P_CTRL_P_IEN ISI_DMA_P_CTRL_P_IEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_IEN_Msk instead */ +#define ISI_DMA_P_CTRL_P_DONE_Pos 3 /**< (ISI_DMA_P_CTRL) Preview Transfer Done Position */ +#define ISI_DMA_P_CTRL_P_DONE_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_DONE_Pos) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Mask */ +#define ISI_DMA_P_CTRL_P_DONE ISI_DMA_P_CTRL_P_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_P_CTRL_P_DONE_Msk instead */ +#define ISI_DMA_P_CTRL_MASK _U_(0x0F) /**< \deprecated (ISI_DMA_P_CTRL) Register MASK (Use ISI_DMA_P_CTRL_Msk instead) */ +#define ISI_DMA_P_CTRL_Msk _U_(0x0F) /**< (ISI_DMA_P_CTRL) Register Mask */ + + +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4c) (R/W 32) DMA Preview Descriptor Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t P_DSCR:30; /**< bit: 2..31 Preview Descriptor Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_P_DSCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_P_DSCR_OFFSET (0x4C) /**< (ISI_DMA_P_DSCR) DMA Preview Descriptor Address Register Offset */ + +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Position */ +#define ISI_DMA_P_DSCR_P_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Mask */ +#define ISI_DMA_P_DSCR_P_DSCR(value) (ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)) +#define ISI_DMA_P_DSCR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_P_DSCR) Register MASK (Use ISI_DMA_P_DSCR_Msk instead) */ +#define ISI_DMA_P_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_DSCR) Register Mask */ + + +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) (R/W 32) DMA Codec Base Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t C_ADDR:30; /**< bit: 2..31 Codec Image Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_C_ADDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_C_ADDR_OFFSET (0x50) /**< (ISI_DMA_C_ADDR) DMA Codec Base Address Register Offset */ + +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 /**< (ISI_DMA_C_ADDR) Codec Image Base Address Position */ +#define ISI_DMA_C_ADDR_C_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Mask */ +#define ISI_DMA_C_ADDR_C_ADDR(value) (ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)) +#define ISI_DMA_C_ADDR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_C_ADDR) Register MASK (Use ISI_DMA_C_ADDR_Msk instead) */ +#define ISI_DMA_C_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_ADDR) Register Mask */ + + +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) (R/W 32) DMA Codec Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t C_FETCH:1; /**< bit: 0 Descriptor Fetch Control Bit */ + uint32_t C_WB:1; /**< bit: 1 Descriptor Writeback Control Bit */ + uint32_t C_IEN:1; /**< bit: 2 Transfer Done Flag Control */ + uint32_t C_DONE:1; /**< bit: 3 Codec Transfer Done */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_C_CTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_C_CTRL_OFFSET (0x54) /**< (ISI_DMA_C_CTRL) DMA Codec Control Register Offset */ + +#define ISI_DMA_C_CTRL_C_FETCH_Pos 0 /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_C_CTRL_C_FETCH_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_FETCH_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_FETCH ISI_DMA_C_CTRL_C_FETCH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_FETCH_Msk instead */ +#define ISI_DMA_C_CTRL_C_WB_Pos 1 /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_C_CTRL_C_WB_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_WB_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_WB ISI_DMA_C_CTRL_C_WB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_WB_Msk instead */ +#define ISI_DMA_C_CTRL_C_IEN_Pos 2 /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_C_CTRL_C_IEN_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_IEN_Pos) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_C_CTRL_C_IEN ISI_DMA_C_CTRL_C_IEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_IEN_Msk instead */ +#define ISI_DMA_C_CTRL_C_DONE_Pos 3 /**< (ISI_DMA_C_CTRL) Codec Transfer Done Position */ +#define ISI_DMA_C_CTRL_C_DONE_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_DONE_Pos) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Mask */ +#define ISI_DMA_C_CTRL_C_DONE ISI_DMA_C_CTRL_C_DONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_DMA_C_CTRL_C_DONE_Msk instead */ +#define ISI_DMA_C_CTRL_MASK _U_(0x0F) /**< \deprecated (ISI_DMA_C_CTRL) Register MASK (Use ISI_DMA_C_CTRL_Msk instead) */ +#define ISI_DMA_C_CTRL_Msk _U_(0x0F) /**< (ISI_DMA_C_CTRL) Register Mask */ + + +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) (R/W 32) DMA Codec Descriptor Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t C_DSCR:30; /**< bit: 2..31 Codec Descriptor Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_DMA_C_DSCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_DMA_C_DSCR_OFFSET (0x58) /**< (ISI_DMA_C_DSCR) DMA Codec Descriptor Address Register Offset */ + +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Position */ +#define ISI_DMA_C_DSCR_C_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Mask */ +#define ISI_DMA_C_DSCR_C_DSCR(value) (ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)) +#define ISI_DMA_C_DSCR_MASK _U_(0xFFFFFFFC) /**< \deprecated (ISI_DMA_C_DSCR) Register MASK (Use ISI_DMA_C_DSCR_Msk instead) */ +#define ISI_DMA_C_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_DSCR) Register Mask */ + + +/* -------- ISI_WPMR : (ISI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key Password */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_WPMR_OFFSET (0xE4) /**< (ISI_WPMR) Write Protection Mode Register Offset */ + +#define ISI_WPMR_WPEN_Pos 0 /**< (ISI_WPMR) Write Protection Enable Position */ +#define ISI_WPMR_WPEN_Msk (_U_(0x1) << ISI_WPMR_WPEN_Pos) /**< (ISI_WPMR) Write Protection Enable Mask */ +#define ISI_WPMR_WPEN ISI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_WPMR_WPEN_Msk instead */ +#define ISI_WPMR_WPKEY_Pos 8 /**< (ISI_WPMR) Write Protection Key Password Position */ +#define ISI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Write Protection Key Password Mask */ +#define ISI_WPMR_WPKEY(value) (ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)) +#define ISI_WPMR_WPKEY_PASSWD_Val _U_(0x495349) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ISI_WPMR_WPKEY_PASSWD (ISI_WPMR_WPKEY_PASSWD_Val << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ISI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (ISI_WPMR) Register MASK (Use ISI_WPMR_Msk instead) */ +#define ISI_WPMR_Msk _U_(0xFFFFFF01) /**< (ISI_WPMR) Register Mask */ + + +/* -------- ISI_WPSR : (ISI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} ISI_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ISI_WPSR_OFFSET (0xE8) /**< (ISI_WPSR) Write Protection Status Register Offset */ + +#define ISI_WPSR_WPVS_Pos 0 /**< (ISI_WPSR) Write Protection Violation Status Position */ +#define ISI_WPSR_WPVS_Msk (_U_(0x1) << ISI_WPSR_WPVS_Pos) /**< (ISI_WPSR) Write Protection Violation Status Mask */ +#define ISI_WPSR_WPVS ISI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ISI_WPSR_WPVS_Msk instead */ +#define ISI_WPSR_WPVSRC_Pos 8 /**< (ISI_WPSR) Write Protection Violation Source Position */ +#define ISI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << ISI_WPSR_WPVSRC_Pos) /**< (ISI_WPSR) Write Protection Violation Source Mask */ +#define ISI_WPSR_WPVSRC(value) (ISI_WPSR_WPVSRC_Msk & ((value) << ISI_WPSR_WPVSRC_Pos)) +#define ISI_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (ISI_WPSR) Register MASK (Use ISI_WPSR_Msk instead) */ +#define ISI_WPSR_Msk _U_(0xFFFF01) /**< (ISI_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief ISI hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< (ISI Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< (ISI Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< (ISI Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< (ISI Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< (ISI Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< (ISI Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< (ISI Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< (ISI Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< (ISI Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< (ISI Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< (ISI Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< (ISI Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< (ISI Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< (ISI Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< (ISI Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< (ISI Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< (ISI Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< (ISI Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint8_t Reserved1[136]; + __IO uint32_t ISI_WPMR; /**< (ISI Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< (ISI Offset: 0xE8) Write Protection Status Register */ +} Isi; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief ISI hardware registers */ +typedef struct { + __IO ISI_CFG1_Type ISI_CFG1; /**< Offset: 0x00 (R/W 32) ISI Configuration 1 Register */ + __IO ISI_CFG2_Type ISI_CFG2; /**< Offset: 0x04 (R/W 32) ISI Configuration 2 Register */ + __IO ISI_PSIZE_Type ISI_PSIZE; /**< Offset: 0x08 (R/W 32) ISI Preview Size Register */ + __IO ISI_PDECF_Type ISI_PDECF; /**< Offset: 0x0C (R/W 32) ISI Preview Decimation Factor Register */ + __IO ISI_Y2R_SET0_Type ISI_Y2R_SET0; /**< Offset: 0x10 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO ISI_Y2R_SET1_Type ISI_Y2R_SET1; /**< Offset: 0x14 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO ISI_R2Y_SET0_Type ISI_R2Y_SET0; /**< Offset: 0x18 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO ISI_R2Y_SET1_Type ISI_R2Y_SET1; /**< Offset: 0x1C (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO ISI_R2Y_SET2_Type ISI_R2Y_SET2; /**< Offset: 0x20 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O ISI_CR_Type ISI_CR; /**< Offset: 0x24 ( /W 32) ISI Control Register */ + __I ISI_SR_Type ISI_SR; /**< Offset: 0x28 (R/ 32) ISI Status Register */ + __O ISI_IER_Type ISI_IER; /**< Offset: 0x2C ( /W 32) ISI Interrupt Enable Register */ + __O ISI_IDR_Type ISI_IDR; /**< Offset: 0x30 ( /W 32) ISI Interrupt Disable Register */ + __I ISI_IMR_Type ISI_IMR; /**< Offset: 0x34 (R/ 32) ISI Interrupt Mask Register */ + __O ISI_DMA_CHER_Type ISI_DMA_CHER; /**< Offset: 0x38 ( /W 32) DMA Channel Enable Register */ + __O ISI_DMA_CHDR_Type ISI_DMA_CHDR; /**< Offset: 0x3C ( /W 32) DMA Channel Disable Register */ + __I ISI_DMA_CHSR_Type ISI_DMA_CHSR; /**< Offset: 0x40 (R/ 32) DMA Channel Status Register */ + __IO ISI_DMA_P_ADDR_Type ISI_DMA_P_ADDR; /**< Offset: 0x44 (R/W 32) DMA Preview Base Address Register */ + __IO ISI_DMA_P_CTRL_Type ISI_DMA_P_CTRL; /**< Offset: 0x48 (R/W 32) DMA Preview Control Register */ + __IO ISI_DMA_P_DSCR_Type ISI_DMA_P_DSCR; /**< Offset: 0x4C (R/W 32) DMA Preview Descriptor Address Register */ + __IO ISI_DMA_C_ADDR_Type ISI_DMA_C_ADDR; /**< Offset: 0x50 (R/W 32) DMA Codec Base Address Register */ + __IO ISI_DMA_C_CTRL_Type ISI_DMA_C_CTRL; /**< Offset: 0x54 (R/W 32) DMA Codec Control Register */ + __IO ISI_DMA_C_DSCR_Type ISI_DMA_C_DSCR; /**< Offset: 0x58 (R/W 32) DMA Codec Descriptor Address Register */ + __I uint8_t Reserved1[136]; + __IO ISI_WPMR_Type ISI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I ISI_WPSR_Type ISI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Isi; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Image Sensor Interface */ + +#endif /* _SAME70_ISI_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/matrix.h b/bsp/microchip/same70/bsp/same70b/include/component/matrix.h new file mode 100644 index 0000000000..fb04f68f99 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/matrix.h @@ -0,0 +1,591 @@ +/** + * \file + * + * \brief Component description for MATRIX + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_MATRIX_COMPONENT_H_ +#define _SAME70_MATRIX_COMPONENT_H_ +#define _SAME70_MATRIX_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 AHB Bus Matrix + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR MATRIX */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define MATRIX_11282 /**< (MATRIX) Module ID */ +#define REV_MATRIX L /**< (MATRIX) Module revision */ + +/* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t M0PR:2; /**< bit: 0..1 Master 0 Priority */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t M1PR:2; /**< bit: 4..5 Master 1 Priority */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t M2PR:2; /**< bit: 8..9 Master 2 Priority */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t M3PR:2; /**< bit: 12..13 Master 3 Priority */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t M4PR:2; /**< bit: 16..17 Master 4 Priority */ + uint32_t :2; /**< bit: 18..19 Reserved */ + uint32_t M5PR:2; /**< bit: 20..21 Master 5 Priority */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t M6PR:2; /**< bit: 24..25 Master 6 Priority */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_PRAS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_PRAS_OFFSET (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */ + +#define MATRIX_PRAS_M0PR_Pos 0 /**< (MATRIX_PRAS) Master 0 Priority Position */ +#define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */ +#define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)) +#define MATRIX_PRAS_M1PR_Pos 4 /**< (MATRIX_PRAS) Master 1 Priority Position */ +#define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */ +#define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)) +#define MATRIX_PRAS_M2PR_Pos 8 /**< (MATRIX_PRAS) Master 2 Priority Position */ +#define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */ +#define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)) +#define MATRIX_PRAS_M3PR_Pos 12 /**< (MATRIX_PRAS) Master 3 Priority Position */ +#define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */ +#define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)) +#define MATRIX_PRAS_M4PR_Pos 16 /**< (MATRIX_PRAS) Master 4 Priority Position */ +#define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */ +#define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)) +#define MATRIX_PRAS_M5PR_Pos 20 /**< (MATRIX_PRAS) Master 5 Priority Position */ +#define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */ +#define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)) +#define MATRIX_PRAS_M6PR_Pos 24 /**< (MATRIX_PRAS) Master 6 Priority Position */ +#define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */ +#define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)) +#define MATRIX_PRAS_MASK _U_(0x3333333) /**< \deprecated (MATRIX_PRAS) Register MASK (Use MATRIX_PRAS_Msk instead) */ +#define MATRIX_PRAS_Msk _U_(0x3333333) /**< (MATRIX_PRAS) Register Mask */ + + +/* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t M8PR:2; /**< bit: 0..1 Master 8 Priority */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t M9PR:2; /**< bit: 4..5 Master 9 Priority */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t M10PR:2; /**< bit: 8..9 Master 10 Priority */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t M11PR:2; /**< bit: 12..13 Master 11 Priority */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t M12PR:2; /**< bit: 16..17 Master 12 Priority */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_PRBS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_PRBS_OFFSET (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */ + +#define MATRIX_PRBS_M8PR_Pos 0 /**< (MATRIX_PRBS) Master 8 Priority Position */ +#define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */ +#define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)) +#define MATRIX_PRBS_M9PR_Pos 4 /**< (MATRIX_PRBS) Master 9 Priority Position */ +#define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */ +#define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)) +#define MATRIX_PRBS_M10PR_Pos 8 /**< (MATRIX_PRBS) Master 10 Priority Position */ +#define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */ +#define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)) +#define MATRIX_PRBS_M11PR_Pos 12 /**< (MATRIX_PRBS) Master 11 Priority Position */ +#define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */ +#define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)) +#define MATRIX_PRBS_M12PR_Pos 16 /**< (MATRIX_PRBS) Master 12 Priority Position */ +#define MATRIX_PRBS_M12PR_Msk (_U_(0x3) << MATRIX_PRBS_M12PR_Pos) /**< (MATRIX_PRBS) Master 12 Priority Mask */ +#define MATRIX_PRBS_M12PR(value) (MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)) +#define MATRIX_PRBS_MASK _U_(0x33333) /**< \deprecated (MATRIX_PRBS) Register MASK (Use MATRIX_PRBS_Msk instead) */ +#define MATRIX_PRBS_Msk _U_(0x33333) /**< (MATRIX_PRBS) Register Mask */ + + +/* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ULBT:3; /**< bit: 0..2 Undefined Length Burst Type */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_MCFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_MCFG_OFFSET (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */ + +#define MATRIX_MCFG_ULBT_Pos 0 /**< (MATRIX_MCFG) Undefined Length Burst Type Position */ +#define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */ +#define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */ +#define MATRIX_MCFG_MASK _U_(0x07) /**< \deprecated (MATRIX_MCFG) Register MASK (Use MATRIX_MCFG_Msk instead) */ +#define MATRIX_MCFG_Msk _U_(0x07) /**< (MATRIX_MCFG) Register Mask */ + + +/* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SLOT_CYCLE:9; /**< bit: 0..8 Maximum Bus Grant Duration for Masters */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t DEFMSTR_TYPE:2; /**< bit: 16..17 Default Master Type */ + uint32_t FIXED_DEFMSTR:4; /**< bit: 18..21 Fixed Default Master */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_SCFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_SCFG_OFFSET (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */ + +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */ +#define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */ +#define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 /**< (MATRIX_SCFG) Default Master Type Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 /**< (MATRIX_SCFG) Fixed Default Master Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)) +#define MATRIX_SCFG_MASK _U_(0x3F01FF) /**< \deprecated (MATRIX_SCFG) Register MASK (Use MATRIX_SCFG_Msk instead) */ +#define MATRIX_SCFG_Msk _U_(0x3F01FF) /**< (MATRIX_SCFG) Register Mask */ + + +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RCB0:1; /**< bit: 0 Remap Command Bit for Master 0 */ + uint32_t RCB1:1; /**< bit: 1 Remap Command Bit for Master 1 */ + uint32_t RCB2:1; /**< bit: 2 Remap Command Bit for Master 2 */ + uint32_t RCB3:1; /**< bit: 3 Remap Command Bit for Master 3 */ + uint32_t RCB4:1; /**< bit: 4 Remap Command Bit for Master 4 */ + uint32_t RCB5:1; /**< bit: 5 Remap Command Bit for Master 5 */ + uint32_t RCB6:1; /**< bit: 6 Remap Command Bit for Master 6 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t RCB8:1; /**< bit: 8 Remap Command Bit for Master 8 */ + uint32_t RCB9:1; /**< bit: 9 Remap Command Bit for Master 9 */ + uint32_t RCB10:1; /**< bit: 10 Remap Command Bit for Master 10 */ + uint32_t RCB11:1; /**< bit: 11 Remap Command Bit for Master 11 */ + uint32_t RCB12:1; /**< bit: 12 Remap Command Bit for Master 12 */ + uint32_t :19; /**< bit: 13..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t RCB:12; /**< bit: 0..11 Remap Command Bit for Master x2 */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_MRCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_MRCR_OFFSET (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */ + +#define MATRIX_MRCR_RCB0_Pos 0 /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */ +#define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */ +#define MATRIX_MRCR_RCB0 MATRIX_MRCR_RCB0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB0_Msk instead */ +#define MATRIX_MRCR_RCB1_Pos 1 /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */ +#define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */ +#define MATRIX_MRCR_RCB1 MATRIX_MRCR_RCB1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB1_Msk instead */ +#define MATRIX_MRCR_RCB2_Pos 2 /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */ +#define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */ +#define MATRIX_MRCR_RCB2 MATRIX_MRCR_RCB2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB2_Msk instead */ +#define MATRIX_MRCR_RCB3_Pos 3 /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */ +#define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */ +#define MATRIX_MRCR_RCB3 MATRIX_MRCR_RCB3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB3_Msk instead */ +#define MATRIX_MRCR_RCB4_Pos 4 /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */ +#define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */ +#define MATRIX_MRCR_RCB4 MATRIX_MRCR_RCB4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB4_Msk instead */ +#define MATRIX_MRCR_RCB5_Pos 5 /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */ +#define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */ +#define MATRIX_MRCR_RCB5 MATRIX_MRCR_RCB5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB5_Msk instead */ +#define MATRIX_MRCR_RCB6_Pos 6 /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */ +#define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */ +#define MATRIX_MRCR_RCB6 MATRIX_MRCR_RCB6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB6_Msk instead */ +#define MATRIX_MRCR_RCB8_Pos 8 /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */ +#define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */ +#define MATRIX_MRCR_RCB8 MATRIX_MRCR_RCB8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB8_Msk instead */ +#define MATRIX_MRCR_RCB9_Pos 9 /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */ +#define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */ +#define MATRIX_MRCR_RCB9 MATRIX_MRCR_RCB9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB9_Msk instead */ +#define MATRIX_MRCR_RCB10_Pos 10 /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */ +#define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */ +#define MATRIX_MRCR_RCB10 MATRIX_MRCR_RCB10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB10_Msk instead */ +#define MATRIX_MRCR_RCB11_Pos 11 /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */ +#define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */ +#define MATRIX_MRCR_RCB11 MATRIX_MRCR_RCB11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB11_Msk instead */ +#define MATRIX_MRCR_RCB12_Pos 12 /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Position */ +#define MATRIX_MRCR_RCB12_Msk (_U_(0x1) << MATRIX_MRCR_RCB12_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Mask */ +#define MATRIX_MRCR_RCB12 MATRIX_MRCR_RCB12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB12_Msk instead */ +#define MATRIX_MRCR_MASK _U_(0x1F7F) /**< \deprecated (MATRIX_MRCR) Register MASK (Use MATRIX_MRCR_Msk instead) */ +#define MATRIX_MRCR_Msk _U_(0x1F7F) /**< (MATRIX_MRCR) Register Mask */ + +#define MATRIX_MRCR_RCB_Pos 0 /**< (MATRIX_MRCR Position) Remap Command Bit for Master x2 */ +#define MATRIX_MRCR_RCB_Msk (_U_(0xFFF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */ +#define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos)) + +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :16; /**< bit: 0..15 Reserved */ + uint32_t CAN0DMABA:16; /**< bit: 16..31 CAN0 DMA Base Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CCFG_CAN0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCFG_CAN0_OFFSET (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */ + +#define CCFG_CAN0_CAN0DMABA_Pos 16 /**< (CCFG_CAN0) CAN0 DMA Base Address Position */ +#define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */ +#define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)) +#define CCFG_CAN0_MASK _U_(0xFFFF0000) /**< \deprecated (CCFG_CAN0) Register MASK (Use CCFG_CAN0_Msk instead) */ +#define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */ + + +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t SYSIO4:1; /**< bit: 4 PB4 or TDI Assignment */ + uint32_t SYSIO5:1; /**< bit: 5 PB5 or TDO/TRACESWO Assignment */ + uint32_t SYSIO6:1; /**< bit: 6 PB6 or TMS/SWDIO Assignment */ + uint32_t SYSIO7:1; /**< bit: 7 PB7 or TCK/SWCLK Assignment */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t SYSIO12:1; /**< bit: 12 PB12 or ERASE Assignment */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t CAN1DMABA:16; /**< bit: 16..31 CAN1 DMA Base Address */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t SYSIO:5; /**< bit: 4..8 PB4 or TDI Assignment */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} CCFG_SYSIO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCFG_SYSIO_OFFSET (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */ + +#define CCFG_SYSIO_SYSIO4_Pos 4 /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */ +#define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */ +#define CCFG_SYSIO_SYSIO4 CCFG_SYSIO_SYSIO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO4_Msk instead */ +#define CCFG_SYSIO_SYSIO5_Pos 5 /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */ +#define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */ +#define CCFG_SYSIO_SYSIO5 CCFG_SYSIO_SYSIO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO5_Msk instead */ +#define CCFG_SYSIO_SYSIO6_Pos 6 /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */ +#define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */ +#define CCFG_SYSIO_SYSIO6 CCFG_SYSIO_SYSIO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO6_Msk instead */ +#define CCFG_SYSIO_SYSIO7_Pos 7 /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */ +#define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */ +#define CCFG_SYSIO_SYSIO7 CCFG_SYSIO_SYSIO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO7_Msk instead */ +#define CCFG_SYSIO_SYSIO12_Pos 12 /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */ +#define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */ +#define CCFG_SYSIO_SYSIO12 CCFG_SYSIO_SYSIO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO12_Msk instead */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */ +#define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */ +#define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)) +#define CCFG_SYSIO_MASK _U_(0xFFFF10F0) /**< \deprecated (CCFG_SYSIO) Register MASK (Use CCFG_SYSIO_Msk instead) */ +#define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */ + +#define CCFG_SYSIO_SYSIO_Pos 4 /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */ +#define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos)) + +/* -------- CCFG_PCCR : (MATRIX Offset: 0x118) (R/W 32) Peripheral Clock Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :20; /**< bit: 0..19 Reserved */ + uint32_t TC0CC:1; /**< bit: 20 TC0 Clock Configuration */ + uint32_t I2SC0CC:1; /**< bit: 21 I2SC0 Clock Configuration */ + uint32_t I2SC1CC:1; /**< bit: 22 I2SC1 Clock Configuration */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CCFG_PCCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCFG_PCCR_OFFSET (0x118) /**< (CCFG_PCCR) Peripheral Clock Configuration Register Offset */ + +#define CCFG_PCCR_TC0CC_Pos 20 /**< (CCFG_PCCR) TC0 Clock Configuration Position */ +#define CCFG_PCCR_TC0CC_Msk (_U_(0x1) << CCFG_PCCR_TC0CC_Pos) /**< (CCFG_PCCR) TC0 Clock Configuration Mask */ +#define CCFG_PCCR_TC0CC CCFG_PCCR_TC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_TC0CC_Msk instead */ +#define CCFG_PCCR_I2SC0CC_Pos 21 /**< (CCFG_PCCR) I2SC0 Clock Configuration Position */ +#define CCFG_PCCR_I2SC0CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC0CC_Pos) /**< (CCFG_PCCR) I2SC0 Clock Configuration Mask */ +#define CCFG_PCCR_I2SC0CC CCFG_PCCR_I2SC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC0CC_Msk instead */ +#define CCFG_PCCR_I2SC1CC_Pos 22 /**< (CCFG_PCCR) I2SC1 Clock Configuration Position */ +#define CCFG_PCCR_I2SC1CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC1CC_Pos) /**< (CCFG_PCCR) I2SC1 Clock Configuration Mask */ +#define CCFG_PCCR_I2SC1CC CCFG_PCCR_I2SC1CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC1CC_Msk instead */ +#define CCFG_PCCR_MASK _U_(0x700000) /**< \deprecated (CCFG_PCCR) Register MASK (Use CCFG_PCCR_Msk instead) */ +#define CCFG_PCCR_Msk _U_(0x700000) /**< (CCFG_PCCR) Register Mask */ + + +/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MATCKG:1; /**< bit: 0 MATRIX Dynamic Clock Gating */ + uint32_t BRIDCKG:1; /**< bit: 1 Bridge Dynamic Clock Gating Enable */ + uint32_t EFCCKG:1; /**< bit: 2 EFC Dynamic Clock Gating Enable */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CCFG_DYNCKG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCFG_DYNCKG_OFFSET (0x11C) /**< (CCFG_DYNCKG) Dynamic Clock Gating Register Offset */ + +#define CCFG_DYNCKG_MATCKG_Pos 0 /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Position */ +#define CCFG_DYNCKG_MATCKG_Msk (_U_(0x1) << CCFG_DYNCKG_MATCKG_Pos) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Mask */ +#define CCFG_DYNCKG_MATCKG CCFG_DYNCKG_MATCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_MATCKG_Msk instead */ +#define CCFG_DYNCKG_BRIDCKG_Pos 1 /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Position */ +#define CCFG_DYNCKG_BRIDCKG_Msk (_U_(0x1) << CCFG_DYNCKG_BRIDCKG_Pos) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Mask */ +#define CCFG_DYNCKG_BRIDCKG CCFG_DYNCKG_BRIDCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_BRIDCKG_Msk instead */ +#define CCFG_DYNCKG_EFCCKG_Pos 2 /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Position */ +#define CCFG_DYNCKG_EFCCKG_Msk (_U_(0x1) << CCFG_DYNCKG_EFCCKG_Pos) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Mask */ +#define CCFG_DYNCKG_EFCCKG CCFG_DYNCKG_EFCCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_EFCCKG_Msk instead */ +#define CCFG_DYNCKG_MASK _U_(0x07) /**< \deprecated (CCFG_DYNCKG) Register MASK (Use CCFG_DYNCKG_Msk instead) */ +#define CCFG_DYNCKG_Msk _U_(0x07) /**< (CCFG_DYNCKG) Register Mask */ + + +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SMC_NFCS0:1; /**< bit: 0 SMC NAND Flash Chip Select 0 Assignment */ + uint32_t SMC_NFCS1:1; /**< bit: 1 SMC NAND Flash Chip Select 1 Assignment */ + uint32_t SMC_NFCS2:1; /**< bit: 2 SMC NAND Flash Chip Select 2 Assignment */ + uint32_t SMC_NFCS3:1; /**< bit: 3 SMC NAND Flash Chip Select 3 Assignment */ + uint32_t SDRAMEN:1; /**< bit: 4 SDRAM Enable */ + uint32_t :27; /**< bit: 5..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SMC_NFCS:4; /**< bit: 0..3 SMC NAND Flash Chip Select x Assignment */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} CCFG_SMCNFCS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCFG_SMCNFCS_OFFSET (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */ + +#define CCFG_SMCNFCS_SMC_NFCS0_Pos 0 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS0 CCFG_SMCNFCS_SMC_NFCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS0_Msk instead */ +#define CCFG_SMCNFCS_SMC_NFCS1_Pos 1 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS1 CCFG_SMCNFCS_SMC_NFCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS1_Msk instead */ +#define CCFG_SMCNFCS_SMC_NFCS2_Pos 2 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS2 CCFG_SMCNFCS_SMC_NFCS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS2_Msk instead */ +#define CCFG_SMCNFCS_SMC_NFCS3_Pos 3 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS3 CCFG_SMCNFCS_SMC_NFCS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS3_Msk instead */ +#define CCFG_SMCNFCS_SDRAMEN_Pos 4 /**< (CCFG_SMCNFCS) SDRAM Enable Position */ +#define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */ +#define CCFG_SMCNFCS_SDRAMEN CCFG_SMCNFCS_SDRAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SDRAMEN_Msk instead */ +#define CCFG_SMCNFCS_MASK _U_(0x1F) /**< \deprecated (CCFG_SMCNFCS) Register MASK (Use CCFG_SMCNFCS_Msk instead) */ +#define CCFG_SMCNFCS_Msk _U_(0x1F) /**< (CCFG_SMCNFCS) Register Mask */ + +#define CCFG_SMCNFCS_SMC_NFCS_Pos 0 /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */ +#define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos)) + +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1e4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_WPMR_OFFSET (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */ + +#define MATRIX_WPMR_WPEN_Pos 0 /**< (MATRIX_WPMR) Write Protection Enable Position */ +#define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */ +#define MATRIX_WPMR_WPEN MATRIX_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPMR_WPEN_Msk instead */ +#define MATRIX_WPMR_WPKEY_Pos 8 /**< (MATRIX_WPMR) Write Protection Key Position */ +#define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */ +#define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)) +#define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define MATRIX_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (MATRIX_WPMR) Register MASK (Use MATRIX_WPMR_Msk instead) */ +#define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */ + + +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1e8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MATRIX_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MATRIX_WPSR_OFFSET (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */ + +#define MATRIX_WPSR_WPVS_Pos 0 /**< (MATRIX_WPSR) Write Protection Violation Status Position */ +#define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */ +#define MATRIX_WPSR_WPVS MATRIX_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPSR_WPVS_Msk instead */ +#define MATRIX_WPSR_WPVSRC_Pos 8 /**< (MATRIX_WPSR) Write Protection Violation Source Position */ +#define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */ +#define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos)) +#define MATRIX_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (MATRIX_WPSR) Register MASK (Use MATRIX_WPSR_Msk instead) */ +#define MATRIX_WPSR_Msk _U_(0xFFFF01) /**< (MATRIX_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief MATRIX_PR hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< (MATRIX_PR Offset: 0x00) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< (MATRIX_PR Offset: 0x04) Priority Register B for Slave 0 */ +} MatrixPr; + +#define MATRIXPR_NUMBER 9 +/** \brief MATRIX hardware registers */ +typedef struct { + __IO uint32_t MATRIX_MCFG[13]; /**< (MATRIX Offset: 0x00) Master Configuration Register 0 */ + __I uint8_t Reserved1[12]; + __IO uint32_t MATRIX_SCFG[9]; /**< (MATRIX Offset: 0x40) Slave Configuration Register 0 */ + __I uint8_t Reserved2[28]; + MatrixPr MatrixPr[MATRIXPR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */ + __I uint8_t Reserved3[56]; + __IO uint32_t MATRIX_MRCR; /**< (MATRIX Offset: 0x100) Master Remap Control Register */ + __I uint8_t Reserved4[12]; + __IO uint32_t CCFG_CAN0; /**< (MATRIX Offset: 0x110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< (MATRIX Offset: 0x114) System I/O and CAN1 Configuration Register */ + __IO uint32_t CCFG_PCCR; /**< (MATRIX Offset: 0x118) Peripheral Clock Configuration Register */ + __IO uint32_t CCFG_DYNCKG; /**< (MATRIX Offset: 0x11C) Dynamic Clock Gating Register */ + __I uint8_t Reserved5[4]; + __IO uint32_t CCFG_SMCNFCS; /**< (MATRIX Offset: 0x124) SMC NAND Flash Chip Select Configuration Register */ + __I uint8_t Reserved6[188]; + __IO uint32_t MATRIX_WPMR; /**< (MATRIX Offset: 0x1E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< (MATRIX Offset: 0x1E8) Write Protection Status Register */ +} Matrix; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief MATRIX_PR hardware registers */ +typedef struct { + __IO MATRIX_PRAS_Type MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */ + __IO MATRIX_PRBS_Type MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */ +} MatrixPr; + +/** \brief MATRIX hardware registers */ +typedef struct { + __IO MATRIX_MCFG_Type MATRIX_MCFG[13]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */ + __I uint8_t Reserved1[12]; + __IO MATRIX_SCFG_Type MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */ + __I uint8_t Reserved2[28]; + MatrixPr MatrixPr[9]; /**< Offset: 0x80 Priority Register A for Slave 0 */ + __I uint8_t Reserved3[56]; + __IO MATRIX_MRCR_Type MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */ + __I uint8_t Reserved4[12]; + __IO CCFG_CAN0_Type CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */ + __IO CCFG_SYSIO_Type CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */ + __IO CCFG_PCCR_Type CCFG_PCCR; /**< Offset: 0x118 (R/W 32) Peripheral Clock Configuration Register */ + __IO CCFG_DYNCKG_Type CCFG_DYNCKG; /**< Offset: 0x11C (R/W 32) Dynamic Clock Gating Register */ + __I uint8_t Reserved5[4]; + __IO CCFG_SMCNFCS_Type CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */ + __I uint8_t Reserved6[188]; + __IO MATRIX_WPMR_Type MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */ + __I MATRIX_WPSR_Type MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */ +} Matrix; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of AHB Bus Matrix */ + +#endif /* _SAME70_MATRIX_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/mcan.h b/bsp/microchip/same70/bsp/same70b/include/component/mcan.h new file mode 100644 index 0000000000..780253e365 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/mcan.h @@ -0,0 +1,4032 @@ +/** + * \file + * + * \brief Component description for MCAN + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_MCAN_COMPONENT_H_ +#define _SAME70_MCAN_COMPONENT_H_ +#define _SAME70_MCAN_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Controller Area Network + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR MCAN */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define MCAN_11273 /**< (MCAN) Module ID */ +#define REV_MCAN N /**< (MCAN) Module revision */ + +/* -------- MCAN_RXBE_0 : (MCAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID:29; /**< bit: 0..28 Identifier */ + uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /**< bit: 30 Extended Identifier */ + uint32_t ESI:1; /**< bit: 31 Error State Indicator */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXBE_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXBE_0_OFFSET (0x00) /**< (MCAN_RXBE_0) Rx Buffer Element 0 Offset */ + +#define MCAN_RXBE_0_ID_Pos 0 /**< (MCAN_RXBE_0) Identifier Position */ +#define MCAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXBE_0_ID_Pos) /**< (MCAN_RXBE_0) Identifier Mask */ +#define MCAN_RXBE_0_ID(value) (MCAN_RXBE_0_ID_Msk & ((value) << MCAN_RXBE_0_ID_Pos)) +#define MCAN_RXBE_0_RTR_Pos 29 /**< (MCAN_RXBE_0) Remote Transmission Request Position */ +#define MCAN_RXBE_0_RTR_Msk (_U_(0x1) << MCAN_RXBE_0_RTR_Pos) /**< (MCAN_RXBE_0) Remote Transmission Request Mask */ +#define MCAN_RXBE_0_RTR MCAN_RXBE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_RTR_Msk instead */ +#define MCAN_RXBE_0_XTD_Pos 30 /**< (MCAN_RXBE_0) Extended Identifier Position */ +#define MCAN_RXBE_0_XTD_Msk (_U_(0x1) << MCAN_RXBE_0_XTD_Pos) /**< (MCAN_RXBE_0) Extended Identifier Mask */ +#define MCAN_RXBE_0_XTD MCAN_RXBE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_XTD_Msk instead */ +#define MCAN_RXBE_0_ESI_Pos 31 /**< (MCAN_RXBE_0) Error State Indicator Position */ +#define MCAN_RXBE_0_ESI_Msk (_U_(0x1) << MCAN_RXBE_0_ESI_Pos) /**< (MCAN_RXBE_0) Error State Indicator Mask */ +#define MCAN_RXBE_0_ESI MCAN_RXBE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_ESI_Msk instead */ +#define MCAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXBE_0) Register MASK (Use MCAN_RXBE_0_Msk instead) */ +#define MCAN_RXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_0) Register Mask */ + + +/* -------- MCAN_RXBE_1 : (MCAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ + uint32_t FDF:1; /**< bit: 21 FD Format */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXBE_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXBE_1_OFFSET (0x04) /**< (MCAN_RXBE_1) Rx Buffer Element 1 Offset */ + +#define MCAN_RXBE_1_RXTS_Pos 0 /**< (MCAN_RXBE_1) Rx Timestamp Position */ +#define MCAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXBE_1_RXTS_Pos) /**< (MCAN_RXBE_1) Rx Timestamp Mask */ +#define MCAN_RXBE_1_RXTS(value) (MCAN_RXBE_1_RXTS_Msk & ((value) << MCAN_RXBE_1_RXTS_Pos)) +#define MCAN_RXBE_1_DLC_Pos 16 /**< (MCAN_RXBE_1) Data Length Code Position */ +#define MCAN_RXBE_1_DLC_Msk (_U_(0xF) << MCAN_RXBE_1_DLC_Pos) /**< (MCAN_RXBE_1) Data Length Code Mask */ +#define MCAN_RXBE_1_DLC(value) (MCAN_RXBE_1_DLC_Msk & ((value) << MCAN_RXBE_1_DLC_Pos)) +#define MCAN_RXBE_1_BRS_Pos 20 /**< (MCAN_RXBE_1) Bit Rate Switch Position */ +#define MCAN_RXBE_1_BRS_Msk (_U_(0x1) << MCAN_RXBE_1_BRS_Pos) /**< (MCAN_RXBE_1) Bit Rate Switch Mask */ +#define MCAN_RXBE_1_BRS MCAN_RXBE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_BRS_Msk instead */ +#define MCAN_RXBE_1_FDF_Pos 21 /**< (MCAN_RXBE_1) FD Format Position */ +#define MCAN_RXBE_1_FDF_Msk (_U_(0x1) << MCAN_RXBE_1_FDF_Pos) /**< (MCAN_RXBE_1) FD Format Mask */ +#define MCAN_RXBE_1_FDF MCAN_RXBE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_FDF_Msk instead */ +#define MCAN_RXBE_1_FIDX_Pos 24 /**< (MCAN_RXBE_1) Filter Index Position */ +#define MCAN_RXBE_1_FIDX_Msk (_U_(0x7F) << MCAN_RXBE_1_FIDX_Pos) /**< (MCAN_RXBE_1) Filter Index Mask */ +#define MCAN_RXBE_1_FIDX(value) (MCAN_RXBE_1_FIDX_Msk & ((value) << MCAN_RXBE_1_FIDX_Pos)) +#define MCAN_RXBE_1_ANMF_Pos 31 /**< (MCAN_RXBE_1) Accepted Non-matching Frame Position */ +#define MCAN_RXBE_1_ANMF_Msk (_U_(0x1) << MCAN_RXBE_1_ANMF_Pos) /**< (MCAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXBE_1_ANMF MCAN_RXBE_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_ANMF_Msk instead */ +#define MCAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXBE_1) Register MASK (Use MCAN_RXBE_1_Msk instead) */ +#define MCAN_RXBE_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXBE_1) Register Mask */ + + +/* -------- MCAN_RXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ + uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXBE_DATA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXBE_DATA_OFFSET (0x08) /**< (MCAN_RXBE_DATA) Rx Buffer Element Data Offset */ + +#define MCAN_RXBE_DATA_DB0_Pos 0 /**< (MCAN_RXBE_DATA) Data Byte 0 Position */ +#define MCAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB0_Pos) /**< (MCAN_RXBE_DATA) Data Byte 0 Mask */ +#define MCAN_RXBE_DATA_DB0(value) (MCAN_RXBE_DATA_DB0_Msk & ((value) << MCAN_RXBE_DATA_DB0_Pos)) +#define MCAN_RXBE_DATA_DB1_Pos 8 /**< (MCAN_RXBE_DATA) Data Byte 1 Position */ +#define MCAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB1_Pos) /**< (MCAN_RXBE_DATA) Data Byte 1 Mask */ +#define MCAN_RXBE_DATA_DB1(value) (MCAN_RXBE_DATA_DB1_Msk & ((value) << MCAN_RXBE_DATA_DB1_Pos)) +#define MCAN_RXBE_DATA_DB2_Pos 16 /**< (MCAN_RXBE_DATA) Data Byte 2 Position */ +#define MCAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB2_Pos) /**< (MCAN_RXBE_DATA) Data Byte 2 Mask */ +#define MCAN_RXBE_DATA_DB2(value) (MCAN_RXBE_DATA_DB2_Msk & ((value) << MCAN_RXBE_DATA_DB2_Pos)) +#define MCAN_RXBE_DATA_DB3_Pos 24 /**< (MCAN_RXBE_DATA) Data Byte 3 Position */ +#define MCAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB3_Pos) /**< (MCAN_RXBE_DATA) Data Byte 3 Mask */ +#define MCAN_RXBE_DATA_DB3(value) (MCAN_RXBE_DATA_DB3_Msk & ((value) << MCAN_RXBE_DATA_DB3_Pos)) +#define MCAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXBE_DATA) Register MASK (Use MCAN_RXBE_DATA_Msk instead) */ +#define MCAN_RXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_DATA) Register Mask */ + + +/* -------- MCAN_RXF0E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID:29; /**< bit: 0..28 Identifier */ + uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /**< bit: 30 Extended Identifier */ + uint32_t ESI:1; /**< bit: 31 Error State Indicator */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0E_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0E_0_OFFSET (0x00) /**< (MCAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ + +#define MCAN_RXF0E_0_ID_Pos 0 /**< (MCAN_RXF0E_0) Identifier Position */ +#define MCAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF0E_0_ID_Pos) /**< (MCAN_RXF0E_0) Identifier Mask */ +#define MCAN_RXF0E_0_ID(value) (MCAN_RXF0E_0_ID_Msk & ((value) << MCAN_RXF0E_0_ID_Pos)) +#define MCAN_RXF0E_0_RTR_Pos 29 /**< (MCAN_RXF0E_0) Remote Transmission Request Position */ +#define MCAN_RXF0E_0_RTR_Msk (_U_(0x1) << MCAN_RXF0E_0_RTR_Pos) /**< (MCAN_RXF0E_0) Remote Transmission Request Mask */ +#define MCAN_RXF0E_0_RTR MCAN_RXF0E_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_RTR_Msk instead */ +#define MCAN_RXF0E_0_XTD_Pos 30 /**< (MCAN_RXF0E_0) Extended Identifier Position */ +#define MCAN_RXF0E_0_XTD_Msk (_U_(0x1) << MCAN_RXF0E_0_XTD_Pos) /**< (MCAN_RXF0E_0) Extended Identifier Mask */ +#define MCAN_RXF0E_0_XTD MCAN_RXF0E_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_XTD_Msk instead */ +#define MCAN_RXF0E_0_ESI_Pos 31 /**< (MCAN_RXF0E_0) Error State Indicator Position */ +#define MCAN_RXF0E_0_ESI_Msk (_U_(0x1) << MCAN_RXF0E_0_ESI_Pos) /**< (MCAN_RXF0E_0) Error State Indicator Mask */ +#define MCAN_RXF0E_0_ESI MCAN_RXF0E_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_ESI_Msk instead */ +#define MCAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF0E_0) Register MASK (Use MCAN_RXF0E_0_Msk instead) */ +#define MCAN_RXF0E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_0) Register Mask */ + + +/* -------- MCAN_RXF0E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ + uint32_t FDF:1; /**< bit: 21 FD Format */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0E_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0E_1_OFFSET (0x04) /**< (MCAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ + +#define MCAN_RXF0E_1_RXTS_Pos 0 /**< (MCAN_RXF0E_1) Rx Timestamp Position */ +#define MCAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF0E_1_RXTS_Pos) /**< (MCAN_RXF0E_1) Rx Timestamp Mask */ +#define MCAN_RXF0E_1_RXTS(value) (MCAN_RXF0E_1_RXTS_Msk & ((value) << MCAN_RXF0E_1_RXTS_Pos)) +#define MCAN_RXF0E_1_DLC_Pos 16 /**< (MCAN_RXF0E_1) Data Length Code Position */ +#define MCAN_RXF0E_1_DLC_Msk (_U_(0xF) << MCAN_RXF0E_1_DLC_Pos) /**< (MCAN_RXF0E_1) Data Length Code Mask */ +#define MCAN_RXF0E_1_DLC(value) (MCAN_RXF0E_1_DLC_Msk & ((value) << MCAN_RXF0E_1_DLC_Pos)) +#define MCAN_RXF0E_1_BRS_Pos 20 /**< (MCAN_RXF0E_1) Bit Rate Switch Position */ +#define MCAN_RXF0E_1_BRS_Msk (_U_(0x1) << MCAN_RXF0E_1_BRS_Pos) /**< (MCAN_RXF0E_1) Bit Rate Switch Mask */ +#define MCAN_RXF0E_1_BRS MCAN_RXF0E_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_BRS_Msk instead */ +#define MCAN_RXF0E_1_FDF_Pos 21 /**< (MCAN_RXF0E_1) FD Format Position */ +#define MCAN_RXF0E_1_FDF_Msk (_U_(0x1) << MCAN_RXF0E_1_FDF_Pos) /**< (MCAN_RXF0E_1) FD Format Mask */ +#define MCAN_RXF0E_1_FDF MCAN_RXF0E_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_FDF_Msk instead */ +#define MCAN_RXF0E_1_FIDX_Pos 24 /**< (MCAN_RXF0E_1) Filter Index Position */ +#define MCAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF0E_1_FIDX_Pos) /**< (MCAN_RXF0E_1) Filter Index Mask */ +#define MCAN_RXF0E_1_FIDX(value) (MCAN_RXF0E_1_FIDX_Msk & ((value) << MCAN_RXF0E_1_FIDX_Pos)) +#define MCAN_RXF0E_1_ANMF_Pos 31 /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define MCAN_RXF0E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF0E_1_ANMF_Pos) /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXF0E_1_ANMF MCAN_RXF0E_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_ANMF_Msk instead */ +#define MCAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXF0E_1) Register MASK (Use MCAN_RXF0E_1_Msk instead) */ +#define MCAN_RXF0E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF0E_1) Register Mask */ + + +/* -------- MCAN_RXF0E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ + uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0E_DATA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0E_DATA_OFFSET (0x08) /**< (MCAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ + +#define MCAN_RXF0E_DATA_DB0_Pos 0 /**< (MCAN_RXF0E_DATA) Data Byte 0 Position */ +#define MCAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB0_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 0 Mask */ +#define MCAN_RXF0E_DATA_DB0(value) (MCAN_RXF0E_DATA_DB0_Msk & ((value) << MCAN_RXF0E_DATA_DB0_Pos)) +#define MCAN_RXF0E_DATA_DB1_Pos 8 /**< (MCAN_RXF0E_DATA) Data Byte 1 Position */ +#define MCAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB1_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 1 Mask */ +#define MCAN_RXF0E_DATA_DB1(value) (MCAN_RXF0E_DATA_DB1_Msk & ((value) << MCAN_RXF0E_DATA_DB1_Pos)) +#define MCAN_RXF0E_DATA_DB2_Pos 16 /**< (MCAN_RXF0E_DATA) Data Byte 2 Position */ +#define MCAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB2_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 2 Mask */ +#define MCAN_RXF0E_DATA_DB2(value) (MCAN_RXF0E_DATA_DB2_Msk & ((value) << MCAN_RXF0E_DATA_DB2_Pos)) +#define MCAN_RXF0E_DATA_DB3_Pos 24 /**< (MCAN_RXF0E_DATA) Data Byte 3 Position */ +#define MCAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB3_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 3 Mask */ +#define MCAN_RXF0E_DATA_DB3(value) (MCAN_RXF0E_DATA_DB3_Msk & ((value) << MCAN_RXF0E_DATA_DB3_Pos)) +#define MCAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF0E_DATA) Register MASK (Use MCAN_RXF0E_DATA_Msk instead) */ +#define MCAN_RXF0E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_DATA) Register Mask */ + + +/* -------- MCAN_RXF1E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID:29; /**< bit: 0..28 Identifier */ + uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /**< bit: 30 Extended Identifier */ + uint32_t ESI:1; /**< bit: 31 Error State Indicator */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1E_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1E_0_OFFSET (0x00) /**< (MCAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ + +#define MCAN_RXF1E_0_ID_Pos 0 /**< (MCAN_RXF1E_0) Identifier Position */ +#define MCAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF1E_0_ID_Pos) /**< (MCAN_RXF1E_0) Identifier Mask */ +#define MCAN_RXF1E_0_ID(value) (MCAN_RXF1E_0_ID_Msk & ((value) << MCAN_RXF1E_0_ID_Pos)) +#define MCAN_RXF1E_0_RTR_Pos 29 /**< (MCAN_RXF1E_0) Remote Transmission Request Position */ +#define MCAN_RXF1E_0_RTR_Msk (_U_(0x1) << MCAN_RXF1E_0_RTR_Pos) /**< (MCAN_RXF1E_0) Remote Transmission Request Mask */ +#define MCAN_RXF1E_0_RTR MCAN_RXF1E_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_RTR_Msk instead */ +#define MCAN_RXF1E_0_XTD_Pos 30 /**< (MCAN_RXF1E_0) Extended Identifier Position */ +#define MCAN_RXF1E_0_XTD_Msk (_U_(0x1) << MCAN_RXF1E_0_XTD_Pos) /**< (MCAN_RXF1E_0) Extended Identifier Mask */ +#define MCAN_RXF1E_0_XTD MCAN_RXF1E_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_XTD_Msk instead */ +#define MCAN_RXF1E_0_ESI_Pos 31 /**< (MCAN_RXF1E_0) Error State Indicator Position */ +#define MCAN_RXF1E_0_ESI_Msk (_U_(0x1) << MCAN_RXF1E_0_ESI_Pos) /**< (MCAN_RXF1E_0) Error State Indicator Mask */ +#define MCAN_RXF1E_0_ESI MCAN_RXF1E_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_ESI_Msk instead */ +#define MCAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF1E_0) Register MASK (Use MCAN_RXF1E_0_Msk instead) */ +#define MCAN_RXF1E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_0) Register Mask */ + + +/* -------- MCAN_RXF1E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ + uint32_t FDF:1; /**< bit: 21 FD Format */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1E_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1E_1_OFFSET (0x04) /**< (MCAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ + +#define MCAN_RXF1E_1_RXTS_Pos 0 /**< (MCAN_RXF1E_1) Rx Timestamp Position */ +#define MCAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF1E_1_RXTS_Pos) /**< (MCAN_RXF1E_1) Rx Timestamp Mask */ +#define MCAN_RXF1E_1_RXTS(value) (MCAN_RXF1E_1_RXTS_Msk & ((value) << MCAN_RXF1E_1_RXTS_Pos)) +#define MCAN_RXF1E_1_DLC_Pos 16 /**< (MCAN_RXF1E_1) Data Length Code Position */ +#define MCAN_RXF1E_1_DLC_Msk (_U_(0xF) << MCAN_RXF1E_1_DLC_Pos) /**< (MCAN_RXF1E_1) Data Length Code Mask */ +#define MCAN_RXF1E_1_DLC(value) (MCAN_RXF1E_1_DLC_Msk & ((value) << MCAN_RXF1E_1_DLC_Pos)) +#define MCAN_RXF1E_1_BRS_Pos 20 /**< (MCAN_RXF1E_1) Bit Rate Switch Position */ +#define MCAN_RXF1E_1_BRS_Msk (_U_(0x1) << MCAN_RXF1E_1_BRS_Pos) /**< (MCAN_RXF1E_1) Bit Rate Switch Mask */ +#define MCAN_RXF1E_1_BRS MCAN_RXF1E_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_BRS_Msk instead */ +#define MCAN_RXF1E_1_FDF_Pos 21 /**< (MCAN_RXF1E_1) FD Format Position */ +#define MCAN_RXF1E_1_FDF_Msk (_U_(0x1) << MCAN_RXF1E_1_FDF_Pos) /**< (MCAN_RXF1E_1) FD Format Mask */ +#define MCAN_RXF1E_1_FDF MCAN_RXF1E_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_FDF_Msk instead */ +#define MCAN_RXF1E_1_FIDX_Pos 24 /**< (MCAN_RXF1E_1) Filter Index Position */ +#define MCAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF1E_1_FIDX_Pos) /**< (MCAN_RXF1E_1) Filter Index Mask */ +#define MCAN_RXF1E_1_FIDX(value) (MCAN_RXF1E_1_FIDX_Msk & ((value) << MCAN_RXF1E_1_FIDX_Pos)) +#define MCAN_RXF1E_1_ANMF_Pos 31 /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define MCAN_RXF1E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF1E_1_ANMF_Pos) /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXF1E_1_ANMF MCAN_RXF1E_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_ANMF_Msk instead */ +#define MCAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXF1E_1) Register MASK (Use MCAN_RXF1E_1_Msk instead) */ +#define MCAN_RXF1E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF1E_1) Register Mask */ + + +/* -------- MCAN_RXF1E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ + uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1E_DATA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1E_DATA_OFFSET (0x08) /**< (MCAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ + +#define MCAN_RXF1E_DATA_DB0_Pos 0 /**< (MCAN_RXF1E_DATA) Data Byte 0 Position */ +#define MCAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB0_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 0 Mask */ +#define MCAN_RXF1E_DATA_DB0(value) (MCAN_RXF1E_DATA_DB0_Msk & ((value) << MCAN_RXF1E_DATA_DB0_Pos)) +#define MCAN_RXF1E_DATA_DB1_Pos 8 /**< (MCAN_RXF1E_DATA) Data Byte 1 Position */ +#define MCAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB1_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 1 Mask */ +#define MCAN_RXF1E_DATA_DB1(value) (MCAN_RXF1E_DATA_DB1_Msk & ((value) << MCAN_RXF1E_DATA_DB1_Pos)) +#define MCAN_RXF1E_DATA_DB2_Pos 16 /**< (MCAN_RXF1E_DATA) Data Byte 2 Position */ +#define MCAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB2_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 2 Mask */ +#define MCAN_RXF1E_DATA_DB2(value) (MCAN_RXF1E_DATA_DB2_Msk & ((value) << MCAN_RXF1E_DATA_DB2_Pos)) +#define MCAN_RXF1E_DATA_DB3_Pos 24 /**< (MCAN_RXF1E_DATA) Data Byte 3 Position */ +#define MCAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB3_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 3 Mask */ +#define MCAN_RXF1E_DATA_DB3(value) (MCAN_RXF1E_DATA_DB3_Msk & ((value) << MCAN_RXF1E_DATA_DB3_Pos)) +#define MCAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF1E_DATA) Register MASK (Use MCAN_RXF1E_DATA_Msk instead) */ +#define MCAN_RXF1E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_DATA) Register Mask */ + + +/* -------- MCAN_TXBE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID:29; /**< bit: 0..28 Identifier */ + uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /**< bit: 30 Extended Identifier */ + uint32_t ESI:1; /**< bit: 31 Error State Indicator */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBE_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBE_0_OFFSET (0x00) /**< (MCAN_TXBE_0) Tx Buffer Element 0 Offset */ + +#define MCAN_TXBE_0_ID_Pos 0 /**< (MCAN_TXBE_0) Identifier Position */ +#define MCAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXBE_0_ID_Pos) /**< (MCAN_TXBE_0) Identifier Mask */ +#define MCAN_TXBE_0_ID(value) (MCAN_TXBE_0_ID_Msk & ((value) << MCAN_TXBE_0_ID_Pos)) +#define MCAN_TXBE_0_RTR_Pos 29 /**< (MCAN_TXBE_0) Remote Transmission Request Position */ +#define MCAN_TXBE_0_RTR_Msk (_U_(0x1) << MCAN_TXBE_0_RTR_Pos) /**< (MCAN_TXBE_0) Remote Transmission Request Mask */ +#define MCAN_TXBE_0_RTR MCAN_TXBE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_RTR_Msk instead */ +#define MCAN_TXBE_0_XTD_Pos 30 /**< (MCAN_TXBE_0) Extended Identifier Position */ +#define MCAN_TXBE_0_XTD_Msk (_U_(0x1) << MCAN_TXBE_0_XTD_Pos) /**< (MCAN_TXBE_0) Extended Identifier Mask */ +#define MCAN_TXBE_0_XTD MCAN_TXBE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_XTD_Msk instead */ +#define MCAN_TXBE_0_ESI_Pos 31 /**< (MCAN_TXBE_0) Error State Indicator Position */ +#define MCAN_TXBE_0_ESI_Msk (_U_(0x1) << MCAN_TXBE_0_ESI_Pos) /**< (MCAN_TXBE_0) Error State Indicator Mask */ +#define MCAN_TXBE_0_ESI MCAN_TXBE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_ESI_Msk instead */ +#define MCAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBE_0) Register MASK (Use MCAN_TXBE_0_Msk instead) */ +#define MCAN_TXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_0) Register Mask */ + + +/* -------- MCAN_TXBE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :16; /**< bit: 0..15 Reserved */ + uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ + uint32_t FDF:1; /**< bit: 21 FD Format */ + uint32_t :1; /**< bit: 22 Reserved */ + uint32_t EFC:1; /**< bit: 23 Event FIFO Control */ + uint32_t MM:8; /**< bit: 24..31 Message Marker */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBE_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBE_1_OFFSET (0x04) /**< (MCAN_TXBE_1) Tx Buffer Element 1 Offset */ + +#define MCAN_TXBE_1_DLC_Pos 16 /**< (MCAN_TXBE_1) Data Length Code Position */ +#define MCAN_TXBE_1_DLC_Msk (_U_(0xF) << MCAN_TXBE_1_DLC_Pos) /**< (MCAN_TXBE_1) Data Length Code Mask */ +#define MCAN_TXBE_1_DLC(value) (MCAN_TXBE_1_DLC_Msk & ((value) << MCAN_TXBE_1_DLC_Pos)) +#define MCAN_TXBE_1_BRS_Pos 20 /**< (MCAN_TXBE_1) Bit Rate Switch Position */ +#define MCAN_TXBE_1_BRS_Msk (_U_(0x1) << MCAN_TXBE_1_BRS_Pos) /**< (MCAN_TXBE_1) Bit Rate Switch Mask */ +#define MCAN_TXBE_1_BRS MCAN_TXBE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_BRS_Msk instead */ +#define MCAN_TXBE_1_FDF_Pos 21 /**< (MCAN_TXBE_1) FD Format Position */ +#define MCAN_TXBE_1_FDF_Msk (_U_(0x1) << MCAN_TXBE_1_FDF_Pos) /**< (MCAN_TXBE_1) FD Format Mask */ +#define MCAN_TXBE_1_FDF MCAN_TXBE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_FDF_Msk instead */ +#define MCAN_TXBE_1_EFC_Pos 23 /**< (MCAN_TXBE_1) Event FIFO Control Position */ +#define MCAN_TXBE_1_EFC_Msk (_U_(0x1) << MCAN_TXBE_1_EFC_Pos) /**< (MCAN_TXBE_1) Event FIFO Control Mask */ +#define MCAN_TXBE_1_EFC MCAN_TXBE_1_EFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_EFC_Msk instead */ +#define MCAN_TXBE_1_MM_Pos 24 /**< (MCAN_TXBE_1) Message Marker Position */ +#define MCAN_TXBE_1_MM_Msk (_U_(0xFF) << MCAN_TXBE_1_MM_Pos) /**< (MCAN_TXBE_1) Message Marker Mask */ +#define MCAN_TXBE_1_MM(value) (MCAN_TXBE_1_MM_Msk & ((value) << MCAN_TXBE_1_MM_Pos)) +#define MCAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \deprecated (MCAN_TXBE_1) Register MASK (Use MCAN_TXBE_1_Msk instead) */ +#define MCAN_TXBE_1_Msk _U_(0xFFBF0000) /**< (MCAN_TXBE_1) Register Mask */ + + +/* -------- MCAN_TXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ + uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBE_DATA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBE_DATA_OFFSET (0x08) /**< (MCAN_TXBE_DATA) Tx Buffer Element Data Offset */ + +#define MCAN_TXBE_DATA_DB0_Pos 0 /**< (MCAN_TXBE_DATA) Data Byte 0 Position */ +#define MCAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB0_Pos) /**< (MCAN_TXBE_DATA) Data Byte 0 Mask */ +#define MCAN_TXBE_DATA_DB0(value) (MCAN_TXBE_DATA_DB0_Msk & ((value) << MCAN_TXBE_DATA_DB0_Pos)) +#define MCAN_TXBE_DATA_DB1_Pos 8 /**< (MCAN_TXBE_DATA) Data Byte 1 Position */ +#define MCAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB1_Pos) /**< (MCAN_TXBE_DATA) Data Byte 1 Mask */ +#define MCAN_TXBE_DATA_DB1(value) (MCAN_TXBE_DATA_DB1_Msk & ((value) << MCAN_TXBE_DATA_DB1_Pos)) +#define MCAN_TXBE_DATA_DB2_Pos 16 /**< (MCAN_TXBE_DATA) Data Byte 2 Position */ +#define MCAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB2_Pos) /**< (MCAN_TXBE_DATA) Data Byte 2 Mask */ +#define MCAN_TXBE_DATA_DB2(value) (MCAN_TXBE_DATA_DB2_Msk & ((value) << MCAN_TXBE_DATA_DB2_Pos)) +#define MCAN_TXBE_DATA_DB3_Pos 24 /**< (MCAN_TXBE_DATA) Data Byte 3 Position */ +#define MCAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB3_Pos) /**< (MCAN_TXBE_DATA) Data Byte 3 Mask */ +#define MCAN_TXBE_DATA_DB3(value) (MCAN_TXBE_DATA_DB3_Msk & ((value) << MCAN_TXBE_DATA_DB3_Pos)) +#define MCAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBE_DATA) Register MASK (Use MCAN_TXBE_DATA_Msk instead) */ +#define MCAN_TXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_DATA) Register Mask */ + + +/* -------- MCAN_TXEFE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID:29; /**< bit: 0..28 Identifier */ + uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /**< bit: 30 Extended Identifier */ + uint32_t ESI:1; /**< bit: 31 Error State Indicator */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXEFE_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXEFE_0_OFFSET (0x00) /**< (MCAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ + +#define MCAN_TXEFE_0_ID_Pos 0 /**< (MCAN_TXEFE_0) Identifier Position */ +#define MCAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXEFE_0_ID_Pos) /**< (MCAN_TXEFE_0) Identifier Mask */ +#define MCAN_TXEFE_0_ID(value) (MCAN_TXEFE_0_ID_Msk & ((value) << MCAN_TXEFE_0_ID_Pos)) +#define MCAN_TXEFE_0_RTR_Pos 29 /**< (MCAN_TXEFE_0) Remote Transmission Request Position */ +#define MCAN_TXEFE_0_RTR_Msk (_U_(0x1) << MCAN_TXEFE_0_RTR_Pos) /**< (MCAN_TXEFE_0) Remote Transmission Request Mask */ +#define MCAN_TXEFE_0_RTR MCAN_TXEFE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_RTR_Msk instead */ +#define MCAN_TXEFE_0_XTD_Pos 30 /**< (MCAN_TXEFE_0) Extended Identifier Position */ +#define MCAN_TXEFE_0_XTD_Msk (_U_(0x1) << MCAN_TXEFE_0_XTD_Pos) /**< (MCAN_TXEFE_0) Extended Identifier Mask */ +#define MCAN_TXEFE_0_XTD MCAN_TXEFE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_XTD_Msk instead */ +#define MCAN_TXEFE_0_ESI_Pos 31 /**< (MCAN_TXEFE_0) Error State Indicator Position */ +#define MCAN_TXEFE_0_ESI_Msk (_U_(0x1) << MCAN_TXEFE_0_ESI_Pos) /**< (MCAN_TXEFE_0) Error State Indicator Mask */ +#define MCAN_TXEFE_0_ESI MCAN_TXEFE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_ESI_Msk instead */ +#define MCAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXEFE_0) Register MASK (Use MCAN_TXEFE_0_Msk instead) */ +#define MCAN_TXEFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_0) Register Mask */ + + +/* -------- MCAN_TXEFE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXTS:16; /**< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ + uint32_t FDF:1; /**< bit: 21 FD Format */ + uint32_t ET:2; /**< bit: 22..23 Event Type */ + uint32_t MM:8; /**< bit: 24..31 Message Marker */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXEFE_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXEFE_1_OFFSET (0x04) /**< (MCAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ + +#define MCAN_TXEFE_1_TXTS_Pos 0 /**< (MCAN_TXEFE_1) Tx Timestamp Position */ +#define MCAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << MCAN_TXEFE_1_TXTS_Pos) /**< (MCAN_TXEFE_1) Tx Timestamp Mask */ +#define MCAN_TXEFE_1_TXTS(value) (MCAN_TXEFE_1_TXTS_Msk & ((value) << MCAN_TXEFE_1_TXTS_Pos)) +#define MCAN_TXEFE_1_DLC_Pos 16 /**< (MCAN_TXEFE_1) Data Length Code Position */ +#define MCAN_TXEFE_1_DLC_Msk (_U_(0xF) << MCAN_TXEFE_1_DLC_Pos) /**< (MCAN_TXEFE_1) Data Length Code Mask */ +#define MCAN_TXEFE_1_DLC(value) (MCAN_TXEFE_1_DLC_Msk & ((value) << MCAN_TXEFE_1_DLC_Pos)) +#define MCAN_TXEFE_1_BRS_Pos 20 /**< (MCAN_TXEFE_1) Bit Rate Switch Position */ +#define MCAN_TXEFE_1_BRS_Msk (_U_(0x1) << MCAN_TXEFE_1_BRS_Pos) /**< (MCAN_TXEFE_1) Bit Rate Switch Mask */ +#define MCAN_TXEFE_1_BRS MCAN_TXEFE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_1_BRS_Msk instead */ +#define MCAN_TXEFE_1_FDF_Pos 21 /**< (MCAN_TXEFE_1) FD Format Position */ +#define MCAN_TXEFE_1_FDF_Msk (_U_(0x1) << MCAN_TXEFE_1_FDF_Pos) /**< (MCAN_TXEFE_1) FD Format Mask */ +#define MCAN_TXEFE_1_FDF MCAN_TXEFE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_1_FDF_Msk instead */ +#define MCAN_TXEFE_1_ET_Pos 22 /**< (MCAN_TXEFE_1) Event Type Position */ +#define MCAN_TXEFE_1_ET_Msk (_U_(0x3) << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Event Type Mask */ +#define MCAN_TXEFE_1_ET(value) (MCAN_TXEFE_1_ET_Msk & ((value) << MCAN_TXEFE_1_ET_Pos)) +#define MCAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< (MCAN_TXEFE_1) Tx event */ +#define MCAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation */ +#define MCAN_TXEFE_1_ET_TXE (MCAN_TXEFE_1_ET_TXE_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Tx event Position */ +#define MCAN_TXEFE_1_ET_TXC (MCAN_TXEFE_1_ET_TXC_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define MCAN_TXEFE_1_MM_Pos 24 /**< (MCAN_TXEFE_1) Message Marker Position */ +#define MCAN_TXEFE_1_MM_Msk (_U_(0xFF) << MCAN_TXEFE_1_MM_Pos) /**< (MCAN_TXEFE_1) Message Marker Mask */ +#define MCAN_TXEFE_1_MM(value) (MCAN_TXEFE_1_MM_Msk & ((value) << MCAN_TXEFE_1_MM_Pos)) +#define MCAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXEFE_1) Register MASK (Use MCAN_TXEFE_1_Msk instead) */ +#define MCAN_TXEFE_1_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_1) Register Mask */ + + +/* -------- MCAN_SIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SFID2:11; /**< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t SFID1:11; /**< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /**< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /**< bit: 30..31 Standard Filter Type */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_SIDFE_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_SIDFE_0_OFFSET (0x00) /**< (MCAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ + +#define MCAN_SIDFE_0_SFID2_Pos 0 /**< (MCAN_SIDFE_0) Standard Filter ID 2 Position */ +#define MCAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID2_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define MCAN_SIDFE_0_SFID2(value) (MCAN_SIDFE_0_SFID2_Msk & ((value) << MCAN_SIDFE_0_SFID2_Pos)) +#define MCAN_SIDFE_0_SFID1_Pos 16 /**< (MCAN_SIDFE_0) Standard Filter ID 1 Position */ +#define MCAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID1_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define MCAN_SIDFE_0_SFID1(value) (MCAN_SIDFE_0_SFID1_Msk & ((value) << MCAN_SIDFE_0_SFID1_Pos)) +#define MCAN_SIDFE_0_SFEC_Pos 27 /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define MCAN_SIDFE_0_SFEC_Msk (_U_(0x7) << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define MCAN_SIDFE_0_SFEC(value) (MCAN_SIDFE_0_SFEC_Msk & ((value) << MCAN_SIDFE_0_SFEC_Pos)) +#define MCAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Disable filter element */ +#define MCAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches */ +#define MCAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches */ +#define MCAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< (MCAN_SIDFE_0) Reject ID if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_SIDFE_0) Set priority if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches */ +#define MCAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_SIDFE_0) Store into Rx Buffer */ +#define MCAN_SIDFE_0_SFEC_DISABLE (MCAN_SIDFE_0_SFEC_DISABLE_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Disable filter element Position */ +#define MCAN_SIDFE_0_SFEC_STF0M (MCAN_SIDFE_0_SFEC_STF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_STF1M (MCAN_SIDFE_0_SFEC_STF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_REJECT (MCAN_SIDFE_0_SFEC_REJECT_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Reject ID if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIORITY (MCAN_SIDFE_0_SFEC_PRIORITY_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIF0M (MCAN_SIDFE_0_SFEC_PRIF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIF1M (MCAN_SIDFE_0_SFEC_PRIF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_STRXBUF (MCAN_SIDFE_0_SFEC_STRXBUF_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store into Rx Buffer Position */ +#define MCAN_SIDFE_0_SFT_Pos 30 /**< (MCAN_SIDFE_0) Standard Filter Type Position */ +#define MCAN_SIDFE_0_SFT_Msk (_U_(0x3) << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Standard Filter Type Mask */ +#define MCAN_SIDFE_0_SFT(value) (MCAN_SIDFE_0_SFT_Msk & ((value) << MCAN_SIDFE_0_SFT_Pos)) +#define MCAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define MCAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID */ +#define MCAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< (MCAN_SIDFE_0) Classic filter */ +#define MCAN_SIDFE_0_SFT_RANGE (MCAN_SIDFE_0_SFT_RANGE_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define MCAN_SIDFE_0_SFT_DUAL (MCAN_SIDFE_0_SFT_DUAL_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID Position */ +#define MCAN_SIDFE_0_SFT_CLASSIC (MCAN_SIDFE_0_SFT_CLASSIC_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Classic filter Position */ +#define MCAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \deprecated (MCAN_SIDFE_0) Register MASK (Use MCAN_SIDFE_0_Msk instead) */ +#define MCAN_SIDFE_0_Msk _U_(0xFFFF07FF) /**< (MCAN_SIDFE_0) Register Mask */ + + +/* -------- MCAN_XIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EFID1:29; /**< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /**< bit: 29..31 Extended Filter Element Configuration */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_XIDFE_0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_XIDFE_0_OFFSET (0x00) /**< (MCAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ + +#define MCAN_XIDFE_0_EFID1_Pos 0 /**< (MCAN_XIDFE_0) Extended Filter ID 1 Position */ +#define MCAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_0_EFID1_Pos) /**< (MCAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define MCAN_XIDFE_0_EFID1(value) (MCAN_XIDFE_0_EFID1_Msk & ((value) << MCAN_XIDFE_0_EFID1_Pos)) +#define MCAN_XIDFE_0_EFEC_Pos 29 /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define MCAN_XIDFE_0_EFEC_Msk (_U_(0x7) << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define MCAN_XIDFE_0_EFEC(value) (MCAN_XIDFE_0_EFEC_Msk & ((value) << MCAN_XIDFE_0_EFEC_Pos)) +#define MCAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< (MCAN_XIDFE_0) Disable filter element */ +#define MCAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches */ +#define MCAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches */ +#define MCAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< (MCAN_XIDFE_0) Reject ID if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_XIDFE_0) Set priority if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches */ +#define MCAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_XIDFE_0) Store into Rx Buffer */ +#define MCAN_XIDFE_0_EFEC_DISABLE (MCAN_XIDFE_0_EFEC_DISABLE_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Disable filter element Position */ +#define MCAN_XIDFE_0_EFEC_STF0M (MCAN_XIDFE_0_EFEC_STF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_STF1M (MCAN_XIDFE_0_EFEC_STF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_REJECT (MCAN_XIDFE_0_EFEC_REJECT_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Reject ID if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIORITY (MCAN_XIDFE_0_EFEC_PRIORITY_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIF0M (MCAN_XIDFE_0_EFEC_PRIF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIF1M (MCAN_XIDFE_0_EFEC_PRIF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_STRXBUF (MCAN_XIDFE_0_EFEC_STRXBUF_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store into Rx Buffer Position */ +#define MCAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_XIDFE_0) Register MASK (Use MCAN_XIDFE_0_Msk instead) */ +#define MCAN_XIDFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_XIDFE_0) Register Mask */ + + +/* -------- MCAN_XIDFE_1 : (MCAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EFID2:29; /**< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /**< bit: 29 Reserved */ + uint32_t EFT:2; /**< bit: 30..31 Extended Filter Type */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_XIDFE_1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_XIDFE_1_OFFSET (0x04) /**< (MCAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ + +#define MCAN_XIDFE_1_EFID2_Pos 0 /**< (MCAN_XIDFE_1) Extended Filter ID 2 Position */ +#define MCAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_1_EFID2_Pos) /**< (MCAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define MCAN_XIDFE_1_EFID2(value) (MCAN_XIDFE_1_EFID2_Msk & ((value) << MCAN_XIDFE_1_EFID2_Pos)) +#define MCAN_XIDFE_1_EFT_Pos 30 /**< (MCAN_XIDFE_1) Extended Filter Type Position */ +#define MCAN_XIDFE_1_EFT_Msk (_U_(0x3) << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Extended Filter Type Mask */ +#define MCAN_XIDFE_1_EFT(value) (MCAN_XIDFE_1_EFT_Msk & ((value) << MCAN_XIDFE_1_EFT_Pos)) +#define MCAN_XIDFE_1_EFT_RANGE_Val _U_(0x0) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define MCAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define MCAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< (MCAN_XIDFE_1) Classic filter */ +#define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val _U_(0x3) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define MCAN_XIDFE_1_EFT_RANGE (MCAN_XIDFE_1_EFT_RANGE_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define MCAN_XIDFE_1_EFT_DUAL (MCAN_XIDFE_1_EFT_DUAL_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define MCAN_XIDFE_1_EFT_CLASSIC (MCAN_XIDFE_1_EFT_CLASSIC_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Classic filter Position */ +#define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM (MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define MCAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \deprecated (MCAN_XIDFE_1) Register MASK (Use MCAN_XIDFE_1_Msk instead) */ +#define MCAN_XIDFE_1_Msk _U_(0xDFFFFFFF) /**< (MCAN_XIDFE_1) Register Mask */ + + +/* -------- MCAN_CREL : (MCAN Offset: 0x00) (R/ 32) Core Release Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DAY:8; /**< bit: 0..7 Timestamp Day */ + uint32_t MON:8; /**< bit: 8..15 Timestamp Month */ + uint32_t YEAR:4; /**< bit: 16..19 Timestamp Year */ + uint32_t SUBSTEP:4; /**< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /**< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /**< bit: 28..31 Core Release */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_CREL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_CREL_OFFSET (0x00) /**< (MCAN_CREL) Core Release Register Offset */ + +#define MCAN_CREL_DAY_Pos 0 /**< (MCAN_CREL) Timestamp Day Position */ +#define MCAN_CREL_DAY_Msk (_U_(0xFF) << MCAN_CREL_DAY_Pos) /**< (MCAN_CREL) Timestamp Day Mask */ +#define MCAN_CREL_DAY(value) (MCAN_CREL_DAY_Msk & ((value) << MCAN_CREL_DAY_Pos)) +#define MCAN_CREL_MON_Pos 8 /**< (MCAN_CREL) Timestamp Month Position */ +#define MCAN_CREL_MON_Msk (_U_(0xFF) << MCAN_CREL_MON_Pos) /**< (MCAN_CREL) Timestamp Month Mask */ +#define MCAN_CREL_MON(value) (MCAN_CREL_MON_Msk & ((value) << MCAN_CREL_MON_Pos)) +#define MCAN_CREL_YEAR_Pos 16 /**< (MCAN_CREL) Timestamp Year Position */ +#define MCAN_CREL_YEAR_Msk (_U_(0xF) << MCAN_CREL_YEAR_Pos) /**< (MCAN_CREL) Timestamp Year Mask */ +#define MCAN_CREL_YEAR(value) (MCAN_CREL_YEAR_Msk & ((value) << MCAN_CREL_YEAR_Pos)) +#define MCAN_CREL_SUBSTEP_Pos 20 /**< (MCAN_CREL) Sub-step of Core Release Position */ +#define MCAN_CREL_SUBSTEP_Msk (_U_(0xF) << MCAN_CREL_SUBSTEP_Pos) /**< (MCAN_CREL) Sub-step of Core Release Mask */ +#define MCAN_CREL_SUBSTEP(value) (MCAN_CREL_SUBSTEP_Msk & ((value) << MCAN_CREL_SUBSTEP_Pos)) +#define MCAN_CREL_STEP_Pos 24 /**< (MCAN_CREL) Step of Core Release Position */ +#define MCAN_CREL_STEP_Msk (_U_(0xF) << MCAN_CREL_STEP_Pos) /**< (MCAN_CREL) Step of Core Release Mask */ +#define MCAN_CREL_STEP(value) (MCAN_CREL_STEP_Msk & ((value) << MCAN_CREL_STEP_Pos)) +#define MCAN_CREL_REL_Pos 28 /**< (MCAN_CREL) Core Release Position */ +#define MCAN_CREL_REL_Msk (_U_(0xF) << MCAN_CREL_REL_Pos) /**< (MCAN_CREL) Core Release Mask */ +#define MCAN_CREL_REL(value) (MCAN_CREL_REL_Msk & ((value) << MCAN_CREL_REL_Pos)) +#define MCAN_CREL_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_CREL) Register MASK (Use MCAN_CREL_Msk instead) */ +#define MCAN_CREL_Msk _U_(0xFFFFFFFF) /**< (MCAN_CREL) Register Mask */ + + +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) (R/ 32) Endian Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ETV:32; /**< bit: 0..31 Endianness Test Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_ENDN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_ENDN_OFFSET (0x04) /**< (MCAN_ENDN) Endian Register Offset */ + +#define MCAN_ENDN_ETV_Pos 0 /**< (MCAN_ENDN) Endianness Test Value Position */ +#define MCAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << MCAN_ENDN_ETV_Pos) /**< (MCAN_ENDN) Endianness Test Value Mask */ +#define MCAN_ENDN_ETV(value) (MCAN_ENDN_ETV_Msk & ((value) << MCAN_ENDN_ETV_Pos)) +#define MCAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_ENDN) Register MASK (Use MCAN_ENDN_Msk instead) */ +#define MCAN_ENDN_Msk _U_(0xFFFFFFFF) /**< (MCAN_ENDN) Register Mask */ + + +/* -------- MCAN_CUST : (MCAN Offset: 0x08) (R/W 32) Customer Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSV:32; /**< bit: 0..31 Customer-specific Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_CUST_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_CUST_OFFSET (0x08) /**< (MCAN_CUST) Customer Register Offset */ + +#define MCAN_CUST_CSV_Pos 0 /**< (MCAN_CUST) Customer-specific Value Position */ +#define MCAN_CUST_CSV_Msk (_U_(0xFFFFFFFF) << MCAN_CUST_CSV_Pos) /**< (MCAN_CUST) Customer-specific Value Mask */ +#define MCAN_CUST_CSV(value) (MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)) +#define MCAN_CUST_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_CUST) Register MASK (Use MCAN_CUST_Msk instead) */ +#define MCAN_CUST_Msk _U_(0xFFFFFFFF) /**< (MCAN_CUST) Register Mask */ + + +/* -------- MCAN_DBTP : (MCAN Offset: 0x0c) (R/W 32) Data Bit Timing and Prescaler Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DSJW:3; /**< bit: 0..2 Data (Re) Synchronization Jump Width */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t DTSEG2:4; /**< bit: 4..7 Data Time Segment After Sample Point */ + uint32_t DTSEG1:5; /**< bit: 8..12 Data Time Segment Before Sample Point */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t DBRP:5; /**< bit: 16..20 Data Bit Rate Prescaler */ + uint32_t :2; /**< bit: 21..22 Reserved */ + uint32_t TDC:1; /**< bit: 23 Transmitter Delay Compensation */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_DBTP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_DBTP_OFFSET (0x0C) /**< (MCAN_DBTP) Data Bit Timing and Prescaler Register Offset */ + +#define MCAN_DBTP_DSJW_Pos 0 /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Position */ +#define MCAN_DBTP_DSJW_Msk (_U_(0x7) << MCAN_DBTP_DSJW_Pos) /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Mask */ +#define MCAN_DBTP_DSJW(value) (MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)) +#define MCAN_DBTP_DTSEG2_Pos 4 /**< (MCAN_DBTP) Data Time Segment After Sample Point Position */ +#define MCAN_DBTP_DTSEG2_Msk (_U_(0xF) << MCAN_DBTP_DTSEG2_Pos) /**< (MCAN_DBTP) Data Time Segment After Sample Point Mask */ +#define MCAN_DBTP_DTSEG2(value) (MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)) +#define MCAN_DBTP_DTSEG1_Pos 8 /**< (MCAN_DBTP) Data Time Segment Before Sample Point Position */ +#define MCAN_DBTP_DTSEG1_Msk (_U_(0x1F) << MCAN_DBTP_DTSEG1_Pos) /**< (MCAN_DBTP) Data Time Segment Before Sample Point Mask */ +#define MCAN_DBTP_DTSEG1(value) (MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)) +#define MCAN_DBTP_DBRP_Pos 16 /**< (MCAN_DBTP) Data Bit Rate Prescaler Position */ +#define MCAN_DBTP_DBRP_Msk (_U_(0x1F) << MCAN_DBTP_DBRP_Pos) /**< (MCAN_DBTP) Data Bit Rate Prescaler Mask */ +#define MCAN_DBTP_DBRP(value) (MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos)) +#define MCAN_DBTP_TDC_Pos 23 /**< (MCAN_DBTP) Transmitter Delay Compensation Position */ +#define MCAN_DBTP_TDC_Msk (_U_(0x1) << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation Mask */ +#define MCAN_DBTP_TDC MCAN_DBTP_TDC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_DBTP_TDC_Msk instead */ +#define MCAN_DBTP_TDC_DISABLED_Val _U_(0x0) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. */ +#define MCAN_DBTP_TDC_ENABLED_Val _U_(0x1) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. */ +#define MCAN_DBTP_TDC_DISABLED (MCAN_DBTP_TDC_DISABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. Position */ +#define MCAN_DBTP_TDC_ENABLED (MCAN_DBTP_TDC_ENABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. Position */ +#define MCAN_DBTP_MASK _U_(0x9F1FF7) /**< \deprecated (MCAN_DBTP) Register MASK (Use MCAN_DBTP_Msk instead) */ +#define MCAN_DBTP_Msk _U_(0x9F1FF7) /**< (MCAN_DBTP) Register Mask */ + + +/* -------- MCAN_TEST : (MCAN Offset: 0x10) (R/W 32) Test Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t LBCK:1; /**< bit: 4 Loop Back Mode (read/write) */ + uint32_t TX:2; /**< bit: 5..6 Control of Transmit Pin (read/write) */ + uint32_t RX:1; /**< bit: 7 Receive Pin (read-only) */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TEST_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TEST_OFFSET (0x10) /**< (MCAN_TEST) Test Register Offset */ + +#define MCAN_TEST_LBCK_Pos 4 /**< (MCAN_TEST) Loop Back Mode (read/write) Position */ +#define MCAN_TEST_LBCK_Msk (_U_(0x1) << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back Mode (read/write) Mask */ +#define MCAN_TEST_LBCK MCAN_TEST_LBCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TEST_LBCK_Msk instead */ +#define MCAN_TEST_LBCK_DISABLED_Val _U_(0x0) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED_Val _U_(0x1) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_LBCK_DISABLED (MCAN_TEST_LBCK_DISABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. Position */ +#define MCAN_TEST_LBCK_ENABLED (MCAN_TEST_LBCK_ENABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). Position */ +#define MCAN_TEST_TX_Pos 5 /**< (MCAN_TEST) Control of Transmit Pin (read/write) Position */ +#define MCAN_TEST_TX_Msk (_U_(0x3) << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Mask */ +#define MCAN_TEST_TX(value) (MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)) +#define MCAN_TEST_TX_RESET_Val _U_(0x0) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val _U_(0x1) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_TX_RESET (MCAN_TEST_TX_RESET_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. Position */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. Position */ +#define MCAN_TEST_TX_DOMINANT (MCAN_TEST_TX_DOMINANT_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. Position */ +#define MCAN_TEST_TX_RECESSIVE (MCAN_TEST_TX_RECESSIVE_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. Position */ +#define MCAN_TEST_RX_Pos 7 /**< (MCAN_TEST) Receive Pin (read-only) Position */ +#define MCAN_TEST_RX_Msk (_U_(0x1) << MCAN_TEST_RX_Pos) /**< (MCAN_TEST) Receive Pin (read-only) Mask */ +#define MCAN_TEST_RX MCAN_TEST_RX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TEST_RX_Msk instead */ +#define MCAN_TEST_MASK _U_(0xF0) /**< \deprecated (MCAN_TEST) Register MASK (Use MCAN_TEST_Msk instead) */ +#define MCAN_TEST_Msk _U_(0xF0) /**< (MCAN_TEST) Register Mask */ + + +/* -------- MCAN_RWD : (MCAN Offset: 0x14) (R/W 32) RAM Watchdog Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDC:8; /**< bit: 0..7 Watchdog Configuration (read/write) */ + uint32_t WDV:8; /**< bit: 8..15 Watchdog Value (read-only) */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RWD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RWD_OFFSET (0x14) /**< (MCAN_RWD) RAM Watchdog Register Offset */ + +#define MCAN_RWD_WDC_Pos 0 /**< (MCAN_RWD) Watchdog Configuration (read/write) Position */ +#define MCAN_RWD_WDC_Msk (_U_(0xFF) << MCAN_RWD_WDC_Pos) /**< (MCAN_RWD) Watchdog Configuration (read/write) Mask */ +#define MCAN_RWD_WDC(value) (MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)) +#define MCAN_RWD_WDV_Pos 8 /**< (MCAN_RWD) Watchdog Value (read-only) Position */ +#define MCAN_RWD_WDV_Msk (_U_(0xFF) << MCAN_RWD_WDV_Pos) /**< (MCAN_RWD) Watchdog Value (read-only) Mask */ +#define MCAN_RWD_WDV(value) (MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)) +#define MCAN_RWD_MASK _U_(0xFFFF) /**< \deprecated (MCAN_RWD) Register MASK (Use MCAN_RWD_Msk instead) */ +#define MCAN_RWD_Msk _U_(0xFFFF) /**< (MCAN_RWD) Register Mask */ + + +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) (R/W 32) CC Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t INIT:1; /**< bit: 0 Initialization (read/write) */ + uint32_t CCE:1; /**< bit: 1 Configuration Change Enable (read/write, write protection) */ + uint32_t ASM:1; /**< bit: 2 Restricted Operation Mode (read/write, write protection against '1') */ + uint32_t CSA:1; /**< bit: 3 Clock Stop Acknowledge (read-only) */ + uint32_t CSR:1; /**< bit: 4 Clock Stop Request (read/write) */ + uint32_t MON:1; /**< bit: 5 Bus Monitoring Mode (read/write, write protection against '1') */ + uint32_t DAR:1; /**< bit: 6 Disable Automatic Retransmission (read/write, write protection) */ + uint32_t TEST:1; /**< bit: 7 Test Mode Enable (read/write, write protection against '1') */ + uint32_t FDOE:1; /**< bit: 8 CAN FD Operation Enable (read/write, write protection) */ + uint32_t BRSE:1; /**< bit: 9 Bit Rate Switching Enable (read/write, write protection) */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t PXHD:1; /**< bit: 12 Protocol Exception Event Handling (read/write, write protection) */ + uint32_t EFBI:1; /**< bit: 13 Edge Filtering during Bus Integration (read/write, write protection) */ + uint32_t TXP:1; /**< bit: 14 Transmit Pause (read/write, write protection) */ + uint32_t NISO:1; /**< bit: 15 Non-ISO Operation */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_CCCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_CCCR_OFFSET (0x18) /**< (MCAN_CCCR) CC Control Register Offset */ + +#define MCAN_CCCR_INIT_Pos 0 /**< (MCAN_CCCR) Initialization (read/write) Position */ +#define MCAN_CCCR_INIT_Msk (_U_(0x1) << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization (read/write) Mask */ +#define MCAN_CCCR_INIT MCAN_CCCR_INIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_INIT_Msk instead */ +#define MCAN_CCCR_INIT_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_INIT_DISABLED (MCAN_CCCR_INIT_DISABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Normal operation. Position */ +#define MCAN_CCCR_INIT_ENABLED (MCAN_CCCR_INIT_ENABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization is started. Position */ +#define MCAN_CCCR_CCE_Pos 1 /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Position */ +#define MCAN_CCCR_CCE_Msk (_U_(0x1) << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_CCE MCAN_CCCR_CCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CCE_Msk instead */ +#define MCAN_CCCR_CCE_PROTECTED_Val _U_(0x0) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE_Val _U_(0x1) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_CCE_PROTECTED (MCAN_CCCR_CCE_PROTECTED_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. Position */ +#define MCAN_CCCR_CCE_CONFIGURABLE (MCAN_CCCR_CCE_CONFIGURABLE_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). Position */ +#define MCAN_CCCR_ASM_Pos 2 /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_ASM_Msk (_U_(0x1) << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_ASM MCAN_CCCR_ASM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_ASM_Msk instead */ +#define MCAN_CCCR_ASM_NORMAL_Val _U_(0x0) /**< (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED_Val _U_(0x1) /**< (MCAN_CCCR) Restricted Operation mode active. */ +#define MCAN_CCCR_ASM_NORMAL (MCAN_CCCR_ASM_NORMAL_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Normal CAN operation. Position */ +#define MCAN_CCCR_ASM_RESTRICTED (MCAN_CCCR_ASM_RESTRICTED_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation mode active. Position */ +#define MCAN_CCCR_CSA_Pos 3 /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Position */ +#define MCAN_CCCR_CSA_Msk (_U_(0x1) << MCAN_CCCR_CSA_Pos) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Mask */ +#define MCAN_CCCR_CSA MCAN_CCCR_CSA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CSA_Msk instead */ +#define MCAN_CCCR_CSR_Pos 4 /**< (MCAN_CCCR) Clock Stop Request (read/write) Position */ +#define MCAN_CCCR_CSR_Msk (_U_(0x1) << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock Stop Request (read/write) Mask */ +#define MCAN_CCCR_CSR MCAN_CCCR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CSR_Msk instead */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP_Val _U_(0x0) /**< (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP_Val _U_(0x1) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (MCAN_CCCR_CSR_NO_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) No clock stop is requested. Position */ +#define MCAN_CCCR_CSR_CLOCK_STOP (MCAN_CCCR_CSR_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. Position */ +#define MCAN_CCCR_MON_Pos 5 /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_MON_Msk (_U_(0x1) << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_MON MCAN_CCCR_MON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_MON_Msk instead */ +#define MCAN_CCCR_MON_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_MON_DISABLED (MCAN_CCCR_MON_DISABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. Position */ +#define MCAN_CCCR_MON_ENABLED (MCAN_CCCR_MON_ENABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. Position */ +#define MCAN_CCCR_DAR_Pos 6 /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Position */ +#define MCAN_CCCR_DAR_Msk (_U_(0x1) << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Mask */ +#define MCAN_CCCR_DAR MCAN_CCCR_DAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_DAR_Msk instead */ +#define MCAN_CCCR_DAR_AUTO_RETX_Val _U_(0x0) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX_Val _U_(0x1) /**< (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_DAR_AUTO_RETX (MCAN_CCCR_DAR_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. Position */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (MCAN_CCCR_DAR_NO_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission disabled. Position */ +#define MCAN_CCCR_TEST_Pos 7 /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Position */ +#define MCAN_CCCR_TEST_Msk (_U_(0x1) << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_TEST MCAN_CCCR_TEST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_TEST_Msk instead */ +#define MCAN_CCCR_TEST_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_TEST_DISABLED (MCAN_CCCR_TEST_DISABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. Position */ +#define MCAN_CCCR_TEST_ENABLED (MCAN_CCCR_TEST_ENABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. Position */ +#define MCAN_CCCR_FDOE_Pos 8 /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Position */ +#define MCAN_CCCR_FDOE_Msk (_U_(0x1) << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_FDOE MCAN_CCCR_FDOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_FDOE_Msk instead */ +#define MCAN_CCCR_FDOE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) FD operation disabled. */ +#define MCAN_CCCR_FDOE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) FD operation enabled. */ +#define MCAN_CCCR_FDOE_DISABLED (MCAN_CCCR_FDOE_DISABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation disabled. Position */ +#define MCAN_CCCR_FDOE_ENABLED (MCAN_CCCR_FDOE_ENABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation enabled. Position */ +#define MCAN_CCCR_BRSE_Pos 9 /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Position */ +#define MCAN_CCCR_BRSE_Msk (_U_(0x1) << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_BRSE MCAN_CCCR_BRSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_BRSE_Msk instead */ +#define MCAN_CCCR_BRSE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. */ +#define MCAN_CCCR_BRSE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. */ +#define MCAN_CCCR_BRSE_DISABLED (MCAN_CCCR_BRSE_DISABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. Position */ +#define MCAN_CCCR_BRSE_ENABLED (MCAN_CCCR_BRSE_ENABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. Position */ +#define MCAN_CCCR_PXHD_Pos 12 /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Position */ +#define MCAN_CCCR_PXHD_Msk (_U_(0x1) << MCAN_CCCR_PXHD_Pos) /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Mask */ +#define MCAN_CCCR_PXHD MCAN_CCCR_PXHD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_PXHD_Msk instead */ +#define MCAN_CCCR_EFBI_Pos 13 /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Position */ +#define MCAN_CCCR_EFBI_Msk (_U_(0x1) << MCAN_CCCR_EFBI_Pos) /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Mask */ +#define MCAN_CCCR_EFBI MCAN_CCCR_EFBI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_EFBI_Msk instead */ +#define MCAN_CCCR_TXP_Pos 14 /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Position */ +#define MCAN_CCCR_TXP_Msk (_U_(0x1) << MCAN_CCCR_TXP_Pos) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Mask */ +#define MCAN_CCCR_TXP MCAN_CCCR_TXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_TXP_Msk instead */ +#define MCAN_CCCR_NISO_Pos 15 /**< (MCAN_CCCR) Non-ISO Operation Position */ +#define MCAN_CCCR_NISO_Msk (_U_(0x1) << MCAN_CCCR_NISO_Pos) /**< (MCAN_CCCR) Non-ISO Operation Mask */ +#define MCAN_CCCR_NISO MCAN_CCCR_NISO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_NISO_Msk instead */ +#define MCAN_CCCR_MASK _U_(0xF3FF) /**< \deprecated (MCAN_CCCR) Register MASK (Use MCAN_CCCR_Msk instead) */ +#define MCAN_CCCR_Msk _U_(0xF3FF) /**< (MCAN_CCCR) Register Mask */ + + +/* -------- MCAN_NBTP : (MCAN Offset: 0x1c) (R/W 32) Nominal Bit Timing and Prescaler Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NTSEG2:7; /**< bit: 0..6 Nominal Time Segment After Sample Point */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t NTSEG1:8; /**< bit: 8..15 Nominal Time Segment Before Sample Point */ + uint32_t NBRP:9; /**< bit: 16..24 Nominal Bit Rate Prescaler */ + uint32_t NSJW:7; /**< bit: 25..31 Nominal (Re) Synchronization Jump Width */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_NBTP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_NBTP_OFFSET (0x1C) /**< (MCAN_NBTP) Nominal Bit Timing and Prescaler Register Offset */ + +#define MCAN_NBTP_NTSEG2_Pos 0 /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Position */ +#define MCAN_NBTP_NTSEG2_Msk (_U_(0x7F) << MCAN_NBTP_NTSEG2_Pos) /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Mask */ +#define MCAN_NBTP_NTSEG2(value) (MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)) +#define MCAN_NBTP_NTSEG1_Pos 8 /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Position */ +#define MCAN_NBTP_NTSEG1_Msk (_U_(0xFF) << MCAN_NBTP_NTSEG1_Pos) /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Mask */ +#define MCAN_NBTP_NTSEG1(value) (MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)) +#define MCAN_NBTP_NBRP_Pos 16 /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Position */ +#define MCAN_NBTP_NBRP_Msk (_U_(0x1FF) << MCAN_NBTP_NBRP_Pos) /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Mask */ +#define MCAN_NBTP_NBRP(value) (MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)) +#define MCAN_NBTP_NSJW_Pos 25 /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Position */ +#define MCAN_NBTP_NSJW_Msk (_U_(0x7F) << MCAN_NBTP_NSJW_Pos) /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Mask */ +#define MCAN_NBTP_NSJW(value) (MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)) +#define MCAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \deprecated (MCAN_NBTP) Register MASK (Use MCAN_NBTP_Msk instead) */ +#define MCAN_NBTP_Msk _U_(0xFFFFFF7F) /**< (MCAN_NBTP) Register Mask */ + + +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TSS:2; /**< bit: 0..1 Timestamp Select */ + uint32_t :14; /**< bit: 2..15 Reserved */ + uint32_t TCP:4; /**< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TSCC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TSCC_OFFSET (0x20) /**< (MCAN_TSCC) Timestamp Counter Configuration Register Offset */ + +#define MCAN_TSCC_TSS_Pos 0 /**< (MCAN_TSCC) Timestamp Select Position */ +#define MCAN_TSCC_TSS_Msk (_U_(0x3) << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp Select Mask */ +#define MCAN_TSCC_TSS(value) (MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)) +#define MCAN_TSCC_TSS_ALWAYS_0_Val _U_(0x0) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC_Val _U_(0x1) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP_Val _U_(0x2) /**< (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TSS_ALWAYS_0 (MCAN_TSCC_TSS_ALWAYS_0_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define MCAN_TSCC_TSS_TCP_INC (MCAN_TSCC_TSS_TCP_INC_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP Position */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (MCAN_TSCC_TSS_EXT_TIMESTAMP_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) External timestamp counter value used Position */ +#define MCAN_TSCC_TCP_Pos 16 /**< (MCAN_TSCC) Timestamp Counter Prescaler Position */ +#define MCAN_TSCC_TCP_Msk (_U_(0xF) << MCAN_TSCC_TCP_Pos) /**< (MCAN_TSCC) Timestamp Counter Prescaler Mask */ +#define MCAN_TSCC_TCP(value) (MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)) +#define MCAN_TSCC_MASK _U_(0xF0003) /**< \deprecated (MCAN_TSCC) Register MASK (Use MCAN_TSCC_Msk instead) */ +#define MCAN_TSCC_Msk _U_(0xF0003) /**< (MCAN_TSCC) Register Mask */ + + +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) (R/W 32) Timestamp Counter Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TSC:16; /**< bit: 0..15 Timestamp Counter (cleared on write) */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TSCV_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TSCV_OFFSET (0x24) /**< (MCAN_TSCV) Timestamp Counter Value Register Offset */ + +#define MCAN_TSCV_TSC_Pos 0 /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Position */ +#define MCAN_TSCV_TSC_Msk (_U_(0xFFFF) << MCAN_TSCV_TSC_Pos) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Mask */ +#define MCAN_TSCV_TSC(value) (MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)) +#define MCAN_TSCV_MASK _U_(0xFFFF) /**< \deprecated (MCAN_TSCV) Register MASK (Use MCAN_TSCV_Msk instead) */ +#define MCAN_TSCV_Msk _U_(0xFFFF) /**< (MCAN_TSCV) Register Mask */ + + +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) (R/W 32) Timeout Counter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ETOC:1; /**< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /**< bit: 1..2 Timeout Select */ + uint32_t :13; /**< bit: 3..15 Reserved */ + uint32_t TOP:16; /**< bit: 16..31 Timeout Period */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TOCC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TOCC_OFFSET (0x28) /**< (MCAN_TOCC) Timeout Counter Configuration Register Offset */ + +#define MCAN_TOCC_ETOC_Pos 0 /**< (MCAN_TOCC) Enable Timeout Counter Position */ +#define MCAN_TOCC_ETOC_Msk (_U_(0x1) << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Enable Timeout Counter Mask */ +#define MCAN_TOCC_ETOC MCAN_TOCC_ETOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TOCC_ETOC_Msk instead */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT_Val _U_(0x0) /**< (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED_Val _U_(0x1) /**< (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (MCAN_TOCC_ETOC_NO_TIMEOUT_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter disabled. Position */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (MCAN_TOCC_ETOC_TOS_CONTROLLED_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter enabled. Position */ +#define MCAN_TOCC_TOS_Pos 1 /**< (MCAN_TOCC) Timeout Select Position */ +#define MCAN_TOCC_TOS_Msk (_U_(0x3) << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout Select Mask */ +#define MCAN_TOCC_TOS(value) (MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)) +#define MCAN_TOCC_TOS_CONTINUOUS_Val _U_(0x0) /**< (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val _U_(0x1) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val _U_(0x2) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val _U_(0x3) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOS_CONTINUOUS (MCAN_TOCC_TOS_CONTINUOUS_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Continuous operation Position */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO Position */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 Position */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 Position */ +#define MCAN_TOCC_TOP_Pos 16 /**< (MCAN_TOCC) Timeout Period Position */ +#define MCAN_TOCC_TOP_Msk (_U_(0xFFFF) << MCAN_TOCC_TOP_Pos) /**< (MCAN_TOCC) Timeout Period Mask */ +#define MCAN_TOCC_TOP(value) (MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)) +#define MCAN_TOCC_MASK _U_(0xFFFF0007) /**< \deprecated (MCAN_TOCC) Register MASK (Use MCAN_TOCC_Msk instead) */ +#define MCAN_TOCC_Msk _U_(0xFFFF0007) /**< (MCAN_TOCC) Register Mask */ + + +/* -------- MCAN_TOCV : (MCAN Offset: 0x2c) (R/W 32) Timeout Counter Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TOC:16; /**< bit: 0..15 Timeout Counter (cleared on write) */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TOCV_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TOCV_OFFSET (0x2C) /**< (MCAN_TOCV) Timeout Counter Value Register Offset */ + +#define MCAN_TOCV_TOC_Pos 0 /**< (MCAN_TOCV) Timeout Counter (cleared on write) Position */ +#define MCAN_TOCV_TOC_Msk (_U_(0xFFFF) << MCAN_TOCV_TOC_Pos) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Mask */ +#define MCAN_TOCV_TOC(value) (MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)) +#define MCAN_TOCV_MASK _U_(0xFFFF) /**< \deprecated (MCAN_TOCV) Register MASK (Use MCAN_TOCV_Msk instead) */ +#define MCAN_TOCV_Msk _U_(0xFFFF) /**< (MCAN_TOCV) Register Mask */ + + +/* -------- MCAN_ECR : (MCAN Offset: 0x40) (R/ 32) Error Counter Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TEC:8; /**< bit: 0..7 Transmit Error Counter */ + uint32_t REC:7; /**< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /**< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /**< bit: 16..23 CAN Error Logging (cleared on read) */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_ECR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_ECR_OFFSET (0x40) /**< (MCAN_ECR) Error Counter Register Offset */ + +#define MCAN_ECR_TEC_Pos 0 /**< (MCAN_ECR) Transmit Error Counter Position */ +#define MCAN_ECR_TEC_Msk (_U_(0xFF) << MCAN_ECR_TEC_Pos) /**< (MCAN_ECR) Transmit Error Counter Mask */ +#define MCAN_ECR_TEC(value) (MCAN_ECR_TEC_Msk & ((value) << MCAN_ECR_TEC_Pos)) +#define MCAN_ECR_REC_Pos 8 /**< (MCAN_ECR) Receive Error Counter Position */ +#define MCAN_ECR_REC_Msk (_U_(0x7F) << MCAN_ECR_REC_Pos) /**< (MCAN_ECR) Receive Error Counter Mask */ +#define MCAN_ECR_REC(value) (MCAN_ECR_REC_Msk & ((value) << MCAN_ECR_REC_Pos)) +#define MCAN_ECR_RP_Pos 15 /**< (MCAN_ECR) Receive Error Passive Position */ +#define MCAN_ECR_RP_Msk (_U_(0x1) << MCAN_ECR_RP_Pos) /**< (MCAN_ECR) Receive Error Passive Mask */ +#define MCAN_ECR_RP MCAN_ECR_RP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ECR_RP_Msk instead */ +#define MCAN_ECR_CEL_Pos 16 /**< (MCAN_ECR) CAN Error Logging (cleared on read) Position */ +#define MCAN_ECR_CEL_Msk (_U_(0xFF) << MCAN_ECR_CEL_Pos) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Mask */ +#define MCAN_ECR_CEL(value) (MCAN_ECR_CEL_Msk & ((value) << MCAN_ECR_CEL_Pos)) +#define MCAN_ECR_MASK _U_(0xFFFFFF) /**< \deprecated (MCAN_ECR) Register MASK (Use MCAN_ECR_Msk instead) */ +#define MCAN_ECR_Msk _U_(0xFFFFFF) /**< (MCAN_ECR) Register Mask */ + + +/* -------- MCAN_PSR : (MCAN Offset: 0x44) (R/ 32) Protocol Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LEC:3; /**< bit: 0..2 Last Error Code (set to 111 on read) */ + uint32_t ACT:2; /**< bit: 3..4 Activity */ + uint32_t EP:1; /**< bit: 5 Error Passive */ + uint32_t EW:1; /**< bit: 6 Warning Status */ + uint32_t BO:1; /**< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /**< bit: 8..10 Data Phase Last Error Code (set to 111 on read) */ + uint32_t RESI:1; /**< bit: 11 ESI Flag of Last Received CAN FD Message (cleared on read) */ + uint32_t RBRS:1; /**< bit: 12 BRS Flag of Last Received CAN FD Message (cleared on read) */ + uint32_t RFDF:1; /**< bit: 13 Received a CAN FD Message (cleared on read) */ + uint32_t PXE:1; /**< bit: 14 Protocol Exception Event (cleared on read) */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t TDCV:7; /**< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_PSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_PSR_OFFSET (0x44) /**< (MCAN_PSR) Protocol Status Register Offset */ + +#define MCAN_PSR_LEC_Pos 0 /**< (MCAN_PSR) Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_LEC_Msk (_U_(0x7) << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_LEC(value) (MCAN_PSR_LEC_Msk & ((value) << MCAN_PSR_LEC_Pos)) +#define MCAN_PSR_LEC_NO_ERROR_Val _U_(0x0) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR_Val _U_(0x1) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR_Val _U_(0x2) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR_Val _U_(0x3) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR_Val _U_(0x4) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR_Val _U_(0x5) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR_Val _U_(0x6) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE_Val _U_(0x7) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_LEC_NO_ERROR (MCAN_PSR_LEC_NO_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. Position */ +#define MCAN_PSR_LEC_STUFF_ERROR (MCAN_PSR_LEC_STUFF_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Position */ +#define MCAN_PSR_LEC_FORM_ERROR (MCAN_PSR_LEC_FORM_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. Position */ +#define MCAN_PSR_LEC_ACK_ERROR (MCAN_PSR_LEC_ACK_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. Position */ +#define MCAN_PSR_LEC_BIT1_ERROR (MCAN_PSR_LEC_BIT1_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. Position */ +#define MCAN_PSR_LEC_BIT0_ERROR (MCAN_PSR_LEC_BIT0_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). Position */ +#define MCAN_PSR_LEC_CRC_ERROR (MCAN_PSR_LEC_CRC_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. Position */ +#define MCAN_PSR_LEC_NO_CHANGE (MCAN_PSR_LEC_NO_CHANGE_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. Position */ +#define MCAN_PSR_ACT_Pos 3 /**< (MCAN_PSR) Activity Position */ +#define MCAN_PSR_ACT_Msk (_U_(0x3) << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Activity Mask */ +#define MCAN_PSR_ACT(value) (MCAN_PSR_ACT_Msk & ((value) << MCAN_PSR_ACT_Pos)) +#define MCAN_PSR_ACT_SYNCHRONIZING_Val _U_(0x0) /**< (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER_Val _U_(0x2) /**< (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER_Val _U_(0x3) /**< (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_ACT_SYNCHRONIZING (MCAN_PSR_ACT_SYNCHRONIZING_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is synchronizing on CAN communication Position */ +#define MCAN_PSR_ACT_IDLE (MCAN_PSR_ACT_IDLE_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is neither receiver nor transmitter Position */ +#define MCAN_PSR_ACT_RECEIVER (MCAN_PSR_ACT_RECEIVER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as receiver Position */ +#define MCAN_PSR_ACT_TRANSMITTER (MCAN_PSR_ACT_TRANSMITTER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as transmitter Position */ +#define MCAN_PSR_EP_Pos 5 /**< (MCAN_PSR) Error Passive Position */ +#define MCAN_PSR_EP_Msk (_U_(0x1) << MCAN_PSR_EP_Pos) /**< (MCAN_PSR) Error Passive Mask */ +#define MCAN_PSR_EP MCAN_PSR_EP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_EP_Msk instead */ +#define MCAN_PSR_EW_Pos 6 /**< (MCAN_PSR) Warning Status Position */ +#define MCAN_PSR_EW_Msk (_U_(0x1) << MCAN_PSR_EW_Pos) /**< (MCAN_PSR) Warning Status Mask */ +#define MCAN_PSR_EW MCAN_PSR_EW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_EW_Msk instead */ +#define MCAN_PSR_BO_Pos 7 /**< (MCAN_PSR) Bus_Off Status Position */ +#define MCAN_PSR_BO_Msk (_U_(0x1) << MCAN_PSR_BO_Pos) /**< (MCAN_PSR) Bus_Off Status Mask */ +#define MCAN_PSR_BO MCAN_PSR_BO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_BO_Msk instead */ +#define MCAN_PSR_DLEC_Pos 8 /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_DLEC_Msk (_U_(0x7) << MCAN_PSR_DLEC_Pos) /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_DLEC(value) (MCAN_PSR_DLEC_Msk & ((value) << MCAN_PSR_DLEC_Pos)) +#define MCAN_PSR_RESI_Pos 11 /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RESI_Msk (_U_(0x1) << MCAN_PSR_RESI_Pos) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RESI MCAN_PSR_RESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RESI_Msk instead */ +#define MCAN_PSR_RBRS_Pos 12 /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RBRS_Msk (_U_(0x1) << MCAN_PSR_RBRS_Pos) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RBRS MCAN_PSR_RBRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RBRS_Msk instead */ +#define MCAN_PSR_RFDF_Pos 13 /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RFDF_Msk (_U_(0x1) << MCAN_PSR_RFDF_Pos) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RFDF MCAN_PSR_RFDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RFDF_Msk instead */ +#define MCAN_PSR_PXE_Pos 14 /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Position */ +#define MCAN_PSR_PXE_Msk (_U_(0x1) << MCAN_PSR_PXE_Pos) /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Mask */ +#define MCAN_PSR_PXE MCAN_PSR_PXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_PXE_Msk instead */ +#define MCAN_PSR_TDCV_Pos 16 /**< (MCAN_PSR) Transmitter Delay Compensation Value Position */ +#define MCAN_PSR_TDCV_Msk (_U_(0x7F) << MCAN_PSR_TDCV_Pos) /**< (MCAN_PSR) Transmitter Delay Compensation Value Mask */ +#define MCAN_PSR_TDCV(value) (MCAN_PSR_TDCV_Msk & ((value) << MCAN_PSR_TDCV_Pos)) +#define MCAN_PSR_MASK _U_(0x7F7FFF) /**< \deprecated (MCAN_PSR) Register MASK (Use MCAN_PSR_Msk instead) */ +#define MCAN_PSR_Msk _U_(0x7F7FFF) /**< (MCAN_PSR) Register Mask */ + + +/* -------- MCAN_TDCR : (MCAN Offset: 0x48) (R/W 32) Transmit Delay Compensation Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TDCF:7; /**< bit: 0..6 Transmitter Delay Compensation Filter */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t TDCO:7; /**< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TDCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TDCR_OFFSET (0x48) /**< (MCAN_TDCR) Transmit Delay Compensation Register Offset */ + +#define MCAN_TDCR_TDCF_Pos 0 /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Position */ +#define MCAN_TDCR_TDCF_Msk (_U_(0x7F) << MCAN_TDCR_TDCF_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Mask */ +#define MCAN_TDCR_TDCF(value) (MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)) +#define MCAN_TDCR_TDCO_Pos 8 /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define MCAN_TDCR_TDCO_Msk (_U_(0x7F) << MCAN_TDCR_TDCO_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define MCAN_TDCR_TDCO(value) (MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)) +#define MCAN_TDCR_MASK _U_(0x7F7F) /**< \deprecated (MCAN_TDCR) Register MASK (Use MCAN_TDCR_Msk instead) */ +#define MCAN_TDCR_Msk _U_(0x7F7F) /**< (MCAN_TDCR) Register Mask */ + + +/* -------- MCAN_IR : (MCAN Offset: 0x50) (R/W 32) Interrupt Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RF0N:1; /**< bit: 0 Receive FIFO 0 New Message */ + uint32_t RF0W:1; /**< bit: 1 Receive FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /**< bit: 2 Receive FIFO 0 Full */ + uint32_t RF0L:1; /**< bit: 3 Receive FIFO 0 Message Lost */ + uint32_t RF1N:1; /**< bit: 4 Receive FIFO 1 New Message */ + uint32_t RF1W:1; /**< bit: 5 Receive FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /**< bit: 6 Receive FIFO 1 Full */ + uint32_t RF1L:1; /**< bit: 7 Receive FIFO 1 Message Lost */ + uint32_t HPM:1; /**< bit: 8 High Priority Message */ + uint32_t TC:1; /**< bit: 9 Transmission Completed */ + uint32_t TCF:1; /**< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /**< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /**< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /**< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /**< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /**< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /**< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /**< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /**< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /**< bit: 19 Message stored to Dedicated Receive Buffer */ + uint32_t :2; /**< bit: 20..21 Reserved */ + uint32_t ELO:1; /**< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /**< bit: 23 Error Passive */ + uint32_t EW:1; /**< bit: 24 Warning Status */ + uint32_t BO:1; /**< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /**< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /**< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /**< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /**< bit: 29 Access to Reserved Address */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_IR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_IR_OFFSET (0x50) /**< (MCAN_IR) Interrupt Register Offset */ + +#define MCAN_IR_RF0N_Pos 0 /**< (MCAN_IR) Receive FIFO 0 New Message Position */ +#define MCAN_IR_RF0N_Msk (_U_(0x1) << MCAN_IR_RF0N_Pos) /**< (MCAN_IR) Receive FIFO 0 New Message Mask */ +#define MCAN_IR_RF0N MCAN_IR_RF0N_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0N_Msk instead */ +#define MCAN_IR_RF0W_Pos 1 /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Position */ +#define MCAN_IR_RF0W_Msk (_U_(0x1) << MCAN_IR_RF0W_Pos) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Mask */ +#define MCAN_IR_RF0W MCAN_IR_RF0W_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0W_Msk instead */ +#define MCAN_IR_RF0F_Pos 2 /**< (MCAN_IR) Receive FIFO 0 Full Position */ +#define MCAN_IR_RF0F_Msk (_U_(0x1) << MCAN_IR_RF0F_Pos) /**< (MCAN_IR) Receive FIFO 0 Full Mask */ +#define MCAN_IR_RF0F MCAN_IR_RF0F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0F_Msk instead */ +#define MCAN_IR_RF0L_Pos 3 /**< (MCAN_IR) Receive FIFO 0 Message Lost Position */ +#define MCAN_IR_RF0L_Msk (_U_(0x1) << MCAN_IR_RF0L_Pos) /**< (MCAN_IR) Receive FIFO 0 Message Lost Mask */ +#define MCAN_IR_RF0L MCAN_IR_RF0L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0L_Msk instead */ +#define MCAN_IR_RF1N_Pos 4 /**< (MCAN_IR) Receive FIFO 1 New Message Position */ +#define MCAN_IR_RF1N_Msk (_U_(0x1) << MCAN_IR_RF1N_Pos) /**< (MCAN_IR) Receive FIFO 1 New Message Mask */ +#define MCAN_IR_RF1N MCAN_IR_RF1N_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1N_Msk instead */ +#define MCAN_IR_RF1W_Pos 5 /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Position */ +#define MCAN_IR_RF1W_Msk (_U_(0x1) << MCAN_IR_RF1W_Pos) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Mask */ +#define MCAN_IR_RF1W MCAN_IR_RF1W_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1W_Msk instead */ +#define MCAN_IR_RF1F_Pos 6 /**< (MCAN_IR) Receive FIFO 1 Full Position */ +#define MCAN_IR_RF1F_Msk (_U_(0x1) << MCAN_IR_RF1F_Pos) /**< (MCAN_IR) Receive FIFO 1 Full Mask */ +#define MCAN_IR_RF1F MCAN_IR_RF1F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1F_Msk instead */ +#define MCAN_IR_RF1L_Pos 7 /**< (MCAN_IR) Receive FIFO 1 Message Lost Position */ +#define MCAN_IR_RF1L_Msk (_U_(0x1) << MCAN_IR_RF1L_Pos) /**< (MCAN_IR) Receive FIFO 1 Message Lost Mask */ +#define MCAN_IR_RF1L MCAN_IR_RF1L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1L_Msk instead */ +#define MCAN_IR_HPM_Pos 8 /**< (MCAN_IR) High Priority Message Position */ +#define MCAN_IR_HPM_Msk (_U_(0x1) << MCAN_IR_HPM_Pos) /**< (MCAN_IR) High Priority Message Mask */ +#define MCAN_IR_HPM MCAN_IR_HPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_HPM_Msk instead */ +#define MCAN_IR_TC_Pos 9 /**< (MCAN_IR) Transmission Completed Position */ +#define MCAN_IR_TC_Msk (_U_(0x1) << MCAN_IR_TC_Pos) /**< (MCAN_IR) Transmission Completed Mask */ +#define MCAN_IR_TC MCAN_IR_TC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TC_Msk instead */ +#define MCAN_IR_TCF_Pos 10 /**< (MCAN_IR) Transmission Cancellation Finished Position */ +#define MCAN_IR_TCF_Msk (_U_(0x1) << MCAN_IR_TCF_Pos) /**< (MCAN_IR) Transmission Cancellation Finished Mask */ +#define MCAN_IR_TCF MCAN_IR_TCF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TCF_Msk instead */ +#define MCAN_IR_TFE_Pos 11 /**< (MCAN_IR) Tx FIFO Empty Position */ +#define MCAN_IR_TFE_Msk (_U_(0x1) << MCAN_IR_TFE_Pos) /**< (MCAN_IR) Tx FIFO Empty Mask */ +#define MCAN_IR_TFE MCAN_IR_TFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TFE_Msk instead */ +#define MCAN_IR_TEFN_Pos 12 /**< (MCAN_IR) Tx Event FIFO New Entry Position */ +#define MCAN_IR_TEFN_Msk (_U_(0x1) << MCAN_IR_TEFN_Pos) /**< (MCAN_IR) Tx Event FIFO New Entry Mask */ +#define MCAN_IR_TEFN MCAN_IR_TEFN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFN_Msk instead */ +#define MCAN_IR_TEFW_Pos 13 /**< (MCAN_IR) Tx Event FIFO Watermark Reached Position */ +#define MCAN_IR_TEFW_Msk (_U_(0x1) << MCAN_IR_TEFW_Pos) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define MCAN_IR_TEFW MCAN_IR_TEFW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFW_Msk instead */ +#define MCAN_IR_TEFF_Pos 14 /**< (MCAN_IR) Tx Event FIFO Full Position */ +#define MCAN_IR_TEFF_Msk (_U_(0x1) << MCAN_IR_TEFF_Pos) /**< (MCAN_IR) Tx Event FIFO Full Mask */ +#define MCAN_IR_TEFF MCAN_IR_TEFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFF_Msk instead */ +#define MCAN_IR_TEFL_Pos 15 /**< (MCAN_IR) Tx Event FIFO Element Lost Position */ +#define MCAN_IR_TEFL_Msk (_U_(0x1) << MCAN_IR_TEFL_Pos) /**< (MCAN_IR) Tx Event FIFO Element Lost Mask */ +#define MCAN_IR_TEFL MCAN_IR_TEFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFL_Msk instead */ +#define MCAN_IR_TSW_Pos 16 /**< (MCAN_IR) Timestamp Wraparound Position */ +#define MCAN_IR_TSW_Msk (_U_(0x1) << MCAN_IR_TSW_Pos) /**< (MCAN_IR) Timestamp Wraparound Mask */ +#define MCAN_IR_TSW MCAN_IR_TSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TSW_Msk instead */ +#define MCAN_IR_MRAF_Pos 17 /**< (MCAN_IR) Message RAM Access Failure Position */ +#define MCAN_IR_MRAF_Msk (_U_(0x1) << MCAN_IR_MRAF_Pos) /**< (MCAN_IR) Message RAM Access Failure Mask */ +#define MCAN_IR_MRAF MCAN_IR_MRAF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_MRAF_Msk instead */ +#define MCAN_IR_TOO_Pos 18 /**< (MCAN_IR) Timeout Occurred Position */ +#define MCAN_IR_TOO_Msk (_U_(0x1) << MCAN_IR_TOO_Pos) /**< (MCAN_IR) Timeout Occurred Mask */ +#define MCAN_IR_TOO MCAN_IR_TOO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TOO_Msk instead */ +#define MCAN_IR_DRX_Pos 19 /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Position */ +#define MCAN_IR_DRX_Msk (_U_(0x1) << MCAN_IR_DRX_Pos) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Mask */ +#define MCAN_IR_DRX MCAN_IR_DRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_DRX_Msk instead */ +#define MCAN_IR_ELO_Pos 22 /**< (MCAN_IR) Error Logging Overflow Position */ +#define MCAN_IR_ELO_Msk (_U_(0x1) << MCAN_IR_ELO_Pos) /**< (MCAN_IR) Error Logging Overflow Mask */ +#define MCAN_IR_ELO MCAN_IR_ELO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_ELO_Msk instead */ +#define MCAN_IR_EP_Pos 23 /**< (MCAN_IR) Error Passive Position */ +#define MCAN_IR_EP_Msk (_U_(0x1) << MCAN_IR_EP_Pos) /**< (MCAN_IR) Error Passive Mask */ +#define MCAN_IR_EP MCAN_IR_EP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_EP_Msk instead */ +#define MCAN_IR_EW_Pos 24 /**< (MCAN_IR) Warning Status Position */ +#define MCAN_IR_EW_Msk (_U_(0x1) << MCAN_IR_EW_Pos) /**< (MCAN_IR) Warning Status Mask */ +#define MCAN_IR_EW MCAN_IR_EW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_EW_Msk instead */ +#define MCAN_IR_BO_Pos 25 /**< (MCAN_IR) Bus_Off Status Position */ +#define MCAN_IR_BO_Msk (_U_(0x1) << MCAN_IR_BO_Pos) /**< (MCAN_IR) Bus_Off Status Mask */ +#define MCAN_IR_BO MCAN_IR_BO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_BO_Msk instead */ +#define MCAN_IR_WDI_Pos 26 /**< (MCAN_IR) Watchdog Interrupt Position */ +#define MCAN_IR_WDI_Msk (_U_(0x1) << MCAN_IR_WDI_Pos) /**< (MCAN_IR) Watchdog Interrupt Mask */ +#define MCAN_IR_WDI MCAN_IR_WDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_WDI_Msk instead */ +#define MCAN_IR_PEA_Pos 27 /**< (MCAN_IR) Protocol Error in Arbitration Phase Position */ +#define MCAN_IR_PEA_Msk (_U_(0x1) << MCAN_IR_PEA_Pos) /**< (MCAN_IR) Protocol Error in Arbitration Phase Mask */ +#define MCAN_IR_PEA MCAN_IR_PEA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_PEA_Msk instead */ +#define MCAN_IR_PED_Pos 28 /**< (MCAN_IR) Protocol Error in Data Phase Position */ +#define MCAN_IR_PED_Msk (_U_(0x1) << MCAN_IR_PED_Pos) /**< (MCAN_IR) Protocol Error in Data Phase Mask */ +#define MCAN_IR_PED MCAN_IR_PED_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_PED_Msk instead */ +#define MCAN_IR_ARA_Pos 29 /**< (MCAN_IR) Access to Reserved Address Position */ +#define MCAN_IR_ARA_Msk (_U_(0x1) << MCAN_IR_ARA_Pos) /**< (MCAN_IR) Access to Reserved Address Mask */ +#define MCAN_IR_ARA MCAN_IR_ARA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_ARA_Msk instead */ +#define MCAN_IR_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_IR) Register MASK (Use MCAN_IR_Msk instead) */ +#define MCAN_IR_Msk _U_(0x3FCFFFFF) /**< (MCAN_IR) Register Mask */ + + +/* -------- MCAN_IE : (MCAN Offset: 0x54) (R/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RF0NE:1; /**< bit: 0 Receive FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /**< bit: 1 Receive FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /**< bit: 2 Receive FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /**< bit: 3 Receive FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /**< bit: 4 Receive FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /**< bit: 5 Receive FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /**< bit: 6 Receive FIFO 1 Full Interrupt Enable */ + uint32_t RF1LE:1; /**< bit: 7 Receive FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /**< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /**< bit: 9 Transmission Completed Interrupt Enable */ + uint32_t TCFE:1; /**< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /**< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /**< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /**< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /**< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /**< bit: 15 Tx Event FIFO Event Lost Interrupt Enable */ + uint32_t TSWE:1; /**< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /**< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /**< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /**< bit: 19 Message stored to Dedicated Receive Buffer Interrupt Enable */ + uint32_t :2; /**< bit: 20..21 Reserved */ + uint32_t ELOE:1; /**< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /**< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /**< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /**< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /**< bit: 26 Watchdog Interrupt Enable */ + uint32_t PEAE:1; /**< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /**< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /**< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_IE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_IE_OFFSET (0x54) /**< (MCAN_IE) Interrupt Enable Register Offset */ + +#define MCAN_IE_RF0NE_Pos 0 /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Position */ +#define MCAN_IE_RF0NE_Msk (_U_(0x1) << MCAN_IE_RF0NE_Pos) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF0NE MCAN_IE_RF0NE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0NE_Msk instead */ +#define MCAN_IE_RF0WE_Pos 1 /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF0WE_Msk (_U_(0x1) << MCAN_IE_RF0WE_Pos) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF0WE MCAN_IE_RF0WE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0WE_Msk instead */ +#define MCAN_IE_RF0FE_Pos 2 /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Position */ +#define MCAN_IE_RF0FE_Msk (_U_(0x1) << MCAN_IE_RF0FE_Pos) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Mask */ +#define MCAN_IE_RF0FE MCAN_IE_RF0FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0FE_Msk instead */ +#define MCAN_IE_RF0LE_Pos 3 /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF0LE_Msk (_U_(0x1) << MCAN_IE_RF0LE_Pos) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF0LE MCAN_IE_RF0LE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0LE_Msk instead */ +#define MCAN_IE_RF1NE_Pos 4 /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Position */ +#define MCAN_IE_RF1NE_Msk (_U_(0x1) << MCAN_IE_RF1NE_Pos) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF1NE MCAN_IE_RF1NE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1NE_Msk instead */ +#define MCAN_IE_RF1WE_Pos 5 /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF1WE_Msk (_U_(0x1) << MCAN_IE_RF1WE_Pos) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF1WE MCAN_IE_RF1WE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1WE_Msk instead */ +#define MCAN_IE_RF1FE_Pos 6 /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Position */ +#define MCAN_IE_RF1FE_Msk (_U_(0x1) << MCAN_IE_RF1FE_Pos) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Mask */ +#define MCAN_IE_RF1FE MCAN_IE_RF1FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1FE_Msk instead */ +#define MCAN_IE_RF1LE_Pos 7 /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF1LE_Msk (_U_(0x1) << MCAN_IE_RF1LE_Pos) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF1LE MCAN_IE_RF1LE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1LE_Msk instead */ +#define MCAN_IE_HPME_Pos 8 /**< (MCAN_IE) High Priority Message Interrupt Enable Position */ +#define MCAN_IE_HPME_Msk (_U_(0x1) << MCAN_IE_HPME_Pos) /**< (MCAN_IE) High Priority Message Interrupt Enable Mask */ +#define MCAN_IE_HPME MCAN_IE_HPME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_HPME_Msk instead */ +#define MCAN_IE_TCE_Pos 9 /**< (MCAN_IE) Transmission Completed Interrupt Enable Position */ +#define MCAN_IE_TCE_Msk (_U_(0x1) << MCAN_IE_TCE_Pos) /**< (MCAN_IE) Transmission Completed Interrupt Enable Mask */ +#define MCAN_IE_TCE MCAN_IE_TCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TCE_Msk instead */ +#define MCAN_IE_TCFE_Pos 10 /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define MCAN_IE_TCFE_Msk (_U_(0x1) << MCAN_IE_TCFE_Pos) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define MCAN_IE_TCFE MCAN_IE_TCFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TCFE_Msk instead */ +#define MCAN_IE_TFEE_Pos 11 /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define MCAN_IE_TFEE_Msk (_U_(0x1) << MCAN_IE_TFEE_Pos) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define MCAN_IE_TFEE MCAN_IE_TFEE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TFEE_Msk instead */ +#define MCAN_IE_TEFNE_Pos 12 /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define MCAN_IE_TEFNE_Msk (_U_(0x1) << MCAN_IE_TEFNE_Pos) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define MCAN_IE_TEFNE MCAN_IE_TEFNE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFNE_Msk instead */ +#define MCAN_IE_TEFWE_Pos 13 /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_TEFWE_Msk (_U_(0x1) << MCAN_IE_TEFWE_Pos) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_TEFWE MCAN_IE_TEFWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFWE_Msk instead */ +#define MCAN_IE_TEFFE_Pos 14 /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define MCAN_IE_TEFFE_Msk (_U_(0x1) << MCAN_IE_TEFFE_Pos) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define MCAN_IE_TEFFE MCAN_IE_TEFFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFFE_Msk instead */ +#define MCAN_IE_TEFLE_Pos 15 /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Position */ +#define MCAN_IE_TEFLE_Msk (_U_(0x1) << MCAN_IE_TEFLE_Pos) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Mask */ +#define MCAN_IE_TEFLE MCAN_IE_TEFLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFLE_Msk instead */ +#define MCAN_IE_TSWE_Pos 16 /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define MCAN_IE_TSWE_Msk (_U_(0x1) << MCAN_IE_TSWE_Pos) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define MCAN_IE_TSWE MCAN_IE_TSWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TSWE_Msk instead */ +#define MCAN_IE_MRAFE_Pos 17 /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define MCAN_IE_MRAFE_Msk (_U_(0x1) << MCAN_IE_MRAFE_Pos) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define MCAN_IE_MRAFE MCAN_IE_MRAFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_MRAFE_Msk instead */ +#define MCAN_IE_TOOE_Pos 18 /**< (MCAN_IE) Timeout Occurred Interrupt Enable Position */ +#define MCAN_IE_TOOE_Msk (_U_(0x1) << MCAN_IE_TOOE_Pos) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define MCAN_IE_TOOE MCAN_IE_TOOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TOOE_Msk instead */ +#define MCAN_IE_DRXE_Pos 19 /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Position */ +#define MCAN_IE_DRXE_Msk (_U_(0x1) << MCAN_IE_DRXE_Pos) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Mask */ +#define MCAN_IE_DRXE MCAN_IE_DRXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_DRXE_Msk instead */ +#define MCAN_IE_ELOE_Pos 22 /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define MCAN_IE_ELOE_Msk (_U_(0x1) << MCAN_IE_ELOE_Pos) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define MCAN_IE_ELOE MCAN_IE_ELOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_ELOE_Msk instead */ +#define MCAN_IE_EPE_Pos 23 /**< (MCAN_IE) Error Passive Interrupt Enable Position */ +#define MCAN_IE_EPE_Msk (_U_(0x1) << MCAN_IE_EPE_Pos) /**< (MCAN_IE) Error Passive Interrupt Enable Mask */ +#define MCAN_IE_EPE MCAN_IE_EPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_EPE_Msk instead */ +#define MCAN_IE_EWE_Pos 24 /**< (MCAN_IE) Warning Status Interrupt Enable Position */ +#define MCAN_IE_EWE_Msk (_U_(0x1) << MCAN_IE_EWE_Pos) /**< (MCAN_IE) Warning Status Interrupt Enable Mask */ +#define MCAN_IE_EWE MCAN_IE_EWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_EWE_Msk instead */ +#define MCAN_IE_BOE_Pos 25 /**< (MCAN_IE) Bus_Off Status Interrupt Enable Position */ +#define MCAN_IE_BOE_Msk (_U_(0x1) << MCAN_IE_BOE_Pos) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define MCAN_IE_BOE MCAN_IE_BOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_BOE_Msk instead */ +#define MCAN_IE_WDIE_Pos 26 /**< (MCAN_IE) Watchdog Interrupt Enable Position */ +#define MCAN_IE_WDIE_Msk (_U_(0x1) << MCAN_IE_WDIE_Pos) /**< (MCAN_IE) Watchdog Interrupt Enable Mask */ +#define MCAN_IE_WDIE MCAN_IE_WDIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_WDIE_Msk instead */ +#define MCAN_IE_PEAE_Pos 27 /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define MCAN_IE_PEAE_Msk (_U_(0x1) << MCAN_IE_PEAE_Pos) /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define MCAN_IE_PEAE MCAN_IE_PEAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_PEAE_Msk instead */ +#define MCAN_IE_PEDE_Pos 28 /**< (MCAN_IE) Protocol Error in Data Phase Enable Position */ +#define MCAN_IE_PEDE_Msk (_U_(0x1) << MCAN_IE_PEDE_Pos) /**< (MCAN_IE) Protocol Error in Data Phase Enable Mask */ +#define MCAN_IE_PEDE MCAN_IE_PEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_PEDE_Msk instead */ +#define MCAN_IE_ARAE_Pos 29 /**< (MCAN_IE) Access to Reserved Address Enable Position */ +#define MCAN_IE_ARAE_Msk (_U_(0x1) << MCAN_IE_ARAE_Pos) /**< (MCAN_IE) Access to Reserved Address Enable Mask */ +#define MCAN_IE_ARAE MCAN_IE_ARAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_ARAE_Msk instead */ +#define MCAN_IE_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_IE) Register MASK (Use MCAN_IE_Msk instead) */ +#define MCAN_IE_Msk _U_(0x3FCFFFFF) /**< (MCAN_IE) Register Mask */ + + +/* -------- MCAN_ILS : (MCAN Offset: 0x58) (R/W 32) Interrupt Line Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RF0NL:1; /**< bit: 0 Receive FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /**< bit: 1 Receive FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /**< bit: 2 Receive FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /**< bit: 3 Receive FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /**< bit: 4 Receive FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /**< bit: 5 Receive FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /**< bit: 6 Receive FIFO 1 Full Interrupt Line */ + uint32_t RF1LL:1; /**< bit: 7 Receive FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /**< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /**< bit: 9 Transmission Completed Interrupt Line */ + uint32_t TCFL:1; /**< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /**< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /**< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /**< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /**< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /**< bit: 15 Tx Event FIFO Event Lost Interrupt Line */ + uint32_t TSWL:1; /**< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /**< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /**< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /**< bit: 19 Message stored to Dedicated Receive Buffer Interrupt Line */ + uint32_t :2; /**< bit: 20..21 Reserved */ + uint32_t ELOL:1; /**< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /**< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /**< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /**< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /**< bit: 26 Watchdog Interrupt Line */ + uint32_t PEAL:1; /**< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /**< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /**< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_ILS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_ILS_OFFSET (0x58) /**< (MCAN_ILS) Interrupt Line Select Register Offset */ + +#define MCAN_ILS_RF0NL_Pos 0 /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Position */ +#define MCAN_ILS_RF0NL_Msk (_U_(0x1) << MCAN_ILS_RF0NL_Pos) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF0NL MCAN_ILS_RF0NL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0NL_Msk instead */ +#define MCAN_ILS_RF0WL_Pos 1 /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF0WL_Msk (_U_(0x1) << MCAN_ILS_RF0WL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF0WL MCAN_ILS_RF0WL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0WL_Msk instead */ +#define MCAN_ILS_RF0FL_Pos 2 /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Position */ +#define MCAN_ILS_RF0FL_Msk (_U_(0x1) << MCAN_ILS_RF0FL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Mask */ +#define MCAN_ILS_RF0FL MCAN_ILS_RF0FL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0FL_Msk instead */ +#define MCAN_ILS_RF0LL_Pos 3 /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF0LL_Msk (_U_(0x1) << MCAN_ILS_RF0LL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF0LL MCAN_ILS_RF0LL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0LL_Msk instead */ +#define MCAN_ILS_RF1NL_Pos 4 /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Position */ +#define MCAN_ILS_RF1NL_Msk (_U_(0x1) << MCAN_ILS_RF1NL_Pos) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF1NL MCAN_ILS_RF1NL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1NL_Msk instead */ +#define MCAN_ILS_RF1WL_Pos 5 /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF1WL_Msk (_U_(0x1) << MCAN_ILS_RF1WL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF1WL MCAN_ILS_RF1WL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1WL_Msk instead */ +#define MCAN_ILS_RF1FL_Pos 6 /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Position */ +#define MCAN_ILS_RF1FL_Msk (_U_(0x1) << MCAN_ILS_RF1FL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Mask */ +#define MCAN_ILS_RF1FL MCAN_ILS_RF1FL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1FL_Msk instead */ +#define MCAN_ILS_RF1LL_Pos 7 /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF1LL_Msk (_U_(0x1) << MCAN_ILS_RF1LL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF1LL MCAN_ILS_RF1LL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1LL_Msk instead */ +#define MCAN_ILS_HPML_Pos 8 /**< (MCAN_ILS) High Priority Message Interrupt Line Position */ +#define MCAN_ILS_HPML_Msk (_U_(0x1) << MCAN_ILS_HPML_Pos) /**< (MCAN_ILS) High Priority Message Interrupt Line Mask */ +#define MCAN_ILS_HPML MCAN_ILS_HPML_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_HPML_Msk instead */ +#define MCAN_ILS_TCL_Pos 9 /**< (MCAN_ILS) Transmission Completed Interrupt Line Position */ +#define MCAN_ILS_TCL_Msk (_U_(0x1) << MCAN_ILS_TCL_Pos) /**< (MCAN_ILS) Transmission Completed Interrupt Line Mask */ +#define MCAN_ILS_TCL MCAN_ILS_TCL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TCL_Msk instead */ +#define MCAN_ILS_TCFL_Pos 10 /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define MCAN_ILS_TCFL_Msk (_U_(0x1) << MCAN_ILS_TCFL_Pos) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define MCAN_ILS_TCFL MCAN_ILS_TCFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TCFL_Msk instead */ +#define MCAN_ILS_TFEL_Pos 11 /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define MCAN_ILS_TFEL_Msk (_U_(0x1) << MCAN_ILS_TFEL_Pos) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define MCAN_ILS_TFEL MCAN_ILS_TFEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TFEL_Msk instead */ +#define MCAN_ILS_TEFNL_Pos 12 /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define MCAN_ILS_TEFNL_Msk (_U_(0x1) << MCAN_ILS_TEFNL_Pos) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define MCAN_ILS_TEFNL MCAN_ILS_TEFNL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFNL_Msk instead */ +#define MCAN_ILS_TEFWL_Pos 13 /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_TEFWL_Msk (_U_(0x1) << MCAN_ILS_TEFWL_Pos) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_TEFWL MCAN_ILS_TEFWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFWL_Msk instead */ +#define MCAN_ILS_TEFFL_Pos 14 /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define MCAN_ILS_TEFFL_Msk (_U_(0x1) << MCAN_ILS_TEFFL_Pos) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define MCAN_ILS_TEFFL MCAN_ILS_TEFFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFFL_Msk instead */ +#define MCAN_ILS_TEFLL_Pos 15 /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Position */ +#define MCAN_ILS_TEFLL_Msk (_U_(0x1) << MCAN_ILS_TEFLL_Pos) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Mask */ +#define MCAN_ILS_TEFLL MCAN_ILS_TEFLL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFLL_Msk instead */ +#define MCAN_ILS_TSWL_Pos 16 /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define MCAN_ILS_TSWL_Msk (_U_(0x1) << MCAN_ILS_TSWL_Pos) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define MCAN_ILS_TSWL MCAN_ILS_TSWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TSWL_Msk instead */ +#define MCAN_ILS_MRAFL_Pos 17 /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define MCAN_ILS_MRAFL_Msk (_U_(0x1) << MCAN_ILS_MRAFL_Pos) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define MCAN_ILS_MRAFL MCAN_ILS_MRAFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_MRAFL_Msk instead */ +#define MCAN_ILS_TOOL_Pos 18 /**< (MCAN_ILS) Timeout Occurred Interrupt Line Position */ +#define MCAN_ILS_TOOL_Msk (_U_(0x1) << MCAN_ILS_TOOL_Pos) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define MCAN_ILS_TOOL MCAN_ILS_TOOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TOOL_Msk instead */ +#define MCAN_ILS_DRXL_Pos 19 /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Position */ +#define MCAN_ILS_DRXL_Msk (_U_(0x1) << MCAN_ILS_DRXL_Pos) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Mask */ +#define MCAN_ILS_DRXL MCAN_ILS_DRXL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_DRXL_Msk instead */ +#define MCAN_ILS_ELOL_Pos 22 /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define MCAN_ILS_ELOL_Msk (_U_(0x1) << MCAN_ILS_ELOL_Pos) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define MCAN_ILS_ELOL MCAN_ILS_ELOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_ELOL_Msk instead */ +#define MCAN_ILS_EPL_Pos 23 /**< (MCAN_ILS) Error Passive Interrupt Line Position */ +#define MCAN_ILS_EPL_Msk (_U_(0x1) << MCAN_ILS_EPL_Pos) /**< (MCAN_ILS) Error Passive Interrupt Line Mask */ +#define MCAN_ILS_EPL MCAN_ILS_EPL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_EPL_Msk instead */ +#define MCAN_ILS_EWL_Pos 24 /**< (MCAN_ILS) Warning Status Interrupt Line Position */ +#define MCAN_ILS_EWL_Msk (_U_(0x1) << MCAN_ILS_EWL_Pos) /**< (MCAN_ILS) Warning Status Interrupt Line Mask */ +#define MCAN_ILS_EWL MCAN_ILS_EWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_EWL_Msk instead */ +#define MCAN_ILS_BOL_Pos 25 /**< (MCAN_ILS) Bus_Off Status Interrupt Line Position */ +#define MCAN_ILS_BOL_Msk (_U_(0x1) << MCAN_ILS_BOL_Pos) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define MCAN_ILS_BOL MCAN_ILS_BOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_BOL_Msk instead */ +#define MCAN_ILS_WDIL_Pos 26 /**< (MCAN_ILS) Watchdog Interrupt Line Position */ +#define MCAN_ILS_WDIL_Msk (_U_(0x1) << MCAN_ILS_WDIL_Pos) /**< (MCAN_ILS) Watchdog Interrupt Line Mask */ +#define MCAN_ILS_WDIL MCAN_ILS_WDIL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_WDIL_Msk instead */ +#define MCAN_ILS_PEAL_Pos 27 /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define MCAN_ILS_PEAL_Msk (_U_(0x1) << MCAN_ILS_PEAL_Pos) /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define MCAN_ILS_PEAL MCAN_ILS_PEAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_PEAL_Msk instead */ +#define MCAN_ILS_PEDL_Pos 28 /**< (MCAN_ILS) Protocol Error in Data Phase Line Position */ +#define MCAN_ILS_PEDL_Msk (_U_(0x1) << MCAN_ILS_PEDL_Pos) /**< (MCAN_ILS) Protocol Error in Data Phase Line Mask */ +#define MCAN_ILS_PEDL MCAN_ILS_PEDL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_PEDL_Msk instead */ +#define MCAN_ILS_ARAL_Pos 29 /**< (MCAN_ILS) Access to Reserved Address Line Position */ +#define MCAN_ILS_ARAL_Msk (_U_(0x1) << MCAN_ILS_ARAL_Pos) /**< (MCAN_ILS) Access to Reserved Address Line Mask */ +#define MCAN_ILS_ARAL MCAN_ILS_ARAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_ARAL_Msk instead */ +#define MCAN_ILS_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_ILS) Register MASK (Use MCAN_ILS_Msk instead) */ +#define MCAN_ILS_Msk _U_(0x3FCFFFFF) /**< (MCAN_ILS) Register Mask */ + + +/* -------- MCAN_ILE : (MCAN Offset: 0x5c) (R/W 32) Interrupt Line Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EINT0:1; /**< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /**< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EINT:2; /**< bit: 0..1 Enable Interrupt Line x */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_ILE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_ILE_OFFSET (0x5C) /**< (MCAN_ILE) Interrupt Line Enable Register Offset */ + +#define MCAN_ILE_EINT0_Pos 0 /**< (MCAN_ILE) Enable Interrupt Line 0 Position */ +#define MCAN_ILE_EINT0_Msk (_U_(0x1) << MCAN_ILE_EINT0_Pos) /**< (MCAN_ILE) Enable Interrupt Line 0 Mask */ +#define MCAN_ILE_EINT0 MCAN_ILE_EINT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILE_EINT0_Msk instead */ +#define MCAN_ILE_EINT1_Pos 1 /**< (MCAN_ILE) Enable Interrupt Line 1 Position */ +#define MCAN_ILE_EINT1_Msk (_U_(0x1) << MCAN_ILE_EINT1_Pos) /**< (MCAN_ILE) Enable Interrupt Line 1 Mask */ +#define MCAN_ILE_EINT1 MCAN_ILE_EINT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILE_EINT1_Msk instead */ +#define MCAN_ILE_MASK _U_(0x03) /**< \deprecated (MCAN_ILE) Register MASK (Use MCAN_ILE_Msk instead) */ +#define MCAN_ILE_Msk _U_(0x03) /**< (MCAN_ILE) Register Mask */ + +#define MCAN_ILE_EINT_Pos 0 /**< (MCAN_ILE Position) Enable Interrupt Line x */ +#define MCAN_ILE_EINT_Msk (_U_(0x3) << MCAN_ILE_EINT_Pos) /**< (MCAN_ILE Mask) EINT */ +#define MCAN_ILE_EINT(value) (MCAN_ILE_EINT_Msk & ((value) << MCAN_ILE_EINT_Pos)) + +/* -------- MCAN_GFC : (MCAN Offset: 0x80) (R/W 32) Global Filter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RRFE:1; /**< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /**< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /**< bit: 2..3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /**< bit: 4..5 Accept Non-matching Frames Standard */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_GFC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_GFC_OFFSET (0x80) /**< (MCAN_GFC) Global Filter Configuration Register Offset */ + +#define MCAN_GFC_RRFE_Pos 0 /**< (MCAN_GFC) Reject Remote Frames Extended Position */ +#define MCAN_GFC_RRFE_Msk (_U_(0x1) << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject Remote Frames Extended Mask */ +#define MCAN_GFC_RRFE MCAN_GFC_RRFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_GFC_RRFE_Msk instead */ +#define MCAN_GFC_RRFE_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_FILTER (MCAN_GFC_RRFE_FILTER_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFE_REJECT (MCAN_GFC_RRFE_REJECT_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFS_Pos 1 /**< (MCAN_GFC) Reject Remote Frames Standard Position */ +#define MCAN_GFC_RRFS_Msk (_U_(0x1) << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject Remote Frames Standard Mask */ +#define MCAN_GFC_RRFS MCAN_GFC_RRFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_GFC_RRFS_Msk instead */ +#define MCAN_GFC_RRFS_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_FILTER (MCAN_GFC_RRFS_FILTER_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_RRFS_REJECT (MCAN_GFC_RRFS_REJECT_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_ANFE_Pos 2 /**< (MCAN_GFC) Accept Non-matching Frames Extended Position */ +#define MCAN_GFC_ANFE_Msk (_U_(0x3) << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Extended Mask */ +#define MCAN_GFC_ANFE(value) (MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)) +#define MCAN_GFC_ANFE_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ +#define MCAN_GFC_ANFE_RX_FIFO_0 (MCAN_GFC_ANFE_RX_FIFO_0_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (MCAN_GFC_ANFE_RX_FIFO_1_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ +#define MCAN_GFC_ANFS_Pos 4 /**< (MCAN_GFC) Accept Non-matching Frames Standard Position */ +#define MCAN_GFC_ANFS_Msk (_U_(0x3) << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Standard Mask */ +#define MCAN_GFC_ANFS(value) (MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)) +#define MCAN_GFC_ANFS_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ +#define MCAN_GFC_ANFS_RX_FIFO_0 (MCAN_GFC_ANFS_RX_FIFO_0_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (MCAN_GFC_ANFS_RX_FIFO_1_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ +#define MCAN_GFC_MASK _U_(0x3F) /**< \deprecated (MCAN_GFC) Register MASK (Use MCAN_GFC_Msk instead) */ +#define MCAN_GFC_Msk _U_(0x3F) /**< (MCAN_GFC) Register Mask */ + + +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t FLSSA:14; /**< bit: 2..15 Filter List Standard Start Address */ + uint32_t LSS:8; /**< bit: 16..23 List Size Standard */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_SIDFC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_SIDFC_OFFSET (0x84) /**< (MCAN_SIDFC) Standard ID Filter Configuration Register Offset */ + +#define MCAN_SIDFC_FLSSA_Pos 2 /**< (MCAN_SIDFC) Filter List Standard Start Address Position */ +#define MCAN_SIDFC_FLSSA_Msk (_U_(0x3FFF) << MCAN_SIDFC_FLSSA_Pos) /**< (MCAN_SIDFC) Filter List Standard Start Address Mask */ +#define MCAN_SIDFC_FLSSA(value) (MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)) +#define MCAN_SIDFC_LSS_Pos 16 /**< (MCAN_SIDFC) List Size Standard Position */ +#define MCAN_SIDFC_LSS_Msk (_U_(0xFF) << MCAN_SIDFC_LSS_Pos) /**< (MCAN_SIDFC) List Size Standard Mask */ +#define MCAN_SIDFC_LSS(value) (MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)) +#define MCAN_SIDFC_MASK _U_(0xFFFFFC) /**< \deprecated (MCAN_SIDFC) Register MASK (Use MCAN_SIDFC_Msk instead) */ +#define MCAN_SIDFC_Msk _U_(0xFFFFFC) /**< (MCAN_SIDFC) Register Mask */ + + +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t FLESA:14; /**< bit: 2..15 Filter List Extended Start Address */ + uint32_t LSE:7; /**< bit: 16..22 List Size Extended */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_XIDFC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_XIDFC_OFFSET (0x88) /**< (MCAN_XIDFC) Extended ID Filter Configuration Register Offset */ + +#define MCAN_XIDFC_FLESA_Pos 2 /**< (MCAN_XIDFC) Filter List Extended Start Address Position */ +#define MCAN_XIDFC_FLESA_Msk (_U_(0x3FFF) << MCAN_XIDFC_FLESA_Pos) /**< (MCAN_XIDFC) Filter List Extended Start Address Mask */ +#define MCAN_XIDFC_FLESA(value) (MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)) +#define MCAN_XIDFC_LSE_Pos 16 /**< (MCAN_XIDFC) List Size Extended Position */ +#define MCAN_XIDFC_LSE_Msk (_U_(0x7F) << MCAN_XIDFC_LSE_Pos) /**< (MCAN_XIDFC) List Size Extended Mask */ +#define MCAN_XIDFC_LSE(value) (MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)) +#define MCAN_XIDFC_MASK _U_(0x7FFFFC) /**< \deprecated (MCAN_XIDFC) Register MASK (Use MCAN_XIDFC_Msk instead) */ +#define MCAN_XIDFC_Msk _U_(0x7FFFFC) /**< (MCAN_XIDFC) Register Mask */ + + +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) (R/W 32) Extended ID AND Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EIDM:29; /**< bit: 0..28 Extended ID Mask */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_XIDAM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_XIDAM_OFFSET (0x90) /**< (MCAN_XIDAM) Extended ID AND Mask Register Offset */ + +#define MCAN_XIDAM_EIDM_Pos 0 /**< (MCAN_XIDAM) Extended ID Mask Position */ +#define MCAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << MCAN_XIDAM_EIDM_Pos) /**< (MCAN_XIDAM) Extended ID Mask Mask */ +#define MCAN_XIDAM_EIDM(value) (MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)) +#define MCAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \deprecated (MCAN_XIDAM) Register MASK (Use MCAN_XIDAM_Msk instead) */ +#define MCAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (MCAN_XIDAM) Register Mask */ + + +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) (R/ 32) High Priority Message Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BIDX:6; /**< bit: 0..5 Buffer Index */ + uint32_t MSI:2; /**< bit: 6..7 Message Storage Indicator */ + uint32_t FIDX:7; /**< bit: 8..14 Filter Index */ + uint32_t FLST:1; /**< bit: 15 Filter List */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_HPMS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_HPMS_OFFSET (0x94) /**< (MCAN_HPMS) High Priority Message Status Register Offset */ + +#define MCAN_HPMS_BIDX_Pos 0 /**< (MCAN_HPMS) Buffer Index Position */ +#define MCAN_HPMS_BIDX_Msk (_U_(0x3F) << MCAN_HPMS_BIDX_Pos) /**< (MCAN_HPMS) Buffer Index Mask */ +#define MCAN_HPMS_BIDX(value) (MCAN_HPMS_BIDX_Msk & ((value) << MCAN_HPMS_BIDX_Pos)) +#define MCAN_HPMS_MSI_Pos 6 /**< (MCAN_HPMS) Message Storage Indicator Position */ +#define MCAN_HPMS_MSI_Msk (_U_(0x3) << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message Storage Indicator Mask */ +#define MCAN_HPMS_MSI(value) (MCAN_HPMS_MSI_Msk & ((value) << MCAN_HPMS_MSI_Pos)) +#define MCAN_HPMS_MSI_NO_FIFO_SEL_Val _U_(0x0) /**< (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (MCAN_HPMS) FIFO message lost. */ +#define MCAN_HPMS_MSI_FIFO_0_Val _U_(0x2) /**< (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1_Val _U_(0x3) /**< (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (MCAN_HPMS_MSI_NO_FIFO_SEL_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) No FIFO selected. Position */ +#define MCAN_HPMS_MSI_LOST (MCAN_HPMS_MSI_LOST_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) FIFO message lost. Position */ +#define MCAN_HPMS_MSI_FIFO_0 (MCAN_HPMS_MSI_FIFO_0_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 0. Position */ +#define MCAN_HPMS_MSI_FIFO_1 (MCAN_HPMS_MSI_FIFO_1_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 1. Position */ +#define MCAN_HPMS_FIDX_Pos 8 /**< (MCAN_HPMS) Filter Index Position */ +#define MCAN_HPMS_FIDX_Msk (_U_(0x7F) << MCAN_HPMS_FIDX_Pos) /**< (MCAN_HPMS) Filter Index Mask */ +#define MCAN_HPMS_FIDX(value) (MCAN_HPMS_FIDX_Msk & ((value) << MCAN_HPMS_FIDX_Pos)) +#define MCAN_HPMS_FLST_Pos 15 /**< (MCAN_HPMS) Filter List Position */ +#define MCAN_HPMS_FLST_Msk (_U_(0x1) << MCAN_HPMS_FLST_Pos) /**< (MCAN_HPMS) Filter List Mask */ +#define MCAN_HPMS_FLST MCAN_HPMS_FLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_HPMS_FLST_Msk instead */ +#define MCAN_HPMS_MASK _U_(0xFFFF) /**< \deprecated (MCAN_HPMS) Register MASK (Use MCAN_HPMS_Msk instead) */ +#define MCAN_HPMS_Msk _U_(0xFFFF) /**< (MCAN_HPMS) Register Mask */ + + +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) (R/W 32) New Data 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ND0:1; /**< bit: 0 New Data */ + uint32_t ND1:1; /**< bit: 1 New Data */ + uint32_t ND2:1; /**< bit: 2 New Data */ + uint32_t ND3:1; /**< bit: 3 New Data */ + uint32_t ND4:1; /**< bit: 4 New Data */ + uint32_t ND5:1; /**< bit: 5 New Data */ + uint32_t ND6:1; /**< bit: 6 New Data */ + uint32_t ND7:1; /**< bit: 7 New Data */ + uint32_t ND8:1; /**< bit: 8 New Data */ + uint32_t ND9:1; /**< bit: 9 New Data */ + uint32_t ND10:1; /**< bit: 10 New Data */ + uint32_t ND11:1; /**< bit: 11 New Data */ + uint32_t ND12:1; /**< bit: 12 New Data */ + uint32_t ND13:1; /**< bit: 13 New Data */ + uint32_t ND14:1; /**< bit: 14 New Data */ + uint32_t ND15:1; /**< bit: 15 New Data */ + uint32_t ND16:1; /**< bit: 16 New Data */ + uint32_t ND17:1; /**< bit: 17 New Data */ + uint32_t ND18:1; /**< bit: 18 New Data */ + uint32_t ND19:1; /**< bit: 19 New Data */ + uint32_t ND20:1; /**< bit: 20 New Data */ + uint32_t ND21:1; /**< bit: 21 New Data */ + uint32_t ND22:1; /**< bit: 22 New Data */ + uint32_t ND23:1; /**< bit: 23 New Data */ + uint32_t ND24:1; /**< bit: 24 New Data */ + uint32_t ND25:1; /**< bit: 25 New Data */ + uint32_t ND26:1; /**< bit: 26 New Data */ + uint32_t ND27:1; /**< bit: 27 New Data */ + uint32_t ND28:1; /**< bit: 28 New Data */ + uint32_t ND29:1; /**< bit: 29 New Data */ + uint32_t ND30:1; /**< bit: 30 New Data */ + uint32_t ND31:1; /**< bit: 31 New Data */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ND:32; /**< bit: 0..31 New Data */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_NDAT1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_NDAT1_OFFSET (0x98) /**< (MCAN_NDAT1) New Data 1 Register Offset */ + +#define MCAN_NDAT1_ND0_Pos 0 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND0_Msk (_U_(0x1) << MCAN_NDAT1_ND0_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND0 MCAN_NDAT1_ND0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND0_Msk instead */ +#define MCAN_NDAT1_ND1_Pos 1 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND1_Msk (_U_(0x1) << MCAN_NDAT1_ND1_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND1 MCAN_NDAT1_ND1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND1_Msk instead */ +#define MCAN_NDAT1_ND2_Pos 2 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND2_Msk (_U_(0x1) << MCAN_NDAT1_ND2_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND2 MCAN_NDAT1_ND2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND2_Msk instead */ +#define MCAN_NDAT1_ND3_Pos 3 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND3_Msk (_U_(0x1) << MCAN_NDAT1_ND3_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND3 MCAN_NDAT1_ND3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND3_Msk instead */ +#define MCAN_NDAT1_ND4_Pos 4 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND4_Msk (_U_(0x1) << MCAN_NDAT1_ND4_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND4 MCAN_NDAT1_ND4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND4_Msk instead */ +#define MCAN_NDAT1_ND5_Pos 5 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND5_Msk (_U_(0x1) << MCAN_NDAT1_ND5_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND5 MCAN_NDAT1_ND5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND5_Msk instead */ +#define MCAN_NDAT1_ND6_Pos 6 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND6_Msk (_U_(0x1) << MCAN_NDAT1_ND6_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND6 MCAN_NDAT1_ND6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND6_Msk instead */ +#define MCAN_NDAT1_ND7_Pos 7 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND7_Msk (_U_(0x1) << MCAN_NDAT1_ND7_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND7 MCAN_NDAT1_ND7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND7_Msk instead */ +#define MCAN_NDAT1_ND8_Pos 8 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND8_Msk (_U_(0x1) << MCAN_NDAT1_ND8_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND8 MCAN_NDAT1_ND8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND8_Msk instead */ +#define MCAN_NDAT1_ND9_Pos 9 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND9_Msk (_U_(0x1) << MCAN_NDAT1_ND9_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND9 MCAN_NDAT1_ND9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND9_Msk instead */ +#define MCAN_NDAT1_ND10_Pos 10 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND10_Msk (_U_(0x1) << MCAN_NDAT1_ND10_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND10 MCAN_NDAT1_ND10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND10_Msk instead */ +#define MCAN_NDAT1_ND11_Pos 11 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND11_Msk (_U_(0x1) << MCAN_NDAT1_ND11_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND11 MCAN_NDAT1_ND11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND11_Msk instead */ +#define MCAN_NDAT1_ND12_Pos 12 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND12_Msk (_U_(0x1) << MCAN_NDAT1_ND12_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND12 MCAN_NDAT1_ND12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND12_Msk instead */ +#define MCAN_NDAT1_ND13_Pos 13 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND13_Msk (_U_(0x1) << MCAN_NDAT1_ND13_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND13 MCAN_NDAT1_ND13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND13_Msk instead */ +#define MCAN_NDAT1_ND14_Pos 14 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND14_Msk (_U_(0x1) << MCAN_NDAT1_ND14_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND14 MCAN_NDAT1_ND14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND14_Msk instead */ +#define MCAN_NDAT1_ND15_Pos 15 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND15_Msk (_U_(0x1) << MCAN_NDAT1_ND15_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND15 MCAN_NDAT1_ND15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND15_Msk instead */ +#define MCAN_NDAT1_ND16_Pos 16 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND16_Msk (_U_(0x1) << MCAN_NDAT1_ND16_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND16 MCAN_NDAT1_ND16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND16_Msk instead */ +#define MCAN_NDAT1_ND17_Pos 17 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND17_Msk (_U_(0x1) << MCAN_NDAT1_ND17_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND17 MCAN_NDAT1_ND17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND17_Msk instead */ +#define MCAN_NDAT1_ND18_Pos 18 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND18_Msk (_U_(0x1) << MCAN_NDAT1_ND18_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND18 MCAN_NDAT1_ND18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND18_Msk instead */ +#define MCAN_NDAT1_ND19_Pos 19 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND19_Msk (_U_(0x1) << MCAN_NDAT1_ND19_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND19 MCAN_NDAT1_ND19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND19_Msk instead */ +#define MCAN_NDAT1_ND20_Pos 20 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND20_Msk (_U_(0x1) << MCAN_NDAT1_ND20_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND20 MCAN_NDAT1_ND20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND20_Msk instead */ +#define MCAN_NDAT1_ND21_Pos 21 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND21_Msk (_U_(0x1) << MCAN_NDAT1_ND21_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND21 MCAN_NDAT1_ND21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND21_Msk instead */ +#define MCAN_NDAT1_ND22_Pos 22 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND22_Msk (_U_(0x1) << MCAN_NDAT1_ND22_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND22 MCAN_NDAT1_ND22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND22_Msk instead */ +#define MCAN_NDAT1_ND23_Pos 23 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND23_Msk (_U_(0x1) << MCAN_NDAT1_ND23_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND23 MCAN_NDAT1_ND23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND23_Msk instead */ +#define MCAN_NDAT1_ND24_Pos 24 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND24_Msk (_U_(0x1) << MCAN_NDAT1_ND24_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND24 MCAN_NDAT1_ND24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND24_Msk instead */ +#define MCAN_NDAT1_ND25_Pos 25 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND25_Msk (_U_(0x1) << MCAN_NDAT1_ND25_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND25 MCAN_NDAT1_ND25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND25_Msk instead */ +#define MCAN_NDAT1_ND26_Pos 26 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND26_Msk (_U_(0x1) << MCAN_NDAT1_ND26_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND26 MCAN_NDAT1_ND26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND26_Msk instead */ +#define MCAN_NDAT1_ND27_Pos 27 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND27_Msk (_U_(0x1) << MCAN_NDAT1_ND27_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND27 MCAN_NDAT1_ND27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND27_Msk instead */ +#define MCAN_NDAT1_ND28_Pos 28 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND28_Msk (_U_(0x1) << MCAN_NDAT1_ND28_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND28 MCAN_NDAT1_ND28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND28_Msk instead */ +#define MCAN_NDAT1_ND29_Pos 29 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND29_Msk (_U_(0x1) << MCAN_NDAT1_ND29_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND29 MCAN_NDAT1_ND29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND29_Msk instead */ +#define MCAN_NDAT1_ND30_Pos 30 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND30_Msk (_U_(0x1) << MCAN_NDAT1_ND30_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND30 MCAN_NDAT1_ND30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND30_Msk instead */ +#define MCAN_NDAT1_ND31_Pos 31 /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND31_Msk (_U_(0x1) << MCAN_NDAT1_ND31_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND31 MCAN_NDAT1_ND31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND31_Msk instead */ +#define MCAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_NDAT1) Register MASK (Use MCAN_NDAT1_Msk instead) */ +#define MCAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT1) Register Mask */ + +#define MCAN_NDAT1_ND_Pos 0 /**< (MCAN_NDAT1 Position) New Data */ +#define MCAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT1_ND_Pos) /**< (MCAN_NDAT1 Mask) ND */ +#define MCAN_NDAT1_ND(value) (MCAN_NDAT1_ND_Msk & ((value) << MCAN_NDAT1_ND_Pos)) + +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9c) (R/W 32) New Data 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ND32:1; /**< bit: 0 New Data */ + uint32_t ND33:1; /**< bit: 1 New Data */ + uint32_t ND34:1; /**< bit: 2 New Data */ + uint32_t ND35:1; /**< bit: 3 New Data */ + uint32_t ND36:1; /**< bit: 4 New Data */ + uint32_t ND37:1; /**< bit: 5 New Data */ + uint32_t ND38:1; /**< bit: 6 New Data */ + uint32_t ND39:1; /**< bit: 7 New Data */ + uint32_t ND40:1; /**< bit: 8 New Data */ + uint32_t ND41:1; /**< bit: 9 New Data */ + uint32_t ND42:1; /**< bit: 10 New Data */ + uint32_t ND43:1; /**< bit: 11 New Data */ + uint32_t ND44:1; /**< bit: 12 New Data */ + uint32_t ND45:1; /**< bit: 13 New Data */ + uint32_t ND46:1; /**< bit: 14 New Data */ + uint32_t ND47:1; /**< bit: 15 New Data */ + uint32_t ND48:1; /**< bit: 16 New Data */ + uint32_t ND49:1; /**< bit: 17 New Data */ + uint32_t ND50:1; /**< bit: 18 New Data */ + uint32_t ND51:1; /**< bit: 19 New Data */ + uint32_t ND52:1; /**< bit: 20 New Data */ + uint32_t ND53:1; /**< bit: 21 New Data */ + uint32_t ND54:1; /**< bit: 22 New Data */ + uint32_t ND55:1; /**< bit: 23 New Data */ + uint32_t ND56:1; /**< bit: 24 New Data */ + uint32_t ND57:1; /**< bit: 25 New Data */ + uint32_t ND58:1; /**< bit: 26 New Data */ + uint32_t ND59:1; /**< bit: 27 New Data */ + uint32_t ND60:1; /**< bit: 28 New Data */ + uint32_t ND61:1; /**< bit: 29 New Data */ + uint32_t ND62:1; /**< bit: 30 New Data */ + uint32_t ND63:1; /**< bit: 31 New Data */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ND:32; /**< bit: 0..31 New Data */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_NDAT2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_NDAT2_OFFSET (0x9C) /**< (MCAN_NDAT2) New Data 2 Register Offset */ + +#define MCAN_NDAT2_ND32_Pos 0 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND32_Msk (_U_(0x1) << MCAN_NDAT2_ND32_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND32 MCAN_NDAT2_ND32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND32_Msk instead */ +#define MCAN_NDAT2_ND33_Pos 1 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND33_Msk (_U_(0x1) << MCAN_NDAT2_ND33_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND33 MCAN_NDAT2_ND33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND33_Msk instead */ +#define MCAN_NDAT2_ND34_Pos 2 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND34_Msk (_U_(0x1) << MCAN_NDAT2_ND34_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND34 MCAN_NDAT2_ND34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND34_Msk instead */ +#define MCAN_NDAT2_ND35_Pos 3 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND35_Msk (_U_(0x1) << MCAN_NDAT2_ND35_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND35 MCAN_NDAT2_ND35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND35_Msk instead */ +#define MCAN_NDAT2_ND36_Pos 4 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND36_Msk (_U_(0x1) << MCAN_NDAT2_ND36_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND36 MCAN_NDAT2_ND36_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND36_Msk instead */ +#define MCAN_NDAT2_ND37_Pos 5 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND37_Msk (_U_(0x1) << MCAN_NDAT2_ND37_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND37 MCAN_NDAT2_ND37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND37_Msk instead */ +#define MCAN_NDAT2_ND38_Pos 6 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND38_Msk (_U_(0x1) << MCAN_NDAT2_ND38_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND38 MCAN_NDAT2_ND38_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND38_Msk instead */ +#define MCAN_NDAT2_ND39_Pos 7 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND39_Msk (_U_(0x1) << MCAN_NDAT2_ND39_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND39 MCAN_NDAT2_ND39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND39_Msk instead */ +#define MCAN_NDAT2_ND40_Pos 8 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND40_Msk (_U_(0x1) << MCAN_NDAT2_ND40_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND40 MCAN_NDAT2_ND40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND40_Msk instead */ +#define MCAN_NDAT2_ND41_Pos 9 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND41_Msk (_U_(0x1) << MCAN_NDAT2_ND41_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND41 MCAN_NDAT2_ND41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND41_Msk instead */ +#define MCAN_NDAT2_ND42_Pos 10 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND42_Msk (_U_(0x1) << MCAN_NDAT2_ND42_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND42 MCAN_NDAT2_ND42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND42_Msk instead */ +#define MCAN_NDAT2_ND43_Pos 11 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND43_Msk (_U_(0x1) << MCAN_NDAT2_ND43_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND43 MCAN_NDAT2_ND43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND43_Msk instead */ +#define MCAN_NDAT2_ND44_Pos 12 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND44_Msk (_U_(0x1) << MCAN_NDAT2_ND44_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND44 MCAN_NDAT2_ND44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND44_Msk instead */ +#define MCAN_NDAT2_ND45_Pos 13 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND45_Msk (_U_(0x1) << MCAN_NDAT2_ND45_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND45 MCAN_NDAT2_ND45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND45_Msk instead */ +#define MCAN_NDAT2_ND46_Pos 14 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND46_Msk (_U_(0x1) << MCAN_NDAT2_ND46_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND46 MCAN_NDAT2_ND46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND46_Msk instead */ +#define MCAN_NDAT2_ND47_Pos 15 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND47_Msk (_U_(0x1) << MCAN_NDAT2_ND47_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND47 MCAN_NDAT2_ND47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND47_Msk instead */ +#define MCAN_NDAT2_ND48_Pos 16 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND48_Msk (_U_(0x1) << MCAN_NDAT2_ND48_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND48 MCAN_NDAT2_ND48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND48_Msk instead */ +#define MCAN_NDAT2_ND49_Pos 17 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND49_Msk (_U_(0x1) << MCAN_NDAT2_ND49_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND49 MCAN_NDAT2_ND49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND49_Msk instead */ +#define MCAN_NDAT2_ND50_Pos 18 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND50_Msk (_U_(0x1) << MCAN_NDAT2_ND50_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND50 MCAN_NDAT2_ND50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND50_Msk instead */ +#define MCAN_NDAT2_ND51_Pos 19 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND51_Msk (_U_(0x1) << MCAN_NDAT2_ND51_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND51 MCAN_NDAT2_ND51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND51_Msk instead */ +#define MCAN_NDAT2_ND52_Pos 20 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND52_Msk (_U_(0x1) << MCAN_NDAT2_ND52_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND52 MCAN_NDAT2_ND52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND52_Msk instead */ +#define MCAN_NDAT2_ND53_Pos 21 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND53_Msk (_U_(0x1) << MCAN_NDAT2_ND53_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND53 MCAN_NDAT2_ND53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND53_Msk instead */ +#define MCAN_NDAT2_ND54_Pos 22 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND54_Msk (_U_(0x1) << MCAN_NDAT2_ND54_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND54 MCAN_NDAT2_ND54_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND54_Msk instead */ +#define MCAN_NDAT2_ND55_Pos 23 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND55_Msk (_U_(0x1) << MCAN_NDAT2_ND55_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND55 MCAN_NDAT2_ND55_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND55_Msk instead */ +#define MCAN_NDAT2_ND56_Pos 24 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND56_Msk (_U_(0x1) << MCAN_NDAT2_ND56_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND56 MCAN_NDAT2_ND56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND56_Msk instead */ +#define MCAN_NDAT2_ND57_Pos 25 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND57_Msk (_U_(0x1) << MCAN_NDAT2_ND57_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND57 MCAN_NDAT2_ND57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND57_Msk instead */ +#define MCAN_NDAT2_ND58_Pos 26 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND58_Msk (_U_(0x1) << MCAN_NDAT2_ND58_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND58 MCAN_NDAT2_ND58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND58_Msk instead */ +#define MCAN_NDAT2_ND59_Pos 27 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND59_Msk (_U_(0x1) << MCAN_NDAT2_ND59_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND59 MCAN_NDAT2_ND59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND59_Msk instead */ +#define MCAN_NDAT2_ND60_Pos 28 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND60_Msk (_U_(0x1) << MCAN_NDAT2_ND60_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND60 MCAN_NDAT2_ND60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND60_Msk instead */ +#define MCAN_NDAT2_ND61_Pos 29 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND61_Msk (_U_(0x1) << MCAN_NDAT2_ND61_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND61 MCAN_NDAT2_ND61_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND61_Msk instead */ +#define MCAN_NDAT2_ND62_Pos 30 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND62_Msk (_U_(0x1) << MCAN_NDAT2_ND62_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND62 MCAN_NDAT2_ND62_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND62_Msk instead */ +#define MCAN_NDAT2_ND63_Pos 31 /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND63_Msk (_U_(0x1) << MCAN_NDAT2_ND63_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND63 MCAN_NDAT2_ND63_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND63_Msk instead */ +#define MCAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_NDAT2) Register MASK (Use MCAN_NDAT2_Msk instead) */ +#define MCAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT2) Register Mask */ + +#define MCAN_NDAT2_ND_Pos 0 /**< (MCAN_NDAT2 Position) New Data */ +#define MCAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT2_ND_Pos) /**< (MCAN_NDAT2 Mask) ND */ +#define MCAN_NDAT2_ND(value) (MCAN_NDAT2_ND_Msk & ((value) << MCAN_NDAT2_ND_Pos)) + +/* -------- MCAN_RXF0C : (MCAN Offset: 0xa0) (R/W 32) Receive FIFO 0 Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t F0SA:14; /**< bit: 2..15 Receive FIFO 0 Start Address */ + uint32_t F0S:7; /**< bit: 16..22 Receive FIFO 0 Start Address */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t F0WM:7; /**< bit: 24..30 Receive FIFO 0 Watermark */ + uint32_t F0OM:1; /**< bit: 31 FIFO 0 Operation Mode */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0C_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0C_OFFSET (0xA0) /**< (MCAN_RXF0C) Receive FIFO 0 Configuration Register Offset */ + +#define MCAN_RXF0C_F0SA_Pos 2 /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0SA_Msk (_U_(0x3FFF) << MCAN_RXF0C_F0SA_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0SA(value) (MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)) +#define MCAN_RXF0C_F0S_Pos 16 /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0S_Msk (_U_(0x7F) << MCAN_RXF0C_F0S_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0S(value) (MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)) +#define MCAN_RXF0C_F0WM_Pos 24 /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Position */ +#define MCAN_RXF0C_F0WM_Msk (_U_(0x7F) << MCAN_RXF0C_F0WM_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Mask */ +#define MCAN_RXF0C_F0WM(value) (MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)) +#define MCAN_RXF0C_F0OM_Pos 31 /**< (MCAN_RXF0C) FIFO 0 Operation Mode Position */ +#define MCAN_RXF0C_F0OM_Msk (_U_(0x1) << MCAN_RXF0C_F0OM_Pos) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define MCAN_RXF0C_F0OM MCAN_RXF0C_F0OM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0C_F0OM_Msk instead */ +#define MCAN_RXF0C_MASK _U_(0xFF7FFFFC) /**< \deprecated (MCAN_RXF0C) Register MASK (Use MCAN_RXF0C_Msk instead) */ +#define MCAN_RXF0C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF0C) Register Mask */ + + +/* -------- MCAN_RXF0S : (MCAN Offset: 0xa4) (R/ 32) Receive FIFO 0 Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t F0FL:7; /**< bit: 0..6 Receive FIFO 0 Fill Level */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t F0GI:6; /**< bit: 8..13 Receive FIFO 0 Get Index */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t F0PI:6; /**< bit: 16..21 Receive FIFO 0 Put Index */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t F0F:1; /**< bit: 24 Receive FIFO 0 Fill Level */ + uint32_t RF0L:1; /**< bit: 25 Receive FIFO 0 Message Lost */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0S_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0S_OFFSET (0xA4) /**< (MCAN_RXF0S) Receive FIFO 0 Status Register Offset */ + +#define MCAN_RXF0S_F0FL_Pos 0 /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0FL_Msk (_U_(0x7F) << MCAN_RXF0S_F0FL_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0FL(value) (MCAN_RXF0S_F0FL_Msk & ((value) << MCAN_RXF0S_F0FL_Pos)) +#define MCAN_RXF0S_F0GI_Pos 8 /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Position */ +#define MCAN_RXF0S_F0GI_Msk (_U_(0x3F) << MCAN_RXF0S_F0GI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Mask */ +#define MCAN_RXF0S_F0GI(value) (MCAN_RXF0S_F0GI_Msk & ((value) << MCAN_RXF0S_F0GI_Pos)) +#define MCAN_RXF0S_F0PI_Pos 16 /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Position */ +#define MCAN_RXF0S_F0PI_Msk (_U_(0x3F) << MCAN_RXF0S_F0PI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Mask */ +#define MCAN_RXF0S_F0PI(value) (MCAN_RXF0S_F0PI_Msk & ((value) << MCAN_RXF0S_F0PI_Pos)) +#define MCAN_RXF0S_F0F_Pos 24 /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0F_Msk (_U_(0x1) << MCAN_RXF0S_F0F_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0F MCAN_RXF0S_F0F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0S_F0F_Msk instead */ +#define MCAN_RXF0S_RF0L_Pos 25 /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Position */ +#define MCAN_RXF0S_RF0L_Msk (_U_(0x1) << MCAN_RXF0S_RF0L_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Mask */ +#define MCAN_RXF0S_RF0L MCAN_RXF0S_RF0L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0S_RF0L_Msk instead */ +#define MCAN_RXF0S_MASK _U_(0x33F3F7F) /**< \deprecated (MCAN_RXF0S) Register MASK (Use MCAN_RXF0S_Msk instead) */ +#define MCAN_RXF0S_Msk _U_(0x33F3F7F) /**< (MCAN_RXF0S) Register Mask */ + + +/* -------- MCAN_RXF0A : (MCAN Offset: 0xa8) (R/W 32) Receive FIFO 0 Acknowledge Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t F0AI:6; /**< bit: 0..5 Receive FIFO 0 Acknowledge Index */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF0A_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF0A_OFFSET (0xA8) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Register Offset */ + +#define MCAN_RXF0A_F0AI_Pos 0 /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Position */ +#define MCAN_RXF0A_F0AI_Msk (_U_(0x3F) << MCAN_RXF0A_F0AI_Pos) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Mask */ +#define MCAN_RXF0A_F0AI(value) (MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)) +#define MCAN_RXF0A_MASK _U_(0x3F) /**< \deprecated (MCAN_RXF0A) Register MASK (Use MCAN_RXF0A_Msk instead) */ +#define MCAN_RXF0A_Msk _U_(0x3F) /**< (MCAN_RXF0A) Register Mask */ + + +/* -------- MCAN_RXBC : (MCAN Offset: 0xac) (R/W 32) Receive Rx Buffer Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RBSA:14; /**< bit: 2..15 Receive Buffer Start Address */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXBC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXBC_OFFSET (0xAC) /**< (MCAN_RXBC) Receive Rx Buffer Configuration Register Offset */ + +#define MCAN_RXBC_RBSA_Pos 2 /**< (MCAN_RXBC) Receive Buffer Start Address Position */ +#define MCAN_RXBC_RBSA_Msk (_U_(0x3FFF) << MCAN_RXBC_RBSA_Pos) /**< (MCAN_RXBC) Receive Buffer Start Address Mask */ +#define MCAN_RXBC_RBSA(value) (MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)) +#define MCAN_RXBC_MASK _U_(0xFFFC) /**< \deprecated (MCAN_RXBC) Register MASK (Use MCAN_RXBC_Msk instead) */ +#define MCAN_RXBC_Msk _U_(0xFFFC) /**< (MCAN_RXBC) Register Mask */ + + +/* -------- MCAN_RXF1C : (MCAN Offset: 0xb0) (R/W 32) Receive FIFO 1 Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t F1SA:14; /**< bit: 2..15 Receive FIFO 1 Start Address */ + uint32_t F1S:7; /**< bit: 16..22 Receive FIFO 1 Start Address */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t F1WM:7; /**< bit: 24..30 Receive FIFO 1 Watermark */ + uint32_t F1OM:1; /**< bit: 31 FIFO 1 Operation Mode */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1C_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1C_OFFSET (0xB0) /**< (MCAN_RXF1C) Receive FIFO 1 Configuration Register Offset */ + +#define MCAN_RXF1C_F1SA_Pos 2 /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1SA_Msk (_U_(0x3FFF) << MCAN_RXF1C_F1SA_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1SA(value) (MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)) +#define MCAN_RXF1C_F1S_Pos 16 /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1S_Msk (_U_(0x7F) << MCAN_RXF1C_F1S_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1S(value) (MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)) +#define MCAN_RXF1C_F1WM_Pos 24 /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Position */ +#define MCAN_RXF1C_F1WM_Msk (_U_(0x7F) << MCAN_RXF1C_F1WM_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Mask */ +#define MCAN_RXF1C_F1WM(value) (MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)) +#define MCAN_RXF1C_F1OM_Pos 31 /**< (MCAN_RXF1C) FIFO 1 Operation Mode Position */ +#define MCAN_RXF1C_F1OM_Msk (_U_(0x1) << MCAN_RXF1C_F1OM_Pos) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define MCAN_RXF1C_F1OM MCAN_RXF1C_F1OM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1C_F1OM_Msk instead */ +#define MCAN_RXF1C_MASK _U_(0xFF7FFFFC) /**< \deprecated (MCAN_RXF1C) Register MASK (Use MCAN_RXF1C_Msk instead) */ +#define MCAN_RXF1C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF1C) Register Mask */ + + +/* -------- MCAN_RXF1S : (MCAN Offset: 0xb4) (R/ 32) Receive FIFO 1 Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t F1FL:7; /**< bit: 0..6 Receive FIFO 1 Fill Level */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t F1GI:6; /**< bit: 8..13 Receive FIFO 1 Get Index */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t F1PI:6; /**< bit: 16..21 Receive FIFO 1 Put Index */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t F1F:1; /**< bit: 24 Receive FIFO 1 Fill Level */ + uint32_t RF1L:1; /**< bit: 25 Receive FIFO 1 Message Lost */ + uint32_t :4; /**< bit: 26..29 Reserved */ + uint32_t DMS:2; /**< bit: 30..31 Debug Message Status */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1S_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1S_OFFSET (0xB4) /**< (MCAN_RXF1S) Receive FIFO 1 Status Register Offset */ + +#define MCAN_RXF1S_F1FL_Pos 0 /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1FL_Msk (_U_(0x7F) << MCAN_RXF1S_F1FL_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1FL(value) (MCAN_RXF1S_F1FL_Msk & ((value) << MCAN_RXF1S_F1FL_Pos)) +#define MCAN_RXF1S_F1GI_Pos 8 /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Position */ +#define MCAN_RXF1S_F1GI_Msk (_U_(0x3F) << MCAN_RXF1S_F1GI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Mask */ +#define MCAN_RXF1S_F1GI(value) (MCAN_RXF1S_F1GI_Msk & ((value) << MCAN_RXF1S_F1GI_Pos)) +#define MCAN_RXF1S_F1PI_Pos 16 /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Position */ +#define MCAN_RXF1S_F1PI_Msk (_U_(0x3F) << MCAN_RXF1S_F1PI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Mask */ +#define MCAN_RXF1S_F1PI(value) (MCAN_RXF1S_F1PI_Msk & ((value) << MCAN_RXF1S_F1PI_Pos)) +#define MCAN_RXF1S_F1F_Pos 24 /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1F_Msk (_U_(0x1) << MCAN_RXF1S_F1F_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1F MCAN_RXF1S_F1F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1S_F1F_Msk instead */ +#define MCAN_RXF1S_RF1L_Pos 25 /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Position */ +#define MCAN_RXF1S_RF1L_Msk (_U_(0x1) << MCAN_RXF1S_RF1L_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Mask */ +#define MCAN_RXF1S_RF1L MCAN_RXF1S_RF1L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1S_RF1L_Msk instead */ +#define MCAN_RXF1S_DMS_Pos 30 /**< (MCAN_RXF1S) Debug Message Status Position */ +#define MCAN_RXF1S_DMS_Msk (_U_(0x3) << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug Message Status Mask */ +#define MCAN_RXF1S_DMS(value) (MCAN_RXF1S_DMS_Msk & ((value) << MCAN_RXF1S_DMS_Pos)) +#define MCAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A_Val _U_(0x1) /**< (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB_Val _U_(0x2) /**< (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC_Val _U_(0x3) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +#define MCAN_RXF1S_DMS_IDLE (MCAN_RXF1S_DMS_IDLE_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. Position */ +#define MCAN_RXF1S_DMS_MSG_A (MCAN_RXF1S_DMS_MSG_A_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug message A received. Position */ +#define MCAN_RXF1S_DMS_MSG_AB (MCAN_RXF1S_DMS_MSG_AB_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B received. Position */ +#define MCAN_RXF1S_DMS_MSG_ABC (MCAN_RXF1S_DMS_MSG_ABC_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. Position */ +#define MCAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \deprecated (MCAN_RXF1S) Register MASK (Use MCAN_RXF1S_Msk instead) */ +#define MCAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (MCAN_RXF1S) Register Mask */ + + +/* -------- MCAN_RXF1A : (MCAN Offset: 0xb8) (R/W 32) Receive FIFO 1 Acknowledge Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t F1AI:6; /**< bit: 0..5 Receive FIFO 1 Acknowledge Index */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXF1A_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXF1A_OFFSET (0xB8) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Register Offset */ + +#define MCAN_RXF1A_F1AI_Pos 0 /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Position */ +#define MCAN_RXF1A_F1AI_Msk (_U_(0x3F) << MCAN_RXF1A_F1AI_Pos) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Mask */ +#define MCAN_RXF1A_F1AI(value) (MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)) +#define MCAN_RXF1A_MASK _U_(0x3F) /**< \deprecated (MCAN_RXF1A) Register MASK (Use MCAN_RXF1A_Msk instead) */ +#define MCAN_RXF1A_Msk _U_(0x3F) /**< (MCAN_RXF1A) Register Mask */ + + +/* -------- MCAN_RXESC : (MCAN Offset: 0xbc) (R/W 32) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t F0DS:3; /**< bit: 0..2 Receive FIFO 0 Data Field Size */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t F1DS:3; /**< bit: 4..6 Receive FIFO 1 Data Field Size */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t RBDS:3; /**< bit: 8..10 Receive Buffer Data Field Size */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_RXESC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_RXESC_OFFSET (0xBC) /**< (MCAN_RXESC) Receive Buffer / FIFO Element Size Configuration Register Offset */ + +#define MCAN_RXESC_F0DS_Pos 0 /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Position */ +#define MCAN_RXESC_F0DS_Msk (_U_(0x7) << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Mask */ +#define MCAN_RXESC_F0DS(value) (MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)) +#define MCAN_RXESC_F0DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F0DS_8_BYTE (MCAN_RXESC_F0DS_8_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F0DS_12_BYTE (MCAN_RXESC_F0DS_12_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F0DS_16_BYTE (MCAN_RXESC_F0DS_16_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F0DS_20_BYTE (MCAN_RXESC_F0DS_20_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F0DS_24_BYTE (MCAN_RXESC_F0DS_24_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F0DS_32_BYTE (MCAN_RXESC_F0DS_32_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F0DS_48_BYTE (MCAN_RXESC_F0DS_48_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F0DS_64_BYTE (MCAN_RXESC_F0DS_64_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_F1DS_Pos 4 /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Position */ +#define MCAN_RXESC_F1DS_Msk (_U_(0x7) << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Mask */ +#define MCAN_RXESC_F1DS(value) (MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)) +#define MCAN_RXESC_F1DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_8_BYTE (MCAN_RXESC_F1DS_8_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F1DS_12_BYTE (MCAN_RXESC_F1DS_12_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F1DS_16_BYTE (MCAN_RXESC_F1DS_16_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F1DS_20_BYTE (MCAN_RXESC_F1DS_20_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F1DS_24_BYTE (MCAN_RXESC_F1DS_24_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F1DS_32_BYTE (MCAN_RXESC_F1DS_32_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F1DS_48_BYTE (MCAN_RXESC_F1DS_48_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F1DS_64_BYTE (MCAN_RXESC_F1DS_64_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_RBDS_Pos 8 /**< (MCAN_RXESC) Receive Buffer Data Field Size Position */ +#define MCAN_RXESC_RBDS_Msk (_U_(0x7) << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) Receive Buffer Data Field Size Mask */ +#define MCAN_RXESC_RBDS(value) (MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)) +#define MCAN_RXESC_RBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_8_BYTE (MCAN_RXESC_RBDS_8_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_RBDS_12_BYTE (MCAN_RXESC_RBDS_12_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_RBDS_16_BYTE (MCAN_RXESC_RBDS_16_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_RBDS_20_BYTE (MCAN_RXESC_RBDS_20_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_RBDS_24_BYTE (MCAN_RXESC_RBDS_24_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_RBDS_32_BYTE (MCAN_RXESC_RBDS_32_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_RBDS_48_BYTE (MCAN_RXESC_RBDS_48_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_RBDS_64_BYTE (MCAN_RXESC_RBDS_64_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_MASK _U_(0x777) /**< \deprecated (MCAN_RXESC) Register MASK (Use MCAN_RXESC_Msk instead) */ +#define MCAN_RXESC_Msk _U_(0x777) /**< (MCAN_RXESC) Register Mask */ + + +/* -------- MCAN_TXBC : (MCAN Offset: 0xc0) (R/W 32) Transmit Buffer Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TBSA:14; /**< bit: 2..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /**< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t TFQS:6; /**< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /**< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBC_OFFSET (0xC0) /**< (MCAN_TXBC) Transmit Buffer Configuration Register Offset */ + +#define MCAN_TXBC_TBSA_Pos 2 /**< (MCAN_TXBC) Tx Buffers Start Address Position */ +#define MCAN_TXBC_TBSA_Msk (_U_(0x3FFF) << MCAN_TXBC_TBSA_Pos) /**< (MCAN_TXBC) Tx Buffers Start Address Mask */ +#define MCAN_TXBC_TBSA(value) (MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)) +#define MCAN_TXBC_NDTB_Pos 16 /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define MCAN_TXBC_NDTB_Msk (_U_(0x3F) << MCAN_TXBC_NDTB_Pos) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define MCAN_TXBC_NDTB(value) (MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)) +#define MCAN_TXBC_TFQS_Pos 24 /**< (MCAN_TXBC) Transmit FIFO/Queue Size Position */ +#define MCAN_TXBC_TFQS_Msk (_U_(0x3F) << MCAN_TXBC_TFQS_Pos) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define MCAN_TXBC_TFQS(value) (MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)) +#define MCAN_TXBC_TFQM_Pos 30 /**< (MCAN_TXBC) Tx FIFO/Queue Mode Position */ +#define MCAN_TXBC_TFQM_Msk (_U_(0x1) << MCAN_TXBC_TFQM_Pos) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define MCAN_TXBC_TFQM MCAN_TXBC_TFQM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBC_TFQM_Msk instead */ +#define MCAN_TXBC_MASK _U_(0x7F3FFFFC) /**< \deprecated (MCAN_TXBC) Register MASK (Use MCAN_TXBC_Msk instead) */ +#define MCAN_TXBC_Msk _U_(0x7F3FFFFC) /**< (MCAN_TXBC) Register Mask */ + + +/* -------- MCAN_TXFQS : (MCAN Offset: 0xc4) (R/ 32) Transmit FIFO/Queue Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TFFL:6; /**< bit: 0..5 Tx FIFO Free Level */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t TFGI:5; /**< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /**< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /**< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXFQS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXFQS_OFFSET (0xC4) /**< (MCAN_TXFQS) Transmit FIFO/Queue Status Register Offset */ + +#define MCAN_TXFQS_TFFL_Pos 0 /**< (MCAN_TXFQS) Tx FIFO Free Level Position */ +#define MCAN_TXFQS_TFFL_Msk (_U_(0x3F) << MCAN_TXFQS_TFFL_Pos) /**< (MCAN_TXFQS) Tx FIFO Free Level Mask */ +#define MCAN_TXFQS_TFFL(value) (MCAN_TXFQS_TFFL_Msk & ((value) << MCAN_TXFQS_TFFL_Pos)) +#define MCAN_TXFQS_TFGI_Pos 8 /**< (MCAN_TXFQS) Tx FIFO Get Index Position */ +#define MCAN_TXFQS_TFGI_Msk (_U_(0x1F) << MCAN_TXFQS_TFGI_Pos) /**< (MCAN_TXFQS) Tx FIFO Get Index Mask */ +#define MCAN_TXFQS_TFGI(value) (MCAN_TXFQS_TFGI_Msk & ((value) << MCAN_TXFQS_TFGI_Pos)) +#define MCAN_TXFQS_TFQPI_Pos 16 /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define MCAN_TXFQS_TFQPI_Msk (_U_(0x1F) << MCAN_TXFQS_TFQPI_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define MCAN_TXFQS_TFQPI(value) (MCAN_TXFQS_TFQPI_Msk & ((value) << MCAN_TXFQS_TFQPI_Pos)) +#define MCAN_TXFQS_TFQF_Pos 21 /**< (MCAN_TXFQS) Tx FIFO/Queue Full Position */ +#define MCAN_TXFQS_TFQF_Msk (_U_(0x1) << MCAN_TXFQS_TFQF_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define MCAN_TXFQS_TFQF MCAN_TXFQS_TFQF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXFQS_TFQF_Msk instead */ +#define MCAN_TXFQS_MASK _U_(0x3F1F3F) /**< \deprecated (MCAN_TXFQS) Register MASK (Use MCAN_TXFQS_Msk instead) */ +#define MCAN_TXFQS_Msk _U_(0x3F1F3F) /**< (MCAN_TXFQS) Register Mask */ + + +/* -------- MCAN_TXESC : (MCAN Offset: 0xc8) (R/W 32) Transmit Buffer Element Size Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TBDS:3; /**< bit: 0..2 Tx Buffer Data Field Size */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXESC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXESC_OFFSET (0xC8) /**< (MCAN_TXESC) Transmit Buffer Element Size Configuration Register Offset */ + +#define MCAN_TXESC_TBDS_Pos 0 /**< (MCAN_TXESC) Tx Buffer Data Field Size Position */ +#define MCAN_TXESC_TBDS_Msk (_U_(0x7) << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) Tx Buffer Data Field Size Mask */ +#define MCAN_TXESC_TBDS(value) (MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)) +#define MCAN_TXESC_TBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_TXESC) 48-byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_TXESC) 64-byte data field */ +#define MCAN_TXESC_TBDS_8_BYTE (MCAN_TXESC_TBDS_8_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 8-byte data field Position */ +#define MCAN_TXESC_TBDS_12_BYTE (MCAN_TXESC_TBDS_12_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 12-byte data field Position */ +#define MCAN_TXESC_TBDS_16_BYTE (MCAN_TXESC_TBDS_16_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 16-byte data field Position */ +#define MCAN_TXESC_TBDS_20_BYTE (MCAN_TXESC_TBDS_20_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 20-byte data field Position */ +#define MCAN_TXESC_TBDS_24_BYTE (MCAN_TXESC_TBDS_24_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 24-byte data field Position */ +#define MCAN_TXESC_TBDS_32_BYTE (MCAN_TXESC_TBDS_32_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 32-byte data field Position */ +#define MCAN_TXESC_TBDS_48_BYTE (MCAN_TXESC_TBDS_48_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 48-byte data field Position */ +#define MCAN_TXESC_TBDS_64_BYTE (MCAN_TXESC_TBDS_64_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 64-byte data field Position */ +#define MCAN_TXESC_MASK _U_(0x07) /**< \deprecated (MCAN_TXESC) Register MASK (Use MCAN_TXESC_Msk instead) */ +#define MCAN_TXESC_Msk _U_(0x07) /**< (MCAN_TXESC) Register Mask */ + + +/* -------- MCAN_TXBRP : (MCAN Offset: 0xcc) (R/ 32) Transmit Buffer Request Pending Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TRP0:1; /**< bit: 0 Transmission Request Pending for Buffer 0 */ + uint32_t TRP1:1; /**< bit: 1 Transmission Request Pending for Buffer 1 */ + uint32_t TRP2:1; /**< bit: 2 Transmission Request Pending for Buffer 2 */ + uint32_t TRP3:1; /**< bit: 3 Transmission Request Pending for Buffer 3 */ + uint32_t TRP4:1; /**< bit: 4 Transmission Request Pending for Buffer 4 */ + uint32_t TRP5:1; /**< bit: 5 Transmission Request Pending for Buffer 5 */ + uint32_t TRP6:1; /**< bit: 6 Transmission Request Pending for Buffer 6 */ + uint32_t TRP7:1; /**< bit: 7 Transmission Request Pending for Buffer 7 */ + uint32_t TRP8:1; /**< bit: 8 Transmission Request Pending for Buffer 8 */ + uint32_t TRP9:1; /**< bit: 9 Transmission Request Pending for Buffer 9 */ + uint32_t TRP10:1; /**< bit: 10 Transmission Request Pending for Buffer 10 */ + uint32_t TRP11:1; /**< bit: 11 Transmission Request Pending for Buffer 11 */ + uint32_t TRP12:1; /**< bit: 12 Transmission Request Pending for Buffer 12 */ + uint32_t TRP13:1; /**< bit: 13 Transmission Request Pending for Buffer 13 */ + uint32_t TRP14:1; /**< bit: 14 Transmission Request Pending for Buffer 14 */ + uint32_t TRP15:1; /**< bit: 15 Transmission Request Pending for Buffer 15 */ + uint32_t TRP16:1; /**< bit: 16 Transmission Request Pending for Buffer 16 */ + uint32_t TRP17:1; /**< bit: 17 Transmission Request Pending for Buffer 17 */ + uint32_t TRP18:1; /**< bit: 18 Transmission Request Pending for Buffer 18 */ + uint32_t TRP19:1; /**< bit: 19 Transmission Request Pending for Buffer 19 */ + uint32_t TRP20:1; /**< bit: 20 Transmission Request Pending for Buffer 20 */ + uint32_t TRP21:1; /**< bit: 21 Transmission Request Pending for Buffer 21 */ + uint32_t TRP22:1; /**< bit: 22 Transmission Request Pending for Buffer 22 */ + uint32_t TRP23:1; /**< bit: 23 Transmission Request Pending for Buffer 23 */ + uint32_t TRP24:1; /**< bit: 24 Transmission Request Pending for Buffer 24 */ + uint32_t TRP25:1; /**< bit: 25 Transmission Request Pending for Buffer 25 */ + uint32_t TRP26:1; /**< bit: 26 Transmission Request Pending for Buffer 26 */ + uint32_t TRP27:1; /**< bit: 27 Transmission Request Pending for Buffer 27 */ + uint32_t TRP28:1; /**< bit: 28 Transmission Request Pending for Buffer 28 */ + uint32_t TRP29:1; /**< bit: 29 Transmission Request Pending for Buffer 29 */ + uint32_t TRP30:1; /**< bit: 30 Transmission Request Pending for Buffer 30 */ + uint32_t TRP31:1; /**< bit: 31 Transmission Request Pending for Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TRP:32; /**< bit: 0..31 Transmission Request Pending for Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBRP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBRP_OFFSET (0xCC) /**< (MCAN_TXBRP) Transmit Buffer Request Pending Register Offset */ + +#define MCAN_TXBRP_TRP0_Pos 0 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Position */ +#define MCAN_TXBRP_TRP0_Msk (_U_(0x1) << MCAN_TXBRP_TRP0_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Mask */ +#define MCAN_TXBRP_TRP0 MCAN_TXBRP_TRP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP0_Msk instead */ +#define MCAN_TXBRP_TRP1_Pos 1 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Position */ +#define MCAN_TXBRP_TRP1_Msk (_U_(0x1) << MCAN_TXBRP_TRP1_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Mask */ +#define MCAN_TXBRP_TRP1 MCAN_TXBRP_TRP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP1_Msk instead */ +#define MCAN_TXBRP_TRP2_Pos 2 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Position */ +#define MCAN_TXBRP_TRP2_Msk (_U_(0x1) << MCAN_TXBRP_TRP2_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Mask */ +#define MCAN_TXBRP_TRP2 MCAN_TXBRP_TRP2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP2_Msk instead */ +#define MCAN_TXBRP_TRP3_Pos 3 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Position */ +#define MCAN_TXBRP_TRP3_Msk (_U_(0x1) << MCAN_TXBRP_TRP3_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Mask */ +#define MCAN_TXBRP_TRP3 MCAN_TXBRP_TRP3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP3_Msk instead */ +#define MCAN_TXBRP_TRP4_Pos 4 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Position */ +#define MCAN_TXBRP_TRP4_Msk (_U_(0x1) << MCAN_TXBRP_TRP4_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Mask */ +#define MCAN_TXBRP_TRP4 MCAN_TXBRP_TRP4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP4_Msk instead */ +#define MCAN_TXBRP_TRP5_Pos 5 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Position */ +#define MCAN_TXBRP_TRP5_Msk (_U_(0x1) << MCAN_TXBRP_TRP5_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Mask */ +#define MCAN_TXBRP_TRP5 MCAN_TXBRP_TRP5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP5_Msk instead */ +#define MCAN_TXBRP_TRP6_Pos 6 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Position */ +#define MCAN_TXBRP_TRP6_Msk (_U_(0x1) << MCAN_TXBRP_TRP6_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Mask */ +#define MCAN_TXBRP_TRP6 MCAN_TXBRP_TRP6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP6_Msk instead */ +#define MCAN_TXBRP_TRP7_Pos 7 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Position */ +#define MCAN_TXBRP_TRP7_Msk (_U_(0x1) << MCAN_TXBRP_TRP7_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Mask */ +#define MCAN_TXBRP_TRP7 MCAN_TXBRP_TRP7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP7_Msk instead */ +#define MCAN_TXBRP_TRP8_Pos 8 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Position */ +#define MCAN_TXBRP_TRP8_Msk (_U_(0x1) << MCAN_TXBRP_TRP8_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Mask */ +#define MCAN_TXBRP_TRP8 MCAN_TXBRP_TRP8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP8_Msk instead */ +#define MCAN_TXBRP_TRP9_Pos 9 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Position */ +#define MCAN_TXBRP_TRP9_Msk (_U_(0x1) << MCAN_TXBRP_TRP9_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Mask */ +#define MCAN_TXBRP_TRP9 MCAN_TXBRP_TRP9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP9_Msk instead */ +#define MCAN_TXBRP_TRP10_Pos 10 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Position */ +#define MCAN_TXBRP_TRP10_Msk (_U_(0x1) << MCAN_TXBRP_TRP10_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Mask */ +#define MCAN_TXBRP_TRP10 MCAN_TXBRP_TRP10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP10_Msk instead */ +#define MCAN_TXBRP_TRP11_Pos 11 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Position */ +#define MCAN_TXBRP_TRP11_Msk (_U_(0x1) << MCAN_TXBRP_TRP11_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Mask */ +#define MCAN_TXBRP_TRP11 MCAN_TXBRP_TRP11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP11_Msk instead */ +#define MCAN_TXBRP_TRP12_Pos 12 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Position */ +#define MCAN_TXBRP_TRP12_Msk (_U_(0x1) << MCAN_TXBRP_TRP12_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Mask */ +#define MCAN_TXBRP_TRP12 MCAN_TXBRP_TRP12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP12_Msk instead */ +#define MCAN_TXBRP_TRP13_Pos 13 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Position */ +#define MCAN_TXBRP_TRP13_Msk (_U_(0x1) << MCAN_TXBRP_TRP13_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Mask */ +#define MCAN_TXBRP_TRP13 MCAN_TXBRP_TRP13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP13_Msk instead */ +#define MCAN_TXBRP_TRP14_Pos 14 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Position */ +#define MCAN_TXBRP_TRP14_Msk (_U_(0x1) << MCAN_TXBRP_TRP14_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Mask */ +#define MCAN_TXBRP_TRP14 MCAN_TXBRP_TRP14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP14_Msk instead */ +#define MCAN_TXBRP_TRP15_Pos 15 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Position */ +#define MCAN_TXBRP_TRP15_Msk (_U_(0x1) << MCAN_TXBRP_TRP15_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Mask */ +#define MCAN_TXBRP_TRP15 MCAN_TXBRP_TRP15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP15_Msk instead */ +#define MCAN_TXBRP_TRP16_Pos 16 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Position */ +#define MCAN_TXBRP_TRP16_Msk (_U_(0x1) << MCAN_TXBRP_TRP16_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Mask */ +#define MCAN_TXBRP_TRP16 MCAN_TXBRP_TRP16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP16_Msk instead */ +#define MCAN_TXBRP_TRP17_Pos 17 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Position */ +#define MCAN_TXBRP_TRP17_Msk (_U_(0x1) << MCAN_TXBRP_TRP17_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Mask */ +#define MCAN_TXBRP_TRP17 MCAN_TXBRP_TRP17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP17_Msk instead */ +#define MCAN_TXBRP_TRP18_Pos 18 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Position */ +#define MCAN_TXBRP_TRP18_Msk (_U_(0x1) << MCAN_TXBRP_TRP18_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Mask */ +#define MCAN_TXBRP_TRP18 MCAN_TXBRP_TRP18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP18_Msk instead */ +#define MCAN_TXBRP_TRP19_Pos 19 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Position */ +#define MCAN_TXBRP_TRP19_Msk (_U_(0x1) << MCAN_TXBRP_TRP19_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Mask */ +#define MCAN_TXBRP_TRP19 MCAN_TXBRP_TRP19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP19_Msk instead */ +#define MCAN_TXBRP_TRP20_Pos 20 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Position */ +#define MCAN_TXBRP_TRP20_Msk (_U_(0x1) << MCAN_TXBRP_TRP20_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Mask */ +#define MCAN_TXBRP_TRP20 MCAN_TXBRP_TRP20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP20_Msk instead */ +#define MCAN_TXBRP_TRP21_Pos 21 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Position */ +#define MCAN_TXBRP_TRP21_Msk (_U_(0x1) << MCAN_TXBRP_TRP21_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Mask */ +#define MCAN_TXBRP_TRP21 MCAN_TXBRP_TRP21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP21_Msk instead */ +#define MCAN_TXBRP_TRP22_Pos 22 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Position */ +#define MCAN_TXBRP_TRP22_Msk (_U_(0x1) << MCAN_TXBRP_TRP22_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Mask */ +#define MCAN_TXBRP_TRP22 MCAN_TXBRP_TRP22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP22_Msk instead */ +#define MCAN_TXBRP_TRP23_Pos 23 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Position */ +#define MCAN_TXBRP_TRP23_Msk (_U_(0x1) << MCAN_TXBRP_TRP23_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Mask */ +#define MCAN_TXBRP_TRP23 MCAN_TXBRP_TRP23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP23_Msk instead */ +#define MCAN_TXBRP_TRP24_Pos 24 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Position */ +#define MCAN_TXBRP_TRP24_Msk (_U_(0x1) << MCAN_TXBRP_TRP24_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Mask */ +#define MCAN_TXBRP_TRP24 MCAN_TXBRP_TRP24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP24_Msk instead */ +#define MCAN_TXBRP_TRP25_Pos 25 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Position */ +#define MCAN_TXBRP_TRP25_Msk (_U_(0x1) << MCAN_TXBRP_TRP25_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Mask */ +#define MCAN_TXBRP_TRP25 MCAN_TXBRP_TRP25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP25_Msk instead */ +#define MCAN_TXBRP_TRP26_Pos 26 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Position */ +#define MCAN_TXBRP_TRP26_Msk (_U_(0x1) << MCAN_TXBRP_TRP26_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Mask */ +#define MCAN_TXBRP_TRP26 MCAN_TXBRP_TRP26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP26_Msk instead */ +#define MCAN_TXBRP_TRP27_Pos 27 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Position */ +#define MCAN_TXBRP_TRP27_Msk (_U_(0x1) << MCAN_TXBRP_TRP27_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Mask */ +#define MCAN_TXBRP_TRP27 MCAN_TXBRP_TRP27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP27_Msk instead */ +#define MCAN_TXBRP_TRP28_Pos 28 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Position */ +#define MCAN_TXBRP_TRP28_Msk (_U_(0x1) << MCAN_TXBRP_TRP28_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Mask */ +#define MCAN_TXBRP_TRP28 MCAN_TXBRP_TRP28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP28_Msk instead */ +#define MCAN_TXBRP_TRP29_Pos 29 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Position */ +#define MCAN_TXBRP_TRP29_Msk (_U_(0x1) << MCAN_TXBRP_TRP29_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Mask */ +#define MCAN_TXBRP_TRP29 MCAN_TXBRP_TRP29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP29_Msk instead */ +#define MCAN_TXBRP_TRP30_Pos 30 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Position */ +#define MCAN_TXBRP_TRP30_Msk (_U_(0x1) << MCAN_TXBRP_TRP30_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Mask */ +#define MCAN_TXBRP_TRP30 MCAN_TXBRP_TRP30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP30_Msk instead */ +#define MCAN_TXBRP_TRP31_Pos 31 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Position */ +#define MCAN_TXBRP_TRP31_Msk (_U_(0x1) << MCAN_TXBRP_TRP31_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Mask */ +#define MCAN_TXBRP_TRP31 MCAN_TXBRP_TRP31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP31_Msk instead */ +#define MCAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBRP) Register MASK (Use MCAN_TXBRP_Msk instead) */ +#define MCAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBRP) Register Mask */ + +#define MCAN_TXBRP_TRP_Pos 0 /**< (MCAN_TXBRP Position) Transmission Request Pending for Buffer 3x */ +#define MCAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << MCAN_TXBRP_TRP_Pos) /**< (MCAN_TXBRP Mask) TRP */ +#define MCAN_TXBRP_TRP(value) (MCAN_TXBRP_TRP_Msk & ((value) << MCAN_TXBRP_TRP_Pos)) + +/* -------- MCAN_TXBAR : (MCAN Offset: 0xd0) (R/W 32) Transmit Buffer Add Request Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t AR0:1; /**< bit: 0 Add Request for Transmit Buffer 0 */ + uint32_t AR1:1; /**< bit: 1 Add Request for Transmit Buffer 1 */ + uint32_t AR2:1; /**< bit: 2 Add Request for Transmit Buffer 2 */ + uint32_t AR3:1; /**< bit: 3 Add Request for Transmit Buffer 3 */ + uint32_t AR4:1; /**< bit: 4 Add Request for Transmit Buffer 4 */ + uint32_t AR5:1; /**< bit: 5 Add Request for Transmit Buffer 5 */ + uint32_t AR6:1; /**< bit: 6 Add Request for Transmit Buffer 6 */ + uint32_t AR7:1; /**< bit: 7 Add Request for Transmit Buffer 7 */ + uint32_t AR8:1; /**< bit: 8 Add Request for Transmit Buffer 8 */ + uint32_t AR9:1; /**< bit: 9 Add Request for Transmit Buffer 9 */ + uint32_t AR10:1; /**< bit: 10 Add Request for Transmit Buffer 10 */ + uint32_t AR11:1; /**< bit: 11 Add Request for Transmit Buffer 11 */ + uint32_t AR12:1; /**< bit: 12 Add Request for Transmit Buffer 12 */ + uint32_t AR13:1; /**< bit: 13 Add Request for Transmit Buffer 13 */ + uint32_t AR14:1; /**< bit: 14 Add Request for Transmit Buffer 14 */ + uint32_t AR15:1; /**< bit: 15 Add Request for Transmit Buffer 15 */ + uint32_t AR16:1; /**< bit: 16 Add Request for Transmit Buffer 16 */ + uint32_t AR17:1; /**< bit: 17 Add Request for Transmit Buffer 17 */ + uint32_t AR18:1; /**< bit: 18 Add Request for Transmit Buffer 18 */ + uint32_t AR19:1; /**< bit: 19 Add Request for Transmit Buffer 19 */ + uint32_t AR20:1; /**< bit: 20 Add Request for Transmit Buffer 20 */ + uint32_t AR21:1; /**< bit: 21 Add Request for Transmit Buffer 21 */ + uint32_t AR22:1; /**< bit: 22 Add Request for Transmit Buffer 22 */ + uint32_t AR23:1; /**< bit: 23 Add Request for Transmit Buffer 23 */ + uint32_t AR24:1; /**< bit: 24 Add Request for Transmit Buffer 24 */ + uint32_t AR25:1; /**< bit: 25 Add Request for Transmit Buffer 25 */ + uint32_t AR26:1; /**< bit: 26 Add Request for Transmit Buffer 26 */ + uint32_t AR27:1; /**< bit: 27 Add Request for Transmit Buffer 27 */ + uint32_t AR28:1; /**< bit: 28 Add Request for Transmit Buffer 28 */ + uint32_t AR29:1; /**< bit: 29 Add Request for Transmit Buffer 29 */ + uint32_t AR30:1; /**< bit: 30 Add Request for Transmit Buffer 30 */ + uint32_t AR31:1; /**< bit: 31 Add Request for Transmit Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t AR:32; /**< bit: 0..31 Add Request for Transmit Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBAR_OFFSET (0xD0) /**< (MCAN_TXBAR) Transmit Buffer Add Request Register Offset */ + +#define MCAN_TXBAR_AR0_Pos 0 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Position */ +#define MCAN_TXBAR_AR0_Msk (_U_(0x1) << MCAN_TXBAR_AR0_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBAR_AR0 MCAN_TXBAR_AR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR0_Msk instead */ +#define MCAN_TXBAR_AR1_Pos 1 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Position */ +#define MCAN_TXBAR_AR1_Msk (_U_(0x1) << MCAN_TXBAR_AR1_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBAR_AR1 MCAN_TXBAR_AR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR1_Msk instead */ +#define MCAN_TXBAR_AR2_Pos 2 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Position */ +#define MCAN_TXBAR_AR2_Msk (_U_(0x1) << MCAN_TXBAR_AR2_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBAR_AR2 MCAN_TXBAR_AR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR2_Msk instead */ +#define MCAN_TXBAR_AR3_Pos 3 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Position */ +#define MCAN_TXBAR_AR3_Msk (_U_(0x1) << MCAN_TXBAR_AR3_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBAR_AR3 MCAN_TXBAR_AR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR3_Msk instead */ +#define MCAN_TXBAR_AR4_Pos 4 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Position */ +#define MCAN_TXBAR_AR4_Msk (_U_(0x1) << MCAN_TXBAR_AR4_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBAR_AR4 MCAN_TXBAR_AR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR4_Msk instead */ +#define MCAN_TXBAR_AR5_Pos 5 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Position */ +#define MCAN_TXBAR_AR5_Msk (_U_(0x1) << MCAN_TXBAR_AR5_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBAR_AR5 MCAN_TXBAR_AR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR5_Msk instead */ +#define MCAN_TXBAR_AR6_Pos 6 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Position */ +#define MCAN_TXBAR_AR6_Msk (_U_(0x1) << MCAN_TXBAR_AR6_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBAR_AR6 MCAN_TXBAR_AR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR6_Msk instead */ +#define MCAN_TXBAR_AR7_Pos 7 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Position */ +#define MCAN_TXBAR_AR7_Msk (_U_(0x1) << MCAN_TXBAR_AR7_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBAR_AR7 MCAN_TXBAR_AR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR7_Msk instead */ +#define MCAN_TXBAR_AR8_Pos 8 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Position */ +#define MCAN_TXBAR_AR8_Msk (_U_(0x1) << MCAN_TXBAR_AR8_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBAR_AR8 MCAN_TXBAR_AR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR8_Msk instead */ +#define MCAN_TXBAR_AR9_Pos 9 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Position */ +#define MCAN_TXBAR_AR9_Msk (_U_(0x1) << MCAN_TXBAR_AR9_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBAR_AR9 MCAN_TXBAR_AR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR9_Msk instead */ +#define MCAN_TXBAR_AR10_Pos 10 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Position */ +#define MCAN_TXBAR_AR10_Msk (_U_(0x1) << MCAN_TXBAR_AR10_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBAR_AR10 MCAN_TXBAR_AR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR10_Msk instead */ +#define MCAN_TXBAR_AR11_Pos 11 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Position */ +#define MCAN_TXBAR_AR11_Msk (_U_(0x1) << MCAN_TXBAR_AR11_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBAR_AR11 MCAN_TXBAR_AR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR11_Msk instead */ +#define MCAN_TXBAR_AR12_Pos 12 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Position */ +#define MCAN_TXBAR_AR12_Msk (_U_(0x1) << MCAN_TXBAR_AR12_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBAR_AR12 MCAN_TXBAR_AR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR12_Msk instead */ +#define MCAN_TXBAR_AR13_Pos 13 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Position */ +#define MCAN_TXBAR_AR13_Msk (_U_(0x1) << MCAN_TXBAR_AR13_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBAR_AR13 MCAN_TXBAR_AR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR13_Msk instead */ +#define MCAN_TXBAR_AR14_Pos 14 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Position */ +#define MCAN_TXBAR_AR14_Msk (_U_(0x1) << MCAN_TXBAR_AR14_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBAR_AR14 MCAN_TXBAR_AR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR14_Msk instead */ +#define MCAN_TXBAR_AR15_Pos 15 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Position */ +#define MCAN_TXBAR_AR15_Msk (_U_(0x1) << MCAN_TXBAR_AR15_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBAR_AR15 MCAN_TXBAR_AR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR15_Msk instead */ +#define MCAN_TXBAR_AR16_Pos 16 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Position */ +#define MCAN_TXBAR_AR16_Msk (_U_(0x1) << MCAN_TXBAR_AR16_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBAR_AR16 MCAN_TXBAR_AR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR16_Msk instead */ +#define MCAN_TXBAR_AR17_Pos 17 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Position */ +#define MCAN_TXBAR_AR17_Msk (_U_(0x1) << MCAN_TXBAR_AR17_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBAR_AR17 MCAN_TXBAR_AR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR17_Msk instead */ +#define MCAN_TXBAR_AR18_Pos 18 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Position */ +#define MCAN_TXBAR_AR18_Msk (_U_(0x1) << MCAN_TXBAR_AR18_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBAR_AR18 MCAN_TXBAR_AR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR18_Msk instead */ +#define MCAN_TXBAR_AR19_Pos 19 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Position */ +#define MCAN_TXBAR_AR19_Msk (_U_(0x1) << MCAN_TXBAR_AR19_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBAR_AR19 MCAN_TXBAR_AR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR19_Msk instead */ +#define MCAN_TXBAR_AR20_Pos 20 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Position */ +#define MCAN_TXBAR_AR20_Msk (_U_(0x1) << MCAN_TXBAR_AR20_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBAR_AR20 MCAN_TXBAR_AR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR20_Msk instead */ +#define MCAN_TXBAR_AR21_Pos 21 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Position */ +#define MCAN_TXBAR_AR21_Msk (_U_(0x1) << MCAN_TXBAR_AR21_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBAR_AR21 MCAN_TXBAR_AR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR21_Msk instead */ +#define MCAN_TXBAR_AR22_Pos 22 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Position */ +#define MCAN_TXBAR_AR22_Msk (_U_(0x1) << MCAN_TXBAR_AR22_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBAR_AR22 MCAN_TXBAR_AR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR22_Msk instead */ +#define MCAN_TXBAR_AR23_Pos 23 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Position */ +#define MCAN_TXBAR_AR23_Msk (_U_(0x1) << MCAN_TXBAR_AR23_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBAR_AR23 MCAN_TXBAR_AR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR23_Msk instead */ +#define MCAN_TXBAR_AR24_Pos 24 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Position */ +#define MCAN_TXBAR_AR24_Msk (_U_(0x1) << MCAN_TXBAR_AR24_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBAR_AR24 MCAN_TXBAR_AR24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR24_Msk instead */ +#define MCAN_TXBAR_AR25_Pos 25 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Position */ +#define MCAN_TXBAR_AR25_Msk (_U_(0x1) << MCAN_TXBAR_AR25_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBAR_AR25 MCAN_TXBAR_AR25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR25_Msk instead */ +#define MCAN_TXBAR_AR26_Pos 26 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Position */ +#define MCAN_TXBAR_AR26_Msk (_U_(0x1) << MCAN_TXBAR_AR26_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBAR_AR26 MCAN_TXBAR_AR26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR26_Msk instead */ +#define MCAN_TXBAR_AR27_Pos 27 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Position */ +#define MCAN_TXBAR_AR27_Msk (_U_(0x1) << MCAN_TXBAR_AR27_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBAR_AR27 MCAN_TXBAR_AR27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR27_Msk instead */ +#define MCAN_TXBAR_AR28_Pos 28 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Position */ +#define MCAN_TXBAR_AR28_Msk (_U_(0x1) << MCAN_TXBAR_AR28_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBAR_AR28 MCAN_TXBAR_AR28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR28_Msk instead */ +#define MCAN_TXBAR_AR29_Pos 29 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Position */ +#define MCAN_TXBAR_AR29_Msk (_U_(0x1) << MCAN_TXBAR_AR29_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBAR_AR29 MCAN_TXBAR_AR29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR29_Msk instead */ +#define MCAN_TXBAR_AR30_Pos 30 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Position */ +#define MCAN_TXBAR_AR30_Msk (_U_(0x1) << MCAN_TXBAR_AR30_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBAR_AR30 MCAN_TXBAR_AR30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR30_Msk instead */ +#define MCAN_TXBAR_AR31_Pos 31 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Position */ +#define MCAN_TXBAR_AR31_Msk (_U_(0x1) << MCAN_TXBAR_AR31_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBAR_AR31 MCAN_TXBAR_AR31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR31_Msk instead */ +#define MCAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBAR) Register MASK (Use MCAN_TXBAR_Msk instead) */ +#define MCAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBAR) Register Mask */ + +#define MCAN_TXBAR_AR_Pos 0 /**< (MCAN_TXBAR Position) Add Request for Transmit Buffer 3x */ +#define MCAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBAR_AR_Pos) /**< (MCAN_TXBAR Mask) AR */ +#define MCAN_TXBAR_AR(value) (MCAN_TXBAR_AR_Msk & ((value) << MCAN_TXBAR_AR_Pos)) + +/* -------- MCAN_TXBCR : (MCAN Offset: 0xd4) (R/W 32) Transmit Buffer Cancellation Request Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CR0:1; /**< bit: 0 Cancellation Request for Transmit Buffer 0 */ + uint32_t CR1:1; /**< bit: 1 Cancellation Request for Transmit Buffer 1 */ + uint32_t CR2:1; /**< bit: 2 Cancellation Request for Transmit Buffer 2 */ + uint32_t CR3:1; /**< bit: 3 Cancellation Request for Transmit Buffer 3 */ + uint32_t CR4:1; /**< bit: 4 Cancellation Request for Transmit Buffer 4 */ + uint32_t CR5:1; /**< bit: 5 Cancellation Request for Transmit Buffer 5 */ + uint32_t CR6:1; /**< bit: 6 Cancellation Request for Transmit Buffer 6 */ + uint32_t CR7:1; /**< bit: 7 Cancellation Request for Transmit Buffer 7 */ + uint32_t CR8:1; /**< bit: 8 Cancellation Request for Transmit Buffer 8 */ + uint32_t CR9:1; /**< bit: 9 Cancellation Request for Transmit Buffer 9 */ + uint32_t CR10:1; /**< bit: 10 Cancellation Request for Transmit Buffer 10 */ + uint32_t CR11:1; /**< bit: 11 Cancellation Request for Transmit Buffer 11 */ + uint32_t CR12:1; /**< bit: 12 Cancellation Request for Transmit Buffer 12 */ + uint32_t CR13:1; /**< bit: 13 Cancellation Request for Transmit Buffer 13 */ + uint32_t CR14:1; /**< bit: 14 Cancellation Request for Transmit Buffer 14 */ + uint32_t CR15:1; /**< bit: 15 Cancellation Request for Transmit Buffer 15 */ + uint32_t CR16:1; /**< bit: 16 Cancellation Request for Transmit Buffer 16 */ + uint32_t CR17:1; /**< bit: 17 Cancellation Request for Transmit Buffer 17 */ + uint32_t CR18:1; /**< bit: 18 Cancellation Request for Transmit Buffer 18 */ + uint32_t CR19:1; /**< bit: 19 Cancellation Request for Transmit Buffer 19 */ + uint32_t CR20:1; /**< bit: 20 Cancellation Request for Transmit Buffer 20 */ + uint32_t CR21:1; /**< bit: 21 Cancellation Request for Transmit Buffer 21 */ + uint32_t CR22:1; /**< bit: 22 Cancellation Request for Transmit Buffer 22 */ + uint32_t CR23:1; /**< bit: 23 Cancellation Request for Transmit Buffer 23 */ + uint32_t CR24:1; /**< bit: 24 Cancellation Request for Transmit Buffer 24 */ + uint32_t CR25:1; /**< bit: 25 Cancellation Request for Transmit Buffer 25 */ + uint32_t CR26:1; /**< bit: 26 Cancellation Request for Transmit Buffer 26 */ + uint32_t CR27:1; /**< bit: 27 Cancellation Request for Transmit Buffer 27 */ + uint32_t CR28:1; /**< bit: 28 Cancellation Request for Transmit Buffer 28 */ + uint32_t CR29:1; /**< bit: 29 Cancellation Request for Transmit Buffer 29 */ + uint32_t CR30:1; /**< bit: 30 Cancellation Request for Transmit Buffer 30 */ + uint32_t CR31:1; /**< bit: 31 Cancellation Request for Transmit Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CR:32; /**< bit: 0..31 Cancellation Request for Transmit Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBCR_OFFSET (0xD4) /**< (MCAN_TXBCR) Transmit Buffer Cancellation Request Register Offset */ + +#define MCAN_TXBCR_CR0_Pos 0 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Position */ +#define MCAN_TXBCR_CR0_Msk (_U_(0x1) << MCAN_TXBCR_CR0_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBCR_CR0 MCAN_TXBCR_CR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR0_Msk instead */ +#define MCAN_TXBCR_CR1_Pos 1 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Position */ +#define MCAN_TXBCR_CR1_Msk (_U_(0x1) << MCAN_TXBCR_CR1_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBCR_CR1 MCAN_TXBCR_CR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR1_Msk instead */ +#define MCAN_TXBCR_CR2_Pos 2 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Position */ +#define MCAN_TXBCR_CR2_Msk (_U_(0x1) << MCAN_TXBCR_CR2_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBCR_CR2 MCAN_TXBCR_CR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR2_Msk instead */ +#define MCAN_TXBCR_CR3_Pos 3 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Position */ +#define MCAN_TXBCR_CR3_Msk (_U_(0x1) << MCAN_TXBCR_CR3_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBCR_CR3 MCAN_TXBCR_CR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR3_Msk instead */ +#define MCAN_TXBCR_CR4_Pos 4 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Position */ +#define MCAN_TXBCR_CR4_Msk (_U_(0x1) << MCAN_TXBCR_CR4_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBCR_CR4 MCAN_TXBCR_CR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR4_Msk instead */ +#define MCAN_TXBCR_CR5_Pos 5 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Position */ +#define MCAN_TXBCR_CR5_Msk (_U_(0x1) << MCAN_TXBCR_CR5_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBCR_CR5 MCAN_TXBCR_CR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR5_Msk instead */ +#define MCAN_TXBCR_CR6_Pos 6 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Position */ +#define MCAN_TXBCR_CR6_Msk (_U_(0x1) << MCAN_TXBCR_CR6_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBCR_CR6 MCAN_TXBCR_CR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR6_Msk instead */ +#define MCAN_TXBCR_CR7_Pos 7 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Position */ +#define MCAN_TXBCR_CR7_Msk (_U_(0x1) << MCAN_TXBCR_CR7_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBCR_CR7 MCAN_TXBCR_CR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR7_Msk instead */ +#define MCAN_TXBCR_CR8_Pos 8 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Position */ +#define MCAN_TXBCR_CR8_Msk (_U_(0x1) << MCAN_TXBCR_CR8_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBCR_CR8 MCAN_TXBCR_CR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR8_Msk instead */ +#define MCAN_TXBCR_CR9_Pos 9 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Position */ +#define MCAN_TXBCR_CR9_Msk (_U_(0x1) << MCAN_TXBCR_CR9_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBCR_CR9 MCAN_TXBCR_CR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR9_Msk instead */ +#define MCAN_TXBCR_CR10_Pos 10 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Position */ +#define MCAN_TXBCR_CR10_Msk (_U_(0x1) << MCAN_TXBCR_CR10_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBCR_CR10 MCAN_TXBCR_CR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR10_Msk instead */ +#define MCAN_TXBCR_CR11_Pos 11 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Position */ +#define MCAN_TXBCR_CR11_Msk (_U_(0x1) << MCAN_TXBCR_CR11_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBCR_CR11 MCAN_TXBCR_CR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR11_Msk instead */ +#define MCAN_TXBCR_CR12_Pos 12 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Position */ +#define MCAN_TXBCR_CR12_Msk (_U_(0x1) << MCAN_TXBCR_CR12_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBCR_CR12 MCAN_TXBCR_CR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR12_Msk instead */ +#define MCAN_TXBCR_CR13_Pos 13 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Position */ +#define MCAN_TXBCR_CR13_Msk (_U_(0x1) << MCAN_TXBCR_CR13_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBCR_CR13 MCAN_TXBCR_CR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR13_Msk instead */ +#define MCAN_TXBCR_CR14_Pos 14 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Position */ +#define MCAN_TXBCR_CR14_Msk (_U_(0x1) << MCAN_TXBCR_CR14_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBCR_CR14 MCAN_TXBCR_CR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR14_Msk instead */ +#define MCAN_TXBCR_CR15_Pos 15 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Position */ +#define MCAN_TXBCR_CR15_Msk (_U_(0x1) << MCAN_TXBCR_CR15_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBCR_CR15 MCAN_TXBCR_CR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR15_Msk instead */ +#define MCAN_TXBCR_CR16_Pos 16 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Position */ +#define MCAN_TXBCR_CR16_Msk (_U_(0x1) << MCAN_TXBCR_CR16_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBCR_CR16 MCAN_TXBCR_CR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR16_Msk instead */ +#define MCAN_TXBCR_CR17_Pos 17 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Position */ +#define MCAN_TXBCR_CR17_Msk (_U_(0x1) << MCAN_TXBCR_CR17_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBCR_CR17 MCAN_TXBCR_CR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR17_Msk instead */ +#define MCAN_TXBCR_CR18_Pos 18 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Position */ +#define MCAN_TXBCR_CR18_Msk (_U_(0x1) << MCAN_TXBCR_CR18_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBCR_CR18 MCAN_TXBCR_CR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR18_Msk instead */ +#define MCAN_TXBCR_CR19_Pos 19 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Position */ +#define MCAN_TXBCR_CR19_Msk (_U_(0x1) << MCAN_TXBCR_CR19_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBCR_CR19 MCAN_TXBCR_CR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR19_Msk instead */ +#define MCAN_TXBCR_CR20_Pos 20 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Position */ +#define MCAN_TXBCR_CR20_Msk (_U_(0x1) << MCAN_TXBCR_CR20_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBCR_CR20 MCAN_TXBCR_CR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR20_Msk instead */ +#define MCAN_TXBCR_CR21_Pos 21 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Position */ +#define MCAN_TXBCR_CR21_Msk (_U_(0x1) << MCAN_TXBCR_CR21_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBCR_CR21 MCAN_TXBCR_CR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR21_Msk instead */ +#define MCAN_TXBCR_CR22_Pos 22 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Position */ +#define MCAN_TXBCR_CR22_Msk (_U_(0x1) << MCAN_TXBCR_CR22_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBCR_CR22 MCAN_TXBCR_CR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR22_Msk instead */ +#define MCAN_TXBCR_CR23_Pos 23 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Position */ +#define MCAN_TXBCR_CR23_Msk (_U_(0x1) << MCAN_TXBCR_CR23_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBCR_CR23 MCAN_TXBCR_CR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR23_Msk instead */ +#define MCAN_TXBCR_CR24_Pos 24 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Position */ +#define MCAN_TXBCR_CR24_Msk (_U_(0x1) << MCAN_TXBCR_CR24_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBCR_CR24 MCAN_TXBCR_CR24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR24_Msk instead */ +#define MCAN_TXBCR_CR25_Pos 25 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Position */ +#define MCAN_TXBCR_CR25_Msk (_U_(0x1) << MCAN_TXBCR_CR25_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBCR_CR25 MCAN_TXBCR_CR25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR25_Msk instead */ +#define MCAN_TXBCR_CR26_Pos 26 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Position */ +#define MCAN_TXBCR_CR26_Msk (_U_(0x1) << MCAN_TXBCR_CR26_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBCR_CR26 MCAN_TXBCR_CR26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR26_Msk instead */ +#define MCAN_TXBCR_CR27_Pos 27 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Position */ +#define MCAN_TXBCR_CR27_Msk (_U_(0x1) << MCAN_TXBCR_CR27_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBCR_CR27 MCAN_TXBCR_CR27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR27_Msk instead */ +#define MCAN_TXBCR_CR28_Pos 28 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Position */ +#define MCAN_TXBCR_CR28_Msk (_U_(0x1) << MCAN_TXBCR_CR28_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBCR_CR28 MCAN_TXBCR_CR28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR28_Msk instead */ +#define MCAN_TXBCR_CR29_Pos 29 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Position */ +#define MCAN_TXBCR_CR29_Msk (_U_(0x1) << MCAN_TXBCR_CR29_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBCR_CR29 MCAN_TXBCR_CR29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR29_Msk instead */ +#define MCAN_TXBCR_CR30_Pos 30 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Position */ +#define MCAN_TXBCR_CR30_Msk (_U_(0x1) << MCAN_TXBCR_CR30_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBCR_CR30 MCAN_TXBCR_CR30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR30_Msk instead */ +#define MCAN_TXBCR_CR31_Pos 31 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Position */ +#define MCAN_TXBCR_CR31_Msk (_U_(0x1) << MCAN_TXBCR_CR31_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBCR_CR31 MCAN_TXBCR_CR31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR31_Msk instead */ +#define MCAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCR) Register MASK (Use MCAN_TXBCR_Msk instead) */ +#define MCAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCR) Register Mask */ + +#define MCAN_TXBCR_CR_Pos 0 /**< (MCAN_TXBCR Position) Cancellation Request for Transmit Buffer 3x */ +#define MCAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCR_CR_Pos) /**< (MCAN_TXBCR Mask) CR */ +#define MCAN_TXBCR_CR(value) (MCAN_TXBCR_CR_Msk & ((value) << MCAN_TXBCR_CR_Pos)) + +/* -------- MCAN_TXBTO : (MCAN Offset: 0xd8) (R/ 32) Transmit Buffer Transmission Occurred Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TO0:1; /**< bit: 0 Transmission Occurred for Buffer 0 */ + uint32_t TO1:1; /**< bit: 1 Transmission Occurred for Buffer 1 */ + uint32_t TO2:1; /**< bit: 2 Transmission Occurred for Buffer 2 */ + uint32_t TO3:1; /**< bit: 3 Transmission Occurred for Buffer 3 */ + uint32_t TO4:1; /**< bit: 4 Transmission Occurred for Buffer 4 */ + uint32_t TO5:1; /**< bit: 5 Transmission Occurred for Buffer 5 */ + uint32_t TO6:1; /**< bit: 6 Transmission Occurred for Buffer 6 */ + uint32_t TO7:1; /**< bit: 7 Transmission Occurred for Buffer 7 */ + uint32_t TO8:1; /**< bit: 8 Transmission Occurred for Buffer 8 */ + uint32_t TO9:1; /**< bit: 9 Transmission Occurred for Buffer 9 */ + uint32_t TO10:1; /**< bit: 10 Transmission Occurred for Buffer 10 */ + uint32_t TO11:1; /**< bit: 11 Transmission Occurred for Buffer 11 */ + uint32_t TO12:1; /**< bit: 12 Transmission Occurred for Buffer 12 */ + uint32_t TO13:1; /**< bit: 13 Transmission Occurred for Buffer 13 */ + uint32_t TO14:1; /**< bit: 14 Transmission Occurred for Buffer 14 */ + uint32_t TO15:1; /**< bit: 15 Transmission Occurred for Buffer 15 */ + uint32_t TO16:1; /**< bit: 16 Transmission Occurred for Buffer 16 */ + uint32_t TO17:1; /**< bit: 17 Transmission Occurred for Buffer 17 */ + uint32_t TO18:1; /**< bit: 18 Transmission Occurred for Buffer 18 */ + uint32_t TO19:1; /**< bit: 19 Transmission Occurred for Buffer 19 */ + uint32_t TO20:1; /**< bit: 20 Transmission Occurred for Buffer 20 */ + uint32_t TO21:1; /**< bit: 21 Transmission Occurred for Buffer 21 */ + uint32_t TO22:1; /**< bit: 22 Transmission Occurred for Buffer 22 */ + uint32_t TO23:1; /**< bit: 23 Transmission Occurred for Buffer 23 */ + uint32_t TO24:1; /**< bit: 24 Transmission Occurred for Buffer 24 */ + uint32_t TO25:1; /**< bit: 25 Transmission Occurred for Buffer 25 */ + uint32_t TO26:1; /**< bit: 26 Transmission Occurred for Buffer 26 */ + uint32_t TO27:1; /**< bit: 27 Transmission Occurred for Buffer 27 */ + uint32_t TO28:1; /**< bit: 28 Transmission Occurred for Buffer 28 */ + uint32_t TO29:1; /**< bit: 29 Transmission Occurred for Buffer 29 */ + uint32_t TO30:1; /**< bit: 30 Transmission Occurred for Buffer 30 */ + uint32_t TO31:1; /**< bit: 31 Transmission Occurred for Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TO:32; /**< bit: 0..31 Transmission Occurred for Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBTO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBTO_OFFSET (0xD8) /**< (MCAN_TXBTO) Transmit Buffer Transmission Occurred Register Offset */ + +#define MCAN_TXBTO_TO0_Pos 0 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Position */ +#define MCAN_TXBTO_TO0_Msk (_U_(0x1) << MCAN_TXBTO_TO0_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Mask */ +#define MCAN_TXBTO_TO0 MCAN_TXBTO_TO0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO0_Msk instead */ +#define MCAN_TXBTO_TO1_Pos 1 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Position */ +#define MCAN_TXBTO_TO1_Msk (_U_(0x1) << MCAN_TXBTO_TO1_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Mask */ +#define MCAN_TXBTO_TO1 MCAN_TXBTO_TO1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO1_Msk instead */ +#define MCAN_TXBTO_TO2_Pos 2 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Position */ +#define MCAN_TXBTO_TO2_Msk (_U_(0x1) << MCAN_TXBTO_TO2_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Mask */ +#define MCAN_TXBTO_TO2 MCAN_TXBTO_TO2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO2_Msk instead */ +#define MCAN_TXBTO_TO3_Pos 3 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Position */ +#define MCAN_TXBTO_TO3_Msk (_U_(0x1) << MCAN_TXBTO_TO3_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Mask */ +#define MCAN_TXBTO_TO3 MCAN_TXBTO_TO3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO3_Msk instead */ +#define MCAN_TXBTO_TO4_Pos 4 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Position */ +#define MCAN_TXBTO_TO4_Msk (_U_(0x1) << MCAN_TXBTO_TO4_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Mask */ +#define MCAN_TXBTO_TO4 MCAN_TXBTO_TO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO4_Msk instead */ +#define MCAN_TXBTO_TO5_Pos 5 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Position */ +#define MCAN_TXBTO_TO5_Msk (_U_(0x1) << MCAN_TXBTO_TO5_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Mask */ +#define MCAN_TXBTO_TO5 MCAN_TXBTO_TO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO5_Msk instead */ +#define MCAN_TXBTO_TO6_Pos 6 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Position */ +#define MCAN_TXBTO_TO6_Msk (_U_(0x1) << MCAN_TXBTO_TO6_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Mask */ +#define MCAN_TXBTO_TO6 MCAN_TXBTO_TO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO6_Msk instead */ +#define MCAN_TXBTO_TO7_Pos 7 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Position */ +#define MCAN_TXBTO_TO7_Msk (_U_(0x1) << MCAN_TXBTO_TO7_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Mask */ +#define MCAN_TXBTO_TO7 MCAN_TXBTO_TO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO7_Msk instead */ +#define MCAN_TXBTO_TO8_Pos 8 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Position */ +#define MCAN_TXBTO_TO8_Msk (_U_(0x1) << MCAN_TXBTO_TO8_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Mask */ +#define MCAN_TXBTO_TO8 MCAN_TXBTO_TO8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO8_Msk instead */ +#define MCAN_TXBTO_TO9_Pos 9 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Position */ +#define MCAN_TXBTO_TO9_Msk (_U_(0x1) << MCAN_TXBTO_TO9_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Mask */ +#define MCAN_TXBTO_TO9 MCAN_TXBTO_TO9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO9_Msk instead */ +#define MCAN_TXBTO_TO10_Pos 10 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Position */ +#define MCAN_TXBTO_TO10_Msk (_U_(0x1) << MCAN_TXBTO_TO10_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Mask */ +#define MCAN_TXBTO_TO10 MCAN_TXBTO_TO10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO10_Msk instead */ +#define MCAN_TXBTO_TO11_Pos 11 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Position */ +#define MCAN_TXBTO_TO11_Msk (_U_(0x1) << MCAN_TXBTO_TO11_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Mask */ +#define MCAN_TXBTO_TO11 MCAN_TXBTO_TO11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO11_Msk instead */ +#define MCAN_TXBTO_TO12_Pos 12 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Position */ +#define MCAN_TXBTO_TO12_Msk (_U_(0x1) << MCAN_TXBTO_TO12_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Mask */ +#define MCAN_TXBTO_TO12 MCAN_TXBTO_TO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO12_Msk instead */ +#define MCAN_TXBTO_TO13_Pos 13 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Position */ +#define MCAN_TXBTO_TO13_Msk (_U_(0x1) << MCAN_TXBTO_TO13_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Mask */ +#define MCAN_TXBTO_TO13 MCAN_TXBTO_TO13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO13_Msk instead */ +#define MCAN_TXBTO_TO14_Pos 14 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Position */ +#define MCAN_TXBTO_TO14_Msk (_U_(0x1) << MCAN_TXBTO_TO14_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Mask */ +#define MCAN_TXBTO_TO14 MCAN_TXBTO_TO14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO14_Msk instead */ +#define MCAN_TXBTO_TO15_Pos 15 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Position */ +#define MCAN_TXBTO_TO15_Msk (_U_(0x1) << MCAN_TXBTO_TO15_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Mask */ +#define MCAN_TXBTO_TO15 MCAN_TXBTO_TO15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO15_Msk instead */ +#define MCAN_TXBTO_TO16_Pos 16 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Position */ +#define MCAN_TXBTO_TO16_Msk (_U_(0x1) << MCAN_TXBTO_TO16_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Mask */ +#define MCAN_TXBTO_TO16 MCAN_TXBTO_TO16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO16_Msk instead */ +#define MCAN_TXBTO_TO17_Pos 17 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Position */ +#define MCAN_TXBTO_TO17_Msk (_U_(0x1) << MCAN_TXBTO_TO17_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Mask */ +#define MCAN_TXBTO_TO17 MCAN_TXBTO_TO17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO17_Msk instead */ +#define MCAN_TXBTO_TO18_Pos 18 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Position */ +#define MCAN_TXBTO_TO18_Msk (_U_(0x1) << MCAN_TXBTO_TO18_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Mask */ +#define MCAN_TXBTO_TO18 MCAN_TXBTO_TO18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO18_Msk instead */ +#define MCAN_TXBTO_TO19_Pos 19 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Position */ +#define MCAN_TXBTO_TO19_Msk (_U_(0x1) << MCAN_TXBTO_TO19_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Mask */ +#define MCAN_TXBTO_TO19 MCAN_TXBTO_TO19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO19_Msk instead */ +#define MCAN_TXBTO_TO20_Pos 20 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Position */ +#define MCAN_TXBTO_TO20_Msk (_U_(0x1) << MCAN_TXBTO_TO20_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Mask */ +#define MCAN_TXBTO_TO20 MCAN_TXBTO_TO20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO20_Msk instead */ +#define MCAN_TXBTO_TO21_Pos 21 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Position */ +#define MCAN_TXBTO_TO21_Msk (_U_(0x1) << MCAN_TXBTO_TO21_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Mask */ +#define MCAN_TXBTO_TO21 MCAN_TXBTO_TO21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO21_Msk instead */ +#define MCAN_TXBTO_TO22_Pos 22 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Position */ +#define MCAN_TXBTO_TO22_Msk (_U_(0x1) << MCAN_TXBTO_TO22_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Mask */ +#define MCAN_TXBTO_TO22 MCAN_TXBTO_TO22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO22_Msk instead */ +#define MCAN_TXBTO_TO23_Pos 23 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Position */ +#define MCAN_TXBTO_TO23_Msk (_U_(0x1) << MCAN_TXBTO_TO23_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Mask */ +#define MCAN_TXBTO_TO23 MCAN_TXBTO_TO23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO23_Msk instead */ +#define MCAN_TXBTO_TO24_Pos 24 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Position */ +#define MCAN_TXBTO_TO24_Msk (_U_(0x1) << MCAN_TXBTO_TO24_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Mask */ +#define MCAN_TXBTO_TO24 MCAN_TXBTO_TO24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO24_Msk instead */ +#define MCAN_TXBTO_TO25_Pos 25 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Position */ +#define MCAN_TXBTO_TO25_Msk (_U_(0x1) << MCAN_TXBTO_TO25_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Mask */ +#define MCAN_TXBTO_TO25 MCAN_TXBTO_TO25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO25_Msk instead */ +#define MCAN_TXBTO_TO26_Pos 26 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Position */ +#define MCAN_TXBTO_TO26_Msk (_U_(0x1) << MCAN_TXBTO_TO26_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Mask */ +#define MCAN_TXBTO_TO26 MCAN_TXBTO_TO26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO26_Msk instead */ +#define MCAN_TXBTO_TO27_Pos 27 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Position */ +#define MCAN_TXBTO_TO27_Msk (_U_(0x1) << MCAN_TXBTO_TO27_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Mask */ +#define MCAN_TXBTO_TO27 MCAN_TXBTO_TO27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO27_Msk instead */ +#define MCAN_TXBTO_TO28_Pos 28 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Position */ +#define MCAN_TXBTO_TO28_Msk (_U_(0x1) << MCAN_TXBTO_TO28_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Mask */ +#define MCAN_TXBTO_TO28 MCAN_TXBTO_TO28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO28_Msk instead */ +#define MCAN_TXBTO_TO29_Pos 29 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Position */ +#define MCAN_TXBTO_TO29_Msk (_U_(0x1) << MCAN_TXBTO_TO29_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Mask */ +#define MCAN_TXBTO_TO29 MCAN_TXBTO_TO29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO29_Msk instead */ +#define MCAN_TXBTO_TO30_Pos 30 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Position */ +#define MCAN_TXBTO_TO30_Msk (_U_(0x1) << MCAN_TXBTO_TO30_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Mask */ +#define MCAN_TXBTO_TO30 MCAN_TXBTO_TO30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO30_Msk instead */ +#define MCAN_TXBTO_TO31_Pos 31 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Position */ +#define MCAN_TXBTO_TO31_Msk (_U_(0x1) << MCAN_TXBTO_TO31_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Mask */ +#define MCAN_TXBTO_TO31 MCAN_TXBTO_TO31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO31_Msk instead */ +#define MCAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBTO) Register MASK (Use MCAN_TXBTO_Msk instead) */ +#define MCAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTO) Register Mask */ + +#define MCAN_TXBTO_TO_Pos 0 /**< (MCAN_TXBTO Position) Transmission Occurred for Buffer 3x */ +#define MCAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTO_TO_Pos) /**< (MCAN_TXBTO Mask) TO */ +#define MCAN_TXBTO_TO(value) (MCAN_TXBTO_TO_Msk & ((value) << MCAN_TXBTO_TO_Pos)) + +/* -------- MCAN_TXBCF : (MCAN Offset: 0xdc) (R/ 32) Transmit Buffer Cancellation Finished Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CF0:1; /**< bit: 0 Cancellation Finished for Transmit Buffer 0 */ + uint32_t CF1:1; /**< bit: 1 Cancellation Finished for Transmit Buffer 1 */ + uint32_t CF2:1; /**< bit: 2 Cancellation Finished for Transmit Buffer 2 */ + uint32_t CF3:1; /**< bit: 3 Cancellation Finished for Transmit Buffer 3 */ + uint32_t CF4:1; /**< bit: 4 Cancellation Finished for Transmit Buffer 4 */ + uint32_t CF5:1; /**< bit: 5 Cancellation Finished for Transmit Buffer 5 */ + uint32_t CF6:1; /**< bit: 6 Cancellation Finished for Transmit Buffer 6 */ + uint32_t CF7:1; /**< bit: 7 Cancellation Finished for Transmit Buffer 7 */ + uint32_t CF8:1; /**< bit: 8 Cancellation Finished for Transmit Buffer 8 */ + uint32_t CF9:1; /**< bit: 9 Cancellation Finished for Transmit Buffer 9 */ + uint32_t CF10:1; /**< bit: 10 Cancellation Finished for Transmit Buffer 10 */ + uint32_t CF11:1; /**< bit: 11 Cancellation Finished for Transmit Buffer 11 */ + uint32_t CF12:1; /**< bit: 12 Cancellation Finished for Transmit Buffer 12 */ + uint32_t CF13:1; /**< bit: 13 Cancellation Finished for Transmit Buffer 13 */ + uint32_t CF14:1; /**< bit: 14 Cancellation Finished for Transmit Buffer 14 */ + uint32_t CF15:1; /**< bit: 15 Cancellation Finished for Transmit Buffer 15 */ + uint32_t CF16:1; /**< bit: 16 Cancellation Finished for Transmit Buffer 16 */ + uint32_t CF17:1; /**< bit: 17 Cancellation Finished for Transmit Buffer 17 */ + uint32_t CF18:1; /**< bit: 18 Cancellation Finished for Transmit Buffer 18 */ + uint32_t CF19:1; /**< bit: 19 Cancellation Finished for Transmit Buffer 19 */ + uint32_t CF20:1; /**< bit: 20 Cancellation Finished for Transmit Buffer 20 */ + uint32_t CF21:1; /**< bit: 21 Cancellation Finished for Transmit Buffer 21 */ + uint32_t CF22:1; /**< bit: 22 Cancellation Finished for Transmit Buffer 22 */ + uint32_t CF23:1; /**< bit: 23 Cancellation Finished for Transmit Buffer 23 */ + uint32_t CF24:1; /**< bit: 24 Cancellation Finished for Transmit Buffer 24 */ + uint32_t CF25:1; /**< bit: 25 Cancellation Finished for Transmit Buffer 25 */ + uint32_t CF26:1; /**< bit: 26 Cancellation Finished for Transmit Buffer 26 */ + uint32_t CF27:1; /**< bit: 27 Cancellation Finished for Transmit Buffer 27 */ + uint32_t CF28:1; /**< bit: 28 Cancellation Finished for Transmit Buffer 28 */ + uint32_t CF29:1; /**< bit: 29 Cancellation Finished for Transmit Buffer 29 */ + uint32_t CF30:1; /**< bit: 30 Cancellation Finished for Transmit Buffer 30 */ + uint32_t CF31:1; /**< bit: 31 Cancellation Finished for Transmit Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CF:32; /**< bit: 0..31 Cancellation Finished for Transmit Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBCF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBCF_OFFSET (0xDC) /**< (MCAN_TXBCF) Transmit Buffer Cancellation Finished Register Offset */ + +#define MCAN_TXBCF_CF0_Pos 0 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Position */ +#define MCAN_TXBCF_CF0_Msk (_U_(0x1) << MCAN_TXBCF_CF0_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Mask */ +#define MCAN_TXBCF_CF0 MCAN_TXBCF_CF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF0_Msk instead */ +#define MCAN_TXBCF_CF1_Pos 1 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Position */ +#define MCAN_TXBCF_CF1_Msk (_U_(0x1) << MCAN_TXBCF_CF1_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Mask */ +#define MCAN_TXBCF_CF1 MCAN_TXBCF_CF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF1_Msk instead */ +#define MCAN_TXBCF_CF2_Pos 2 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Position */ +#define MCAN_TXBCF_CF2_Msk (_U_(0x1) << MCAN_TXBCF_CF2_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Mask */ +#define MCAN_TXBCF_CF2 MCAN_TXBCF_CF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF2_Msk instead */ +#define MCAN_TXBCF_CF3_Pos 3 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Position */ +#define MCAN_TXBCF_CF3_Msk (_U_(0x1) << MCAN_TXBCF_CF3_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Mask */ +#define MCAN_TXBCF_CF3 MCAN_TXBCF_CF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF3_Msk instead */ +#define MCAN_TXBCF_CF4_Pos 4 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Position */ +#define MCAN_TXBCF_CF4_Msk (_U_(0x1) << MCAN_TXBCF_CF4_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Mask */ +#define MCAN_TXBCF_CF4 MCAN_TXBCF_CF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF4_Msk instead */ +#define MCAN_TXBCF_CF5_Pos 5 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Position */ +#define MCAN_TXBCF_CF5_Msk (_U_(0x1) << MCAN_TXBCF_CF5_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Mask */ +#define MCAN_TXBCF_CF5 MCAN_TXBCF_CF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF5_Msk instead */ +#define MCAN_TXBCF_CF6_Pos 6 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Position */ +#define MCAN_TXBCF_CF6_Msk (_U_(0x1) << MCAN_TXBCF_CF6_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Mask */ +#define MCAN_TXBCF_CF6 MCAN_TXBCF_CF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF6_Msk instead */ +#define MCAN_TXBCF_CF7_Pos 7 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Position */ +#define MCAN_TXBCF_CF7_Msk (_U_(0x1) << MCAN_TXBCF_CF7_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Mask */ +#define MCAN_TXBCF_CF7 MCAN_TXBCF_CF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF7_Msk instead */ +#define MCAN_TXBCF_CF8_Pos 8 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Position */ +#define MCAN_TXBCF_CF8_Msk (_U_(0x1) << MCAN_TXBCF_CF8_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Mask */ +#define MCAN_TXBCF_CF8 MCAN_TXBCF_CF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF8_Msk instead */ +#define MCAN_TXBCF_CF9_Pos 9 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Position */ +#define MCAN_TXBCF_CF9_Msk (_U_(0x1) << MCAN_TXBCF_CF9_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Mask */ +#define MCAN_TXBCF_CF9 MCAN_TXBCF_CF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF9_Msk instead */ +#define MCAN_TXBCF_CF10_Pos 10 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Position */ +#define MCAN_TXBCF_CF10_Msk (_U_(0x1) << MCAN_TXBCF_CF10_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Mask */ +#define MCAN_TXBCF_CF10 MCAN_TXBCF_CF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF10_Msk instead */ +#define MCAN_TXBCF_CF11_Pos 11 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Position */ +#define MCAN_TXBCF_CF11_Msk (_U_(0x1) << MCAN_TXBCF_CF11_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Mask */ +#define MCAN_TXBCF_CF11 MCAN_TXBCF_CF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF11_Msk instead */ +#define MCAN_TXBCF_CF12_Pos 12 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Position */ +#define MCAN_TXBCF_CF12_Msk (_U_(0x1) << MCAN_TXBCF_CF12_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Mask */ +#define MCAN_TXBCF_CF12 MCAN_TXBCF_CF12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF12_Msk instead */ +#define MCAN_TXBCF_CF13_Pos 13 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Position */ +#define MCAN_TXBCF_CF13_Msk (_U_(0x1) << MCAN_TXBCF_CF13_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Mask */ +#define MCAN_TXBCF_CF13 MCAN_TXBCF_CF13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF13_Msk instead */ +#define MCAN_TXBCF_CF14_Pos 14 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Position */ +#define MCAN_TXBCF_CF14_Msk (_U_(0x1) << MCAN_TXBCF_CF14_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Mask */ +#define MCAN_TXBCF_CF14 MCAN_TXBCF_CF14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF14_Msk instead */ +#define MCAN_TXBCF_CF15_Pos 15 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Position */ +#define MCAN_TXBCF_CF15_Msk (_U_(0x1) << MCAN_TXBCF_CF15_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Mask */ +#define MCAN_TXBCF_CF15 MCAN_TXBCF_CF15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF15_Msk instead */ +#define MCAN_TXBCF_CF16_Pos 16 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Position */ +#define MCAN_TXBCF_CF16_Msk (_U_(0x1) << MCAN_TXBCF_CF16_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Mask */ +#define MCAN_TXBCF_CF16 MCAN_TXBCF_CF16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF16_Msk instead */ +#define MCAN_TXBCF_CF17_Pos 17 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Position */ +#define MCAN_TXBCF_CF17_Msk (_U_(0x1) << MCAN_TXBCF_CF17_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Mask */ +#define MCAN_TXBCF_CF17 MCAN_TXBCF_CF17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF17_Msk instead */ +#define MCAN_TXBCF_CF18_Pos 18 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Position */ +#define MCAN_TXBCF_CF18_Msk (_U_(0x1) << MCAN_TXBCF_CF18_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Mask */ +#define MCAN_TXBCF_CF18 MCAN_TXBCF_CF18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF18_Msk instead */ +#define MCAN_TXBCF_CF19_Pos 19 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Position */ +#define MCAN_TXBCF_CF19_Msk (_U_(0x1) << MCAN_TXBCF_CF19_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Mask */ +#define MCAN_TXBCF_CF19 MCAN_TXBCF_CF19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF19_Msk instead */ +#define MCAN_TXBCF_CF20_Pos 20 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Position */ +#define MCAN_TXBCF_CF20_Msk (_U_(0x1) << MCAN_TXBCF_CF20_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Mask */ +#define MCAN_TXBCF_CF20 MCAN_TXBCF_CF20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF20_Msk instead */ +#define MCAN_TXBCF_CF21_Pos 21 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Position */ +#define MCAN_TXBCF_CF21_Msk (_U_(0x1) << MCAN_TXBCF_CF21_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Mask */ +#define MCAN_TXBCF_CF21 MCAN_TXBCF_CF21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF21_Msk instead */ +#define MCAN_TXBCF_CF22_Pos 22 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Position */ +#define MCAN_TXBCF_CF22_Msk (_U_(0x1) << MCAN_TXBCF_CF22_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Mask */ +#define MCAN_TXBCF_CF22 MCAN_TXBCF_CF22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF22_Msk instead */ +#define MCAN_TXBCF_CF23_Pos 23 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Position */ +#define MCAN_TXBCF_CF23_Msk (_U_(0x1) << MCAN_TXBCF_CF23_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Mask */ +#define MCAN_TXBCF_CF23 MCAN_TXBCF_CF23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF23_Msk instead */ +#define MCAN_TXBCF_CF24_Pos 24 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Position */ +#define MCAN_TXBCF_CF24_Msk (_U_(0x1) << MCAN_TXBCF_CF24_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Mask */ +#define MCAN_TXBCF_CF24 MCAN_TXBCF_CF24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF24_Msk instead */ +#define MCAN_TXBCF_CF25_Pos 25 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Position */ +#define MCAN_TXBCF_CF25_Msk (_U_(0x1) << MCAN_TXBCF_CF25_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Mask */ +#define MCAN_TXBCF_CF25 MCAN_TXBCF_CF25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF25_Msk instead */ +#define MCAN_TXBCF_CF26_Pos 26 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Position */ +#define MCAN_TXBCF_CF26_Msk (_U_(0x1) << MCAN_TXBCF_CF26_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Mask */ +#define MCAN_TXBCF_CF26 MCAN_TXBCF_CF26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF26_Msk instead */ +#define MCAN_TXBCF_CF27_Pos 27 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Position */ +#define MCAN_TXBCF_CF27_Msk (_U_(0x1) << MCAN_TXBCF_CF27_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Mask */ +#define MCAN_TXBCF_CF27 MCAN_TXBCF_CF27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF27_Msk instead */ +#define MCAN_TXBCF_CF28_Pos 28 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Position */ +#define MCAN_TXBCF_CF28_Msk (_U_(0x1) << MCAN_TXBCF_CF28_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Mask */ +#define MCAN_TXBCF_CF28 MCAN_TXBCF_CF28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF28_Msk instead */ +#define MCAN_TXBCF_CF29_Pos 29 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Position */ +#define MCAN_TXBCF_CF29_Msk (_U_(0x1) << MCAN_TXBCF_CF29_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Mask */ +#define MCAN_TXBCF_CF29 MCAN_TXBCF_CF29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF29_Msk instead */ +#define MCAN_TXBCF_CF30_Pos 30 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Position */ +#define MCAN_TXBCF_CF30_Msk (_U_(0x1) << MCAN_TXBCF_CF30_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Mask */ +#define MCAN_TXBCF_CF30 MCAN_TXBCF_CF30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF30_Msk instead */ +#define MCAN_TXBCF_CF31_Pos 31 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Position */ +#define MCAN_TXBCF_CF31_Msk (_U_(0x1) << MCAN_TXBCF_CF31_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Mask */ +#define MCAN_TXBCF_CF31 MCAN_TXBCF_CF31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF31_Msk instead */ +#define MCAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCF) Register MASK (Use MCAN_TXBCF_Msk instead) */ +#define MCAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCF) Register Mask */ + +#define MCAN_TXBCF_CF_Pos 0 /**< (MCAN_TXBCF Position) Cancellation Finished for Transmit Buffer 3x */ +#define MCAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCF_CF_Pos) /**< (MCAN_TXBCF Mask) CF */ +#define MCAN_TXBCF_CF(value) (MCAN_TXBCF_CF_Msk & ((value) << MCAN_TXBCF_CF_Pos)) + +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xe0) (R/W 32) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TIE0:1; /**< bit: 0 Transmission Interrupt Enable for Buffer 0 */ + uint32_t TIE1:1; /**< bit: 1 Transmission Interrupt Enable for Buffer 1 */ + uint32_t TIE2:1; /**< bit: 2 Transmission Interrupt Enable for Buffer 2 */ + uint32_t TIE3:1; /**< bit: 3 Transmission Interrupt Enable for Buffer 3 */ + uint32_t TIE4:1; /**< bit: 4 Transmission Interrupt Enable for Buffer 4 */ + uint32_t TIE5:1; /**< bit: 5 Transmission Interrupt Enable for Buffer 5 */ + uint32_t TIE6:1; /**< bit: 6 Transmission Interrupt Enable for Buffer 6 */ + uint32_t TIE7:1; /**< bit: 7 Transmission Interrupt Enable for Buffer 7 */ + uint32_t TIE8:1; /**< bit: 8 Transmission Interrupt Enable for Buffer 8 */ + uint32_t TIE9:1; /**< bit: 9 Transmission Interrupt Enable for Buffer 9 */ + uint32_t TIE10:1; /**< bit: 10 Transmission Interrupt Enable for Buffer 10 */ + uint32_t TIE11:1; /**< bit: 11 Transmission Interrupt Enable for Buffer 11 */ + uint32_t TIE12:1; /**< bit: 12 Transmission Interrupt Enable for Buffer 12 */ + uint32_t TIE13:1; /**< bit: 13 Transmission Interrupt Enable for Buffer 13 */ + uint32_t TIE14:1; /**< bit: 14 Transmission Interrupt Enable for Buffer 14 */ + uint32_t TIE15:1; /**< bit: 15 Transmission Interrupt Enable for Buffer 15 */ + uint32_t TIE16:1; /**< bit: 16 Transmission Interrupt Enable for Buffer 16 */ + uint32_t TIE17:1; /**< bit: 17 Transmission Interrupt Enable for Buffer 17 */ + uint32_t TIE18:1; /**< bit: 18 Transmission Interrupt Enable for Buffer 18 */ + uint32_t TIE19:1; /**< bit: 19 Transmission Interrupt Enable for Buffer 19 */ + uint32_t TIE20:1; /**< bit: 20 Transmission Interrupt Enable for Buffer 20 */ + uint32_t TIE21:1; /**< bit: 21 Transmission Interrupt Enable for Buffer 21 */ + uint32_t TIE22:1; /**< bit: 22 Transmission Interrupt Enable for Buffer 22 */ + uint32_t TIE23:1; /**< bit: 23 Transmission Interrupt Enable for Buffer 23 */ + uint32_t TIE24:1; /**< bit: 24 Transmission Interrupt Enable for Buffer 24 */ + uint32_t TIE25:1; /**< bit: 25 Transmission Interrupt Enable for Buffer 25 */ + uint32_t TIE26:1; /**< bit: 26 Transmission Interrupt Enable for Buffer 26 */ + uint32_t TIE27:1; /**< bit: 27 Transmission Interrupt Enable for Buffer 27 */ + uint32_t TIE28:1; /**< bit: 28 Transmission Interrupt Enable for Buffer 28 */ + uint32_t TIE29:1; /**< bit: 29 Transmission Interrupt Enable for Buffer 29 */ + uint32_t TIE30:1; /**< bit: 30 Transmission Interrupt Enable for Buffer 30 */ + uint32_t TIE31:1; /**< bit: 31 Transmission Interrupt Enable for Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t TIE:32; /**< bit: 0..31 Transmission Interrupt Enable for Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBTIE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBTIE_OFFSET (0xE0) /**< (MCAN_TXBTIE) Transmit Buffer Transmission Interrupt Enable Register Offset */ + +#define MCAN_TXBTIE_TIE0_Pos 0 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Position */ +#define MCAN_TXBTIE_TIE0_Msk (_U_(0x1) << MCAN_TXBTIE_TIE0_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Mask */ +#define MCAN_TXBTIE_TIE0 MCAN_TXBTIE_TIE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE0_Msk instead */ +#define MCAN_TXBTIE_TIE1_Pos 1 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Position */ +#define MCAN_TXBTIE_TIE1_Msk (_U_(0x1) << MCAN_TXBTIE_TIE1_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Mask */ +#define MCAN_TXBTIE_TIE1 MCAN_TXBTIE_TIE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE1_Msk instead */ +#define MCAN_TXBTIE_TIE2_Pos 2 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Position */ +#define MCAN_TXBTIE_TIE2_Msk (_U_(0x1) << MCAN_TXBTIE_TIE2_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Mask */ +#define MCAN_TXBTIE_TIE2 MCAN_TXBTIE_TIE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE2_Msk instead */ +#define MCAN_TXBTIE_TIE3_Pos 3 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Position */ +#define MCAN_TXBTIE_TIE3_Msk (_U_(0x1) << MCAN_TXBTIE_TIE3_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Mask */ +#define MCAN_TXBTIE_TIE3 MCAN_TXBTIE_TIE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE3_Msk instead */ +#define MCAN_TXBTIE_TIE4_Pos 4 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Position */ +#define MCAN_TXBTIE_TIE4_Msk (_U_(0x1) << MCAN_TXBTIE_TIE4_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Mask */ +#define MCAN_TXBTIE_TIE4 MCAN_TXBTIE_TIE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE4_Msk instead */ +#define MCAN_TXBTIE_TIE5_Pos 5 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Position */ +#define MCAN_TXBTIE_TIE5_Msk (_U_(0x1) << MCAN_TXBTIE_TIE5_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Mask */ +#define MCAN_TXBTIE_TIE5 MCAN_TXBTIE_TIE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE5_Msk instead */ +#define MCAN_TXBTIE_TIE6_Pos 6 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Position */ +#define MCAN_TXBTIE_TIE6_Msk (_U_(0x1) << MCAN_TXBTIE_TIE6_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Mask */ +#define MCAN_TXBTIE_TIE6 MCAN_TXBTIE_TIE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE6_Msk instead */ +#define MCAN_TXBTIE_TIE7_Pos 7 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Position */ +#define MCAN_TXBTIE_TIE7_Msk (_U_(0x1) << MCAN_TXBTIE_TIE7_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Mask */ +#define MCAN_TXBTIE_TIE7 MCAN_TXBTIE_TIE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE7_Msk instead */ +#define MCAN_TXBTIE_TIE8_Pos 8 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Position */ +#define MCAN_TXBTIE_TIE8_Msk (_U_(0x1) << MCAN_TXBTIE_TIE8_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Mask */ +#define MCAN_TXBTIE_TIE8 MCAN_TXBTIE_TIE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE8_Msk instead */ +#define MCAN_TXBTIE_TIE9_Pos 9 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Position */ +#define MCAN_TXBTIE_TIE9_Msk (_U_(0x1) << MCAN_TXBTIE_TIE9_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Mask */ +#define MCAN_TXBTIE_TIE9 MCAN_TXBTIE_TIE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE9_Msk instead */ +#define MCAN_TXBTIE_TIE10_Pos 10 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Position */ +#define MCAN_TXBTIE_TIE10_Msk (_U_(0x1) << MCAN_TXBTIE_TIE10_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Mask */ +#define MCAN_TXBTIE_TIE10 MCAN_TXBTIE_TIE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE10_Msk instead */ +#define MCAN_TXBTIE_TIE11_Pos 11 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Position */ +#define MCAN_TXBTIE_TIE11_Msk (_U_(0x1) << MCAN_TXBTIE_TIE11_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Mask */ +#define MCAN_TXBTIE_TIE11 MCAN_TXBTIE_TIE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE11_Msk instead */ +#define MCAN_TXBTIE_TIE12_Pos 12 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Position */ +#define MCAN_TXBTIE_TIE12_Msk (_U_(0x1) << MCAN_TXBTIE_TIE12_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Mask */ +#define MCAN_TXBTIE_TIE12 MCAN_TXBTIE_TIE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE12_Msk instead */ +#define MCAN_TXBTIE_TIE13_Pos 13 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Position */ +#define MCAN_TXBTIE_TIE13_Msk (_U_(0x1) << MCAN_TXBTIE_TIE13_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Mask */ +#define MCAN_TXBTIE_TIE13 MCAN_TXBTIE_TIE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE13_Msk instead */ +#define MCAN_TXBTIE_TIE14_Pos 14 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Position */ +#define MCAN_TXBTIE_TIE14_Msk (_U_(0x1) << MCAN_TXBTIE_TIE14_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Mask */ +#define MCAN_TXBTIE_TIE14 MCAN_TXBTIE_TIE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE14_Msk instead */ +#define MCAN_TXBTIE_TIE15_Pos 15 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Position */ +#define MCAN_TXBTIE_TIE15_Msk (_U_(0x1) << MCAN_TXBTIE_TIE15_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Mask */ +#define MCAN_TXBTIE_TIE15 MCAN_TXBTIE_TIE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE15_Msk instead */ +#define MCAN_TXBTIE_TIE16_Pos 16 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Position */ +#define MCAN_TXBTIE_TIE16_Msk (_U_(0x1) << MCAN_TXBTIE_TIE16_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Mask */ +#define MCAN_TXBTIE_TIE16 MCAN_TXBTIE_TIE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE16_Msk instead */ +#define MCAN_TXBTIE_TIE17_Pos 17 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Position */ +#define MCAN_TXBTIE_TIE17_Msk (_U_(0x1) << MCAN_TXBTIE_TIE17_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Mask */ +#define MCAN_TXBTIE_TIE17 MCAN_TXBTIE_TIE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE17_Msk instead */ +#define MCAN_TXBTIE_TIE18_Pos 18 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Position */ +#define MCAN_TXBTIE_TIE18_Msk (_U_(0x1) << MCAN_TXBTIE_TIE18_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Mask */ +#define MCAN_TXBTIE_TIE18 MCAN_TXBTIE_TIE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE18_Msk instead */ +#define MCAN_TXBTIE_TIE19_Pos 19 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Position */ +#define MCAN_TXBTIE_TIE19_Msk (_U_(0x1) << MCAN_TXBTIE_TIE19_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Mask */ +#define MCAN_TXBTIE_TIE19 MCAN_TXBTIE_TIE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE19_Msk instead */ +#define MCAN_TXBTIE_TIE20_Pos 20 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Position */ +#define MCAN_TXBTIE_TIE20_Msk (_U_(0x1) << MCAN_TXBTIE_TIE20_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Mask */ +#define MCAN_TXBTIE_TIE20 MCAN_TXBTIE_TIE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE20_Msk instead */ +#define MCAN_TXBTIE_TIE21_Pos 21 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Position */ +#define MCAN_TXBTIE_TIE21_Msk (_U_(0x1) << MCAN_TXBTIE_TIE21_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Mask */ +#define MCAN_TXBTIE_TIE21 MCAN_TXBTIE_TIE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE21_Msk instead */ +#define MCAN_TXBTIE_TIE22_Pos 22 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Position */ +#define MCAN_TXBTIE_TIE22_Msk (_U_(0x1) << MCAN_TXBTIE_TIE22_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Mask */ +#define MCAN_TXBTIE_TIE22 MCAN_TXBTIE_TIE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE22_Msk instead */ +#define MCAN_TXBTIE_TIE23_Pos 23 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Position */ +#define MCAN_TXBTIE_TIE23_Msk (_U_(0x1) << MCAN_TXBTIE_TIE23_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Mask */ +#define MCAN_TXBTIE_TIE23 MCAN_TXBTIE_TIE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE23_Msk instead */ +#define MCAN_TXBTIE_TIE24_Pos 24 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Position */ +#define MCAN_TXBTIE_TIE24_Msk (_U_(0x1) << MCAN_TXBTIE_TIE24_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Mask */ +#define MCAN_TXBTIE_TIE24 MCAN_TXBTIE_TIE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE24_Msk instead */ +#define MCAN_TXBTIE_TIE25_Pos 25 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Position */ +#define MCAN_TXBTIE_TIE25_Msk (_U_(0x1) << MCAN_TXBTIE_TIE25_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Mask */ +#define MCAN_TXBTIE_TIE25 MCAN_TXBTIE_TIE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE25_Msk instead */ +#define MCAN_TXBTIE_TIE26_Pos 26 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Position */ +#define MCAN_TXBTIE_TIE26_Msk (_U_(0x1) << MCAN_TXBTIE_TIE26_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Mask */ +#define MCAN_TXBTIE_TIE26 MCAN_TXBTIE_TIE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE26_Msk instead */ +#define MCAN_TXBTIE_TIE27_Pos 27 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Position */ +#define MCAN_TXBTIE_TIE27_Msk (_U_(0x1) << MCAN_TXBTIE_TIE27_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Mask */ +#define MCAN_TXBTIE_TIE27 MCAN_TXBTIE_TIE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE27_Msk instead */ +#define MCAN_TXBTIE_TIE28_Pos 28 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Position */ +#define MCAN_TXBTIE_TIE28_Msk (_U_(0x1) << MCAN_TXBTIE_TIE28_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Mask */ +#define MCAN_TXBTIE_TIE28 MCAN_TXBTIE_TIE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE28_Msk instead */ +#define MCAN_TXBTIE_TIE29_Pos 29 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Position */ +#define MCAN_TXBTIE_TIE29_Msk (_U_(0x1) << MCAN_TXBTIE_TIE29_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Mask */ +#define MCAN_TXBTIE_TIE29 MCAN_TXBTIE_TIE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE29_Msk instead */ +#define MCAN_TXBTIE_TIE30_Pos 30 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Position */ +#define MCAN_TXBTIE_TIE30_Msk (_U_(0x1) << MCAN_TXBTIE_TIE30_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Mask */ +#define MCAN_TXBTIE_TIE30 MCAN_TXBTIE_TIE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE30_Msk instead */ +#define MCAN_TXBTIE_TIE31_Pos 31 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Position */ +#define MCAN_TXBTIE_TIE31_Msk (_U_(0x1) << MCAN_TXBTIE_TIE31_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Mask */ +#define MCAN_TXBTIE_TIE31 MCAN_TXBTIE_TIE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE31_Msk instead */ +#define MCAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBTIE) Register MASK (Use MCAN_TXBTIE_Msk instead) */ +#define MCAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTIE) Register Mask */ + +#define MCAN_TXBTIE_TIE_Pos 0 /**< (MCAN_TXBTIE Position) Transmission Interrupt Enable for Buffer 3x */ +#define MCAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTIE_TIE_Pos) /**< (MCAN_TXBTIE Mask) TIE */ +#define MCAN_TXBTIE_TIE(value) (MCAN_TXBTIE_TIE_Msk & ((value) << MCAN_TXBTIE_TIE_Pos)) + +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xe4) (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CFIE0:1; /**< bit: 0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ + uint32_t CFIE1:1; /**< bit: 1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ + uint32_t CFIE2:1; /**< bit: 2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ + uint32_t CFIE3:1; /**< bit: 3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ + uint32_t CFIE4:1; /**< bit: 4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ + uint32_t CFIE5:1; /**< bit: 5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ + uint32_t CFIE6:1; /**< bit: 6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ + uint32_t CFIE7:1; /**< bit: 7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ + uint32_t CFIE8:1; /**< bit: 8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ + uint32_t CFIE9:1; /**< bit: 9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ + uint32_t CFIE10:1; /**< bit: 10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ + uint32_t CFIE11:1; /**< bit: 11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ + uint32_t CFIE12:1; /**< bit: 12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ + uint32_t CFIE13:1; /**< bit: 13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ + uint32_t CFIE14:1; /**< bit: 14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ + uint32_t CFIE15:1; /**< bit: 15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ + uint32_t CFIE16:1; /**< bit: 16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ + uint32_t CFIE17:1; /**< bit: 17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ + uint32_t CFIE18:1; /**< bit: 18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ + uint32_t CFIE19:1; /**< bit: 19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ + uint32_t CFIE20:1; /**< bit: 20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ + uint32_t CFIE21:1; /**< bit: 21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ + uint32_t CFIE22:1; /**< bit: 22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ + uint32_t CFIE23:1; /**< bit: 23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ + uint32_t CFIE24:1; /**< bit: 24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ + uint32_t CFIE25:1; /**< bit: 25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ + uint32_t CFIE26:1; /**< bit: 26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ + uint32_t CFIE27:1; /**< bit: 27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ + uint32_t CFIE28:1; /**< bit: 28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ + uint32_t CFIE29:1; /**< bit: 29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ + uint32_t CFIE30:1; /**< bit: 30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ + uint32_t CFIE31:1; /**< bit: 31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CFIE:32; /**< bit: 0..31 Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXBCIE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXBCIE_OFFSET (0xE4) /**< (MCAN_TXBCIE) Transmit Buffer Cancellation Finished Interrupt Enable Register Offset */ + +#define MCAN_TXBCIE_CFIE0_Pos 0 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Position */ +#define MCAN_TXBCIE_CFIE0_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE0_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Mask */ +#define MCAN_TXBCIE_CFIE0 MCAN_TXBCIE_CFIE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE0_Msk instead */ +#define MCAN_TXBCIE_CFIE1_Pos 1 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Position */ +#define MCAN_TXBCIE_CFIE1_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE1_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Mask */ +#define MCAN_TXBCIE_CFIE1 MCAN_TXBCIE_CFIE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE1_Msk instead */ +#define MCAN_TXBCIE_CFIE2_Pos 2 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Position */ +#define MCAN_TXBCIE_CFIE2_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE2_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Mask */ +#define MCAN_TXBCIE_CFIE2 MCAN_TXBCIE_CFIE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE2_Msk instead */ +#define MCAN_TXBCIE_CFIE3_Pos 3 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Position */ +#define MCAN_TXBCIE_CFIE3_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE3_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Mask */ +#define MCAN_TXBCIE_CFIE3 MCAN_TXBCIE_CFIE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE3_Msk instead */ +#define MCAN_TXBCIE_CFIE4_Pos 4 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Position */ +#define MCAN_TXBCIE_CFIE4_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE4_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Mask */ +#define MCAN_TXBCIE_CFIE4 MCAN_TXBCIE_CFIE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE4_Msk instead */ +#define MCAN_TXBCIE_CFIE5_Pos 5 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Position */ +#define MCAN_TXBCIE_CFIE5_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE5_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Mask */ +#define MCAN_TXBCIE_CFIE5 MCAN_TXBCIE_CFIE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE5_Msk instead */ +#define MCAN_TXBCIE_CFIE6_Pos 6 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Position */ +#define MCAN_TXBCIE_CFIE6_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE6_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Mask */ +#define MCAN_TXBCIE_CFIE6 MCAN_TXBCIE_CFIE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE6_Msk instead */ +#define MCAN_TXBCIE_CFIE7_Pos 7 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Position */ +#define MCAN_TXBCIE_CFIE7_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE7_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Mask */ +#define MCAN_TXBCIE_CFIE7 MCAN_TXBCIE_CFIE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE7_Msk instead */ +#define MCAN_TXBCIE_CFIE8_Pos 8 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Position */ +#define MCAN_TXBCIE_CFIE8_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE8_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Mask */ +#define MCAN_TXBCIE_CFIE8 MCAN_TXBCIE_CFIE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE8_Msk instead */ +#define MCAN_TXBCIE_CFIE9_Pos 9 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Position */ +#define MCAN_TXBCIE_CFIE9_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE9_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Mask */ +#define MCAN_TXBCIE_CFIE9 MCAN_TXBCIE_CFIE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE9_Msk instead */ +#define MCAN_TXBCIE_CFIE10_Pos 10 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Position */ +#define MCAN_TXBCIE_CFIE10_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE10_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Mask */ +#define MCAN_TXBCIE_CFIE10 MCAN_TXBCIE_CFIE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE10_Msk instead */ +#define MCAN_TXBCIE_CFIE11_Pos 11 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Position */ +#define MCAN_TXBCIE_CFIE11_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE11_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Mask */ +#define MCAN_TXBCIE_CFIE11 MCAN_TXBCIE_CFIE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE11_Msk instead */ +#define MCAN_TXBCIE_CFIE12_Pos 12 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Position */ +#define MCAN_TXBCIE_CFIE12_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE12_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Mask */ +#define MCAN_TXBCIE_CFIE12 MCAN_TXBCIE_CFIE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE12_Msk instead */ +#define MCAN_TXBCIE_CFIE13_Pos 13 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Position */ +#define MCAN_TXBCIE_CFIE13_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE13_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Mask */ +#define MCAN_TXBCIE_CFIE13 MCAN_TXBCIE_CFIE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE13_Msk instead */ +#define MCAN_TXBCIE_CFIE14_Pos 14 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Position */ +#define MCAN_TXBCIE_CFIE14_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE14_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Mask */ +#define MCAN_TXBCIE_CFIE14 MCAN_TXBCIE_CFIE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE14_Msk instead */ +#define MCAN_TXBCIE_CFIE15_Pos 15 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Position */ +#define MCAN_TXBCIE_CFIE15_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE15_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Mask */ +#define MCAN_TXBCIE_CFIE15 MCAN_TXBCIE_CFIE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE15_Msk instead */ +#define MCAN_TXBCIE_CFIE16_Pos 16 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Position */ +#define MCAN_TXBCIE_CFIE16_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE16_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Mask */ +#define MCAN_TXBCIE_CFIE16 MCAN_TXBCIE_CFIE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE16_Msk instead */ +#define MCAN_TXBCIE_CFIE17_Pos 17 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Position */ +#define MCAN_TXBCIE_CFIE17_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE17_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Mask */ +#define MCAN_TXBCIE_CFIE17 MCAN_TXBCIE_CFIE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE17_Msk instead */ +#define MCAN_TXBCIE_CFIE18_Pos 18 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Position */ +#define MCAN_TXBCIE_CFIE18_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE18_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Mask */ +#define MCAN_TXBCIE_CFIE18 MCAN_TXBCIE_CFIE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE18_Msk instead */ +#define MCAN_TXBCIE_CFIE19_Pos 19 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Position */ +#define MCAN_TXBCIE_CFIE19_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE19_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Mask */ +#define MCAN_TXBCIE_CFIE19 MCAN_TXBCIE_CFIE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE19_Msk instead */ +#define MCAN_TXBCIE_CFIE20_Pos 20 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Position */ +#define MCAN_TXBCIE_CFIE20_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE20_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Mask */ +#define MCAN_TXBCIE_CFIE20 MCAN_TXBCIE_CFIE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE20_Msk instead */ +#define MCAN_TXBCIE_CFIE21_Pos 21 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Position */ +#define MCAN_TXBCIE_CFIE21_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE21_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Mask */ +#define MCAN_TXBCIE_CFIE21 MCAN_TXBCIE_CFIE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE21_Msk instead */ +#define MCAN_TXBCIE_CFIE22_Pos 22 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Position */ +#define MCAN_TXBCIE_CFIE22_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE22_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Mask */ +#define MCAN_TXBCIE_CFIE22 MCAN_TXBCIE_CFIE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE22_Msk instead */ +#define MCAN_TXBCIE_CFIE23_Pos 23 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Position */ +#define MCAN_TXBCIE_CFIE23_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE23_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Mask */ +#define MCAN_TXBCIE_CFIE23 MCAN_TXBCIE_CFIE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE23_Msk instead */ +#define MCAN_TXBCIE_CFIE24_Pos 24 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Position */ +#define MCAN_TXBCIE_CFIE24_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE24_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Mask */ +#define MCAN_TXBCIE_CFIE24 MCAN_TXBCIE_CFIE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE24_Msk instead */ +#define MCAN_TXBCIE_CFIE25_Pos 25 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Position */ +#define MCAN_TXBCIE_CFIE25_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE25_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Mask */ +#define MCAN_TXBCIE_CFIE25 MCAN_TXBCIE_CFIE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE25_Msk instead */ +#define MCAN_TXBCIE_CFIE26_Pos 26 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Position */ +#define MCAN_TXBCIE_CFIE26_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE26_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Mask */ +#define MCAN_TXBCIE_CFIE26 MCAN_TXBCIE_CFIE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE26_Msk instead */ +#define MCAN_TXBCIE_CFIE27_Pos 27 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Position */ +#define MCAN_TXBCIE_CFIE27_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE27_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Mask */ +#define MCAN_TXBCIE_CFIE27 MCAN_TXBCIE_CFIE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE27_Msk instead */ +#define MCAN_TXBCIE_CFIE28_Pos 28 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Position */ +#define MCAN_TXBCIE_CFIE28_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE28_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Mask */ +#define MCAN_TXBCIE_CFIE28 MCAN_TXBCIE_CFIE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE28_Msk instead */ +#define MCAN_TXBCIE_CFIE29_Pos 29 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Position */ +#define MCAN_TXBCIE_CFIE29_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE29_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Mask */ +#define MCAN_TXBCIE_CFIE29 MCAN_TXBCIE_CFIE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE29_Msk instead */ +#define MCAN_TXBCIE_CFIE30_Pos 30 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Position */ +#define MCAN_TXBCIE_CFIE30_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE30_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Mask */ +#define MCAN_TXBCIE_CFIE30 MCAN_TXBCIE_CFIE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE30_Msk instead */ +#define MCAN_TXBCIE_CFIE31_Pos 31 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Position */ +#define MCAN_TXBCIE_CFIE31_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE31_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Mask */ +#define MCAN_TXBCIE_CFIE31 MCAN_TXBCIE_CFIE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE31_Msk instead */ +#define MCAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCIE) Register MASK (Use MCAN_TXBCIE_Msk instead) */ +#define MCAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCIE) Register Mask */ + +#define MCAN_TXBCIE_CFIE_Pos 0 /**< (MCAN_TXBCIE Position) Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ +#define MCAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCIE_CFIE_Pos) /**< (MCAN_TXBCIE Mask) CFIE */ +#define MCAN_TXBCIE_CFIE(value) (MCAN_TXBCIE_CFIE_Msk & ((value) << MCAN_TXBCIE_CFIE_Pos)) + +/* -------- MCAN_TXEFC : (MCAN Offset: 0xf0) (R/W 32) Transmit Event FIFO Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t EFSA:14; /**< bit: 2..15 Event FIFO Start Address */ + uint32_t EFS:6; /**< bit: 16..21 Event FIFO Size */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t EFWM:6; /**< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXEFC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXEFC_OFFSET (0xF0) /**< (MCAN_TXEFC) Transmit Event FIFO Configuration Register Offset */ + +#define MCAN_TXEFC_EFSA_Pos 2 /**< (MCAN_TXEFC) Event FIFO Start Address Position */ +#define MCAN_TXEFC_EFSA_Msk (_U_(0x3FFF) << MCAN_TXEFC_EFSA_Pos) /**< (MCAN_TXEFC) Event FIFO Start Address Mask */ +#define MCAN_TXEFC_EFSA(value) (MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)) +#define MCAN_TXEFC_EFS_Pos 16 /**< (MCAN_TXEFC) Event FIFO Size Position */ +#define MCAN_TXEFC_EFS_Msk (_U_(0x3F) << MCAN_TXEFC_EFS_Pos) /**< (MCAN_TXEFC) Event FIFO Size Mask */ +#define MCAN_TXEFC_EFS(value) (MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)) +#define MCAN_TXEFC_EFWM_Pos 24 /**< (MCAN_TXEFC) Event FIFO Watermark Position */ +#define MCAN_TXEFC_EFWM_Msk (_U_(0x3F) << MCAN_TXEFC_EFWM_Pos) /**< (MCAN_TXEFC) Event FIFO Watermark Mask */ +#define MCAN_TXEFC_EFWM(value) (MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)) +#define MCAN_TXEFC_MASK _U_(0x3F3FFFFC) /**< \deprecated (MCAN_TXEFC) Register MASK (Use MCAN_TXEFC_Msk instead) */ +#define MCAN_TXEFC_Msk _U_(0x3F3FFFFC) /**< (MCAN_TXEFC) Register Mask */ + + +/* -------- MCAN_TXEFS : (MCAN Offset: 0xf4) (R/ 32) Transmit Event FIFO Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EFFL:6; /**< bit: 0..5 Event FIFO Fill Level */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t EFGI:5; /**< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t EFPI:5; /**< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t EFF:1; /**< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /**< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXEFS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXEFS_OFFSET (0xF4) /**< (MCAN_TXEFS) Transmit Event FIFO Status Register Offset */ + +#define MCAN_TXEFS_EFFL_Pos 0 /**< (MCAN_TXEFS) Event FIFO Fill Level Position */ +#define MCAN_TXEFS_EFFL_Msk (_U_(0x3F) << MCAN_TXEFS_EFFL_Pos) /**< (MCAN_TXEFS) Event FIFO Fill Level Mask */ +#define MCAN_TXEFS_EFFL(value) (MCAN_TXEFS_EFFL_Msk & ((value) << MCAN_TXEFS_EFFL_Pos)) +#define MCAN_TXEFS_EFGI_Pos 8 /**< (MCAN_TXEFS) Event FIFO Get Index Position */ +#define MCAN_TXEFS_EFGI_Msk (_U_(0x1F) << MCAN_TXEFS_EFGI_Pos) /**< (MCAN_TXEFS) Event FIFO Get Index Mask */ +#define MCAN_TXEFS_EFGI(value) (MCAN_TXEFS_EFGI_Msk & ((value) << MCAN_TXEFS_EFGI_Pos)) +#define MCAN_TXEFS_EFPI_Pos 16 /**< (MCAN_TXEFS) Event FIFO Put Index Position */ +#define MCAN_TXEFS_EFPI_Msk (_U_(0x1F) << MCAN_TXEFS_EFPI_Pos) /**< (MCAN_TXEFS) Event FIFO Put Index Mask */ +#define MCAN_TXEFS_EFPI(value) (MCAN_TXEFS_EFPI_Msk & ((value) << MCAN_TXEFS_EFPI_Pos)) +#define MCAN_TXEFS_EFF_Pos 24 /**< (MCAN_TXEFS) Event FIFO Full Position */ +#define MCAN_TXEFS_EFF_Msk (_U_(0x1) << MCAN_TXEFS_EFF_Pos) /**< (MCAN_TXEFS) Event FIFO Full Mask */ +#define MCAN_TXEFS_EFF MCAN_TXEFS_EFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFS_EFF_Msk instead */ +#define MCAN_TXEFS_TEFL_Pos 25 /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define MCAN_TXEFS_TEFL_Msk (_U_(0x1) << MCAN_TXEFS_TEFL_Pos) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define MCAN_TXEFS_TEFL MCAN_TXEFS_TEFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFS_TEFL_Msk instead */ +#define MCAN_TXEFS_MASK _U_(0x31F1F3F) /**< \deprecated (MCAN_TXEFS) Register MASK (Use MCAN_TXEFS_Msk instead) */ +#define MCAN_TXEFS_Msk _U_(0x31F1F3F) /**< (MCAN_TXEFS) Register Mask */ + + +/* -------- MCAN_TXEFA : (MCAN Offset: 0xf8) (R/W 32) Transmit Event FIFO Acknowledge Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EFAI:5; /**< bit: 0..4 Event FIFO Acknowledge Index */ + uint32_t :27; /**< bit: 5..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} MCAN_TXEFA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define MCAN_TXEFA_OFFSET (0xF8) /**< (MCAN_TXEFA) Transmit Event FIFO Acknowledge Register Offset */ + +#define MCAN_TXEFA_EFAI_Pos 0 /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define MCAN_TXEFA_EFAI_Msk (_U_(0x1F) << MCAN_TXEFA_EFAI_Pos) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define MCAN_TXEFA_EFAI(value) (MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)) +#define MCAN_TXEFA_MASK _U_(0x1F) /**< \deprecated (MCAN_TXEFA) Register MASK (Use MCAN_TXEFA_Msk instead) */ +#define MCAN_TXEFA_Msk _U_(0x1F) /**< (MCAN_TXEFA) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief MCAN_RXBE hardware registers */ +typedef struct { /* Rx Buffer Element */ + __IO uint32_t MCAN_RXBE_0; /**< (MCAN_RXBE Offset: 0x00) Rx Buffer Element 0 */ + __IO uint32_t MCAN_RXBE_1; /**< (MCAN_RXBE Offset: 0x04) Rx Buffer Element 1 */ + __IO uint32_t MCAN_RXBE_DATA; /**< (MCAN_RXBE Offset: 0x08) Rx Buffer Element Data */ +} McanRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF0E hardware registers */ +typedef struct { /* Rx FIFO 0 Element */ + __IO uint32_t MCAN_RXF0E_0; /**< (MCAN_RXF0E Offset: 0x00) Rx FIFO 0 Element 0 */ + __IO uint32_t MCAN_RXF0E_1; /**< (MCAN_RXF0E Offset: 0x04) Rx FIFO 0 Element 1 */ + __IO uint32_t MCAN_RXF0E_DATA; /**< (MCAN_RXF0E Offset: 0x08) Rx FIFO 0 Element Data */ +} McanRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF1E hardware registers */ +typedef struct { /* Rx FIFO 1 Element */ + __IO uint32_t MCAN_RXF1E_0; /**< (MCAN_RXF1E Offset: 0x00) Rx FIFO 1 Element 0 */ + __IO uint32_t MCAN_RXF1E_1; /**< (MCAN_RXF1E Offset: 0x04) Rx FIFO 1 Element 1 */ + __IO uint32_t MCAN_RXF1E_DATA; /**< (MCAN_RXF1E Offset: 0x08) Rx FIFO 1 Element Data */ +} McanRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXBE hardware registers */ +typedef struct { /* Tx Buffer Element */ + __IO uint32_t MCAN_TXBE_0; /**< (MCAN_TXBE Offset: 0x00) Tx Buffer Element 0 */ + __IO uint32_t MCAN_TXBE_1; /**< (MCAN_TXBE Offset: 0x04) Tx Buffer Element 1 */ + __IO uint32_t MCAN_TXBE_DATA; /**< (MCAN_TXBE Offset: 0x08) Tx Buffer Element Data */ +} McanTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXEFE hardware registers */ +typedef struct { /* Tx Event FIFO Element */ + __IO uint32_t MCAN_TXEFE_0; /**< (MCAN_TXEFE Offset: 0x00) Tx Event FIFO Element 0 */ + __IO uint32_t MCAN_TXEFE_1; /**< (MCAN_TXEFE Offset: 0x04) Tx Event FIFO Element 1 */ +} McanTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_SIDFE hardware registers */ +typedef struct { /* Standard Message ID Filter Element */ + __IO uint32_t MCAN_SIDFE_0; /**< (MCAN_SIDFE Offset: 0x00) Standard Message ID Filter Element 0 */ +} McanSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_XIDFE hardware registers */ +typedef struct { /* Extended Message ID Filter Element */ + __IO uint32_t MCAN_XIDFE_0; /**< (MCAN_XIDFE Offset: 0x00) Extended Message ID Filter Element 0 */ + __IO uint32_t MCAN_XIDFE_1; /**< (MCAN_XIDFE Offset: 0x04) Extended Message ID Filter Element 1 */ +} McanXidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN hardware registers */ +typedef struct { + __I uint32_t MCAN_CREL; /**< (MCAN Offset: 0x00) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< (MCAN Offset: 0x04) Endian Register */ + __IO uint32_t MCAN_CUST; /**< (MCAN Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_DBTP; /**< (MCAN Offset: 0x0C) Data Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< (MCAN Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< (MCAN Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< (MCAN Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_NBTP; /**< (MCAN Offset: 0x1C) Nominal Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< (MCAN Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< (MCAN Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< (MCAN Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< (MCAN Offset: 0x2C) Timeout Counter Value Register */ + __I uint8_t Reserved1[16]; + __I uint32_t MCAN_ECR; /**< (MCAN Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< (MCAN Offset: 0x44) Protocol Status Register */ + __IO uint32_t MCAN_TDCR; /**< (MCAN Offset: 0x48) Transmit Delay Compensation Register */ + __I uint8_t Reserved2[4]; + __IO uint32_t MCAN_IR; /**< (MCAN Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< (MCAN Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< (MCAN Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< (MCAN Offset: 0x5C) Interrupt Line Enable Register */ + __I uint8_t Reserved3[32]; + __IO uint32_t MCAN_GFC; /**< (MCAN Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< (MCAN Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< (MCAN Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint8_t Reserved4[4]; + __IO uint32_t MCAN_XIDAM; /**< (MCAN Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< (MCAN Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< (MCAN Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< (MCAN Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< (MCAN Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< (MCAN Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< (MCAN Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< (MCAN Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint8_t Reserved5[8]; + __IO uint32_t MCAN_TXEFC; /**< (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< (MCAN Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief MCAN_RXBE hardware registers */ +typedef struct { /* Rx Buffer Element */ + __IO MCAN_RXBE_0_Type MCAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO MCAN_RXBE_1_Type MCAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO MCAN_RXBE_DATA_Type MCAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} McanRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF0E hardware registers */ +typedef struct { /* Rx FIFO 0 Element */ + __IO MCAN_RXF0E_0_Type MCAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO MCAN_RXF0E_1_Type MCAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO MCAN_RXF0E_DATA_Type MCAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} McanRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF1E hardware registers */ +typedef struct { /* Rx FIFO 1 Element */ + __IO MCAN_RXF1E_0_Type MCAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO MCAN_RXF1E_1_Type MCAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO MCAN_RXF1E_DATA_Type MCAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} McanRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXBE hardware registers */ +typedef struct { /* Tx Buffer Element */ + __IO MCAN_TXBE_0_Type MCAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO MCAN_TXBE_1_Type MCAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO MCAN_TXBE_DATA_Type MCAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} McanTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXEFE hardware registers */ +typedef struct { /* Tx Event FIFO Element */ + __IO MCAN_TXEFE_0_Type MCAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO MCAN_TXEFE_1_Type MCAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} McanTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_SIDFE hardware registers */ +typedef struct { /* Standard Message ID Filter Element */ + __IO MCAN_SIDFE_0_Type MCAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} McanSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_XIDFE hardware registers */ +typedef struct { /* Extended Message ID Filter Element */ + __IO MCAN_XIDFE_0_Type MCAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO MCAN_XIDFE_1_Type MCAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} McanXidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN hardware registers */ +typedef struct { + __I MCAN_CREL_Type MCAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release Register */ + __I MCAN_ENDN_Type MCAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian Register */ + __IO MCAN_CUST_Type MCAN_CUST; /**< Offset: 0x08 (R/W 32) Customer Register */ + __IO MCAN_DBTP_Type MCAN_DBTP; /**< Offset: 0x0C (R/W 32) Data Bit Timing and Prescaler Register */ + __IO MCAN_TEST_Type MCAN_TEST; /**< Offset: 0x10 (R/W 32) Test Register */ + __IO MCAN_RWD_Type MCAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog Register */ + __IO MCAN_CCCR_Type MCAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control Register */ + __IO MCAN_NBTP_Type MCAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler Register */ + __IO MCAN_TSCC_Type MCAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration Register */ + __IO MCAN_TSCV_Type MCAN_TSCV; /**< Offset: 0x24 (R/W 32) Timestamp Counter Value Register */ + __IO MCAN_TOCC_Type MCAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration Register */ + __IO MCAN_TOCV_Type MCAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value Register */ + __I uint8_t Reserved1[16]; + __I MCAN_ECR_Type MCAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter Register */ + __I MCAN_PSR_Type MCAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status Register */ + __IO MCAN_TDCR_Type MCAN_TDCR; /**< Offset: 0x48 (R/W 32) Transmit Delay Compensation Register */ + __I uint8_t Reserved2[4]; + __IO MCAN_IR_Type MCAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt Register */ + __IO MCAN_IE_Type MCAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable Register */ + __IO MCAN_ILS_Type MCAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select Register */ + __IO MCAN_ILE_Type MCAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable Register */ + __I uint8_t Reserved3[32]; + __IO MCAN_GFC_Type MCAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration Register */ + __IO MCAN_SIDFC_Type MCAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration Register */ + __IO MCAN_XIDFC_Type MCAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration Register */ + __I uint8_t Reserved4[4]; + __IO MCAN_XIDAM_Type MCAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask Register */ + __I MCAN_HPMS_Type MCAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status Register */ + __IO MCAN_NDAT1_Type MCAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 Register */ + __IO MCAN_NDAT2_Type MCAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 Register */ + __IO MCAN_RXF0C_Type MCAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Receive FIFO 0 Configuration Register */ + __I MCAN_RXF0S_Type MCAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Receive FIFO 0 Status Register */ + __IO MCAN_RXF0A_Type MCAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Receive FIFO 0 Acknowledge Register */ + __IO MCAN_RXBC_Type MCAN_RXBC; /**< Offset: 0xAC (R/W 32) Receive Rx Buffer Configuration Register */ + __IO MCAN_RXF1C_Type MCAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Receive FIFO 1 Configuration Register */ + __I MCAN_RXF1S_Type MCAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Receive FIFO 1 Status Register */ + __IO MCAN_RXF1A_Type MCAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Receive FIFO 1 Acknowledge Register */ + __IO MCAN_RXESC_Type MCAN_RXESC; /**< Offset: 0xBC (R/W 32) Receive Buffer / FIFO Element Size Configuration Register */ + __IO MCAN_TXBC_Type MCAN_TXBC; /**< Offset: 0xC0 (R/W 32) Transmit Buffer Configuration Register */ + __I MCAN_TXFQS_Type MCAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Transmit FIFO/Queue Status Register */ + __IO MCAN_TXESC_Type MCAN_TXESC; /**< Offset: 0xC8 (R/W 32) Transmit Buffer Element Size Configuration Register */ + __I MCAN_TXBRP_Type MCAN_TXBRP; /**< Offset: 0xCC (R/ 32) Transmit Buffer Request Pending Register */ + __IO MCAN_TXBAR_Type MCAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Transmit Buffer Add Request Register */ + __IO MCAN_TXBCR_Type MCAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Transmit Buffer Cancellation Request Register */ + __I MCAN_TXBTO_Type MCAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Transmit Buffer Transmission Occurred Register */ + __I MCAN_TXBCF_Type MCAN_TXBCF; /**< Offset: 0xDC (R/ 32) Transmit Buffer Cancellation Finished Register */ + __IO MCAN_TXBTIE_Type MCAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Transmit Buffer Transmission Interrupt Enable Register */ + __IO MCAN_TXBCIE_Type MCAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint8_t Reserved5[8]; + __IO MCAN_TXEFC_Type MCAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Transmit Event FIFO Configuration Register */ + __I MCAN_TXEFS_Type MCAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Transmit Event FIFO Status Register */ + __IO MCAN_TXEFA_Type MCAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Transmit Event FIFO Acknowledge Register */ +} Mcan; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Controller Area Network */ + +#endif /* _SAME70_MCAN_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/pio.h b/bsp/microchip/same70/bsp/same70b/include/component/pio.h new file mode 100644 index 0000000000..c722826a52 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/pio.h @@ -0,0 +1,7397 @@ +/** + * \file + * + * \brief Component description for PIO + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIO_COMPONENT_H_ +#define _SAME70_PIO_COMPONENT_H_ +#define _SAME70_PIO_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Parallel Input/Output Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PIO */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define PIO_11004 /**< (PIO) Module ID */ +#define REV_PIO V /**< (PIO) Module revision */ + +/* -------- PIO_PER : (PIO Offset: 0x00) (/W 32) PIO Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 PIO Enable */ + uint32_t P1:1; /**< bit: 1 PIO Enable */ + uint32_t P2:1; /**< bit: 2 PIO Enable */ + uint32_t P3:1; /**< bit: 3 PIO Enable */ + uint32_t P4:1; /**< bit: 4 PIO Enable */ + uint32_t P5:1; /**< bit: 5 PIO Enable */ + uint32_t P6:1; /**< bit: 6 PIO Enable */ + uint32_t P7:1; /**< bit: 7 PIO Enable */ + uint32_t P8:1; /**< bit: 8 PIO Enable */ + uint32_t P9:1; /**< bit: 9 PIO Enable */ + uint32_t P10:1; /**< bit: 10 PIO Enable */ + uint32_t P11:1; /**< bit: 11 PIO Enable */ + uint32_t P12:1; /**< bit: 12 PIO Enable */ + uint32_t P13:1; /**< bit: 13 PIO Enable */ + uint32_t P14:1; /**< bit: 14 PIO Enable */ + uint32_t P15:1; /**< bit: 15 PIO Enable */ + uint32_t P16:1; /**< bit: 16 PIO Enable */ + uint32_t P17:1; /**< bit: 17 PIO Enable */ + uint32_t P18:1; /**< bit: 18 PIO Enable */ + uint32_t P19:1; /**< bit: 19 PIO Enable */ + uint32_t P20:1; /**< bit: 20 PIO Enable */ + uint32_t P21:1; /**< bit: 21 PIO Enable */ + uint32_t P22:1; /**< bit: 22 PIO Enable */ + uint32_t P23:1; /**< bit: 23 PIO Enable */ + uint32_t P24:1; /**< bit: 24 PIO Enable */ + uint32_t P25:1; /**< bit: 25 PIO Enable */ + uint32_t P26:1; /**< bit: 26 PIO Enable */ + uint32_t P27:1; /**< bit: 27 PIO Enable */ + uint32_t P28:1; /**< bit: 28 PIO Enable */ + uint32_t P29:1; /**< bit: 29 PIO Enable */ + uint32_t P30:1; /**< bit: 30 PIO Enable */ + uint32_t P31:1; /**< bit: 31 PIO Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 PIO Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PER_OFFSET (0x00) /**< (PIO_PER) PIO Enable Register Offset */ + +#define PIO_PER_P0_Pos 0 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P0_Msk (_U_(0x1) << PIO_PER_P0_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P0 PIO_PER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P0_Msk instead */ +#define PIO_PER_P1_Pos 1 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P1_Msk (_U_(0x1) << PIO_PER_P1_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P1 PIO_PER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P1_Msk instead */ +#define PIO_PER_P2_Pos 2 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P2_Msk (_U_(0x1) << PIO_PER_P2_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P2 PIO_PER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P2_Msk instead */ +#define PIO_PER_P3_Pos 3 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P3_Msk (_U_(0x1) << PIO_PER_P3_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P3 PIO_PER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P3_Msk instead */ +#define PIO_PER_P4_Pos 4 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P4_Msk (_U_(0x1) << PIO_PER_P4_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P4 PIO_PER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P4_Msk instead */ +#define PIO_PER_P5_Pos 5 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P5_Msk (_U_(0x1) << PIO_PER_P5_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P5 PIO_PER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P5_Msk instead */ +#define PIO_PER_P6_Pos 6 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P6_Msk (_U_(0x1) << PIO_PER_P6_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P6 PIO_PER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P6_Msk instead */ +#define PIO_PER_P7_Pos 7 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P7_Msk (_U_(0x1) << PIO_PER_P7_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P7 PIO_PER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P7_Msk instead */ +#define PIO_PER_P8_Pos 8 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P8_Msk (_U_(0x1) << PIO_PER_P8_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P8 PIO_PER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P8_Msk instead */ +#define PIO_PER_P9_Pos 9 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P9_Msk (_U_(0x1) << PIO_PER_P9_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P9 PIO_PER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P9_Msk instead */ +#define PIO_PER_P10_Pos 10 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P10_Msk (_U_(0x1) << PIO_PER_P10_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P10 PIO_PER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P10_Msk instead */ +#define PIO_PER_P11_Pos 11 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P11_Msk (_U_(0x1) << PIO_PER_P11_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P11 PIO_PER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P11_Msk instead */ +#define PIO_PER_P12_Pos 12 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P12_Msk (_U_(0x1) << PIO_PER_P12_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P12 PIO_PER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P12_Msk instead */ +#define PIO_PER_P13_Pos 13 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P13_Msk (_U_(0x1) << PIO_PER_P13_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P13 PIO_PER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P13_Msk instead */ +#define PIO_PER_P14_Pos 14 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P14_Msk (_U_(0x1) << PIO_PER_P14_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P14 PIO_PER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P14_Msk instead */ +#define PIO_PER_P15_Pos 15 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P15_Msk (_U_(0x1) << PIO_PER_P15_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P15 PIO_PER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P15_Msk instead */ +#define PIO_PER_P16_Pos 16 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P16_Msk (_U_(0x1) << PIO_PER_P16_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P16 PIO_PER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P16_Msk instead */ +#define PIO_PER_P17_Pos 17 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P17_Msk (_U_(0x1) << PIO_PER_P17_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P17 PIO_PER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P17_Msk instead */ +#define PIO_PER_P18_Pos 18 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P18_Msk (_U_(0x1) << PIO_PER_P18_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P18 PIO_PER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P18_Msk instead */ +#define PIO_PER_P19_Pos 19 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P19_Msk (_U_(0x1) << PIO_PER_P19_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P19 PIO_PER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P19_Msk instead */ +#define PIO_PER_P20_Pos 20 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P20_Msk (_U_(0x1) << PIO_PER_P20_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P20 PIO_PER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P20_Msk instead */ +#define PIO_PER_P21_Pos 21 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P21_Msk (_U_(0x1) << PIO_PER_P21_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P21 PIO_PER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P21_Msk instead */ +#define PIO_PER_P22_Pos 22 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P22_Msk (_U_(0x1) << PIO_PER_P22_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P22 PIO_PER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P22_Msk instead */ +#define PIO_PER_P23_Pos 23 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P23_Msk (_U_(0x1) << PIO_PER_P23_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P23 PIO_PER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P23_Msk instead */ +#define PIO_PER_P24_Pos 24 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P24_Msk (_U_(0x1) << PIO_PER_P24_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P24 PIO_PER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P24_Msk instead */ +#define PIO_PER_P25_Pos 25 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P25_Msk (_U_(0x1) << PIO_PER_P25_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P25 PIO_PER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P25_Msk instead */ +#define PIO_PER_P26_Pos 26 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P26_Msk (_U_(0x1) << PIO_PER_P26_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P26 PIO_PER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P26_Msk instead */ +#define PIO_PER_P27_Pos 27 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P27_Msk (_U_(0x1) << PIO_PER_P27_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P27 PIO_PER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P27_Msk instead */ +#define PIO_PER_P28_Pos 28 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P28_Msk (_U_(0x1) << PIO_PER_P28_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P28 PIO_PER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P28_Msk instead */ +#define PIO_PER_P29_Pos 29 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P29_Msk (_U_(0x1) << PIO_PER_P29_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P29 PIO_PER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P29_Msk instead */ +#define PIO_PER_P30_Pos 30 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P30_Msk (_U_(0x1) << PIO_PER_P30_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P30 PIO_PER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P30_Msk instead */ +#define PIO_PER_P31_Pos 31 /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P31_Msk (_U_(0x1) << PIO_PER_P31_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P31 PIO_PER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PER_P31_Msk instead */ +#define PIO_PER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PER) Register MASK (Use PIO_PER_Msk instead) */ +#define PIO_PER_Msk _U_(0xFFFFFFFF) /**< (PIO_PER) Register Mask */ + +#define PIO_PER_P_Pos 0 /**< (PIO_PER Position) PIO Enable */ +#define PIO_PER_P_Msk (_U_(0xFFFFFFFF) << PIO_PER_P_Pos) /**< (PIO_PER Mask) P */ +#define PIO_PER_P(value) (PIO_PER_P_Msk & ((value) << PIO_PER_P_Pos)) + +/* -------- PIO_PDR : (PIO Offset: 0x04) (/W 32) PIO Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 PIO Disable */ + uint32_t P1:1; /**< bit: 1 PIO Disable */ + uint32_t P2:1; /**< bit: 2 PIO Disable */ + uint32_t P3:1; /**< bit: 3 PIO Disable */ + uint32_t P4:1; /**< bit: 4 PIO Disable */ + uint32_t P5:1; /**< bit: 5 PIO Disable */ + uint32_t P6:1; /**< bit: 6 PIO Disable */ + uint32_t P7:1; /**< bit: 7 PIO Disable */ + uint32_t P8:1; /**< bit: 8 PIO Disable */ + uint32_t P9:1; /**< bit: 9 PIO Disable */ + uint32_t P10:1; /**< bit: 10 PIO Disable */ + uint32_t P11:1; /**< bit: 11 PIO Disable */ + uint32_t P12:1; /**< bit: 12 PIO Disable */ + uint32_t P13:1; /**< bit: 13 PIO Disable */ + uint32_t P14:1; /**< bit: 14 PIO Disable */ + uint32_t P15:1; /**< bit: 15 PIO Disable */ + uint32_t P16:1; /**< bit: 16 PIO Disable */ + uint32_t P17:1; /**< bit: 17 PIO Disable */ + uint32_t P18:1; /**< bit: 18 PIO Disable */ + uint32_t P19:1; /**< bit: 19 PIO Disable */ + uint32_t P20:1; /**< bit: 20 PIO Disable */ + uint32_t P21:1; /**< bit: 21 PIO Disable */ + uint32_t P22:1; /**< bit: 22 PIO Disable */ + uint32_t P23:1; /**< bit: 23 PIO Disable */ + uint32_t P24:1; /**< bit: 24 PIO Disable */ + uint32_t P25:1; /**< bit: 25 PIO Disable */ + uint32_t P26:1; /**< bit: 26 PIO Disable */ + uint32_t P27:1; /**< bit: 27 PIO Disable */ + uint32_t P28:1; /**< bit: 28 PIO Disable */ + uint32_t P29:1; /**< bit: 29 PIO Disable */ + uint32_t P30:1; /**< bit: 30 PIO Disable */ + uint32_t P31:1; /**< bit: 31 PIO Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 PIO Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PDR_OFFSET (0x04) /**< (PIO_PDR) PIO Disable Register Offset */ + +#define PIO_PDR_P0_Pos 0 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P0_Msk (_U_(0x1) << PIO_PDR_P0_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P0 PIO_PDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P0_Msk instead */ +#define PIO_PDR_P1_Pos 1 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P1_Msk (_U_(0x1) << PIO_PDR_P1_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P1 PIO_PDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P1_Msk instead */ +#define PIO_PDR_P2_Pos 2 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P2_Msk (_U_(0x1) << PIO_PDR_P2_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P2 PIO_PDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P2_Msk instead */ +#define PIO_PDR_P3_Pos 3 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P3_Msk (_U_(0x1) << PIO_PDR_P3_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P3 PIO_PDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P3_Msk instead */ +#define PIO_PDR_P4_Pos 4 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P4_Msk (_U_(0x1) << PIO_PDR_P4_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P4 PIO_PDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P4_Msk instead */ +#define PIO_PDR_P5_Pos 5 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P5_Msk (_U_(0x1) << PIO_PDR_P5_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P5 PIO_PDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P5_Msk instead */ +#define PIO_PDR_P6_Pos 6 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P6_Msk (_U_(0x1) << PIO_PDR_P6_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P6 PIO_PDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P6_Msk instead */ +#define PIO_PDR_P7_Pos 7 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P7_Msk (_U_(0x1) << PIO_PDR_P7_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P7 PIO_PDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P7_Msk instead */ +#define PIO_PDR_P8_Pos 8 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P8_Msk (_U_(0x1) << PIO_PDR_P8_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P8 PIO_PDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P8_Msk instead */ +#define PIO_PDR_P9_Pos 9 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P9_Msk (_U_(0x1) << PIO_PDR_P9_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P9 PIO_PDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P9_Msk instead */ +#define PIO_PDR_P10_Pos 10 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P10_Msk (_U_(0x1) << PIO_PDR_P10_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P10 PIO_PDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P10_Msk instead */ +#define PIO_PDR_P11_Pos 11 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P11_Msk (_U_(0x1) << PIO_PDR_P11_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P11 PIO_PDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P11_Msk instead */ +#define PIO_PDR_P12_Pos 12 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P12_Msk (_U_(0x1) << PIO_PDR_P12_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P12 PIO_PDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P12_Msk instead */ +#define PIO_PDR_P13_Pos 13 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P13_Msk (_U_(0x1) << PIO_PDR_P13_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P13 PIO_PDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P13_Msk instead */ +#define PIO_PDR_P14_Pos 14 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P14_Msk (_U_(0x1) << PIO_PDR_P14_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P14 PIO_PDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P14_Msk instead */ +#define PIO_PDR_P15_Pos 15 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P15_Msk (_U_(0x1) << PIO_PDR_P15_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P15 PIO_PDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P15_Msk instead */ +#define PIO_PDR_P16_Pos 16 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P16_Msk (_U_(0x1) << PIO_PDR_P16_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P16 PIO_PDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P16_Msk instead */ +#define PIO_PDR_P17_Pos 17 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P17_Msk (_U_(0x1) << PIO_PDR_P17_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P17 PIO_PDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P17_Msk instead */ +#define PIO_PDR_P18_Pos 18 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P18_Msk (_U_(0x1) << PIO_PDR_P18_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P18 PIO_PDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P18_Msk instead */ +#define PIO_PDR_P19_Pos 19 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P19_Msk (_U_(0x1) << PIO_PDR_P19_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P19 PIO_PDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P19_Msk instead */ +#define PIO_PDR_P20_Pos 20 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P20_Msk (_U_(0x1) << PIO_PDR_P20_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P20 PIO_PDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P20_Msk instead */ +#define PIO_PDR_P21_Pos 21 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P21_Msk (_U_(0x1) << PIO_PDR_P21_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P21 PIO_PDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P21_Msk instead */ +#define PIO_PDR_P22_Pos 22 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P22_Msk (_U_(0x1) << PIO_PDR_P22_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P22 PIO_PDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P22_Msk instead */ +#define PIO_PDR_P23_Pos 23 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P23_Msk (_U_(0x1) << PIO_PDR_P23_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P23 PIO_PDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P23_Msk instead */ +#define PIO_PDR_P24_Pos 24 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P24_Msk (_U_(0x1) << PIO_PDR_P24_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P24 PIO_PDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P24_Msk instead */ +#define PIO_PDR_P25_Pos 25 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P25_Msk (_U_(0x1) << PIO_PDR_P25_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P25 PIO_PDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P25_Msk instead */ +#define PIO_PDR_P26_Pos 26 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P26_Msk (_U_(0x1) << PIO_PDR_P26_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P26 PIO_PDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P26_Msk instead */ +#define PIO_PDR_P27_Pos 27 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P27_Msk (_U_(0x1) << PIO_PDR_P27_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P27 PIO_PDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P27_Msk instead */ +#define PIO_PDR_P28_Pos 28 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P28_Msk (_U_(0x1) << PIO_PDR_P28_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P28 PIO_PDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P28_Msk instead */ +#define PIO_PDR_P29_Pos 29 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P29_Msk (_U_(0x1) << PIO_PDR_P29_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P29 PIO_PDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P29_Msk instead */ +#define PIO_PDR_P30_Pos 30 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P30_Msk (_U_(0x1) << PIO_PDR_P30_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P30 PIO_PDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P30_Msk instead */ +#define PIO_PDR_P31_Pos 31 /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P31_Msk (_U_(0x1) << PIO_PDR_P31_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P31 PIO_PDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDR_P31_Msk instead */ +#define PIO_PDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PDR) Register MASK (Use PIO_PDR_Msk instead) */ +#define PIO_PDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDR) Register Mask */ + +#define PIO_PDR_P_Pos 0 /**< (PIO_PDR Position) PIO Disable */ +#define PIO_PDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDR_P_Pos) /**< (PIO_PDR Mask) P */ +#define PIO_PDR_P(value) (PIO_PDR_P_Msk & ((value) << PIO_PDR_P_Pos)) + +/* -------- PIO_PSR : (PIO Offset: 0x08) (R/ 32) PIO Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 PIO Status */ + uint32_t P1:1; /**< bit: 1 PIO Status */ + uint32_t P2:1; /**< bit: 2 PIO Status */ + uint32_t P3:1; /**< bit: 3 PIO Status */ + uint32_t P4:1; /**< bit: 4 PIO Status */ + uint32_t P5:1; /**< bit: 5 PIO Status */ + uint32_t P6:1; /**< bit: 6 PIO Status */ + uint32_t P7:1; /**< bit: 7 PIO Status */ + uint32_t P8:1; /**< bit: 8 PIO Status */ + uint32_t P9:1; /**< bit: 9 PIO Status */ + uint32_t P10:1; /**< bit: 10 PIO Status */ + uint32_t P11:1; /**< bit: 11 PIO Status */ + uint32_t P12:1; /**< bit: 12 PIO Status */ + uint32_t P13:1; /**< bit: 13 PIO Status */ + uint32_t P14:1; /**< bit: 14 PIO Status */ + uint32_t P15:1; /**< bit: 15 PIO Status */ + uint32_t P16:1; /**< bit: 16 PIO Status */ + uint32_t P17:1; /**< bit: 17 PIO Status */ + uint32_t P18:1; /**< bit: 18 PIO Status */ + uint32_t P19:1; /**< bit: 19 PIO Status */ + uint32_t P20:1; /**< bit: 20 PIO Status */ + uint32_t P21:1; /**< bit: 21 PIO Status */ + uint32_t P22:1; /**< bit: 22 PIO Status */ + uint32_t P23:1; /**< bit: 23 PIO Status */ + uint32_t P24:1; /**< bit: 24 PIO Status */ + uint32_t P25:1; /**< bit: 25 PIO Status */ + uint32_t P26:1; /**< bit: 26 PIO Status */ + uint32_t P27:1; /**< bit: 27 PIO Status */ + uint32_t P28:1; /**< bit: 28 PIO Status */ + uint32_t P29:1; /**< bit: 29 PIO Status */ + uint32_t P30:1; /**< bit: 30 PIO Status */ + uint32_t P31:1; /**< bit: 31 PIO Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 PIO Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PSR_OFFSET (0x08) /**< (PIO_PSR) PIO Status Register Offset */ + +#define PIO_PSR_P0_Pos 0 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P0_Msk (_U_(0x1) << PIO_PSR_P0_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P0 PIO_PSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P0_Msk instead */ +#define PIO_PSR_P1_Pos 1 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P1_Msk (_U_(0x1) << PIO_PSR_P1_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P1 PIO_PSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P1_Msk instead */ +#define PIO_PSR_P2_Pos 2 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P2_Msk (_U_(0x1) << PIO_PSR_P2_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P2 PIO_PSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P2_Msk instead */ +#define PIO_PSR_P3_Pos 3 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P3_Msk (_U_(0x1) << PIO_PSR_P3_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P3 PIO_PSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P3_Msk instead */ +#define PIO_PSR_P4_Pos 4 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P4_Msk (_U_(0x1) << PIO_PSR_P4_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P4 PIO_PSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P4_Msk instead */ +#define PIO_PSR_P5_Pos 5 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P5_Msk (_U_(0x1) << PIO_PSR_P5_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P5 PIO_PSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P5_Msk instead */ +#define PIO_PSR_P6_Pos 6 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P6_Msk (_U_(0x1) << PIO_PSR_P6_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P6 PIO_PSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P6_Msk instead */ +#define PIO_PSR_P7_Pos 7 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P7_Msk (_U_(0x1) << PIO_PSR_P7_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P7 PIO_PSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P7_Msk instead */ +#define PIO_PSR_P8_Pos 8 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P8_Msk (_U_(0x1) << PIO_PSR_P8_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P8 PIO_PSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P8_Msk instead */ +#define PIO_PSR_P9_Pos 9 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P9_Msk (_U_(0x1) << PIO_PSR_P9_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P9 PIO_PSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P9_Msk instead */ +#define PIO_PSR_P10_Pos 10 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P10_Msk (_U_(0x1) << PIO_PSR_P10_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P10 PIO_PSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P10_Msk instead */ +#define PIO_PSR_P11_Pos 11 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P11_Msk (_U_(0x1) << PIO_PSR_P11_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P11 PIO_PSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P11_Msk instead */ +#define PIO_PSR_P12_Pos 12 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P12_Msk (_U_(0x1) << PIO_PSR_P12_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P12 PIO_PSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P12_Msk instead */ +#define PIO_PSR_P13_Pos 13 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P13_Msk (_U_(0x1) << PIO_PSR_P13_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P13 PIO_PSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P13_Msk instead */ +#define PIO_PSR_P14_Pos 14 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P14_Msk (_U_(0x1) << PIO_PSR_P14_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P14 PIO_PSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P14_Msk instead */ +#define PIO_PSR_P15_Pos 15 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P15_Msk (_U_(0x1) << PIO_PSR_P15_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P15 PIO_PSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P15_Msk instead */ +#define PIO_PSR_P16_Pos 16 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P16_Msk (_U_(0x1) << PIO_PSR_P16_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P16 PIO_PSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P16_Msk instead */ +#define PIO_PSR_P17_Pos 17 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P17_Msk (_U_(0x1) << PIO_PSR_P17_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P17 PIO_PSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P17_Msk instead */ +#define PIO_PSR_P18_Pos 18 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P18_Msk (_U_(0x1) << PIO_PSR_P18_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P18 PIO_PSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P18_Msk instead */ +#define PIO_PSR_P19_Pos 19 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P19_Msk (_U_(0x1) << PIO_PSR_P19_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P19 PIO_PSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P19_Msk instead */ +#define PIO_PSR_P20_Pos 20 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P20_Msk (_U_(0x1) << PIO_PSR_P20_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P20 PIO_PSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P20_Msk instead */ +#define PIO_PSR_P21_Pos 21 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P21_Msk (_U_(0x1) << PIO_PSR_P21_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P21 PIO_PSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P21_Msk instead */ +#define PIO_PSR_P22_Pos 22 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P22_Msk (_U_(0x1) << PIO_PSR_P22_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P22 PIO_PSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P22_Msk instead */ +#define PIO_PSR_P23_Pos 23 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P23_Msk (_U_(0x1) << PIO_PSR_P23_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P23 PIO_PSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P23_Msk instead */ +#define PIO_PSR_P24_Pos 24 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P24_Msk (_U_(0x1) << PIO_PSR_P24_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P24 PIO_PSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P24_Msk instead */ +#define PIO_PSR_P25_Pos 25 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P25_Msk (_U_(0x1) << PIO_PSR_P25_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P25 PIO_PSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P25_Msk instead */ +#define PIO_PSR_P26_Pos 26 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P26_Msk (_U_(0x1) << PIO_PSR_P26_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P26 PIO_PSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P26_Msk instead */ +#define PIO_PSR_P27_Pos 27 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P27_Msk (_U_(0x1) << PIO_PSR_P27_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P27 PIO_PSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P27_Msk instead */ +#define PIO_PSR_P28_Pos 28 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P28_Msk (_U_(0x1) << PIO_PSR_P28_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P28 PIO_PSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P28_Msk instead */ +#define PIO_PSR_P29_Pos 29 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P29_Msk (_U_(0x1) << PIO_PSR_P29_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P29 PIO_PSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P29_Msk instead */ +#define PIO_PSR_P30_Pos 30 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P30_Msk (_U_(0x1) << PIO_PSR_P30_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P30 PIO_PSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P30_Msk instead */ +#define PIO_PSR_P31_Pos 31 /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P31_Msk (_U_(0x1) << PIO_PSR_P31_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P31 PIO_PSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PSR_P31_Msk instead */ +#define PIO_PSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PSR) Register MASK (Use PIO_PSR_Msk instead) */ +#define PIO_PSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PSR) Register Mask */ + +#define PIO_PSR_P_Pos 0 /**< (PIO_PSR Position) PIO Status */ +#define PIO_PSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PSR_P_Pos) /**< (PIO_PSR Mask) P */ +#define PIO_PSR_P(value) (PIO_PSR_P_Msk & ((value) << PIO_PSR_P_Pos)) + +/* -------- PIO_OER : (PIO Offset: 0x10) (/W 32) Output Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Enable */ + uint32_t P1:1; /**< bit: 1 Output Enable */ + uint32_t P2:1; /**< bit: 2 Output Enable */ + uint32_t P3:1; /**< bit: 3 Output Enable */ + uint32_t P4:1; /**< bit: 4 Output Enable */ + uint32_t P5:1; /**< bit: 5 Output Enable */ + uint32_t P6:1; /**< bit: 6 Output Enable */ + uint32_t P7:1; /**< bit: 7 Output Enable */ + uint32_t P8:1; /**< bit: 8 Output Enable */ + uint32_t P9:1; /**< bit: 9 Output Enable */ + uint32_t P10:1; /**< bit: 10 Output Enable */ + uint32_t P11:1; /**< bit: 11 Output Enable */ + uint32_t P12:1; /**< bit: 12 Output Enable */ + uint32_t P13:1; /**< bit: 13 Output Enable */ + uint32_t P14:1; /**< bit: 14 Output Enable */ + uint32_t P15:1; /**< bit: 15 Output Enable */ + uint32_t P16:1; /**< bit: 16 Output Enable */ + uint32_t P17:1; /**< bit: 17 Output Enable */ + uint32_t P18:1; /**< bit: 18 Output Enable */ + uint32_t P19:1; /**< bit: 19 Output Enable */ + uint32_t P20:1; /**< bit: 20 Output Enable */ + uint32_t P21:1; /**< bit: 21 Output Enable */ + uint32_t P22:1; /**< bit: 22 Output Enable */ + uint32_t P23:1; /**< bit: 23 Output Enable */ + uint32_t P24:1; /**< bit: 24 Output Enable */ + uint32_t P25:1; /**< bit: 25 Output Enable */ + uint32_t P26:1; /**< bit: 26 Output Enable */ + uint32_t P27:1; /**< bit: 27 Output Enable */ + uint32_t P28:1; /**< bit: 28 Output Enable */ + uint32_t P29:1; /**< bit: 29 Output Enable */ + uint32_t P30:1; /**< bit: 30 Output Enable */ + uint32_t P31:1; /**< bit: 31 Output Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_OER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_OER_OFFSET (0x10) /**< (PIO_OER) Output Enable Register Offset */ + +#define PIO_OER_P0_Pos 0 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P0_Msk (_U_(0x1) << PIO_OER_P0_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P0 PIO_OER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P0_Msk instead */ +#define PIO_OER_P1_Pos 1 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P1_Msk (_U_(0x1) << PIO_OER_P1_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P1 PIO_OER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P1_Msk instead */ +#define PIO_OER_P2_Pos 2 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P2_Msk (_U_(0x1) << PIO_OER_P2_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P2 PIO_OER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P2_Msk instead */ +#define PIO_OER_P3_Pos 3 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P3_Msk (_U_(0x1) << PIO_OER_P3_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P3 PIO_OER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P3_Msk instead */ +#define PIO_OER_P4_Pos 4 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P4_Msk (_U_(0x1) << PIO_OER_P4_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P4 PIO_OER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P4_Msk instead */ +#define PIO_OER_P5_Pos 5 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P5_Msk (_U_(0x1) << PIO_OER_P5_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P5 PIO_OER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P5_Msk instead */ +#define PIO_OER_P6_Pos 6 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P6_Msk (_U_(0x1) << PIO_OER_P6_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P6 PIO_OER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P6_Msk instead */ +#define PIO_OER_P7_Pos 7 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P7_Msk (_U_(0x1) << PIO_OER_P7_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P7 PIO_OER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P7_Msk instead */ +#define PIO_OER_P8_Pos 8 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P8_Msk (_U_(0x1) << PIO_OER_P8_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P8 PIO_OER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P8_Msk instead */ +#define PIO_OER_P9_Pos 9 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P9_Msk (_U_(0x1) << PIO_OER_P9_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P9 PIO_OER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P9_Msk instead */ +#define PIO_OER_P10_Pos 10 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P10_Msk (_U_(0x1) << PIO_OER_P10_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P10 PIO_OER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P10_Msk instead */ +#define PIO_OER_P11_Pos 11 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P11_Msk (_U_(0x1) << PIO_OER_P11_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P11 PIO_OER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P11_Msk instead */ +#define PIO_OER_P12_Pos 12 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P12_Msk (_U_(0x1) << PIO_OER_P12_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P12 PIO_OER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P12_Msk instead */ +#define PIO_OER_P13_Pos 13 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P13_Msk (_U_(0x1) << PIO_OER_P13_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P13 PIO_OER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P13_Msk instead */ +#define PIO_OER_P14_Pos 14 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P14_Msk (_U_(0x1) << PIO_OER_P14_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P14 PIO_OER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P14_Msk instead */ +#define PIO_OER_P15_Pos 15 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P15_Msk (_U_(0x1) << PIO_OER_P15_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P15 PIO_OER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P15_Msk instead */ +#define PIO_OER_P16_Pos 16 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P16_Msk (_U_(0x1) << PIO_OER_P16_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P16 PIO_OER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P16_Msk instead */ +#define PIO_OER_P17_Pos 17 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P17_Msk (_U_(0x1) << PIO_OER_P17_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P17 PIO_OER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P17_Msk instead */ +#define PIO_OER_P18_Pos 18 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P18_Msk (_U_(0x1) << PIO_OER_P18_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P18 PIO_OER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P18_Msk instead */ +#define PIO_OER_P19_Pos 19 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P19_Msk (_U_(0x1) << PIO_OER_P19_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P19 PIO_OER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P19_Msk instead */ +#define PIO_OER_P20_Pos 20 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P20_Msk (_U_(0x1) << PIO_OER_P20_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P20 PIO_OER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P20_Msk instead */ +#define PIO_OER_P21_Pos 21 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P21_Msk (_U_(0x1) << PIO_OER_P21_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P21 PIO_OER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P21_Msk instead */ +#define PIO_OER_P22_Pos 22 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P22_Msk (_U_(0x1) << PIO_OER_P22_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P22 PIO_OER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P22_Msk instead */ +#define PIO_OER_P23_Pos 23 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P23_Msk (_U_(0x1) << PIO_OER_P23_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P23 PIO_OER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P23_Msk instead */ +#define PIO_OER_P24_Pos 24 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P24_Msk (_U_(0x1) << PIO_OER_P24_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P24 PIO_OER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P24_Msk instead */ +#define PIO_OER_P25_Pos 25 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P25_Msk (_U_(0x1) << PIO_OER_P25_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P25 PIO_OER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P25_Msk instead */ +#define PIO_OER_P26_Pos 26 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P26_Msk (_U_(0x1) << PIO_OER_P26_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P26 PIO_OER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P26_Msk instead */ +#define PIO_OER_P27_Pos 27 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P27_Msk (_U_(0x1) << PIO_OER_P27_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P27 PIO_OER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P27_Msk instead */ +#define PIO_OER_P28_Pos 28 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P28_Msk (_U_(0x1) << PIO_OER_P28_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P28 PIO_OER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P28_Msk instead */ +#define PIO_OER_P29_Pos 29 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P29_Msk (_U_(0x1) << PIO_OER_P29_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P29 PIO_OER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P29_Msk instead */ +#define PIO_OER_P30_Pos 30 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P30_Msk (_U_(0x1) << PIO_OER_P30_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P30 PIO_OER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P30_Msk instead */ +#define PIO_OER_P31_Pos 31 /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P31_Msk (_U_(0x1) << PIO_OER_P31_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P31 PIO_OER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OER_P31_Msk instead */ +#define PIO_OER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OER) Register MASK (Use PIO_OER_Msk instead) */ +#define PIO_OER_Msk _U_(0xFFFFFFFF) /**< (PIO_OER) Register Mask */ + +#define PIO_OER_P_Pos 0 /**< (PIO_OER Position) Output Enable */ +#define PIO_OER_P_Msk (_U_(0xFFFFFFFF) << PIO_OER_P_Pos) /**< (PIO_OER Mask) P */ +#define PIO_OER_P(value) (PIO_OER_P_Msk & ((value) << PIO_OER_P_Pos)) + +/* -------- PIO_ODR : (PIO Offset: 0x14) (/W 32) Output Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Disable */ + uint32_t P1:1; /**< bit: 1 Output Disable */ + uint32_t P2:1; /**< bit: 2 Output Disable */ + uint32_t P3:1; /**< bit: 3 Output Disable */ + uint32_t P4:1; /**< bit: 4 Output Disable */ + uint32_t P5:1; /**< bit: 5 Output Disable */ + uint32_t P6:1; /**< bit: 6 Output Disable */ + uint32_t P7:1; /**< bit: 7 Output Disable */ + uint32_t P8:1; /**< bit: 8 Output Disable */ + uint32_t P9:1; /**< bit: 9 Output Disable */ + uint32_t P10:1; /**< bit: 10 Output Disable */ + uint32_t P11:1; /**< bit: 11 Output Disable */ + uint32_t P12:1; /**< bit: 12 Output Disable */ + uint32_t P13:1; /**< bit: 13 Output Disable */ + uint32_t P14:1; /**< bit: 14 Output Disable */ + uint32_t P15:1; /**< bit: 15 Output Disable */ + uint32_t P16:1; /**< bit: 16 Output Disable */ + uint32_t P17:1; /**< bit: 17 Output Disable */ + uint32_t P18:1; /**< bit: 18 Output Disable */ + uint32_t P19:1; /**< bit: 19 Output Disable */ + uint32_t P20:1; /**< bit: 20 Output Disable */ + uint32_t P21:1; /**< bit: 21 Output Disable */ + uint32_t P22:1; /**< bit: 22 Output Disable */ + uint32_t P23:1; /**< bit: 23 Output Disable */ + uint32_t P24:1; /**< bit: 24 Output Disable */ + uint32_t P25:1; /**< bit: 25 Output Disable */ + uint32_t P26:1; /**< bit: 26 Output Disable */ + uint32_t P27:1; /**< bit: 27 Output Disable */ + uint32_t P28:1; /**< bit: 28 Output Disable */ + uint32_t P29:1; /**< bit: 29 Output Disable */ + uint32_t P30:1; /**< bit: 30 Output Disable */ + uint32_t P31:1; /**< bit: 31 Output Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ODR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ODR_OFFSET (0x14) /**< (PIO_ODR) Output Disable Register Offset */ + +#define PIO_ODR_P0_Pos 0 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P0_Msk (_U_(0x1) << PIO_ODR_P0_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P0 PIO_ODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P0_Msk instead */ +#define PIO_ODR_P1_Pos 1 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P1_Msk (_U_(0x1) << PIO_ODR_P1_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P1 PIO_ODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P1_Msk instead */ +#define PIO_ODR_P2_Pos 2 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P2_Msk (_U_(0x1) << PIO_ODR_P2_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P2 PIO_ODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P2_Msk instead */ +#define PIO_ODR_P3_Pos 3 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P3_Msk (_U_(0x1) << PIO_ODR_P3_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P3 PIO_ODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P3_Msk instead */ +#define PIO_ODR_P4_Pos 4 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P4_Msk (_U_(0x1) << PIO_ODR_P4_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P4 PIO_ODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P4_Msk instead */ +#define PIO_ODR_P5_Pos 5 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P5_Msk (_U_(0x1) << PIO_ODR_P5_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P5 PIO_ODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P5_Msk instead */ +#define PIO_ODR_P6_Pos 6 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P6_Msk (_U_(0x1) << PIO_ODR_P6_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P6 PIO_ODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P6_Msk instead */ +#define PIO_ODR_P7_Pos 7 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P7_Msk (_U_(0x1) << PIO_ODR_P7_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P7 PIO_ODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P7_Msk instead */ +#define PIO_ODR_P8_Pos 8 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P8_Msk (_U_(0x1) << PIO_ODR_P8_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P8 PIO_ODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P8_Msk instead */ +#define PIO_ODR_P9_Pos 9 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P9_Msk (_U_(0x1) << PIO_ODR_P9_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P9 PIO_ODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P9_Msk instead */ +#define PIO_ODR_P10_Pos 10 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P10_Msk (_U_(0x1) << PIO_ODR_P10_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P10 PIO_ODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P10_Msk instead */ +#define PIO_ODR_P11_Pos 11 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P11_Msk (_U_(0x1) << PIO_ODR_P11_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P11 PIO_ODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P11_Msk instead */ +#define PIO_ODR_P12_Pos 12 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P12_Msk (_U_(0x1) << PIO_ODR_P12_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P12 PIO_ODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P12_Msk instead */ +#define PIO_ODR_P13_Pos 13 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P13_Msk (_U_(0x1) << PIO_ODR_P13_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P13 PIO_ODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P13_Msk instead */ +#define PIO_ODR_P14_Pos 14 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P14_Msk (_U_(0x1) << PIO_ODR_P14_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P14 PIO_ODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P14_Msk instead */ +#define PIO_ODR_P15_Pos 15 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P15_Msk (_U_(0x1) << PIO_ODR_P15_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P15 PIO_ODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P15_Msk instead */ +#define PIO_ODR_P16_Pos 16 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P16_Msk (_U_(0x1) << PIO_ODR_P16_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P16 PIO_ODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P16_Msk instead */ +#define PIO_ODR_P17_Pos 17 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P17_Msk (_U_(0x1) << PIO_ODR_P17_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P17 PIO_ODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P17_Msk instead */ +#define PIO_ODR_P18_Pos 18 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P18_Msk (_U_(0x1) << PIO_ODR_P18_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P18 PIO_ODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P18_Msk instead */ +#define PIO_ODR_P19_Pos 19 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P19_Msk (_U_(0x1) << PIO_ODR_P19_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P19 PIO_ODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P19_Msk instead */ +#define PIO_ODR_P20_Pos 20 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P20_Msk (_U_(0x1) << PIO_ODR_P20_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P20 PIO_ODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P20_Msk instead */ +#define PIO_ODR_P21_Pos 21 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P21_Msk (_U_(0x1) << PIO_ODR_P21_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P21 PIO_ODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P21_Msk instead */ +#define PIO_ODR_P22_Pos 22 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P22_Msk (_U_(0x1) << PIO_ODR_P22_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P22 PIO_ODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P22_Msk instead */ +#define PIO_ODR_P23_Pos 23 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P23_Msk (_U_(0x1) << PIO_ODR_P23_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P23 PIO_ODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P23_Msk instead */ +#define PIO_ODR_P24_Pos 24 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P24_Msk (_U_(0x1) << PIO_ODR_P24_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P24 PIO_ODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P24_Msk instead */ +#define PIO_ODR_P25_Pos 25 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P25_Msk (_U_(0x1) << PIO_ODR_P25_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P25 PIO_ODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P25_Msk instead */ +#define PIO_ODR_P26_Pos 26 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P26_Msk (_U_(0x1) << PIO_ODR_P26_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P26 PIO_ODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P26_Msk instead */ +#define PIO_ODR_P27_Pos 27 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P27_Msk (_U_(0x1) << PIO_ODR_P27_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P27 PIO_ODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P27_Msk instead */ +#define PIO_ODR_P28_Pos 28 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P28_Msk (_U_(0x1) << PIO_ODR_P28_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P28 PIO_ODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P28_Msk instead */ +#define PIO_ODR_P29_Pos 29 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P29_Msk (_U_(0x1) << PIO_ODR_P29_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P29 PIO_ODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P29_Msk instead */ +#define PIO_ODR_P30_Pos 30 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P30_Msk (_U_(0x1) << PIO_ODR_P30_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P30 PIO_ODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P30_Msk instead */ +#define PIO_ODR_P31_Pos 31 /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P31_Msk (_U_(0x1) << PIO_ODR_P31_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P31 PIO_ODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODR_P31_Msk instead */ +#define PIO_ODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ODR) Register MASK (Use PIO_ODR_Msk instead) */ +#define PIO_ODR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODR) Register Mask */ + +#define PIO_ODR_P_Pos 0 /**< (PIO_ODR Position) Output Disable */ +#define PIO_ODR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODR_P_Pos) /**< (PIO_ODR Mask) P */ +#define PIO_ODR_P(value) (PIO_ODR_P_Msk & ((value) << PIO_ODR_P_Pos)) + +/* -------- PIO_OSR : (PIO Offset: 0x18) (R/ 32) Output Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Status */ + uint32_t P1:1; /**< bit: 1 Output Status */ + uint32_t P2:1; /**< bit: 2 Output Status */ + uint32_t P3:1; /**< bit: 3 Output Status */ + uint32_t P4:1; /**< bit: 4 Output Status */ + uint32_t P5:1; /**< bit: 5 Output Status */ + uint32_t P6:1; /**< bit: 6 Output Status */ + uint32_t P7:1; /**< bit: 7 Output Status */ + uint32_t P8:1; /**< bit: 8 Output Status */ + uint32_t P9:1; /**< bit: 9 Output Status */ + uint32_t P10:1; /**< bit: 10 Output Status */ + uint32_t P11:1; /**< bit: 11 Output Status */ + uint32_t P12:1; /**< bit: 12 Output Status */ + uint32_t P13:1; /**< bit: 13 Output Status */ + uint32_t P14:1; /**< bit: 14 Output Status */ + uint32_t P15:1; /**< bit: 15 Output Status */ + uint32_t P16:1; /**< bit: 16 Output Status */ + uint32_t P17:1; /**< bit: 17 Output Status */ + uint32_t P18:1; /**< bit: 18 Output Status */ + uint32_t P19:1; /**< bit: 19 Output Status */ + uint32_t P20:1; /**< bit: 20 Output Status */ + uint32_t P21:1; /**< bit: 21 Output Status */ + uint32_t P22:1; /**< bit: 22 Output Status */ + uint32_t P23:1; /**< bit: 23 Output Status */ + uint32_t P24:1; /**< bit: 24 Output Status */ + uint32_t P25:1; /**< bit: 25 Output Status */ + uint32_t P26:1; /**< bit: 26 Output Status */ + uint32_t P27:1; /**< bit: 27 Output Status */ + uint32_t P28:1; /**< bit: 28 Output Status */ + uint32_t P29:1; /**< bit: 29 Output Status */ + uint32_t P30:1; /**< bit: 30 Output Status */ + uint32_t P31:1; /**< bit: 31 Output Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_OSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_OSR_OFFSET (0x18) /**< (PIO_OSR) Output Status Register Offset */ + +#define PIO_OSR_P0_Pos 0 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P0_Msk (_U_(0x1) << PIO_OSR_P0_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P0 PIO_OSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P0_Msk instead */ +#define PIO_OSR_P1_Pos 1 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P1_Msk (_U_(0x1) << PIO_OSR_P1_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P1 PIO_OSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P1_Msk instead */ +#define PIO_OSR_P2_Pos 2 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P2_Msk (_U_(0x1) << PIO_OSR_P2_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P2 PIO_OSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P2_Msk instead */ +#define PIO_OSR_P3_Pos 3 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P3_Msk (_U_(0x1) << PIO_OSR_P3_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P3 PIO_OSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P3_Msk instead */ +#define PIO_OSR_P4_Pos 4 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P4_Msk (_U_(0x1) << PIO_OSR_P4_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P4 PIO_OSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P4_Msk instead */ +#define PIO_OSR_P5_Pos 5 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P5_Msk (_U_(0x1) << PIO_OSR_P5_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P5 PIO_OSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P5_Msk instead */ +#define PIO_OSR_P6_Pos 6 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P6_Msk (_U_(0x1) << PIO_OSR_P6_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P6 PIO_OSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P6_Msk instead */ +#define PIO_OSR_P7_Pos 7 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P7_Msk (_U_(0x1) << PIO_OSR_P7_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P7 PIO_OSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P7_Msk instead */ +#define PIO_OSR_P8_Pos 8 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P8_Msk (_U_(0x1) << PIO_OSR_P8_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P8 PIO_OSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P8_Msk instead */ +#define PIO_OSR_P9_Pos 9 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P9_Msk (_U_(0x1) << PIO_OSR_P9_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P9 PIO_OSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P9_Msk instead */ +#define PIO_OSR_P10_Pos 10 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P10_Msk (_U_(0x1) << PIO_OSR_P10_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P10 PIO_OSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P10_Msk instead */ +#define PIO_OSR_P11_Pos 11 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P11_Msk (_U_(0x1) << PIO_OSR_P11_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P11 PIO_OSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P11_Msk instead */ +#define PIO_OSR_P12_Pos 12 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P12_Msk (_U_(0x1) << PIO_OSR_P12_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P12 PIO_OSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P12_Msk instead */ +#define PIO_OSR_P13_Pos 13 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P13_Msk (_U_(0x1) << PIO_OSR_P13_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P13 PIO_OSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P13_Msk instead */ +#define PIO_OSR_P14_Pos 14 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P14_Msk (_U_(0x1) << PIO_OSR_P14_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P14 PIO_OSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P14_Msk instead */ +#define PIO_OSR_P15_Pos 15 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P15_Msk (_U_(0x1) << PIO_OSR_P15_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P15 PIO_OSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P15_Msk instead */ +#define PIO_OSR_P16_Pos 16 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P16_Msk (_U_(0x1) << PIO_OSR_P16_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P16 PIO_OSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P16_Msk instead */ +#define PIO_OSR_P17_Pos 17 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P17_Msk (_U_(0x1) << PIO_OSR_P17_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P17 PIO_OSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P17_Msk instead */ +#define PIO_OSR_P18_Pos 18 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P18_Msk (_U_(0x1) << PIO_OSR_P18_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P18 PIO_OSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P18_Msk instead */ +#define PIO_OSR_P19_Pos 19 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P19_Msk (_U_(0x1) << PIO_OSR_P19_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P19 PIO_OSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P19_Msk instead */ +#define PIO_OSR_P20_Pos 20 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P20_Msk (_U_(0x1) << PIO_OSR_P20_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P20 PIO_OSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P20_Msk instead */ +#define PIO_OSR_P21_Pos 21 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P21_Msk (_U_(0x1) << PIO_OSR_P21_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P21 PIO_OSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P21_Msk instead */ +#define PIO_OSR_P22_Pos 22 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P22_Msk (_U_(0x1) << PIO_OSR_P22_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P22 PIO_OSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P22_Msk instead */ +#define PIO_OSR_P23_Pos 23 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P23_Msk (_U_(0x1) << PIO_OSR_P23_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P23 PIO_OSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P23_Msk instead */ +#define PIO_OSR_P24_Pos 24 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P24_Msk (_U_(0x1) << PIO_OSR_P24_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P24 PIO_OSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P24_Msk instead */ +#define PIO_OSR_P25_Pos 25 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P25_Msk (_U_(0x1) << PIO_OSR_P25_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P25 PIO_OSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P25_Msk instead */ +#define PIO_OSR_P26_Pos 26 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P26_Msk (_U_(0x1) << PIO_OSR_P26_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P26 PIO_OSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P26_Msk instead */ +#define PIO_OSR_P27_Pos 27 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P27_Msk (_U_(0x1) << PIO_OSR_P27_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P27 PIO_OSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P27_Msk instead */ +#define PIO_OSR_P28_Pos 28 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P28_Msk (_U_(0x1) << PIO_OSR_P28_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P28 PIO_OSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P28_Msk instead */ +#define PIO_OSR_P29_Pos 29 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P29_Msk (_U_(0x1) << PIO_OSR_P29_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P29 PIO_OSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P29_Msk instead */ +#define PIO_OSR_P30_Pos 30 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P30_Msk (_U_(0x1) << PIO_OSR_P30_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P30 PIO_OSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P30_Msk instead */ +#define PIO_OSR_P31_Pos 31 /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P31_Msk (_U_(0x1) << PIO_OSR_P31_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P31 PIO_OSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OSR_P31_Msk instead */ +#define PIO_OSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OSR) Register MASK (Use PIO_OSR_Msk instead) */ +#define PIO_OSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OSR) Register Mask */ + +#define PIO_OSR_P_Pos 0 /**< (PIO_OSR Position) Output Status */ +#define PIO_OSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OSR_P_Pos) /**< (PIO_OSR Mask) P */ +#define PIO_OSR_P(value) (PIO_OSR_P_Msk & ((value) << PIO_OSR_P_Pos)) + +/* -------- PIO_IFER : (PIO Offset: 0x20) (/W 32) Glitch Input Filter Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Filter Enable */ + uint32_t P1:1; /**< bit: 1 Input Filter Enable */ + uint32_t P2:1; /**< bit: 2 Input Filter Enable */ + uint32_t P3:1; /**< bit: 3 Input Filter Enable */ + uint32_t P4:1; /**< bit: 4 Input Filter Enable */ + uint32_t P5:1; /**< bit: 5 Input Filter Enable */ + uint32_t P6:1; /**< bit: 6 Input Filter Enable */ + uint32_t P7:1; /**< bit: 7 Input Filter Enable */ + uint32_t P8:1; /**< bit: 8 Input Filter Enable */ + uint32_t P9:1; /**< bit: 9 Input Filter Enable */ + uint32_t P10:1; /**< bit: 10 Input Filter Enable */ + uint32_t P11:1; /**< bit: 11 Input Filter Enable */ + uint32_t P12:1; /**< bit: 12 Input Filter Enable */ + uint32_t P13:1; /**< bit: 13 Input Filter Enable */ + uint32_t P14:1; /**< bit: 14 Input Filter Enable */ + uint32_t P15:1; /**< bit: 15 Input Filter Enable */ + uint32_t P16:1; /**< bit: 16 Input Filter Enable */ + uint32_t P17:1; /**< bit: 17 Input Filter Enable */ + uint32_t P18:1; /**< bit: 18 Input Filter Enable */ + uint32_t P19:1; /**< bit: 19 Input Filter Enable */ + uint32_t P20:1; /**< bit: 20 Input Filter Enable */ + uint32_t P21:1; /**< bit: 21 Input Filter Enable */ + uint32_t P22:1; /**< bit: 22 Input Filter Enable */ + uint32_t P23:1; /**< bit: 23 Input Filter Enable */ + uint32_t P24:1; /**< bit: 24 Input Filter Enable */ + uint32_t P25:1; /**< bit: 25 Input Filter Enable */ + uint32_t P26:1; /**< bit: 26 Input Filter Enable */ + uint32_t P27:1; /**< bit: 27 Input Filter Enable */ + uint32_t P28:1; /**< bit: 28 Input Filter Enable */ + uint32_t P29:1; /**< bit: 29 Input Filter Enable */ + uint32_t P30:1; /**< bit: 30 Input Filter Enable */ + uint32_t P31:1; /**< bit: 31 Input Filter Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Filter Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFER_OFFSET (0x20) /**< (PIO_IFER) Glitch Input Filter Enable Register Offset */ + +#define PIO_IFER_P0_Pos 0 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P0_Msk (_U_(0x1) << PIO_IFER_P0_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P0 PIO_IFER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P0_Msk instead */ +#define PIO_IFER_P1_Pos 1 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P1_Msk (_U_(0x1) << PIO_IFER_P1_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P1 PIO_IFER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P1_Msk instead */ +#define PIO_IFER_P2_Pos 2 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P2_Msk (_U_(0x1) << PIO_IFER_P2_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P2 PIO_IFER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P2_Msk instead */ +#define PIO_IFER_P3_Pos 3 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P3_Msk (_U_(0x1) << PIO_IFER_P3_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P3 PIO_IFER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P3_Msk instead */ +#define PIO_IFER_P4_Pos 4 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P4_Msk (_U_(0x1) << PIO_IFER_P4_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P4 PIO_IFER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P4_Msk instead */ +#define PIO_IFER_P5_Pos 5 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P5_Msk (_U_(0x1) << PIO_IFER_P5_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P5 PIO_IFER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P5_Msk instead */ +#define PIO_IFER_P6_Pos 6 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P6_Msk (_U_(0x1) << PIO_IFER_P6_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P6 PIO_IFER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P6_Msk instead */ +#define PIO_IFER_P7_Pos 7 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P7_Msk (_U_(0x1) << PIO_IFER_P7_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P7 PIO_IFER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P7_Msk instead */ +#define PIO_IFER_P8_Pos 8 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P8_Msk (_U_(0x1) << PIO_IFER_P8_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P8 PIO_IFER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P8_Msk instead */ +#define PIO_IFER_P9_Pos 9 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P9_Msk (_U_(0x1) << PIO_IFER_P9_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P9 PIO_IFER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P9_Msk instead */ +#define PIO_IFER_P10_Pos 10 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P10_Msk (_U_(0x1) << PIO_IFER_P10_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P10 PIO_IFER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P10_Msk instead */ +#define PIO_IFER_P11_Pos 11 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P11_Msk (_U_(0x1) << PIO_IFER_P11_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P11 PIO_IFER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P11_Msk instead */ +#define PIO_IFER_P12_Pos 12 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P12_Msk (_U_(0x1) << PIO_IFER_P12_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P12 PIO_IFER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P12_Msk instead */ +#define PIO_IFER_P13_Pos 13 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P13_Msk (_U_(0x1) << PIO_IFER_P13_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P13 PIO_IFER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P13_Msk instead */ +#define PIO_IFER_P14_Pos 14 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P14_Msk (_U_(0x1) << PIO_IFER_P14_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P14 PIO_IFER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P14_Msk instead */ +#define PIO_IFER_P15_Pos 15 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P15_Msk (_U_(0x1) << PIO_IFER_P15_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P15 PIO_IFER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P15_Msk instead */ +#define PIO_IFER_P16_Pos 16 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P16_Msk (_U_(0x1) << PIO_IFER_P16_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P16 PIO_IFER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P16_Msk instead */ +#define PIO_IFER_P17_Pos 17 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P17_Msk (_U_(0x1) << PIO_IFER_P17_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P17 PIO_IFER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P17_Msk instead */ +#define PIO_IFER_P18_Pos 18 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P18_Msk (_U_(0x1) << PIO_IFER_P18_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P18 PIO_IFER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P18_Msk instead */ +#define PIO_IFER_P19_Pos 19 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P19_Msk (_U_(0x1) << PIO_IFER_P19_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P19 PIO_IFER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P19_Msk instead */ +#define PIO_IFER_P20_Pos 20 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P20_Msk (_U_(0x1) << PIO_IFER_P20_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P20 PIO_IFER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P20_Msk instead */ +#define PIO_IFER_P21_Pos 21 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P21_Msk (_U_(0x1) << PIO_IFER_P21_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P21 PIO_IFER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P21_Msk instead */ +#define PIO_IFER_P22_Pos 22 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P22_Msk (_U_(0x1) << PIO_IFER_P22_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P22 PIO_IFER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P22_Msk instead */ +#define PIO_IFER_P23_Pos 23 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P23_Msk (_U_(0x1) << PIO_IFER_P23_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P23 PIO_IFER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P23_Msk instead */ +#define PIO_IFER_P24_Pos 24 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P24_Msk (_U_(0x1) << PIO_IFER_P24_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P24 PIO_IFER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P24_Msk instead */ +#define PIO_IFER_P25_Pos 25 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P25_Msk (_U_(0x1) << PIO_IFER_P25_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P25 PIO_IFER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P25_Msk instead */ +#define PIO_IFER_P26_Pos 26 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P26_Msk (_U_(0x1) << PIO_IFER_P26_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P26 PIO_IFER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P26_Msk instead */ +#define PIO_IFER_P27_Pos 27 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P27_Msk (_U_(0x1) << PIO_IFER_P27_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P27 PIO_IFER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P27_Msk instead */ +#define PIO_IFER_P28_Pos 28 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P28_Msk (_U_(0x1) << PIO_IFER_P28_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P28 PIO_IFER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P28_Msk instead */ +#define PIO_IFER_P29_Pos 29 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P29_Msk (_U_(0x1) << PIO_IFER_P29_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P29 PIO_IFER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P29_Msk instead */ +#define PIO_IFER_P30_Pos 30 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P30_Msk (_U_(0x1) << PIO_IFER_P30_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P30 PIO_IFER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P30_Msk instead */ +#define PIO_IFER_P31_Pos 31 /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P31_Msk (_U_(0x1) << PIO_IFER_P31_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P31 PIO_IFER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFER_P31_Msk instead */ +#define PIO_IFER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFER) Register MASK (Use PIO_IFER_Msk instead) */ +#define PIO_IFER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFER) Register Mask */ + +#define PIO_IFER_P_Pos 0 /**< (PIO_IFER Position) Input Filter Enable */ +#define PIO_IFER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFER_P_Pos) /**< (PIO_IFER Mask) P */ +#define PIO_IFER_P(value) (PIO_IFER_P_Msk & ((value) << PIO_IFER_P_Pos)) + +/* -------- PIO_IFDR : (PIO Offset: 0x24) (/W 32) Glitch Input Filter Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Filter Disable */ + uint32_t P1:1; /**< bit: 1 Input Filter Disable */ + uint32_t P2:1; /**< bit: 2 Input Filter Disable */ + uint32_t P3:1; /**< bit: 3 Input Filter Disable */ + uint32_t P4:1; /**< bit: 4 Input Filter Disable */ + uint32_t P5:1; /**< bit: 5 Input Filter Disable */ + uint32_t P6:1; /**< bit: 6 Input Filter Disable */ + uint32_t P7:1; /**< bit: 7 Input Filter Disable */ + uint32_t P8:1; /**< bit: 8 Input Filter Disable */ + uint32_t P9:1; /**< bit: 9 Input Filter Disable */ + uint32_t P10:1; /**< bit: 10 Input Filter Disable */ + uint32_t P11:1; /**< bit: 11 Input Filter Disable */ + uint32_t P12:1; /**< bit: 12 Input Filter Disable */ + uint32_t P13:1; /**< bit: 13 Input Filter Disable */ + uint32_t P14:1; /**< bit: 14 Input Filter Disable */ + uint32_t P15:1; /**< bit: 15 Input Filter Disable */ + uint32_t P16:1; /**< bit: 16 Input Filter Disable */ + uint32_t P17:1; /**< bit: 17 Input Filter Disable */ + uint32_t P18:1; /**< bit: 18 Input Filter Disable */ + uint32_t P19:1; /**< bit: 19 Input Filter Disable */ + uint32_t P20:1; /**< bit: 20 Input Filter Disable */ + uint32_t P21:1; /**< bit: 21 Input Filter Disable */ + uint32_t P22:1; /**< bit: 22 Input Filter Disable */ + uint32_t P23:1; /**< bit: 23 Input Filter Disable */ + uint32_t P24:1; /**< bit: 24 Input Filter Disable */ + uint32_t P25:1; /**< bit: 25 Input Filter Disable */ + uint32_t P26:1; /**< bit: 26 Input Filter Disable */ + uint32_t P27:1; /**< bit: 27 Input Filter Disable */ + uint32_t P28:1; /**< bit: 28 Input Filter Disable */ + uint32_t P29:1; /**< bit: 29 Input Filter Disable */ + uint32_t P30:1; /**< bit: 30 Input Filter Disable */ + uint32_t P31:1; /**< bit: 31 Input Filter Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Filter Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFDR_OFFSET (0x24) /**< (PIO_IFDR) Glitch Input Filter Disable Register Offset */ + +#define PIO_IFDR_P0_Pos 0 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P0_Msk (_U_(0x1) << PIO_IFDR_P0_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P0 PIO_IFDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P0_Msk instead */ +#define PIO_IFDR_P1_Pos 1 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P1_Msk (_U_(0x1) << PIO_IFDR_P1_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P1 PIO_IFDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P1_Msk instead */ +#define PIO_IFDR_P2_Pos 2 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P2_Msk (_U_(0x1) << PIO_IFDR_P2_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P2 PIO_IFDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P2_Msk instead */ +#define PIO_IFDR_P3_Pos 3 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P3_Msk (_U_(0x1) << PIO_IFDR_P3_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P3 PIO_IFDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P3_Msk instead */ +#define PIO_IFDR_P4_Pos 4 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P4_Msk (_U_(0x1) << PIO_IFDR_P4_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P4 PIO_IFDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P4_Msk instead */ +#define PIO_IFDR_P5_Pos 5 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P5_Msk (_U_(0x1) << PIO_IFDR_P5_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P5 PIO_IFDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P5_Msk instead */ +#define PIO_IFDR_P6_Pos 6 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P6_Msk (_U_(0x1) << PIO_IFDR_P6_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P6 PIO_IFDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P6_Msk instead */ +#define PIO_IFDR_P7_Pos 7 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P7_Msk (_U_(0x1) << PIO_IFDR_P7_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P7 PIO_IFDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P7_Msk instead */ +#define PIO_IFDR_P8_Pos 8 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P8_Msk (_U_(0x1) << PIO_IFDR_P8_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P8 PIO_IFDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P8_Msk instead */ +#define PIO_IFDR_P9_Pos 9 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P9_Msk (_U_(0x1) << PIO_IFDR_P9_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P9 PIO_IFDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P9_Msk instead */ +#define PIO_IFDR_P10_Pos 10 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P10_Msk (_U_(0x1) << PIO_IFDR_P10_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P10 PIO_IFDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P10_Msk instead */ +#define PIO_IFDR_P11_Pos 11 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P11_Msk (_U_(0x1) << PIO_IFDR_P11_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P11 PIO_IFDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P11_Msk instead */ +#define PIO_IFDR_P12_Pos 12 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P12_Msk (_U_(0x1) << PIO_IFDR_P12_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P12 PIO_IFDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P12_Msk instead */ +#define PIO_IFDR_P13_Pos 13 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P13_Msk (_U_(0x1) << PIO_IFDR_P13_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P13 PIO_IFDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P13_Msk instead */ +#define PIO_IFDR_P14_Pos 14 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P14_Msk (_U_(0x1) << PIO_IFDR_P14_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P14 PIO_IFDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P14_Msk instead */ +#define PIO_IFDR_P15_Pos 15 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P15_Msk (_U_(0x1) << PIO_IFDR_P15_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P15 PIO_IFDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P15_Msk instead */ +#define PIO_IFDR_P16_Pos 16 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P16_Msk (_U_(0x1) << PIO_IFDR_P16_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P16 PIO_IFDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P16_Msk instead */ +#define PIO_IFDR_P17_Pos 17 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P17_Msk (_U_(0x1) << PIO_IFDR_P17_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P17 PIO_IFDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P17_Msk instead */ +#define PIO_IFDR_P18_Pos 18 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P18_Msk (_U_(0x1) << PIO_IFDR_P18_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P18 PIO_IFDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P18_Msk instead */ +#define PIO_IFDR_P19_Pos 19 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P19_Msk (_U_(0x1) << PIO_IFDR_P19_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P19 PIO_IFDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P19_Msk instead */ +#define PIO_IFDR_P20_Pos 20 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P20_Msk (_U_(0x1) << PIO_IFDR_P20_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P20 PIO_IFDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P20_Msk instead */ +#define PIO_IFDR_P21_Pos 21 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P21_Msk (_U_(0x1) << PIO_IFDR_P21_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P21 PIO_IFDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P21_Msk instead */ +#define PIO_IFDR_P22_Pos 22 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P22_Msk (_U_(0x1) << PIO_IFDR_P22_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P22 PIO_IFDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P22_Msk instead */ +#define PIO_IFDR_P23_Pos 23 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P23_Msk (_U_(0x1) << PIO_IFDR_P23_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P23 PIO_IFDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P23_Msk instead */ +#define PIO_IFDR_P24_Pos 24 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P24_Msk (_U_(0x1) << PIO_IFDR_P24_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P24 PIO_IFDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P24_Msk instead */ +#define PIO_IFDR_P25_Pos 25 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P25_Msk (_U_(0x1) << PIO_IFDR_P25_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P25 PIO_IFDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P25_Msk instead */ +#define PIO_IFDR_P26_Pos 26 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P26_Msk (_U_(0x1) << PIO_IFDR_P26_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P26 PIO_IFDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P26_Msk instead */ +#define PIO_IFDR_P27_Pos 27 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P27_Msk (_U_(0x1) << PIO_IFDR_P27_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P27 PIO_IFDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P27_Msk instead */ +#define PIO_IFDR_P28_Pos 28 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P28_Msk (_U_(0x1) << PIO_IFDR_P28_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P28 PIO_IFDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P28_Msk instead */ +#define PIO_IFDR_P29_Pos 29 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P29_Msk (_U_(0x1) << PIO_IFDR_P29_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P29 PIO_IFDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P29_Msk instead */ +#define PIO_IFDR_P30_Pos 30 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P30_Msk (_U_(0x1) << PIO_IFDR_P30_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P30 PIO_IFDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P30_Msk instead */ +#define PIO_IFDR_P31_Pos 31 /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P31_Msk (_U_(0x1) << PIO_IFDR_P31_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P31 PIO_IFDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFDR_P31_Msk instead */ +#define PIO_IFDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFDR) Register MASK (Use PIO_IFDR_Msk instead) */ +#define PIO_IFDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFDR) Register Mask */ + +#define PIO_IFDR_P_Pos 0 /**< (PIO_IFDR Position) Input Filter Disable */ +#define PIO_IFDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFDR_P_Pos) /**< (PIO_IFDR Mask) P */ +#define PIO_IFDR_P(value) (PIO_IFDR_P_Msk & ((value) << PIO_IFDR_P_Pos)) + +/* -------- PIO_IFSR : (PIO Offset: 0x28) (R/ 32) Glitch Input Filter Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Filter Status */ + uint32_t P1:1; /**< bit: 1 Input Filter Status */ + uint32_t P2:1; /**< bit: 2 Input Filter Status */ + uint32_t P3:1; /**< bit: 3 Input Filter Status */ + uint32_t P4:1; /**< bit: 4 Input Filter Status */ + uint32_t P5:1; /**< bit: 5 Input Filter Status */ + uint32_t P6:1; /**< bit: 6 Input Filter Status */ + uint32_t P7:1; /**< bit: 7 Input Filter Status */ + uint32_t P8:1; /**< bit: 8 Input Filter Status */ + uint32_t P9:1; /**< bit: 9 Input Filter Status */ + uint32_t P10:1; /**< bit: 10 Input Filter Status */ + uint32_t P11:1; /**< bit: 11 Input Filter Status */ + uint32_t P12:1; /**< bit: 12 Input Filter Status */ + uint32_t P13:1; /**< bit: 13 Input Filter Status */ + uint32_t P14:1; /**< bit: 14 Input Filter Status */ + uint32_t P15:1; /**< bit: 15 Input Filter Status */ + uint32_t P16:1; /**< bit: 16 Input Filter Status */ + uint32_t P17:1; /**< bit: 17 Input Filter Status */ + uint32_t P18:1; /**< bit: 18 Input Filter Status */ + uint32_t P19:1; /**< bit: 19 Input Filter Status */ + uint32_t P20:1; /**< bit: 20 Input Filter Status */ + uint32_t P21:1; /**< bit: 21 Input Filter Status */ + uint32_t P22:1; /**< bit: 22 Input Filter Status */ + uint32_t P23:1; /**< bit: 23 Input Filter Status */ + uint32_t P24:1; /**< bit: 24 Input Filter Status */ + uint32_t P25:1; /**< bit: 25 Input Filter Status */ + uint32_t P26:1; /**< bit: 26 Input Filter Status */ + uint32_t P27:1; /**< bit: 27 Input Filter Status */ + uint32_t P28:1; /**< bit: 28 Input Filter Status */ + uint32_t P29:1; /**< bit: 29 Input Filter Status */ + uint32_t P30:1; /**< bit: 30 Input Filter Status */ + uint32_t P31:1; /**< bit: 31 Input Filter Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Filter Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFSR_OFFSET (0x28) /**< (PIO_IFSR) Glitch Input Filter Status Register Offset */ + +#define PIO_IFSR_P0_Pos 0 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P0_Msk (_U_(0x1) << PIO_IFSR_P0_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P0 PIO_IFSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P0_Msk instead */ +#define PIO_IFSR_P1_Pos 1 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P1_Msk (_U_(0x1) << PIO_IFSR_P1_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P1 PIO_IFSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P1_Msk instead */ +#define PIO_IFSR_P2_Pos 2 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P2_Msk (_U_(0x1) << PIO_IFSR_P2_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P2 PIO_IFSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P2_Msk instead */ +#define PIO_IFSR_P3_Pos 3 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P3_Msk (_U_(0x1) << PIO_IFSR_P3_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P3 PIO_IFSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P3_Msk instead */ +#define PIO_IFSR_P4_Pos 4 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P4_Msk (_U_(0x1) << PIO_IFSR_P4_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P4 PIO_IFSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P4_Msk instead */ +#define PIO_IFSR_P5_Pos 5 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P5_Msk (_U_(0x1) << PIO_IFSR_P5_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P5 PIO_IFSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P5_Msk instead */ +#define PIO_IFSR_P6_Pos 6 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P6_Msk (_U_(0x1) << PIO_IFSR_P6_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P6 PIO_IFSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P6_Msk instead */ +#define PIO_IFSR_P7_Pos 7 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P7_Msk (_U_(0x1) << PIO_IFSR_P7_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P7 PIO_IFSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P7_Msk instead */ +#define PIO_IFSR_P8_Pos 8 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P8_Msk (_U_(0x1) << PIO_IFSR_P8_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P8 PIO_IFSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P8_Msk instead */ +#define PIO_IFSR_P9_Pos 9 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P9_Msk (_U_(0x1) << PIO_IFSR_P9_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P9 PIO_IFSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P9_Msk instead */ +#define PIO_IFSR_P10_Pos 10 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P10_Msk (_U_(0x1) << PIO_IFSR_P10_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P10 PIO_IFSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P10_Msk instead */ +#define PIO_IFSR_P11_Pos 11 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P11_Msk (_U_(0x1) << PIO_IFSR_P11_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P11 PIO_IFSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P11_Msk instead */ +#define PIO_IFSR_P12_Pos 12 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P12_Msk (_U_(0x1) << PIO_IFSR_P12_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P12 PIO_IFSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P12_Msk instead */ +#define PIO_IFSR_P13_Pos 13 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P13_Msk (_U_(0x1) << PIO_IFSR_P13_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P13 PIO_IFSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P13_Msk instead */ +#define PIO_IFSR_P14_Pos 14 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P14_Msk (_U_(0x1) << PIO_IFSR_P14_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P14 PIO_IFSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P14_Msk instead */ +#define PIO_IFSR_P15_Pos 15 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P15_Msk (_U_(0x1) << PIO_IFSR_P15_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P15 PIO_IFSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P15_Msk instead */ +#define PIO_IFSR_P16_Pos 16 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P16_Msk (_U_(0x1) << PIO_IFSR_P16_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P16 PIO_IFSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P16_Msk instead */ +#define PIO_IFSR_P17_Pos 17 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P17_Msk (_U_(0x1) << PIO_IFSR_P17_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P17 PIO_IFSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P17_Msk instead */ +#define PIO_IFSR_P18_Pos 18 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P18_Msk (_U_(0x1) << PIO_IFSR_P18_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P18 PIO_IFSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P18_Msk instead */ +#define PIO_IFSR_P19_Pos 19 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P19_Msk (_U_(0x1) << PIO_IFSR_P19_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P19 PIO_IFSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P19_Msk instead */ +#define PIO_IFSR_P20_Pos 20 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P20_Msk (_U_(0x1) << PIO_IFSR_P20_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P20 PIO_IFSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P20_Msk instead */ +#define PIO_IFSR_P21_Pos 21 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P21_Msk (_U_(0x1) << PIO_IFSR_P21_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P21 PIO_IFSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P21_Msk instead */ +#define PIO_IFSR_P22_Pos 22 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P22_Msk (_U_(0x1) << PIO_IFSR_P22_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P22 PIO_IFSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P22_Msk instead */ +#define PIO_IFSR_P23_Pos 23 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P23_Msk (_U_(0x1) << PIO_IFSR_P23_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P23 PIO_IFSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P23_Msk instead */ +#define PIO_IFSR_P24_Pos 24 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P24_Msk (_U_(0x1) << PIO_IFSR_P24_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P24 PIO_IFSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P24_Msk instead */ +#define PIO_IFSR_P25_Pos 25 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P25_Msk (_U_(0x1) << PIO_IFSR_P25_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P25 PIO_IFSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P25_Msk instead */ +#define PIO_IFSR_P26_Pos 26 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P26_Msk (_U_(0x1) << PIO_IFSR_P26_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P26 PIO_IFSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P26_Msk instead */ +#define PIO_IFSR_P27_Pos 27 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P27_Msk (_U_(0x1) << PIO_IFSR_P27_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P27 PIO_IFSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P27_Msk instead */ +#define PIO_IFSR_P28_Pos 28 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P28_Msk (_U_(0x1) << PIO_IFSR_P28_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P28 PIO_IFSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P28_Msk instead */ +#define PIO_IFSR_P29_Pos 29 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P29_Msk (_U_(0x1) << PIO_IFSR_P29_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P29 PIO_IFSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P29_Msk instead */ +#define PIO_IFSR_P30_Pos 30 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P30_Msk (_U_(0x1) << PIO_IFSR_P30_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P30 PIO_IFSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P30_Msk instead */ +#define PIO_IFSR_P31_Pos 31 /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P31_Msk (_U_(0x1) << PIO_IFSR_P31_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P31 PIO_IFSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSR_P31_Msk instead */ +#define PIO_IFSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSR) Register MASK (Use PIO_IFSR_Msk instead) */ +#define PIO_IFSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSR) Register Mask */ + +#define PIO_IFSR_P_Pos 0 /**< (PIO_IFSR Position) Input Filter Status */ +#define PIO_IFSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSR_P_Pos) /**< (PIO_IFSR Mask) P */ +#define PIO_IFSR_P(value) (PIO_IFSR_P_Msk & ((value) << PIO_IFSR_P_Pos)) + +/* -------- PIO_SODR : (PIO Offset: 0x30) (/W 32) Set Output Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Set Output Data */ + uint32_t P1:1; /**< bit: 1 Set Output Data */ + uint32_t P2:1; /**< bit: 2 Set Output Data */ + uint32_t P3:1; /**< bit: 3 Set Output Data */ + uint32_t P4:1; /**< bit: 4 Set Output Data */ + uint32_t P5:1; /**< bit: 5 Set Output Data */ + uint32_t P6:1; /**< bit: 6 Set Output Data */ + uint32_t P7:1; /**< bit: 7 Set Output Data */ + uint32_t P8:1; /**< bit: 8 Set Output Data */ + uint32_t P9:1; /**< bit: 9 Set Output Data */ + uint32_t P10:1; /**< bit: 10 Set Output Data */ + uint32_t P11:1; /**< bit: 11 Set Output Data */ + uint32_t P12:1; /**< bit: 12 Set Output Data */ + uint32_t P13:1; /**< bit: 13 Set Output Data */ + uint32_t P14:1; /**< bit: 14 Set Output Data */ + uint32_t P15:1; /**< bit: 15 Set Output Data */ + uint32_t P16:1; /**< bit: 16 Set Output Data */ + uint32_t P17:1; /**< bit: 17 Set Output Data */ + uint32_t P18:1; /**< bit: 18 Set Output Data */ + uint32_t P19:1; /**< bit: 19 Set Output Data */ + uint32_t P20:1; /**< bit: 20 Set Output Data */ + uint32_t P21:1; /**< bit: 21 Set Output Data */ + uint32_t P22:1; /**< bit: 22 Set Output Data */ + uint32_t P23:1; /**< bit: 23 Set Output Data */ + uint32_t P24:1; /**< bit: 24 Set Output Data */ + uint32_t P25:1; /**< bit: 25 Set Output Data */ + uint32_t P26:1; /**< bit: 26 Set Output Data */ + uint32_t P27:1; /**< bit: 27 Set Output Data */ + uint32_t P28:1; /**< bit: 28 Set Output Data */ + uint32_t P29:1; /**< bit: 29 Set Output Data */ + uint32_t P30:1; /**< bit: 30 Set Output Data */ + uint32_t P31:1; /**< bit: 31 Set Output Data */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Set Output Data */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_SODR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_SODR_OFFSET (0x30) /**< (PIO_SODR) Set Output Data Register Offset */ + +#define PIO_SODR_P0_Pos 0 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P0_Msk (_U_(0x1) << PIO_SODR_P0_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P0 PIO_SODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P0_Msk instead */ +#define PIO_SODR_P1_Pos 1 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P1_Msk (_U_(0x1) << PIO_SODR_P1_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P1 PIO_SODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P1_Msk instead */ +#define PIO_SODR_P2_Pos 2 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P2_Msk (_U_(0x1) << PIO_SODR_P2_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P2 PIO_SODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P2_Msk instead */ +#define PIO_SODR_P3_Pos 3 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P3_Msk (_U_(0x1) << PIO_SODR_P3_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P3 PIO_SODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P3_Msk instead */ +#define PIO_SODR_P4_Pos 4 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P4_Msk (_U_(0x1) << PIO_SODR_P4_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P4 PIO_SODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P4_Msk instead */ +#define PIO_SODR_P5_Pos 5 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P5_Msk (_U_(0x1) << PIO_SODR_P5_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P5 PIO_SODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P5_Msk instead */ +#define PIO_SODR_P6_Pos 6 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P6_Msk (_U_(0x1) << PIO_SODR_P6_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P6 PIO_SODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P6_Msk instead */ +#define PIO_SODR_P7_Pos 7 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P7_Msk (_U_(0x1) << PIO_SODR_P7_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P7 PIO_SODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P7_Msk instead */ +#define PIO_SODR_P8_Pos 8 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P8_Msk (_U_(0x1) << PIO_SODR_P8_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P8 PIO_SODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P8_Msk instead */ +#define PIO_SODR_P9_Pos 9 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P9_Msk (_U_(0x1) << PIO_SODR_P9_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P9 PIO_SODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P9_Msk instead */ +#define PIO_SODR_P10_Pos 10 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P10_Msk (_U_(0x1) << PIO_SODR_P10_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P10 PIO_SODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P10_Msk instead */ +#define PIO_SODR_P11_Pos 11 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P11_Msk (_U_(0x1) << PIO_SODR_P11_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P11 PIO_SODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P11_Msk instead */ +#define PIO_SODR_P12_Pos 12 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P12_Msk (_U_(0x1) << PIO_SODR_P12_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P12 PIO_SODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P12_Msk instead */ +#define PIO_SODR_P13_Pos 13 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P13_Msk (_U_(0x1) << PIO_SODR_P13_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P13 PIO_SODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P13_Msk instead */ +#define PIO_SODR_P14_Pos 14 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P14_Msk (_U_(0x1) << PIO_SODR_P14_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P14 PIO_SODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P14_Msk instead */ +#define PIO_SODR_P15_Pos 15 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P15_Msk (_U_(0x1) << PIO_SODR_P15_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P15 PIO_SODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P15_Msk instead */ +#define PIO_SODR_P16_Pos 16 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P16_Msk (_U_(0x1) << PIO_SODR_P16_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P16 PIO_SODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P16_Msk instead */ +#define PIO_SODR_P17_Pos 17 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P17_Msk (_U_(0x1) << PIO_SODR_P17_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P17 PIO_SODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P17_Msk instead */ +#define PIO_SODR_P18_Pos 18 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P18_Msk (_U_(0x1) << PIO_SODR_P18_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P18 PIO_SODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P18_Msk instead */ +#define PIO_SODR_P19_Pos 19 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P19_Msk (_U_(0x1) << PIO_SODR_P19_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P19 PIO_SODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P19_Msk instead */ +#define PIO_SODR_P20_Pos 20 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P20_Msk (_U_(0x1) << PIO_SODR_P20_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P20 PIO_SODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P20_Msk instead */ +#define PIO_SODR_P21_Pos 21 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P21_Msk (_U_(0x1) << PIO_SODR_P21_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P21 PIO_SODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P21_Msk instead */ +#define PIO_SODR_P22_Pos 22 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P22_Msk (_U_(0x1) << PIO_SODR_P22_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P22 PIO_SODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P22_Msk instead */ +#define PIO_SODR_P23_Pos 23 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P23_Msk (_U_(0x1) << PIO_SODR_P23_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P23 PIO_SODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P23_Msk instead */ +#define PIO_SODR_P24_Pos 24 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P24_Msk (_U_(0x1) << PIO_SODR_P24_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P24 PIO_SODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P24_Msk instead */ +#define PIO_SODR_P25_Pos 25 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P25_Msk (_U_(0x1) << PIO_SODR_P25_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P25 PIO_SODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P25_Msk instead */ +#define PIO_SODR_P26_Pos 26 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P26_Msk (_U_(0x1) << PIO_SODR_P26_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P26 PIO_SODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P26_Msk instead */ +#define PIO_SODR_P27_Pos 27 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P27_Msk (_U_(0x1) << PIO_SODR_P27_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P27 PIO_SODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P27_Msk instead */ +#define PIO_SODR_P28_Pos 28 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P28_Msk (_U_(0x1) << PIO_SODR_P28_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P28 PIO_SODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P28_Msk instead */ +#define PIO_SODR_P29_Pos 29 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P29_Msk (_U_(0x1) << PIO_SODR_P29_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P29 PIO_SODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P29_Msk instead */ +#define PIO_SODR_P30_Pos 30 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P30_Msk (_U_(0x1) << PIO_SODR_P30_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P30 PIO_SODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P30_Msk instead */ +#define PIO_SODR_P31_Pos 31 /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P31_Msk (_U_(0x1) << PIO_SODR_P31_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P31 PIO_SODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SODR_P31_Msk instead */ +#define PIO_SODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_SODR) Register MASK (Use PIO_SODR_Msk instead) */ +#define PIO_SODR_Msk _U_(0xFFFFFFFF) /**< (PIO_SODR) Register Mask */ + +#define PIO_SODR_P_Pos 0 /**< (PIO_SODR Position) Set Output Data */ +#define PIO_SODR_P_Msk (_U_(0xFFFFFFFF) << PIO_SODR_P_Pos) /**< (PIO_SODR Mask) P */ +#define PIO_SODR_P(value) (PIO_SODR_P_Msk & ((value) << PIO_SODR_P_Pos)) + +/* -------- PIO_CODR : (PIO Offset: 0x34) (/W 32) Clear Output Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Clear Output Data */ + uint32_t P1:1; /**< bit: 1 Clear Output Data */ + uint32_t P2:1; /**< bit: 2 Clear Output Data */ + uint32_t P3:1; /**< bit: 3 Clear Output Data */ + uint32_t P4:1; /**< bit: 4 Clear Output Data */ + uint32_t P5:1; /**< bit: 5 Clear Output Data */ + uint32_t P6:1; /**< bit: 6 Clear Output Data */ + uint32_t P7:1; /**< bit: 7 Clear Output Data */ + uint32_t P8:1; /**< bit: 8 Clear Output Data */ + uint32_t P9:1; /**< bit: 9 Clear Output Data */ + uint32_t P10:1; /**< bit: 10 Clear Output Data */ + uint32_t P11:1; /**< bit: 11 Clear Output Data */ + uint32_t P12:1; /**< bit: 12 Clear Output Data */ + uint32_t P13:1; /**< bit: 13 Clear Output Data */ + uint32_t P14:1; /**< bit: 14 Clear Output Data */ + uint32_t P15:1; /**< bit: 15 Clear Output Data */ + uint32_t P16:1; /**< bit: 16 Clear Output Data */ + uint32_t P17:1; /**< bit: 17 Clear Output Data */ + uint32_t P18:1; /**< bit: 18 Clear Output Data */ + uint32_t P19:1; /**< bit: 19 Clear Output Data */ + uint32_t P20:1; /**< bit: 20 Clear Output Data */ + uint32_t P21:1; /**< bit: 21 Clear Output Data */ + uint32_t P22:1; /**< bit: 22 Clear Output Data */ + uint32_t P23:1; /**< bit: 23 Clear Output Data */ + uint32_t P24:1; /**< bit: 24 Clear Output Data */ + uint32_t P25:1; /**< bit: 25 Clear Output Data */ + uint32_t P26:1; /**< bit: 26 Clear Output Data */ + uint32_t P27:1; /**< bit: 27 Clear Output Data */ + uint32_t P28:1; /**< bit: 28 Clear Output Data */ + uint32_t P29:1; /**< bit: 29 Clear Output Data */ + uint32_t P30:1; /**< bit: 30 Clear Output Data */ + uint32_t P31:1; /**< bit: 31 Clear Output Data */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Clear Output Data */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_CODR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_CODR_OFFSET (0x34) /**< (PIO_CODR) Clear Output Data Register Offset */ + +#define PIO_CODR_P0_Pos 0 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P0_Msk (_U_(0x1) << PIO_CODR_P0_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P0 PIO_CODR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P0_Msk instead */ +#define PIO_CODR_P1_Pos 1 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P1_Msk (_U_(0x1) << PIO_CODR_P1_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P1 PIO_CODR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P1_Msk instead */ +#define PIO_CODR_P2_Pos 2 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P2_Msk (_U_(0x1) << PIO_CODR_P2_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P2 PIO_CODR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P2_Msk instead */ +#define PIO_CODR_P3_Pos 3 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P3_Msk (_U_(0x1) << PIO_CODR_P3_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P3 PIO_CODR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P3_Msk instead */ +#define PIO_CODR_P4_Pos 4 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P4_Msk (_U_(0x1) << PIO_CODR_P4_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P4 PIO_CODR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P4_Msk instead */ +#define PIO_CODR_P5_Pos 5 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P5_Msk (_U_(0x1) << PIO_CODR_P5_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P5 PIO_CODR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P5_Msk instead */ +#define PIO_CODR_P6_Pos 6 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P6_Msk (_U_(0x1) << PIO_CODR_P6_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P6 PIO_CODR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P6_Msk instead */ +#define PIO_CODR_P7_Pos 7 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P7_Msk (_U_(0x1) << PIO_CODR_P7_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P7 PIO_CODR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P7_Msk instead */ +#define PIO_CODR_P8_Pos 8 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P8_Msk (_U_(0x1) << PIO_CODR_P8_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P8 PIO_CODR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P8_Msk instead */ +#define PIO_CODR_P9_Pos 9 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P9_Msk (_U_(0x1) << PIO_CODR_P9_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P9 PIO_CODR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P9_Msk instead */ +#define PIO_CODR_P10_Pos 10 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P10_Msk (_U_(0x1) << PIO_CODR_P10_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P10 PIO_CODR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P10_Msk instead */ +#define PIO_CODR_P11_Pos 11 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P11_Msk (_U_(0x1) << PIO_CODR_P11_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P11 PIO_CODR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P11_Msk instead */ +#define PIO_CODR_P12_Pos 12 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P12_Msk (_U_(0x1) << PIO_CODR_P12_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P12 PIO_CODR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P12_Msk instead */ +#define PIO_CODR_P13_Pos 13 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P13_Msk (_U_(0x1) << PIO_CODR_P13_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P13 PIO_CODR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P13_Msk instead */ +#define PIO_CODR_P14_Pos 14 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P14_Msk (_U_(0x1) << PIO_CODR_P14_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P14 PIO_CODR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P14_Msk instead */ +#define PIO_CODR_P15_Pos 15 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P15_Msk (_U_(0x1) << PIO_CODR_P15_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P15 PIO_CODR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P15_Msk instead */ +#define PIO_CODR_P16_Pos 16 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P16_Msk (_U_(0x1) << PIO_CODR_P16_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P16 PIO_CODR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P16_Msk instead */ +#define PIO_CODR_P17_Pos 17 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P17_Msk (_U_(0x1) << PIO_CODR_P17_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P17 PIO_CODR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P17_Msk instead */ +#define PIO_CODR_P18_Pos 18 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P18_Msk (_U_(0x1) << PIO_CODR_P18_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P18 PIO_CODR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P18_Msk instead */ +#define PIO_CODR_P19_Pos 19 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P19_Msk (_U_(0x1) << PIO_CODR_P19_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P19 PIO_CODR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P19_Msk instead */ +#define PIO_CODR_P20_Pos 20 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P20_Msk (_U_(0x1) << PIO_CODR_P20_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P20 PIO_CODR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P20_Msk instead */ +#define PIO_CODR_P21_Pos 21 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P21_Msk (_U_(0x1) << PIO_CODR_P21_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P21 PIO_CODR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P21_Msk instead */ +#define PIO_CODR_P22_Pos 22 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P22_Msk (_U_(0x1) << PIO_CODR_P22_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P22 PIO_CODR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P22_Msk instead */ +#define PIO_CODR_P23_Pos 23 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P23_Msk (_U_(0x1) << PIO_CODR_P23_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P23 PIO_CODR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P23_Msk instead */ +#define PIO_CODR_P24_Pos 24 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P24_Msk (_U_(0x1) << PIO_CODR_P24_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P24 PIO_CODR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P24_Msk instead */ +#define PIO_CODR_P25_Pos 25 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P25_Msk (_U_(0x1) << PIO_CODR_P25_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P25 PIO_CODR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P25_Msk instead */ +#define PIO_CODR_P26_Pos 26 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P26_Msk (_U_(0x1) << PIO_CODR_P26_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P26 PIO_CODR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P26_Msk instead */ +#define PIO_CODR_P27_Pos 27 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P27_Msk (_U_(0x1) << PIO_CODR_P27_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P27 PIO_CODR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P27_Msk instead */ +#define PIO_CODR_P28_Pos 28 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P28_Msk (_U_(0x1) << PIO_CODR_P28_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P28 PIO_CODR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P28_Msk instead */ +#define PIO_CODR_P29_Pos 29 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P29_Msk (_U_(0x1) << PIO_CODR_P29_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P29 PIO_CODR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P29_Msk instead */ +#define PIO_CODR_P30_Pos 30 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P30_Msk (_U_(0x1) << PIO_CODR_P30_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P30 PIO_CODR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P30_Msk instead */ +#define PIO_CODR_P31_Pos 31 /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P31_Msk (_U_(0x1) << PIO_CODR_P31_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P31 PIO_CODR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_CODR_P31_Msk instead */ +#define PIO_CODR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_CODR) Register MASK (Use PIO_CODR_Msk instead) */ +#define PIO_CODR_Msk _U_(0xFFFFFFFF) /**< (PIO_CODR) Register Mask */ + +#define PIO_CODR_P_Pos 0 /**< (PIO_CODR Position) Clear Output Data */ +#define PIO_CODR_P_Msk (_U_(0xFFFFFFFF) << PIO_CODR_P_Pos) /**< (PIO_CODR Mask) P */ +#define PIO_CODR_P(value) (PIO_CODR_P_Msk & ((value) << PIO_CODR_P_Pos)) + +/* -------- PIO_ODSR : (PIO Offset: 0x38) (R/W 32) Output Data Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Data Status */ + uint32_t P1:1; /**< bit: 1 Output Data Status */ + uint32_t P2:1; /**< bit: 2 Output Data Status */ + uint32_t P3:1; /**< bit: 3 Output Data Status */ + uint32_t P4:1; /**< bit: 4 Output Data Status */ + uint32_t P5:1; /**< bit: 5 Output Data Status */ + uint32_t P6:1; /**< bit: 6 Output Data Status */ + uint32_t P7:1; /**< bit: 7 Output Data Status */ + uint32_t P8:1; /**< bit: 8 Output Data Status */ + uint32_t P9:1; /**< bit: 9 Output Data Status */ + uint32_t P10:1; /**< bit: 10 Output Data Status */ + uint32_t P11:1; /**< bit: 11 Output Data Status */ + uint32_t P12:1; /**< bit: 12 Output Data Status */ + uint32_t P13:1; /**< bit: 13 Output Data Status */ + uint32_t P14:1; /**< bit: 14 Output Data Status */ + uint32_t P15:1; /**< bit: 15 Output Data Status */ + uint32_t P16:1; /**< bit: 16 Output Data Status */ + uint32_t P17:1; /**< bit: 17 Output Data Status */ + uint32_t P18:1; /**< bit: 18 Output Data Status */ + uint32_t P19:1; /**< bit: 19 Output Data Status */ + uint32_t P20:1; /**< bit: 20 Output Data Status */ + uint32_t P21:1; /**< bit: 21 Output Data Status */ + uint32_t P22:1; /**< bit: 22 Output Data Status */ + uint32_t P23:1; /**< bit: 23 Output Data Status */ + uint32_t P24:1; /**< bit: 24 Output Data Status */ + uint32_t P25:1; /**< bit: 25 Output Data Status */ + uint32_t P26:1; /**< bit: 26 Output Data Status */ + uint32_t P27:1; /**< bit: 27 Output Data Status */ + uint32_t P28:1; /**< bit: 28 Output Data Status */ + uint32_t P29:1; /**< bit: 29 Output Data Status */ + uint32_t P30:1; /**< bit: 30 Output Data Status */ + uint32_t P31:1; /**< bit: 31 Output Data Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Data Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ODSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ODSR_OFFSET (0x38) /**< (PIO_ODSR) Output Data Status Register Offset */ + +#define PIO_ODSR_P0_Pos 0 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P0_Msk (_U_(0x1) << PIO_ODSR_P0_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P0 PIO_ODSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P0_Msk instead */ +#define PIO_ODSR_P1_Pos 1 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P1_Msk (_U_(0x1) << PIO_ODSR_P1_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P1 PIO_ODSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P1_Msk instead */ +#define PIO_ODSR_P2_Pos 2 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P2_Msk (_U_(0x1) << PIO_ODSR_P2_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P2 PIO_ODSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P2_Msk instead */ +#define PIO_ODSR_P3_Pos 3 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P3_Msk (_U_(0x1) << PIO_ODSR_P3_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P3 PIO_ODSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P3_Msk instead */ +#define PIO_ODSR_P4_Pos 4 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P4_Msk (_U_(0x1) << PIO_ODSR_P4_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P4 PIO_ODSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P4_Msk instead */ +#define PIO_ODSR_P5_Pos 5 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P5_Msk (_U_(0x1) << PIO_ODSR_P5_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P5 PIO_ODSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P5_Msk instead */ +#define PIO_ODSR_P6_Pos 6 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P6_Msk (_U_(0x1) << PIO_ODSR_P6_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P6 PIO_ODSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P6_Msk instead */ +#define PIO_ODSR_P7_Pos 7 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P7_Msk (_U_(0x1) << PIO_ODSR_P7_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P7 PIO_ODSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P7_Msk instead */ +#define PIO_ODSR_P8_Pos 8 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P8_Msk (_U_(0x1) << PIO_ODSR_P8_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P8 PIO_ODSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P8_Msk instead */ +#define PIO_ODSR_P9_Pos 9 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P9_Msk (_U_(0x1) << PIO_ODSR_P9_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P9 PIO_ODSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P9_Msk instead */ +#define PIO_ODSR_P10_Pos 10 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P10_Msk (_U_(0x1) << PIO_ODSR_P10_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P10 PIO_ODSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P10_Msk instead */ +#define PIO_ODSR_P11_Pos 11 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P11_Msk (_U_(0x1) << PIO_ODSR_P11_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P11 PIO_ODSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P11_Msk instead */ +#define PIO_ODSR_P12_Pos 12 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P12_Msk (_U_(0x1) << PIO_ODSR_P12_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P12 PIO_ODSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P12_Msk instead */ +#define PIO_ODSR_P13_Pos 13 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P13_Msk (_U_(0x1) << PIO_ODSR_P13_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P13 PIO_ODSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P13_Msk instead */ +#define PIO_ODSR_P14_Pos 14 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P14_Msk (_U_(0x1) << PIO_ODSR_P14_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P14 PIO_ODSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P14_Msk instead */ +#define PIO_ODSR_P15_Pos 15 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P15_Msk (_U_(0x1) << PIO_ODSR_P15_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P15 PIO_ODSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P15_Msk instead */ +#define PIO_ODSR_P16_Pos 16 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P16_Msk (_U_(0x1) << PIO_ODSR_P16_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P16 PIO_ODSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P16_Msk instead */ +#define PIO_ODSR_P17_Pos 17 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P17_Msk (_U_(0x1) << PIO_ODSR_P17_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P17 PIO_ODSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P17_Msk instead */ +#define PIO_ODSR_P18_Pos 18 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P18_Msk (_U_(0x1) << PIO_ODSR_P18_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P18 PIO_ODSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P18_Msk instead */ +#define PIO_ODSR_P19_Pos 19 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P19_Msk (_U_(0x1) << PIO_ODSR_P19_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P19 PIO_ODSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P19_Msk instead */ +#define PIO_ODSR_P20_Pos 20 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P20_Msk (_U_(0x1) << PIO_ODSR_P20_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P20 PIO_ODSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P20_Msk instead */ +#define PIO_ODSR_P21_Pos 21 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P21_Msk (_U_(0x1) << PIO_ODSR_P21_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P21 PIO_ODSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P21_Msk instead */ +#define PIO_ODSR_P22_Pos 22 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P22_Msk (_U_(0x1) << PIO_ODSR_P22_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P22 PIO_ODSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P22_Msk instead */ +#define PIO_ODSR_P23_Pos 23 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P23_Msk (_U_(0x1) << PIO_ODSR_P23_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P23 PIO_ODSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P23_Msk instead */ +#define PIO_ODSR_P24_Pos 24 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P24_Msk (_U_(0x1) << PIO_ODSR_P24_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P24 PIO_ODSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P24_Msk instead */ +#define PIO_ODSR_P25_Pos 25 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P25_Msk (_U_(0x1) << PIO_ODSR_P25_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P25 PIO_ODSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P25_Msk instead */ +#define PIO_ODSR_P26_Pos 26 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P26_Msk (_U_(0x1) << PIO_ODSR_P26_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P26 PIO_ODSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P26_Msk instead */ +#define PIO_ODSR_P27_Pos 27 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P27_Msk (_U_(0x1) << PIO_ODSR_P27_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P27 PIO_ODSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P27_Msk instead */ +#define PIO_ODSR_P28_Pos 28 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P28_Msk (_U_(0x1) << PIO_ODSR_P28_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P28 PIO_ODSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P28_Msk instead */ +#define PIO_ODSR_P29_Pos 29 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P29_Msk (_U_(0x1) << PIO_ODSR_P29_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P29 PIO_ODSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P29_Msk instead */ +#define PIO_ODSR_P30_Pos 30 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P30_Msk (_U_(0x1) << PIO_ODSR_P30_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P30 PIO_ODSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P30_Msk instead */ +#define PIO_ODSR_P31_Pos 31 /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P31_Msk (_U_(0x1) << PIO_ODSR_P31_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P31 PIO_ODSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ODSR_P31_Msk instead */ +#define PIO_ODSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ODSR) Register MASK (Use PIO_ODSR_Msk instead) */ +#define PIO_ODSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODSR) Register Mask */ + +#define PIO_ODSR_P_Pos 0 /**< (PIO_ODSR Position) Output Data Status */ +#define PIO_ODSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODSR_P_Pos) /**< (PIO_ODSR Mask) P */ +#define PIO_ODSR_P(value) (PIO_ODSR_P_Msk & ((value) << PIO_ODSR_P_Pos)) + +/* -------- PIO_PDSR : (PIO Offset: 0x3c) (R/ 32) Pin Data Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Data Status */ + uint32_t P1:1; /**< bit: 1 Output Data Status */ + uint32_t P2:1; /**< bit: 2 Output Data Status */ + uint32_t P3:1; /**< bit: 3 Output Data Status */ + uint32_t P4:1; /**< bit: 4 Output Data Status */ + uint32_t P5:1; /**< bit: 5 Output Data Status */ + uint32_t P6:1; /**< bit: 6 Output Data Status */ + uint32_t P7:1; /**< bit: 7 Output Data Status */ + uint32_t P8:1; /**< bit: 8 Output Data Status */ + uint32_t P9:1; /**< bit: 9 Output Data Status */ + uint32_t P10:1; /**< bit: 10 Output Data Status */ + uint32_t P11:1; /**< bit: 11 Output Data Status */ + uint32_t P12:1; /**< bit: 12 Output Data Status */ + uint32_t P13:1; /**< bit: 13 Output Data Status */ + uint32_t P14:1; /**< bit: 14 Output Data Status */ + uint32_t P15:1; /**< bit: 15 Output Data Status */ + uint32_t P16:1; /**< bit: 16 Output Data Status */ + uint32_t P17:1; /**< bit: 17 Output Data Status */ + uint32_t P18:1; /**< bit: 18 Output Data Status */ + uint32_t P19:1; /**< bit: 19 Output Data Status */ + uint32_t P20:1; /**< bit: 20 Output Data Status */ + uint32_t P21:1; /**< bit: 21 Output Data Status */ + uint32_t P22:1; /**< bit: 22 Output Data Status */ + uint32_t P23:1; /**< bit: 23 Output Data Status */ + uint32_t P24:1; /**< bit: 24 Output Data Status */ + uint32_t P25:1; /**< bit: 25 Output Data Status */ + uint32_t P26:1; /**< bit: 26 Output Data Status */ + uint32_t P27:1; /**< bit: 27 Output Data Status */ + uint32_t P28:1; /**< bit: 28 Output Data Status */ + uint32_t P29:1; /**< bit: 29 Output Data Status */ + uint32_t P30:1; /**< bit: 30 Output Data Status */ + uint32_t P31:1; /**< bit: 31 Output Data Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Data Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PDSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PDSR_OFFSET (0x3C) /**< (PIO_PDSR) Pin Data Status Register Offset */ + +#define PIO_PDSR_P0_Pos 0 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P0_Msk (_U_(0x1) << PIO_PDSR_P0_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P0 PIO_PDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P0_Msk instead */ +#define PIO_PDSR_P1_Pos 1 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P1_Msk (_U_(0x1) << PIO_PDSR_P1_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P1 PIO_PDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P1_Msk instead */ +#define PIO_PDSR_P2_Pos 2 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P2_Msk (_U_(0x1) << PIO_PDSR_P2_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P2 PIO_PDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P2_Msk instead */ +#define PIO_PDSR_P3_Pos 3 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P3_Msk (_U_(0x1) << PIO_PDSR_P3_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P3 PIO_PDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P3_Msk instead */ +#define PIO_PDSR_P4_Pos 4 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P4_Msk (_U_(0x1) << PIO_PDSR_P4_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P4 PIO_PDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P4_Msk instead */ +#define PIO_PDSR_P5_Pos 5 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P5_Msk (_U_(0x1) << PIO_PDSR_P5_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P5 PIO_PDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P5_Msk instead */ +#define PIO_PDSR_P6_Pos 6 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P6_Msk (_U_(0x1) << PIO_PDSR_P6_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P6 PIO_PDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P6_Msk instead */ +#define PIO_PDSR_P7_Pos 7 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P7_Msk (_U_(0x1) << PIO_PDSR_P7_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P7 PIO_PDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P7_Msk instead */ +#define PIO_PDSR_P8_Pos 8 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P8_Msk (_U_(0x1) << PIO_PDSR_P8_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P8 PIO_PDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P8_Msk instead */ +#define PIO_PDSR_P9_Pos 9 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P9_Msk (_U_(0x1) << PIO_PDSR_P9_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P9 PIO_PDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P9_Msk instead */ +#define PIO_PDSR_P10_Pos 10 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P10_Msk (_U_(0x1) << PIO_PDSR_P10_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P10 PIO_PDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P10_Msk instead */ +#define PIO_PDSR_P11_Pos 11 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P11_Msk (_U_(0x1) << PIO_PDSR_P11_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P11 PIO_PDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P11_Msk instead */ +#define PIO_PDSR_P12_Pos 12 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P12_Msk (_U_(0x1) << PIO_PDSR_P12_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P12 PIO_PDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P12_Msk instead */ +#define PIO_PDSR_P13_Pos 13 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P13_Msk (_U_(0x1) << PIO_PDSR_P13_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P13 PIO_PDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P13_Msk instead */ +#define PIO_PDSR_P14_Pos 14 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P14_Msk (_U_(0x1) << PIO_PDSR_P14_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P14 PIO_PDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P14_Msk instead */ +#define PIO_PDSR_P15_Pos 15 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P15_Msk (_U_(0x1) << PIO_PDSR_P15_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P15 PIO_PDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P15_Msk instead */ +#define PIO_PDSR_P16_Pos 16 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P16_Msk (_U_(0x1) << PIO_PDSR_P16_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P16 PIO_PDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P16_Msk instead */ +#define PIO_PDSR_P17_Pos 17 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P17_Msk (_U_(0x1) << PIO_PDSR_P17_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P17 PIO_PDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P17_Msk instead */ +#define PIO_PDSR_P18_Pos 18 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P18_Msk (_U_(0x1) << PIO_PDSR_P18_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P18 PIO_PDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P18_Msk instead */ +#define PIO_PDSR_P19_Pos 19 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P19_Msk (_U_(0x1) << PIO_PDSR_P19_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P19 PIO_PDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P19_Msk instead */ +#define PIO_PDSR_P20_Pos 20 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P20_Msk (_U_(0x1) << PIO_PDSR_P20_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P20 PIO_PDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P20_Msk instead */ +#define PIO_PDSR_P21_Pos 21 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P21_Msk (_U_(0x1) << PIO_PDSR_P21_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P21 PIO_PDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P21_Msk instead */ +#define PIO_PDSR_P22_Pos 22 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P22_Msk (_U_(0x1) << PIO_PDSR_P22_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P22 PIO_PDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P22_Msk instead */ +#define PIO_PDSR_P23_Pos 23 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P23_Msk (_U_(0x1) << PIO_PDSR_P23_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P23 PIO_PDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P23_Msk instead */ +#define PIO_PDSR_P24_Pos 24 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P24_Msk (_U_(0x1) << PIO_PDSR_P24_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P24 PIO_PDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P24_Msk instead */ +#define PIO_PDSR_P25_Pos 25 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P25_Msk (_U_(0x1) << PIO_PDSR_P25_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P25 PIO_PDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P25_Msk instead */ +#define PIO_PDSR_P26_Pos 26 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P26_Msk (_U_(0x1) << PIO_PDSR_P26_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P26 PIO_PDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P26_Msk instead */ +#define PIO_PDSR_P27_Pos 27 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P27_Msk (_U_(0x1) << PIO_PDSR_P27_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P27 PIO_PDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P27_Msk instead */ +#define PIO_PDSR_P28_Pos 28 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P28_Msk (_U_(0x1) << PIO_PDSR_P28_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P28 PIO_PDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P28_Msk instead */ +#define PIO_PDSR_P29_Pos 29 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P29_Msk (_U_(0x1) << PIO_PDSR_P29_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P29 PIO_PDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P29_Msk instead */ +#define PIO_PDSR_P30_Pos 30 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P30_Msk (_U_(0x1) << PIO_PDSR_P30_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P30 PIO_PDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P30_Msk instead */ +#define PIO_PDSR_P31_Pos 31 /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P31_Msk (_U_(0x1) << PIO_PDSR_P31_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P31 PIO_PDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PDSR_P31_Msk instead */ +#define PIO_PDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PDSR) Register MASK (Use PIO_PDSR_Msk instead) */ +#define PIO_PDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDSR) Register Mask */ + +#define PIO_PDSR_P_Pos 0 /**< (PIO_PDSR Position) Output Data Status */ +#define PIO_PDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDSR_P_Pos) /**< (PIO_PDSR Mask) P */ +#define PIO_PDSR_P(value) (PIO_PDSR_P_Msk & ((value) << PIO_PDSR_P_Pos)) + +/* -------- PIO_IER : (PIO Offset: 0x40) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Change Interrupt Enable */ + uint32_t P1:1; /**< bit: 1 Input Change Interrupt Enable */ + uint32_t P2:1; /**< bit: 2 Input Change Interrupt Enable */ + uint32_t P3:1; /**< bit: 3 Input Change Interrupt Enable */ + uint32_t P4:1; /**< bit: 4 Input Change Interrupt Enable */ + uint32_t P5:1; /**< bit: 5 Input Change Interrupt Enable */ + uint32_t P6:1; /**< bit: 6 Input Change Interrupt Enable */ + uint32_t P7:1; /**< bit: 7 Input Change Interrupt Enable */ + uint32_t P8:1; /**< bit: 8 Input Change Interrupt Enable */ + uint32_t P9:1; /**< bit: 9 Input Change Interrupt Enable */ + uint32_t P10:1; /**< bit: 10 Input Change Interrupt Enable */ + uint32_t P11:1; /**< bit: 11 Input Change Interrupt Enable */ + uint32_t P12:1; /**< bit: 12 Input Change Interrupt Enable */ + uint32_t P13:1; /**< bit: 13 Input Change Interrupt Enable */ + uint32_t P14:1; /**< bit: 14 Input Change Interrupt Enable */ + uint32_t P15:1; /**< bit: 15 Input Change Interrupt Enable */ + uint32_t P16:1; /**< bit: 16 Input Change Interrupt Enable */ + uint32_t P17:1; /**< bit: 17 Input Change Interrupt Enable */ + uint32_t P18:1; /**< bit: 18 Input Change Interrupt Enable */ + uint32_t P19:1; /**< bit: 19 Input Change Interrupt Enable */ + uint32_t P20:1; /**< bit: 20 Input Change Interrupt Enable */ + uint32_t P21:1; /**< bit: 21 Input Change Interrupt Enable */ + uint32_t P22:1; /**< bit: 22 Input Change Interrupt Enable */ + uint32_t P23:1; /**< bit: 23 Input Change Interrupt Enable */ + uint32_t P24:1; /**< bit: 24 Input Change Interrupt Enable */ + uint32_t P25:1; /**< bit: 25 Input Change Interrupt Enable */ + uint32_t P26:1; /**< bit: 26 Input Change Interrupt Enable */ + uint32_t P27:1; /**< bit: 27 Input Change Interrupt Enable */ + uint32_t P28:1; /**< bit: 28 Input Change Interrupt Enable */ + uint32_t P29:1; /**< bit: 29 Input Change Interrupt Enable */ + uint32_t P30:1; /**< bit: 30 Input Change Interrupt Enable */ + uint32_t P31:1; /**< bit: 31 Input Change Interrupt Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IER_OFFSET (0x40) /**< (PIO_IER) Interrupt Enable Register Offset */ + +#define PIO_IER_P0_Pos 0 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P0_Msk (_U_(0x1) << PIO_IER_P0_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P0 PIO_IER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P0_Msk instead */ +#define PIO_IER_P1_Pos 1 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P1_Msk (_U_(0x1) << PIO_IER_P1_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P1 PIO_IER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P1_Msk instead */ +#define PIO_IER_P2_Pos 2 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P2_Msk (_U_(0x1) << PIO_IER_P2_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P2 PIO_IER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P2_Msk instead */ +#define PIO_IER_P3_Pos 3 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P3_Msk (_U_(0x1) << PIO_IER_P3_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P3 PIO_IER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P3_Msk instead */ +#define PIO_IER_P4_Pos 4 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P4_Msk (_U_(0x1) << PIO_IER_P4_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P4 PIO_IER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P4_Msk instead */ +#define PIO_IER_P5_Pos 5 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P5_Msk (_U_(0x1) << PIO_IER_P5_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P5 PIO_IER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P5_Msk instead */ +#define PIO_IER_P6_Pos 6 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P6_Msk (_U_(0x1) << PIO_IER_P6_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P6 PIO_IER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P6_Msk instead */ +#define PIO_IER_P7_Pos 7 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P7_Msk (_U_(0x1) << PIO_IER_P7_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P7 PIO_IER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P7_Msk instead */ +#define PIO_IER_P8_Pos 8 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P8_Msk (_U_(0x1) << PIO_IER_P8_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P8 PIO_IER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P8_Msk instead */ +#define PIO_IER_P9_Pos 9 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P9_Msk (_U_(0x1) << PIO_IER_P9_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P9 PIO_IER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P9_Msk instead */ +#define PIO_IER_P10_Pos 10 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P10_Msk (_U_(0x1) << PIO_IER_P10_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P10 PIO_IER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P10_Msk instead */ +#define PIO_IER_P11_Pos 11 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P11_Msk (_U_(0x1) << PIO_IER_P11_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P11 PIO_IER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P11_Msk instead */ +#define PIO_IER_P12_Pos 12 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P12_Msk (_U_(0x1) << PIO_IER_P12_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P12 PIO_IER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P12_Msk instead */ +#define PIO_IER_P13_Pos 13 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P13_Msk (_U_(0x1) << PIO_IER_P13_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P13 PIO_IER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P13_Msk instead */ +#define PIO_IER_P14_Pos 14 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P14_Msk (_U_(0x1) << PIO_IER_P14_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P14 PIO_IER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P14_Msk instead */ +#define PIO_IER_P15_Pos 15 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P15_Msk (_U_(0x1) << PIO_IER_P15_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P15 PIO_IER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P15_Msk instead */ +#define PIO_IER_P16_Pos 16 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P16_Msk (_U_(0x1) << PIO_IER_P16_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P16 PIO_IER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P16_Msk instead */ +#define PIO_IER_P17_Pos 17 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P17_Msk (_U_(0x1) << PIO_IER_P17_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P17 PIO_IER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P17_Msk instead */ +#define PIO_IER_P18_Pos 18 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P18_Msk (_U_(0x1) << PIO_IER_P18_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P18 PIO_IER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P18_Msk instead */ +#define PIO_IER_P19_Pos 19 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P19_Msk (_U_(0x1) << PIO_IER_P19_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P19 PIO_IER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P19_Msk instead */ +#define PIO_IER_P20_Pos 20 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P20_Msk (_U_(0x1) << PIO_IER_P20_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P20 PIO_IER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P20_Msk instead */ +#define PIO_IER_P21_Pos 21 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P21_Msk (_U_(0x1) << PIO_IER_P21_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P21 PIO_IER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P21_Msk instead */ +#define PIO_IER_P22_Pos 22 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P22_Msk (_U_(0x1) << PIO_IER_P22_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P22 PIO_IER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P22_Msk instead */ +#define PIO_IER_P23_Pos 23 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P23_Msk (_U_(0x1) << PIO_IER_P23_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P23 PIO_IER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P23_Msk instead */ +#define PIO_IER_P24_Pos 24 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P24_Msk (_U_(0x1) << PIO_IER_P24_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P24 PIO_IER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P24_Msk instead */ +#define PIO_IER_P25_Pos 25 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P25_Msk (_U_(0x1) << PIO_IER_P25_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P25 PIO_IER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P25_Msk instead */ +#define PIO_IER_P26_Pos 26 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P26_Msk (_U_(0x1) << PIO_IER_P26_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P26 PIO_IER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P26_Msk instead */ +#define PIO_IER_P27_Pos 27 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P27_Msk (_U_(0x1) << PIO_IER_P27_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P27 PIO_IER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P27_Msk instead */ +#define PIO_IER_P28_Pos 28 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P28_Msk (_U_(0x1) << PIO_IER_P28_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P28 PIO_IER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P28_Msk instead */ +#define PIO_IER_P29_Pos 29 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P29_Msk (_U_(0x1) << PIO_IER_P29_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P29 PIO_IER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P29_Msk instead */ +#define PIO_IER_P30_Pos 30 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P30_Msk (_U_(0x1) << PIO_IER_P30_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P30 PIO_IER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P30_Msk instead */ +#define PIO_IER_P31_Pos 31 /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P31_Msk (_U_(0x1) << PIO_IER_P31_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P31 PIO_IER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IER_P31_Msk instead */ +#define PIO_IER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IER) Register MASK (Use PIO_IER_Msk instead) */ +#define PIO_IER_Msk _U_(0xFFFFFFFF) /**< (PIO_IER) Register Mask */ + +#define PIO_IER_P_Pos 0 /**< (PIO_IER Position) Input Change Interrupt Enable */ +#define PIO_IER_P_Msk (_U_(0xFFFFFFFF) << PIO_IER_P_Pos) /**< (PIO_IER Mask) P */ +#define PIO_IER_P(value) (PIO_IER_P_Msk & ((value) << PIO_IER_P_Pos)) + +/* -------- PIO_IDR : (PIO Offset: 0x44) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Change Interrupt Disable */ + uint32_t P1:1; /**< bit: 1 Input Change Interrupt Disable */ + uint32_t P2:1; /**< bit: 2 Input Change Interrupt Disable */ + uint32_t P3:1; /**< bit: 3 Input Change Interrupt Disable */ + uint32_t P4:1; /**< bit: 4 Input Change Interrupt Disable */ + uint32_t P5:1; /**< bit: 5 Input Change Interrupt Disable */ + uint32_t P6:1; /**< bit: 6 Input Change Interrupt Disable */ + uint32_t P7:1; /**< bit: 7 Input Change Interrupt Disable */ + uint32_t P8:1; /**< bit: 8 Input Change Interrupt Disable */ + uint32_t P9:1; /**< bit: 9 Input Change Interrupt Disable */ + uint32_t P10:1; /**< bit: 10 Input Change Interrupt Disable */ + uint32_t P11:1; /**< bit: 11 Input Change Interrupt Disable */ + uint32_t P12:1; /**< bit: 12 Input Change Interrupt Disable */ + uint32_t P13:1; /**< bit: 13 Input Change Interrupt Disable */ + uint32_t P14:1; /**< bit: 14 Input Change Interrupt Disable */ + uint32_t P15:1; /**< bit: 15 Input Change Interrupt Disable */ + uint32_t P16:1; /**< bit: 16 Input Change Interrupt Disable */ + uint32_t P17:1; /**< bit: 17 Input Change Interrupt Disable */ + uint32_t P18:1; /**< bit: 18 Input Change Interrupt Disable */ + uint32_t P19:1; /**< bit: 19 Input Change Interrupt Disable */ + uint32_t P20:1; /**< bit: 20 Input Change Interrupt Disable */ + uint32_t P21:1; /**< bit: 21 Input Change Interrupt Disable */ + uint32_t P22:1; /**< bit: 22 Input Change Interrupt Disable */ + uint32_t P23:1; /**< bit: 23 Input Change Interrupt Disable */ + uint32_t P24:1; /**< bit: 24 Input Change Interrupt Disable */ + uint32_t P25:1; /**< bit: 25 Input Change Interrupt Disable */ + uint32_t P26:1; /**< bit: 26 Input Change Interrupt Disable */ + uint32_t P27:1; /**< bit: 27 Input Change Interrupt Disable */ + uint32_t P28:1; /**< bit: 28 Input Change Interrupt Disable */ + uint32_t P29:1; /**< bit: 29 Input Change Interrupt Disable */ + uint32_t P30:1; /**< bit: 30 Input Change Interrupt Disable */ + uint32_t P31:1; /**< bit: 31 Input Change Interrupt Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IDR_OFFSET (0x44) /**< (PIO_IDR) Interrupt Disable Register Offset */ + +#define PIO_IDR_P0_Pos 0 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P0_Msk (_U_(0x1) << PIO_IDR_P0_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P0 PIO_IDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P0_Msk instead */ +#define PIO_IDR_P1_Pos 1 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P1_Msk (_U_(0x1) << PIO_IDR_P1_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P1 PIO_IDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P1_Msk instead */ +#define PIO_IDR_P2_Pos 2 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P2_Msk (_U_(0x1) << PIO_IDR_P2_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P2 PIO_IDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P2_Msk instead */ +#define PIO_IDR_P3_Pos 3 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P3_Msk (_U_(0x1) << PIO_IDR_P3_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P3 PIO_IDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P3_Msk instead */ +#define PIO_IDR_P4_Pos 4 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P4_Msk (_U_(0x1) << PIO_IDR_P4_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P4 PIO_IDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P4_Msk instead */ +#define PIO_IDR_P5_Pos 5 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P5_Msk (_U_(0x1) << PIO_IDR_P5_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P5 PIO_IDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P5_Msk instead */ +#define PIO_IDR_P6_Pos 6 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P6_Msk (_U_(0x1) << PIO_IDR_P6_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P6 PIO_IDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P6_Msk instead */ +#define PIO_IDR_P7_Pos 7 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P7_Msk (_U_(0x1) << PIO_IDR_P7_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P7 PIO_IDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P7_Msk instead */ +#define PIO_IDR_P8_Pos 8 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P8_Msk (_U_(0x1) << PIO_IDR_P8_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P8 PIO_IDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P8_Msk instead */ +#define PIO_IDR_P9_Pos 9 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P9_Msk (_U_(0x1) << PIO_IDR_P9_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P9 PIO_IDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P9_Msk instead */ +#define PIO_IDR_P10_Pos 10 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P10_Msk (_U_(0x1) << PIO_IDR_P10_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P10 PIO_IDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P10_Msk instead */ +#define PIO_IDR_P11_Pos 11 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P11_Msk (_U_(0x1) << PIO_IDR_P11_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P11 PIO_IDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P11_Msk instead */ +#define PIO_IDR_P12_Pos 12 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P12_Msk (_U_(0x1) << PIO_IDR_P12_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P12 PIO_IDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P12_Msk instead */ +#define PIO_IDR_P13_Pos 13 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P13_Msk (_U_(0x1) << PIO_IDR_P13_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P13 PIO_IDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P13_Msk instead */ +#define PIO_IDR_P14_Pos 14 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P14_Msk (_U_(0x1) << PIO_IDR_P14_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P14 PIO_IDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P14_Msk instead */ +#define PIO_IDR_P15_Pos 15 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P15_Msk (_U_(0x1) << PIO_IDR_P15_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P15 PIO_IDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P15_Msk instead */ +#define PIO_IDR_P16_Pos 16 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P16_Msk (_U_(0x1) << PIO_IDR_P16_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P16 PIO_IDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P16_Msk instead */ +#define PIO_IDR_P17_Pos 17 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P17_Msk (_U_(0x1) << PIO_IDR_P17_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P17 PIO_IDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P17_Msk instead */ +#define PIO_IDR_P18_Pos 18 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P18_Msk (_U_(0x1) << PIO_IDR_P18_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P18 PIO_IDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P18_Msk instead */ +#define PIO_IDR_P19_Pos 19 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P19_Msk (_U_(0x1) << PIO_IDR_P19_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P19 PIO_IDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P19_Msk instead */ +#define PIO_IDR_P20_Pos 20 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P20_Msk (_U_(0x1) << PIO_IDR_P20_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P20 PIO_IDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P20_Msk instead */ +#define PIO_IDR_P21_Pos 21 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P21_Msk (_U_(0x1) << PIO_IDR_P21_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P21 PIO_IDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P21_Msk instead */ +#define PIO_IDR_P22_Pos 22 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P22_Msk (_U_(0x1) << PIO_IDR_P22_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P22 PIO_IDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P22_Msk instead */ +#define PIO_IDR_P23_Pos 23 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P23_Msk (_U_(0x1) << PIO_IDR_P23_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P23 PIO_IDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P23_Msk instead */ +#define PIO_IDR_P24_Pos 24 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P24_Msk (_U_(0x1) << PIO_IDR_P24_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P24 PIO_IDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P24_Msk instead */ +#define PIO_IDR_P25_Pos 25 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P25_Msk (_U_(0x1) << PIO_IDR_P25_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P25 PIO_IDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P25_Msk instead */ +#define PIO_IDR_P26_Pos 26 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P26_Msk (_U_(0x1) << PIO_IDR_P26_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P26 PIO_IDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P26_Msk instead */ +#define PIO_IDR_P27_Pos 27 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P27_Msk (_U_(0x1) << PIO_IDR_P27_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P27 PIO_IDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P27_Msk instead */ +#define PIO_IDR_P28_Pos 28 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P28_Msk (_U_(0x1) << PIO_IDR_P28_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P28 PIO_IDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P28_Msk instead */ +#define PIO_IDR_P29_Pos 29 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P29_Msk (_U_(0x1) << PIO_IDR_P29_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P29 PIO_IDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P29_Msk instead */ +#define PIO_IDR_P30_Pos 30 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P30_Msk (_U_(0x1) << PIO_IDR_P30_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P30 PIO_IDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P30_Msk instead */ +#define PIO_IDR_P31_Pos 31 /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P31_Msk (_U_(0x1) << PIO_IDR_P31_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P31 PIO_IDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IDR_P31_Msk instead */ +#define PIO_IDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IDR) Register MASK (Use PIO_IDR_Msk instead) */ +#define PIO_IDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IDR) Register Mask */ + +#define PIO_IDR_P_Pos 0 /**< (PIO_IDR Position) Input Change Interrupt Disable */ +#define PIO_IDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IDR_P_Pos) /**< (PIO_IDR Mask) P */ +#define PIO_IDR_P(value) (PIO_IDR_P_Msk & ((value) << PIO_IDR_P_Pos)) + +/* -------- PIO_IMR : (PIO Offset: 0x48) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Change Interrupt Mask */ + uint32_t P1:1; /**< bit: 1 Input Change Interrupt Mask */ + uint32_t P2:1; /**< bit: 2 Input Change Interrupt Mask */ + uint32_t P3:1; /**< bit: 3 Input Change Interrupt Mask */ + uint32_t P4:1; /**< bit: 4 Input Change Interrupt Mask */ + uint32_t P5:1; /**< bit: 5 Input Change Interrupt Mask */ + uint32_t P6:1; /**< bit: 6 Input Change Interrupt Mask */ + uint32_t P7:1; /**< bit: 7 Input Change Interrupt Mask */ + uint32_t P8:1; /**< bit: 8 Input Change Interrupt Mask */ + uint32_t P9:1; /**< bit: 9 Input Change Interrupt Mask */ + uint32_t P10:1; /**< bit: 10 Input Change Interrupt Mask */ + uint32_t P11:1; /**< bit: 11 Input Change Interrupt Mask */ + uint32_t P12:1; /**< bit: 12 Input Change Interrupt Mask */ + uint32_t P13:1; /**< bit: 13 Input Change Interrupt Mask */ + uint32_t P14:1; /**< bit: 14 Input Change Interrupt Mask */ + uint32_t P15:1; /**< bit: 15 Input Change Interrupt Mask */ + uint32_t P16:1; /**< bit: 16 Input Change Interrupt Mask */ + uint32_t P17:1; /**< bit: 17 Input Change Interrupt Mask */ + uint32_t P18:1; /**< bit: 18 Input Change Interrupt Mask */ + uint32_t P19:1; /**< bit: 19 Input Change Interrupt Mask */ + uint32_t P20:1; /**< bit: 20 Input Change Interrupt Mask */ + uint32_t P21:1; /**< bit: 21 Input Change Interrupt Mask */ + uint32_t P22:1; /**< bit: 22 Input Change Interrupt Mask */ + uint32_t P23:1; /**< bit: 23 Input Change Interrupt Mask */ + uint32_t P24:1; /**< bit: 24 Input Change Interrupt Mask */ + uint32_t P25:1; /**< bit: 25 Input Change Interrupt Mask */ + uint32_t P26:1; /**< bit: 26 Input Change Interrupt Mask */ + uint32_t P27:1; /**< bit: 27 Input Change Interrupt Mask */ + uint32_t P28:1; /**< bit: 28 Input Change Interrupt Mask */ + uint32_t P29:1; /**< bit: 29 Input Change Interrupt Mask */ + uint32_t P30:1; /**< bit: 30 Input Change Interrupt Mask */ + uint32_t P31:1; /**< bit: 31 Input Change Interrupt Mask */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Mask */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IMR_OFFSET (0x48) /**< (PIO_IMR) Interrupt Mask Register Offset */ + +#define PIO_IMR_P0_Pos 0 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P0_Msk (_U_(0x1) << PIO_IMR_P0_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P0 PIO_IMR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P0_Msk instead */ +#define PIO_IMR_P1_Pos 1 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P1_Msk (_U_(0x1) << PIO_IMR_P1_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P1 PIO_IMR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P1_Msk instead */ +#define PIO_IMR_P2_Pos 2 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P2_Msk (_U_(0x1) << PIO_IMR_P2_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P2 PIO_IMR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P2_Msk instead */ +#define PIO_IMR_P3_Pos 3 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P3_Msk (_U_(0x1) << PIO_IMR_P3_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P3 PIO_IMR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P3_Msk instead */ +#define PIO_IMR_P4_Pos 4 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P4_Msk (_U_(0x1) << PIO_IMR_P4_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P4 PIO_IMR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P4_Msk instead */ +#define PIO_IMR_P5_Pos 5 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P5_Msk (_U_(0x1) << PIO_IMR_P5_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P5 PIO_IMR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P5_Msk instead */ +#define PIO_IMR_P6_Pos 6 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P6_Msk (_U_(0x1) << PIO_IMR_P6_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P6 PIO_IMR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P6_Msk instead */ +#define PIO_IMR_P7_Pos 7 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P7_Msk (_U_(0x1) << PIO_IMR_P7_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P7 PIO_IMR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P7_Msk instead */ +#define PIO_IMR_P8_Pos 8 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P8_Msk (_U_(0x1) << PIO_IMR_P8_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P8 PIO_IMR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P8_Msk instead */ +#define PIO_IMR_P9_Pos 9 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P9_Msk (_U_(0x1) << PIO_IMR_P9_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P9 PIO_IMR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P9_Msk instead */ +#define PIO_IMR_P10_Pos 10 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P10_Msk (_U_(0x1) << PIO_IMR_P10_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P10 PIO_IMR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P10_Msk instead */ +#define PIO_IMR_P11_Pos 11 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P11_Msk (_U_(0x1) << PIO_IMR_P11_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P11 PIO_IMR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P11_Msk instead */ +#define PIO_IMR_P12_Pos 12 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P12_Msk (_U_(0x1) << PIO_IMR_P12_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P12 PIO_IMR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P12_Msk instead */ +#define PIO_IMR_P13_Pos 13 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P13_Msk (_U_(0x1) << PIO_IMR_P13_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P13 PIO_IMR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P13_Msk instead */ +#define PIO_IMR_P14_Pos 14 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P14_Msk (_U_(0x1) << PIO_IMR_P14_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P14 PIO_IMR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P14_Msk instead */ +#define PIO_IMR_P15_Pos 15 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P15_Msk (_U_(0x1) << PIO_IMR_P15_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P15 PIO_IMR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P15_Msk instead */ +#define PIO_IMR_P16_Pos 16 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P16_Msk (_U_(0x1) << PIO_IMR_P16_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P16 PIO_IMR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P16_Msk instead */ +#define PIO_IMR_P17_Pos 17 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P17_Msk (_U_(0x1) << PIO_IMR_P17_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P17 PIO_IMR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P17_Msk instead */ +#define PIO_IMR_P18_Pos 18 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P18_Msk (_U_(0x1) << PIO_IMR_P18_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P18 PIO_IMR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P18_Msk instead */ +#define PIO_IMR_P19_Pos 19 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P19_Msk (_U_(0x1) << PIO_IMR_P19_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P19 PIO_IMR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P19_Msk instead */ +#define PIO_IMR_P20_Pos 20 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P20_Msk (_U_(0x1) << PIO_IMR_P20_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P20 PIO_IMR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P20_Msk instead */ +#define PIO_IMR_P21_Pos 21 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P21_Msk (_U_(0x1) << PIO_IMR_P21_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P21 PIO_IMR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P21_Msk instead */ +#define PIO_IMR_P22_Pos 22 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P22_Msk (_U_(0x1) << PIO_IMR_P22_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P22 PIO_IMR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P22_Msk instead */ +#define PIO_IMR_P23_Pos 23 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P23_Msk (_U_(0x1) << PIO_IMR_P23_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P23 PIO_IMR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P23_Msk instead */ +#define PIO_IMR_P24_Pos 24 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P24_Msk (_U_(0x1) << PIO_IMR_P24_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P24 PIO_IMR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P24_Msk instead */ +#define PIO_IMR_P25_Pos 25 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P25_Msk (_U_(0x1) << PIO_IMR_P25_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P25 PIO_IMR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P25_Msk instead */ +#define PIO_IMR_P26_Pos 26 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P26_Msk (_U_(0x1) << PIO_IMR_P26_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P26 PIO_IMR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P26_Msk instead */ +#define PIO_IMR_P27_Pos 27 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P27_Msk (_U_(0x1) << PIO_IMR_P27_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P27 PIO_IMR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P27_Msk instead */ +#define PIO_IMR_P28_Pos 28 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P28_Msk (_U_(0x1) << PIO_IMR_P28_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P28 PIO_IMR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P28_Msk instead */ +#define PIO_IMR_P29_Pos 29 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P29_Msk (_U_(0x1) << PIO_IMR_P29_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P29 PIO_IMR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P29_Msk instead */ +#define PIO_IMR_P30_Pos 30 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P30_Msk (_U_(0x1) << PIO_IMR_P30_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P30 PIO_IMR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P30_Msk instead */ +#define PIO_IMR_P31_Pos 31 /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P31_Msk (_U_(0x1) << PIO_IMR_P31_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P31 PIO_IMR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IMR_P31_Msk instead */ +#define PIO_IMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IMR) Register MASK (Use PIO_IMR_Msk instead) */ +#define PIO_IMR_Msk _U_(0xFFFFFFFF) /**< (PIO_IMR) Register Mask */ + +#define PIO_IMR_P_Pos 0 /**< (PIO_IMR Position) Input Change Interrupt Mask */ +#define PIO_IMR_P_Msk (_U_(0xFFFFFFFF) << PIO_IMR_P_Pos) /**< (PIO_IMR Mask) P */ +#define PIO_IMR_P(value) (PIO_IMR_P_Msk & ((value) << PIO_IMR_P_Pos)) + +/* -------- PIO_ISR : (PIO Offset: 0x4c) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Input Change Interrupt Status */ + uint32_t P1:1; /**< bit: 1 Input Change Interrupt Status */ + uint32_t P2:1; /**< bit: 2 Input Change Interrupt Status */ + uint32_t P3:1; /**< bit: 3 Input Change Interrupt Status */ + uint32_t P4:1; /**< bit: 4 Input Change Interrupt Status */ + uint32_t P5:1; /**< bit: 5 Input Change Interrupt Status */ + uint32_t P6:1; /**< bit: 6 Input Change Interrupt Status */ + uint32_t P7:1; /**< bit: 7 Input Change Interrupt Status */ + uint32_t P8:1; /**< bit: 8 Input Change Interrupt Status */ + uint32_t P9:1; /**< bit: 9 Input Change Interrupt Status */ + uint32_t P10:1; /**< bit: 10 Input Change Interrupt Status */ + uint32_t P11:1; /**< bit: 11 Input Change Interrupt Status */ + uint32_t P12:1; /**< bit: 12 Input Change Interrupt Status */ + uint32_t P13:1; /**< bit: 13 Input Change Interrupt Status */ + uint32_t P14:1; /**< bit: 14 Input Change Interrupt Status */ + uint32_t P15:1; /**< bit: 15 Input Change Interrupt Status */ + uint32_t P16:1; /**< bit: 16 Input Change Interrupt Status */ + uint32_t P17:1; /**< bit: 17 Input Change Interrupt Status */ + uint32_t P18:1; /**< bit: 18 Input Change Interrupt Status */ + uint32_t P19:1; /**< bit: 19 Input Change Interrupt Status */ + uint32_t P20:1; /**< bit: 20 Input Change Interrupt Status */ + uint32_t P21:1; /**< bit: 21 Input Change Interrupt Status */ + uint32_t P22:1; /**< bit: 22 Input Change Interrupt Status */ + uint32_t P23:1; /**< bit: 23 Input Change Interrupt Status */ + uint32_t P24:1; /**< bit: 24 Input Change Interrupt Status */ + uint32_t P25:1; /**< bit: 25 Input Change Interrupt Status */ + uint32_t P26:1; /**< bit: 26 Input Change Interrupt Status */ + uint32_t P27:1; /**< bit: 27 Input Change Interrupt Status */ + uint32_t P28:1; /**< bit: 28 Input Change Interrupt Status */ + uint32_t P29:1; /**< bit: 29 Input Change Interrupt Status */ + uint32_t P30:1; /**< bit: 30 Input Change Interrupt Status */ + uint32_t P31:1; /**< bit: 31 Input Change Interrupt Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Input Change Interrupt Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ISR_OFFSET (0x4C) /**< (PIO_ISR) Interrupt Status Register Offset */ + +#define PIO_ISR_P0_Pos 0 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P0_Msk (_U_(0x1) << PIO_ISR_P0_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P0 PIO_ISR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P0_Msk instead */ +#define PIO_ISR_P1_Pos 1 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P1_Msk (_U_(0x1) << PIO_ISR_P1_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P1 PIO_ISR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P1_Msk instead */ +#define PIO_ISR_P2_Pos 2 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P2_Msk (_U_(0x1) << PIO_ISR_P2_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P2 PIO_ISR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P2_Msk instead */ +#define PIO_ISR_P3_Pos 3 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P3_Msk (_U_(0x1) << PIO_ISR_P3_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P3 PIO_ISR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P3_Msk instead */ +#define PIO_ISR_P4_Pos 4 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P4_Msk (_U_(0x1) << PIO_ISR_P4_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P4 PIO_ISR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P4_Msk instead */ +#define PIO_ISR_P5_Pos 5 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P5_Msk (_U_(0x1) << PIO_ISR_P5_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P5 PIO_ISR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P5_Msk instead */ +#define PIO_ISR_P6_Pos 6 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P6_Msk (_U_(0x1) << PIO_ISR_P6_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P6 PIO_ISR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P6_Msk instead */ +#define PIO_ISR_P7_Pos 7 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P7_Msk (_U_(0x1) << PIO_ISR_P7_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P7 PIO_ISR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P7_Msk instead */ +#define PIO_ISR_P8_Pos 8 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P8_Msk (_U_(0x1) << PIO_ISR_P8_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P8 PIO_ISR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P8_Msk instead */ +#define PIO_ISR_P9_Pos 9 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P9_Msk (_U_(0x1) << PIO_ISR_P9_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P9 PIO_ISR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P9_Msk instead */ +#define PIO_ISR_P10_Pos 10 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P10_Msk (_U_(0x1) << PIO_ISR_P10_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P10 PIO_ISR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P10_Msk instead */ +#define PIO_ISR_P11_Pos 11 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P11_Msk (_U_(0x1) << PIO_ISR_P11_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P11 PIO_ISR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P11_Msk instead */ +#define PIO_ISR_P12_Pos 12 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P12_Msk (_U_(0x1) << PIO_ISR_P12_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P12 PIO_ISR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P12_Msk instead */ +#define PIO_ISR_P13_Pos 13 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P13_Msk (_U_(0x1) << PIO_ISR_P13_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P13 PIO_ISR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P13_Msk instead */ +#define PIO_ISR_P14_Pos 14 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P14_Msk (_U_(0x1) << PIO_ISR_P14_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P14 PIO_ISR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P14_Msk instead */ +#define PIO_ISR_P15_Pos 15 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P15_Msk (_U_(0x1) << PIO_ISR_P15_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P15 PIO_ISR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P15_Msk instead */ +#define PIO_ISR_P16_Pos 16 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P16_Msk (_U_(0x1) << PIO_ISR_P16_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P16 PIO_ISR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P16_Msk instead */ +#define PIO_ISR_P17_Pos 17 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P17_Msk (_U_(0x1) << PIO_ISR_P17_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P17 PIO_ISR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P17_Msk instead */ +#define PIO_ISR_P18_Pos 18 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P18_Msk (_U_(0x1) << PIO_ISR_P18_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P18 PIO_ISR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P18_Msk instead */ +#define PIO_ISR_P19_Pos 19 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P19_Msk (_U_(0x1) << PIO_ISR_P19_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P19 PIO_ISR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P19_Msk instead */ +#define PIO_ISR_P20_Pos 20 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P20_Msk (_U_(0x1) << PIO_ISR_P20_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P20 PIO_ISR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P20_Msk instead */ +#define PIO_ISR_P21_Pos 21 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P21_Msk (_U_(0x1) << PIO_ISR_P21_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P21 PIO_ISR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P21_Msk instead */ +#define PIO_ISR_P22_Pos 22 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P22_Msk (_U_(0x1) << PIO_ISR_P22_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P22 PIO_ISR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P22_Msk instead */ +#define PIO_ISR_P23_Pos 23 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P23_Msk (_U_(0x1) << PIO_ISR_P23_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P23 PIO_ISR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P23_Msk instead */ +#define PIO_ISR_P24_Pos 24 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P24_Msk (_U_(0x1) << PIO_ISR_P24_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P24 PIO_ISR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P24_Msk instead */ +#define PIO_ISR_P25_Pos 25 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P25_Msk (_U_(0x1) << PIO_ISR_P25_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P25 PIO_ISR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P25_Msk instead */ +#define PIO_ISR_P26_Pos 26 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P26_Msk (_U_(0x1) << PIO_ISR_P26_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P26 PIO_ISR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P26_Msk instead */ +#define PIO_ISR_P27_Pos 27 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P27_Msk (_U_(0x1) << PIO_ISR_P27_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P27 PIO_ISR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P27_Msk instead */ +#define PIO_ISR_P28_Pos 28 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P28_Msk (_U_(0x1) << PIO_ISR_P28_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P28 PIO_ISR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P28_Msk instead */ +#define PIO_ISR_P29_Pos 29 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P29_Msk (_U_(0x1) << PIO_ISR_P29_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P29 PIO_ISR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P29_Msk instead */ +#define PIO_ISR_P30_Pos 30 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P30_Msk (_U_(0x1) << PIO_ISR_P30_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P30 PIO_ISR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P30_Msk instead */ +#define PIO_ISR_P31_Pos 31 /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P31_Msk (_U_(0x1) << PIO_ISR_P31_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P31 PIO_ISR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ISR_P31_Msk instead */ +#define PIO_ISR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ISR) Register MASK (Use PIO_ISR_Msk instead) */ +#define PIO_ISR_Msk _U_(0xFFFFFFFF) /**< (PIO_ISR) Register Mask */ + +#define PIO_ISR_P_Pos 0 /**< (PIO_ISR Position) Input Change Interrupt Status */ +#define PIO_ISR_P_Msk (_U_(0xFFFFFFFF) << PIO_ISR_P_Pos) /**< (PIO_ISR Mask) P */ +#define PIO_ISR_P(value) (PIO_ISR_P_Msk & ((value) << PIO_ISR_P_Pos)) + +/* -------- PIO_MDER : (PIO Offset: 0x50) (/W 32) Multi-driver Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Multi-drive Enable */ + uint32_t P1:1; /**< bit: 1 Multi-drive Enable */ + uint32_t P2:1; /**< bit: 2 Multi-drive Enable */ + uint32_t P3:1; /**< bit: 3 Multi-drive Enable */ + uint32_t P4:1; /**< bit: 4 Multi-drive Enable */ + uint32_t P5:1; /**< bit: 5 Multi-drive Enable */ + uint32_t P6:1; /**< bit: 6 Multi-drive Enable */ + uint32_t P7:1; /**< bit: 7 Multi-drive Enable */ + uint32_t P8:1; /**< bit: 8 Multi-drive Enable */ + uint32_t P9:1; /**< bit: 9 Multi-drive Enable */ + uint32_t P10:1; /**< bit: 10 Multi-drive Enable */ + uint32_t P11:1; /**< bit: 11 Multi-drive Enable */ + uint32_t P12:1; /**< bit: 12 Multi-drive Enable */ + uint32_t P13:1; /**< bit: 13 Multi-drive Enable */ + uint32_t P14:1; /**< bit: 14 Multi-drive Enable */ + uint32_t P15:1; /**< bit: 15 Multi-drive Enable */ + uint32_t P16:1; /**< bit: 16 Multi-drive Enable */ + uint32_t P17:1; /**< bit: 17 Multi-drive Enable */ + uint32_t P18:1; /**< bit: 18 Multi-drive Enable */ + uint32_t P19:1; /**< bit: 19 Multi-drive Enable */ + uint32_t P20:1; /**< bit: 20 Multi-drive Enable */ + uint32_t P21:1; /**< bit: 21 Multi-drive Enable */ + uint32_t P22:1; /**< bit: 22 Multi-drive Enable */ + uint32_t P23:1; /**< bit: 23 Multi-drive Enable */ + uint32_t P24:1; /**< bit: 24 Multi-drive Enable */ + uint32_t P25:1; /**< bit: 25 Multi-drive Enable */ + uint32_t P26:1; /**< bit: 26 Multi-drive Enable */ + uint32_t P27:1; /**< bit: 27 Multi-drive Enable */ + uint32_t P28:1; /**< bit: 28 Multi-drive Enable */ + uint32_t P29:1; /**< bit: 29 Multi-drive Enable */ + uint32_t P30:1; /**< bit: 30 Multi-drive Enable */ + uint32_t P31:1; /**< bit: 31 Multi-drive Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Multi-drive Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_MDER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_MDER_OFFSET (0x50) /**< (PIO_MDER) Multi-driver Enable Register Offset */ + +#define PIO_MDER_P0_Pos 0 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P0_Msk (_U_(0x1) << PIO_MDER_P0_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P0 PIO_MDER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P0_Msk instead */ +#define PIO_MDER_P1_Pos 1 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P1_Msk (_U_(0x1) << PIO_MDER_P1_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P1 PIO_MDER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P1_Msk instead */ +#define PIO_MDER_P2_Pos 2 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P2_Msk (_U_(0x1) << PIO_MDER_P2_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P2 PIO_MDER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P2_Msk instead */ +#define PIO_MDER_P3_Pos 3 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P3_Msk (_U_(0x1) << PIO_MDER_P3_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P3 PIO_MDER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P3_Msk instead */ +#define PIO_MDER_P4_Pos 4 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P4_Msk (_U_(0x1) << PIO_MDER_P4_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P4 PIO_MDER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P4_Msk instead */ +#define PIO_MDER_P5_Pos 5 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P5_Msk (_U_(0x1) << PIO_MDER_P5_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P5 PIO_MDER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P5_Msk instead */ +#define PIO_MDER_P6_Pos 6 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P6_Msk (_U_(0x1) << PIO_MDER_P6_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P6 PIO_MDER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P6_Msk instead */ +#define PIO_MDER_P7_Pos 7 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P7_Msk (_U_(0x1) << PIO_MDER_P7_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P7 PIO_MDER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P7_Msk instead */ +#define PIO_MDER_P8_Pos 8 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P8_Msk (_U_(0x1) << PIO_MDER_P8_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P8 PIO_MDER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P8_Msk instead */ +#define PIO_MDER_P9_Pos 9 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P9_Msk (_U_(0x1) << PIO_MDER_P9_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P9 PIO_MDER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P9_Msk instead */ +#define PIO_MDER_P10_Pos 10 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P10_Msk (_U_(0x1) << PIO_MDER_P10_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P10 PIO_MDER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P10_Msk instead */ +#define PIO_MDER_P11_Pos 11 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P11_Msk (_U_(0x1) << PIO_MDER_P11_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P11 PIO_MDER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P11_Msk instead */ +#define PIO_MDER_P12_Pos 12 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P12_Msk (_U_(0x1) << PIO_MDER_P12_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P12 PIO_MDER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P12_Msk instead */ +#define PIO_MDER_P13_Pos 13 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P13_Msk (_U_(0x1) << PIO_MDER_P13_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P13 PIO_MDER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P13_Msk instead */ +#define PIO_MDER_P14_Pos 14 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P14_Msk (_U_(0x1) << PIO_MDER_P14_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P14 PIO_MDER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P14_Msk instead */ +#define PIO_MDER_P15_Pos 15 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P15_Msk (_U_(0x1) << PIO_MDER_P15_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P15 PIO_MDER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P15_Msk instead */ +#define PIO_MDER_P16_Pos 16 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P16_Msk (_U_(0x1) << PIO_MDER_P16_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P16 PIO_MDER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P16_Msk instead */ +#define PIO_MDER_P17_Pos 17 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P17_Msk (_U_(0x1) << PIO_MDER_P17_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P17 PIO_MDER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P17_Msk instead */ +#define PIO_MDER_P18_Pos 18 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P18_Msk (_U_(0x1) << PIO_MDER_P18_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P18 PIO_MDER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P18_Msk instead */ +#define PIO_MDER_P19_Pos 19 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P19_Msk (_U_(0x1) << PIO_MDER_P19_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P19 PIO_MDER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P19_Msk instead */ +#define PIO_MDER_P20_Pos 20 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P20_Msk (_U_(0x1) << PIO_MDER_P20_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P20 PIO_MDER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P20_Msk instead */ +#define PIO_MDER_P21_Pos 21 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P21_Msk (_U_(0x1) << PIO_MDER_P21_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P21 PIO_MDER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P21_Msk instead */ +#define PIO_MDER_P22_Pos 22 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P22_Msk (_U_(0x1) << PIO_MDER_P22_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P22 PIO_MDER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P22_Msk instead */ +#define PIO_MDER_P23_Pos 23 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P23_Msk (_U_(0x1) << PIO_MDER_P23_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P23 PIO_MDER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P23_Msk instead */ +#define PIO_MDER_P24_Pos 24 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P24_Msk (_U_(0x1) << PIO_MDER_P24_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P24 PIO_MDER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P24_Msk instead */ +#define PIO_MDER_P25_Pos 25 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P25_Msk (_U_(0x1) << PIO_MDER_P25_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P25 PIO_MDER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P25_Msk instead */ +#define PIO_MDER_P26_Pos 26 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P26_Msk (_U_(0x1) << PIO_MDER_P26_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P26 PIO_MDER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P26_Msk instead */ +#define PIO_MDER_P27_Pos 27 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P27_Msk (_U_(0x1) << PIO_MDER_P27_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P27 PIO_MDER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P27_Msk instead */ +#define PIO_MDER_P28_Pos 28 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P28_Msk (_U_(0x1) << PIO_MDER_P28_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P28 PIO_MDER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P28_Msk instead */ +#define PIO_MDER_P29_Pos 29 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P29_Msk (_U_(0x1) << PIO_MDER_P29_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P29 PIO_MDER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P29_Msk instead */ +#define PIO_MDER_P30_Pos 30 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P30_Msk (_U_(0x1) << PIO_MDER_P30_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P30 PIO_MDER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P30_Msk instead */ +#define PIO_MDER_P31_Pos 31 /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P31_Msk (_U_(0x1) << PIO_MDER_P31_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P31 PIO_MDER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDER_P31_Msk instead */ +#define PIO_MDER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDER) Register MASK (Use PIO_MDER_Msk instead) */ +#define PIO_MDER_Msk _U_(0xFFFFFFFF) /**< (PIO_MDER) Register Mask */ + +#define PIO_MDER_P_Pos 0 /**< (PIO_MDER Position) Multi-drive Enable */ +#define PIO_MDER_P_Msk (_U_(0xFFFFFFFF) << PIO_MDER_P_Pos) /**< (PIO_MDER Mask) P */ +#define PIO_MDER_P(value) (PIO_MDER_P_Msk & ((value) << PIO_MDER_P_Pos)) + +/* -------- PIO_MDDR : (PIO Offset: 0x54) (/W 32) Multi-driver Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Multi-drive Disable */ + uint32_t P1:1; /**< bit: 1 Multi-drive Disable */ + uint32_t P2:1; /**< bit: 2 Multi-drive Disable */ + uint32_t P3:1; /**< bit: 3 Multi-drive Disable */ + uint32_t P4:1; /**< bit: 4 Multi-drive Disable */ + uint32_t P5:1; /**< bit: 5 Multi-drive Disable */ + uint32_t P6:1; /**< bit: 6 Multi-drive Disable */ + uint32_t P7:1; /**< bit: 7 Multi-drive Disable */ + uint32_t P8:1; /**< bit: 8 Multi-drive Disable */ + uint32_t P9:1; /**< bit: 9 Multi-drive Disable */ + uint32_t P10:1; /**< bit: 10 Multi-drive Disable */ + uint32_t P11:1; /**< bit: 11 Multi-drive Disable */ + uint32_t P12:1; /**< bit: 12 Multi-drive Disable */ + uint32_t P13:1; /**< bit: 13 Multi-drive Disable */ + uint32_t P14:1; /**< bit: 14 Multi-drive Disable */ + uint32_t P15:1; /**< bit: 15 Multi-drive Disable */ + uint32_t P16:1; /**< bit: 16 Multi-drive Disable */ + uint32_t P17:1; /**< bit: 17 Multi-drive Disable */ + uint32_t P18:1; /**< bit: 18 Multi-drive Disable */ + uint32_t P19:1; /**< bit: 19 Multi-drive Disable */ + uint32_t P20:1; /**< bit: 20 Multi-drive Disable */ + uint32_t P21:1; /**< bit: 21 Multi-drive Disable */ + uint32_t P22:1; /**< bit: 22 Multi-drive Disable */ + uint32_t P23:1; /**< bit: 23 Multi-drive Disable */ + uint32_t P24:1; /**< bit: 24 Multi-drive Disable */ + uint32_t P25:1; /**< bit: 25 Multi-drive Disable */ + uint32_t P26:1; /**< bit: 26 Multi-drive Disable */ + uint32_t P27:1; /**< bit: 27 Multi-drive Disable */ + uint32_t P28:1; /**< bit: 28 Multi-drive Disable */ + uint32_t P29:1; /**< bit: 29 Multi-drive Disable */ + uint32_t P30:1; /**< bit: 30 Multi-drive Disable */ + uint32_t P31:1; /**< bit: 31 Multi-drive Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Multi-drive Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_MDDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_MDDR_OFFSET (0x54) /**< (PIO_MDDR) Multi-driver Disable Register Offset */ + +#define PIO_MDDR_P0_Pos 0 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P0_Msk (_U_(0x1) << PIO_MDDR_P0_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P0 PIO_MDDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P0_Msk instead */ +#define PIO_MDDR_P1_Pos 1 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P1_Msk (_U_(0x1) << PIO_MDDR_P1_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P1 PIO_MDDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P1_Msk instead */ +#define PIO_MDDR_P2_Pos 2 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P2_Msk (_U_(0x1) << PIO_MDDR_P2_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P2 PIO_MDDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P2_Msk instead */ +#define PIO_MDDR_P3_Pos 3 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P3_Msk (_U_(0x1) << PIO_MDDR_P3_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P3 PIO_MDDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P3_Msk instead */ +#define PIO_MDDR_P4_Pos 4 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P4_Msk (_U_(0x1) << PIO_MDDR_P4_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P4 PIO_MDDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P4_Msk instead */ +#define PIO_MDDR_P5_Pos 5 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P5_Msk (_U_(0x1) << PIO_MDDR_P5_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P5 PIO_MDDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P5_Msk instead */ +#define PIO_MDDR_P6_Pos 6 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P6_Msk (_U_(0x1) << PIO_MDDR_P6_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P6 PIO_MDDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P6_Msk instead */ +#define PIO_MDDR_P7_Pos 7 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P7_Msk (_U_(0x1) << PIO_MDDR_P7_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P7 PIO_MDDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P7_Msk instead */ +#define PIO_MDDR_P8_Pos 8 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P8_Msk (_U_(0x1) << PIO_MDDR_P8_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P8 PIO_MDDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P8_Msk instead */ +#define PIO_MDDR_P9_Pos 9 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P9_Msk (_U_(0x1) << PIO_MDDR_P9_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P9 PIO_MDDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P9_Msk instead */ +#define PIO_MDDR_P10_Pos 10 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P10_Msk (_U_(0x1) << PIO_MDDR_P10_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P10 PIO_MDDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P10_Msk instead */ +#define PIO_MDDR_P11_Pos 11 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P11_Msk (_U_(0x1) << PIO_MDDR_P11_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P11 PIO_MDDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P11_Msk instead */ +#define PIO_MDDR_P12_Pos 12 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P12_Msk (_U_(0x1) << PIO_MDDR_P12_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P12 PIO_MDDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P12_Msk instead */ +#define PIO_MDDR_P13_Pos 13 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P13_Msk (_U_(0x1) << PIO_MDDR_P13_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P13 PIO_MDDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P13_Msk instead */ +#define PIO_MDDR_P14_Pos 14 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P14_Msk (_U_(0x1) << PIO_MDDR_P14_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P14 PIO_MDDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P14_Msk instead */ +#define PIO_MDDR_P15_Pos 15 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P15_Msk (_U_(0x1) << PIO_MDDR_P15_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P15 PIO_MDDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P15_Msk instead */ +#define PIO_MDDR_P16_Pos 16 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P16_Msk (_U_(0x1) << PIO_MDDR_P16_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P16 PIO_MDDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P16_Msk instead */ +#define PIO_MDDR_P17_Pos 17 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P17_Msk (_U_(0x1) << PIO_MDDR_P17_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P17 PIO_MDDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P17_Msk instead */ +#define PIO_MDDR_P18_Pos 18 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P18_Msk (_U_(0x1) << PIO_MDDR_P18_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P18 PIO_MDDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P18_Msk instead */ +#define PIO_MDDR_P19_Pos 19 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P19_Msk (_U_(0x1) << PIO_MDDR_P19_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P19 PIO_MDDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P19_Msk instead */ +#define PIO_MDDR_P20_Pos 20 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P20_Msk (_U_(0x1) << PIO_MDDR_P20_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P20 PIO_MDDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P20_Msk instead */ +#define PIO_MDDR_P21_Pos 21 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P21_Msk (_U_(0x1) << PIO_MDDR_P21_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P21 PIO_MDDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P21_Msk instead */ +#define PIO_MDDR_P22_Pos 22 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P22_Msk (_U_(0x1) << PIO_MDDR_P22_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P22 PIO_MDDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P22_Msk instead */ +#define PIO_MDDR_P23_Pos 23 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P23_Msk (_U_(0x1) << PIO_MDDR_P23_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P23 PIO_MDDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P23_Msk instead */ +#define PIO_MDDR_P24_Pos 24 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P24_Msk (_U_(0x1) << PIO_MDDR_P24_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P24 PIO_MDDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P24_Msk instead */ +#define PIO_MDDR_P25_Pos 25 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P25_Msk (_U_(0x1) << PIO_MDDR_P25_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P25 PIO_MDDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P25_Msk instead */ +#define PIO_MDDR_P26_Pos 26 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P26_Msk (_U_(0x1) << PIO_MDDR_P26_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P26 PIO_MDDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P26_Msk instead */ +#define PIO_MDDR_P27_Pos 27 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P27_Msk (_U_(0x1) << PIO_MDDR_P27_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P27 PIO_MDDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P27_Msk instead */ +#define PIO_MDDR_P28_Pos 28 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P28_Msk (_U_(0x1) << PIO_MDDR_P28_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P28 PIO_MDDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P28_Msk instead */ +#define PIO_MDDR_P29_Pos 29 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P29_Msk (_U_(0x1) << PIO_MDDR_P29_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P29 PIO_MDDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P29_Msk instead */ +#define PIO_MDDR_P30_Pos 30 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P30_Msk (_U_(0x1) << PIO_MDDR_P30_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P30 PIO_MDDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P30_Msk instead */ +#define PIO_MDDR_P31_Pos 31 /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P31_Msk (_U_(0x1) << PIO_MDDR_P31_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P31 PIO_MDDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDDR_P31_Msk instead */ +#define PIO_MDDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDDR) Register MASK (Use PIO_MDDR_Msk instead) */ +#define PIO_MDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDDR) Register Mask */ + +#define PIO_MDDR_P_Pos 0 /**< (PIO_MDDR Position) Multi-drive Disable */ +#define PIO_MDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDDR_P_Pos) /**< (PIO_MDDR Mask) P */ +#define PIO_MDDR_P(value) (PIO_MDDR_P_Msk & ((value) << PIO_MDDR_P_Pos)) + +/* -------- PIO_MDSR : (PIO Offset: 0x58) (R/ 32) Multi-driver Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Multi-drive Status */ + uint32_t P1:1; /**< bit: 1 Multi-drive Status */ + uint32_t P2:1; /**< bit: 2 Multi-drive Status */ + uint32_t P3:1; /**< bit: 3 Multi-drive Status */ + uint32_t P4:1; /**< bit: 4 Multi-drive Status */ + uint32_t P5:1; /**< bit: 5 Multi-drive Status */ + uint32_t P6:1; /**< bit: 6 Multi-drive Status */ + uint32_t P7:1; /**< bit: 7 Multi-drive Status */ + uint32_t P8:1; /**< bit: 8 Multi-drive Status */ + uint32_t P9:1; /**< bit: 9 Multi-drive Status */ + uint32_t P10:1; /**< bit: 10 Multi-drive Status */ + uint32_t P11:1; /**< bit: 11 Multi-drive Status */ + uint32_t P12:1; /**< bit: 12 Multi-drive Status */ + uint32_t P13:1; /**< bit: 13 Multi-drive Status */ + uint32_t P14:1; /**< bit: 14 Multi-drive Status */ + uint32_t P15:1; /**< bit: 15 Multi-drive Status */ + uint32_t P16:1; /**< bit: 16 Multi-drive Status */ + uint32_t P17:1; /**< bit: 17 Multi-drive Status */ + uint32_t P18:1; /**< bit: 18 Multi-drive Status */ + uint32_t P19:1; /**< bit: 19 Multi-drive Status */ + uint32_t P20:1; /**< bit: 20 Multi-drive Status */ + uint32_t P21:1; /**< bit: 21 Multi-drive Status */ + uint32_t P22:1; /**< bit: 22 Multi-drive Status */ + uint32_t P23:1; /**< bit: 23 Multi-drive Status */ + uint32_t P24:1; /**< bit: 24 Multi-drive Status */ + uint32_t P25:1; /**< bit: 25 Multi-drive Status */ + uint32_t P26:1; /**< bit: 26 Multi-drive Status */ + uint32_t P27:1; /**< bit: 27 Multi-drive Status */ + uint32_t P28:1; /**< bit: 28 Multi-drive Status */ + uint32_t P29:1; /**< bit: 29 Multi-drive Status */ + uint32_t P30:1; /**< bit: 30 Multi-drive Status */ + uint32_t P31:1; /**< bit: 31 Multi-drive Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Multi-drive Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_MDSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_MDSR_OFFSET (0x58) /**< (PIO_MDSR) Multi-driver Status Register Offset */ + +#define PIO_MDSR_P0_Pos 0 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P0_Msk (_U_(0x1) << PIO_MDSR_P0_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P0 PIO_MDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P0_Msk instead */ +#define PIO_MDSR_P1_Pos 1 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P1_Msk (_U_(0x1) << PIO_MDSR_P1_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P1 PIO_MDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P1_Msk instead */ +#define PIO_MDSR_P2_Pos 2 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P2_Msk (_U_(0x1) << PIO_MDSR_P2_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P2 PIO_MDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P2_Msk instead */ +#define PIO_MDSR_P3_Pos 3 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P3_Msk (_U_(0x1) << PIO_MDSR_P3_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P3 PIO_MDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P3_Msk instead */ +#define PIO_MDSR_P4_Pos 4 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P4_Msk (_U_(0x1) << PIO_MDSR_P4_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P4 PIO_MDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P4_Msk instead */ +#define PIO_MDSR_P5_Pos 5 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P5_Msk (_U_(0x1) << PIO_MDSR_P5_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P5 PIO_MDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P5_Msk instead */ +#define PIO_MDSR_P6_Pos 6 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P6_Msk (_U_(0x1) << PIO_MDSR_P6_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P6 PIO_MDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P6_Msk instead */ +#define PIO_MDSR_P7_Pos 7 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P7_Msk (_U_(0x1) << PIO_MDSR_P7_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P7 PIO_MDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P7_Msk instead */ +#define PIO_MDSR_P8_Pos 8 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P8_Msk (_U_(0x1) << PIO_MDSR_P8_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P8 PIO_MDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P8_Msk instead */ +#define PIO_MDSR_P9_Pos 9 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P9_Msk (_U_(0x1) << PIO_MDSR_P9_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P9 PIO_MDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P9_Msk instead */ +#define PIO_MDSR_P10_Pos 10 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P10_Msk (_U_(0x1) << PIO_MDSR_P10_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P10 PIO_MDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P10_Msk instead */ +#define PIO_MDSR_P11_Pos 11 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P11_Msk (_U_(0x1) << PIO_MDSR_P11_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P11 PIO_MDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P11_Msk instead */ +#define PIO_MDSR_P12_Pos 12 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P12_Msk (_U_(0x1) << PIO_MDSR_P12_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P12 PIO_MDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P12_Msk instead */ +#define PIO_MDSR_P13_Pos 13 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P13_Msk (_U_(0x1) << PIO_MDSR_P13_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P13 PIO_MDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P13_Msk instead */ +#define PIO_MDSR_P14_Pos 14 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P14_Msk (_U_(0x1) << PIO_MDSR_P14_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P14 PIO_MDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P14_Msk instead */ +#define PIO_MDSR_P15_Pos 15 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P15_Msk (_U_(0x1) << PIO_MDSR_P15_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P15 PIO_MDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P15_Msk instead */ +#define PIO_MDSR_P16_Pos 16 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P16_Msk (_U_(0x1) << PIO_MDSR_P16_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P16 PIO_MDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P16_Msk instead */ +#define PIO_MDSR_P17_Pos 17 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P17_Msk (_U_(0x1) << PIO_MDSR_P17_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P17 PIO_MDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P17_Msk instead */ +#define PIO_MDSR_P18_Pos 18 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P18_Msk (_U_(0x1) << PIO_MDSR_P18_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P18 PIO_MDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P18_Msk instead */ +#define PIO_MDSR_P19_Pos 19 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P19_Msk (_U_(0x1) << PIO_MDSR_P19_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P19 PIO_MDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P19_Msk instead */ +#define PIO_MDSR_P20_Pos 20 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P20_Msk (_U_(0x1) << PIO_MDSR_P20_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P20 PIO_MDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P20_Msk instead */ +#define PIO_MDSR_P21_Pos 21 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P21_Msk (_U_(0x1) << PIO_MDSR_P21_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P21 PIO_MDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P21_Msk instead */ +#define PIO_MDSR_P22_Pos 22 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P22_Msk (_U_(0x1) << PIO_MDSR_P22_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P22 PIO_MDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P22_Msk instead */ +#define PIO_MDSR_P23_Pos 23 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P23_Msk (_U_(0x1) << PIO_MDSR_P23_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P23 PIO_MDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P23_Msk instead */ +#define PIO_MDSR_P24_Pos 24 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P24_Msk (_U_(0x1) << PIO_MDSR_P24_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P24 PIO_MDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P24_Msk instead */ +#define PIO_MDSR_P25_Pos 25 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P25_Msk (_U_(0x1) << PIO_MDSR_P25_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P25 PIO_MDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P25_Msk instead */ +#define PIO_MDSR_P26_Pos 26 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P26_Msk (_U_(0x1) << PIO_MDSR_P26_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P26 PIO_MDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P26_Msk instead */ +#define PIO_MDSR_P27_Pos 27 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P27_Msk (_U_(0x1) << PIO_MDSR_P27_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P27 PIO_MDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P27_Msk instead */ +#define PIO_MDSR_P28_Pos 28 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P28_Msk (_U_(0x1) << PIO_MDSR_P28_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P28 PIO_MDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P28_Msk instead */ +#define PIO_MDSR_P29_Pos 29 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P29_Msk (_U_(0x1) << PIO_MDSR_P29_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P29 PIO_MDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P29_Msk instead */ +#define PIO_MDSR_P30_Pos 30 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P30_Msk (_U_(0x1) << PIO_MDSR_P30_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P30 PIO_MDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P30_Msk instead */ +#define PIO_MDSR_P31_Pos 31 /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P31_Msk (_U_(0x1) << PIO_MDSR_P31_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P31 PIO_MDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_MDSR_P31_Msk instead */ +#define PIO_MDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_MDSR) Register MASK (Use PIO_MDSR_Msk instead) */ +#define PIO_MDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDSR) Register Mask */ + +#define PIO_MDSR_P_Pos 0 /**< (PIO_MDSR Position) Multi-drive Status */ +#define PIO_MDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDSR_P_Pos) /**< (PIO_MDSR Mask) P */ +#define PIO_MDSR_P(value) (PIO_MDSR_P_Msk & ((value) << PIO_MDSR_P_Pos)) + +/* -------- PIO_PUDR : (PIO Offset: 0x60) (/W 32) Pull-up Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Up Disable */ + uint32_t P1:1; /**< bit: 1 Pull-Up Disable */ + uint32_t P2:1; /**< bit: 2 Pull-Up Disable */ + uint32_t P3:1; /**< bit: 3 Pull-Up Disable */ + uint32_t P4:1; /**< bit: 4 Pull-Up Disable */ + uint32_t P5:1; /**< bit: 5 Pull-Up Disable */ + uint32_t P6:1; /**< bit: 6 Pull-Up Disable */ + uint32_t P7:1; /**< bit: 7 Pull-Up Disable */ + uint32_t P8:1; /**< bit: 8 Pull-Up Disable */ + uint32_t P9:1; /**< bit: 9 Pull-Up Disable */ + uint32_t P10:1; /**< bit: 10 Pull-Up Disable */ + uint32_t P11:1; /**< bit: 11 Pull-Up Disable */ + uint32_t P12:1; /**< bit: 12 Pull-Up Disable */ + uint32_t P13:1; /**< bit: 13 Pull-Up Disable */ + uint32_t P14:1; /**< bit: 14 Pull-Up Disable */ + uint32_t P15:1; /**< bit: 15 Pull-Up Disable */ + uint32_t P16:1; /**< bit: 16 Pull-Up Disable */ + uint32_t P17:1; /**< bit: 17 Pull-Up Disable */ + uint32_t P18:1; /**< bit: 18 Pull-Up Disable */ + uint32_t P19:1; /**< bit: 19 Pull-Up Disable */ + uint32_t P20:1; /**< bit: 20 Pull-Up Disable */ + uint32_t P21:1; /**< bit: 21 Pull-Up Disable */ + uint32_t P22:1; /**< bit: 22 Pull-Up Disable */ + uint32_t P23:1; /**< bit: 23 Pull-Up Disable */ + uint32_t P24:1; /**< bit: 24 Pull-Up Disable */ + uint32_t P25:1; /**< bit: 25 Pull-Up Disable */ + uint32_t P26:1; /**< bit: 26 Pull-Up Disable */ + uint32_t P27:1; /**< bit: 27 Pull-Up Disable */ + uint32_t P28:1; /**< bit: 28 Pull-Up Disable */ + uint32_t P29:1; /**< bit: 29 Pull-Up Disable */ + uint32_t P30:1; /**< bit: 30 Pull-Up Disable */ + uint32_t P31:1; /**< bit: 31 Pull-Up Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Up Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PUDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PUDR_OFFSET (0x60) /**< (PIO_PUDR) Pull-up Disable Register Offset */ + +#define PIO_PUDR_P0_Pos 0 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P0_Msk (_U_(0x1) << PIO_PUDR_P0_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P0 PIO_PUDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P0_Msk instead */ +#define PIO_PUDR_P1_Pos 1 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P1_Msk (_U_(0x1) << PIO_PUDR_P1_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P1 PIO_PUDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P1_Msk instead */ +#define PIO_PUDR_P2_Pos 2 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P2_Msk (_U_(0x1) << PIO_PUDR_P2_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P2 PIO_PUDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P2_Msk instead */ +#define PIO_PUDR_P3_Pos 3 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P3_Msk (_U_(0x1) << PIO_PUDR_P3_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P3 PIO_PUDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P3_Msk instead */ +#define PIO_PUDR_P4_Pos 4 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P4_Msk (_U_(0x1) << PIO_PUDR_P4_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P4 PIO_PUDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P4_Msk instead */ +#define PIO_PUDR_P5_Pos 5 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P5_Msk (_U_(0x1) << PIO_PUDR_P5_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P5 PIO_PUDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P5_Msk instead */ +#define PIO_PUDR_P6_Pos 6 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P6_Msk (_U_(0x1) << PIO_PUDR_P6_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P6 PIO_PUDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P6_Msk instead */ +#define PIO_PUDR_P7_Pos 7 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P7_Msk (_U_(0x1) << PIO_PUDR_P7_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P7 PIO_PUDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P7_Msk instead */ +#define PIO_PUDR_P8_Pos 8 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P8_Msk (_U_(0x1) << PIO_PUDR_P8_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P8 PIO_PUDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P8_Msk instead */ +#define PIO_PUDR_P9_Pos 9 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P9_Msk (_U_(0x1) << PIO_PUDR_P9_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P9 PIO_PUDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P9_Msk instead */ +#define PIO_PUDR_P10_Pos 10 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P10_Msk (_U_(0x1) << PIO_PUDR_P10_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P10 PIO_PUDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P10_Msk instead */ +#define PIO_PUDR_P11_Pos 11 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P11_Msk (_U_(0x1) << PIO_PUDR_P11_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P11 PIO_PUDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P11_Msk instead */ +#define PIO_PUDR_P12_Pos 12 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P12_Msk (_U_(0x1) << PIO_PUDR_P12_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P12 PIO_PUDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P12_Msk instead */ +#define PIO_PUDR_P13_Pos 13 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P13_Msk (_U_(0x1) << PIO_PUDR_P13_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P13 PIO_PUDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P13_Msk instead */ +#define PIO_PUDR_P14_Pos 14 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P14_Msk (_U_(0x1) << PIO_PUDR_P14_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P14 PIO_PUDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P14_Msk instead */ +#define PIO_PUDR_P15_Pos 15 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P15_Msk (_U_(0x1) << PIO_PUDR_P15_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P15 PIO_PUDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P15_Msk instead */ +#define PIO_PUDR_P16_Pos 16 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P16_Msk (_U_(0x1) << PIO_PUDR_P16_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P16 PIO_PUDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P16_Msk instead */ +#define PIO_PUDR_P17_Pos 17 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P17_Msk (_U_(0x1) << PIO_PUDR_P17_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P17 PIO_PUDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P17_Msk instead */ +#define PIO_PUDR_P18_Pos 18 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P18_Msk (_U_(0x1) << PIO_PUDR_P18_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P18 PIO_PUDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P18_Msk instead */ +#define PIO_PUDR_P19_Pos 19 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P19_Msk (_U_(0x1) << PIO_PUDR_P19_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P19 PIO_PUDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P19_Msk instead */ +#define PIO_PUDR_P20_Pos 20 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P20_Msk (_U_(0x1) << PIO_PUDR_P20_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P20 PIO_PUDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P20_Msk instead */ +#define PIO_PUDR_P21_Pos 21 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P21_Msk (_U_(0x1) << PIO_PUDR_P21_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P21 PIO_PUDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P21_Msk instead */ +#define PIO_PUDR_P22_Pos 22 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P22_Msk (_U_(0x1) << PIO_PUDR_P22_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P22 PIO_PUDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P22_Msk instead */ +#define PIO_PUDR_P23_Pos 23 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P23_Msk (_U_(0x1) << PIO_PUDR_P23_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P23 PIO_PUDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P23_Msk instead */ +#define PIO_PUDR_P24_Pos 24 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P24_Msk (_U_(0x1) << PIO_PUDR_P24_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P24 PIO_PUDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P24_Msk instead */ +#define PIO_PUDR_P25_Pos 25 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P25_Msk (_U_(0x1) << PIO_PUDR_P25_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P25 PIO_PUDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P25_Msk instead */ +#define PIO_PUDR_P26_Pos 26 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P26_Msk (_U_(0x1) << PIO_PUDR_P26_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P26 PIO_PUDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P26_Msk instead */ +#define PIO_PUDR_P27_Pos 27 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P27_Msk (_U_(0x1) << PIO_PUDR_P27_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P27 PIO_PUDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P27_Msk instead */ +#define PIO_PUDR_P28_Pos 28 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P28_Msk (_U_(0x1) << PIO_PUDR_P28_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P28 PIO_PUDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P28_Msk instead */ +#define PIO_PUDR_P29_Pos 29 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P29_Msk (_U_(0x1) << PIO_PUDR_P29_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P29 PIO_PUDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P29_Msk instead */ +#define PIO_PUDR_P30_Pos 30 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P30_Msk (_U_(0x1) << PIO_PUDR_P30_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P30 PIO_PUDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P30_Msk instead */ +#define PIO_PUDR_P31_Pos 31 /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P31_Msk (_U_(0x1) << PIO_PUDR_P31_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P31 PIO_PUDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUDR_P31_Msk instead */ +#define PIO_PUDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUDR) Register MASK (Use PIO_PUDR_Msk instead) */ +#define PIO_PUDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUDR) Register Mask */ + +#define PIO_PUDR_P_Pos 0 /**< (PIO_PUDR Position) Pull-Up Disable */ +#define PIO_PUDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUDR_P_Pos) /**< (PIO_PUDR Mask) P */ +#define PIO_PUDR_P(value) (PIO_PUDR_P_Msk & ((value) << PIO_PUDR_P_Pos)) + +/* -------- PIO_PUER : (PIO Offset: 0x64) (/W 32) Pull-up Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Up Enable */ + uint32_t P1:1; /**< bit: 1 Pull-Up Enable */ + uint32_t P2:1; /**< bit: 2 Pull-Up Enable */ + uint32_t P3:1; /**< bit: 3 Pull-Up Enable */ + uint32_t P4:1; /**< bit: 4 Pull-Up Enable */ + uint32_t P5:1; /**< bit: 5 Pull-Up Enable */ + uint32_t P6:1; /**< bit: 6 Pull-Up Enable */ + uint32_t P7:1; /**< bit: 7 Pull-Up Enable */ + uint32_t P8:1; /**< bit: 8 Pull-Up Enable */ + uint32_t P9:1; /**< bit: 9 Pull-Up Enable */ + uint32_t P10:1; /**< bit: 10 Pull-Up Enable */ + uint32_t P11:1; /**< bit: 11 Pull-Up Enable */ + uint32_t P12:1; /**< bit: 12 Pull-Up Enable */ + uint32_t P13:1; /**< bit: 13 Pull-Up Enable */ + uint32_t P14:1; /**< bit: 14 Pull-Up Enable */ + uint32_t P15:1; /**< bit: 15 Pull-Up Enable */ + uint32_t P16:1; /**< bit: 16 Pull-Up Enable */ + uint32_t P17:1; /**< bit: 17 Pull-Up Enable */ + uint32_t P18:1; /**< bit: 18 Pull-Up Enable */ + uint32_t P19:1; /**< bit: 19 Pull-Up Enable */ + uint32_t P20:1; /**< bit: 20 Pull-Up Enable */ + uint32_t P21:1; /**< bit: 21 Pull-Up Enable */ + uint32_t P22:1; /**< bit: 22 Pull-Up Enable */ + uint32_t P23:1; /**< bit: 23 Pull-Up Enable */ + uint32_t P24:1; /**< bit: 24 Pull-Up Enable */ + uint32_t P25:1; /**< bit: 25 Pull-Up Enable */ + uint32_t P26:1; /**< bit: 26 Pull-Up Enable */ + uint32_t P27:1; /**< bit: 27 Pull-Up Enable */ + uint32_t P28:1; /**< bit: 28 Pull-Up Enable */ + uint32_t P29:1; /**< bit: 29 Pull-Up Enable */ + uint32_t P30:1; /**< bit: 30 Pull-Up Enable */ + uint32_t P31:1; /**< bit: 31 Pull-Up Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Up Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PUER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PUER_OFFSET (0x64) /**< (PIO_PUER) Pull-up Enable Register Offset */ + +#define PIO_PUER_P0_Pos 0 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P0_Msk (_U_(0x1) << PIO_PUER_P0_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P0 PIO_PUER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P0_Msk instead */ +#define PIO_PUER_P1_Pos 1 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P1_Msk (_U_(0x1) << PIO_PUER_P1_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P1 PIO_PUER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P1_Msk instead */ +#define PIO_PUER_P2_Pos 2 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P2_Msk (_U_(0x1) << PIO_PUER_P2_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P2 PIO_PUER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P2_Msk instead */ +#define PIO_PUER_P3_Pos 3 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P3_Msk (_U_(0x1) << PIO_PUER_P3_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P3 PIO_PUER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P3_Msk instead */ +#define PIO_PUER_P4_Pos 4 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P4_Msk (_U_(0x1) << PIO_PUER_P4_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P4 PIO_PUER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P4_Msk instead */ +#define PIO_PUER_P5_Pos 5 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P5_Msk (_U_(0x1) << PIO_PUER_P5_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P5 PIO_PUER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P5_Msk instead */ +#define PIO_PUER_P6_Pos 6 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P6_Msk (_U_(0x1) << PIO_PUER_P6_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P6 PIO_PUER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P6_Msk instead */ +#define PIO_PUER_P7_Pos 7 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P7_Msk (_U_(0x1) << PIO_PUER_P7_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P7 PIO_PUER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P7_Msk instead */ +#define PIO_PUER_P8_Pos 8 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P8_Msk (_U_(0x1) << PIO_PUER_P8_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P8 PIO_PUER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P8_Msk instead */ +#define PIO_PUER_P9_Pos 9 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P9_Msk (_U_(0x1) << PIO_PUER_P9_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P9 PIO_PUER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P9_Msk instead */ +#define PIO_PUER_P10_Pos 10 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P10_Msk (_U_(0x1) << PIO_PUER_P10_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P10 PIO_PUER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P10_Msk instead */ +#define PIO_PUER_P11_Pos 11 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P11_Msk (_U_(0x1) << PIO_PUER_P11_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P11 PIO_PUER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P11_Msk instead */ +#define PIO_PUER_P12_Pos 12 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P12_Msk (_U_(0x1) << PIO_PUER_P12_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P12 PIO_PUER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P12_Msk instead */ +#define PIO_PUER_P13_Pos 13 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P13_Msk (_U_(0x1) << PIO_PUER_P13_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P13 PIO_PUER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P13_Msk instead */ +#define PIO_PUER_P14_Pos 14 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P14_Msk (_U_(0x1) << PIO_PUER_P14_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P14 PIO_PUER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P14_Msk instead */ +#define PIO_PUER_P15_Pos 15 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P15_Msk (_U_(0x1) << PIO_PUER_P15_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P15 PIO_PUER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P15_Msk instead */ +#define PIO_PUER_P16_Pos 16 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P16_Msk (_U_(0x1) << PIO_PUER_P16_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P16 PIO_PUER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P16_Msk instead */ +#define PIO_PUER_P17_Pos 17 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P17_Msk (_U_(0x1) << PIO_PUER_P17_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P17 PIO_PUER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P17_Msk instead */ +#define PIO_PUER_P18_Pos 18 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P18_Msk (_U_(0x1) << PIO_PUER_P18_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P18 PIO_PUER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P18_Msk instead */ +#define PIO_PUER_P19_Pos 19 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P19_Msk (_U_(0x1) << PIO_PUER_P19_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P19 PIO_PUER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P19_Msk instead */ +#define PIO_PUER_P20_Pos 20 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P20_Msk (_U_(0x1) << PIO_PUER_P20_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P20 PIO_PUER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P20_Msk instead */ +#define PIO_PUER_P21_Pos 21 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P21_Msk (_U_(0x1) << PIO_PUER_P21_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P21 PIO_PUER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P21_Msk instead */ +#define PIO_PUER_P22_Pos 22 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P22_Msk (_U_(0x1) << PIO_PUER_P22_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P22 PIO_PUER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P22_Msk instead */ +#define PIO_PUER_P23_Pos 23 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P23_Msk (_U_(0x1) << PIO_PUER_P23_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P23 PIO_PUER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P23_Msk instead */ +#define PIO_PUER_P24_Pos 24 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P24_Msk (_U_(0x1) << PIO_PUER_P24_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P24 PIO_PUER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P24_Msk instead */ +#define PIO_PUER_P25_Pos 25 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P25_Msk (_U_(0x1) << PIO_PUER_P25_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P25 PIO_PUER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P25_Msk instead */ +#define PIO_PUER_P26_Pos 26 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P26_Msk (_U_(0x1) << PIO_PUER_P26_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P26 PIO_PUER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P26_Msk instead */ +#define PIO_PUER_P27_Pos 27 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P27_Msk (_U_(0x1) << PIO_PUER_P27_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P27 PIO_PUER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P27_Msk instead */ +#define PIO_PUER_P28_Pos 28 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P28_Msk (_U_(0x1) << PIO_PUER_P28_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P28 PIO_PUER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P28_Msk instead */ +#define PIO_PUER_P29_Pos 29 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P29_Msk (_U_(0x1) << PIO_PUER_P29_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P29 PIO_PUER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P29_Msk instead */ +#define PIO_PUER_P30_Pos 30 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P30_Msk (_U_(0x1) << PIO_PUER_P30_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P30 PIO_PUER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P30_Msk instead */ +#define PIO_PUER_P31_Pos 31 /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P31_Msk (_U_(0x1) << PIO_PUER_P31_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P31 PIO_PUER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUER_P31_Msk instead */ +#define PIO_PUER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUER) Register MASK (Use PIO_PUER_Msk instead) */ +#define PIO_PUER_Msk _U_(0xFFFFFFFF) /**< (PIO_PUER) Register Mask */ + +#define PIO_PUER_P_Pos 0 /**< (PIO_PUER Position) Pull-Up Enable */ +#define PIO_PUER_P_Msk (_U_(0xFFFFFFFF) << PIO_PUER_P_Pos) /**< (PIO_PUER Mask) P */ +#define PIO_PUER_P(value) (PIO_PUER_P_Msk & ((value) << PIO_PUER_P_Pos)) + +/* -------- PIO_PUSR : (PIO Offset: 0x68) (R/ 32) Pad Pull-up Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Up Status */ + uint32_t P1:1; /**< bit: 1 Pull-Up Status */ + uint32_t P2:1; /**< bit: 2 Pull-Up Status */ + uint32_t P3:1; /**< bit: 3 Pull-Up Status */ + uint32_t P4:1; /**< bit: 4 Pull-Up Status */ + uint32_t P5:1; /**< bit: 5 Pull-Up Status */ + uint32_t P6:1; /**< bit: 6 Pull-Up Status */ + uint32_t P7:1; /**< bit: 7 Pull-Up Status */ + uint32_t P8:1; /**< bit: 8 Pull-Up Status */ + uint32_t P9:1; /**< bit: 9 Pull-Up Status */ + uint32_t P10:1; /**< bit: 10 Pull-Up Status */ + uint32_t P11:1; /**< bit: 11 Pull-Up Status */ + uint32_t P12:1; /**< bit: 12 Pull-Up Status */ + uint32_t P13:1; /**< bit: 13 Pull-Up Status */ + uint32_t P14:1; /**< bit: 14 Pull-Up Status */ + uint32_t P15:1; /**< bit: 15 Pull-Up Status */ + uint32_t P16:1; /**< bit: 16 Pull-Up Status */ + uint32_t P17:1; /**< bit: 17 Pull-Up Status */ + uint32_t P18:1; /**< bit: 18 Pull-Up Status */ + uint32_t P19:1; /**< bit: 19 Pull-Up Status */ + uint32_t P20:1; /**< bit: 20 Pull-Up Status */ + uint32_t P21:1; /**< bit: 21 Pull-Up Status */ + uint32_t P22:1; /**< bit: 22 Pull-Up Status */ + uint32_t P23:1; /**< bit: 23 Pull-Up Status */ + uint32_t P24:1; /**< bit: 24 Pull-Up Status */ + uint32_t P25:1; /**< bit: 25 Pull-Up Status */ + uint32_t P26:1; /**< bit: 26 Pull-Up Status */ + uint32_t P27:1; /**< bit: 27 Pull-Up Status */ + uint32_t P28:1; /**< bit: 28 Pull-Up Status */ + uint32_t P29:1; /**< bit: 29 Pull-Up Status */ + uint32_t P30:1; /**< bit: 30 Pull-Up Status */ + uint32_t P31:1; /**< bit: 31 Pull-Up Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Up Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PUSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PUSR_OFFSET (0x68) /**< (PIO_PUSR) Pad Pull-up Status Register Offset */ + +#define PIO_PUSR_P0_Pos 0 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P0_Msk (_U_(0x1) << PIO_PUSR_P0_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P0 PIO_PUSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P0_Msk instead */ +#define PIO_PUSR_P1_Pos 1 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P1_Msk (_U_(0x1) << PIO_PUSR_P1_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P1 PIO_PUSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P1_Msk instead */ +#define PIO_PUSR_P2_Pos 2 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P2_Msk (_U_(0x1) << PIO_PUSR_P2_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P2 PIO_PUSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P2_Msk instead */ +#define PIO_PUSR_P3_Pos 3 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P3_Msk (_U_(0x1) << PIO_PUSR_P3_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P3 PIO_PUSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P3_Msk instead */ +#define PIO_PUSR_P4_Pos 4 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P4_Msk (_U_(0x1) << PIO_PUSR_P4_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P4 PIO_PUSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P4_Msk instead */ +#define PIO_PUSR_P5_Pos 5 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P5_Msk (_U_(0x1) << PIO_PUSR_P5_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P5 PIO_PUSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P5_Msk instead */ +#define PIO_PUSR_P6_Pos 6 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P6_Msk (_U_(0x1) << PIO_PUSR_P6_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P6 PIO_PUSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P6_Msk instead */ +#define PIO_PUSR_P7_Pos 7 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P7_Msk (_U_(0x1) << PIO_PUSR_P7_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P7 PIO_PUSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P7_Msk instead */ +#define PIO_PUSR_P8_Pos 8 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P8_Msk (_U_(0x1) << PIO_PUSR_P8_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P8 PIO_PUSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P8_Msk instead */ +#define PIO_PUSR_P9_Pos 9 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P9_Msk (_U_(0x1) << PIO_PUSR_P9_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P9 PIO_PUSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P9_Msk instead */ +#define PIO_PUSR_P10_Pos 10 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P10_Msk (_U_(0x1) << PIO_PUSR_P10_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P10 PIO_PUSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P10_Msk instead */ +#define PIO_PUSR_P11_Pos 11 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P11_Msk (_U_(0x1) << PIO_PUSR_P11_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P11 PIO_PUSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P11_Msk instead */ +#define PIO_PUSR_P12_Pos 12 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P12_Msk (_U_(0x1) << PIO_PUSR_P12_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P12 PIO_PUSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P12_Msk instead */ +#define PIO_PUSR_P13_Pos 13 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P13_Msk (_U_(0x1) << PIO_PUSR_P13_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P13 PIO_PUSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P13_Msk instead */ +#define PIO_PUSR_P14_Pos 14 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P14_Msk (_U_(0x1) << PIO_PUSR_P14_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P14 PIO_PUSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P14_Msk instead */ +#define PIO_PUSR_P15_Pos 15 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P15_Msk (_U_(0x1) << PIO_PUSR_P15_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P15 PIO_PUSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P15_Msk instead */ +#define PIO_PUSR_P16_Pos 16 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P16_Msk (_U_(0x1) << PIO_PUSR_P16_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P16 PIO_PUSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P16_Msk instead */ +#define PIO_PUSR_P17_Pos 17 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P17_Msk (_U_(0x1) << PIO_PUSR_P17_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P17 PIO_PUSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P17_Msk instead */ +#define PIO_PUSR_P18_Pos 18 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P18_Msk (_U_(0x1) << PIO_PUSR_P18_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P18 PIO_PUSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P18_Msk instead */ +#define PIO_PUSR_P19_Pos 19 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P19_Msk (_U_(0x1) << PIO_PUSR_P19_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P19 PIO_PUSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P19_Msk instead */ +#define PIO_PUSR_P20_Pos 20 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P20_Msk (_U_(0x1) << PIO_PUSR_P20_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P20 PIO_PUSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P20_Msk instead */ +#define PIO_PUSR_P21_Pos 21 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P21_Msk (_U_(0x1) << PIO_PUSR_P21_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P21 PIO_PUSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P21_Msk instead */ +#define PIO_PUSR_P22_Pos 22 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P22_Msk (_U_(0x1) << PIO_PUSR_P22_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P22 PIO_PUSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P22_Msk instead */ +#define PIO_PUSR_P23_Pos 23 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P23_Msk (_U_(0x1) << PIO_PUSR_P23_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P23 PIO_PUSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P23_Msk instead */ +#define PIO_PUSR_P24_Pos 24 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P24_Msk (_U_(0x1) << PIO_PUSR_P24_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P24 PIO_PUSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P24_Msk instead */ +#define PIO_PUSR_P25_Pos 25 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P25_Msk (_U_(0x1) << PIO_PUSR_P25_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P25 PIO_PUSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P25_Msk instead */ +#define PIO_PUSR_P26_Pos 26 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P26_Msk (_U_(0x1) << PIO_PUSR_P26_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P26 PIO_PUSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P26_Msk instead */ +#define PIO_PUSR_P27_Pos 27 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P27_Msk (_U_(0x1) << PIO_PUSR_P27_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P27 PIO_PUSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P27_Msk instead */ +#define PIO_PUSR_P28_Pos 28 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P28_Msk (_U_(0x1) << PIO_PUSR_P28_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P28 PIO_PUSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P28_Msk instead */ +#define PIO_PUSR_P29_Pos 29 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P29_Msk (_U_(0x1) << PIO_PUSR_P29_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P29 PIO_PUSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P29_Msk instead */ +#define PIO_PUSR_P30_Pos 30 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P30_Msk (_U_(0x1) << PIO_PUSR_P30_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P30 PIO_PUSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P30_Msk instead */ +#define PIO_PUSR_P31_Pos 31 /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P31_Msk (_U_(0x1) << PIO_PUSR_P31_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P31 PIO_PUSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PUSR_P31_Msk instead */ +#define PIO_PUSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PUSR) Register MASK (Use PIO_PUSR_Msk instead) */ +#define PIO_PUSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUSR) Register Mask */ + +#define PIO_PUSR_P_Pos 0 /**< (PIO_PUSR Position) Pull-Up Status */ +#define PIO_PUSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUSR_P_Pos) /**< (PIO_PUSR Mask) P */ +#define PIO_PUSR_P(value) (PIO_PUSR_P_Msk & ((value) << PIO_PUSR_P_Pos)) + +/* -------- PIO_ABCDSR : (PIO Offset: 0x70) (R/W 32) Peripheral ABCD Select Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Peripheral Select */ + uint32_t P1:1; /**< bit: 1 Peripheral Select */ + uint32_t P2:1; /**< bit: 2 Peripheral Select */ + uint32_t P3:1; /**< bit: 3 Peripheral Select */ + uint32_t P4:1; /**< bit: 4 Peripheral Select */ + uint32_t P5:1; /**< bit: 5 Peripheral Select */ + uint32_t P6:1; /**< bit: 6 Peripheral Select */ + uint32_t P7:1; /**< bit: 7 Peripheral Select */ + uint32_t P8:1; /**< bit: 8 Peripheral Select */ + uint32_t P9:1; /**< bit: 9 Peripheral Select */ + uint32_t P10:1; /**< bit: 10 Peripheral Select */ + uint32_t P11:1; /**< bit: 11 Peripheral Select */ + uint32_t P12:1; /**< bit: 12 Peripheral Select */ + uint32_t P13:1; /**< bit: 13 Peripheral Select */ + uint32_t P14:1; /**< bit: 14 Peripheral Select */ + uint32_t P15:1; /**< bit: 15 Peripheral Select */ + uint32_t P16:1; /**< bit: 16 Peripheral Select */ + uint32_t P17:1; /**< bit: 17 Peripheral Select */ + uint32_t P18:1; /**< bit: 18 Peripheral Select */ + uint32_t P19:1; /**< bit: 19 Peripheral Select */ + uint32_t P20:1; /**< bit: 20 Peripheral Select */ + uint32_t P21:1; /**< bit: 21 Peripheral Select */ + uint32_t P22:1; /**< bit: 22 Peripheral Select */ + uint32_t P23:1; /**< bit: 23 Peripheral Select */ + uint32_t P24:1; /**< bit: 24 Peripheral Select */ + uint32_t P25:1; /**< bit: 25 Peripheral Select */ + uint32_t P26:1; /**< bit: 26 Peripheral Select */ + uint32_t P27:1; /**< bit: 27 Peripheral Select */ + uint32_t P28:1; /**< bit: 28 Peripheral Select */ + uint32_t P29:1; /**< bit: 29 Peripheral Select */ + uint32_t P30:1; /**< bit: 30 Peripheral Select */ + uint32_t P31:1; /**< bit: 31 Peripheral Select */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Peripheral Select */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ABCDSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ABCDSR_OFFSET (0x70) /**< (PIO_ABCDSR) Peripheral ABCD Select Register 0 Offset */ + +#define PIO_ABCDSR_P0_Pos 0 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P0_Msk (_U_(0x1) << PIO_ABCDSR_P0_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P0 PIO_ABCDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P0_Msk instead */ +#define PIO_ABCDSR_P1_Pos 1 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P1_Msk (_U_(0x1) << PIO_ABCDSR_P1_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P1 PIO_ABCDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P1_Msk instead */ +#define PIO_ABCDSR_P2_Pos 2 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P2_Msk (_U_(0x1) << PIO_ABCDSR_P2_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P2 PIO_ABCDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P2_Msk instead */ +#define PIO_ABCDSR_P3_Pos 3 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P3_Msk (_U_(0x1) << PIO_ABCDSR_P3_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P3 PIO_ABCDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P3_Msk instead */ +#define PIO_ABCDSR_P4_Pos 4 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P4_Msk (_U_(0x1) << PIO_ABCDSR_P4_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P4 PIO_ABCDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P4_Msk instead */ +#define PIO_ABCDSR_P5_Pos 5 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P5_Msk (_U_(0x1) << PIO_ABCDSR_P5_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P5 PIO_ABCDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P5_Msk instead */ +#define PIO_ABCDSR_P6_Pos 6 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P6_Msk (_U_(0x1) << PIO_ABCDSR_P6_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P6 PIO_ABCDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P6_Msk instead */ +#define PIO_ABCDSR_P7_Pos 7 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P7_Msk (_U_(0x1) << PIO_ABCDSR_P7_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P7 PIO_ABCDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P7_Msk instead */ +#define PIO_ABCDSR_P8_Pos 8 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P8_Msk (_U_(0x1) << PIO_ABCDSR_P8_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P8 PIO_ABCDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P8_Msk instead */ +#define PIO_ABCDSR_P9_Pos 9 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P9_Msk (_U_(0x1) << PIO_ABCDSR_P9_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P9 PIO_ABCDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P9_Msk instead */ +#define PIO_ABCDSR_P10_Pos 10 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P10_Msk (_U_(0x1) << PIO_ABCDSR_P10_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P10 PIO_ABCDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P10_Msk instead */ +#define PIO_ABCDSR_P11_Pos 11 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P11_Msk (_U_(0x1) << PIO_ABCDSR_P11_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P11 PIO_ABCDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P11_Msk instead */ +#define PIO_ABCDSR_P12_Pos 12 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P12_Msk (_U_(0x1) << PIO_ABCDSR_P12_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P12 PIO_ABCDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P12_Msk instead */ +#define PIO_ABCDSR_P13_Pos 13 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P13_Msk (_U_(0x1) << PIO_ABCDSR_P13_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P13 PIO_ABCDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P13_Msk instead */ +#define PIO_ABCDSR_P14_Pos 14 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P14_Msk (_U_(0x1) << PIO_ABCDSR_P14_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P14 PIO_ABCDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P14_Msk instead */ +#define PIO_ABCDSR_P15_Pos 15 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P15_Msk (_U_(0x1) << PIO_ABCDSR_P15_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P15 PIO_ABCDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P15_Msk instead */ +#define PIO_ABCDSR_P16_Pos 16 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P16_Msk (_U_(0x1) << PIO_ABCDSR_P16_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P16 PIO_ABCDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P16_Msk instead */ +#define PIO_ABCDSR_P17_Pos 17 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P17_Msk (_U_(0x1) << PIO_ABCDSR_P17_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P17 PIO_ABCDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P17_Msk instead */ +#define PIO_ABCDSR_P18_Pos 18 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P18_Msk (_U_(0x1) << PIO_ABCDSR_P18_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P18 PIO_ABCDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P18_Msk instead */ +#define PIO_ABCDSR_P19_Pos 19 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P19_Msk (_U_(0x1) << PIO_ABCDSR_P19_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P19 PIO_ABCDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P19_Msk instead */ +#define PIO_ABCDSR_P20_Pos 20 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P20_Msk (_U_(0x1) << PIO_ABCDSR_P20_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P20 PIO_ABCDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P20_Msk instead */ +#define PIO_ABCDSR_P21_Pos 21 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P21_Msk (_U_(0x1) << PIO_ABCDSR_P21_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P21 PIO_ABCDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P21_Msk instead */ +#define PIO_ABCDSR_P22_Pos 22 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P22_Msk (_U_(0x1) << PIO_ABCDSR_P22_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P22 PIO_ABCDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P22_Msk instead */ +#define PIO_ABCDSR_P23_Pos 23 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P23_Msk (_U_(0x1) << PIO_ABCDSR_P23_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P23 PIO_ABCDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P23_Msk instead */ +#define PIO_ABCDSR_P24_Pos 24 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P24_Msk (_U_(0x1) << PIO_ABCDSR_P24_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P24 PIO_ABCDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P24_Msk instead */ +#define PIO_ABCDSR_P25_Pos 25 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P25_Msk (_U_(0x1) << PIO_ABCDSR_P25_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P25 PIO_ABCDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P25_Msk instead */ +#define PIO_ABCDSR_P26_Pos 26 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P26_Msk (_U_(0x1) << PIO_ABCDSR_P26_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P26 PIO_ABCDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P26_Msk instead */ +#define PIO_ABCDSR_P27_Pos 27 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P27_Msk (_U_(0x1) << PIO_ABCDSR_P27_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P27 PIO_ABCDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P27_Msk instead */ +#define PIO_ABCDSR_P28_Pos 28 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P28_Msk (_U_(0x1) << PIO_ABCDSR_P28_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P28 PIO_ABCDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P28_Msk instead */ +#define PIO_ABCDSR_P29_Pos 29 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P29_Msk (_U_(0x1) << PIO_ABCDSR_P29_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P29 PIO_ABCDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P29_Msk instead */ +#define PIO_ABCDSR_P30_Pos 30 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P30_Msk (_U_(0x1) << PIO_ABCDSR_P30_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P30 PIO_ABCDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P30_Msk instead */ +#define PIO_ABCDSR_P31_Pos 31 /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P31_Msk (_U_(0x1) << PIO_ABCDSR_P31_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P31 PIO_ABCDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ABCDSR_P31_Msk instead */ +#define PIO_ABCDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ABCDSR) Register MASK (Use PIO_ABCDSR_Msk instead) */ +#define PIO_ABCDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ABCDSR) Register Mask */ + +#define PIO_ABCDSR_P_Pos 0 /**< (PIO_ABCDSR Position) Peripheral Select */ +#define PIO_ABCDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ABCDSR_P_Pos) /**< (PIO_ABCDSR Mask) P */ +#define PIO_ABCDSR_P(value) (PIO_ABCDSR_P_Msk & ((value) << PIO_ABCDSR_P_Pos)) + +/* -------- PIO_IFSCDR : (PIO Offset: 0x80) (/W 32) Input Filter Slow Clock Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Peripheral Clock Glitch Filtering Select */ + uint32_t P1:1; /**< bit: 1 Peripheral Clock Glitch Filtering Select */ + uint32_t P2:1; /**< bit: 2 Peripheral Clock Glitch Filtering Select */ + uint32_t P3:1; /**< bit: 3 Peripheral Clock Glitch Filtering Select */ + uint32_t P4:1; /**< bit: 4 Peripheral Clock Glitch Filtering Select */ + uint32_t P5:1; /**< bit: 5 Peripheral Clock Glitch Filtering Select */ + uint32_t P6:1; /**< bit: 6 Peripheral Clock Glitch Filtering Select */ + uint32_t P7:1; /**< bit: 7 Peripheral Clock Glitch Filtering Select */ + uint32_t P8:1; /**< bit: 8 Peripheral Clock Glitch Filtering Select */ + uint32_t P9:1; /**< bit: 9 Peripheral Clock Glitch Filtering Select */ + uint32_t P10:1; /**< bit: 10 Peripheral Clock Glitch Filtering Select */ + uint32_t P11:1; /**< bit: 11 Peripheral Clock Glitch Filtering Select */ + uint32_t P12:1; /**< bit: 12 Peripheral Clock Glitch Filtering Select */ + uint32_t P13:1; /**< bit: 13 Peripheral Clock Glitch Filtering Select */ + uint32_t P14:1; /**< bit: 14 Peripheral Clock Glitch Filtering Select */ + uint32_t P15:1; /**< bit: 15 Peripheral Clock Glitch Filtering Select */ + uint32_t P16:1; /**< bit: 16 Peripheral Clock Glitch Filtering Select */ + uint32_t P17:1; /**< bit: 17 Peripheral Clock Glitch Filtering Select */ + uint32_t P18:1; /**< bit: 18 Peripheral Clock Glitch Filtering Select */ + uint32_t P19:1; /**< bit: 19 Peripheral Clock Glitch Filtering Select */ + uint32_t P20:1; /**< bit: 20 Peripheral Clock Glitch Filtering Select */ + uint32_t P21:1; /**< bit: 21 Peripheral Clock Glitch Filtering Select */ + uint32_t P22:1; /**< bit: 22 Peripheral Clock Glitch Filtering Select */ + uint32_t P23:1; /**< bit: 23 Peripheral Clock Glitch Filtering Select */ + uint32_t P24:1; /**< bit: 24 Peripheral Clock Glitch Filtering Select */ + uint32_t P25:1; /**< bit: 25 Peripheral Clock Glitch Filtering Select */ + uint32_t P26:1; /**< bit: 26 Peripheral Clock Glitch Filtering Select */ + uint32_t P27:1; /**< bit: 27 Peripheral Clock Glitch Filtering Select */ + uint32_t P28:1; /**< bit: 28 Peripheral Clock Glitch Filtering Select */ + uint32_t P29:1; /**< bit: 29 Peripheral Clock Glitch Filtering Select */ + uint32_t P30:1; /**< bit: 30 Peripheral Clock Glitch Filtering Select */ + uint32_t P31:1; /**< bit: 31 Peripheral Clock Glitch Filtering Select */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Peripheral Clock Glitch Filtering Select */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFSCDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFSCDR_OFFSET (0x80) /**< (PIO_IFSCDR) Input Filter Slow Clock Disable Register Offset */ + +#define PIO_IFSCDR_P0_Pos 0 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P0_Msk (_U_(0x1) << PIO_IFSCDR_P0_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P0 PIO_IFSCDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P0_Msk instead */ +#define PIO_IFSCDR_P1_Pos 1 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P1_Msk (_U_(0x1) << PIO_IFSCDR_P1_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P1 PIO_IFSCDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P1_Msk instead */ +#define PIO_IFSCDR_P2_Pos 2 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P2_Msk (_U_(0x1) << PIO_IFSCDR_P2_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P2 PIO_IFSCDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P2_Msk instead */ +#define PIO_IFSCDR_P3_Pos 3 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P3_Msk (_U_(0x1) << PIO_IFSCDR_P3_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P3 PIO_IFSCDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P3_Msk instead */ +#define PIO_IFSCDR_P4_Pos 4 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P4_Msk (_U_(0x1) << PIO_IFSCDR_P4_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P4 PIO_IFSCDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P4_Msk instead */ +#define PIO_IFSCDR_P5_Pos 5 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P5_Msk (_U_(0x1) << PIO_IFSCDR_P5_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P5 PIO_IFSCDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P5_Msk instead */ +#define PIO_IFSCDR_P6_Pos 6 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P6_Msk (_U_(0x1) << PIO_IFSCDR_P6_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P6 PIO_IFSCDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P6_Msk instead */ +#define PIO_IFSCDR_P7_Pos 7 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P7_Msk (_U_(0x1) << PIO_IFSCDR_P7_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P7 PIO_IFSCDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P7_Msk instead */ +#define PIO_IFSCDR_P8_Pos 8 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P8_Msk (_U_(0x1) << PIO_IFSCDR_P8_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P8 PIO_IFSCDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P8_Msk instead */ +#define PIO_IFSCDR_P9_Pos 9 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P9_Msk (_U_(0x1) << PIO_IFSCDR_P9_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P9 PIO_IFSCDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P9_Msk instead */ +#define PIO_IFSCDR_P10_Pos 10 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P10_Msk (_U_(0x1) << PIO_IFSCDR_P10_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P10 PIO_IFSCDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P10_Msk instead */ +#define PIO_IFSCDR_P11_Pos 11 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P11_Msk (_U_(0x1) << PIO_IFSCDR_P11_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P11 PIO_IFSCDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P11_Msk instead */ +#define PIO_IFSCDR_P12_Pos 12 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P12_Msk (_U_(0x1) << PIO_IFSCDR_P12_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P12 PIO_IFSCDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P12_Msk instead */ +#define PIO_IFSCDR_P13_Pos 13 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P13_Msk (_U_(0x1) << PIO_IFSCDR_P13_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P13 PIO_IFSCDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P13_Msk instead */ +#define PIO_IFSCDR_P14_Pos 14 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P14_Msk (_U_(0x1) << PIO_IFSCDR_P14_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P14 PIO_IFSCDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P14_Msk instead */ +#define PIO_IFSCDR_P15_Pos 15 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P15_Msk (_U_(0x1) << PIO_IFSCDR_P15_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P15 PIO_IFSCDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P15_Msk instead */ +#define PIO_IFSCDR_P16_Pos 16 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P16_Msk (_U_(0x1) << PIO_IFSCDR_P16_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P16 PIO_IFSCDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P16_Msk instead */ +#define PIO_IFSCDR_P17_Pos 17 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P17_Msk (_U_(0x1) << PIO_IFSCDR_P17_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P17 PIO_IFSCDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P17_Msk instead */ +#define PIO_IFSCDR_P18_Pos 18 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P18_Msk (_U_(0x1) << PIO_IFSCDR_P18_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P18 PIO_IFSCDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P18_Msk instead */ +#define PIO_IFSCDR_P19_Pos 19 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P19_Msk (_U_(0x1) << PIO_IFSCDR_P19_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P19 PIO_IFSCDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P19_Msk instead */ +#define PIO_IFSCDR_P20_Pos 20 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P20_Msk (_U_(0x1) << PIO_IFSCDR_P20_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P20 PIO_IFSCDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P20_Msk instead */ +#define PIO_IFSCDR_P21_Pos 21 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P21_Msk (_U_(0x1) << PIO_IFSCDR_P21_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P21 PIO_IFSCDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P21_Msk instead */ +#define PIO_IFSCDR_P22_Pos 22 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P22_Msk (_U_(0x1) << PIO_IFSCDR_P22_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P22 PIO_IFSCDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P22_Msk instead */ +#define PIO_IFSCDR_P23_Pos 23 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P23_Msk (_U_(0x1) << PIO_IFSCDR_P23_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P23 PIO_IFSCDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P23_Msk instead */ +#define PIO_IFSCDR_P24_Pos 24 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P24_Msk (_U_(0x1) << PIO_IFSCDR_P24_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P24 PIO_IFSCDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P24_Msk instead */ +#define PIO_IFSCDR_P25_Pos 25 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P25_Msk (_U_(0x1) << PIO_IFSCDR_P25_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P25 PIO_IFSCDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P25_Msk instead */ +#define PIO_IFSCDR_P26_Pos 26 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P26_Msk (_U_(0x1) << PIO_IFSCDR_P26_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P26 PIO_IFSCDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P26_Msk instead */ +#define PIO_IFSCDR_P27_Pos 27 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P27_Msk (_U_(0x1) << PIO_IFSCDR_P27_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P27 PIO_IFSCDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P27_Msk instead */ +#define PIO_IFSCDR_P28_Pos 28 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P28_Msk (_U_(0x1) << PIO_IFSCDR_P28_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P28 PIO_IFSCDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P28_Msk instead */ +#define PIO_IFSCDR_P29_Pos 29 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P29_Msk (_U_(0x1) << PIO_IFSCDR_P29_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P29 PIO_IFSCDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P29_Msk instead */ +#define PIO_IFSCDR_P30_Pos 30 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P30_Msk (_U_(0x1) << PIO_IFSCDR_P30_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P30 PIO_IFSCDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P30_Msk instead */ +#define PIO_IFSCDR_P31_Pos 31 /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P31_Msk (_U_(0x1) << PIO_IFSCDR_P31_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P31 PIO_IFSCDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCDR_P31_Msk instead */ +#define PIO_IFSCDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCDR) Register MASK (Use PIO_IFSCDR_Msk instead) */ +#define PIO_IFSCDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCDR) Register Mask */ + +#define PIO_IFSCDR_P_Pos 0 /**< (PIO_IFSCDR Position) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCDR_P_Pos) /**< (PIO_IFSCDR Mask) P */ +#define PIO_IFSCDR_P(value) (PIO_IFSCDR_P_Msk & ((value) << PIO_IFSCDR_P_Pos)) + +/* -------- PIO_IFSCER : (PIO Offset: 0x84) (/W 32) Input Filter Slow Clock Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Slow Clock Debouncing Filtering Select */ + uint32_t P1:1; /**< bit: 1 Slow Clock Debouncing Filtering Select */ + uint32_t P2:1; /**< bit: 2 Slow Clock Debouncing Filtering Select */ + uint32_t P3:1; /**< bit: 3 Slow Clock Debouncing Filtering Select */ + uint32_t P4:1; /**< bit: 4 Slow Clock Debouncing Filtering Select */ + uint32_t P5:1; /**< bit: 5 Slow Clock Debouncing Filtering Select */ + uint32_t P6:1; /**< bit: 6 Slow Clock Debouncing Filtering Select */ + uint32_t P7:1; /**< bit: 7 Slow Clock Debouncing Filtering Select */ + uint32_t P8:1; /**< bit: 8 Slow Clock Debouncing Filtering Select */ + uint32_t P9:1; /**< bit: 9 Slow Clock Debouncing Filtering Select */ + uint32_t P10:1; /**< bit: 10 Slow Clock Debouncing Filtering Select */ + uint32_t P11:1; /**< bit: 11 Slow Clock Debouncing Filtering Select */ + uint32_t P12:1; /**< bit: 12 Slow Clock Debouncing Filtering Select */ + uint32_t P13:1; /**< bit: 13 Slow Clock Debouncing Filtering Select */ + uint32_t P14:1; /**< bit: 14 Slow Clock Debouncing Filtering Select */ + uint32_t P15:1; /**< bit: 15 Slow Clock Debouncing Filtering Select */ + uint32_t P16:1; /**< bit: 16 Slow Clock Debouncing Filtering Select */ + uint32_t P17:1; /**< bit: 17 Slow Clock Debouncing Filtering Select */ + uint32_t P18:1; /**< bit: 18 Slow Clock Debouncing Filtering Select */ + uint32_t P19:1; /**< bit: 19 Slow Clock Debouncing Filtering Select */ + uint32_t P20:1; /**< bit: 20 Slow Clock Debouncing Filtering Select */ + uint32_t P21:1; /**< bit: 21 Slow Clock Debouncing Filtering Select */ + uint32_t P22:1; /**< bit: 22 Slow Clock Debouncing Filtering Select */ + uint32_t P23:1; /**< bit: 23 Slow Clock Debouncing Filtering Select */ + uint32_t P24:1; /**< bit: 24 Slow Clock Debouncing Filtering Select */ + uint32_t P25:1; /**< bit: 25 Slow Clock Debouncing Filtering Select */ + uint32_t P26:1; /**< bit: 26 Slow Clock Debouncing Filtering Select */ + uint32_t P27:1; /**< bit: 27 Slow Clock Debouncing Filtering Select */ + uint32_t P28:1; /**< bit: 28 Slow Clock Debouncing Filtering Select */ + uint32_t P29:1; /**< bit: 29 Slow Clock Debouncing Filtering Select */ + uint32_t P30:1; /**< bit: 30 Slow Clock Debouncing Filtering Select */ + uint32_t P31:1; /**< bit: 31 Slow Clock Debouncing Filtering Select */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Slow Clock Debouncing Filtering Select */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFSCER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFSCER_OFFSET (0x84) /**< (PIO_IFSCER) Input Filter Slow Clock Enable Register Offset */ + +#define PIO_IFSCER_P0_Pos 0 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P0_Msk (_U_(0x1) << PIO_IFSCER_P0_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P0 PIO_IFSCER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P0_Msk instead */ +#define PIO_IFSCER_P1_Pos 1 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P1_Msk (_U_(0x1) << PIO_IFSCER_P1_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P1 PIO_IFSCER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P1_Msk instead */ +#define PIO_IFSCER_P2_Pos 2 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P2_Msk (_U_(0x1) << PIO_IFSCER_P2_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P2 PIO_IFSCER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P2_Msk instead */ +#define PIO_IFSCER_P3_Pos 3 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P3_Msk (_U_(0x1) << PIO_IFSCER_P3_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P3 PIO_IFSCER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P3_Msk instead */ +#define PIO_IFSCER_P4_Pos 4 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P4_Msk (_U_(0x1) << PIO_IFSCER_P4_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P4 PIO_IFSCER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P4_Msk instead */ +#define PIO_IFSCER_P5_Pos 5 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P5_Msk (_U_(0x1) << PIO_IFSCER_P5_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P5 PIO_IFSCER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P5_Msk instead */ +#define PIO_IFSCER_P6_Pos 6 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P6_Msk (_U_(0x1) << PIO_IFSCER_P6_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P6 PIO_IFSCER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P6_Msk instead */ +#define PIO_IFSCER_P7_Pos 7 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P7_Msk (_U_(0x1) << PIO_IFSCER_P7_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P7 PIO_IFSCER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P7_Msk instead */ +#define PIO_IFSCER_P8_Pos 8 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P8_Msk (_U_(0x1) << PIO_IFSCER_P8_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P8 PIO_IFSCER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P8_Msk instead */ +#define PIO_IFSCER_P9_Pos 9 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P9_Msk (_U_(0x1) << PIO_IFSCER_P9_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P9 PIO_IFSCER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P9_Msk instead */ +#define PIO_IFSCER_P10_Pos 10 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P10_Msk (_U_(0x1) << PIO_IFSCER_P10_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P10 PIO_IFSCER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P10_Msk instead */ +#define PIO_IFSCER_P11_Pos 11 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P11_Msk (_U_(0x1) << PIO_IFSCER_P11_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P11 PIO_IFSCER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P11_Msk instead */ +#define PIO_IFSCER_P12_Pos 12 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P12_Msk (_U_(0x1) << PIO_IFSCER_P12_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P12 PIO_IFSCER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P12_Msk instead */ +#define PIO_IFSCER_P13_Pos 13 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P13_Msk (_U_(0x1) << PIO_IFSCER_P13_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P13 PIO_IFSCER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P13_Msk instead */ +#define PIO_IFSCER_P14_Pos 14 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P14_Msk (_U_(0x1) << PIO_IFSCER_P14_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P14 PIO_IFSCER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P14_Msk instead */ +#define PIO_IFSCER_P15_Pos 15 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P15_Msk (_U_(0x1) << PIO_IFSCER_P15_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P15 PIO_IFSCER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P15_Msk instead */ +#define PIO_IFSCER_P16_Pos 16 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P16_Msk (_U_(0x1) << PIO_IFSCER_P16_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P16 PIO_IFSCER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P16_Msk instead */ +#define PIO_IFSCER_P17_Pos 17 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P17_Msk (_U_(0x1) << PIO_IFSCER_P17_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P17 PIO_IFSCER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P17_Msk instead */ +#define PIO_IFSCER_P18_Pos 18 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P18_Msk (_U_(0x1) << PIO_IFSCER_P18_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P18 PIO_IFSCER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P18_Msk instead */ +#define PIO_IFSCER_P19_Pos 19 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P19_Msk (_U_(0x1) << PIO_IFSCER_P19_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P19 PIO_IFSCER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P19_Msk instead */ +#define PIO_IFSCER_P20_Pos 20 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P20_Msk (_U_(0x1) << PIO_IFSCER_P20_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P20 PIO_IFSCER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P20_Msk instead */ +#define PIO_IFSCER_P21_Pos 21 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P21_Msk (_U_(0x1) << PIO_IFSCER_P21_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P21 PIO_IFSCER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P21_Msk instead */ +#define PIO_IFSCER_P22_Pos 22 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P22_Msk (_U_(0x1) << PIO_IFSCER_P22_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P22 PIO_IFSCER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P22_Msk instead */ +#define PIO_IFSCER_P23_Pos 23 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P23_Msk (_U_(0x1) << PIO_IFSCER_P23_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P23 PIO_IFSCER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P23_Msk instead */ +#define PIO_IFSCER_P24_Pos 24 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P24_Msk (_U_(0x1) << PIO_IFSCER_P24_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P24 PIO_IFSCER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P24_Msk instead */ +#define PIO_IFSCER_P25_Pos 25 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P25_Msk (_U_(0x1) << PIO_IFSCER_P25_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P25 PIO_IFSCER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P25_Msk instead */ +#define PIO_IFSCER_P26_Pos 26 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P26_Msk (_U_(0x1) << PIO_IFSCER_P26_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P26 PIO_IFSCER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P26_Msk instead */ +#define PIO_IFSCER_P27_Pos 27 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P27_Msk (_U_(0x1) << PIO_IFSCER_P27_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P27 PIO_IFSCER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P27_Msk instead */ +#define PIO_IFSCER_P28_Pos 28 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P28_Msk (_U_(0x1) << PIO_IFSCER_P28_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P28 PIO_IFSCER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P28_Msk instead */ +#define PIO_IFSCER_P29_Pos 29 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P29_Msk (_U_(0x1) << PIO_IFSCER_P29_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P29 PIO_IFSCER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P29_Msk instead */ +#define PIO_IFSCER_P30_Pos 30 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P30_Msk (_U_(0x1) << PIO_IFSCER_P30_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P30 PIO_IFSCER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P30_Msk instead */ +#define PIO_IFSCER_P31_Pos 31 /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P31_Msk (_U_(0x1) << PIO_IFSCER_P31_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P31 PIO_IFSCER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCER_P31_Msk instead */ +#define PIO_IFSCER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCER) Register MASK (Use PIO_IFSCER_Msk instead) */ +#define PIO_IFSCER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCER) Register Mask */ + +#define PIO_IFSCER_P_Pos 0 /**< (PIO_IFSCER Position) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCER_P_Pos) /**< (PIO_IFSCER Mask) P */ +#define PIO_IFSCER_P(value) (PIO_IFSCER_P_Msk & ((value) << PIO_IFSCER_P_Pos)) + +/* -------- PIO_IFSCSR : (PIO Offset: 0x88) (R/ 32) Input Filter Slow Clock Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Glitch or Debouncing Filter Selection Status */ + uint32_t P1:1; /**< bit: 1 Glitch or Debouncing Filter Selection Status */ + uint32_t P2:1; /**< bit: 2 Glitch or Debouncing Filter Selection Status */ + uint32_t P3:1; /**< bit: 3 Glitch or Debouncing Filter Selection Status */ + uint32_t P4:1; /**< bit: 4 Glitch or Debouncing Filter Selection Status */ + uint32_t P5:1; /**< bit: 5 Glitch or Debouncing Filter Selection Status */ + uint32_t P6:1; /**< bit: 6 Glitch or Debouncing Filter Selection Status */ + uint32_t P7:1; /**< bit: 7 Glitch or Debouncing Filter Selection Status */ + uint32_t P8:1; /**< bit: 8 Glitch or Debouncing Filter Selection Status */ + uint32_t P9:1; /**< bit: 9 Glitch or Debouncing Filter Selection Status */ + uint32_t P10:1; /**< bit: 10 Glitch or Debouncing Filter Selection Status */ + uint32_t P11:1; /**< bit: 11 Glitch or Debouncing Filter Selection Status */ + uint32_t P12:1; /**< bit: 12 Glitch or Debouncing Filter Selection Status */ + uint32_t P13:1; /**< bit: 13 Glitch or Debouncing Filter Selection Status */ + uint32_t P14:1; /**< bit: 14 Glitch or Debouncing Filter Selection Status */ + uint32_t P15:1; /**< bit: 15 Glitch or Debouncing Filter Selection Status */ + uint32_t P16:1; /**< bit: 16 Glitch or Debouncing Filter Selection Status */ + uint32_t P17:1; /**< bit: 17 Glitch or Debouncing Filter Selection Status */ + uint32_t P18:1; /**< bit: 18 Glitch or Debouncing Filter Selection Status */ + uint32_t P19:1; /**< bit: 19 Glitch or Debouncing Filter Selection Status */ + uint32_t P20:1; /**< bit: 20 Glitch or Debouncing Filter Selection Status */ + uint32_t P21:1; /**< bit: 21 Glitch or Debouncing Filter Selection Status */ + uint32_t P22:1; /**< bit: 22 Glitch or Debouncing Filter Selection Status */ + uint32_t P23:1; /**< bit: 23 Glitch or Debouncing Filter Selection Status */ + uint32_t P24:1; /**< bit: 24 Glitch or Debouncing Filter Selection Status */ + uint32_t P25:1; /**< bit: 25 Glitch or Debouncing Filter Selection Status */ + uint32_t P26:1; /**< bit: 26 Glitch or Debouncing Filter Selection Status */ + uint32_t P27:1; /**< bit: 27 Glitch or Debouncing Filter Selection Status */ + uint32_t P28:1; /**< bit: 28 Glitch or Debouncing Filter Selection Status */ + uint32_t P29:1; /**< bit: 29 Glitch or Debouncing Filter Selection Status */ + uint32_t P30:1; /**< bit: 30 Glitch or Debouncing Filter Selection Status */ + uint32_t P31:1; /**< bit: 31 Glitch or Debouncing Filter Selection Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Glitch or Debouncing Filter Selection Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_IFSCSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_IFSCSR_OFFSET (0x88) /**< (PIO_IFSCSR) Input Filter Slow Clock Status Register Offset */ + +#define PIO_IFSCSR_P0_Pos 0 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P0_Msk (_U_(0x1) << PIO_IFSCSR_P0_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P0 PIO_IFSCSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P0_Msk instead */ +#define PIO_IFSCSR_P1_Pos 1 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P1_Msk (_U_(0x1) << PIO_IFSCSR_P1_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P1 PIO_IFSCSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P1_Msk instead */ +#define PIO_IFSCSR_P2_Pos 2 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P2_Msk (_U_(0x1) << PIO_IFSCSR_P2_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P2 PIO_IFSCSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P2_Msk instead */ +#define PIO_IFSCSR_P3_Pos 3 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P3_Msk (_U_(0x1) << PIO_IFSCSR_P3_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P3 PIO_IFSCSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P3_Msk instead */ +#define PIO_IFSCSR_P4_Pos 4 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P4_Msk (_U_(0x1) << PIO_IFSCSR_P4_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P4 PIO_IFSCSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P4_Msk instead */ +#define PIO_IFSCSR_P5_Pos 5 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P5_Msk (_U_(0x1) << PIO_IFSCSR_P5_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P5 PIO_IFSCSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P5_Msk instead */ +#define PIO_IFSCSR_P6_Pos 6 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P6_Msk (_U_(0x1) << PIO_IFSCSR_P6_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P6 PIO_IFSCSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P6_Msk instead */ +#define PIO_IFSCSR_P7_Pos 7 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P7_Msk (_U_(0x1) << PIO_IFSCSR_P7_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P7 PIO_IFSCSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P7_Msk instead */ +#define PIO_IFSCSR_P8_Pos 8 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P8_Msk (_U_(0x1) << PIO_IFSCSR_P8_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P8 PIO_IFSCSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P8_Msk instead */ +#define PIO_IFSCSR_P9_Pos 9 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P9_Msk (_U_(0x1) << PIO_IFSCSR_P9_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P9 PIO_IFSCSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P9_Msk instead */ +#define PIO_IFSCSR_P10_Pos 10 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P10_Msk (_U_(0x1) << PIO_IFSCSR_P10_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P10 PIO_IFSCSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P10_Msk instead */ +#define PIO_IFSCSR_P11_Pos 11 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P11_Msk (_U_(0x1) << PIO_IFSCSR_P11_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P11 PIO_IFSCSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P11_Msk instead */ +#define PIO_IFSCSR_P12_Pos 12 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P12_Msk (_U_(0x1) << PIO_IFSCSR_P12_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P12 PIO_IFSCSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P12_Msk instead */ +#define PIO_IFSCSR_P13_Pos 13 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P13_Msk (_U_(0x1) << PIO_IFSCSR_P13_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P13 PIO_IFSCSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P13_Msk instead */ +#define PIO_IFSCSR_P14_Pos 14 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P14_Msk (_U_(0x1) << PIO_IFSCSR_P14_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P14 PIO_IFSCSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P14_Msk instead */ +#define PIO_IFSCSR_P15_Pos 15 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P15_Msk (_U_(0x1) << PIO_IFSCSR_P15_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P15 PIO_IFSCSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P15_Msk instead */ +#define PIO_IFSCSR_P16_Pos 16 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P16_Msk (_U_(0x1) << PIO_IFSCSR_P16_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P16 PIO_IFSCSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P16_Msk instead */ +#define PIO_IFSCSR_P17_Pos 17 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P17_Msk (_U_(0x1) << PIO_IFSCSR_P17_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P17 PIO_IFSCSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P17_Msk instead */ +#define PIO_IFSCSR_P18_Pos 18 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P18_Msk (_U_(0x1) << PIO_IFSCSR_P18_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P18 PIO_IFSCSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P18_Msk instead */ +#define PIO_IFSCSR_P19_Pos 19 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P19_Msk (_U_(0x1) << PIO_IFSCSR_P19_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P19 PIO_IFSCSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P19_Msk instead */ +#define PIO_IFSCSR_P20_Pos 20 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P20_Msk (_U_(0x1) << PIO_IFSCSR_P20_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P20 PIO_IFSCSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P20_Msk instead */ +#define PIO_IFSCSR_P21_Pos 21 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P21_Msk (_U_(0x1) << PIO_IFSCSR_P21_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P21 PIO_IFSCSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P21_Msk instead */ +#define PIO_IFSCSR_P22_Pos 22 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P22_Msk (_U_(0x1) << PIO_IFSCSR_P22_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P22 PIO_IFSCSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P22_Msk instead */ +#define PIO_IFSCSR_P23_Pos 23 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P23_Msk (_U_(0x1) << PIO_IFSCSR_P23_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P23 PIO_IFSCSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P23_Msk instead */ +#define PIO_IFSCSR_P24_Pos 24 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P24_Msk (_U_(0x1) << PIO_IFSCSR_P24_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P24 PIO_IFSCSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P24_Msk instead */ +#define PIO_IFSCSR_P25_Pos 25 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P25_Msk (_U_(0x1) << PIO_IFSCSR_P25_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P25 PIO_IFSCSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P25_Msk instead */ +#define PIO_IFSCSR_P26_Pos 26 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P26_Msk (_U_(0x1) << PIO_IFSCSR_P26_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P26 PIO_IFSCSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P26_Msk instead */ +#define PIO_IFSCSR_P27_Pos 27 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P27_Msk (_U_(0x1) << PIO_IFSCSR_P27_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P27 PIO_IFSCSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P27_Msk instead */ +#define PIO_IFSCSR_P28_Pos 28 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P28_Msk (_U_(0x1) << PIO_IFSCSR_P28_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P28 PIO_IFSCSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P28_Msk instead */ +#define PIO_IFSCSR_P29_Pos 29 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P29_Msk (_U_(0x1) << PIO_IFSCSR_P29_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P29 PIO_IFSCSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P29_Msk instead */ +#define PIO_IFSCSR_P30_Pos 30 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P30_Msk (_U_(0x1) << PIO_IFSCSR_P30_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P30 PIO_IFSCSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P30_Msk instead */ +#define PIO_IFSCSR_P31_Pos 31 /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P31_Msk (_U_(0x1) << PIO_IFSCSR_P31_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P31 PIO_IFSCSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_IFSCSR_P31_Msk instead */ +#define PIO_IFSCSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_IFSCSR) Register MASK (Use PIO_IFSCSR_Msk instead) */ +#define PIO_IFSCSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCSR) Register Mask */ + +#define PIO_IFSCSR_P_Pos 0 /**< (PIO_IFSCSR Position) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCSR_P_Pos) /**< (PIO_IFSCSR Mask) P */ +#define PIO_IFSCSR_P(value) (PIO_IFSCSR_P_Msk & ((value) << PIO_IFSCSR_P_Pos)) + +/* -------- PIO_SCDR : (PIO Offset: 0x8c) (R/W 32) Slow Clock Divider Debouncing Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DIV:14; /**< bit: 0..13 Slow Clock Divider Selection for Debouncing */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_SCDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_SCDR_OFFSET (0x8C) /**< (PIO_SCDR) Slow Clock Divider Debouncing Register Offset */ + +#define PIO_SCDR_DIV_Pos 0 /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Position */ +#define PIO_SCDR_DIV_Msk (_U_(0x3FFF) << PIO_SCDR_DIV_Pos) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Mask */ +#define PIO_SCDR_DIV(value) (PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)) +#define PIO_SCDR_MASK _U_(0x3FFF) /**< \deprecated (PIO_SCDR) Register MASK (Use PIO_SCDR_Msk instead) */ +#define PIO_SCDR_Msk _U_(0x3FFF) /**< (PIO_SCDR) Register Mask */ + + +/* -------- PIO_PPDDR : (PIO Offset: 0x90) (/W 32) Pad Pull-down Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Down Disable */ + uint32_t P1:1; /**< bit: 1 Pull-Down Disable */ + uint32_t P2:1; /**< bit: 2 Pull-Down Disable */ + uint32_t P3:1; /**< bit: 3 Pull-Down Disable */ + uint32_t P4:1; /**< bit: 4 Pull-Down Disable */ + uint32_t P5:1; /**< bit: 5 Pull-Down Disable */ + uint32_t P6:1; /**< bit: 6 Pull-Down Disable */ + uint32_t P7:1; /**< bit: 7 Pull-Down Disable */ + uint32_t P8:1; /**< bit: 8 Pull-Down Disable */ + uint32_t P9:1; /**< bit: 9 Pull-Down Disable */ + uint32_t P10:1; /**< bit: 10 Pull-Down Disable */ + uint32_t P11:1; /**< bit: 11 Pull-Down Disable */ + uint32_t P12:1; /**< bit: 12 Pull-Down Disable */ + uint32_t P13:1; /**< bit: 13 Pull-Down Disable */ + uint32_t P14:1; /**< bit: 14 Pull-Down Disable */ + uint32_t P15:1; /**< bit: 15 Pull-Down Disable */ + uint32_t P16:1; /**< bit: 16 Pull-Down Disable */ + uint32_t P17:1; /**< bit: 17 Pull-Down Disable */ + uint32_t P18:1; /**< bit: 18 Pull-Down Disable */ + uint32_t P19:1; /**< bit: 19 Pull-Down Disable */ + uint32_t P20:1; /**< bit: 20 Pull-Down Disable */ + uint32_t P21:1; /**< bit: 21 Pull-Down Disable */ + uint32_t P22:1; /**< bit: 22 Pull-Down Disable */ + uint32_t P23:1; /**< bit: 23 Pull-Down Disable */ + uint32_t P24:1; /**< bit: 24 Pull-Down Disable */ + uint32_t P25:1; /**< bit: 25 Pull-Down Disable */ + uint32_t P26:1; /**< bit: 26 Pull-Down Disable */ + uint32_t P27:1; /**< bit: 27 Pull-Down Disable */ + uint32_t P28:1; /**< bit: 28 Pull-Down Disable */ + uint32_t P29:1; /**< bit: 29 Pull-Down Disable */ + uint32_t P30:1; /**< bit: 30 Pull-Down Disable */ + uint32_t P31:1; /**< bit: 31 Pull-Down Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Down Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PPDDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PPDDR_OFFSET (0x90) /**< (PIO_PPDDR) Pad Pull-down Disable Register Offset */ + +#define PIO_PPDDR_P0_Pos 0 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P0_Msk (_U_(0x1) << PIO_PPDDR_P0_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P0 PIO_PPDDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P0_Msk instead */ +#define PIO_PPDDR_P1_Pos 1 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P1_Msk (_U_(0x1) << PIO_PPDDR_P1_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P1 PIO_PPDDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P1_Msk instead */ +#define PIO_PPDDR_P2_Pos 2 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P2_Msk (_U_(0x1) << PIO_PPDDR_P2_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P2 PIO_PPDDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P2_Msk instead */ +#define PIO_PPDDR_P3_Pos 3 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P3_Msk (_U_(0x1) << PIO_PPDDR_P3_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P3 PIO_PPDDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P3_Msk instead */ +#define PIO_PPDDR_P4_Pos 4 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P4_Msk (_U_(0x1) << PIO_PPDDR_P4_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P4 PIO_PPDDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P4_Msk instead */ +#define PIO_PPDDR_P5_Pos 5 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P5_Msk (_U_(0x1) << PIO_PPDDR_P5_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P5 PIO_PPDDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P5_Msk instead */ +#define PIO_PPDDR_P6_Pos 6 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P6_Msk (_U_(0x1) << PIO_PPDDR_P6_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P6 PIO_PPDDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P6_Msk instead */ +#define PIO_PPDDR_P7_Pos 7 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P7_Msk (_U_(0x1) << PIO_PPDDR_P7_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P7 PIO_PPDDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P7_Msk instead */ +#define PIO_PPDDR_P8_Pos 8 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P8_Msk (_U_(0x1) << PIO_PPDDR_P8_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P8 PIO_PPDDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P8_Msk instead */ +#define PIO_PPDDR_P9_Pos 9 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P9_Msk (_U_(0x1) << PIO_PPDDR_P9_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P9 PIO_PPDDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P9_Msk instead */ +#define PIO_PPDDR_P10_Pos 10 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P10_Msk (_U_(0x1) << PIO_PPDDR_P10_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P10 PIO_PPDDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P10_Msk instead */ +#define PIO_PPDDR_P11_Pos 11 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P11_Msk (_U_(0x1) << PIO_PPDDR_P11_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P11 PIO_PPDDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P11_Msk instead */ +#define PIO_PPDDR_P12_Pos 12 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P12_Msk (_U_(0x1) << PIO_PPDDR_P12_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P12 PIO_PPDDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P12_Msk instead */ +#define PIO_PPDDR_P13_Pos 13 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P13_Msk (_U_(0x1) << PIO_PPDDR_P13_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P13 PIO_PPDDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P13_Msk instead */ +#define PIO_PPDDR_P14_Pos 14 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P14_Msk (_U_(0x1) << PIO_PPDDR_P14_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P14 PIO_PPDDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P14_Msk instead */ +#define PIO_PPDDR_P15_Pos 15 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P15_Msk (_U_(0x1) << PIO_PPDDR_P15_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P15 PIO_PPDDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P15_Msk instead */ +#define PIO_PPDDR_P16_Pos 16 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P16_Msk (_U_(0x1) << PIO_PPDDR_P16_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P16 PIO_PPDDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P16_Msk instead */ +#define PIO_PPDDR_P17_Pos 17 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P17_Msk (_U_(0x1) << PIO_PPDDR_P17_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P17 PIO_PPDDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P17_Msk instead */ +#define PIO_PPDDR_P18_Pos 18 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P18_Msk (_U_(0x1) << PIO_PPDDR_P18_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P18 PIO_PPDDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P18_Msk instead */ +#define PIO_PPDDR_P19_Pos 19 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P19_Msk (_U_(0x1) << PIO_PPDDR_P19_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P19 PIO_PPDDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P19_Msk instead */ +#define PIO_PPDDR_P20_Pos 20 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P20_Msk (_U_(0x1) << PIO_PPDDR_P20_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P20 PIO_PPDDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P20_Msk instead */ +#define PIO_PPDDR_P21_Pos 21 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P21_Msk (_U_(0x1) << PIO_PPDDR_P21_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P21 PIO_PPDDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P21_Msk instead */ +#define PIO_PPDDR_P22_Pos 22 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P22_Msk (_U_(0x1) << PIO_PPDDR_P22_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P22 PIO_PPDDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P22_Msk instead */ +#define PIO_PPDDR_P23_Pos 23 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P23_Msk (_U_(0x1) << PIO_PPDDR_P23_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P23 PIO_PPDDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P23_Msk instead */ +#define PIO_PPDDR_P24_Pos 24 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P24_Msk (_U_(0x1) << PIO_PPDDR_P24_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P24 PIO_PPDDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P24_Msk instead */ +#define PIO_PPDDR_P25_Pos 25 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P25_Msk (_U_(0x1) << PIO_PPDDR_P25_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P25 PIO_PPDDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P25_Msk instead */ +#define PIO_PPDDR_P26_Pos 26 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P26_Msk (_U_(0x1) << PIO_PPDDR_P26_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P26 PIO_PPDDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P26_Msk instead */ +#define PIO_PPDDR_P27_Pos 27 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P27_Msk (_U_(0x1) << PIO_PPDDR_P27_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P27 PIO_PPDDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P27_Msk instead */ +#define PIO_PPDDR_P28_Pos 28 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P28_Msk (_U_(0x1) << PIO_PPDDR_P28_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P28 PIO_PPDDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P28_Msk instead */ +#define PIO_PPDDR_P29_Pos 29 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P29_Msk (_U_(0x1) << PIO_PPDDR_P29_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P29 PIO_PPDDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P29_Msk instead */ +#define PIO_PPDDR_P30_Pos 30 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P30_Msk (_U_(0x1) << PIO_PPDDR_P30_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P30 PIO_PPDDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P30_Msk instead */ +#define PIO_PPDDR_P31_Pos 31 /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P31_Msk (_U_(0x1) << PIO_PPDDR_P31_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P31 PIO_PPDDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDDR_P31_Msk instead */ +#define PIO_PPDDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDDR) Register MASK (Use PIO_PPDDR_Msk instead) */ +#define PIO_PPDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDDR) Register Mask */ + +#define PIO_PPDDR_P_Pos 0 /**< (PIO_PPDDR Position) Pull-Down Disable */ +#define PIO_PPDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDDR_P_Pos) /**< (PIO_PPDDR Mask) P */ +#define PIO_PPDDR_P(value) (PIO_PPDDR_P_Msk & ((value) << PIO_PPDDR_P_Pos)) + +/* -------- PIO_PPDER : (PIO Offset: 0x94) (/W 32) Pad Pull-down Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Down Enable */ + uint32_t P1:1; /**< bit: 1 Pull-Down Enable */ + uint32_t P2:1; /**< bit: 2 Pull-Down Enable */ + uint32_t P3:1; /**< bit: 3 Pull-Down Enable */ + uint32_t P4:1; /**< bit: 4 Pull-Down Enable */ + uint32_t P5:1; /**< bit: 5 Pull-Down Enable */ + uint32_t P6:1; /**< bit: 6 Pull-Down Enable */ + uint32_t P7:1; /**< bit: 7 Pull-Down Enable */ + uint32_t P8:1; /**< bit: 8 Pull-Down Enable */ + uint32_t P9:1; /**< bit: 9 Pull-Down Enable */ + uint32_t P10:1; /**< bit: 10 Pull-Down Enable */ + uint32_t P11:1; /**< bit: 11 Pull-Down Enable */ + uint32_t P12:1; /**< bit: 12 Pull-Down Enable */ + uint32_t P13:1; /**< bit: 13 Pull-Down Enable */ + uint32_t P14:1; /**< bit: 14 Pull-Down Enable */ + uint32_t P15:1; /**< bit: 15 Pull-Down Enable */ + uint32_t P16:1; /**< bit: 16 Pull-Down Enable */ + uint32_t P17:1; /**< bit: 17 Pull-Down Enable */ + uint32_t P18:1; /**< bit: 18 Pull-Down Enable */ + uint32_t P19:1; /**< bit: 19 Pull-Down Enable */ + uint32_t P20:1; /**< bit: 20 Pull-Down Enable */ + uint32_t P21:1; /**< bit: 21 Pull-Down Enable */ + uint32_t P22:1; /**< bit: 22 Pull-Down Enable */ + uint32_t P23:1; /**< bit: 23 Pull-Down Enable */ + uint32_t P24:1; /**< bit: 24 Pull-Down Enable */ + uint32_t P25:1; /**< bit: 25 Pull-Down Enable */ + uint32_t P26:1; /**< bit: 26 Pull-Down Enable */ + uint32_t P27:1; /**< bit: 27 Pull-Down Enable */ + uint32_t P28:1; /**< bit: 28 Pull-Down Enable */ + uint32_t P29:1; /**< bit: 29 Pull-Down Enable */ + uint32_t P30:1; /**< bit: 30 Pull-Down Enable */ + uint32_t P31:1; /**< bit: 31 Pull-Down Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Down Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PPDER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PPDER_OFFSET (0x94) /**< (PIO_PPDER) Pad Pull-down Enable Register Offset */ + +#define PIO_PPDER_P0_Pos 0 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P0_Msk (_U_(0x1) << PIO_PPDER_P0_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P0 PIO_PPDER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P0_Msk instead */ +#define PIO_PPDER_P1_Pos 1 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P1_Msk (_U_(0x1) << PIO_PPDER_P1_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P1 PIO_PPDER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P1_Msk instead */ +#define PIO_PPDER_P2_Pos 2 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P2_Msk (_U_(0x1) << PIO_PPDER_P2_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P2 PIO_PPDER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P2_Msk instead */ +#define PIO_PPDER_P3_Pos 3 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P3_Msk (_U_(0x1) << PIO_PPDER_P3_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P3 PIO_PPDER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P3_Msk instead */ +#define PIO_PPDER_P4_Pos 4 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P4_Msk (_U_(0x1) << PIO_PPDER_P4_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P4 PIO_PPDER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P4_Msk instead */ +#define PIO_PPDER_P5_Pos 5 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P5_Msk (_U_(0x1) << PIO_PPDER_P5_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P5 PIO_PPDER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P5_Msk instead */ +#define PIO_PPDER_P6_Pos 6 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P6_Msk (_U_(0x1) << PIO_PPDER_P6_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P6 PIO_PPDER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P6_Msk instead */ +#define PIO_PPDER_P7_Pos 7 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P7_Msk (_U_(0x1) << PIO_PPDER_P7_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P7 PIO_PPDER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P7_Msk instead */ +#define PIO_PPDER_P8_Pos 8 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P8_Msk (_U_(0x1) << PIO_PPDER_P8_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P8 PIO_PPDER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P8_Msk instead */ +#define PIO_PPDER_P9_Pos 9 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P9_Msk (_U_(0x1) << PIO_PPDER_P9_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P9 PIO_PPDER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P9_Msk instead */ +#define PIO_PPDER_P10_Pos 10 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P10_Msk (_U_(0x1) << PIO_PPDER_P10_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P10 PIO_PPDER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P10_Msk instead */ +#define PIO_PPDER_P11_Pos 11 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P11_Msk (_U_(0x1) << PIO_PPDER_P11_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P11 PIO_PPDER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P11_Msk instead */ +#define PIO_PPDER_P12_Pos 12 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P12_Msk (_U_(0x1) << PIO_PPDER_P12_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P12 PIO_PPDER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P12_Msk instead */ +#define PIO_PPDER_P13_Pos 13 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P13_Msk (_U_(0x1) << PIO_PPDER_P13_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P13 PIO_PPDER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P13_Msk instead */ +#define PIO_PPDER_P14_Pos 14 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P14_Msk (_U_(0x1) << PIO_PPDER_P14_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P14 PIO_PPDER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P14_Msk instead */ +#define PIO_PPDER_P15_Pos 15 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P15_Msk (_U_(0x1) << PIO_PPDER_P15_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P15 PIO_PPDER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P15_Msk instead */ +#define PIO_PPDER_P16_Pos 16 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P16_Msk (_U_(0x1) << PIO_PPDER_P16_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P16 PIO_PPDER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P16_Msk instead */ +#define PIO_PPDER_P17_Pos 17 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P17_Msk (_U_(0x1) << PIO_PPDER_P17_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P17 PIO_PPDER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P17_Msk instead */ +#define PIO_PPDER_P18_Pos 18 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P18_Msk (_U_(0x1) << PIO_PPDER_P18_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P18 PIO_PPDER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P18_Msk instead */ +#define PIO_PPDER_P19_Pos 19 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P19_Msk (_U_(0x1) << PIO_PPDER_P19_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P19 PIO_PPDER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P19_Msk instead */ +#define PIO_PPDER_P20_Pos 20 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P20_Msk (_U_(0x1) << PIO_PPDER_P20_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P20 PIO_PPDER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P20_Msk instead */ +#define PIO_PPDER_P21_Pos 21 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P21_Msk (_U_(0x1) << PIO_PPDER_P21_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P21 PIO_PPDER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P21_Msk instead */ +#define PIO_PPDER_P22_Pos 22 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P22_Msk (_U_(0x1) << PIO_PPDER_P22_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P22 PIO_PPDER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P22_Msk instead */ +#define PIO_PPDER_P23_Pos 23 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P23_Msk (_U_(0x1) << PIO_PPDER_P23_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P23 PIO_PPDER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P23_Msk instead */ +#define PIO_PPDER_P24_Pos 24 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P24_Msk (_U_(0x1) << PIO_PPDER_P24_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P24 PIO_PPDER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P24_Msk instead */ +#define PIO_PPDER_P25_Pos 25 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P25_Msk (_U_(0x1) << PIO_PPDER_P25_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P25 PIO_PPDER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P25_Msk instead */ +#define PIO_PPDER_P26_Pos 26 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P26_Msk (_U_(0x1) << PIO_PPDER_P26_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P26 PIO_PPDER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P26_Msk instead */ +#define PIO_PPDER_P27_Pos 27 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P27_Msk (_U_(0x1) << PIO_PPDER_P27_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P27 PIO_PPDER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P27_Msk instead */ +#define PIO_PPDER_P28_Pos 28 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P28_Msk (_U_(0x1) << PIO_PPDER_P28_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P28 PIO_PPDER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P28_Msk instead */ +#define PIO_PPDER_P29_Pos 29 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P29_Msk (_U_(0x1) << PIO_PPDER_P29_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P29 PIO_PPDER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P29_Msk instead */ +#define PIO_PPDER_P30_Pos 30 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P30_Msk (_U_(0x1) << PIO_PPDER_P30_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P30 PIO_PPDER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P30_Msk instead */ +#define PIO_PPDER_P31_Pos 31 /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P31_Msk (_U_(0x1) << PIO_PPDER_P31_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P31 PIO_PPDER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDER_P31_Msk instead */ +#define PIO_PPDER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDER) Register MASK (Use PIO_PPDER_Msk instead) */ +#define PIO_PPDER_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDER) Register Mask */ + +#define PIO_PPDER_P_Pos 0 /**< (PIO_PPDER Position) Pull-Down Enable */ +#define PIO_PPDER_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDER_P_Pos) /**< (PIO_PPDER Mask) P */ +#define PIO_PPDER_P(value) (PIO_PPDER_P_Msk & ((value) << PIO_PPDER_P_Pos)) + +/* -------- PIO_PPDSR : (PIO Offset: 0x98) (R/ 32) Pad Pull-down Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Pull-Down Status */ + uint32_t P1:1; /**< bit: 1 Pull-Down Status */ + uint32_t P2:1; /**< bit: 2 Pull-Down Status */ + uint32_t P3:1; /**< bit: 3 Pull-Down Status */ + uint32_t P4:1; /**< bit: 4 Pull-Down Status */ + uint32_t P5:1; /**< bit: 5 Pull-Down Status */ + uint32_t P6:1; /**< bit: 6 Pull-Down Status */ + uint32_t P7:1; /**< bit: 7 Pull-Down Status */ + uint32_t P8:1; /**< bit: 8 Pull-Down Status */ + uint32_t P9:1; /**< bit: 9 Pull-Down Status */ + uint32_t P10:1; /**< bit: 10 Pull-Down Status */ + uint32_t P11:1; /**< bit: 11 Pull-Down Status */ + uint32_t P12:1; /**< bit: 12 Pull-Down Status */ + uint32_t P13:1; /**< bit: 13 Pull-Down Status */ + uint32_t P14:1; /**< bit: 14 Pull-Down Status */ + uint32_t P15:1; /**< bit: 15 Pull-Down Status */ + uint32_t P16:1; /**< bit: 16 Pull-Down Status */ + uint32_t P17:1; /**< bit: 17 Pull-Down Status */ + uint32_t P18:1; /**< bit: 18 Pull-Down Status */ + uint32_t P19:1; /**< bit: 19 Pull-Down Status */ + uint32_t P20:1; /**< bit: 20 Pull-Down Status */ + uint32_t P21:1; /**< bit: 21 Pull-Down Status */ + uint32_t P22:1; /**< bit: 22 Pull-Down Status */ + uint32_t P23:1; /**< bit: 23 Pull-Down Status */ + uint32_t P24:1; /**< bit: 24 Pull-Down Status */ + uint32_t P25:1; /**< bit: 25 Pull-Down Status */ + uint32_t P26:1; /**< bit: 26 Pull-Down Status */ + uint32_t P27:1; /**< bit: 27 Pull-Down Status */ + uint32_t P28:1; /**< bit: 28 Pull-Down Status */ + uint32_t P29:1; /**< bit: 29 Pull-Down Status */ + uint32_t P30:1; /**< bit: 30 Pull-Down Status */ + uint32_t P31:1; /**< bit: 31 Pull-Down Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Pull-Down Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PPDSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PPDSR_OFFSET (0x98) /**< (PIO_PPDSR) Pad Pull-down Status Register Offset */ + +#define PIO_PPDSR_P0_Pos 0 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P0_Msk (_U_(0x1) << PIO_PPDSR_P0_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P0 PIO_PPDSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P0_Msk instead */ +#define PIO_PPDSR_P1_Pos 1 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P1_Msk (_U_(0x1) << PIO_PPDSR_P1_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P1 PIO_PPDSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P1_Msk instead */ +#define PIO_PPDSR_P2_Pos 2 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P2_Msk (_U_(0x1) << PIO_PPDSR_P2_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P2 PIO_PPDSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P2_Msk instead */ +#define PIO_PPDSR_P3_Pos 3 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P3_Msk (_U_(0x1) << PIO_PPDSR_P3_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P3 PIO_PPDSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P3_Msk instead */ +#define PIO_PPDSR_P4_Pos 4 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P4_Msk (_U_(0x1) << PIO_PPDSR_P4_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P4 PIO_PPDSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P4_Msk instead */ +#define PIO_PPDSR_P5_Pos 5 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P5_Msk (_U_(0x1) << PIO_PPDSR_P5_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P5 PIO_PPDSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P5_Msk instead */ +#define PIO_PPDSR_P6_Pos 6 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P6_Msk (_U_(0x1) << PIO_PPDSR_P6_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P6 PIO_PPDSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P6_Msk instead */ +#define PIO_PPDSR_P7_Pos 7 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P7_Msk (_U_(0x1) << PIO_PPDSR_P7_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P7 PIO_PPDSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P7_Msk instead */ +#define PIO_PPDSR_P8_Pos 8 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P8_Msk (_U_(0x1) << PIO_PPDSR_P8_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P8 PIO_PPDSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P8_Msk instead */ +#define PIO_PPDSR_P9_Pos 9 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P9_Msk (_U_(0x1) << PIO_PPDSR_P9_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P9 PIO_PPDSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P9_Msk instead */ +#define PIO_PPDSR_P10_Pos 10 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P10_Msk (_U_(0x1) << PIO_PPDSR_P10_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P10 PIO_PPDSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P10_Msk instead */ +#define PIO_PPDSR_P11_Pos 11 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P11_Msk (_U_(0x1) << PIO_PPDSR_P11_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P11 PIO_PPDSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P11_Msk instead */ +#define PIO_PPDSR_P12_Pos 12 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P12_Msk (_U_(0x1) << PIO_PPDSR_P12_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P12 PIO_PPDSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P12_Msk instead */ +#define PIO_PPDSR_P13_Pos 13 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P13_Msk (_U_(0x1) << PIO_PPDSR_P13_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P13 PIO_PPDSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P13_Msk instead */ +#define PIO_PPDSR_P14_Pos 14 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P14_Msk (_U_(0x1) << PIO_PPDSR_P14_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P14 PIO_PPDSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P14_Msk instead */ +#define PIO_PPDSR_P15_Pos 15 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P15_Msk (_U_(0x1) << PIO_PPDSR_P15_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P15 PIO_PPDSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P15_Msk instead */ +#define PIO_PPDSR_P16_Pos 16 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P16_Msk (_U_(0x1) << PIO_PPDSR_P16_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P16 PIO_PPDSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P16_Msk instead */ +#define PIO_PPDSR_P17_Pos 17 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P17_Msk (_U_(0x1) << PIO_PPDSR_P17_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P17 PIO_PPDSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P17_Msk instead */ +#define PIO_PPDSR_P18_Pos 18 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P18_Msk (_U_(0x1) << PIO_PPDSR_P18_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P18 PIO_PPDSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P18_Msk instead */ +#define PIO_PPDSR_P19_Pos 19 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P19_Msk (_U_(0x1) << PIO_PPDSR_P19_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P19 PIO_PPDSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P19_Msk instead */ +#define PIO_PPDSR_P20_Pos 20 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P20_Msk (_U_(0x1) << PIO_PPDSR_P20_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P20 PIO_PPDSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P20_Msk instead */ +#define PIO_PPDSR_P21_Pos 21 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P21_Msk (_U_(0x1) << PIO_PPDSR_P21_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P21 PIO_PPDSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P21_Msk instead */ +#define PIO_PPDSR_P22_Pos 22 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P22_Msk (_U_(0x1) << PIO_PPDSR_P22_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P22 PIO_PPDSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P22_Msk instead */ +#define PIO_PPDSR_P23_Pos 23 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P23_Msk (_U_(0x1) << PIO_PPDSR_P23_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P23 PIO_PPDSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P23_Msk instead */ +#define PIO_PPDSR_P24_Pos 24 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P24_Msk (_U_(0x1) << PIO_PPDSR_P24_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P24 PIO_PPDSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P24_Msk instead */ +#define PIO_PPDSR_P25_Pos 25 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P25_Msk (_U_(0x1) << PIO_PPDSR_P25_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P25 PIO_PPDSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P25_Msk instead */ +#define PIO_PPDSR_P26_Pos 26 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P26_Msk (_U_(0x1) << PIO_PPDSR_P26_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P26 PIO_PPDSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P26_Msk instead */ +#define PIO_PPDSR_P27_Pos 27 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P27_Msk (_U_(0x1) << PIO_PPDSR_P27_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P27 PIO_PPDSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P27_Msk instead */ +#define PIO_PPDSR_P28_Pos 28 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P28_Msk (_U_(0x1) << PIO_PPDSR_P28_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P28 PIO_PPDSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P28_Msk instead */ +#define PIO_PPDSR_P29_Pos 29 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P29_Msk (_U_(0x1) << PIO_PPDSR_P29_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P29 PIO_PPDSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P29_Msk instead */ +#define PIO_PPDSR_P30_Pos 30 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P30_Msk (_U_(0x1) << PIO_PPDSR_P30_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P30 PIO_PPDSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P30_Msk instead */ +#define PIO_PPDSR_P31_Pos 31 /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P31_Msk (_U_(0x1) << PIO_PPDSR_P31_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P31 PIO_PPDSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PPDSR_P31_Msk instead */ +#define PIO_PPDSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PPDSR) Register MASK (Use PIO_PPDSR_Msk instead) */ +#define PIO_PPDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDSR) Register Mask */ + +#define PIO_PPDSR_P_Pos 0 /**< (PIO_PPDSR Position) Pull-Down Status */ +#define PIO_PPDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDSR_P_Pos) /**< (PIO_PPDSR Mask) P */ +#define PIO_PPDSR_P(value) (PIO_PPDSR_P_Msk & ((value) << PIO_PPDSR_P_Pos)) + +/* -------- PIO_OWER : (PIO Offset: 0xa0) (/W 32) Output Write Enable -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Write Enable */ + uint32_t P1:1; /**< bit: 1 Output Write Enable */ + uint32_t P2:1; /**< bit: 2 Output Write Enable */ + uint32_t P3:1; /**< bit: 3 Output Write Enable */ + uint32_t P4:1; /**< bit: 4 Output Write Enable */ + uint32_t P5:1; /**< bit: 5 Output Write Enable */ + uint32_t P6:1; /**< bit: 6 Output Write Enable */ + uint32_t P7:1; /**< bit: 7 Output Write Enable */ + uint32_t P8:1; /**< bit: 8 Output Write Enable */ + uint32_t P9:1; /**< bit: 9 Output Write Enable */ + uint32_t P10:1; /**< bit: 10 Output Write Enable */ + uint32_t P11:1; /**< bit: 11 Output Write Enable */ + uint32_t P12:1; /**< bit: 12 Output Write Enable */ + uint32_t P13:1; /**< bit: 13 Output Write Enable */ + uint32_t P14:1; /**< bit: 14 Output Write Enable */ + uint32_t P15:1; /**< bit: 15 Output Write Enable */ + uint32_t P16:1; /**< bit: 16 Output Write Enable */ + uint32_t P17:1; /**< bit: 17 Output Write Enable */ + uint32_t P18:1; /**< bit: 18 Output Write Enable */ + uint32_t P19:1; /**< bit: 19 Output Write Enable */ + uint32_t P20:1; /**< bit: 20 Output Write Enable */ + uint32_t P21:1; /**< bit: 21 Output Write Enable */ + uint32_t P22:1; /**< bit: 22 Output Write Enable */ + uint32_t P23:1; /**< bit: 23 Output Write Enable */ + uint32_t P24:1; /**< bit: 24 Output Write Enable */ + uint32_t P25:1; /**< bit: 25 Output Write Enable */ + uint32_t P26:1; /**< bit: 26 Output Write Enable */ + uint32_t P27:1; /**< bit: 27 Output Write Enable */ + uint32_t P28:1; /**< bit: 28 Output Write Enable */ + uint32_t P29:1; /**< bit: 29 Output Write Enable */ + uint32_t P30:1; /**< bit: 30 Output Write Enable */ + uint32_t P31:1; /**< bit: 31 Output Write Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Write Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_OWER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_OWER_OFFSET (0xA0) /**< (PIO_OWER) Output Write Enable Offset */ + +#define PIO_OWER_P0_Pos 0 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P0_Msk (_U_(0x1) << PIO_OWER_P0_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P0 PIO_OWER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P0_Msk instead */ +#define PIO_OWER_P1_Pos 1 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P1_Msk (_U_(0x1) << PIO_OWER_P1_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P1 PIO_OWER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P1_Msk instead */ +#define PIO_OWER_P2_Pos 2 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P2_Msk (_U_(0x1) << PIO_OWER_P2_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P2 PIO_OWER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P2_Msk instead */ +#define PIO_OWER_P3_Pos 3 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P3_Msk (_U_(0x1) << PIO_OWER_P3_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P3 PIO_OWER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P3_Msk instead */ +#define PIO_OWER_P4_Pos 4 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P4_Msk (_U_(0x1) << PIO_OWER_P4_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P4 PIO_OWER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P4_Msk instead */ +#define PIO_OWER_P5_Pos 5 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P5_Msk (_U_(0x1) << PIO_OWER_P5_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P5 PIO_OWER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P5_Msk instead */ +#define PIO_OWER_P6_Pos 6 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P6_Msk (_U_(0x1) << PIO_OWER_P6_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P6 PIO_OWER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P6_Msk instead */ +#define PIO_OWER_P7_Pos 7 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P7_Msk (_U_(0x1) << PIO_OWER_P7_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P7 PIO_OWER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P7_Msk instead */ +#define PIO_OWER_P8_Pos 8 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P8_Msk (_U_(0x1) << PIO_OWER_P8_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P8 PIO_OWER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P8_Msk instead */ +#define PIO_OWER_P9_Pos 9 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P9_Msk (_U_(0x1) << PIO_OWER_P9_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P9 PIO_OWER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P9_Msk instead */ +#define PIO_OWER_P10_Pos 10 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P10_Msk (_U_(0x1) << PIO_OWER_P10_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P10 PIO_OWER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P10_Msk instead */ +#define PIO_OWER_P11_Pos 11 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P11_Msk (_U_(0x1) << PIO_OWER_P11_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P11 PIO_OWER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P11_Msk instead */ +#define PIO_OWER_P12_Pos 12 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P12_Msk (_U_(0x1) << PIO_OWER_P12_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P12 PIO_OWER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P12_Msk instead */ +#define PIO_OWER_P13_Pos 13 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P13_Msk (_U_(0x1) << PIO_OWER_P13_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P13 PIO_OWER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P13_Msk instead */ +#define PIO_OWER_P14_Pos 14 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P14_Msk (_U_(0x1) << PIO_OWER_P14_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P14 PIO_OWER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P14_Msk instead */ +#define PIO_OWER_P15_Pos 15 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P15_Msk (_U_(0x1) << PIO_OWER_P15_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P15 PIO_OWER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P15_Msk instead */ +#define PIO_OWER_P16_Pos 16 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P16_Msk (_U_(0x1) << PIO_OWER_P16_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P16 PIO_OWER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P16_Msk instead */ +#define PIO_OWER_P17_Pos 17 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P17_Msk (_U_(0x1) << PIO_OWER_P17_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P17 PIO_OWER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P17_Msk instead */ +#define PIO_OWER_P18_Pos 18 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P18_Msk (_U_(0x1) << PIO_OWER_P18_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P18 PIO_OWER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P18_Msk instead */ +#define PIO_OWER_P19_Pos 19 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P19_Msk (_U_(0x1) << PIO_OWER_P19_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P19 PIO_OWER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P19_Msk instead */ +#define PIO_OWER_P20_Pos 20 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P20_Msk (_U_(0x1) << PIO_OWER_P20_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P20 PIO_OWER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P20_Msk instead */ +#define PIO_OWER_P21_Pos 21 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P21_Msk (_U_(0x1) << PIO_OWER_P21_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P21 PIO_OWER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P21_Msk instead */ +#define PIO_OWER_P22_Pos 22 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P22_Msk (_U_(0x1) << PIO_OWER_P22_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P22 PIO_OWER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P22_Msk instead */ +#define PIO_OWER_P23_Pos 23 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P23_Msk (_U_(0x1) << PIO_OWER_P23_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P23 PIO_OWER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P23_Msk instead */ +#define PIO_OWER_P24_Pos 24 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P24_Msk (_U_(0x1) << PIO_OWER_P24_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P24 PIO_OWER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P24_Msk instead */ +#define PIO_OWER_P25_Pos 25 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P25_Msk (_U_(0x1) << PIO_OWER_P25_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P25 PIO_OWER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P25_Msk instead */ +#define PIO_OWER_P26_Pos 26 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P26_Msk (_U_(0x1) << PIO_OWER_P26_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P26 PIO_OWER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P26_Msk instead */ +#define PIO_OWER_P27_Pos 27 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P27_Msk (_U_(0x1) << PIO_OWER_P27_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P27 PIO_OWER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P27_Msk instead */ +#define PIO_OWER_P28_Pos 28 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P28_Msk (_U_(0x1) << PIO_OWER_P28_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P28 PIO_OWER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P28_Msk instead */ +#define PIO_OWER_P29_Pos 29 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P29_Msk (_U_(0x1) << PIO_OWER_P29_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P29 PIO_OWER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P29_Msk instead */ +#define PIO_OWER_P30_Pos 30 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P30_Msk (_U_(0x1) << PIO_OWER_P30_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P30 PIO_OWER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P30_Msk instead */ +#define PIO_OWER_P31_Pos 31 /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P31_Msk (_U_(0x1) << PIO_OWER_P31_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P31 PIO_OWER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWER_P31_Msk instead */ +#define PIO_OWER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWER) Register MASK (Use PIO_OWER_Msk instead) */ +#define PIO_OWER_Msk _U_(0xFFFFFFFF) /**< (PIO_OWER) Register Mask */ + +#define PIO_OWER_P_Pos 0 /**< (PIO_OWER Position) Output Write Enable */ +#define PIO_OWER_P_Msk (_U_(0xFFFFFFFF) << PIO_OWER_P_Pos) /**< (PIO_OWER Mask) P */ +#define PIO_OWER_P(value) (PIO_OWER_P_Msk & ((value) << PIO_OWER_P_Pos)) + +/* -------- PIO_OWDR : (PIO Offset: 0xa4) (/W 32) Output Write Disable -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Write Disable */ + uint32_t P1:1; /**< bit: 1 Output Write Disable */ + uint32_t P2:1; /**< bit: 2 Output Write Disable */ + uint32_t P3:1; /**< bit: 3 Output Write Disable */ + uint32_t P4:1; /**< bit: 4 Output Write Disable */ + uint32_t P5:1; /**< bit: 5 Output Write Disable */ + uint32_t P6:1; /**< bit: 6 Output Write Disable */ + uint32_t P7:1; /**< bit: 7 Output Write Disable */ + uint32_t P8:1; /**< bit: 8 Output Write Disable */ + uint32_t P9:1; /**< bit: 9 Output Write Disable */ + uint32_t P10:1; /**< bit: 10 Output Write Disable */ + uint32_t P11:1; /**< bit: 11 Output Write Disable */ + uint32_t P12:1; /**< bit: 12 Output Write Disable */ + uint32_t P13:1; /**< bit: 13 Output Write Disable */ + uint32_t P14:1; /**< bit: 14 Output Write Disable */ + uint32_t P15:1; /**< bit: 15 Output Write Disable */ + uint32_t P16:1; /**< bit: 16 Output Write Disable */ + uint32_t P17:1; /**< bit: 17 Output Write Disable */ + uint32_t P18:1; /**< bit: 18 Output Write Disable */ + uint32_t P19:1; /**< bit: 19 Output Write Disable */ + uint32_t P20:1; /**< bit: 20 Output Write Disable */ + uint32_t P21:1; /**< bit: 21 Output Write Disable */ + uint32_t P22:1; /**< bit: 22 Output Write Disable */ + uint32_t P23:1; /**< bit: 23 Output Write Disable */ + uint32_t P24:1; /**< bit: 24 Output Write Disable */ + uint32_t P25:1; /**< bit: 25 Output Write Disable */ + uint32_t P26:1; /**< bit: 26 Output Write Disable */ + uint32_t P27:1; /**< bit: 27 Output Write Disable */ + uint32_t P28:1; /**< bit: 28 Output Write Disable */ + uint32_t P29:1; /**< bit: 29 Output Write Disable */ + uint32_t P30:1; /**< bit: 30 Output Write Disable */ + uint32_t P31:1; /**< bit: 31 Output Write Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Write Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_OWDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_OWDR_OFFSET (0xA4) /**< (PIO_OWDR) Output Write Disable Offset */ + +#define PIO_OWDR_P0_Pos 0 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P0_Msk (_U_(0x1) << PIO_OWDR_P0_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P0 PIO_OWDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P0_Msk instead */ +#define PIO_OWDR_P1_Pos 1 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P1_Msk (_U_(0x1) << PIO_OWDR_P1_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P1 PIO_OWDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P1_Msk instead */ +#define PIO_OWDR_P2_Pos 2 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P2_Msk (_U_(0x1) << PIO_OWDR_P2_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P2 PIO_OWDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P2_Msk instead */ +#define PIO_OWDR_P3_Pos 3 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P3_Msk (_U_(0x1) << PIO_OWDR_P3_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P3 PIO_OWDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P3_Msk instead */ +#define PIO_OWDR_P4_Pos 4 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P4_Msk (_U_(0x1) << PIO_OWDR_P4_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P4 PIO_OWDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P4_Msk instead */ +#define PIO_OWDR_P5_Pos 5 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P5_Msk (_U_(0x1) << PIO_OWDR_P5_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P5 PIO_OWDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P5_Msk instead */ +#define PIO_OWDR_P6_Pos 6 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P6_Msk (_U_(0x1) << PIO_OWDR_P6_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P6 PIO_OWDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P6_Msk instead */ +#define PIO_OWDR_P7_Pos 7 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P7_Msk (_U_(0x1) << PIO_OWDR_P7_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P7 PIO_OWDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P7_Msk instead */ +#define PIO_OWDR_P8_Pos 8 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P8_Msk (_U_(0x1) << PIO_OWDR_P8_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P8 PIO_OWDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P8_Msk instead */ +#define PIO_OWDR_P9_Pos 9 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P9_Msk (_U_(0x1) << PIO_OWDR_P9_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P9 PIO_OWDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P9_Msk instead */ +#define PIO_OWDR_P10_Pos 10 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P10_Msk (_U_(0x1) << PIO_OWDR_P10_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P10 PIO_OWDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P10_Msk instead */ +#define PIO_OWDR_P11_Pos 11 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P11_Msk (_U_(0x1) << PIO_OWDR_P11_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P11 PIO_OWDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P11_Msk instead */ +#define PIO_OWDR_P12_Pos 12 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P12_Msk (_U_(0x1) << PIO_OWDR_P12_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P12 PIO_OWDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P12_Msk instead */ +#define PIO_OWDR_P13_Pos 13 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P13_Msk (_U_(0x1) << PIO_OWDR_P13_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P13 PIO_OWDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P13_Msk instead */ +#define PIO_OWDR_P14_Pos 14 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P14_Msk (_U_(0x1) << PIO_OWDR_P14_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P14 PIO_OWDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P14_Msk instead */ +#define PIO_OWDR_P15_Pos 15 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P15_Msk (_U_(0x1) << PIO_OWDR_P15_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P15 PIO_OWDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P15_Msk instead */ +#define PIO_OWDR_P16_Pos 16 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P16_Msk (_U_(0x1) << PIO_OWDR_P16_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P16 PIO_OWDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P16_Msk instead */ +#define PIO_OWDR_P17_Pos 17 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P17_Msk (_U_(0x1) << PIO_OWDR_P17_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P17 PIO_OWDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P17_Msk instead */ +#define PIO_OWDR_P18_Pos 18 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P18_Msk (_U_(0x1) << PIO_OWDR_P18_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P18 PIO_OWDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P18_Msk instead */ +#define PIO_OWDR_P19_Pos 19 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P19_Msk (_U_(0x1) << PIO_OWDR_P19_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P19 PIO_OWDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P19_Msk instead */ +#define PIO_OWDR_P20_Pos 20 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P20_Msk (_U_(0x1) << PIO_OWDR_P20_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P20 PIO_OWDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P20_Msk instead */ +#define PIO_OWDR_P21_Pos 21 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P21_Msk (_U_(0x1) << PIO_OWDR_P21_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P21 PIO_OWDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P21_Msk instead */ +#define PIO_OWDR_P22_Pos 22 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P22_Msk (_U_(0x1) << PIO_OWDR_P22_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P22 PIO_OWDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P22_Msk instead */ +#define PIO_OWDR_P23_Pos 23 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P23_Msk (_U_(0x1) << PIO_OWDR_P23_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P23 PIO_OWDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P23_Msk instead */ +#define PIO_OWDR_P24_Pos 24 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P24_Msk (_U_(0x1) << PIO_OWDR_P24_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P24 PIO_OWDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P24_Msk instead */ +#define PIO_OWDR_P25_Pos 25 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P25_Msk (_U_(0x1) << PIO_OWDR_P25_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P25 PIO_OWDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P25_Msk instead */ +#define PIO_OWDR_P26_Pos 26 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P26_Msk (_U_(0x1) << PIO_OWDR_P26_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P26 PIO_OWDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P26_Msk instead */ +#define PIO_OWDR_P27_Pos 27 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P27_Msk (_U_(0x1) << PIO_OWDR_P27_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P27 PIO_OWDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P27_Msk instead */ +#define PIO_OWDR_P28_Pos 28 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P28_Msk (_U_(0x1) << PIO_OWDR_P28_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P28 PIO_OWDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P28_Msk instead */ +#define PIO_OWDR_P29_Pos 29 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P29_Msk (_U_(0x1) << PIO_OWDR_P29_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P29 PIO_OWDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P29_Msk instead */ +#define PIO_OWDR_P30_Pos 30 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P30_Msk (_U_(0x1) << PIO_OWDR_P30_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P30 PIO_OWDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P30_Msk instead */ +#define PIO_OWDR_P31_Pos 31 /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P31_Msk (_U_(0x1) << PIO_OWDR_P31_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P31 PIO_OWDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWDR_P31_Msk instead */ +#define PIO_OWDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWDR) Register MASK (Use PIO_OWDR_Msk instead) */ +#define PIO_OWDR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWDR) Register Mask */ + +#define PIO_OWDR_P_Pos 0 /**< (PIO_OWDR Position) Output Write Disable */ +#define PIO_OWDR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWDR_P_Pos) /**< (PIO_OWDR Mask) P */ +#define PIO_OWDR_P(value) (PIO_OWDR_P_Msk & ((value) << PIO_OWDR_P_Pos)) + +/* -------- PIO_OWSR : (PIO Offset: 0xa8) (R/ 32) Output Write Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Output Write Status */ + uint32_t P1:1; /**< bit: 1 Output Write Status */ + uint32_t P2:1; /**< bit: 2 Output Write Status */ + uint32_t P3:1; /**< bit: 3 Output Write Status */ + uint32_t P4:1; /**< bit: 4 Output Write Status */ + uint32_t P5:1; /**< bit: 5 Output Write Status */ + uint32_t P6:1; /**< bit: 6 Output Write Status */ + uint32_t P7:1; /**< bit: 7 Output Write Status */ + uint32_t P8:1; /**< bit: 8 Output Write Status */ + uint32_t P9:1; /**< bit: 9 Output Write Status */ + uint32_t P10:1; /**< bit: 10 Output Write Status */ + uint32_t P11:1; /**< bit: 11 Output Write Status */ + uint32_t P12:1; /**< bit: 12 Output Write Status */ + uint32_t P13:1; /**< bit: 13 Output Write Status */ + uint32_t P14:1; /**< bit: 14 Output Write Status */ + uint32_t P15:1; /**< bit: 15 Output Write Status */ + uint32_t P16:1; /**< bit: 16 Output Write Status */ + uint32_t P17:1; /**< bit: 17 Output Write Status */ + uint32_t P18:1; /**< bit: 18 Output Write Status */ + uint32_t P19:1; /**< bit: 19 Output Write Status */ + uint32_t P20:1; /**< bit: 20 Output Write Status */ + uint32_t P21:1; /**< bit: 21 Output Write Status */ + uint32_t P22:1; /**< bit: 22 Output Write Status */ + uint32_t P23:1; /**< bit: 23 Output Write Status */ + uint32_t P24:1; /**< bit: 24 Output Write Status */ + uint32_t P25:1; /**< bit: 25 Output Write Status */ + uint32_t P26:1; /**< bit: 26 Output Write Status */ + uint32_t P27:1; /**< bit: 27 Output Write Status */ + uint32_t P28:1; /**< bit: 28 Output Write Status */ + uint32_t P29:1; /**< bit: 29 Output Write Status */ + uint32_t P30:1; /**< bit: 30 Output Write Status */ + uint32_t P31:1; /**< bit: 31 Output Write Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Output Write Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_OWSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_OWSR_OFFSET (0xA8) /**< (PIO_OWSR) Output Write Status Register Offset */ + +#define PIO_OWSR_P0_Pos 0 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P0_Msk (_U_(0x1) << PIO_OWSR_P0_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P0 PIO_OWSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P0_Msk instead */ +#define PIO_OWSR_P1_Pos 1 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P1_Msk (_U_(0x1) << PIO_OWSR_P1_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P1 PIO_OWSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P1_Msk instead */ +#define PIO_OWSR_P2_Pos 2 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P2_Msk (_U_(0x1) << PIO_OWSR_P2_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P2 PIO_OWSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P2_Msk instead */ +#define PIO_OWSR_P3_Pos 3 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P3_Msk (_U_(0x1) << PIO_OWSR_P3_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P3 PIO_OWSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P3_Msk instead */ +#define PIO_OWSR_P4_Pos 4 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P4_Msk (_U_(0x1) << PIO_OWSR_P4_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P4 PIO_OWSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P4_Msk instead */ +#define PIO_OWSR_P5_Pos 5 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P5_Msk (_U_(0x1) << PIO_OWSR_P5_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P5 PIO_OWSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P5_Msk instead */ +#define PIO_OWSR_P6_Pos 6 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P6_Msk (_U_(0x1) << PIO_OWSR_P6_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P6 PIO_OWSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P6_Msk instead */ +#define PIO_OWSR_P7_Pos 7 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P7_Msk (_U_(0x1) << PIO_OWSR_P7_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P7 PIO_OWSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P7_Msk instead */ +#define PIO_OWSR_P8_Pos 8 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P8_Msk (_U_(0x1) << PIO_OWSR_P8_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P8 PIO_OWSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P8_Msk instead */ +#define PIO_OWSR_P9_Pos 9 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P9_Msk (_U_(0x1) << PIO_OWSR_P9_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P9 PIO_OWSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P9_Msk instead */ +#define PIO_OWSR_P10_Pos 10 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P10_Msk (_U_(0x1) << PIO_OWSR_P10_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P10 PIO_OWSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P10_Msk instead */ +#define PIO_OWSR_P11_Pos 11 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P11_Msk (_U_(0x1) << PIO_OWSR_P11_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P11 PIO_OWSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P11_Msk instead */ +#define PIO_OWSR_P12_Pos 12 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P12_Msk (_U_(0x1) << PIO_OWSR_P12_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P12 PIO_OWSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P12_Msk instead */ +#define PIO_OWSR_P13_Pos 13 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P13_Msk (_U_(0x1) << PIO_OWSR_P13_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P13 PIO_OWSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P13_Msk instead */ +#define PIO_OWSR_P14_Pos 14 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P14_Msk (_U_(0x1) << PIO_OWSR_P14_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P14 PIO_OWSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P14_Msk instead */ +#define PIO_OWSR_P15_Pos 15 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P15_Msk (_U_(0x1) << PIO_OWSR_P15_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P15 PIO_OWSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P15_Msk instead */ +#define PIO_OWSR_P16_Pos 16 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P16_Msk (_U_(0x1) << PIO_OWSR_P16_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P16 PIO_OWSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P16_Msk instead */ +#define PIO_OWSR_P17_Pos 17 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P17_Msk (_U_(0x1) << PIO_OWSR_P17_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P17 PIO_OWSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P17_Msk instead */ +#define PIO_OWSR_P18_Pos 18 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P18_Msk (_U_(0x1) << PIO_OWSR_P18_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P18 PIO_OWSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P18_Msk instead */ +#define PIO_OWSR_P19_Pos 19 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P19_Msk (_U_(0x1) << PIO_OWSR_P19_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P19 PIO_OWSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P19_Msk instead */ +#define PIO_OWSR_P20_Pos 20 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P20_Msk (_U_(0x1) << PIO_OWSR_P20_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P20 PIO_OWSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P20_Msk instead */ +#define PIO_OWSR_P21_Pos 21 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P21_Msk (_U_(0x1) << PIO_OWSR_P21_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P21 PIO_OWSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P21_Msk instead */ +#define PIO_OWSR_P22_Pos 22 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P22_Msk (_U_(0x1) << PIO_OWSR_P22_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P22 PIO_OWSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P22_Msk instead */ +#define PIO_OWSR_P23_Pos 23 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P23_Msk (_U_(0x1) << PIO_OWSR_P23_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P23 PIO_OWSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P23_Msk instead */ +#define PIO_OWSR_P24_Pos 24 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P24_Msk (_U_(0x1) << PIO_OWSR_P24_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P24 PIO_OWSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P24_Msk instead */ +#define PIO_OWSR_P25_Pos 25 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P25_Msk (_U_(0x1) << PIO_OWSR_P25_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P25 PIO_OWSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P25_Msk instead */ +#define PIO_OWSR_P26_Pos 26 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P26_Msk (_U_(0x1) << PIO_OWSR_P26_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P26 PIO_OWSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P26_Msk instead */ +#define PIO_OWSR_P27_Pos 27 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P27_Msk (_U_(0x1) << PIO_OWSR_P27_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P27 PIO_OWSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P27_Msk instead */ +#define PIO_OWSR_P28_Pos 28 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P28_Msk (_U_(0x1) << PIO_OWSR_P28_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P28 PIO_OWSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P28_Msk instead */ +#define PIO_OWSR_P29_Pos 29 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P29_Msk (_U_(0x1) << PIO_OWSR_P29_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P29 PIO_OWSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P29_Msk instead */ +#define PIO_OWSR_P30_Pos 30 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P30_Msk (_U_(0x1) << PIO_OWSR_P30_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P30 PIO_OWSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P30_Msk instead */ +#define PIO_OWSR_P31_Pos 31 /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P31_Msk (_U_(0x1) << PIO_OWSR_P31_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P31 PIO_OWSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_OWSR_P31_Msk instead */ +#define PIO_OWSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_OWSR) Register MASK (Use PIO_OWSR_Msk instead) */ +#define PIO_OWSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWSR) Register Mask */ + +#define PIO_OWSR_P_Pos 0 /**< (PIO_OWSR Position) Output Write Status */ +#define PIO_OWSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWSR_P_Pos) /**< (PIO_OWSR Mask) P */ +#define PIO_OWSR_P(value) (PIO_OWSR_P_Msk & ((value) << PIO_OWSR_P_Pos)) + +/* -------- PIO_AIMER : (PIO Offset: 0xb0) (/W 32) Additional Interrupt Modes Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Enable */ + uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Enable */ + uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Enable */ + uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Enable */ + uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Enable */ + uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Enable */ + uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Enable */ + uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Enable */ + uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Enable */ + uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Enable */ + uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Enable */ + uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Enable */ + uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Enable */ + uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Enable */ + uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Enable */ + uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Enable */ + uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Enable */ + uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Enable */ + uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Enable */ + uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Enable */ + uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Enable */ + uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Enable */ + uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Enable */ + uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Enable */ + uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Enable */ + uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Enable */ + uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Enable */ + uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Enable */ + uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Enable */ + uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Enable */ + uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Enable */ + uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_AIMER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_AIMER_OFFSET (0xB0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Register Offset */ + +#define PIO_AIMER_P0_Pos 0 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P0_Msk (_U_(0x1) << PIO_AIMER_P0_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P0 PIO_AIMER_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P0_Msk instead */ +#define PIO_AIMER_P1_Pos 1 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P1_Msk (_U_(0x1) << PIO_AIMER_P1_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P1 PIO_AIMER_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P1_Msk instead */ +#define PIO_AIMER_P2_Pos 2 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P2_Msk (_U_(0x1) << PIO_AIMER_P2_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P2 PIO_AIMER_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P2_Msk instead */ +#define PIO_AIMER_P3_Pos 3 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P3_Msk (_U_(0x1) << PIO_AIMER_P3_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P3 PIO_AIMER_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P3_Msk instead */ +#define PIO_AIMER_P4_Pos 4 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P4_Msk (_U_(0x1) << PIO_AIMER_P4_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P4 PIO_AIMER_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P4_Msk instead */ +#define PIO_AIMER_P5_Pos 5 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P5_Msk (_U_(0x1) << PIO_AIMER_P5_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P5 PIO_AIMER_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P5_Msk instead */ +#define PIO_AIMER_P6_Pos 6 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P6_Msk (_U_(0x1) << PIO_AIMER_P6_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P6 PIO_AIMER_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P6_Msk instead */ +#define PIO_AIMER_P7_Pos 7 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P7_Msk (_U_(0x1) << PIO_AIMER_P7_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P7 PIO_AIMER_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P7_Msk instead */ +#define PIO_AIMER_P8_Pos 8 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P8_Msk (_U_(0x1) << PIO_AIMER_P8_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P8 PIO_AIMER_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P8_Msk instead */ +#define PIO_AIMER_P9_Pos 9 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P9_Msk (_U_(0x1) << PIO_AIMER_P9_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P9 PIO_AIMER_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P9_Msk instead */ +#define PIO_AIMER_P10_Pos 10 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P10_Msk (_U_(0x1) << PIO_AIMER_P10_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P10 PIO_AIMER_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P10_Msk instead */ +#define PIO_AIMER_P11_Pos 11 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P11_Msk (_U_(0x1) << PIO_AIMER_P11_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P11 PIO_AIMER_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P11_Msk instead */ +#define PIO_AIMER_P12_Pos 12 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P12_Msk (_U_(0x1) << PIO_AIMER_P12_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P12 PIO_AIMER_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P12_Msk instead */ +#define PIO_AIMER_P13_Pos 13 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P13_Msk (_U_(0x1) << PIO_AIMER_P13_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P13 PIO_AIMER_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P13_Msk instead */ +#define PIO_AIMER_P14_Pos 14 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P14_Msk (_U_(0x1) << PIO_AIMER_P14_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P14 PIO_AIMER_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P14_Msk instead */ +#define PIO_AIMER_P15_Pos 15 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P15_Msk (_U_(0x1) << PIO_AIMER_P15_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P15 PIO_AIMER_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P15_Msk instead */ +#define PIO_AIMER_P16_Pos 16 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P16_Msk (_U_(0x1) << PIO_AIMER_P16_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P16 PIO_AIMER_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P16_Msk instead */ +#define PIO_AIMER_P17_Pos 17 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P17_Msk (_U_(0x1) << PIO_AIMER_P17_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P17 PIO_AIMER_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P17_Msk instead */ +#define PIO_AIMER_P18_Pos 18 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P18_Msk (_U_(0x1) << PIO_AIMER_P18_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P18 PIO_AIMER_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P18_Msk instead */ +#define PIO_AIMER_P19_Pos 19 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P19_Msk (_U_(0x1) << PIO_AIMER_P19_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P19 PIO_AIMER_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P19_Msk instead */ +#define PIO_AIMER_P20_Pos 20 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P20_Msk (_U_(0x1) << PIO_AIMER_P20_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P20 PIO_AIMER_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P20_Msk instead */ +#define PIO_AIMER_P21_Pos 21 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P21_Msk (_U_(0x1) << PIO_AIMER_P21_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P21 PIO_AIMER_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P21_Msk instead */ +#define PIO_AIMER_P22_Pos 22 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P22_Msk (_U_(0x1) << PIO_AIMER_P22_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P22 PIO_AIMER_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P22_Msk instead */ +#define PIO_AIMER_P23_Pos 23 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P23_Msk (_U_(0x1) << PIO_AIMER_P23_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P23 PIO_AIMER_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P23_Msk instead */ +#define PIO_AIMER_P24_Pos 24 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P24_Msk (_U_(0x1) << PIO_AIMER_P24_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P24 PIO_AIMER_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P24_Msk instead */ +#define PIO_AIMER_P25_Pos 25 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P25_Msk (_U_(0x1) << PIO_AIMER_P25_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P25 PIO_AIMER_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P25_Msk instead */ +#define PIO_AIMER_P26_Pos 26 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P26_Msk (_U_(0x1) << PIO_AIMER_P26_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P26 PIO_AIMER_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P26_Msk instead */ +#define PIO_AIMER_P27_Pos 27 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P27_Msk (_U_(0x1) << PIO_AIMER_P27_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P27 PIO_AIMER_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P27_Msk instead */ +#define PIO_AIMER_P28_Pos 28 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P28_Msk (_U_(0x1) << PIO_AIMER_P28_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P28 PIO_AIMER_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P28_Msk instead */ +#define PIO_AIMER_P29_Pos 29 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P29_Msk (_U_(0x1) << PIO_AIMER_P29_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P29 PIO_AIMER_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P29_Msk instead */ +#define PIO_AIMER_P30_Pos 30 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P30_Msk (_U_(0x1) << PIO_AIMER_P30_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P30 PIO_AIMER_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P30_Msk instead */ +#define PIO_AIMER_P31_Pos 31 /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P31_Msk (_U_(0x1) << PIO_AIMER_P31_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P31 PIO_AIMER_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMER_P31_Msk instead */ +#define PIO_AIMER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMER) Register MASK (Use PIO_AIMER_Msk instead) */ +#define PIO_AIMER_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMER) Register Mask */ + +#define PIO_AIMER_P_Pos 0 /**< (PIO_AIMER Position) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMER_P_Pos) /**< (PIO_AIMER Mask) P */ +#define PIO_AIMER_P(value) (PIO_AIMER_P_Msk & ((value) << PIO_AIMER_P_Pos)) + +/* -------- PIO_AIMDR : (PIO Offset: 0xb4) (/W 32) Additional Interrupt Modes Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Additional Interrupt Modes Disable */ + uint32_t P1:1; /**< bit: 1 Additional Interrupt Modes Disable */ + uint32_t P2:1; /**< bit: 2 Additional Interrupt Modes Disable */ + uint32_t P3:1; /**< bit: 3 Additional Interrupt Modes Disable */ + uint32_t P4:1; /**< bit: 4 Additional Interrupt Modes Disable */ + uint32_t P5:1; /**< bit: 5 Additional Interrupt Modes Disable */ + uint32_t P6:1; /**< bit: 6 Additional Interrupt Modes Disable */ + uint32_t P7:1; /**< bit: 7 Additional Interrupt Modes Disable */ + uint32_t P8:1; /**< bit: 8 Additional Interrupt Modes Disable */ + uint32_t P9:1; /**< bit: 9 Additional Interrupt Modes Disable */ + uint32_t P10:1; /**< bit: 10 Additional Interrupt Modes Disable */ + uint32_t P11:1; /**< bit: 11 Additional Interrupt Modes Disable */ + uint32_t P12:1; /**< bit: 12 Additional Interrupt Modes Disable */ + uint32_t P13:1; /**< bit: 13 Additional Interrupt Modes Disable */ + uint32_t P14:1; /**< bit: 14 Additional Interrupt Modes Disable */ + uint32_t P15:1; /**< bit: 15 Additional Interrupt Modes Disable */ + uint32_t P16:1; /**< bit: 16 Additional Interrupt Modes Disable */ + uint32_t P17:1; /**< bit: 17 Additional Interrupt Modes Disable */ + uint32_t P18:1; /**< bit: 18 Additional Interrupt Modes Disable */ + uint32_t P19:1; /**< bit: 19 Additional Interrupt Modes Disable */ + uint32_t P20:1; /**< bit: 20 Additional Interrupt Modes Disable */ + uint32_t P21:1; /**< bit: 21 Additional Interrupt Modes Disable */ + uint32_t P22:1; /**< bit: 22 Additional Interrupt Modes Disable */ + uint32_t P23:1; /**< bit: 23 Additional Interrupt Modes Disable */ + uint32_t P24:1; /**< bit: 24 Additional Interrupt Modes Disable */ + uint32_t P25:1; /**< bit: 25 Additional Interrupt Modes Disable */ + uint32_t P26:1; /**< bit: 26 Additional Interrupt Modes Disable */ + uint32_t P27:1; /**< bit: 27 Additional Interrupt Modes Disable */ + uint32_t P28:1; /**< bit: 28 Additional Interrupt Modes Disable */ + uint32_t P29:1; /**< bit: 29 Additional Interrupt Modes Disable */ + uint32_t P30:1; /**< bit: 30 Additional Interrupt Modes Disable */ + uint32_t P31:1; /**< bit: 31 Additional Interrupt Modes Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Additional Interrupt Modes Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_AIMDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_AIMDR_OFFSET (0xB4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Register Offset */ + +#define PIO_AIMDR_P0_Pos 0 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P0_Msk (_U_(0x1) << PIO_AIMDR_P0_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P0 PIO_AIMDR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P0_Msk instead */ +#define PIO_AIMDR_P1_Pos 1 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P1_Msk (_U_(0x1) << PIO_AIMDR_P1_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P1 PIO_AIMDR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P1_Msk instead */ +#define PIO_AIMDR_P2_Pos 2 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P2_Msk (_U_(0x1) << PIO_AIMDR_P2_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P2 PIO_AIMDR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P2_Msk instead */ +#define PIO_AIMDR_P3_Pos 3 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P3_Msk (_U_(0x1) << PIO_AIMDR_P3_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P3 PIO_AIMDR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P3_Msk instead */ +#define PIO_AIMDR_P4_Pos 4 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P4_Msk (_U_(0x1) << PIO_AIMDR_P4_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P4 PIO_AIMDR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P4_Msk instead */ +#define PIO_AIMDR_P5_Pos 5 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P5_Msk (_U_(0x1) << PIO_AIMDR_P5_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P5 PIO_AIMDR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P5_Msk instead */ +#define PIO_AIMDR_P6_Pos 6 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P6_Msk (_U_(0x1) << PIO_AIMDR_P6_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P6 PIO_AIMDR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P6_Msk instead */ +#define PIO_AIMDR_P7_Pos 7 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P7_Msk (_U_(0x1) << PIO_AIMDR_P7_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P7 PIO_AIMDR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P7_Msk instead */ +#define PIO_AIMDR_P8_Pos 8 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P8_Msk (_U_(0x1) << PIO_AIMDR_P8_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P8 PIO_AIMDR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P8_Msk instead */ +#define PIO_AIMDR_P9_Pos 9 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P9_Msk (_U_(0x1) << PIO_AIMDR_P9_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P9 PIO_AIMDR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P9_Msk instead */ +#define PIO_AIMDR_P10_Pos 10 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P10_Msk (_U_(0x1) << PIO_AIMDR_P10_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P10 PIO_AIMDR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P10_Msk instead */ +#define PIO_AIMDR_P11_Pos 11 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P11_Msk (_U_(0x1) << PIO_AIMDR_P11_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P11 PIO_AIMDR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P11_Msk instead */ +#define PIO_AIMDR_P12_Pos 12 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P12_Msk (_U_(0x1) << PIO_AIMDR_P12_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P12 PIO_AIMDR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P12_Msk instead */ +#define PIO_AIMDR_P13_Pos 13 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P13_Msk (_U_(0x1) << PIO_AIMDR_P13_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P13 PIO_AIMDR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P13_Msk instead */ +#define PIO_AIMDR_P14_Pos 14 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P14_Msk (_U_(0x1) << PIO_AIMDR_P14_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P14 PIO_AIMDR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P14_Msk instead */ +#define PIO_AIMDR_P15_Pos 15 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P15_Msk (_U_(0x1) << PIO_AIMDR_P15_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P15 PIO_AIMDR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P15_Msk instead */ +#define PIO_AIMDR_P16_Pos 16 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P16_Msk (_U_(0x1) << PIO_AIMDR_P16_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P16 PIO_AIMDR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P16_Msk instead */ +#define PIO_AIMDR_P17_Pos 17 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P17_Msk (_U_(0x1) << PIO_AIMDR_P17_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P17 PIO_AIMDR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P17_Msk instead */ +#define PIO_AIMDR_P18_Pos 18 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P18_Msk (_U_(0x1) << PIO_AIMDR_P18_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P18 PIO_AIMDR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P18_Msk instead */ +#define PIO_AIMDR_P19_Pos 19 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P19_Msk (_U_(0x1) << PIO_AIMDR_P19_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P19 PIO_AIMDR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P19_Msk instead */ +#define PIO_AIMDR_P20_Pos 20 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P20_Msk (_U_(0x1) << PIO_AIMDR_P20_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P20 PIO_AIMDR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P20_Msk instead */ +#define PIO_AIMDR_P21_Pos 21 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P21_Msk (_U_(0x1) << PIO_AIMDR_P21_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P21 PIO_AIMDR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P21_Msk instead */ +#define PIO_AIMDR_P22_Pos 22 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P22_Msk (_U_(0x1) << PIO_AIMDR_P22_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P22 PIO_AIMDR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P22_Msk instead */ +#define PIO_AIMDR_P23_Pos 23 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P23_Msk (_U_(0x1) << PIO_AIMDR_P23_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P23 PIO_AIMDR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P23_Msk instead */ +#define PIO_AIMDR_P24_Pos 24 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P24_Msk (_U_(0x1) << PIO_AIMDR_P24_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P24 PIO_AIMDR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P24_Msk instead */ +#define PIO_AIMDR_P25_Pos 25 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P25_Msk (_U_(0x1) << PIO_AIMDR_P25_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P25 PIO_AIMDR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P25_Msk instead */ +#define PIO_AIMDR_P26_Pos 26 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P26_Msk (_U_(0x1) << PIO_AIMDR_P26_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P26 PIO_AIMDR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P26_Msk instead */ +#define PIO_AIMDR_P27_Pos 27 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P27_Msk (_U_(0x1) << PIO_AIMDR_P27_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P27 PIO_AIMDR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P27_Msk instead */ +#define PIO_AIMDR_P28_Pos 28 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P28_Msk (_U_(0x1) << PIO_AIMDR_P28_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P28 PIO_AIMDR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P28_Msk instead */ +#define PIO_AIMDR_P29_Pos 29 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P29_Msk (_U_(0x1) << PIO_AIMDR_P29_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P29 PIO_AIMDR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P29_Msk instead */ +#define PIO_AIMDR_P30_Pos 30 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P30_Msk (_U_(0x1) << PIO_AIMDR_P30_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P30 PIO_AIMDR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P30_Msk instead */ +#define PIO_AIMDR_P31_Pos 31 /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P31_Msk (_U_(0x1) << PIO_AIMDR_P31_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P31 PIO_AIMDR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMDR_P31_Msk instead */ +#define PIO_AIMDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMDR) Register MASK (Use PIO_AIMDR_Msk instead) */ +#define PIO_AIMDR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMDR) Register Mask */ + +#define PIO_AIMDR_P_Pos 0 /**< (PIO_AIMDR Position) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMDR_P_Pos) /**< (PIO_AIMDR Mask) P */ +#define PIO_AIMDR_P(value) (PIO_AIMDR_P_Msk & ((value) << PIO_AIMDR_P_Pos)) + +/* -------- PIO_AIMMR : (PIO Offset: 0xb8) (R/ 32) Additional Interrupt Modes Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 IO Line Index */ + uint32_t P1:1; /**< bit: 1 IO Line Index */ + uint32_t P2:1; /**< bit: 2 IO Line Index */ + uint32_t P3:1; /**< bit: 3 IO Line Index */ + uint32_t P4:1; /**< bit: 4 IO Line Index */ + uint32_t P5:1; /**< bit: 5 IO Line Index */ + uint32_t P6:1; /**< bit: 6 IO Line Index */ + uint32_t P7:1; /**< bit: 7 IO Line Index */ + uint32_t P8:1; /**< bit: 8 IO Line Index */ + uint32_t P9:1; /**< bit: 9 IO Line Index */ + uint32_t P10:1; /**< bit: 10 IO Line Index */ + uint32_t P11:1; /**< bit: 11 IO Line Index */ + uint32_t P12:1; /**< bit: 12 IO Line Index */ + uint32_t P13:1; /**< bit: 13 IO Line Index */ + uint32_t P14:1; /**< bit: 14 IO Line Index */ + uint32_t P15:1; /**< bit: 15 IO Line Index */ + uint32_t P16:1; /**< bit: 16 IO Line Index */ + uint32_t P17:1; /**< bit: 17 IO Line Index */ + uint32_t P18:1; /**< bit: 18 IO Line Index */ + uint32_t P19:1; /**< bit: 19 IO Line Index */ + uint32_t P20:1; /**< bit: 20 IO Line Index */ + uint32_t P21:1; /**< bit: 21 IO Line Index */ + uint32_t P22:1; /**< bit: 22 IO Line Index */ + uint32_t P23:1; /**< bit: 23 IO Line Index */ + uint32_t P24:1; /**< bit: 24 IO Line Index */ + uint32_t P25:1; /**< bit: 25 IO Line Index */ + uint32_t P26:1; /**< bit: 26 IO Line Index */ + uint32_t P27:1; /**< bit: 27 IO Line Index */ + uint32_t P28:1; /**< bit: 28 IO Line Index */ + uint32_t P29:1; /**< bit: 29 IO Line Index */ + uint32_t P30:1; /**< bit: 30 IO Line Index */ + uint32_t P31:1; /**< bit: 31 IO Line Index */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 IO Line Index */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_AIMMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_AIMMR_OFFSET (0xB8) /**< (PIO_AIMMR) Additional Interrupt Modes Mask Register Offset */ + +#define PIO_AIMMR_P0_Pos 0 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P0_Msk (_U_(0x1) << PIO_AIMMR_P0_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P0 PIO_AIMMR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P0_Msk instead */ +#define PIO_AIMMR_P1_Pos 1 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P1_Msk (_U_(0x1) << PIO_AIMMR_P1_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P1 PIO_AIMMR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P1_Msk instead */ +#define PIO_AIMMR_P2_Pos 2 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P2_Msk (_U_(0x1) << PIO_AIMMR_P2_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P2 PIO_AIMMR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P2_Msk instead */ +#define PIO_AIMMR_P3_Pos 3 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P3_Msk (_U_(0x1) << PIO_AIMMR_P3_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P3 PIO_AIMMR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P3_Msk instead */ +#define PIO_AIMMR_P4_Pos 4 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P4_Msk (_U_(0x1) << PIO_AIMMR_P4_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P4 PIO_AIMMR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P4_Msk instead */ +#define PIO_AIMMR_P5_Pos 5 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P5_Msk (_U_(0x1) << PIO_AIMMR_P5_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P5 PIO_AIMMR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P5_Msk instead */ +#define PIO_AIMMR_P6_Pos 6 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P6_Msk (_U_(0x1) << PIO_AIMMR_P6_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P6 PIO_AIMMR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P6_Msk instead */ +#define PIO_AIMMR_P7_Pos 7 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P7_Msk (_U_(0x1) << PIO_AIMMR_P7_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P7 PIO_AIMMR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P7_Msk instead */ +#define PIO_AIMMR_P8_Pos 8 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P8_Msk (_U_(0x1) << PIO_AIMMR_P8_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P8 PIO_AIMMR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P8_Msk instead */ +#define PIO_AIMMR_P9_Pos 9 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P9_Msk (_U_(0x1) << PIO_AIMMR_P9_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P9 PIO_AIMMR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P9_Msk instead */ +#define PIO_AIMMR_P10_Pos 10 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P10_Msk (_U_(0x1) << PIO_AIMMR_P10_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P10 PIO_AIMMR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P10_Msk instead */ +#define PIO_AIMMR_P11_Pos 11 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P11_Msk (_U_(0x1) << PIO_AIMMR_P11_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P11 PIO_AIMMR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P11_Msk instead */ +#define PIO_AIMMR_P12_Pos 12 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P12_Msk (_U_(0x1) << PIO_AIMMR_P12_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P12 PIO_AIMMR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P12_Msk instead */ +#define PIO_AIMMR_P13_Pos 13 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P13_Msk (_U_(0x1) << PIO_AIMMR_P13_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P13 PIO_AIMMR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P13_Msk instead */ +#define PIO_AIMMR_P14_Pos 14 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P14_Msk (_U_(0x1) << PIO_AIMMR_P14_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P14 PIO_AIMMR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P14_Msk instead */ +#define PIO_AIMMR_P15_Pos 15 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P15_Msk (_U_(0x1) << PIO_AIMMR_P15_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P15 PIO_AIMMR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P15_Msk instead */ +#define PIO_AIMMR_P16_Pos 16 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P16_Msk (_U_(0x1) << PIO_AIMMR_P16_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P16 PIO_AIMMR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P16_Msk instead */ +#define PIO_AIMMR_P17_Pos 17 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P17_Msk (_U_(0x1) << PIO_AIMMR_P17_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P17 PIO_AIMMR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P17_Msk instead */ +#define PIO_AIMMR_P18_Pos 18 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P18_Msk (_U_(0x1) << PIO_AIMMR_P18_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P18 PIO_AIMMR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P18_Msk instead */ +#define PIO_AIMMR_P19_Pos 19 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P19_Msk (_U_(0x1) << PIO_AIMMR_P19_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P19 PIO_AIMMR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P19_Msk instead */ +#define PIO_AIMMR_P20_Pos 20 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P20_Msk (_U_(0x1) << PIO_AIMMR_P20_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P20 PIO_AIMMR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P20_Msk instead */ +#define PIO_AIMMR_P21_Pos 21 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P21_Msk (_U_(0x1) << PIO_AIMMR_P21_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P21 PIO_AIMMR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P21_Msk instead */ +#define PIO_AIMMR_P22_Pos 22 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P22_Msk (_U_(0x1) << PIO_AIMMR_P22_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P22 PIO_AIMMR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P22_Msk instead */ +#define PIO_AIMMR_P23_Pos 23 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P23_Msk (_U_(0x1) << PIO_AIMMR_P23_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P23 PIO_AIMMR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P23_Msk instead */ +#define PIO_AIMMR_P24_Pos 24 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P24_Msk (_U_(0x1) << PIO_AIMMR_P24_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P24 PIO_AIMMR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P24_Msk instead */ +#define PIO_AIMMR_P25_Pos 25 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P25_Msk (_U_(0x1) << PIO_AIMMR_P25_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P25 PIO_AIMMR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P25_Msk instead */ +#define PIO_AIMMR_P26_Pos 26 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P26_Msk (_U_(0x1) << PIO_AIMMR_P26_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P26 PIO_AIMMR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P26_Msk instead */ +#define PIO_AIMMR_P27_Pos 27 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P27_Msk (_U_(0x1) << PIO_AIMMR_P27_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P27 PIO_AIMMR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P27_Msk instead */ +#define PIO_AIMMR_P28_Pos 28 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P28_Msk (_U_(0x1) << PIO_AIMMR_P28_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P28 PIO_AIMMR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P28_Msk instead */ +#define PIO_AIMMR_P29_Pos 29 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P29_Msk (_U_(0x1) << PIO_AIMMR_P29_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P29 PIO_AIMMR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P29_Msk instead */ +#define PIO_AIMMR_P30_Pos 30 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P30_Msk (_U_(0x1) << PIO_AIMMR_P30_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P30 PIO_AIMMR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P30_Msk instead */ +#define PIO_AIMMR_P31_Pos 31 /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P31_Msk (_U_(0x1) << PIO_AIMMR_P31_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P31 PIO_AIMMR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_AIMMR_P31_Msk instead */ +#define PIO_AIMMR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_AIMMR) Register MASK (Use PIO_AIMMR_Msk instead) */ +#define PIO_AIMMR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMMR) Register Mask */ + +#define PIO_AIMMR_P_Pos 0 /**< (PIO_AIMMR Position) IO Line Index */ +#define PIO_AIMMR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMMR_P_Pos) /**< (PIO_AIMMR Mask) P */ +#define PIO_AIMMR_P(value) (PIO_AIMMR_P_Msk & ((value) << PIO_AIMMR_P_Pos)) + +/* -------- PIO_ESR : (PIO Offset: 0xc0) (/W 32) Edge Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Edge Interrupt Selection */ + uint32_t P1:1; /**< bit: 1 Edge Interrupt Selection */ + uint32_t P2:1; /**< bit: 2 Edge Interrupt Selection */ + uint32_t P3:1; /**< bit: 3 Edge Interrupt Selection */ + uint32_t P4:1; /**< bit: 4 Edge Interrupt Selection */ + uint32_t P5:1; /**< bit: 5 Edge Interrupt Selection */ + uint32_t P6:1; /**< bit: 6 Edge Interrupt Selection */ + uint32_t P7:1; /**< bit: 7 Edge Interrupt Selection */ + uint32_t P8:1; /**< bit: 8 Edge Interrupt Selection */ + uint32_t P9:1; /**< bit: 9 Edge Interrupt Selection */ + uint32_t P10:1; /**< bit: 10 Edge Interrupt Selection */ + uint32_t P11:1; /**< bit: 11 Edge Interrupt Selection */ + uint32_t P12:1; /**< bit: 12 Edge Interrupt Selection */ + uint32_t P13:1; /**< bit: 13 Edge Interrupt Selection */ + uint32_t P14:1; /**< bit: 14 Edge Interrupt Selection */ + uint32_t P15:1; /**< bit: 15 Edge Interrupt Selection */ + uint32_t P16:1; /**< bit: 16 Edge Interrupt Selection */ + uint32_t P17:1; /**< bit: 17 Edge Interrupt Selection */ + uint32_t P18:1; /**< bit: 18 Edge Interrupt Selection */ + uint32_t P19:1; /**< bit: 19 Edge Interrupt Selection */ + uint32_t P20:1; /**< bit: 20 Edge Interrupt Selection */ + uint32_t P21:1; /**< bit: 21 Edge Interrupt Selection */ + uint32_t P22:1; /**< bit: 22 Edge Interrupt Selection */ + uint32_t P23:1; /**< bit: 23 Edge Interrupt Selection */ + uint32_t P24:1; /**< bit: 24 Edge Interrupt Selection */ + uint32_t P25:1; /**< bit: 25 Edge Interrupt Selection */ + uint32_t P26:1; /**< bit: 26 Edge Interrupt Selection */ + uint32_t P27:1; /**< bit: 27 Edge Interrupt Selection */ + uint32_t P28:1; /**< bit: 28 Edge Interrupt Selection */ + uint32_t P29:1; /**< bit: 29 Edge Interrupt Selection */ + uint32_t P30:1; /**< bit: 30 Edge Interrupt Selection */ + uint32_t P31:1; /**< bit: 31 Edge Interrupt Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Edge Interrupt Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ESR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ESR_OFFSET (0xC0) /**< (PIO_ESR) Edge Select Register Offset */ + +#define PIO_ESR_P0_Pos 0 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P0_Msk (_U_(0x1) << PIO_ESR_P0_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P0 PIO_ESR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P0_Msk instead */ +#define PIO_ESR_P1_Pos 1 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P1_Msk (_U_(0x1) << PIO_ESR_P1_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P1 PIO_ESR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P1_Msk instead */ +#define PIO_ESR_P2_Pos 2 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P2_Msk (_U_(0x1) << PIO_ESR_P2_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P2 PIO_ESR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P2_Msk instead */ +#define PIO_ESR_P3_Pos 3 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P3_Msk (_U_(0x1) << PIO_ESR_P3_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P3 PIO_ESR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P3_Msk instead */ +#define PIO_ESR_P4_Pos 4 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P4_Msk (_U_(0x1) << PIO_ESR_P4_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P4 PIO_ESR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P4_Msk instead */ +#define PIO_ESR_P5_Pos 5 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P5_Msk (_U_(0x1) << PIO_ESR_P5_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P5 PIO_ESR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P5_Msk instead */ +#define PIO_ESR_P6_Pos 6 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P6_Msk (_U_(0x1) << PIO_ESR_P6_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P6 PIO_ESR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P6_Msk instead */ +#define PIO_ESR_P7_Pos 7 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P7_Msk (_U_(0x1) << PIO_ESR_P7_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P7 PIO_ESR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P7_Msk instead */ +#define PIO_ESR_P8_Pos 8 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P8_Msk (_U_(0x1) << PIO_ESR_P8_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P8 PIO_ESR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P8_Msk instead */ +#define PIO_ESR_P9_Pos 9 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P9_Msk (_U_(0x1) << PIO_ESR_P9_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P9 PIO_ESR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P9_Msk instead */ +#define PIO_ESR_P10_Pos 10 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P10_Msk (_U_(0x1) << PIO_ESR_P10_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P10 PIO_ESR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P10_Msk instead */ +#define PIO_ESR_P11_Pos 11 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P11_Msk (_U_(0x1) << PIO_ESR_P11_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P11 PIO_ESR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P11_Msk instead */ +#define PIO_ESR_P12_Pos 12 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P12_Msk (_U_(0x1) << PIO_ESR_P12_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P12 PIO_ESR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P12_Msk instead */ +#define PIO_ESR_P13_Pos 13 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P13_Msk (_U_(0x1) << PIO_ESR_P13_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P13 PIO_ESR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P13_Msk instead */ +#define PIO_ESR_P14_Pos 14 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P14_Msk (_U_(0x1) << PIO_ESR_P14_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P14 PIO_ESR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P14_Msk instead */ +#define PIO_ESR_P15_Pos 15 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P15_Msk (_U_(0x1) << PIO_ESR_P15_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P15 PIO_ESR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P15_Msk instead */ +#define PIO_ESR_P16_Pos 16 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P16_Msk (_U_(0x1) << PIO_ESR_P16_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P16 PIO_ESR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P16_Msk instead */ +#define PIO_ESR_P17_Pos 17 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P17_Msk (_U_(0x1) << PIO_ESR_P17_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P17 PIO_ESR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P17_Msk instead */ +#define PIO_ESR_P18_Pos 18 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P18_Msk (_U_(0x1) << PIO_ESR_P18_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P18 PIO_ESR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P18_Msk instead */ +#define PIO_ESR_P19_Pos 19 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P19_Msk (_U_(0x1) << PIO_ESR_P19_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P19 PIO_ESR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P19_Msk instead */ +#define PIO_ESR_P20_Pos 20 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P20_Msk (_U_(0x1) << PIO_ESR_P20_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P20 PIO_ESR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P20_Msk instead */ +#define PIO_ESR_P21_Pos 21 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P21_Msk (_U_(0x1) << PIO_ESR_P21_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P21 PIO_ESR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P21_Msk instead */ +#define PIO_ESR_P22_Pos 22 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P22_Msk (_U_(0x1) << PIO_ESR_P22_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P22 PIO_ESR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P22_Msk instead */ +#define PIO_ESR_P23_Pos 23 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P23_Msk (_U_(0x1) << PIO_ESR_P23_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P23 PIO_ESR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P23_Msk instead */ +#define PIO_ESR_P24_Pos 24 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P24_Msk (_U_(0x1) << PIO_ESR_P24_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P24 PIO_ESR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P24_Msk instead */ +#define PIO_ESR_P25_Pos 25 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P25_Msk (_U_(0x1) << PIO_ESR_P25_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P25 PIO_ESR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P25_Msk instead */ +#define PIO_ESR_P26_Pos 26 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P26_Msk (_U_(0x1) << PIO_ESR_P26_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P26 PIO_ESR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P26_Msk instead */ +#define PIO_ESR_P27_Pos 27 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P27_Msk (_U_(0x1) << PIO_ESR_P27_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P27 PIO_ESR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P27_Msk instead */ +#define PIO_ESR_P28_Pos 28 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P28_Msk (_U_(0x1) << PIO_ESR_P28_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P28 PIO_ESR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P28_Msk instead */ +#define PIO_ESR_P29_Pos 29 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P29_Msk (_U_(0x1) << PIO_ESR_P29_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P29 PIO_ESR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P29_Msk instead */ +#define PIO_ESR_P30_Pos 30 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P30_Msk (_U_(0x1) << PIO_ESR_P30_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P30 PIO_ESR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P30_Msk instead */ +#define PIO_ESR_P31_Pos 31 /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P31_Msk (_U_(0x1) << PIO_ESR_P31_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P31 PIO_ESR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ESR_P31_Msk instead */ +#define PIO_ESR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ESR) Register MASK (Use PIO_ESR_Msk instead) */ +#define PIO_ESR_Msk _U_(0xFFFFFFFF) /**< (PIO_ESR) Register Mask */ + +#define PIO_ESR_P_Pos 0 /**< (PIO_ESR Position) Edge Interrupt Selection */ +#define PIO_ESR_P_Msk (_U_(0xFFFFFFFF) << PIO_ESR_P_Pos) /**< (PIO_ESR Mask) P */ +#define PIO_ESR_P(value) (PIO_ESR_P_Msk & ((value) << PIO_ESR_P_Pos)) + +/* -------- PIO_LSR : (PIO Offset: 0xc4) (/W 32) Level Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Level Interrupt Selection */ + uint32_t P1:1; /**< bit: 1 Level Interrupt Selection */ + uint32_t P2:1; /**< bit: 2 Level Interrupt Selection */ + uint32_t P3:1; /**< bit: 3 Level Interrupt Selection */ + uint32_t P4:1; /**< bit: 4 Level Interrupt Selection */ + uint32_t P5:1; /**< bit: 5 Level Interrupt Selection */ + uint32_t P6:1; /**< bit: 6 Level Interrupt Selection */ + uint32_t P7:1; /**< bit: 7 Level Interrupt Selection */ + uint32_t P8:1; /**< bit: 8 Level Interrupt Selection */ + uint32_t P9:1; /**< bit: 9 Level Interrupt Selection */ + uint32_t P10:1; /**< bit: 10 Level Interrupt Selection */ + uint32_t P11:1; /**< bit: 11 Level Interrupt Selection */ + uint32_t P12:1; /**< bit: 12 Level Interrupt Selection */ + uint32_t P13:1; /**< bit: 13 Level Interrupt Selection */ + uint32_t P14:1; /**< bit: 14 Level Interrupt Selection */ + uint32_t P15:1; /**< bit: 15 Level Interrupt Selection */ + uint32_t P16:1; /**< bit: 16 Level Interrupt Selection */ + uint32_t P17:1; /**< bit: 17 Level Interrupt Selection */ + uint32_t P18:1; /**< bit: 18 Level Interrupt Selection */ + uint32_t P19:1; /**< bit: 19 Level Interrupt Selection */ + uint32_t P20:1; /**< bit: 20 Level Interrupt Selection */ + uint32_t P21:1; /**< bit: 21 Level Interrupt Selection */ + uint32_t P22:1; /**< bit: 22 Level Interrupt Selection */ + uint32_t P23:1; /**< bit: 23 Level Interrupt Selection */ + uint32_t P24:1; /**< bit: 24 Level Interrupt Selection */ + uint32_t P25:1; /**< bit: 25 Level Interrupt Selection */ + uint32_t P26:1; /**< bit: 26 Level Interrupt Selection */ + uint32_t P27:1; /**< bit: 27 Level Interrupt Selection */ + uint32_t P28:1; /**< bit: 28 Level Interrupt Selection */ + uint32_t P29:1; /**< bit: 29 Level Interrupt Selection */ + uint32_t P30:1; /**< bit: 30 Level Interrupt Selection */ + uint32_t P31:1; /**< bit: 31 Level Interrupt Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Level Interrupt Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_LSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_LSR_OFFSET (0xC4) /**< (PIO_LSR) Level Select Register Offset */ + +#define PIO_LSR_P0_Pos 0 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P0_Msk (_U_(0x1) << PIO_LSR_P0_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P0 PIO_LSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P0_Msk instead */ +#define PIO_LSR_P1_Pos 1 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P1_Msk (_U_(0x1) << PIO_LSR_P1_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P1 PIO_LSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P1_Msk instead */ +#define PIO_LSR_P2_Pos 2 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P2_Msk (_U_(0x1) << PIO_LSR_P2_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P2 PIO_LSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P2_Msk instead */ +#define PIO_LSR_P3_Pos 3 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P3_Msk (_U_(0x1) << PIO_LSR_P3_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P3 PIO_LSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P3_Msk instead */ +#define PIO_LSR_P4_Pos 4 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P4_Msk (_U_(0x1) << PIO_LSR_P4_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P4 PIO_LSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P4_Msk instead */ +#define PIO_LSR_P5_Pos 5 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P5_Msk (_U_(0x1) << PIO_LSR_P5_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P5 PIO_LSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P5_Msk instead */ +#define PIO_LSR_P6_Pos 6 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P6_Msk (_U_(0x1) << PIO_LSR_P6_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P6 PIO_LSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P6_Msk instead */ +#define PIO_LSR_P7_Pos 7 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P7_Msk (_U_(0x1) << PIO_LSR_P7_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P7 PIO_LSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P7_Msk instead */ +#define PIO_LSR_P8_Pos 8 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P8_Msk (_U_(0x1) << PIO_LSR_P8_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P8 PIO_LSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P8_Msk instead */ +#define PIO_LSR_P9_Pos 9 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P9_Msk (_U_(0x1) << PIO_LSR_P9_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P9 PIO_LSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P9_Msk instead */ +#define PIO_LSR_P10_Pos 10 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P10_Msk (_U_(0x1) << PIO_LSR_P10_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P10 PIO_LSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P10_Msk instead */ +#define PIO_LSR_P11_Pos 11 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P11_Msk (_U_(0x1) << PIO_LSR_P11_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P11 PIO_LSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P11_Msk instead */ +#define PIO_LSR_P12_Pos 12 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P12_Msk (_U_(0x1) << PIO_LSR_P12_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P12 PIO_LSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P12_Msk instead */ +#define PIO_LSR_P13_Pos 13 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P13_Msk (_U_(0x1) << PIO_LSR_P13_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P13 PIO_LSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P13_Msk instead */ +#define PIO_LSR_P14_Pos 14 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P14_Msk (_U_(0x1) << PIO_LSR_P14_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P14 PIO_LSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P14_Msk instead */ +#define PIO_LSR_P15_Pos 15 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P15_Msk (_U_(0x1) << PIO_LSR_P15_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P15 PIO_LSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P15_Msk instead */ +#define PIO_LSR_P16_Pos 16 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P16_Msk (_U_(0x1) << PIO_LSR_P16_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P16 PIO_LSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P16_Msk instead */ +#define PIO_LSR_P17_Pos 17 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P17_Msk (_U_(0x1) << PIO_LSR_P17_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P17 PIO_LSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P17_Msk instead */ +#define PIO_LSR_P18_Pos 18 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P18_Msk (_U_(0x1) << PIO_LSR_P18_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P18 PIO_LSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P18_Msk instead */ +#define PIO_LSR_P19_Pos 19 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P19_Msk (_U_(0x1) << PIO_LSR_P19_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P19 PIO_LSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P19_Msk instead */ +#define PIO_LSR_P20_Pos 20 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P20_Msk (_U_(0x1) << PIO_LSR_P20_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P20 PIO_LSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P20_Msk instead */ +#define PIO_LSR_P21_Pos 21 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P21_Msk (_U_(0x1) << PIO_LSR_P21_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P21 PIO_LSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P21_Msk instead */ +#define PIO_LSR_P22_Pos 22 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P22_Msk (_U_(0x1) << PIO_LSR_P22_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P22 PIO_LSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P22_Msk instead */ +#define PIO_LSR_P23_Pos 23 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P23_Msk (_U_(0x1) << PIO_LSR_P23_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P23 PIO_LSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P23_Msk instead */ +#define PIO_LSR_P24_Pos 24 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P24_Msk (_U_(0x1) << PIO_LSR_P24_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P24 PIO_LSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P24_Msk instead */ +#define PIO_LSR_P25_Pos 25 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P25_Msk (_U_(0x1) << PIO_LSR_P25_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P25 PIO_LSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P25_Msk instead */ +#define PIO_LSR_P26_Pos 26 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P26_Msk (_U_(0x1) << PIO_LSR_P26_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P26 PIO_LSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P26_Msk instead */ +#define PIO_LSR_P27_Pos 27 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P27_Msk (_U_(0x1) << PIO_LSR_P27_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P27 PIO_LSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P27_Msk instead */ +#define PIO_LSR_P28_Pos 28 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P28_Msk (_U_(0x1) << PIO_LSR_P28_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P28 PIO_LSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P28_Msk instead */ +#define PIO_LSR_P29_Pos 29 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P29_Msk (_U_(0x1) << PIO_LSR_P29_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P29 PIO_LSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P29_Msk instead */ +#define PIO_LSR_P30_Pos 30 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P30_Msk (_U_(0x1) << PIO_LSR_P30_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P30 PIO_LSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P30_Msk instead */ +#define PIO_LSR_P31_Pos 31 /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P31_Msk (_U_(0x1) << PIO_LSR_P31_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P31 PIO_LSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LSR_P31_Msk instead */ +#define PIO_LSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_LSR) Register MASK (Use PIO_LSR_Msk instead) */ +#define PIO_LSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LSR) Register Mask */ + +#define PIO_LSR_P_Pos 0 /**< (PIO_LSR Position) Level Interrupt Selection */ +#define PIO_LSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LSR_P_Pos) /**< (PIO_LSR Mask) P */ +#define PIO_LSR_P(value) (PIO_LSR_P_Msk & ((value) << PIO_LSR_P_Pos)) + +/* -------- PIO_ELSR : (PIO Offset: 0xc8) (R/ 32) Edge/Level Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Edge/Level Interrupt Source Selection */ + uint32_t P1:1; /**< bit: 1 Edge/Level Interrupt Source Selection */ + uint32_t P2:1; /**< bit: 2 Edge/Level Interrupt Source Selection */ + uint32_t P3:1; /**< bit: 3 Edge/Level Interrupt Source Selection */ + uint32_t P4:1; /**< bit: 4 Edge/Level Interrupt Source Selection */ + uint32_t P5:1; /**< bit: 5 Edge/Level Interrupt Source Selection */ + uint32_t P6:1; /**< bit: 6 Edge/Level Interrupt Source Selection */ + uint32_t P7:1; /**< bit: 7 Edge/Level Interrupt Source Selection */ + uint32_t P8:1; /**< bit: 8 Edge/Level Interrupt Source Selection */ + uint32_t P9:1; /**< bit: 9 Edge/Level Interrupt Source Selection */ + uint32_t P10:1; /**< bit: 10 Edge/Level Interrupt Source Selection */ + uint32_t P11:1; /**< bit: 11 Edge/Level Interrupt Source Selection */ + uint32_t P12:1; /**< bit: 12 Edge/Level Interrupt Source Selection */ + uint32_t P13:1; /**< bit: 13 Edge/Level Interrupt Source Selection */ + uint32_t P14:1; /**< bit: 14 Edge/Level Interrupt Source Selection */ + uint32_t P15:1; /**< bit: 15 Edge/Level Interrupt Source Selection */ + uint32_t P16:1; /**< bit: 16 Edge/Level Interrupt Source Selection */ + uint32_t P17:1; /**< bit: 17 Edge/Level Interrupt Source Selection */ + uint32_t P18:1; /**< bit: 18 Edge/Level Interrupt Source Selection */ + uint32_t P19:1; /**< bit: 19 Edge/Level Interrupt Source Selection */ + uint32_t P20:1; /**< bit: 20 Edge/Level Interrupt Source Selection */ + uint32_t P21:1; /**< bit: 21 Edge/Level Interrupt Source Selection */ + uint32_t P22:1; /**< bit: 22 Edge/Level Interrupt Source Selection */ + uint32_t P23:1; /**< bit: 23 Edge/Level Interrupt Source Selection */ + uint32_t P24:1; /**< bit: 24 Edge/Level Interrupt Source Selection */ + uint32_t P25:1; /**< bit: 25 Edge/Level Interrupt Source Selection */ + uint32_t P26:1; /**< bit: 26 Edge/Level Interrupt Source Selection */ + uint32_t P27:1; /**< bit: 27 Edge/Level Interrupt Source Selection */ + uint32_t P28:1; /**< bit: 28 Edge/Level Interrupt Source Selection */ + uint32_t P29:1; /**< bit: 29 Edge/Level Interrupt Source Selection */ + uint32_t P30:1; /**< bit: 30 Edge/Level Interrupt Source Selection */ + uint32_t P31:1; /**< bit: 31 Edge/Level Interrupt Source Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Edge/Level Interrupt Source Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_ELSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_ELSR_OFFSET (0xC8) /**< (PIO_ELSR) Edge/Level Status Register Offset */ + +#define PIO_ELSR_P0_Pos 0 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P0_Msk (_U_(0x1) << PIO_ELSR_P0_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P0 PIO_ELSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P0_Msk instead */ +#define PIO_ELSR_P1_Pos 1 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P1_Msk (_U_(0x1) << PIO_ELSR_P1_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P1 PIO_ELSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P1_Msk instead */ +#define PIO_ELSR_P2_Pos 2 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P2_Msk (_U_(0x1) << PIO_ELSR_P2_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P2 PIO_ELSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P2_Msk instead */ +#define PIO_ELSR_P3_Pos 3 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P3_Msk (_U_(0x1) << PIO_ELSR_P3_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P3 PIO_ELSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P3_Msk instead */ +#define PIO_ELSR_P4_Pos 4 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P4_Msk (_U_(0x1) << PIO_ELSR_P4_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P4 PIO_ELSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P4_Msk instead */ +#define PIO_ELSR_P5_Pos 5 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P5_Msk (_U_(0x1) << PIO_ELSR_P5_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P5 PIO_ELSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P5_Msk instead */ +#define PIO_ELSR_P6_Pos 6 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P6_Msk (_U_(0x1) << PIO_ELSR_P6_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P6 PIO_ELSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P6_Msk instead */ +#define PIO_ELSR_P7_Pos 7 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P7_Msk (_U_(0x1) << PIO_ELSR_P7_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P7 PIO_ELSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P7_Msk instead */ +#define PIO_ELSR_P8_Pos 8 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P8_Msk (_U_(0x1) << PIO_ELSR_P8_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P8 PIO_ELSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P8_Msk instead */ +#define PIO_ELSR_P9_Pos 9 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P9_Msk (_U_(0x1) << PIO_ELSR_P9_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P9 PIO_ELSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P9_Msk instead */ +#define PIO_ELSR_P10_Pos 10 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P10_Msk (_U_(0x1) << PIO_ELSR_P10_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P10 PIO_ELSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P10_Msk instead */ +#define PIO_ELSR_P11_Pos 11 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P11_Msk (_U_(0x1) << PIO_ELSR_P11_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P11 PIO_ELSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P11_Msk instead */ +#define PIO_ELSR_P12_Pos 12 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P12_Msk (_U_(0x1) << PIO_ELSR_P12_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P12 PIO_ELSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P12_Msk instead */ +#define PIO_ELSR_P13_Pos 13 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P13_Msk (_U_(0x1) << PIO_ELSR_P13_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P13 PIO_ELSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P13_Msk instead */ +#define PIO_ELSR_P14_Pos 14 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P14_Msk (_U_(0x1) << PIO_ELSR_P14_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P14 PIO_ELSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P14_Msk instead */ +#define PIO_ELSR_P15_Pos 15 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P15_Msk (_U_(0x1) << PIO_ELSR_P15_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P15 PIO_ELSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P15_Msk instead */ +#define PIO_ELSR_P16_Pos 16 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P16_Msk (_U_(0x1) << PIO_ELSR_P16_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P16 PIO_ELSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P16_Msk instead */ +#define PIO_ELSR_P17_Pos 17 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P17_Msk (_U_(0x1) << PIO_ELSR_P17_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P17 PIO_ELSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P17_Msk instead */ +#define PIO_ELSR_P18_Pos 18 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P18_Msk (_U_(0x1) << PIO_ELSR_P18_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P18 PIO_ELSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P18_Msk instead */ +#define PIO_ELSR_P19_Pos 19 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P19_Msk (_U_(0x1) << PIO_ELSR_P19_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P19 PIO_ELSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P19_Msk instead */ +#define PIO_ELSR_P20_Pos 20 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P20_Msk (_U_(0x1) << PIO_ELSR_P20_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P20 PIO_ELSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P20_Msk instead */ +#define PIO_ELSR_P21_Pos 21 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P21_Msk (_U_(0x1) << PIO_ELSR_P21_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P21 PIO_ELSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P21_Msk instead */ +#define PIO_ELSR_P22_Pos 22 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P22_Msk (_U_(0x1) << PIO_ELSR_P22_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P22 PIO_ELSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P22_Msk instead */ +#define PIO_ELSR_P23_Pos 23 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P23_Msk (_U_(0x1) << PIO_ELSR_P23_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P23 PIO_ELSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P23_Msk instead */ +#define PIO_ELSR_P24_Pos 24 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P24_Msk (_U_(0x1) << PIO_ELSR_P24_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P24 PIO_ELSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P24_Msk instead */ +#define PIO_ELSR_P25_Pos 25 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P25_Msk (_U_(0x1) << PIO_ELSR_P25_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P25 PIO_ELSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P25_Msk instead */ +#define PIO_ELSR_P26_Pos 26 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P26_Msk (_U_(0x1) << PIO_ELSR_P26_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P26 PIO_ELSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P26_Msk instead */ +#define PIO_ELSR_P27_Pos 27 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P27_Msk (_U_(0x1) << PIO_ELSR_P27_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P27 PIO_ELSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P27_Msk instead */ +#define PIO_ELSR_P28_Pos 28 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P28_Msk (_U_(0x1) << PIO_ELSR_P28_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P28 PIO_ELSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P28_Msk instead */ +#define PIO_ELSR_P29_Pos 29 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P29_Msk (_U_(0x1) << PIO_ELSR_P29_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P29 PIO_ELSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P29_Msk instead */ +#define PIO_ELSR_P30_Pos 30 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P30_Msk (_U_(0x1) << PIO_ELSR_P30_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P30 PIO_ELSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P30_Msk instead */ +#define PIO_ELSR_P31_Pos 31 /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P31_Msk (_U_(0x1) << PIO_ELSR_P31_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P31 PIO_ELSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_ELSR_P31_Msk instead */ +#define PIO_ELSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_ELSR) Register MASK (Use PIO_ELSR_Msk instead) */ +#define PIO_ELSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ELSR) Register Mask */ + +#define PIO_ELSR_P_Pos 0 /**< (PIO_ELSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ELSR_P_Pos) /**< (PIO_ELSR Mask) P */ +#define PIO_ELSR_P(value) (PIO_ELSR_P_Msk & ((value) << PIO_ELSR_P_Pos)) + +/* -------- PIO_FELLSR : (PIO Offset: 0xd0) (/W 32) Falling Edge/Low-Level Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P1:1; /**< bit: 1 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P2:1; /**< bit: 2 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P3:1; /**< bit: 3 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P4:1; /**< bit: 4 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P5:1; /**< bit: 5 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P6:1; /**< bit: 6 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P7:1; /**< bit: 7 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P8:1; /**< bit: 8 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P9:1; /**< bit: 9 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P10:1; /**< bit: 10 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P11:1; /**< bit: 11 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P12:1; /**< bit: 12 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P13:1; /**< bit: 13 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P14:1; /**< bit: 14 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P15:1; /**< bit: 15 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P16:1; /**< bit: 16 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P17:1; /**< bit: 17 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P18:1; /**< bit: 18 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P19:1; /**< bit: 19 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P20:1; /**< bit: 20 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P21:1; /**< bit: 21 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P22:1; /**< bit: 22 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P23:1; /**< bit: 23 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P24:1; /**< bit: 24 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P25:1; /**< bit: 25 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P26:1; /**< bit: 26 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P27:1; /**< bit: 27 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P28:1; /**< bit: 28 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P29:1; /**< bit: 29 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P30:1; /**< bit: 30 Falling Edge/Low-Level Interrupt Selection */ + uint32_t P31:1; /**< bit: 31 Falling Edge/Low-Level Interrupt Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Falling Edge/Low-Level Interrupt Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_FELLSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_FELLSR_OFFSET (0xD0) /**< (PIO_FELLSR) Falling Edge/Low-Level Select Register Offset */ + +#define PIO_FELLSR_P0_Pos 0 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P0_Msk (_U_(0x1) << PIO_FELLSR_P0_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P0 PIO_FELLSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P0_Msk instead */ +#define PIO_FELLSR_P1_Pos 1 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P1_Msk (_U_(0x1) << PIO_FELLSR_P1_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P1 PIO_FELLSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P1_Msk instead */ +#define PIO_FELLSR_P2_Pos 2 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P2_Msk (_U_(0x1) << PIO_FELLSR_P2_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P2 PIO_FELLSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P2_Msk instead */ +#define PIO_FELLSR_P3_Pos 3 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P3_Msk (_U_(0x1) << PIO_FELLSR_P3_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P3 PIO_FELLSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P3_Msk instead */ +#define PIO_FELLSR_P4_Pos 4 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P4_Msk (_U_(0x1) << PIO_FELLSR_P4_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P4 PIO_FELLSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P4_Msk instead */ +#define PIO_FELLSR_P5_Pos 5 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P5_Msk (_U_(0x1) << PIO_FELLSR_P5_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P5 PIO_FELLSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P5_Msk instead */ +#define PIO_FELLSR_P6_Pos 6 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P6_Msk (_U_(0x1) << PIO_FELLSR_P6_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P6 PIO_FELLSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P6_Msk instead */ +#define PIO_FELLSR_P7_Pos 7 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P7_Msk (_U_(0x1) << PIO_FELLSR_P7_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P7 PIO_FELLSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P7_Msk instead */ +#define PIO_FELLSR_P8_Pos 8 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P8_Msk (_U_(0x1) << PIO_FELLSR_P8_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P8 PIO_FELLSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P8_Msk instead */ +#define PIO_FELLSR_P9_Pos 9 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P9_Msk (_U_(0x1) << PIO_FELLSR_P9_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P9 PIO_FELLSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P9_Msk instead */ +#define PIO_FELLSR_P10_Pos 10 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P10_Msk (_U_(0x1) << PIO_FELLSR_P10_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P10 PIO_FELLSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P10_Msk instead */ +#define PIO_FELLSR_P11_Pos 11 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P11_Msk (_U_(0x1) << PIO_FELLSR_P11_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P11 PIO_FELLSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P11_Msk instead */ +#define PIO_FELLSR_P12_Pos 12 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P12_Msk (_U_(0x1) << PIO_FELLSR_P12_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P12 PIO_FELLSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P12_Msk instead */ +#define PIO_FELLSR_P13_Pos 13 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P13_Msk (_U_(0x1) << PIO_FELLSR_P13_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P13 PIO_FELLSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P13_Msk instead */ +#define PIO_FELLSR_P14_Pos 14 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P14_Msk (_U_(0x1) << PIO_FELLSR_P14_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P14 PIO_FELLSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P14_Msk instead */ +#define PIO_FELLSR_P15_Pos 15 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P15_Msk (_U_(0x1) << PIO_FELLSR_P15_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P15 PIO_FELLSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P15_Msk instead */ +#define PIO_FELLSR_P16_Pos 16 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P16_Msk (_U_(0x1) << PIO_FELLSR_P16_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P16 PIO_FELLSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P16_Msk instead */ +#define PIO_FELLSR_P17_Pos 17 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P17_Msk (_U_(0x1) << PIO_FELLSR_P17_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P17 PIO_FELLSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P17_Msk instead */ +#define PIO_FELLSR_P18_Pos 18 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P18_Msk (_U_(0x1) << PIO_FELLSR_P18_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P18 PIO_FELLSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P18_Msk instead */ +#define PIO_FELLSR_P19_Pos 19 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P19_Msk (_U_(0x1) << PIO_FELLSR_P19_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P19 PIO_FELLSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P19_Msk instead */ +#define PIO_FELLSR_P20_Pos 20 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P20_Msk (_U_(0x1) << PIO_FELLSR_P20_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P20 PIO_FELLSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P20_Msk instead */ +#define PIO_FELLSR_P21_Pos 21 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P21_Msk (_U_(0x1) << PIO_FELLSR_P21_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P21 PIO_FELLSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P21_Msk instead */ +#define PIO_FELLSR_P22_Pos 22 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P22_Msk (_U_(0x1) << PIO_FELLSR_P22_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P22 PIO_FELLSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P22_Msk instead */ +#define PIO_FELLSR_P23_Pos 23 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P23_Msk (_U_(0x1) << PIO_FELLSR_P23_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P23 PIO_FELLSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P23_Msk instead */ +#define PIO_FELLSR_P24_Pos 24 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P24_Msk (_U_(0x1) << PIO_FELLSR_P24_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P24 PIO_FELLSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P24_Msk instead */ +#define PIO_FELLSR_P25_Pos 25 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P25_Msk (_U_(0x1) << PIO_FELLSR_P25_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P25 PIO_FELLSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P25_Msk instead */ +#define PIO_FELLSR_P26_Pos 26 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P26_Msk (_U_(0x1) << PIO_FELLSR_P26_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P26 PIO_FELLSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P26_Msk instead */ +#define PIO_FELLSR_P27_Pos 27 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P27_Msk (_U_(0x1) << PIO_FELLSR_P27_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P27 PIO_FELLSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P27_Msk instead */ +#define PIO_FELLSR_P28_Pos 28 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P28_Msk (_U_(0x1) << PIO_FELLSR_P28_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P28 PIO_FELLSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P28_Msk instead */ +#define PIO_FELLSR_P29_Pos 29 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P29_Msk (_U_(0x1) << PIO_FELLSR_P29_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P29 PIO_FELLSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P29_Msk instead */ +#define PIO_FELLSR_P30_Pos 30 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P30_Msk (_U_(0x1) << PIO_FELLSR_P30_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P30 PIO_FELLSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P30_Msk instead */ +#define PIO_FELLSR_P31_Pos 31 /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P31_Msk (_U_(0x1) << PIO_FELLSR_P31_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P31 PIO_FELLSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FELLSR_P31_Msk instead */ +#define PIO_FELLSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_FELLSR) Register MASK (Use PIO_FELLSR_Msk instead) */ +#define PIO_FELLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FELLSR) Register Mask */ + +#define PIO_FELLSR_P_Pos 0 /**< (PIO_FELLSR Position) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FELLSR_P_Pos) /**< (PIO_FELLSR Mask) P */ +#define PIO_FELLSR_P(value) (PIO_FELLSR_P_Msk & ((value) << PIO_FELLSR_P_Pos)) + +/* -------- PIO_REHLSR : (PIO Offset: 0xd4) (/W 32) Rising Edge/High-Level Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Rising Edge/High-Level Interrupt Selection */ + uint32_t P1:1; /**< bit: 1 Rising Edge/High-Level Interrupt Selection */ + uint32_t P2:1; /**< bit: 2 Rising Edge/High-Level Interrupt Selection */ + uint32_t P3:1; /**< bit: 3 Rising Edge/High-Level Interrupt Selection */ + uint32_t P4:1; /**< bit: 4 Rising Edge/High-Level Interrupt Selection */ + uint32_t P5:1; /**< bit: 5 Rising Edge/High-Level Interrupt Selection */ + uint32_t P6:1; /**< bit: 6 Rising Edge/High-Level Interrupt Selection */ + uint32_t P7:1; /**< bit: 7 Rising Edge/High-Level Interrupt Selection */ + uint32_t P8:1; /**< bit: 8 Rising Edge/High-Level Interrupt Selection */ + uint32_t P9:1; /**< bit: 9 Rising Edge/High-Level Interrupt Selection */ + uint32_t P10:1; /**< bit: 10 Rising Edge/High-Level Interrupt Selection */ + uint32_t P11:1; /**< bit: 11 Rising Edge/High-Level Interrupt Selection */ + uint32_t P12:1; /**< bit: 12 Rising Edge/High-Level Interrupt Selection */ + uint32_t P13:1; /**< bit: 13 Rising Edge/High-Level Interrupt Selection */ + uint32_t P14:1; /**< bit: 14 Rising Edge/High-Level Interrupt Selection */ + uint32_t P15:1; /**< bit: 15 Rising Edge/High-Level Interrupt Selection */ + uint32_t P16:1; /**< bit: 16 Rising Edge/High-Level Interrupt Selection */ + uint32_t P17:1; /**< bit: 17 Rising Edge/High-Level Interrupt Selection */ + uint32_t P18:1; /**< bit: 18 Rising Edge/High-Level Interrupt Selection */ + uint32_t P19:1; /**< bit: 19 Rising Edge/High-Level Interrupt Selection */ + uint32_t P20:1; /**< bit: 20 Rising Edge/High-Level Interrupt Selection */ + uint32_t P21:1; /**< bit: 21 Rising Edge/High-Level Interrupt Selection */ + uint32_t P22:1; /**< bit: 22 Rising Edge/High-Level Interrupt Selection */ + uint32_t P23:1; /**< bit: 23 Rising Edge/High-Level Interrupt Selection */ + uint32_t P24:1; /**< bit: 24 Rising Edge/High-Level Interrupt Selection */ + uint32_t P25:1; /**< bit: 25 Rising Edge/High-Level Interrupt Selection */ + uint32_t P26:1; /**< bit: 26 Rising Edge/High-Level Interrupt Selection */ + uint32_t P27:1; /**< bit: 27 Rising Edge/High-Level Interrupt Selection */ + uint32_t P28:1; /**< bit: 28 Rising Edge/High-Level Interrupt Selection */ + uint32_t P29:1; /**< bit: 29 Rising Edge/High-Level Interrupt Selection */ + uint32_t P30:1; /**< bit: 30 Rising Edge/High-Level Interrupt Selection */ + uint32_t P31:1; /**< bit: 31 Rising Edge/High-Level Interrupt Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Rising Edge/High-Level Interrupt Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_REHLSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_REHLSR_OFFSET (0xD4) /**< (PIO_REHLSR) Rising Edge/High-Level Select Register Offset */ + +#define PIO_REHLSR_P0_Pos 0 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P0_Msk (_U_(0x1) << PIO_REHLSR_P0_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P0 PIO_REHLSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P0_Msk instead */ +#define PIO_REHLSR_P1_Pos 1 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P1_Msk (_U_(0x1) << PIO_REHLSR_P1_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P1 PIO_REHLSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P1_Msk instead */ +#define PIO_REHLSR_P2_Pos 2 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P2_Msk (_U_(0x1) << PIO_REHLSR_P2_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P2 PIO_REHLSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P2_Msk instead */ +#define PIO_REHLSR_P3_Pos 3 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P3_Msk (_U_(0x1) << PIO_REHLSR_P3_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P3 PIO_REHLSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P3_Msk instead */ +#define PIO_REHLSR_P4_Pos 4 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P4_Msk (_U_(0x1) << PIO_REHLSR_P4_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P4 PIO_REHLSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P4_Msk instead */ +#define PIO_REHLSR_P5_Pos 5 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P5_Msk (_U_(0x1) << PIO_REHLSR_P5_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P5 PIO_REHLSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P5_Msk instead */ +#define PIO_REHLSR_P6_Pos 6 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P6_Msk (_U_(0x1) << PIO_REHLSR_P6_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P6 PIO_REHLSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P6_Msk instead */ +#define PIO_REHLSR_P7_Pos 7 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P7_Msk (_U_(0x1) << PIO_REHLSR_P7_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P7 PIO_REHLSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P7_Msk instead */ +#define PIO_REHLSR_P8_Pos 8 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P8_Msk (_U_(0x1) << PIO_REHLSR_P8_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P8 PIO_REHLSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P8_Msk instead */ +#define PIO_REHLSR_P9_Pos 9 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P9_Msk (_U_(0x1) << PIO_REHLSR_P9_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P9 PIO_REHLSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P9_Msk instead */ +#define PIO_REHLSR_P10_Pos 10 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P10_Msk (_U_(0x1) << PIO_REHLSR_P10_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P10 PIO_REHLSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P10_Msk instead */ +#define PIO_REHLSR_P11_Pos 11 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P11_Msk (_U_(0x1) << PIO_REHLSR_P11_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P11 PIO_REHLSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P11_Msk instead */ +#define PIO_REHLSR_P12_Pos 12 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P12_Msk (_U_(0x1) << PIO_REHLSR_P12_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P12 PIO_REHLSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P12_Msk instead */ +#define PIO_REHLSR_P13_Pos 13 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P13_Msk (_U_(0x1) << PIO_REHLSR_P13_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P13 PIO_REHLSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P13_Msk instead */ +#define PIO_REHLSR_P14_Pos 14 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P14_Msk (_U_(0x1) << PIO_REHLSR_P14_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P14 PIO_REHLSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P14_Msk instead */ +#define PIO_REHLSR_P15_Pos 15 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P15_Msk (_U_(0x1) << PIO_REHLSR_P15_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P15 PIO_REHLSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P15_Msk instead */ +#define PIO_REHLSR_P16_Pos 16 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P16_Msk (_U_(0x1) << PIO_REHLSR_P16_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P16 PIO_REHLSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P16_Msk instead */ +#define PIO_REHLSR_P17_Pos 17 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P17_Msk (_U_(0x1) << PIO_REHLSR_P17_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P17 PIO_REHLSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P17_Msk instead */ +#define PIO_REHLSR_P18_Pos 18 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P18_Msk (_U_(0x1) << PIO_REHLSR_P18_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P18 PIO_REHLSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P18_Msk instead */ +#define PIO_REHLSR_P19_Pos 19 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P19_Msk (_U_(0x1) << PIO_REHLSR_P19_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P19 PIO_REHLSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P19_Msk instead */ +#define PIO_REHLSR_P20_Pos 20 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P20_Msk (_U_(0x1) << PIO_REHLSR_P20_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P20 PIO_REHLSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P20_Msk instead */ +#define PIO_REHLSR_P21_Pos 21 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P21_Msk (_U_(0x1) << PIO_REHLSR_P21_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P21 PIO_REHLSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P21_Msk instead */ +#define PIO_REHLSR_P22_Pos 22 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P22_Msk (_U_(0x1) << PIO_REHLSR_P22_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P22 PIO_REHLSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P22_Msk instead */ +#define PIO_REHLSR_P23_Pos 23 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P23_Msk (_U_(0x1) << PIO_REHLSR_P23_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P23 PIO_REHLSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P23_Msk instead */ +#define PIO_REHLSR_P24_Pos 24 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P24_Msk (_U_(0x1) << PIO_REHLSR_P24_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P24 PIO_REHLSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P24_Msk instead */ +#define PIO_REHLSR_P25_Pos 25 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P25_Msk (_U_(0x1) << PIO_REHLSR_P25_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P25 PIO_REHLSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P25_Msk instead */ +#define PIO_REHLSR_P26_Pos 26 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P26_Msk (_U_(0x1) << PIO_REHLSR_P26_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P26 PIO_REHLSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P26_Msk instead */ +#define PIO_REHLSR_P27_Pos 27 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P27_Msk (_U_(0x1) << PIO_REHLSR_P27_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P27 PIO_REHLSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P27_Msk instead */ +#define PIO_REHLSR_P28_Pos 28 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P28_Msk (_U_(0x1) << PIO_REHLSR_P28_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P28 PIO_REHLSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P28_Msk instead */ +#define PIO_REHLSR_P29_Pos 29 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P29_Msk (_U_(0x1) << PIO_REHLSR_P29_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P29 PIO_REHLSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P29_Msk instead */ +#define PIO_REHLSR_P30_Pos 30 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P30_Msk (_U_(0x1) << PIO_REHLSR_P30_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P30 PIO_REHLSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P30_Msk instead */ +#define PIO_REHLSR_P31_Pos 31 /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P31_Msk (_U_(0x1) << PIO_REHLSR_P31_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P31 PIO_REHLSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_REHLSR_P31_Msk instead */ +#define PIO_REHLSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_REHLSR) Register MASK (Use PIO_REHLSR_Msk instead) */ +#define PIO_REHLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_REHLSR) Register Mask */ + +#define PIO_REHLSR_P_Pos 0 /**< (PIO_REHLSR Position) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_REHLSR_P_Pos) /**< (PIO_REHLSR Mask) P */ +#define PIO_REHLSR_P(value) (PIO_REHLSR_P_Msk & ((value) << PIO_REHLSR_P_Pos)) + +/* -------- PIO_FRLHSR : (PIO Offset: 0xd8) (R/ 32) Fall/Rise - Low/High Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Edge/Level Interrupt Source Selection */ + uint32_t P1:1; /**< bit: 1 Edge/Level Interrupt Source Selection */ + uint32_t P2:1; /**< bit: 2 Edge/Level Interrupt Source Selection */ + uint32_t P3:1; /**< bit: 3 Edge/Level Interrupt Source Selection */ + uint32_t P4:1; /**< bit: 4 Edge/Level Interrupt Source Selection */ + uint32_t P5:1; /**< bit: 5 Edge/Level Interrupt Source Selection */ + uint32_t P6:1; /**< bit: 6 Edge/Level Interrupt Source Selection */ + uint32_t P7:1; /**< bit: 7 Edge/Level Interrupt Source Selection */ + uint32_t P8:1; /**< bit: 8 Edge/Level Interrupt Source Selection */ + uint32_t P9:1; /**< bit: 9 Edge/Level Interrupt Source Selection */ + uint32_t P10:1; /**< bit: 10 Edge/Level Interrupt Source Selection */ + uint32_t P11:1; /**< bit: 11 Edge/Level Interrupt Source Selection */ + uint32_t P12:1; /**< bit: 12 Edge/Level Interrupt Source Selection */ + uint32_t P13:1; /**< bit: 13 Edge/Level Interrupt Source Selection */ + uint32_t P14:1; /**< bit: 14 Edge/Level Interrupt Source Selection */ + uint32_t P15:1; /**< bit: 15 Edge/Level Interrupt Source Selection */ + uint32_t P16:1; /**< bit: 16 Edge/Level Interrupt Source Selection */ + uint32_t P17:1; /**< bit: 17 Edge/Level Interrupt Source Selection */ + uint32_t P18:1; /**< bit: 18 Edge/Level Interrupt Source Selection */ + uint32_t P19:1; /**< bit: 19 Edge/Level Interrupt Source Selection */ + uint32_t P20:1; /**< bit: 20 Edge/Level Interrupt Source Selection */ + uint32_t P21:1; /**< bit: 21 Edge/Level Interrupt Source Selection */ + uint32_t P22:1; /**< bit: 22 Edge/Level Interrupt Source Selection */ + uint32_t P23:1; /**< bit: 23 Edge/Level Interrupt Source Selection */ + uint32_t P24:1; /**< bit: 24 Edge/Level Interrupt Source Selection */ + uint32_t P25:1; /**< bit: 25 Edge/Level Interrupt Source Selection */ + uint32_t P26:1; /**< bit: 26 Edge/Level Interrupt Source Selection */ + uint32_t P27:1; /**< bit: 27 Edge/Level Interrupt Source Selection */ + uint32_t P28:1; /**< bit: 28 Edge/Level Interrupt Source Selection */ + uint32_t P29:1; /**< bit: 29 Edge/Level Interrupt Source Selection */ + uint32_t P30:1; /**< bit: 30 Edge/Level Interrupt Source Selection */ + uint32_t P31:1; /**< bit: 31 Edge/Level Interrupt Source Selection */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Edge/Level Interrupt Source Selection */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_FRLHSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_FRLHSR_OFFSET (0xD8) /**< (PIO_FRLHSR) Fall/Rise - Low/High Status Register Offset */ + +#define PIO_FRLHSR_P0_Pos 0 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P0_Msk (_U_(0x1) << PIO_FRLHSR_P0_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P0 PIO_FRLHSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P0_Msk instead */ +#define PIO_FRLHSR_P1_Pos 1 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P1_Msk (_U_(0x1) << PIO_FRLHSR_P1_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P1 PIO_FRLHSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P1_Msk instead */ +#define PIO_FRLHSR_P2_Pos 2 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P2_Msk (_U_(0x1) << PIO_FRLHSR_P2_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P2 PIO_FRLHSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P2_Msk instead */ +#define PIO_FRLHSR_P3_Pos 3 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P3_Msk (_U_(0x1) << PIO_FRLHSR_P3_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P3 PIO_FRLHSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P3_Msk instead */ +#define PIO_FRLHSR_P4_Pos 4 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P4_Msk (_U_(0x1) << PIO_FRLHSR_P4_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P4 PIO_FRLHSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P4_Msk instead */ +#define PIO_FRLHSR_P5_Pos 5 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P5_Msk (_U_(0x1) << PIO_FRLHSR_P5_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P5 PIO_FRLHSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P5_Msk instead */ +#define PIO_FRLHSR_P6_Pos 6 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P6_Msk (_U_(0x1) << PIO_FRLHSR_P6_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P6 PIO_FRLHSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P6_Msk instead */ +#define PIO_FRLHSR_P7_Pos 7 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P7_Msk (_U_(0x1) << PIO_FRLHSR_P7_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P7 PIO_FRLHSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P7_Msk instead */ +#define PIO_FRLHSR_P8_Pos 8 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P8_Msk (_U_(0x1) << PIO_FRLHSR_P8_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P8 PIO_FRLHSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P8_Msk instead */ +#define PIO_FRLHSR_P9_Pos 9 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P9_Msk (_U_(0x1) << PIO_FRLHSR_P9_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P9 PIO_FRLHSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P9_Msk instead */ +#define PIO_FRLHSR_P10_Pos 10 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P10_Msk (_U_(0x1) << PIO_FRLHSR_P10_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P10 PIO_FRLHSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P10_Msk instead */ +#define PIO_FRLHSR_P11_Pos 11 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P11_Msk (_U_(0x1) << PIO_FRLHSR_P11_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P11 PIO_FRLHSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P11_Msk instead */ +#define PIO_FRLHSR_P12_Pos 12 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P12_Msk (_U_(0x1) << PIO_FRLHSR_P12_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P12 PIO_FRLHSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P12_Msk instead */ +#define PIO_FRLHSR_P13_Pos 13 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P13_Msk (_U_(0x1) << PIO_FRLHSR_P13_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P13 PIO_FRLHSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P13_Msk instead */ +#define PIO_FRLHSR_P14_Pos 14 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P14_Msk (_U_(0x1) << PIO_FRLHSR_P14_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P14 PIO_FRLHSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P14_Msk instead */ +#define PIO_FRLHSR_P15_Pos 15 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P15_Msk (_U_(0x1) << PIO_FRLHSR_P15_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P15 PIO_FRLHSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P15_Msk instead */ +#define PIO_FRLHSR_P16_Pos 16 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P16_Msk (_U_(0x1) << PIO_FRLHSR_P16_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P16 PIO_FRLHSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P16_Msk instead */ +#define PIO_FRLHSR_P17_Pos 17 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P17_Msk (_U_(0x1) << PIO_FRLHSR_P17_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P17 PIO_FRLHSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P17_Msk instead */ +#define PIO_FRLHSR_P18_Pos 18 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P18_Msk (_U_(0x1) << PIO_FRLHSR_P18_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P18 PIO_FRLHSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P18_Msk instead */ +#define PIO_FRLHSR_P19_Pos 19 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P19_Msk (_U_(0x1) << PIO_FRLHSR_P19_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P19 PIO_FRLHSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P19_Msk instead */ +#define PIO_FRLHSR_P20_Pos 20 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P20_Msk (_U_(0x1) << PIO_FRLHSR_P20_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P20 PIO_FRLHSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P20_Msk instead */ +#define PIO_FRLHSR_P21_Pos 21 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P21_Msk (_U_(0x1) << PIO_FRLHSR_P21_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P21 PIO_FRLHSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P21_Msk instead */ +#define PIO_FRLHSR_P22_Pos 22 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P22_Msk (_U_(0x1) << PIO_FRLHSR_P22_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P22 PIO_FRLHSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P22_Msk instead */ +#define PIO_FRLHSR_P23_Pos 23 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P23_Msk (_U_(0x1) << PIO_FRLHSR_P23_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P23 PIO_FRLHSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P23_Msk instead */ +#define PIO_FRLHSR_P24_Pos 24 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P24_Msk (_U_(0x1) << PIO_FRLHSR_P24_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P24 PIO_FRLHSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P24_Msk instead */ +#define PIO_FRLHSR_P25_Pos 25 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P25_Msk (_U_(0x1) << PIO_FRLHSR_P25_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P25 PIO_FRLHSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P25_Msk instead */ +#define PIO_FRLHSR_P26_Pos 26 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P26_Msk (_U_(0x1) << PIO_FRLHSR_P26_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P26 PIO_FRLHSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P26_Msk instead */ +#define PIO_FRLHSR_P27_Pos 27 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P27_Msk (_U_(0x1) << PIO_FRLHSR_P27_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P27 PIO_FRLHSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P27_Msk instead */ +#define PIO_FRLHSR_P28_Pos 28 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P28_Msk (_U_(0x1) << PIO_FRLHSR_P28_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P28 PIO_FRLHSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P28_Msk instead */ +#define PIO_FRLHSR_P29_Pos 29 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P29_Msk (_U_(0x1) << PIO_FRLHSR_P29_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P29 PIO_FRLHSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P29_Msk instead */ +#define PIO_FRLHSR_P30_Pos 30 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P30_Msk (_U_(0x1) << PIO_FRLHSR_P30_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P30 PIO_FRLHSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P30_Msk instead */ +#define PIO_FRLHSR_P31_Pos 31 /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P31_Msk (_U_(0x1) << PIO_FRLHSR_P31_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P31 PIO_FRLHSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_FRLHSR_P31_Msk instead */ +#define PIO_FRLHSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_FRLHSR) Register MASK (Use PIO_FRLHSR_Msk instead) */ +#define PIO_FRLHSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FRLHSR) Register Mask */ + +#define PIO_FRLHSR_P_Pos 0 /**< (PIO_FRLHSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FRLHSR_P_Pos) /**< (PIO_FRLHSR Mask) P */ +#define PIO_FRLHSR_P(value) (PIO_FRLHSR_P_Msk & ((value) << PIO_FRLHSR_P_Pos)) + +/* -------- PIO_LOCKSR : (PIO Offset: 0xe0) (R/ 32) Lock Status -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t P0:1; /**< bit: 0 Lock Status */ + uint32_t P1:1; /**< bit: 1 Lock Status */ + uint32_t P2:1; /**< bit: 2 Lock Status */ + uint32_t P3:1; /**< bit: 3 Lock Status */ + uint32_t P4:1; /**< bit: 4 Lock Status */ + uint32_t P5:1; /**< bit: 5 Lock Status */ + uint32_t P6:1; /**< bit: 6 Lock Status */ + uint32_t P7:1; /**< bit: 7 Lock Status */ + uint32_t P8:1; /**< bit: 8 Lock Status */ + uint32_t P9:1; /**< bit: 9 Lock Status */ + uint32_t P10:1; /**< bit: 10 Lock Status */ + uint32_t P11:1; /**< bit: 11 Lock Status */ + uint32_t P12:1; /**< bit: 12 Lock Status */ + uint32_t P13:1; /**< bit: 13 Lock Status */ + uint32_t P14:1; /**< bit: 14 Lock Status */ + uint32_t P15:1; /**< bit: 15 Lock Status */ + uint32_t P16:1; /**< bit: 16 Lock Status */ + uint32_t P17:1; /**< bit: 17 Lock Status */ + uint32_t P18:1; /**< bit: 18 Lock Status */ + uint32_t P19:1; /**< bit: 19 Lock Status */ + uint32_t P20:1; /**< bit: 20 Lock Status */ + uint32_t P21:1; /**< bit: 21 Lock Status */ + uint32_t P22:1; /**< bit: 22 Lock Status */ + uint32_t P23:1; /**< bit: 23 Lock Status */ + uint32_t P24:1; /**< bit: 24 Lock Status */ + uint32_t P25:1; /**< bit: 25 Lock Status */ + uint32_t P26:1; /**< bit: 26 Lock Status */ + uint32_t P27:1; /**< bit: 27 Lock Status */ + uint32_t P28:1; /**< bit: 28 Lock Status */ + uint32_t P29:1; /**< bit: 29 Lock Status */ + uint32_t P30:1; /**< bit: 30 Lock Status */ + uint32_t P31:1; /**< bit: 31 Lock Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t P:32; /**< bit: 0..31 Lock Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_LOCKSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_LOCKSR_OFFSET (0xE0) /**< (PIO_LOCKSR) Lock Status Offset */ + +#define PIO_LOCKSR_P0_Pos 0 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P0_Msk (_U_(0x1) << PIO_LOCKSR_P0_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P0 PIO_LOCKSR_P0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P0_Msk instead */ +#define PIO_LOCKSR_P1_Pos 1 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P1_Msk (_U_(0x1) << PIO_LOCKSR_P1_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P1 PIO_LOCKSR_P1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P1_Msk instead */ +#define PIO_LOCKSR_P2_Pos 2 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P2_Msk (_U_(0x1) << PIO_LOCKSR_P2_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P2 PIO_LOCKSR_P2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P2_Msk instead */ +#define PIO_LOCKSR_P3_Pos 3 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P3_Msk (_U_(0x1) << PIO_LOCKSR_P3_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P3 PIO_LOCKSR_P3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P3_Msk instead */ +#define PIO_LOCKSR_P4_Pos 4 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P4_Msk (_U_(0x1) << PIO_LOCKSR_P4_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P4 PIO_LOCKSR_P4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P4_Msk instead */ +#define PIO_LOCKSR_P5_Pos 5 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P5_Msk (_U_(0x1) << PIO_LOCKSR_P5_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P5 PIO_LOCKSR_P5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P5_Msk instead */ +#define PIO_LOCKSR_P6_Pos 6 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P6_Msk (_U_(0x1) << PIO_LOCKSR_P6_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P6 PIO_LOCKSR_P6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P6_Msk instead */ +#define PIO_LOCKSR_P7_Pos 7 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P7_Msk (_U_(0x1) << PIO_LOCKSR_P7_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P7 PIO_LOCKSR_P7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P7_Msk instead */ +#define PIO_LOCKSR_P8_Pos 8 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P8_Msk (_U_(0x1) << PIO_LOCKSR_P8_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P8 PIO_LOCKSR_P8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P8_Msk instead */ +#define PIO_LOCKSR_P9_Pos 9 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P9_Msk (_U_(0x1) << PIO_LOCKSR_P9_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P9 PIO_LOCKSR_P9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P9_Msk instead */ +#define PIO_LOCKSR_P10_Pos 10 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P10_Msk (_U_(0x1) << PIO_LOCKSR_P10_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P10 PIO_LOCKSR_P10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P10_Msk instead */ +#define PIO_LOCKSR_P11_Pos 11 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P11_Msk (_U_(0x1) << PIO_LOCKSR_P11_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P11 PIO_LOCKSR_P11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P11_Msk instead */ +#define PIO_LOCKSR_P12_Pos 12 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P12_Msk (_U_(0x1) << PIO_LOCKSR_P12_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P12 PIO_LOCKSR_P12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P12_Msk instead */ +#define PIO_LOCKSR_P13_Pos 13 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P13_Msk (_U_(0x1) << PIO_LOCKSR_P13_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P13 PIO_LOCKSR_P13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P13_Msk instead */ +#define PIO_LOCKSR_P14_Pos 14 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P14_Msk (_U_(0x1) << PIO_LOCKSR_P14_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P14 PIO_LOCKSR_P14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P14_Msk instead */ +#define PIO_LOCKSR_P15_Pos 15 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P15_Msk (_U_(0x1) << PIO_LOCKSR_P15_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P15 PIO_LOCKSR_P15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P15_Msk instead */ +#define PIO_LOCKSR_P16_Pos 16 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P16_Msk (_U_(0x1) << PIO_LOCKSR_P16_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P16 PIO_LOCKSR_P16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P16_Msk instead */ +#define PIO_LOCKSR_P17_Pos 17 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P17_Msk (_U_(0x1) << PIO_LOCKSR_P17_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P17 PIO_LOCKSR_P17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P17_Msk instead */ +#define PIO_LOCKSR_P18_Pos 18 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P18_Msk (_U_(0x1) << PIO_LOCKSR_P18_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P18 PIO_LOCKSR_P18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P18_Msk instead */ +#define PIO_LOCKSR_P19_Pos 19 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P19_Msk (_U_(0x1) << PIO_LOCKSR_P19_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P19 PIO_LOCKSR_P19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P19_Msk instead */ +#define PIO_LOCKSR_P20_Pos 20 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P20_Msk (_U_(0x1) << PIO_LOCKSR_P20_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P20 PIO_LOCKSR_P20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P20_Msk instead */ +#define PIO_LOCKSR_P21_Pos 21 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P21_Msk (_U_(0x1) << PIO_LOCKSR_P21_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P21 PIO_LOCKSR_P21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P21_Msk instead */ +#define PIO_LOCKSR_P22_Pos 22 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P22_Msk (_U_(0x1) << PIO_LOCKSR_P22_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P22 PIO_LOCKSR_P22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P22_Msk instead */ +#define PIO_LOCKSR_P23_Pos 23 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P23_Msk (_U_(0x1) << PIO_LOCKSR_P23_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P23 PIO_LOCKSR_P23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P23_Msk instead */ +#define PIO_LOCKSR_P24_Pos 24 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P24_Msk (_U_(0x1) << PIO_LOCKSR_P24_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P24 PIO_LOCKSR_P24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P24_Msk instead */ +#define PIO_LOCKSR_P25_Pos 25 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P25_Msk (_U_(0x1) << PIO_LOCKSR_P25_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P25 PIO_LOCKSR_P25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P25_Msk instead */ +#define PIO_LOCKSR_P26_Pos 26 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P26_Msk (_U_(0x1) << PIO_LOCKSR_P26_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P26 PIO_LOCKSR_P26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P26_Msk instead */ +#define PIO_LOCKSR_P27_Pos 27 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P27_Msk (_U_(0x1) << PIO_LOCKSR_P27_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P27 PIO_LOCKSR_P27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P27_Msk instead */ +#define PIO_LOCKSR_P28_Pos 28 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P28_Msk (_U_(0x1) << PIO_LOCKSR_P28_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P28 PIO_LOCKSR_P28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P28_Msk instead */ +#define PIO_LOCKSR_P29_Pos 29 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P29_Msk (_U_(0x1) << PIO_LOCKSR_P29_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P29 PIO_LOCKSR_P29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P29_Msk instead */ +#define PIO_LOCKSR_P30_Pos 30 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P30_Msk (_U_(0x1) << PIO_LOCKSR_P30_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P30 PIO_LOCKSR_P30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P30_Msk instead */ +#define PIO_LOCKSR_P31_Pos 31 /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P31_Msk (_U_(0x1) << PIO_LOCKSR_P31_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P31 PIO_LOCKSR_P31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_LOCKSR_P31_Msk instead */ +#define PIO_LOCKSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_LOCKSR) Register MASK (Use PIO_LOCKSR_Msk instead) */ +#define PIO_LOCKSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LOCKSR) Register Mask */ + +#define PIO_LOCKSR_P_Pos 0 /**< (PIO_LOCKSR Position) Lock Status */ +#define PIO_LOCKSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LOCKSR_P_Pos) /**< (PIO_LOCKSR Mask) P */ +#define PIO_LOCKSR_P(value) (PIO_LOCKSR_P_Msk & ((value) << PIO_LOCKSR_P_Pos)) + +/* -------- PIO_WPMR : (PIO Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_WPMR_OFFSET (0xE4) /**< (PIO_WPMR) Write Protection Mode Register Offset */ + +#define PIO_WPMR_WPEN_Pos 0 /**< (PIO_WPMR) Write Protection Enable Position */ +#define PIO_WPMR_WPEN_Msk (_U_(0x1) << PIO_WPMR_WPEN_Pos) /**< (PIO_WPMR) Write Protection Enable Mask */ +#define PIO_WPMR_WPEN PIO_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_WPMR_WPEN_Msk instead */ +#define PIO_WPMR_WPKEY_Pos 8 /**< (PIO_WPMR) Write Protection Key Position */ +#define PIO_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Write Protection Key Mask */ +#define PIO_WPMR_WPKEY(value) (PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)) +#define PIO_WPMR_WPKEY_PASSWD_Val _U_(0x50494F) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define PIO_WPMR_WPKEY_PASSWD (PIO_WPMR_WPKEY_PASSWD_Val << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define PIO_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (PIO_WPMR) Register MASK (Use PIO_WPMR_Msk instead) */ +#define PIO_WPMR_Msk _U_(0xFFFFFF01) /**< (PIO_WPMR) Register Mask */ + + +/* -------- PIO_WPSR : (PIO Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_WPSR_OFFSET (0xE8) /**< (PIO_WPSR) Write Protection Status Register Offset */ + +#define PIO_WPSR_WPVS_Pos 0 /**< (PIO_WPSR) Write Protection Violation Status Position */ +#define PIO_WPSR_WPVS_Msk (_U_(0x1) << PIO_WPSR_WPVS_Pos) /**< (PIO_WPSR) Write Protection Violation Status Mask */ +#define PIO_WPSR_WPVS PIO_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_WPSR_WPVS_Msk instead */ +#define PIO_WPSR_WPVSRC_Pos 8 /**< (PIO_WPSR) Write Protection Violation Source Position */ +#define PIO_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PIO_WPSR_WPVSRC_Pos) /**< (PIO_WPSR) Write Protection Violation Source Mask */ +#define PIO_WPSR_WPVSRC(value) (PIO_WPSR_WPVSRC_Msk & ((value) << PIO_WPSR_WPVSRC_Pos)) +#define PIO_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (PIO_WPSR) Register MASK (Use PIO_WPSR_Msk instead) */ +#define PIO_WPSR_Msk _U_(0xFFFF01) /**< (PIO_WPSR) Register Mask */ + + +/* -------- PIO_SCHMITT : (PIO Offset: 0x100) (R/W 32) Schmitt Trigger Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SCHMITT0:1; /**< bit: 0 Schmitt Trigger Control */ + uint32_t SCHMITT1:1; /**< bit: 1 Schmitt Trigger Control */ + uint32_t SCHMITT2:1; /**< bit: 2 Schmitt Trigger Control */ + uint32_t SCHMITT3:1; /**< bit: 3 Schmitt Trigger Control */ + uint32_t SCHMITT4:1; /**< bit: 4 Schmitt Trigger Control */ + uint32_t SCHMITT5:1; /**< bit: 5 Schmitt Trigger Control */ + uint32_t SCHMITT6:1; /**< bit: 6 Schmitt Trigger Control */ + uint32_t SCHMITT7:1; /**< bit: 7 Schmitt Trigger Control */ + uint32_t SCHMITT8:1; /**< bit: 8 Schmitt Trigger Control */ + uint32_t SCHMITT9:1; /**< bit: 9 Schmitt Trigger Control */ + uint32_t SCHMITT10:1; /**< bit: 10 Schmitt Trigger Control */ + uint32_t SCHMITT11:1; /**< bit: 11 Schmitt Trigger Control */ + uint32_t SCHMITT12:1; /**< bit: 12 Schmitt Trigger Control */ + uint32_t SCHMITT13:1; /**< bit: 13 Schmitt Trigger Control */ + uint32_t SCHMITT14:1; /**< bit: 14 Schmitt Trigger Control */ + uint32_t SCHMITT15:1; /**< bit: 15 Schmitt Trigger Control */ + uint32_t SCHMITT16:1; /**< bit: 16 Schmitt Trigger Control */ + uint32_t SCHMITT17:1; /**< bit: 17 Schmitt Trigger Control */ + uint32_t SCHMITT18:1; /**< bit: 18 Schmitt Trigger Control */ + uint32_t SCHMITT19:1; /**< bit: 19 Schmitt Trigger Control */ + uint32_t SCHMITT20:1; /**< bit: 20 Schmitt Trigger Control */ + uint32_t SCHMITT21:1; /**< bit: 21 Schmitt Trigger Control */ + uint32_t SCHMITT22:1; /**< bit: 22 Schmitt Trigger Control */ + uint32_t SCHMITT23:1; /**< bit: 23 Schmitt Trigger Control */ + uint32_t SCHMITT24:1; /**< bit: 24 Schmitt Trigger Control */ + uint32_t SCHMITT25:1; /**< bit: 25 Schmitt Trigger Control */ + uint32_t SCHMITT26:1; /**< bit: 26 Schmitt Trigger Control */ + uint32_t SCHMITT27:1; /**< bit: 27 Schmitt Trigger Control */ + uint32_t SCHMITT28:1; /**< bit: 28 Schmitt Trigger Control */ + uint32_t SCHMITT29:1; /**< bit: 29 Schmitt Trigger Control */ + uint32_t SCHMITT30:1; /**< bit: 30 Schmitt Trigger Control */ + uint32_t SCHMITT31:1; /**< bit: 31 Schmitt Trigger Control */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SCHMITT:32; /**< bit: 0..31 Schmitt Trigger Control */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_SCHMITT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_SCHMITT_OFFSET (0x100) /**< (PIO_SCHMITT) Schmitt Trigger Register Offset */ + +#define PIO_SCHMITT_SCHMITT0_Pos 0 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT0_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT0_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT0 PIO_SCHMITT_SCHMITT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT0_Msk instead */ +#define PIO_SCHMITT_SCHMITT1_Pos 1 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT1_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT1_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT1 PIO_SCHMITT_SCHMITT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT1_Msk instead */ +#define PIO_SCHMITT_SCHMITT2_Pos 2 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT2_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT2_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT2 PIO_SCHMITT_SCHMITT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT2_Msk instead */ +#define PIO_SCHMITT_SCHMITT3_Pos 3 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT3_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT3_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT3 PIO_SCHMITT_SCHMITT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT3_Msk instead */ +#define PIO_SCHMITT_SCHMITT4_Pos 4 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT4_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT4_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT4 PIO_SCHMITT_SCHMITT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT4_Msk instead */ +#define PIO_SCHMITT_SCHMITT5_Pos 5 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT5_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT5_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT5 PIO_SCHMITT_SCHMITT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT5_Msk instead */ +#define PIO_SCHMITT_SCHMITT6_Pos 6 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT6_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT6_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT6 PIO_SCHMITT_SCHMITT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT6_Msk instead */ +#define PIO_SCHMITT_SCHMITT7_Pos 7 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT7_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT7_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT7 PIO_SCHMITT_SCHMITT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT7_Msk instead */ +#define PIO_SCHMITT_SCHMITT8_Pos 8 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT8_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT8_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT8 PIO_SCHMITT_SCHMITT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT8_Msk instead */ +#define PIO_SCHMITT_SCHMITT9_Pos 9 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT9_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT9_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT9 PIO_SCHMITT_SCHMITT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT9_Msk instead */ +#define PIO_SCHMITT_SCHMITT10_Pos 10 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT10_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT10_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT10 PIO_SCHMITT_SCHMITT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT10_Msk instead */ +#define PIO_SCHMITT_SCHMITT11_Pos 11 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT11_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT11_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT11 PIO_SCHMITT_SCHMITT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT11_Msk instead */ +#define PIO_SCHMITT_SCHMITT12_Pos 12 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT12_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT12_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT12 PIO_SCHMITT_SCHMITT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT12_Msk instead */ +#define PIO_SCHMITT_SCHMITT13_Pos 13 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT13_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT13_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT13 PIO_SCHMITT_SCHMITT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT13_Msk instead */ +#define PIO_SCHMITT_SCHMITT14_Pos 14 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT14_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT14_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT14 PIO_SCHMITT_SCHMITT14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT14_Msk instead */ +#define PIO_SCHMITT_SCHMITT15_Pos 15 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT15_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT15_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT15 PIO_SCHMITT_SCHMITT15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT15_Msk instead */ +#define PIO_SCHMITT_SCHMITT16_Pos 16 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT16_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT16_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT16 PIO_SCHMITT_SCHMITT16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT16_Msk instead */ +#define PIO_SCHMITT_SCHMITT17_Pos 17 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT17_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT17_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT17 PIO_SCHMITT_SCHMITT17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT17_Msk instead */ +#define PIO_SCHMITT_SCHMITT18_Pos 18 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT18_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT18_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT18 PIO_SCHMITT_SCHMITT18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT18_Msk instead */ +#define PIO_SCHMITT_SCHMITT19_Pos 19 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT19_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT19_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT19 PIO_SCHMITT_SCHMITT19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT19_Msk instead */ +#define PIO_SCHMITT_SCHMITT20_Pos 20 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT20_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT20_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT20 PIO_SCHMITT_SCHMITT20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT20_Msk instead */ +#define PIO_SCHMITT_SCHMITT21_Pos 21 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT21_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT21_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT21 PIO_SCHMITT_SCHMITT21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT21_Msk instead */ +#define PIO_SCHMITT_SCHMITT22_Pos 22 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT22_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT22_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT22 PIO_SCHMITT_SCHMITT22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT22_Msk instead */ +#define PIO_SCHMITT_SCHMITT23_Pos 23 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT23_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT23_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT23 PIO_SCHMITT_SCHMITT23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT23_Msk instead */ +#define PIO_SCHMITT_SCHMITT24_Pos 24 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT24_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT24_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT24 PIO_SCHMITT_SCHMITT24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT24_Msk instead */ +#define PIO_SCHMITT_SCHMITT25_Pos 25 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT25_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT25_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT25 PIO_SCHMITT_SCHMITT25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT25_Msk instead */ +#define PIO_SCHMITT_SCHMITT26_Pos 26 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT26_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT26_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT26 PIO_SCHMITT_SCHMITT26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT26_Msk instead */ +#define PIO_SCHMITT_SCHMITT27_Pos 27 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT27_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT27_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT27 PIO_SCHMITT_SCHMITT27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT27_Msk instead */ +#define PIO_SCHMITT_SCHMITT28_Pos 28 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT28_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT28_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT28 PIO_SCHMITT_SCHMITT28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT28_Msk instead */ +#define PIO_SCHMITT_SCHMITT29_Pos 29 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT29_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT29_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT29 PIO_SCHMITT_SCHMITT29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT29_Msk instead */ +#define PIO_SCHMITT_SCHMITT30_Pos 30 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT30_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT30_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT30 PIO_SCHMITT_SCHMITT30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT30_Msk instead */ +#define PIO_SCHMITT_SCHMITT31_Pos 31 /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT31_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT31_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT31 PIO_SCHMITT_SCHMITT31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_SCHMITT_SCHMITT31_Msk instead */ +#define PIO_SCHMITT_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_SCHMITT) Register MASK (Use PIO_SCHMITT_Msk instead) */ +#define PIO_SCHMITT_Msk _U_(0xFFFFFFFF) /**< (PIO_SCHMITT) Register Mask */ + +#define PIO_SCHMITT_SCHMITT_Pos 0 /**< (PIO_SCHMITT Position) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT_Msk (_U_(0xFFFFFFFF) << PIO_SCHMITT_SCHMITT_Pos) /**< (PIO_SCHMITT Mask) SCHMITT */ +#define PIO_SCHMITT_SCHMITT(value) (PIO_SCHMITT_SCHMITT_Msk & ((value) << PIO_SCHMITT_SCHMITT_Pos)) + +/* -------- PIO_DRIVER : (PIO Offset: 0x118) (R/W 32) I/O Drive Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LINE0:1; /**< bit: 0 Drive of PIO Line 0 */ + uint32_t LINE1:1; /**< bit: 1 Drive of PIO Line 1 */ + uint32_t LINE2:1; /**< bit: 2 Drive of PIO Line 2 */ + uint32_t LINE3:1; /**< bit: 3 Drive of PIO Line 3 */ + uint32_t LINE4:1; /**< bit: 4 Drive of PIO Line 4 */ + uint32_t LINE5:1; /**< bit: 5 Drive of PIO Line 5 */ + uint32_t LINE6:1; /**< bit: 6 Drive of PIO Line 6 */ + uint32_t LINE7:1; /**< bit: 7 Drive of PIO Line 7 */ + uint32_t LINE8:1; /**< bit: 8 Drive of PIO Line 8 */ + uint32_t LINE9:1; /**< bit: 9 Drive of PIO Line 9 */ + uint32_t LINE10:1; /**< bit: 10 Drive of PIO Line 10 */ + uint32_t LINE11:1; /**< bit: 11 Drive of PIO Line 11 */ + uint32_t LINE12:1; /**< bit: 12 Drive of PIO Line 12 */ + uint32_t LINE13:1; /**< bit: 13 Drive of PIO Line 13 */ + uint32_t LINE14:1; /**< bit: 14 Drive of PIO Line 14 */ + uint32_t LINE15:1; /**< bit: 15 Drive of PIO Line 15 */ + uint32_t LINE16:1; /**< bit: 16 Drive of PIO Line 16 */ + uint32_t LINE17:1; /**< bit: 17 Drive of PIO Line 17 */ + uint32_t LINE18:1; /**< bit: 18 Drive of PIO Line 18 */ + uint32_t LINE19:1; /**< bit: 19 Drive of PIO Line 19 */ + uint32_t LINE20:1; /**< bit: 20 Drive of PIO Line 20 */ + uint32_t LINE21:1; /**< bit: 21 Drive of PIO Line 21 */ + uint32_t LINE22:1; /**< bit: 22 Drive of PIO Line 22 */ + uint32_t LINE23:1; /**< bit: 23 Drive of PIO Line 23 */ + uint32_t LINE24:1; /**< bit: 24 Drive of PIO Line 24 */ + uint32_t LINE25:1; /**< bit: 25 Drive of PIO Line 25 */ + uint32_t LINE26:1; /**< bit: 26 Drive of PIO Line 26 */ + uint32_t LINE27:1; /**< bit: 27 Drive of PIO Line 27 */ + uint32_t LINE28:1; /**< bit: 28 Drive of PIO Line 28 */ + uint32_t LINE29:1; /**< bit: 29 Drive of PIO Line 29 */ + uint32_t LINE30:1; /**< bit: 30 Drive of PIO Line 30 */ + uint32_t LINE31:1; /**< bit: 31 Drive of PIO Line 31 */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t LINE:32; /**< bit: 0..31 Drive of PIO Line 3x */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PIO_DRIVER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_DRIVER_OFFSET (0x118) /**< (PIO_DRIVER) I/O Drive Register Offset */ + +#define PIO_DRIVER_LINE0_Pos 0 /**< (PIO_DRIVER) Drive of PIO Line 0 Position */ +#define PIO_DRIVER_LINE0_Msk (_U_(0x1) << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Drive of PIO Line 0 Mask */ +#define PIO_DRIVER_LINE0 PIO_DRIVER_LINE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE0_Msk instead */ +#define PIO_DRIVER_LINE0_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (PIO_DRIVER_LINE0_LOW_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (PIO_DRIVER_LINE0_HIGH_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE1_Pos 1 /**< (PIO_DRIVER) Drive of PIO Line 1 Position */ +#define PIO_DRIVER_LINE1_Msk (_U_(0x1) << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Drive of PIO Line 1 Mask */ +#define PIO_DRIVER_LINE1 PIO_DRIVER_LINE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE1_Msk instead */ +#define PIO_DRIVER_LINE1_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (PIO_DRIVER_LINE1_LOW_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (PIO_DRIVER_LINE1_HIGH_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE2_Pos 2 /**< (PIO_DRIVER) Drive of PIO Line 2 Position */ +#define PIO_DRIVER_LINE2_Msk (_U_(0x1) << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Drive of PIO Line 2 Mask */ +#define PIO_DRIVER_LINE2 PIO_DRIVER_LINE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE2_Msk instead */ +#define PIO_DRIVER_LINE2_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (PIO_DRIVER_LINE2_LOW_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (PIO_DRIVER_LINE2_HIGH_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE3_Pos 3 /**< (PIO_DRIVER) Drive of PIO Line 3 Position */ +#define PIO_DRIVER_LINE3_Msk (_U_(0x1) << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Drive of PIO Line 3 Mask */ +#define PIO_DRIVER_LINE3 PIO_DRIVER_LINE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE3_Msk instead */ +#define PIO_DRIVER_LINE3_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (PIO_DRIVER_LINE3_LOW_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (PIO_DRIVER_LINE3_HIGH_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE4_Pos 4 /**< (PIO_DRIVER) Drive of PIO Line 4 Position */ +#define PIO_DRIVER_LINE4_Msk (_U_(0x1) << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Drive of PIO Line 4 Mask */ +#define PIO_DRIVER_LINE4 PIO_DRIVER_LINE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE4_Msk instead */ +#define PIO_DRIVER_LINE4_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (PIO_DRIVER_LINE4_LOW_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (PIO_DRIVER_LINE4_HIGH_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE5_Pos 5 /**< (PIO_DRIVER) Drive of PIO Line 5 Position */ +#define PIO_DRIVER_LINE5_Msk (_U_(0x1) << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Drive of PIO Line 5 Mask */ +#define PIO_DRIVER_LINE5 PIO_DRIVER_LINE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE5_Msk instead */ +#define PIO_DRIVER_LINE5_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (PIO_DRIVER_LINE5_LOW_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (PIO_DRIVER_LINE5_HIGH_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE6_Pos 6 /**< (PIO_DRIVER) Drive of PIO Line 6 Position */ +#define PIO_DRIVER_LINE6_Msk (_U_(0x1) << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Drive of PIO Line 6 Mask */ +#define PIO_DRIVER_LINE6 PIO_DRIVER_LINE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE6_Msk instead */ +#define PIO_DRIVER_LINE6_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (PIO_DRIVER_LINE6_LOW_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (PIO_DRIVER_LINE6_HIGH_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE7_Pos 7 /**< (PIO_DRIVER) Drive of PIO Line 7 Position */ +#define PIO_DRIVER_LINE7_Msk (_U_(0x1) << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Drive of PIO Line 7 Mask */ +#define PIO_DRIVER_LINE7 PIO_DRIVER_LINE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE7_Msk instead */ +#define PIO_DRIVER_LINE7_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (PIO_DRIVER_LINE7_LOW_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (PIO_DRIVER_LINE7_HIGH_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE8_Pos 8 /**< (PIO_DRIVER) Drive of PIO Line 8 Position */ +#define PIO_DRIVER_LINE8_Msk (_U_(0x1) << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Drive of PIO Line 8 Mask */ +#define PIO_DRIVER_LINE8 PIO_DRIVER_LINE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE8_Msk instead */ +#define PIO_DRIVER_LINE8_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (PIO_DRIVER_LINE8_LOW_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (PIO_DRIVER_LINE8_HIGH_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE9_Pos 9 /**< (PIO_DRIVER) Drive of PIO Line 9 Position */ +#define PIO_DRIVER_LINE9_Msk (_U_(0x1) << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Drive of PIO Line 9 Mask */ +#define PIO_DRIVER_LINE9 PIO_DRIVER_LINE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE9_Msk instead */ +#define PIO_DRIVER_LINE9_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (PIO_DRIVER_LINE9_LOW_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (PIO_DRIVER_LINE9_HIGH_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE10_Pos 10 /**< (PIO_DRIVER) Drive of PIO Line 10 Position */ +#define PIO_DRIVER_LINE10_Msk (_U_(0x1) << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Drive of PIO Line 10 Mask */ +#define PIO_DRIVER_LINE10 PIO_DRIVER_LINE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE10_Msk instead */ +#define PIO_DRIVER_LINE10_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (PIO_DRIVER_LINE10_LOW_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (PIO_DRIVER_LINE10_HIGH_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE11_Pos 11 /**< (PIO_DRIVER) Drive of PIO Line 11 Position */ +#define PIO_DRIVER_LINE11_Msk (_U_(0x1) << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Drive of PIO Line 11 Mask */ +#define PIO_DRIVER_LINE11 PIO_DRIVER_LINE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE11_Msk instead */ +#define PIO_DRIVER_LINE11_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (PIO_DRIVER_LINE11_LOW_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (PIO_DRIVER_LINE11_HIGH_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE12_Pos 12 /**< (PIO_DRIVER) Drive of PIO Line 12 Position */ +#define PIO_DRIVER_LINE12_Msk (_U_(0x1) << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Drive of PIO Line 12 Mask */ +#define PIO_DRIVER_LINE12 PIO_DRIVER_LINE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE12_Msk instead */ +#define PIO_DRIVER_LINE12_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (PIO_DRIVER_LINE12_LOW_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (PIO_DRIVER_LINE12_HIGH_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE13_Pos 13 /**< (PIO_DRIVER) Drive of PIO Line 13 Position */ +#define PIO_DRIVER_LINE13_Msk (_U_(0x1) << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Drive of PIO Line 13 Mask */ +#define PIO_DRIVER_LINE13 PIO_DRIVER_LINE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE13_Msk instead */ +#define PIO_DRIVER_LINE13_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (PIO_DRIVER_LINE13_LOW_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (PIO_DRIVER_LINE13_HIGH_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE14_Pos 14 /**< (PIO_DRIVER) Drive of PIO Line 14 Position */ +#define PIO_DRIVER_LINE14_Msk (_U_(0x1) << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Drive of PIO Line 14 Mask */ +#define PIO_DRIVER_LINE14 PIO_DRIVER_LINE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE14_Msk instead */ +#define PIO_DRIVER_LINE14_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (PIO_DRIVER_LINE14_LOW_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (PIO_DRIVER_LINE14_HIGH_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE15_Pos 15 /**< (PIO_DRIVER) Drive of PIO Line 15 Position */ +#define PIO_DRIVER_LINE15_Msk (_U_(0x1) << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Drive of PIO Line 15 Mask */ +#define PIO_DRIVER_LINE15 PIO_DRIVER_LINE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE15_Msk instead */ +#define PIO_DRIVER_LINE15_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (PIO_DRIVER_LINE15_LOW_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (PIO_DRIVER_LINE15_HIGH_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE16_Pos 16 /**< (PIO_DRIVER) Drive of PIO Line 16 Position */ +#define PIO_DRIVER_LINE16_Msk (_U_(0x1) << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Drive of PIO Line 16 Mask */ +#define PIO_DRIVER_LINE16 PIO_DRIVER_LINE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE16_Msk instead */ +#define PIO_DRIVER_LINE16_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (PIO_DRIVER_LINE16_LOW_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (PIO_DRIVER_LINE16_HIGH_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE17_Pos 17 /**< (PIO_DRIVER) Drive of PIO Line 17 Position */ +#define PIO_DRIVER_LINE17_Msk (_U_(0x1) << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Drive of PIO Line 17 Mask */ +#define PIO_DRIVER_LINE17 PIO_DRIVER_LINE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE17_Msk instead */ +#define PIO_DRIVER_LINE17_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (PIO_DRIVER_LINE17_LOW_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (PIO_DRIVER_LINE17_HIGH_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE18_Pos 18 /**< (PIO_DRIVER) Drive of PIO Line 18 Position */ +#define PIO_DRIVER_LINE18_Msk (_U_(0x1) << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Drive of PIO Line 18 Mask */ +#define PIO_DRIVER_LINE18 PIO_DRIVER_LINE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE18_Msk instead */ +#define PIO_DRIVER_LINE18_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (PIO_DRIVER_LINE18_LOW_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (PIO_DRIVER_LINE18_HIGH_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE19_Pos 19 /**< (PIO_DRIVER) Drive of PIO Line 19 Position */ +#define PIO_DRIVER_LINE19_Msk (_U_(0x1) << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Drive of PIO Line 19 Mask */ +#define PIO_DRIVER_LINE19 PIO_DRIVER_LINE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE19_Msk instead */ +#define PIO_DRIVER_LINE19_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (PIO_DRIVER_LINE19_LOW_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (PIO_DRIVER_LINE19_HIGH_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE20_Pos 20 /**< (PIO_DRIVER) Drive of PIO Line 20 Position */ +#define PIO_DRIVER_LINE20_Msk (_U_(0x1) << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Drive of PIO Line 20 Mask */ +#define PIO_DRIVER_LINE20 PIO_DRIVER_LINE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE20_Msk instead */ +#define PIO_DRIVER_LINE20_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (PIO_DRIVER_LINE20_LOW_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (PIO_DRIVER_LINE20_HIGH_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE21_Pos 21 /**< (PIO_DRIVER) Drive of PIO Line 21 Position */ +#define PIO_DRIVER_LINE21_Msk (_U_(0x1) << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Drive of PIO Line 21 Mask */ +#define PIO_DRIVER_LINE21 PIO_DRIVER_LINE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE21_Msk instead */ +#define PIO_DRIVER_LINE21_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (PIO_DRIVER_LINE21_LOW_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (PIO_DRIVER_LINE21_HIGH_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE22_Pos 22 /**< (PIO_DRIVER) Drive of PIO Line 22 Position */ +#define PIO_DRIVER_LINE22_Msk (_U_(0x1) << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Drive of PIO Line 22 Mask */ +#define PIO_DRIVER_LINE22 PIO_DRIVER_LINE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE22_Msk instead */ +#define PIO_DRIVER_LINE22_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (PIO_DRIVER_LINE22_LOW_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (PIO_DRIVER_LINE22_HIGH_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE23_Pos 23 /**< (PIO_DRIVER) Drive of PIO Line 23 Position */ +#define PIO_DRIVER_LINE23_Msk (_U_(0x1) << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Drive of PIO Line 23 Mask */ +#define PIO_DRIVER_LINE23 PIO_DRIVER_LINE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE23_Msk instead */ +#define PIO_DRIVER_LINE23_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (PIO_DRIVER_LINE23_LOW_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (PIO_DRIVER_LINE23_HIGH_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE24_Pos 24 /**< (PIO_DRIVER) Drive of PIO Line 24 Position */ +#define PIO_DRIVER_LINE24_Msk (_U_(0x1) << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Drive of PIO Line 24 Mask */ +#define PIO_DRIVER_LINE24 PIO_DRIVER_LINE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE24_Msk instead */ +#define PIO_DRIVER_LINE24_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (PIO_DRIVER_LINE24_LOW_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (PIO_DRIVER_LINE24_HIGH_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE25_Pos 25 /**< (PIO_DRIVER) Drive of PIO Line 25 Position */ +#define PIO_DRIVER_LINE25_Msk (_U_(0x1) << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Drive of PIO Line 25 Mask */ +#define PIO_DRIVER_LINE25 PIO_DRIVER_LINE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE25_Msk instead */ +#define PIO_DRIVER_LINE25_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (PIO_DRIVER_LINE25_LOW_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (PIO_DRIVER_LINE25_HIGH_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE26_Pos 26 /**< (PIO_DRIVER) Drive of PIO Line 26 Position */ +#define PIO_DRIVER_LINE26_Msk (_U_(0x1) << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Drive of PIO Line 26 Mask */ +#define PIO_DRIVER_LINE26 PIO_DRIVER_LINE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE26_Msk instead */ +#define PIO_DRIVER_LINE26_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (PIO_DRIVER_LINE26_LOW_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (PIO_DRIVER_LINE26_HIGH_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE27_Pos 27 /**< (PIO_DRIVER) Drive of PIO Line 27 Position */ +#define PIO_DRIVER_LINE27_Msk (_U_(0x1) << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Drive of PIO Line 27 Mask */ +#define PIO_DRIVER_LINE27 PIO_DRIVER_LINE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE27_Msk instead */ +#define PIO_DRIVER_LINE27_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (PIO_DRIVER_LINE27_LOW_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (PIO_DRIVER_LINE27_HIGH_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE28_Pos 28 /**< (PIO_DRIVER) Drive of PIO Line 28 Position */ +#define PIO_DRIVER_LINE28_Msk (_U_(0x1) << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Drive of PIO Line 28 Mask */ +#define PIO_DRIVER_LINE28 PIO_DRIVER_LINE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE28_Msk instead */ +#define PIO_DRIVER_LINE28_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (PIO_DRIVER_LINE28_LOW_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (PIO_DRIVER_LINE28_HIGH_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE29_Pos 29 /**< (PIO_DRIVER) Drive of PIO Line 29 Position */ +#define PIO_DRIVER_LINE29_Msk (_U_(0x1) << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Drive of PIO Line 29 Mask */ +#define PIO_DRIVER_LINE29 PIO_DRIVER_LINE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE29_Msk instead */ +#define PIO_DRIVER_LINE29_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (PIO_DRIVER_LINE29_LOW_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (PIO_DRIVER_LINE29_HIGH_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE30_Pos 30 /**< (PIO_DRIVER) Drive of PIO Line 30 Position */ +#define PIO_DRIVER_LINE30_Msk (_U_(0x1) << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Drive of PIO Line 30 Mask */ +#define PIO_DRIVER_LINE30 PIO_DRIVER_LINE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE30_Msk instead */ +#define PIO_DRIVER_LINE30_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (PIO_DRIVER_LINE30_LOW_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (PIO_DRIVER_LINE30_HIGH_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE31_Pos 31 /**< (PIO_DRIVER) Drive of PIO Line 31 Position */ +#define PIO_DRIVER_LINE31_Msk (_U_(0x1) << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Drive of PIO Line 31 Mask */ +#define PIO_DRIVER_LINE31 PIO_DRIVER_LINE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_DRIVER_LINE31_Msk instead */ +#define PIO_DRIVER_LINE31_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (PIO_DRIVER_LINE31_LOW_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (PIO_DRIVER_LINE31_HIGH_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_DRIVER) Register MASK (Use PIO_DRIVER_Msk instead) */ +#define PIO_DRIVER_Msk _U_(0xFFFFFFFF) /**< (PIO_DRIVER) Register Mask */ + +#define PIO_DRIVER_LINE_Pos 0 /**< (PIO_DRIVER Position) Drive of PIO Line 3x */ +#define PIO_DRIVER_LINE_Msk (_U_(0xFFFFFFFF) << PIO_DRIVER_LINE_Pos) /**< (PIO_DRIVER Mask) LINE */ +#define PIO_DRIVER_LINE(value) (PIO_DRIVER_LINE_Msk & ((value) << PIO_DRIVER_LINE_Pos)) + +/* -------- PIO_PCMR : (PIO Offset: 0x150) (R/W 32) Parallel Capture Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PCEN:1; /**< bit: 0 Parallel Capture Mode Enable */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t DSIZE:2; /**< bit: 4..5 Parallel Capture Mode Data Size */ + uint32_t :3; /**< bit: 6..8 Reserved */ + uint32_t ALWYS:1; /**< bit: 9 Parallel Capture Mode Always Sampling */ + uint32_t HALFS:1; /**< bit: 10 Parallel Capture Mode Half Sampling */ + uint32_t FRSTS:1; /**< bit: 11 Parallel Capture Mode First Sample */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCMR_OFFSET (0x150) /**< (PIO_PCMR) Parallel Capture Mode Register Offset */ + +#define PIO_PCMR_PCEN_Pos 0 /**< (PIO_PCMR) Parallel Capture Mode Enable Position */ +#define PIO_PCMR_PCEN_Msk (_U_(0x1) << PIO_PCMR_PCEN_Pos) /**< (PIO_PCMR) Parallel Capture Mode Enable Mask */ +#define PIO_PCMR_PCEN PIO_PCMR_PCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_PCEN_Msk instead */ +#define PIO_PCMR_DSIZE_Pos 4 /**< (PIO_PCMR) Parallel Capture Mode Data Size Position */ +#define PIO_PCMR_DSIZE_Msk (_U_(0x3) << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) Parallel Capture Mode Data Size Mask */ +#define PIO_PCMR_DSIZE(value) (PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)) +#define PIO_PCMR_DSIZE_BYTE_Val _U_(0x0) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD_Val _U_(0x1) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD_Val _U_(0x2) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_DSIZE_BYTE (PIO_PCMR_DSIZE_BYTE_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) Position */ +#define PIO_PCMR_DSIZE_HALFWORD (PIO_PCMR_DSIZE_HALFWORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) Position */ +#define PIO_PCMR_DSIZE_WORD (PIO_PCMR_DSIZE_WORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) Position */ +#define PIO_PCMR_ALWYS_Pos 9 /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Position */ +#define PIO_PCMR_ALWYS_Msk (_U_(0x1) << PIO_PCMR_ALWYS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Mask */ +#define PIO_PCMR_ALWYS PIO_PCMR_ALWYS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_ALWYS_Msk instead */ +#define PIO_PCMR_HALFS_Pos 10 /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Position */ +#define PIO_PCMR_HALFS_Msk (_U_(0x1) << PIO_PCMR_HALFS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Mask */ +#define PIO_PCMR_HALFS PIO_PCMR_HALFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_HALFS_Msk instead */ +#define PIO_PCMR_FRSTS_Pos 11 /**< (PIO_PCMR) Parallel Capture Mode First Sample Position */ +#define PIO_PCMR_FRSTS_Msk (_U_(0x1) << PIO_PCMR_FRSTS_Pos) /**< (PIO_PCMR) Parallel Capture Mode First Sample Mask */ +#define PIO_PCMR_FRSTS PIO_PCMR_FRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCMR_FRSTS_Msk instead */ +#define PIO_PCMR_MASK _U_(0xE31) /**< \deprecated (PIO_PCMR) Register MASK (Use PIO_PCMR_Msk instead) */ +#define PIO_PCMR_Msk _U_(0xE31) /**< (PIO_PCMR) Register Mask */ + + +/* -------- PIO_PCIER : (PIO Offset: 0x154) (/W 32) Parallel Capture Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Enable */ + uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Enable */ + uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Enable */ + uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Enable */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCIER_OFFSET (0x154) /**< (PIO_PCIER) Parallel Capture Interrupt Enable Register Offset */ + +#define PIO_PCIER_DRDY_Pos 0 /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Position */ +#define PIO_PCIER_DRDY_Msk (_U_(0x1) << PIO_PCIER_DRDY_Pos) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Mask */ +#define PIO_PCIER_DRDY PIO_PCIER_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_DRDY_Msk instead */ +#define PIO_PCIER_OVRE_Pos 1 /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Position */ +#define PIO_PCIER_OVRE_Msk (_U_(0x1) << PIO_PCIER_OVRE_Pos) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Mask */ +#define PIO_PCIER_OVRE PIO_PCIER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_OVRE_Msk instead */ +#define PIO_PCIER_ENDRX_Pos 2 /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Position */ +#define PIO_PCIER_ENDRX_Msk (_U_(0x1) << PIO_PCIER_ENDRX_Pos) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Mask */ +#define PIO_PCIER_ENDRX PIO_PCIER_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_ENDRX_Msk instead */ +#define PIO_PCIER_RXBUFF_Pos 3 /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Position */ +#define PIO_PCIER_RXBUFF_Msk (_U_(0x1) << PIO_PCIER_RXBUFF_Pos) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Mask */ +#define PIO_PCIER_RXBUFF PIO_PCIER_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIER_RXBUFF_Msk instead */ +#define PIO_PCIER_MASK _U_(0x0F) /**< \deprecated (PIO_PCIER) Register MASK (Use PIO_PCIER_Msk instead) */ +#define PIO_PCIER_Msk _U_(0x0F) /**< (PIO_PCIER) Register Mask */ + + +/* -------- PIO_PCIDR : (PIO Offset: 0x158) (/W 32) Parallel Capture Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Disable */ + uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Disable */ + uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Disable */ + uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Disable */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCIDR_OFFSET (0x158) /**< (PIO_PCIDR) Parallel Capture Interrupt Disable Register Offset */ + +#define PIO_PCIDR_DRDY_Pos 0 /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Position */ +#define PIO_PCIDR_DRDY_Msk (_U_(0x1) << PIO_PCIDR_DRDY_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Mask */ +#define PIO_PCIDR_DRDY PIO_PCIDR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_DRDY_Msk instead */ +#define PIO_PCIDR_OVRE_Pos 1 /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Position */ +#define PIO_PCIDR_OVRE_Msk (_U_(0x1) << PIO_PCIDR_OVRE_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Mask */ +#define PIO_PCIDR_OVRE PIO_PCIDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_OVRE_Msk instead */ +#define PIO_PCIDR_ENDRX_Pos 2 /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Position */ +#define PIO_PCIDR_ENDRX_Msk (_U_(0x1) << PIO_PCIDR_ENDRX_Pos) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Mask */ +#define PIO_PCIDR_ENDRX PIO_PCIDR_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_ENDRX_Msk instead */ +#define PIO_PCIDR_RXBUFF_Pos 3 /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Position */ +#define PIO_PCIDR_RXBUFF_Msk (_U_(0x1) << PIO_PCIDR_RXBUFF_Pos) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Mask */ +#define PIO_PCIDR_RXBUFF PIO_PCIDR_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIDR_RXBUFF_Msk instead */ +#define PIO_PCIDR_MASK _U_(0x0F) /**< \deprecated (PIO_PCIDR) Register MASK (Use PIO_PCIDR_Msk instead) */ +#define PIO_PCIDR_Msk _U_(0x0F) /**< (PIO_PCIDR) Register Mask */ + + +/* -------- PIO_PCIMR : (PIO Offset: 0x15c) (R/ 32) Parallel Capture Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready Interrupt Mask */ + uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error Interrupt Mask */ + uint32_t ENDRX:1; /**< bit: 2 End of Reception Transfer Interrupt Mask */ + uint32_t RXBUFF:1; /**< bit: 3 Reception Buffer Full Interrupt Mask */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCIMR_OFFSET (0x15C) /**< (PIO_PCIMR) Parallel Capture Interrupt Mask Register Offset */ + +#define PIO_PCIMR_DRDY_Pos 0 /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Position */ +#define PIO_PCIMR_DRDY_Msk (_U_(0x1) << PIO_PCIMR_DRDY_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Mask */ +#define PIO_PCIMR_DRDY PIO_PCIMR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_DRDY_Msk instead */ +#define PIO_PCIMR_OVRE_Pos 1 /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Position */ +#define PIO_PCIMR_OVRE_Msk (_U_(0x1) << PIO_PCIMR_OVRE_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Mask */ +#define PIO_PCIMR_OVRE PIO_PCIMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_OVRE_Msk instead */ +#define PIO_PCIMR_ENDRX_Pos 2 /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Position */ +#define PIO_PCIMR_ENDRX_Msk (_U_(0x1) << PIO_PCIMR_ENDRX_Pos) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Mask */ +#define PIO_PCIMR_ENDRX PIO_PCIMR_ENDRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_ENDRX_Msk instead */ +#define PIO_PCIMR_RXBUFF_Pos 3 /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Position */ +#define PIO_PCIMR_RXBUFF_Msk (_U_(0x1) << PIO_PCIMR_RXBUFF_Pos) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Mask */ +#define PIO_PCIMR_RXBUFF PIO_PCIMR_RXBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCIMR_RXBUFF_Msk instead */ +#define PIO_PCIMR_MASK _U_(0x0F) /**< \deprecated (PIO_PCIMR) Register MASK (Use PIO_PCIMR_Msk instead) */ +#define PIO_PCIMR_Msk _U_(0x0F) /**< (PIO_PCIMR) Register Mask */ + + +/* -------- PIO_PCISR : (PIO Offset: 0x160) (R/ 32) Parallel Capture Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DRDY:1; /**< bit: 0 Parallel Capture Mode Data Ready */ + uint32_t OVRE:1; /**< bit: 1 Parallel Capture Mode Overrun Error */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCISR_OFFSET (0x160) /**< (PIO_PCISR) Parallel Capture Interrupt Status Register Offset */ + +#define PIO_PCISR_DRDY_Pos 0 /**< (PIO_PCISR) Parallel Capture Mode Data Ready Position */ +#define PIO_PCISR_DRDY_Msk (_U_(0x1) << PIO_PCISR_DRDY_Pos) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Mask */ +#define PIO_PCISR_DRDY PIO_PCISR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCISR_DRDY_Msk instead */ +#define PIO_PCISR_OVRE_Pos 1 /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Position */ +#define PIO_PCISR_OVRE_Msk (_U_(0x1) << PIO_PCISR_OVRE_Pos) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Mask */ +#define PIO_PCISR_OVRE PIO_PCISR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PIO_PCISR_OVRE_Msk instead */ +#define PIO_PCISR_MASK _U_(0x03) /**< \deprecated (PIO_PCISR) Register MASK (Use PIO_PCISR_Msk instead) */ +#define PIO_PCISR_Msk _U_(0x03) /**< (PIO_PCISR) Register Mask */ + + +/* -------- PIO_PCRHR : (PIO Offset: 0x164) (R/ 32) Parallel Capture Reception Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDATA:32; /**< bit: 0..31 Parallel Capture Mode Reception Data */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PIO_PCRHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PIO_PCRHR_OFFSET (0x164) /**< (PIO_PCRHR) Parallel Capture Reception Holding Register Offset */ + +#define PIO_PCRHR_RDATA_Pos 0 /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Position */ +#define PIO_PCRHR_RDATA_Msk (_U_(0xFFFFFFFF) << PIO_PCRHR_RDATA_Pos) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Mask */ +#define PIO_PCRHR_RDATA(value) (PIO_PCRHR_RDATA_Msk & ((value) << PIO_PCRHR_RDATA_Pos)) +#define PIO_PCRHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PIO_PCRHR) Register MASK (Use PIO_PCRHR_Msk instead) */ +#define PIO_PCRHR_Msk _U_(0xFFFFFFFF) /**< (PIO_PCRHR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief PIO hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< (PIO Offset: 0x00) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< (PIO Offset: 0x04) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< (PIO Offset: 0x08) PIO Status Register */ + __I uint8_t Reserved1[4]; + __O uint32_t PIO_OER; /**< (PIO Offset: 0x10) Output Enable Register */ + __O uint32_t PIO_ODR; /**< (PIO Offset: 0x14) Output Disable Register */ + __I uint32_t PIO_OSR; /**< (PIO Offset: 0x18) Output Status Register */ + __I uint8_t Reserved2[4]; + __O uint32_t PIO_IFER; /**< (PIO Offset: 0x20) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< (PIO Offset: 0x24) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< (PIO Offset: 0x28) Glitch Input Filter Status Register */ + __I uint8_t Reserved3[4]; + __O uint32_t PIO_SODR; /**< (PIO Offset: 0x30) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< (PIO Offset: 0x34) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< (PIO Offset: 0x38) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< (PIO Offset: 0x3C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< (PIO Offset: 0x40) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< (PIO Offset: 0x44) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< (PIO Offset: 0x48) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< (PIO Offset: 0x4C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< (PIO Offset: 0x50) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< (PIO Offset: 0x54) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< (PIO Offset: 0x58) Multi-driver Status Register */ + __I uint8_t Reserved4[4]; + __O uint32_t PIO_PUDR; /**< (PIO Offset: 0x60) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< (PIO Offset: 0x64) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< (PIO Offset: 0x68) Pad Pull-up Status Register */ + __I uint8_t Reserved5[4]; + __IO uint32_t PIO_ABCDSR[2]; /**< (PIO Offset: 0x70) Peripheral ABCD Select Register 0 */ + __I uint8_t Reserved6[8]; + __O uint32_t PIO_IFSCDR; /**< (PIO Offset: 0x80) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< (PIO Offset: 0x84) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< (PIO Offset: 0x88) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< (PIO Offset: 0x8C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< (PIO Offset: 0x90) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< (PIO Offset: 0x94) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< (PIO Offset: 0x98) Pad Pull-down Status Register */ + __I uint8_t Reserved7[4]; + __O uint32_t PIO_OWER; /**< (PIO Offset: 0xA0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< (PIO Offset: 0xA4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< (PIO Offset: 0xA8) Output Write Status Register */ + __I uint8_t Reserved8[4]; + __O uint32_t PIO_AIMER; /**< (PIO Offset: 0xB0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< (PIO Offset: 0xB4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< (PIO Offset: 0xB8) Additional Interrupt Modes Mask Register */ + __I uint8_t Reserved9[4]; + __O uint32_t PIO_ESR; /**< (PIO Offset: 0xC0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< (PIO Offset: 0xC4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< (PIO Offset: 0xC8) Edge/Level Status Register */ + __I uint8_t Reserved10[4]; + __O uint32_t PIO_FELLSR; /**< (PIO Offset: 0xD0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< (PIO Offset: 0xD4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< (PIO Offset: 0xD8) Fall/Rise - Low/High Status Register */ + __I uint8_t Reserved11[4]; + __I uint32_t PIO_LOCKSR; /**< (PIO Offset: 0xE0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< (PIO Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< (PIO Offset: 0xE8) Write Protection Status Register */ + __I uint8_t Reserved12[20]; + __IO uint32_t PIO_SCHMITT; /**< (PIO Offset: 0x100) Schmitt Trigger Register */ + __I uint8_t Reserved13[20]; + __IO uint32_t PIO_DRIVER; /**< (PIO Offset: 0x118) I/O Drive Register */ + __I uint8_t Reserved14[52]; + __IO uint32_t PIO_PCMR; /**< (PIO Offset: 0x150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< (PIO Offset: 0x160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< (PIO Offset: 0x164) Parallel Capture Reception Holding Register */ +} Pio; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief PIO hardware registers */ +typedef struct { + __O PIO_PER_Type PIO_PER; /**< Offset: 0x00 ( /W 32) PIO Enable Register */ + __O PIO_PDR_Type PIO_PDR; /**< Offset: 0x04 ( /W 32) PIO Disable Register */ + __I PIO_PSR_Type PIO_PSR; /**< Offset: 0x08 (R/ 32) PIO Status Register */ + __I uint8_t Reserved1[4]; + __O PIO_OER_Type PIO_OER; /**< Offset: 0x10 ( /W 32) Output Enable Register */ + __O PIO_ODR_Type PIO_ODR; /**< Offset: 0x14 ( /W 32) Output Disable Register */ + __I PIO_OSR_Type PIO_OSR; /**< Offset: 0x18 (R/ 32) Output Status Register */ + __I uint8_t Reserved2[4]; + __O PIO_IFER_Type PIO_IFER; /**< Offset: 0x20 ( /W 32) Glitch Input Filter Enable Register */ + __O PIO_IFDR_Type PIO_IFDR; /**< Offset: 0x24 ( /W 32) Glitch Input Filter Disable Register */ + __I PIO_IFSR_Type PIO_IFSR; /**< Offset: 0x28 (R/ 32) Glitch Input Filter Status Register */ + __I uint8_t Reserved3[4]; + __O PIO_SODR_Type PIO_SODR; /**< Offset: 0x30 ( /W 32) Set Output Data Register */ + __O PIO_CODR_Type PIO_CODR; /**< Offset: 0x34 ( /W 32) Clear Output Data Register */ + __IO PIO_ODSR_Type PIO_ODSR; /**< Offset: 0x38 (R/W 32) Output Data Status Register */ + __I PIO_PDSR_Type PIO_PDSR; /**< Offset: 0x3C (R/ 32) Pin Data Status Register */ + __O PIO_IER_Type PIO_IER; /**< Offset: 0x40 ( /W 32) Interrupt Enable Register */ + __O PIO_IDR_Type PIO_IDR; /**< Offset: 0x44 ( /W 32) Interrupt Disable Register */ + __I PIO_IMR_Type PIO_IMR; /**< Offset: 0x48 (R/ 32) Interrupt Mask Register */ + __I PIO_ISR_Type PIO_ISR; /**< Offset: 0x4C (R/ 32) Interrupt Status Register */ + __O PIO_MDER_Type PIO_MDER; /**< Offset: 0x50 ( /W 32) Multi-driver Enable Register */ + __O PIO_MDDR_Type PIO_MDDR; /**< Offset: 0x54 ( /W 32) Multi-driver Disable Register */ + __I PIO_MDSR_Type PIO_MDSR; /**< Offset: 0x58 (R/ 32) Multi-driver Status Register */ + __I uint8_t Reserved4[4]; + __O PIO_PUDR_Type PIO_PUDR; /**< Offset: 0x60 ( /W 32) Pull-up Disable Register */ + __O PIO_PUER_Type PIO_PUER; /**< Offset: 0x64 ( /W 32) Pull-up Enable Register */ + __I PIO_PUSR_Type PIO_PUSR; /**< Offset: 0x68 (R/ 32) Pad Pull-up Status Register */ + __I uint8_t Reserved5[4]; + __IO PIO_ABCDSR_Type PIO_ABCDSR[2]; /**< Offset: 0x70 (R/W 32) Peripheral ABCD Select Register 0 */ + __I uint8_t Reserved6[8]; + __O PIO_IFSCDR_Type PIO_IFSCDR; /**< Offset: 0x80 ( /W 32) Input Filter Slow Clock Disable Register */ + __O PIO_IFSCER_Type PIO_IFSCER; /**< Offset: 0x84 ( /W 32) Input Filter Slow Clock Enable Register */ + __I PIO_IFSCSR_Type PIO_IFSCSR; /**< Offset: 0x88 (R/ 32) Input Filter Slow Clock Status Register */ + __IO PIO_SCDR_Type PIO_SCDR; /**< Offset: 0x8C (R/W 32) Slow Clock Divider Debouncing Register */ + __O PIO_PPDDR_Type PIO_PPDDR; /**< Offset: 0x90 ( /W 32) Pad Pull-down Disable Register */ + __O PIO_PPDER_Type PIO_PPDER; /**< Offset: 0x94 ( /W 32) Pad Pull-down Enable Register */ + __I PIO_PPDSR_Type PIO_PPDSR; /**< Offset: 0x98 (R/ 32) Pad Pull-down Status Register */ + __I uint8_t Reserved7[4]; + __O PIO_OWER_Type PIO_OWER; /**< Offset: 0xA0 ( /W 32) Output Write Enable */ + __O PIO_OWDR_Type PIO_OWDR; /**< Offset: 0xA4 ( /W 32) Output Write Disable */ + __I PIO_OWSR_Type PIO_OWSR; /**< Offset: 0xA8 (R/ 32) Output Write Status Register */ + __I uint8_t Reserved8[4]; + __O PIO_AIMER_Type PIO_AIMER; /**< Offset: 0xB0 ( /W 32) Additional Interrupt Modes Enable Register */ + __O PIO_AIMDR_Type PIO_AIMDR; /**< Offset: 0xB4 ( /W 32) Additional Interrupt Modes Disable Register */ + __I PIO_AIMMR_Type PIO_AIMMR; /**< Offset: 0xB8 (R/ 32) Additional Interrupt Modes Mask Register */ + __I uint8_t Reserved9[4]; + __O PIO_ESR_Type PIO_ESR; /**< Offset: 0xC0 ( /W 32) Edge Select Register */ + __O PIO_LSR_Type PIO_LSR; /**< Offset: 0xC4 ( /W 32) Level Select Register */ + __I PIO_ELSR_Type PIO_ELSR; /**< Offset: 0xC8 (R/ 32) Edge/Level Status Register */ + __I uint8_t Reserved10[4]; + __O PIO_FELLSR_Type PIO_FELLSR; /**< Offset: 0xD0 ( /W 32) Falling Edge/Low-Level Select Register */ + __O PIO_REHLSR_Type PIO_REHLSR; /**< Offset: 0xD4 ( /W 32) Rising Edge/High-Level Select Register */ + __I PIO_FRLHSR_Type PIO_FRLHSR; /**< Offset: 0xD8 (R/ 32) Fall/Rise - Low/High Status Register */ + __I uint8_t Reserved11[4]; + __I PIO_LOCKSR_Type PIO_LOCKSR; /**< Offset: 0xE0 (R/ 32) Lock Status */ + __IO PIO_WPMR_Type PIO_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I PIO_WPSR_Type PIO_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved12[20]; + __IO PIO_SCHMITT_Type PIO_SCHMITT; /**< Offset: 0x100 (R/W 32) Schmitt Trigger Register */ + __I uint8_t Reserved13[20]; + __IO PIO_DRIVER_Type PIO_DRIVER; /**< Offset: 0x118 (R/W 32) I/O Drive Register */ + __I uint8_t Reserved14[52]; + __IO PIO_PCMR_Type PIO_PCMR; /**< Offset: 0x150 (R/W 32) Parallel Capture Mode Register */ + __O PIO_PCIER_Type PIO_PCIER; /**< Offset: 0x154 ( /W 32) Parallel Capture Interrupt Enable Register */ + __O PIO_PCIDR_Type PIO_PCIDR; /**< Offset: 0x158 ( /W 32) Parallel Capture Interrupt Disable Register */ + __I PIO_PCIMR_Type PIO_PCIMR; /**< Offset: 0x15C (R/ 32) Parallel Capture Interrupt Mask Register */ + __I PIO_PCISR_Type PIO_PCISR; /**< Offset: 0x160 (R/ 32) Parallel Capture Interrupt Status Register */ + __I PIO_PCRHR_Type PIO_PCRHR; /**< Offset: 0x164 (R/ 32) Parallel Capture Reception Holding Register */ +} Pio; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Parallel Input/Output Controller */ + +#endif /* _SAME70_PIO_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/pmc.h b/bsp/microchip/same70/bsp/same70b/include/component/pmc.h new file mode 100644 index 0000000000..6604eb0960 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/pmc.h @@ -0,0 +1,3218 @@ +/** + * \file + * + * \brief Component description for PMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PMC_COMPONENT_H_ +#define _SAME70_PMC_COMPONENT_H_ +#define _SAME70_PMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Power Management Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PMC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define PMC_44006 /**< (PMC) Module ID */ +#define REV_PMC P /**< (PMC) Module revision */ + +/* -------- PMC_SCER : (PMC Offset: 0x00) (/W 32) System Clock Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :5; /**< bit: 0..4 Reserved */ + uint32_t USBCLK:1; /**< bit: 5 Enable USB FS Clock */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Enable */ + uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Enable */ + uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Enable */ + uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Enable */ + uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Enable */ + uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Enable */ + uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Enable */ + uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Enable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Enable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SCER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SCER_OFFSET (0x00) /**< (PMC_SCER) System Clock Enable Register Offset */ + +#define PMC_SCER_USBCLK_Pos 5 /**< (PMC_SCER) Enable USB FS Clock Position */ +#define PMC_SCER_USBCLK_Msk (_U_(0x1) << PMC_SCER_USBCLK_Pos) /**< (PMC_SCER) Enable USB FS Clock Mask */ +#define PMC_SCER_USBCLK PMC_SCER_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_USBCLK_Msk instead */ +#define PMC_SCER_PCK0_Pos 8 /**< (PMC_SCER) Programmable Clock 0 Output Enable Position */ +#define PMC_SCER_PCK0_Msk (_U_(0x1) << PMC_SCER_PCK0_Pos) /**< (PMC_SCER) Programmable Clock 0 Output Enable Mask */ +#define PMC_SCER_PCK0 PMC_SCER_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK0_Msk instead */ +#define PMC_SCER_PCK1_Pos 9 /**< (PMC_SCER) Programmable Clock 1 Output Enable Position */ +#define PMC_SCER_PCK1_Msk (_U_(0x1) << PMC_SCER_PCK1_Pos) /**< (PMC_SCER) Programmable Clock 1 Output Enable Mask */ +#define PMC_SCER_PCK1 PMC_SCER_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK1_Msk instead */ +#define PMC_SCER_PCK2_Pos 10 /**< (PMC_SCER) Programmable Clock 2 Output Enable Position */ +#define PMC_SCER_PCK2_Msk (_U_(0x1) << PMC_SCER_PCK2_Pos) /**< (PMC_SCER) Programmable Clock 2 Output Enable Mask */ +#define PMC_SCER_PCK2 PMC_SCER_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK2_Msk instead */ +#define PMC_SCER_PCK3_Pos 11 /**< (PMC_SCER) Programmable Clock 3 Output Enable Position */ +#define PMC_SCER_PCK3_Msk (_U_(0x1) << PMC_SCER_PCK3_Pos) /**< (PMC_SCER) Programmable Clock 3 Output Enable Mask */ +#define PMC_SCER_PCK3 PMC_SCER_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK3_Msk instead */ +#define PMC_SCER_PCK4_Pos 12 /**< (PMC_SCER) Programmable Clock 4 Output Enable Position */ +#define PMC_SCER_PCK4_Msk (_U_(0x1) << PMC_SCER_PCK4_Pos) /**< (PMC_SCER) Programmable Clock 4 Output Enable Mask */ +#define PMC_SCER_PCK4 PMC_SCER_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK4_Msk instead */ +#define PMC_SCER_PCK5_Pos 13 /**< (PMC_SCER) Programmable Clock 5 Output Enable Position */ +#define PMC_SCER_PCK5_Msk (_U_(0x1) << PMC_SCER_PCK5_Pos) /**< (PMC_SCER) Programmable Clock 5 Output Enable Mask */ +#define PMC_SCER_PCK5 PMC_SCER_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK5_Msk instead */ +#define PMC_SCER_PCK6_Pos 14 /**< (PMC_SCER) Programmable Clock 6 Output Enable Position */ +#define PMC_SCER_PCK6_Msk (_U_(0x1) << PMC_SCER_PCK6_Pos) /**< (PMC_SCER) Programmable Clock 6 Output Enable Mask */ +#define PMC_SCER_PCK6 PMC_SCER_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK6_Msk instead */ +#define PMC_SCER_PCK7_Pos 15 /**< (PMC_SCER) Programmable Clock 7 Output Enable Position */ +#define PMC_SCER_PCK7_Msk (_U_(0x1) << PMC_SCER_PCK7_Pos) /**< (PMC_SCER) Programmable Clock 7 Output Enable Mask */ +#define PMC_SCER_PCK7 PMC_SCER_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCER_PCK7_Msk instead */ +#define PMC_SCER_MASK _U_(0xFF20) /**< \deprecated (PMC_SCER) Register MASK (Use PMC_SCER_Msk instead) */ +#define PMC_SCER_Msk _U_(0xFF20) /**< (PMC_SCER) Register Mask */ + +#define PMC_SCER_PCK_Pos 8 /**< (PMC_SCER Position) Programmable Clock 7 Output Enable */ +#define PMC_SCER_PCK_Msk (_U_(0xFF) << PMC_SCER_PCK_Pos) /**< (PMC_SCER Mask) PCK */ +#define PMC_SCER_PCK(value) (PMC_SCER_PCK_Msk & ((value) << PMC_SCER_PCK_Pos)) + +/* -------- PMC_SCDR : (PMC Offset: 0x04) (/W 32) System Clock Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :5; /**< bit: 0..4 Reserved */ + uint32_t USBCLK:1; /**< bit: 5 Disable USB FS Clock */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Disable */ + uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Disable */ + uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Disable */ + uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Disable */ + uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Disable */ + uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Disable */ + uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Disable */ + uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Disable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Disable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SCDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SCDR_OFFSET (0x04) /**< (PMC_SCDR) System Clock Disable Register Offset */ + +#define PMC_SCDR_USBCLK_Pos 5 /**< (PMC_SCDR) Disable USB FS Clock Position */ +#define PMC_SCDR_USBCLK_Msk (_U_(0x1) << PMC_SCDR_USBCLK_Pos) /**< (PMC_SCDR) Disable USB FS Clock Mask */ +#define PMC_SCDR_USBCLK PMC_SCDR_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_USBCLK_Msk instead */ +#define PMC_SCDR_PCK0_Pos 8 /**< (PMC_SCDR) Programmable Clock 0 Output Disable Position */ +#define PMC_SCDR_PCK0_Msk (_U_(0x1) << PMC_SCDR_PCK0_Pos) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Mask */ +#define PMC_SCDR_PCK0 PMC_SCDR_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK0_Msk instead */ +#define PMC_SCDR_PCK1_Pos 9 /**< (PMC_SCDR) Programmable Clock 1 Output Disable Position */ +#define PMC_SCDR_PCK1_Msk (_U_(0x1) << PMC_SCDR_PCK1_Pos) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Mask */ +#define PMC_SCDR_PCK1 PMC_SCDR_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK1_Msk instead */ +#define PMC_SCDR_PCK2_Pos 10 /**< (PMC_SCDR) Programmable Clock 2 Output Disable Position */ +#define PMC_SCDR_PCK2_Msk (_U_(0x1) << PMC_SCDR_PCK2_Pos) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Mask */ +#define PMC_SCDR_PCK2 PMC_SCDR_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK2_Msk instead */ +#define PMC_SCDR_PCK3_Pos 11 /**< (PMC_SCDR) Programmable Clock 3 Output Disable Position */ +#define PMC_SCDR_PCK3_Msk (_U_(0x1) << PMC_SCDR_PCK3_Pos) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Mask */ +#define PMC_SCDR_PCK3 PMC_SCDR_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK3_Msk instead */ +#define PMC_SCDR_PCK4_Pos 12 /**< (PMC_SCDR) Programmable Clock 4 Output Disable Position */ +#define PMC_SCDR_PCK4_Msk (_U_(0x1) << PMC_SCDR_PCK4_Pos) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Mask */ +#define PMC_SCDR_PCK4 PMC_SCDR_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK4_Msk instead */ +#define PMC_SCDR_PCK5_Pos 13 /**< (PMC_SCDR) Programmable Clock 5 Output Disable Position */ +#define PMC_SCDR_PCK5_Msk (_U_(0x1) << PMC_SCDR_PCK5_Pos) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Mask */ +#define PMC_SCDR_PCK5 PMC_SCDR_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK5_Msk instead */ +#define PMC_SCDR_PCK6_Pos 14 /**< (PMC_SCDR) Programmable Clock 6 Output Disable Position */ +#define PMC_SCDR_PCK6_Msk (_U_(0x1) << PMC_SCDR_PCK6_Pos) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Mask */ +#define PMC_SCDR_PCK6 PMC_SCDR_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK6_Msk instead */ +#define PMC_SCDR_PCK7_Pos 15 /**< (PMC_SCDR) Programmable Clock 7 Output Disable Position */ +#define PMC_SCDR_PCK7_Msk (_U_(0x1) << PMC_SCDR_PCK7_Pos) /**< (PMC_SCDR) Programmable Clock 7 Output Disable Mask */ +#define PMC_SCDR_PCK7 PMC_SCDR_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCDR_PCK7_Msk instead */ +#define PMC_SCDR_MASK _U_(0xFF20) /**< \deprecated (PMC_SCDR) Register MASK (Use PMC_SCDR_Msk instead) */ +#define PMC_SCDR_Msk _U_(0xFF20) /**< (PMC_SCDR) Register Mask */ + +#define PMC_SCDR_PCK_Pos 8 /**< (PMC_SCDR Position) Programmable Clock 7 Output Disable */ +#define PMC_SCDR_PCK_Msk (_U_(0xFF) << PMC_SCDR_PCK_Pos) /**< (PMC_SCDR Mask) PCK */ +#define PMC_SCDR_PCK(value) (PMC_SCDR_PCK_Msk & ((value) << PMC_SCDR_PCK_Pos)) + +/* -------- PMC_SCSR : (PMC Offset: 0x08) (R/ 32) System Clock Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HCLKS:1; /**< bit: 0 HCLK Status */ + uint32_t :4; /**< bit: 1..4 Reserved */ + uint32_t USBCLK:1; /**< bit: 5 USB FS Clock Status */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t PCK0:1; /**< bit: 8 Programmable Clock 0 Output Status */ + uint32_t PCK1:1; /**< bit: 9 Programmable Clock 1 Output Status */ + uint32_t PCK2:1; /**< bit: 10 Programmable Clock 2 Output Status */ + uint32_t PCK3:1; /**< bit: 11 Programmable Clock 3 Output Status */ + uint32_t PCK4:1; /**< bit: 12 Programmable Clock 4 Output Status */ + uint32_t PCK5:1; /**< bit: 13 Programmable Clock 5 Output Status */ + uint32_t PCK6:1; /**< bit: 14 Programmable Clock 6 Output Status */ + uint32_t PCK7:1; /**< bit: 15 Programmable Clock 7 Output Status */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCK:8; /**< bit: 8..15 Programmable Clock 7 Output Status */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SCSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SCSR_OFFSET (0x08) /**< (PMC_SCSR) System Clock Status Register Offset */ + +#define PMC_SCSR_HCLKS_Pos 0 /**< (PMC_SCSR) HCLK Status Position */ +#define PMC_SCSR_HCLKS_Msk (_U_(0x1) << PMC_SCSR_HCLKS_Pos) /**< (PMC_SCSR) HCLK Status Mask */ +#define PMC_SCSR_HCLKS PMC_SCSR_HCLKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_HCLKS_Msk instead */ +#define PMC_SCSR_USBCLK_Pos 5 /**< (PMC_SCSR) USB FS Clock Status Position */ +#define PMC_SCSR_USBCLK_Msk (_U_(0x1) << PMC_SCSR_USBCLK_Pos) /**< (PMC_SCSR) USB FS Clock Status Mask */ +#define PMC_SCSR_USBCLK PMC_SCSR_USBCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_USBCLK_Msk instead */ +#define PMC_SCSR_PCK0_Pos 8 /**< (PMC_SCSR) Programmable Clock 0 Output Status Position */ +#define PMC_SCSR_PCK0_Msk (_U_(0x1) << PMC_SCSR_PCK0_Pos) /**< (PMC_SCSR) Programmable Clock 0 Output Status Mask */ +#define PMC_SCSR_PCK0 PMC_SCSR_PCK0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK0_Msk instead */ +#define PMC_SCSR_PCK1_Pos 9 /**< (PMC_SCSR) Programmable Clock 1 Output Status Position */ +#define PMC_SCSR_PCK1_Msk (_U_(0x1) << PMC_SCSR_PCK1_Pos) /**< (PMC_SCSR) Programmable Clock 1 Output Status Mask */ +#define PMC_SCSR_PCK1 PMC_SCSR_PCK1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK1_Msk instead */ +#define PMC_SCSR_PCK2_Pos 10 /**< (PMC_SCSR) Programmable Clock 2 Output Status Position */ +#define PMC_SCSR_PCK2_Msk (_U_(0x1) << PMC_SCSR_PCK2_Pos) /**< (PMC_SCSR) Programmable Clock 2 Output Status Mask */ +#define PMC_SCSR_PCK2 PMC_SCSR_PCK2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK2_Msk instead */ +#define PMC_SCSR_PCK3_Pos 11 /**< (PMC_SCSR) Programmable Clock 3 Output Status Position */ +#define PMC_SCSR_PCK3_Msk (_U_(0x1) << PMC_SCSR_PCK3_Pos) /**< (PMC_SCSR) Programmable Clock 3 Output Status Mask */ +#define PMC_SCSR_PCK3 PMC_SCSR_PCK3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK3_Msk instead */ +#define PMC_SCSR_PCK4_Pos 12 /**< (PMC_SCSR) Programmable Clock 4 Output Status Position */ +#define PMC_SCSR_PCK4_Msk (_U_(0x1) << PMC_SCSR_PCK4_Pos) /**< (PMC_SCSR) Programmable Clock 4 Output Status Mask */ +#define PMC_SCSR_PCK4 PMC_SCSR_PCK4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK4_Msk instead */ +#define PMC_SCSR_PCK5_Pos 13 /**< (PMC_SCSR) Programmable Clock 5 Output Status Position */ +#define PMC_SCSR_PCK5_Msk (_U_(0x1) << PMC_SCSR_PCK5_Pos) /**< (PMC_SCSR) Programmable Clock 5 Output Status Mask */ +#define PMC_SCSR_PCK5 PMC_SCSR_PCK5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK5_Msk instead */ +#define PMC_SCSR_PCK6_Pos 14 /**< (PMC_SCSR) Programmable Clock 6 Output Status Position */ +#define PMC_SCSR_PCK6_Msk (_U_(0x1) << PMC_SCSR_PCK6_Pos) /**< (PMC_SCSR) Programmable Clock 6 Output Status Mask */ +#define PMC_SCSR_PCK6 PMC_SCSR_PCK6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK6_Msk instead */ +#define PMC_SCSR_PCK7_Pos 15 /**< (PMC_SCSR) Programmable Clock 7 Output Status Position */ +#define PMC_SCSR_PCK7_Msk (_U_(0x1) << PMC_SCSR_PCK7_Pos) /**< (PMC_SCSR) Programmable Clock 7 Output Status Mask */ +#define PMC_SCSR_PCK7 PMC_SCSR_PCK7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SCSR_PCK7_Msk instead */ +#define PMC_SCSR_MASK _U_(0xFF21) /**< \deprecated (PMC_SCSR) Register MASK (Use PMC_SCSR_Msk instead) */ +#define PMC_SCSR_Msk _U_(0xFF21) /**< (PMC_SCSR) Register Mask */ + +#define PMC_SCSR_PCK_Pos 8 /**< (PMC_SCSR Position) Programmable Clock 7 Output Status */ +#define PMC_SCSR_PCK_Msk (_U_(0xFF) << PMC_SCSR_PCK_Pos) /**< (PMC_SCSR Mask) PCK */ +#define PMC_SCSR_PCK(value) (PMC_SCSR_PCK_Msk & ((value) << PMC_SCSR_PCK_Pos)) + +/* -------- PMC_PCER0 : (PMC Offset: 0x10) (/W 32) Peripheral Clock Enable Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Enable */ + uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Enable */ + uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Enable */ + uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Enable */ + uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Enable */ + uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Enable */ + uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Enable */ + uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Enable */ + uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Enable */ + uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Enable */ + uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Enable */ + uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Enable */ + uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Enable */ + uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Enable */ + uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Enable */ + uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Enable */ + uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Enable */ + uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Enable */ + uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Enable */ + uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Enable */ + uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Enable */ + uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Enable */ + uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Enable */ + uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Enable */ + uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCER0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCER0_OFFSET (0x10) /**< (PMC_PCER0) Peripheral Clock Enable Register 0 Offset */ + +#define PMC_PCER0_PID7_Pos 7 /**< (PMC_PCER0) Peripheral Clock 7 Enable Position */ +#define PMC_PCER0_PID7_Msk (_U_(0x1) << PMC_PCER0_PID7_Pos) /**< (PMC_PCER0) Peripheral Clock 7 Enable Mask */ +#define PMC_PCER0_PID7 PMC_PCER0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID7_Msk instead */ +#define PMC_PCER0_PID8_Pos 8 /**< (PMC_PCER0) Peripheral Clock 8 Enable Position */ +#define PMC_PCER0_PID8_Msk (_U_(0x1) << PMC_PCER0_PID8_Pos) /**< (PMC_PCER0) Peripheral Clock 8 Enable Mask */ +#define PMC_PCER0_PID8 PMC_PCER0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID8_Msk instead */ +#define PMC_PCER0_PID9_Pos 9 /**< (PMC_PCER0) Peripheral Clock 9 Enable Position */ +#define PMC_PCER0_PID9_Msk (_U_(0x1) << PMC_PCER0_PID9_Pos) /**< (PMC_PCER0) Peripheral Clock 9 Enable Mask */ +#define PMC_PCER0_PID9 PMC_PCER0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID9_Msk instead */ +#define PMC_PCER0_PID10_Pos 10 /**< (PMC_PCER0) Peripheral Clock 10 Enable Position */ +#define PMC_PCER0_PID10_Msk (_U_(0x1) << PMC_PCER0_PID10_Pos) /**< (PMC_PCER0) Peripheral Clock 10 Enable Mask */ +#define PMC_PCER0_PID10 PMC_PCER0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID10_Msk instead */ +#define PMC_PCER0_PID11_Pos 11 /**< (PMC_PCER0) Peripheral Clock 11 Enable Position */ +#define PMC_PCER0_PID11_Msk (_U_(0x1) << PMC_PCER0_PID11_Pos) /**< (PMC_PCER0) Peripheral Clock 11 Enable Mask */ +#define PMC_PCER0_PID11 PMC_PCER0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID11_Msk instead */ +#define PMC_PCER0_PID12_Pos 12 /**< (PMC_PCER0) Peripheral Clock 12 Enable Position */ +#define PMC_PCER0_PID12_Msk (_U_(0x1) << PMC_PCER0_PID12_Pos) /**< (PMC_PCER0) Peripheral Clock 12 Enable Mask */ +#define PMC_PCER0_PID12 PMC_PCER0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID12_Msk instead */ +#define PMC_PCER0_PID13_Pos 13 /**< (PMC_PCER0) Peripheral Clock 13 Enable Position */ +#define PMC_PCER0_PID13_Msk (_U_(0x1) << PMC_PCER0_PID13_Pos) /**< (PMC_PCER0) Peripheral Clock 13 Enable Mask */ +#define PMC_PCER0_PID13 PMC_PCER0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID13_Msk instead */ +#define PMC_PCER0_PID14_Pos 14 /**< (PMC_PCER0) Peripheral Clock 14 Enable Position */ +#define PMC_PCER0_PID14_Msk (_U_(0x1) << PMC_PCER0_PID14_Pos) /**< (PMC_PCER0) Peripheral Clock 14 Enable Mask */ +#define PMC_PCER0_PID14 PMC_PCER0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID14_Msk instead */ +#define PMC_PCER0_PID15_Pos 15 /**< (PMC_PCER0) Peripheral Clock 15 Enable Position */ +#define PMC_PCER0_PID15_Msk (_U_(0x1) << PMC_PCER0_PID15_Pos) /**< (PMC_PCER0) Peripheral Clock 15 Enable Mask */ +#define PMC_PCER0_PID15 PMC_PCER0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID15_Msk instead */ +#define PMC_PCER0_PID16_Pos 16 /**< (PMC_PCER0) Peripheral Clock 16 Enable Position */ +#define PMC_PCER0_PID16_Msk (_U_(0x1) << PMC_PCER0_PID16_Pos) /**< (PMC_PCER0) Peripheral Clock 16 Enable Mask */ +#define PMC_PCER0_PID16 PMC_PCER0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID16_Msk instead */ +#define PMC_PCER0_PID17_Pos 17 /**< (PMC_PCER0) Peripheral Clock 17 Enable Position */ +#define PMC_PCER0_PID17_Msk (_U_(0x1) << PMC_PCER0_PID17_Pos) /**< (PMC_PCER0) Peripheral Clock 17 Enable Mask */ +#define PMC_PCER0_PID17 PMC_PCER0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID17_Msk instead */ +#define PMC_PCER0_PID18_Pos 18 /**< (PMC_PCER0) Peripheral Clock 18 Enable Position */ +#define PMC_PCER0_PID18_Msk (_U_(0x1) << PMC_PCER0_PID18_Pos) /**< (PMC_PCER0) Peripheral Clock 18 Enable Mask */ +#define PMC_PCER0_PID18 PMC_PCER0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID18_Msk instead */ +#define PMC_PCER0_PID19_Pos 19 /**< (PMC_PCER0) Peripheral Clock 19 Enable Position */ +#define PMC_PCER0_PID19_Msk (_U_(0x1) << PMC_PCER0_PID19_Pos) /**< (PMC_PCER0) Peripheral Clock 19 Enable Mask */ +#define PMC_PCER0_PID19 PMC_PCER0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID19_Msk instead */ +#define PMC_PCER0_PID20_Pos 20 /**< (PMC_PCER0) Peripheral Clock 20 Enable Position */ +#define PMC_PCER0_PID20_Msk (_U_(0x1) << PMC_PCER0_PID20_Pos) /**< (PMC_PCER0) Peripheral Clock 20 Enable Mask */ +#define PMC_PCER0_PID20 PMC_PCER0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID20_Msk instead */ +#define PMC_PCER0_PID21_Pos 21 /**< (PMC_PCER0) Peripheral Clock 21 Enable Position */ +#define PMC_PCER0_PID21_Msk (_U_(0x1) << PMC_PCER0_PID21_Pos) /**< (PMC_PCER0) Peripheral Clock 21 Enable Mask */ +#define PMC_PCER0_PID21 PMC_PCER0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID21_Msk instead */ +#define PMC_PCER0_PID22_Pos 22 /**< (PMC_PCER0) Peripheral Clock 22 Enable Position */ +#define PMC_PCER0_PID22_Msk (_U_(0x1) << PMC_PCER0_PID22_Pos) /**< (PMC_PCER0) Peripheral Clock 22 Enable Mask */ +#define PMC_PCER0_PID22 PMC_PCER0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID22_Msk instead */ +#define PMC_PCER0_PID23_Pos 23 /**< (PMC_PCER0) Peripheral Clock 23 Enable Position */ +#define PMC_PCER0_PID23_Msk (_U_(0x1) << PMC_PCER0_PID23_Pos) /**< (PMC_PCER0) Peripheral Clock 23 Enable Mask */ +#define PMC_PCER0_PID23 PMC_PCER0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID23_Msk instead */ +#define PMC_PCER0_PID24_Pos 24 /**< (PMC_PCER0) Peripheral Clock 24 Enable Position */ +#define PMC_PCER0_PID24_Msk (_U_(0x1) << PMC_PCER0_PID24_Pos) /**< (PMC_PCER0) Peripheral Clock 24 Enable Mask */ +#define PMC_PCER0_PID24 PMC_PCER0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID24_Msk instead */ +#define PMC_PCER0_PID25_Pos 25 /**< (PMC_PCER0) Peripheral Clock 25 Enable Position */ +#define PMC_PCER0_PID25_Msk (_U_(0x1) << PMC_PCER0_PID25_Pos) /**< (PMC_PCER0) Peripheral Clock 25 Enable Mask */ +#define PMC_PCER0_PID25 PMC_PCER0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID25_Msk instead */ +#define PMC_PCER0_PID26_Pos 26 /**< (PMC_PCER0) Peripheral Clock 26 Enable Position */ +#define PMC_PCER0_PID26_Msk (_U_(0x1) << PMC_PCER0_PID26_Pos) /**< (PMC_PCER0) Peripheral Clock 26 Enable Mask */ +#define PMC_PCER0_PID26 PMC_PCER0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID26_Msk instead */ +#define PMC_PCER0_PID27_Pos 27 /**< (PMC_PCER0) Peripheral Clock 27 Enable Position */ +#define PMC_PCER0_PID27_Msk (_U_(0x1) << PMC_PCER0_PID27_Pos) /**< (PMC_PCER0) Peripheral Clock 27 Enable Mask */ +#define PMC_PCER0_PID27 PMC_PCER0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID27_Msk instead */ +#define PMC_PCER0_PID28_Pos 28 /**< (PMC_PCER0) Peripheral Clock 28 Enable Position */ +#define PMC_PCER0_PID28_Msk (_U_(0x1) << PMC_PCER0_PID28_Pos) /**< (PMC_PCER0) Peripheral Clock 28 Enable Mask */ +#define PMC_PCER0_PID28 PMC_PCER0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID28_Msk instead */ +#define PMC_PCER0_PID29_Pos 29 /**< (PMC_PCER0) Peripheral Clock 29 Enable Position */ +#define PMC_PCER0_PID29_Msk (_U_(0x1) << PMC_PCER0_PID29_Pos) /**< (PMC_PCER0) Peripheral Clock 29 Enable Mask */ +#define PMC_PCER0_PID29 PMC_PCER0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID29_Msk instead */ +#define PMC_PCER0_PID30_Pos 30 /**< (PMC_PCER0) Peripheral Clock 30 Enable Position */ +#define PMC_PCER0_PID30_Msk (_U_(0x1) << PMC_PCER0_PID30_Pos) /**< (PMC_PCER0) Peripheral Clock 30 Enable Mask */ +#define PMC_PCER0_PID30 PMC_PCER0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID30_Msk instead */ +#define PMC_PCER0_PID31_Pos 31 /**< (PMC_PCER0) Peripheral Clock 31 Enable Position */ +#define PMC_PCER0_PID31_Msk (_U_(0x1) << PMC_PCER0_PID31_Pos) /**< (PMC_PCER0) Peripheral Clock 31 Enable Mask */ +#define PMC_PCER0_PID31 PMC_PCER0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER0_PID31_Msk instead */ +#define PMC_PCER0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCER0) Register MASK (Use PMC_PCER0_Msk instead) */ +#define PMC_PCER0_Msk _U_(0xFFFFFF80) /**< (PMC_PCER0) Register Mask */ + +#define PMC_PCER0_PID_Pos 7 /**< (PMC_PCER0 Position) Peripheral Clock 3x Enable */ +#define PMC_PCER0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER0_PID_Pos) /**< (PMC_PCER0 Mask) PID */ +#define PMC_PCER0_PID(value) (PMC_PCER0_PID_Msk & ((value) << PMC_PCER0_PID_Pos)) + +/* -------- PMC_PCDR0 : (PMC Offset: 0x14) (/W 32) Peripheral Clock Disable Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Disable */ + uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Disable */ + uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Disable */ + uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Disable */ + uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Disable */ + uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Disable */ + uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Disable */ + uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Disable */ + uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Disable */ + uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Disable */ + uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Disable */ + uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Disable */ + uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Disable */ + uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Disable */ + uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Disable */ + uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Disable */ + uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Disable */ + uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Disable */ + uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Disable */ + uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Disable */ + uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Disable */ + uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Disable */ + uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Disable */ + uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Disable */ + uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCDR0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCDR0_OFFSET (0x14) /**< (PMC_PCDR0) Peripheral Clock Disable Register 0 Offset */ + +#define PMC_PCDR0_PID7_Pos 7 /**< (PMC_PCDR0) Peripheral Clock 7 Disable Position */ +#define PMC_PCDR0_PID7_Msk (_U_(0x1) << PMC_PCDR0_PID7_Pos) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Mask */ +#define PMC_PCDR0_PID7 PMC_PCDR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID7_Msk instead */ +#define PMC_PCDR0_PID8_Pos 8 /**< (PMC_PCDR0) Peripheral Clock 8 Disable Position */ +#define PMC_PCDR0_PID8_Msk (_U_(0x1) << PMC_PCDR0_PID8_Pos) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Mask */ +#define PMC_PCDR0_PID8 PMC_PCDR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID8_Msk instead */ +#define PMC_PCDR0_PID9_Pos 9 /**< (PMC_PCDR0) Peripheral Clock 9 Disable Position */ +#define PMC_PCDR0_PID9_Msk (_U_(0x1) << PMC_PCDR0_PID9_Pos) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Mask */ +#define PMC_PCDR0_PID9 PMC_PCDR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID9_Msk instead */ +#define PMC_PCDR0_PID10_Pos 10 /**< (PMC_PCDR0) Peripheral Clock 10 Disable Position */ +#define PMC_PCDR0_PID10_Msk (_U_(0x1) << PMC_PCDR0_PID10_Pos) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Mask */ +#define PMC_PCDR0_PID10 PMC_PCDR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID10_Msk instead */ +#define PMC_PCDR0_PID11_Pos 11 /**< (PMC_PCDR0) Peripheral Clock 11 Disable Position */ +#define PMC_PCDR0_PID11_Msk (_U_(0x1) << PMC_PCDR0_PID11_Pos) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Mask */ +#define PMC_PCDR0_PID11 PMC_PCDR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID11_Msk instead */ +#define PMC_PCDR0_PID12_Pos 12 /**< (PMC_PCDR0) Peripheral Clock 12 Disable Position */ +#define PMC_PCDR0_PID12_Msk (_U_(0x1) << PMC_PCDR0_PID12_Pos) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Mask */ +#define PMC_PCDR0_PID12 PMC_PCDR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID12_Msk instead */ +#define PMC_PCDR0_PID13_Pos 13 /**< (PMC_PCDR0) Peripheral Clock 13 Disable Position */ +#define PMC_PCDR0_PID13_Msk (_U_(0x1) << PMC_PCDR0_PID13_Pos) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Mask */ +#define PMC_PCDR0_PID13 PMC_PCDR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID13_Msk instead */ +#define PMC_PCDR0_PID14_Pos 14 /**< (PMC_PCDR0) Peripheral Clock 14 Disable Position */ +#define PMC_PCDR0_PID14_Msk (_U_(0x1) << PMC_PCDR0_PID14_Pos) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Mask */ +#define PMC_PCDR0_PID14 PMC_PCDR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID14_Msk instead */ +#define PMC_PCDR0_PID15_Pos 15 /**< (PMC_PCDR0) Peripheral Clock 15 Disable Position */ +#define PMC_PCDR0_PID15_Msk (_U_(0x1) << PMC_PCDR0_PID15_Pos) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Mask */ +#define PMC_PCDR0_PID15 PMC_PCDR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID15_Msk instead */ +#define PMC_PCDR0_PID16_Pos 16 /**< (PMC_PCDR0) Peripheral Clock 16 Disable Position */ +#define PMC_PCDR0_PID16_Msk (_U_(0x1) << PMC_PCDR0_PID16_Pos) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Mask */ +#define PMC_PCDR0_PID16 PMC_PCDR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID16_Msk instead */ +#define PMC_PCDR0_PID17_Pos 17 /**< (PMC_PCDR0) Peripheral Clock 17 Disable Position */ +#define PMC_PCDR0_PID17_Msk (_U_(0x1) << PMC_PCDR0_PID17_Pos) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Mask */ +#define PMC_PCDR0_PID17 PMC_PCDR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID17_Msk instead */ +#define PMC_PCDR0_PID18_Pos 18 /**< (PMC_PCDR0) Peripheral Clock 18 Disable Position */ +#define PMC_PCDR0_PID18_Msk (_U_(0x1) << PMC_PCDR0_PID18_Pos) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Mask */ +#define PMC_PCDR0_PID18 PMC_PCDR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID18_Msk instead */ +#define PMC_PCDR0_PID19_Pos 19 /**< (PMC_PCDR0) Peripheral Clock 19 Disable Position */ +#define PMC_PCDR0_PID19_Msk (_U_(0x1) << PMC_PCDR0_PID19_Pos) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Mask */ +#define PMC_PCDR0_PID19 PMC_PCDR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID19_Msk instead */ +#define PMC_PCDR0_PID20_Pos 20 /**< (PMC_PCDR0) Peripheral Clock 20 Disable Position */ +#define PMC_PCDR0_PID20_Msk (_U_(0x1) << PMC_PCDR0_PID20_Pos) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Mask */ +#define PMC_PCDR0_PID20 PMC_PCDR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID20_Msk instead */ +#define PMC_PCDR0_PID21_Pos 21 /**< (PMC_PCDR0) Peripheral Clock 21 Disable Position */ +#define PMC_PCDR0_PID21_Msk (_U_(0x1) << PMC_PCDR0_PID21_Pos) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Mask */ +#define PMC_PCDR0_PID21 PMC_PCDR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID21_Msk instead */ +#define PMC_PCDR0_PID22_Pos 22 /**< (PMC_PCDR0) Peripheral Clock 22 Disable Position */ +#define PMC_PCDR0_PID22_Msk (_U_(0x1) << PMC_PCDR0_PID22_Pos) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Mask */ +#define PMC_PCDR0_PID22 PMC_PCDR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID22_Msk instead */ +#define PMC_PCDR0_PID23_Pos 23 /**< (PMC_PCDR0) Peripheral Clock 23 Disable Position */ +#define PMC_PCDR0_PID23_Msk (_U_(0x1) << PMC_PCDR0_PID23_Pos) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Mask */ +#define PMC_PCDR0_PID23 PMC_PCDR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID23_Msk instead */ +#define PMC_PCDR0_PID24_Pos 24 /**< (PMC_PCDR0) Peripheral Clock 24 Disable Position */ +#define PMC_PCDR0_PID24_Msk (_U_(0x1) << PMC_PCDR0_PID24_Pos) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Mask */ +#define PMC_PCDR0_PID24 PMC_PCDR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID24_Msk instead */ +#define PMC_PCDR0_PID25_Pos 25 /**< (PMC_PCDR0) Peripheral Clock 25 Disable Position */ +#define PMC_PCDR0_PID25_Msk (_U_(0x1) << PMC_PCDR0_PID25_Pos) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Mask */ +#define PMC_PCDR0_PID25 PMC_PCDR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID25_Msk instead */ +#define PMC_PCDR0_PID26_Pos 26 /**< (PMC_PCDR0) Peripheral Clock 26 Disable Position */ +#define PMC_PCDR0_PID26_Msk (_U_(0x1) << PMC_PCDR0_PID26_Pos) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Mask */ +#define PMC_PCDR0_PID26 PMC_PCDR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID26_Msk instead */ +#define PMC_PCDR0_PID27_Pos 27 /**< (PMC_PCDR0) Peripheral Clock 27 Disable Position */ +#define PMC_PCDR0_PID27_Msk (_U_(0x1) << PMC_PCDR0_PID27_Pos) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Mask */ +#define PMC_PCDR0_PID27 PMC_PCDR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID27_Msk instead */ +#define PMC_PCDR0_PID28_Pos 28 /**< (PMC_PCDR0) Peripheral Clock 28 Disable Position */ +#define PMC_PCDR0_PID28_Msk (_U_(0x1) << PMC_PCDR0_PID28_Pos) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Mask */ +#define PMC_PCDR0_PID28 PMC_PCDR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID28_Msk instead */ +#define PMC_PCDR0_PID29_Pos 29 /**< (PMC_PCDR0) Peripheral Clock 29 Disable Position */ +#define PMC_PCDR0_PID29_Msk (_U_(0x1) << PMC_PCDR0_PID29_Pos) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Mask */ +#define PMC_PCDR0_PID29 PMC_PCDR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID29_Msk instead */ +#define PMC_PCDR0_PID30_Pos 30 /**< (PMC_PCDR0) Peripheral Clock 30 Disable Position */ +#define PMC_PCDR0_PID30_Msk (_U_(0x1) << PMC_PCDR0_PID30_Pos) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Mask */ +#define PMC_PCDR0_PID30 PMC_PCDR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID30_Msk instead */ +#define PMC_PCDR0_PID31_Pos 31 /**< (PMC_PCDR0) Peripheral Clock 31 Disable Position */ +#define PMC_PCDR0_PID31_Msk (_U_(0x1) << PMC_PCDR0_PID31_Pos) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Mask */ +#define PMC_PCDR0_PID31 PMC_PCDR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR0_PID31_Msk instead */ +#define PMC_PCDR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCDR0) Register MASK (Use PMC_PCDR0_Msk instead) */ +#define PMC_PCDR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCDR0) Register Mask */ + +#define PMC_PCDR0_PID_Pos 7 /**< (PMC_PCDR0 Position) Peripheral Clock 3x Disable */ +#define PMC_PCDR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR0_PID_Pos) /**< (PMC_PCDR0 Mask) PID */ +#define PMC_PCDR0_PID(value) (PMC_PCDR0_PID_Msk & ((value) << PMC_PCDR0_PID_Pos)) + +/* -------- PMC_PCSR0 : (PMC Offset: 0x18) (R/ 32) Peripheral Clock Status Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral Clock 7 Status */ + uint32_t PID8:1; /**< bit: 8 Peripheral Clock 8 Status */ + uint32_t PID9:1; /**< bit: 9 Peripheral Clock 9 Status */ + uint32_t PID10:1; /**< bit: 10 Peripheral Clock 10 Status */ + uint32_t PID11:1; /**< bit: 11 Peripheral Clock 11 Status */ + uint32_t PID12:1; /**< bit: 12 Peripheral Clock 12 Status */ + uint32_t PID13:1; /**< bit: 13 Peripheral Clock 13 Status */ + uint32_t PID14:1; /**< bit: 14 Peripheral Clock 14 Status */ + uint32_t PID15:1; /**< bit: 15 Peripheral Clock 15 Status */ + uint32_t PID16:1; /**< bit: 16 Peripheral Clock 16 Status */ + uint32_t PID17:1; /**< bit: 17 Peripheral Clock 17 Status */ + uint32_t PID18:1; /**< bit: 18 Peripheral Clock 18 Status */ + uint32_t PID19:1; /**< bit: 19 Peripheral Clock 19 Status */ + uint32_t PID20:1; /**< bit: 20 Peripheral Clock 20 Status */ + uint32_t PID21:1; /**< bit: 21 Peripheral Clock 21 Status */ + uint32_t PID22:1; /**< bit: 22 Peripheral Clock 22 Status */ + uint32_t PID23:1; /**< bit: 23 Peripheral Clock 23 Status */ + uint32_t PID24:1; /**< bit: 24 Peripheral Clock 24 Status */ + uint32_t PID25:1; /**< bit: 25 Peripheral Clock 25 Status */ + uint32_t PID26:1; /**< bit: 26 Peripheral Clock 26 Status */ + uint32_t PID27:1; /**< bit: 27 Peripheral Clock 27 Status */ + uint32_t PID28:1; /**< bit: 28 Peripheral Clock 28 Status */ + uint32_t PID29:1; /**< bit: 29 Peripheral Clock 29 Status */ + uint32_t PID30:1; /**< bit: 30 Peripheral Clock 30 Status */ + uint32_t PID31:1; /**< bit: 31 Peripheral Clock 31 Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral Clock 3x Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCSR0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCSR0_OFFSET (0x18) /**< (PMC_PCSR0) Peripheral Clock Status Register 0 Offset */ + +#define PMC_PCSR0_PID7_Pos 7 /**< (PMC_PCSR0) Peripheral Clock 7 Status Position */ +#define PMC_PCSR0_PID7_Msk (_U_(0x1) << PMC_PCSR0_PID7_Pos) /**< (PMC_PCSR0) Peripheral Clock 7 Status Mask */ +#define PMC_PCSR0_PID7 PMC_PCSR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID7_Msk instead */ +#define PMC_PCSR0_PID8_Pos 8 /**< (PMC_PCSR0) Peripheral Clock 8 Status Position */ +#define PMC_PCSR0_PID8_Msk (_U_(0x1) << PMC_PCSR0_PID8_Pos) /**< (PMC_PCSR0) Peripheral Clock 8 Status Mask */ +#define PMC_PCSR0_PID8 PMC_PCSR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID8_Msk instead */ +#define PMC_PCSR0_PID9_Pos 9 /**< (PMC_PCSR0) Peripheral Clock 9 Status Position */ +#define PMC_PCSR0_PID9_Msk (_U_(0x1) << PMC_PCSR0_PID9_Pos) /**< (PMC_PCSR0) Peripheral Clock 9 Status Mask */ +#define PMC_PCSR0_PID9 PMC_PCSR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID9_Msk instead */ +#define PMC_PCSR0_PID10_Pos 10 /**< (PMC_PCSR0) Peripheral Clock 10 Status Position */ +#define PMC_PCSR0_PID10_Msk (_U_(0x1) << PMC_PCSR0_PID10_Pos) /**< (PMC_PCSR0) Peripheral Clock 10 Status Mask */ +#define PMC_PCSR0_PID10 PMC_PCSR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID10_Msk instead */ +#define PMC_PCSR0_PID11_Pos 11 /**< (PMC_PCSR0) Peripheral Clock 11 Status Position */ +#define PMC_PCSR0_PID11_Msk (_U_(0x1) << PMC_PCSR0_PID11_Pos) /**< (PMC_PCSR0) Peripheral Clock 11 Status Mask */ +#define PMC_PCSR0_PID11 PMC_PCSR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID11_Msk instead */ +#define PMC_PCSR0_PID12_Pos 12 /**< (PMC_PCSR0) Peripheral Clock 12 Status Position */ +#define PMC_PCSR0_PID12_Msk (_U_(0x1) << PMC_PCSR0_PID12_Pos) /**< (PMC_PCSR0) Peripheral Clock 12 Status Mask */ +#define PMC_PCSR0_PID12 PMC_PCSR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID12_Msk instead */ +#define PMC_PCSR0_PID13_Pos 13 /**< (PMC_PCSR0) Peripheral Clock 13 Status Position */ +#define PMC_PCSR0_PID13_Msk (_U_(0x1) << PMC_PCSR0_PID13_Pos) /**< (PMC_PCSR0) Peripheral Clock 13 Status Mask */ +#define PMC_PCSR0_PID13 PMC_PCSR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID13_Msk instead */ +#define PMC_PCSR0_PID14_Pos 14 /**< (PMC_PCSR0) Peripheral Clock 14 Status Position */ +#define PMC_PCSR0_PID14_Msk (_U_(0x1) << PMC_PCSR0_PID14_Pos) /**< (PMC_PCSR0) Peripheral Clock 14 Status Mask */ +#define PMC_PCSR0_PID14 PMC_PCSR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID14_Msk instead */ +#define PMC_PCSR0_PID15_Pos 15 /**< (PMC_PCSR0) Peripheral Clock 15 Status Position */ +#define PMC_PCSR0_PID15_Msk (_U_(0x1) << PMC_PCSR0_PID15_Pos) /**< (PMC_PCSR0) Peripheral Clock 15 Status Mask */ +#define PMC_PCSR0_PID15 PMC_PCSR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID15_Msk instead */ +#define PMC_PCSR0_PID16_Pos 16 /**< (PMC_PCSR0) Peripheral Clock 16 Status Position */ +#define PMC_PCSR0_PID16_Msk (_U_(0x1) << PMC_PCSR0_PID16_Pos) /**< (PMC_PCSR0) Peripheral Clock 16 Status Mask */ +#define PMC_PCSR0_PID16 PMC_PCSR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID16_Msk instead */ +#define PMC_PCSR0_PID17_Pos 17 /**< (PMC_PCSR0) Peripheral Clock 17 Status Position */ +#define PMC_PCSR0_PID17_Msk (_U_(0x1) << PMC_PCSR0_PID17_Pos) /**< (PMC_PCSR0) Peripheral Clock 17 Status Mask */ +#define PMC_PCSR0_PID17 PMC_PCSR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID17_Msk instead */ +#define PMC_PCSR0_PID18_Pos 18 /**< (PMC_PCSR0) Peripheral Clock 18 Status Position */ +#define PMC_PCSR0_PID18_Msk (_U_(0x1) << PMC_PCSR0_PID18_Pos) /**< (PMC_PCSR0) Peripheral Clock 18 Status Mask */ +#define PMC_PCSR0_PID18 PMC_PCSR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID18_Msk instead */ +#define PMC_PCSR0_PID19_Pos 19 /**< (PMC_PCSR0) Peripheral Clock 19 Status Position */ +#define PMC_PCSR0_PID19_Msk (_U_(0x1) << PMC_PCSR0_PID19_Pos) /**< (PMC_PCSR0) Peripheral Clock 19 Status Mask */ +#define PMC_PCSR0_PID19 PMC_PCSR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID19_Msk instead */ +#define PMC_PCSR0_PID20_Pos 20 /**< (PMC_PCSR0) Peripheral Clock 20 Status Position */ +#define PMC_PCSR0_PID20_Msk (_U_(0x1) << PMC_PCSR0_PID20_Pos) /**< (PMC_PCSR0) Peripheral Clock 20 Status Mask */ +#define PMC_PCSR0_PID20 PMC_PCSR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID20_Msk instead */ +#define PMC_PCSR0_PID21_Pos 21 /**< (PMC_PCSR0) Peripheral Clock 21 Status Position */ +#define PMC_PCSR0_PID21_Msk (_U_(0x1) << PMC_PCSR0_PID21_Pos) /**< (PMC_PCSR0) Peripheral Clock 21 Status Mask */ +#define PMC_PCSR0_PID21 PMC_PCSR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID21_Msk instead */ +#define PMC_PCSR0_PID22_Pos 22 /**< (PMC_PCSR0) Peripheral Clock 22 Status Position */ +#define PMC_PCSR0_PID22_Msk (_U_(0x1) << PMC_PCSR0_PID22_Pos) /**< (PMC_PCSR0) Peripheral Clock 22 Status Mask */ +#define PMC_PCSR0_PID22 PMC_PCSR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID22_Msk instead */ +#define PMC_PCSR0_PID23_Pos 23 /**< (PMC_PCSR0) Peripheral Clock 23 Status Position */ +#define PMC_PCSR0_PID23_Msk (_U_(0x1) << PMC_PCSR0_PID23_Pos) /**< (PMC_PCSR0) Peripheral Clock 23 Status Mask */ +#define PMC_PCSR0_PID23 PMC_PCSR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID23_Msk instead */ +#define PMC_PCSR0_PID24_Pos 24 /**< (PMC_PCSR0) Peripheral Clock 24 Status Position */ +#define PMC_PCSR0_PID24_Msk (_U_(0x1) << PMC_PCSR0_PID24_Pos) /**< (PMC_PCSR0) Peripheral Clock 24 Status Mask */ +#define PMC_PCSR0_PID24 PMC_PCSR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID24_Msk instead */ +#define PMC_PCSR0_PID25_Pos 25 /**< (PMC_PCSR0) Peripheral Clock 25 Status Position */ +#define PMC_PCSR0_PID25_Msk (_U_(0x1) << PMC_PCSR0_PID25_Pos) /**< (PMC_PCSR0) Peripheral Clock 25 Status Mask */ +#define PMC_PCSR0_PID25 PMC_PCSR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID25_Msk instead */ +#define PMC_PCSR0_PID26_Pos 26 /**< (PMC_PCSR0) Peripheral Clock 26 Status Position */ +#define PMC_PCSR0_PID26_Msk (_U_(0x1) << PMC_PCSR0_PID26_Pos) /**< (PMC_PCSR0) Peripheral Clock 26 Status Mask */ +#define PMC_PCSR0_PID26 PMC_PCSR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID26_Msk instead */ +#define PMC_PCSR0_PID27_Pos 27 /**< (PMC_PCSR0) Peripheral Clock 27 Status Position */ +#define PMC_PCSR0_PID27_Msk (_U_(0x1) << PMC_PCSR0_PID27_Pos) /**< (PMC_PCSR0) Peripheral Clock 27 Status Mask */ +#define PMC_PCSR0_PID27 PMC_PCSR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID27_Msk instead */ +#define PMC_PCSR0_PID28_Pos 28 /**< (PMC_PCSR0) Peripheral Clock 28 Status Position */ +#define PMC_PCSR0_PID28_Msk (_U_(0x1) << PMC_PCSR0_PID28_Pos) /**< (PMC_PCSR0) Peripheral Clock 28 Status Mask */ +#define PMC_PCSR0_PID28 PMC_PCSR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID28_Msk instead */ +#define PMC_PCSR0_PID29_Pos 29 /**< (PMC_PCSR0) Peripheral Clock 29 Status Position */ +#define PMC_PCSR0_PID29_Msk (_U_(0x1) << PMC_PCSR0_PID29_Pos) /**< (PMC_PCSR0) Peripheral Clock 29 Status Mask */ +#define PMC_PCSR0_PID29 PMC_PCSR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID29_Msk instead */ +#define PMC_PCSR0_PID30_Pos 30 /**< (PMC_PCSR0) Peripheral Clock 30 Status Position */ +#define PMC_PCSR0_PID30_Msk (_U_(0x1) << PMC_PCSR0_PID30_Pos) /**< (PMC_PCSR0) Peripheral Clock 30 Status Mask */ +#define PMC_PCSR0_PID30 PMC_PCSR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID30_Msk instead */ +#define PMC_PCSR0_PID31_Pos 31 /**< (PMC_PCSR0) Peripheral Clock 31 Status Position */ +#define PMC_PCSR0_PID31_Msk (_U_(0x1) << PMC_PCSR0_PID31_Pos) /**< (PMC_PCSR0) Peripheral Clock 31 Status Mask */ +#define PMC_PCSR0_PID31 PMC_PCSR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR0_PID31_Msk instead */ +#define PMC_PCSR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_PCSR0) Register MASK (Use PMC_PCSR0_Msk instead) */ +#define PMC_PCSR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCSR0) Register Mask */ + +#define PMC_PCSR0_PID_Pos 7 /**< (PMC_PCSR0 Position) Peripheral Clock 3x Status */ +#define PMC_PCSR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR0_PID_Pos) /**< (PMC_PCSR0 Mask) PID */ +#define PMC_PCSR0_PID(value) (PMC_PCSR0_PID_Msk & ((value) << PMC_PCSR0_PID_Pos)) + +/* -------- CKGR_UCKR : (PMC Offset: 0x1c) (R/W 32) UTMI Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :16; /**< bit: 0..15 Reserved */ + uint32_t UPLLEN:1; /**< bit: 16 UTMI PLL Enable */ + uint32_t :3; /**< bit: 17..19 Reserved */ + uint32_t UPLLCOUNT:4; /**< bit: 20..23 UTMI PLL Start-up Time */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CKGR_UCKR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CKGR_UCKR_OFFSET (0x1C) /**< (CKGR_UCKR) UTMI Clock Register Offset */ + +#define CKGR_UCKR_UPLLEN_Pos 16 /**< (CKGR_UCKR) UTMI PLL Enable Position */ +#define CKGR_UCKR_UPLLEN_Msk (_U_(0x1) << CKGR_UCKR_UPLLEN_Pos) /**< (CKGR_UCKR) UTMI PLL Enable Mask */ +#define CKGR_UCKR_UPLLEN CKGR_UCKR_UPLLEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_UCKR_UPLLEN_Msk instead */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 /**< (CKGR_UCKR) UTMI PLL Start-up Time Position */ +#define CKGR_UCKR_UPLLCOUNT_Msk (_U_(0xF) << CKGR_UCKR_UPLLCOUNT_Pos) /**< (CKGR_UCKR) UTMI PLL Start-up Time Mask */ +#define CKGR_UCKR_UPLLCOUNT(value) (CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)) +#define CKGR_UCKR_MASK _U_(0xF10000) /**< \deprecated (CKGR_UCKR) Register MASK (Use CKGR_UCKR_Msk instead) */ +#define CKGR_UCKR_Msk _U_(0xF10000) /**< (CKGR_UCKR) Register Mask */ + + +/* -------- CKGR_MOR : (PMC Offset: 0x20) (R/W 32) Main Oscillator Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MOSCXTEN:1; /**< bit: 0 Main Crystal Oscillator Enable */ + uint32_t MOSCXTBY:1; /**< bit: 1 Main Crystal Oscillator Bypass */ + uint32_t WAITMODE:1; /**< bit: 2 Wait Mode Command (Write-only) */ + uint32_t MOSCRCEN:1; /**< bit: 3 Main RC Oscillator Enable */ + uint32_t MOSCRCF:3; /**< bit: 4..6 Main RC Oscillator Frequency Selection */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MOSCXTST:8; /**< bit: 8..15 Main Crystal Oscillator Startup Time */ + uint32_t KEY:8; /**< bit: 16..23 Write Access Password */ + uint32_t MOSCSEL:1; /**< bit: 24 Main Clock Oscillator Selection */ + uint32_t CFDEN:1; /**< bit: 25 Clock Failure Detector Enable */ + uint32_t XT32KFME:1; /**< bit: 26 32.768 kHz Crystal Oscillator Frequency Monitoring Enable */ + uint32_t :5; /**< bit: 27..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CKGR_MOR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CKGR_MOR_OFFSET (0x20) /**< (CKGR_MOR) Main Oscillator Register Offset */ + +#define CKGR_MOR_MOSCXTEN_Pos 0 /**< (CKGR_MOR) Main Crystal Oscillator Enable Position */ +#define CKGR_MOR_MOSCXTEN_Msk (_U_(0x1) << CKGR_MOR_MOSCXTEN_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Enable Mask */ +#define CKGR_MOR_MOSCXTEN CKGR_MOR_MOSCXTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCXTEN_Msk instead */ +#define CKGR_MOR_MOSCXTBY_Pos 1 /**< (CKGR_MOR) Main Crystal Oscillator Bypass Position */ +#define CKGR_MOR_MOSCXTBY_Msk (_U_(0x1) << CKGR_MOR_MOSCXTBY_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Mask */ +#define CKGR_MOR_MOSCXTBY CKGR_MOR_MOSCXTBY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCXTBY_Msk instead */ +#define CKGR_MOR_WAITMODE_Pos 2 /**< (CKGR_MOR) Wait Mode Command (Write-only) Position */ +#define CKGR_MOR_WAITMODE_Msk (_U_(0x1) << CKGR_MOR_WAITMODE_Pos) /**< (CKGR_MOR) Wait Mode Command (Write-only) Mask */ +#define CKGR_MOR_WAITMODE CKGR_MOR_WAITMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_WAITMODE_Msk instead */ +#define CKGR_MOR_MOSCRCEN_Pos 3 /**< (CKGR_MOR) Main RC Oscillator Enable Position */ +#define CKGR_MOR_MOSCRCEN_Msk (_U_(0x1) << CKGR_MOR_MOSCRCEN_Pos) /**< (CKGR_MOR) Main RC Oscillator Enable Mask */ +#define CKGR_MOR_MOSCRCEN CKGR_MOR_MOSCRCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCRCEN_Msk instead */ +#define CKGR_MOR_MOSCRCF_Pos 4 /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Position */ +#define CKGR_MOR_MOSCRCF_Msk (_U_(0x7) << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Mask */ +#define CKGR_MOR_MOSCRCF(value) (CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)) +#define CKGR_MOR_MOSCRCF_4_MHz_Val _U_(0x0) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz */ +#define CKGR_MOR_MOSCRCF_8_MHz_Val _U_(0x1) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz_Val _U_(0x2) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCRCF_4_MHz (CKGR_MOR_MOSCRCF_4_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz Position */ +#define CKGR_MOR_MOSCRCF_8_MHz (CKGR_MOR_MOSCRCF_8_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz Position */ +#define CKGR_MOR_MOSCRCF_12_MHz (CKGR_MOR_MOSCRCF_12_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz Position */ +#define CKGR_MOR_MOSCXTST_Pos 8 /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Position */ +#define CKGR_MOR_MOSCXTST_Msk (_U_(0xFF) << CKGR_MOR_MOSCXTST_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Mask */ +#define CKGR_MOR_MOSCXTST(value) (CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)) +#define CKGR_MOR_KEY_Pos 16 /**< (CKGR_MOR) Write Access Password Position */ +#define CKGR_MOR_KEY_Msk (_U_(0xFF) << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Write Access Password Mask */ +#define CKGR_MOR_KEY(value) (CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)) +#define CKGR_MOR_KEY_PASSWD_Val _U_(0x37) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_KEY_PASSWD (CKGR_MOR_KEY_PASSWD_Val << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define CKGR_MOR_MOSCSEL_Pos 24 /**< (CKGR_MOR) Main Clock Oscillator Selection Position */ +#define CKGR_MOR_MOSCSEL_Msk (_U_(0x1) << CKGR_MOR_MOSCSEL_Pos) /**< (CKGR_MOR) Main Clock Oscillator Selection Mask */ +#define CKGR_MOR_MOSCSEL CKGR_MOR_MOSCSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_MOSCSEL_Msk instead */ +#define CKGR_MOR_CFDEN_Pos 25 /**< (CKGR_MOR) Clock Failure Detector Enable Position */ +#define CKGR_MOR_CFDEN_Msk (_U_(0x1) << CKGR_MOR_CFDEN_Pos) /**< (CKGR_MOR) Clock Failure Detector Enable Mask */ +#define CKGR_MOR_CFDEN CKGR_MOR_CFDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_CFDEN_Msk instead */ +#define CKGR_MOR_XT32KFME_Pos 26 /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Position */ +#define CKGR_MOR_XT32KFME_Msk (_U_(0x1) << CKGR_MOR_XT32KFME_Pos) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Mask */ +#define CKGR_MOR_XT32KFME CKGR_MOR_XT32KFME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MOR_XT32KFME_Msk instead */ +#define CKGR_MOR_MASK _U_(0x7FFFF7F) /**< \deprecated (CKGR_MOR) Register MASK (Use CKGR_MOR_Msk instead) */ +#define CKGR_MOR_Msk _U_(0x7FFFF7F) /**< (CKGR_MOR) Register Mask */ + + +/* -------- CKGR_MCFR : (PMC Offset: 0x24) (R/W 32) Main Clock Frequency Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MAINF:16; /**< bit: 0..15 Main Clock Frequency */ + uint32_t MAINFRDY:1; /**< bit: 16 Main Clock Frequency Measure Ready */ + uint32_t :3; /**< bit: 17..19 Reserved */ + uint32_t RCMEAS:1; /**< bit: 20 RC Oscillator Frequency Measure (write-only) */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t CCSS:1; /**< bit: 24 Counter Clock Source Selection */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CKGR_MCFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CKGR_MCFR_OFFSET (0x24) /**< (CKGR_MCFR) Main Clock Frequency Register Offset */ + +#define CKGR_MCFR_MAINF_Pos 0 /**< (CKGR_MCFR) Main Clock Frequency Position */ +#define CKGR_MCFR_MAINF_Msk (_U_(0xFFFF) << CKGR_MCFR_MAINF_Pos) /**< (CKGR_MCFR) Main Clock Frequency Mask */ +#define CKGR_MCFR_MAINF(value) (CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)) +#define CKGR_MCFR_MAINFRDY_Pos 16 /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Position */ +#define CKGR_MCFR_MAINFRDY_Msk (_U_(0x1) << CKGR_MCFR_MAINFRDY_Pos) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Mask */ +#define CKGR_MCFR_MAINFRDY CKGR_MCFR_MAINFRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_MAINFRDY_Msk instead */ +#define CKGR_MCFR_RCMEAS_Pos 20 /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Position */ +#define CKGR_MCFR_RCMEAS_Msk (_U_(0x1) << CKGR_MCFR_RCMEAS_Pos) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Mask */ +#define CKGR_MCFR_RCMEAS CKGR_MCFR_RCMEAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_RCMEAS_Msk instead */ +#define CKGR_MCFR_CCSS_Pos 24 /**< (CKGR_MCFR) Counter Clock Source Selection Position */ +#define CKGR_MCFR_CCSS_Msk (_U_(0x1) << CKGR_MCFR_CCSS_Pos) /**< (CKGR_MCFR) Counter Clock Source Selection Mask */ +#define CKGR_MCFR_CCSS CKGR_MCFR_CCSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_MCFR_CCSS_Msk instead */ +#define CKGR_MCFR_MASK _U_(0x111FFFF) /**< \deprecated (CKGR_MCFR) Register MASK (Use CKGR_MCFR_Msk instead) */ +#define CKGR_MCFR_Msk _U_(0x111FFFF) /**< (CKGR_MCFR) Register Mask */ + + +/* -------- CKGR_PLLAR : (PMC Offset: 0x28) (R/W 32) PLLA Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DIVA:8; /**< bit: 0..7 PLLA Front End Divider */ + uint32_t PLLACOUNT:6; /**< bit: 8..13 PLLA Counter */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t MULA:11; /**< bit: 16..26 PLLA Multiplier */ + uint32_t :2; /**< bit: 27..28 Reserved */ + uint32_t ONE:1; /**< bit: 29 Must Be Set to 1 */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} CKGR_PLLAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CKGR_PLLAR_OFFSET (0x28) /**< (CKGR_PLLAR) PLLA Register Offset */ + +#define CKGR_PLLAR_DIVA_Pos 0 /**< (CKGR_PLLAR) PLLA Front End Divider Position */ +#define CKGR_PLLAR_DIVA_Msk (_U_(0xFF) << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) PLLA Front End Divider Mask */ +#define CKGR_PLLAR_DIVA(value) (CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)) +#define CKGR_PLLAR_DIVA_0_Val _U_(0x0) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS_Val _U_(0x1) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_DIVA_0 (CKGR_PLLAR_DIVA_0_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. Position */ +#define CKGR_PLLAR_DIVA_BYPASS (CKGR_PLLAR_DIVA_BYPASS_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. Position */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 /**< (CKGR_PLLAR) PLLA Counter Position */ +#define CKGR_PLLAR_PLLACOUNT_Msk (_U_(0x3F) << CKGR_PLLAR_PLLACOUNT_Pos) /**< (CKGR_PLLAR) PLLA Counter Mask */ +#define CKGR_PLLAR_PLLACOUNT(value) (CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)) +#define CKGR_PLLAR_MULA_Pos 16 /**< (CKGR_PLLAR) PLLA Multiplier Position */ +#define CKGR_PLLAR_MULA_Msk (_U_(0x7FF) << CKGR_PLLAR_MULA_Pos) /**< (CKGR_PLLAR) PLLA Multiplier Mask */ +#define CKGR_PLLAR_MULA(value) (CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)) +#define CKGR_PLLAR_ONE_Pos 29 /**< (CKGR_PLLAR) Must Be Set to 1 Position */ +#define CKGR_PLLAR_ONE_Msk (_U_(0x1) << CKGR_PLLAR_ONE_Pos) /**< (CKGR_PLLAR) Must Be Set to 1 Mask */ +#define CKGR_PLLAR_ONE CKGR_PLLAR_ONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CKGR_PLLAR_ONE_Msk instead */ +#define CKGR_PLLAR_MASK _U_(0x27FF3FFF) /**< \deprecated (CKGR_PLLAR) Register MASK (Use CKGR_PLLAR_Msk instead) */ +#define CKGR_PLLAR_Msk _U_(0x27FF3FFF) /**< (CKGR_PLLAR) Register Mask */ + + +/* -------- PMC_MCKR : (PMC Offset: 0x30) (R/W 32) Master Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSS:2; /**< bit: 0..1 Master Clock Source Selection */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t PRES:3; /**< bit: 4..6 Processor Clock Prescaler */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MDIV:2; /**< bit: 8..9 Master Clock Division */ + uint32_t :3; /**< bit: 10..12 Reserved */ + uint32_t UPLLDIV2:1; /**< bit: 13 UPLL Divider by 2 */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t UPLLDIV:1; /**< bit: 13 UPLL Divider by 2 */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_MCKR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_MCKR_OFFSET (0x30) /**< (PMC_MCKR) Master Clock Register Offset */ + +#define PMC_MCKR_CSS_Pos 0 /**< (PMC_MCKR) Master Clock Source Selection Position */ +#define PMC_MCKR_CSS_Msk (_U_(0x3) << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Master Clock Source Selection Mask */ +#define PMC_MCKR_CSS(value) (PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)) +#define PMC_MCKR_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_CSS_SLOW_CLK (PMC_MCKR_CSS_SLOW_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Slow Clock is selected Position */ +#define PMC_MCKR_CSS_MAIN_CLK (PMC_MCKR_CSS_MAIN_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Main Clock is selected Position */ +#define PMC_MCKR_CSS_PLLA_CLK (PMC_MCKR_CSS_PLLA_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) PLLA Clock is selected Position */ +#define PMC_MCKR_CSS_UPLL_CLK (PMC_MCKR_CSS_UPLL_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Divided UPLL Clock is selected Position */ +#define PMC_MCKR_PRES_Pos 4 /**< (PMC_MCKR) Processor Clock Prescaler Position */ +#define PMC_MCKR_PRES_Msk (_U_(0x7) << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Processor Clock Prescaler Mask */ +#define PMC_MCKR_PRES(value) (PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)) +#define PMC_MCKR_PRES_CLK_1_Val _U_(0x0) /**< (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2_Val _U_(0x1) /**< (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4_Val _U_(0x2) /**< (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8_Val _U_(0x3) /**< (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16_Val _U_(0x4) /**< (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32_Val _U_(0x5) /**< (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64_Val _U_(0x6) /**< (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3_Val _U_(0x7) /**< (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PRES_CLK_1 (PMC_MCKR_PRES_CLK_1_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock Position */ +#define PMC_MCKR_PRES_CLK_2 (PMC_MCKR_PRES_CLK_2_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 2 Position */ +#define PMC_MCKR_PRES_CLK_4 (PMC_MCKR_PRES_CLK_4_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 4 Position */ +#define PMC_MCKR_PRES_CLK_8 (PMC_MCKR_PRES_CLK_8_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 8 Position */ +#define PMC_MCKR_PRES_CLK_16 (PMC_MCKR_PRES_CLK_16_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 16 Position */ +#define PMC_MCKR_PRES_CLK_32 (PMC_MCKR_PRES_CLK_32_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 32 Position */ +#define PMC_MCKR_PRES_CLK_64 (PMC_MCKR_PRES_CLK_64_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 64 Position */ +#define PMC_MCKR_PRES_CLK_3 (PMC_MCKR_PRES_CLK_3_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 3 Position */ +#define PMC_MCKR_MDIV_Pos 8 /**< (PMC_MCKR) Master Clock Division Position */ +#define PMC_MCKR_MDIV_Msk (_U_(0x3) << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock Division Mask */ +#define PMC_MCKR_MDIV(value) (PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)) +#define PMC_MCKR_MDIV_EQ_PCK_Val _U_(0x0) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2_Val _U_(0x1) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4_Val _U_(0x2) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3_Val _U_(0x3) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_MDIV_EQ_PCK (PMC_MCKR_MDIV_EQ_PCK_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. Position */ +#define PMC_MCKR_MDIV_PCK_DIV2 (PMC_MCKR_MDIV_PCK_DIV2_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. Position */ +#define PMC_MCKR_MDIV_PCK_DIV4 (PMC_MCKR_MDIV_PCK_DIV4_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. Position */ +#define PMC_MCKR_MDIV_PCK_DIV3 (PMC_MCKR_MDIV_PCK_DIV3_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. Position */ +#define PMC_MCKR_UPLLDIV2_Pos 13 /**< (PMC_MCKR) UPLL Divider by 2 Position */ +#define PMC_MCKR_UPLLDIV2_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV2_Pos) /**< (PMC_MCKR) UPLL Divider by 2 Mask */ +#define PMC_MCKR_UPLLDIV2 PMC_MCKR_UPLLDIV2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_MCKR_UPLLDIV2_Msk instead */ +#define PMC_MCKR_MASK _U_(0x2373) /**< \deprecated (PMC_MCKR) Register MASK (Use PMC_MCKR_Msk instead) */ +#define PMC_MCKR_Msk _U_(0x2373) /**< (PMC_MCKR) Register Mask */ + +#define PMC_MCKR_UPLLDIV_Pos 13 /**< (PMC_MCKR Position) UPLL Divider by 2 */ +#define PMC_MCKR_UPLLDIV_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV_Pos) /**< (PMC_MCKR Mask) UPLLDIV */ +#define PMC_MCKR_UPLLDIV(value) (PMC_MCKR_UPLLDIV_Msk & ((value) << PMC_MCKR_UPLLDIV_Pos)) + +/* -------- PMC_USB : (PMC Offset: 0x38) (R/W 32) USB Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t USBS:1; /**< bit: 0 USB Input Clock Selection */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t USBDIV:4; /**< bit: 8..11 Divider for USB_48M */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_USB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_USB_OFFSET (0x38) /**< (PMC_USB) USB Clock Register Offset */ + +#define PMC_USB_USBS_Pos 0 /**< (PMC_USB) USB Input Clock Selection Position */ +#define PMC_USB_USBS_Msk (_U_(0x1) << PMC_USB_USBS_Pos) /**< (PMC_USB) USB Input Clock Selection Mask */ +#define PMC_USB_USBS PMC_USB_USBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_USB_USBS_Msk instead */ +#define PMC_USB_USBDIV_Pos 8 /**< (PMC_USB) Divider for USB_48M Position */ +#define PMC_USB_USBDIV_Msk (_U_(0xF) << PMC_USB_USBDIV_Pos) /**< (PMC_USB) Divider for USB_48M Mask */ +#define PMC_USB_USBDIV(value) (PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)) +#define PMC_USB_MASK _U_(0xF01) /**< \deprecated (PMC_USB) Register MASK (Use PMC_USB_Msk instead) */ +#define PMC_USB_Msk _U_(0xF01) /**< (PMC_USB) Register Mask */ + + +/* -------- PMC_PCK : (PMC Offset: 0x40) (R/W 32) Programmable Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSS:3; /**< bit: 0..2 Programmable Clock Source Selection */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t PRES:8; /**< bit: 4..11 Programmable Clock Prescaler */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCK_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCK_OFFSET (0x40) /**< (PMC_PCK) Programmable Clock Register Offset */ + +#define PMC_PCK_CSS_Pos 0 /**< (PMC_PCK) Programmable Clock Source Selection Position */ +#define PMC_PCK_CSS_Msk (_U_(0x7) << PMC_PCK_CSS_Pos) /**< (PMC_PCK) Programmable Clock Source Selection Mask */ +#define PMC_PCK_CSS(value) (PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)) +#define PMC_PCK_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCK) SLCK is selected */ +#define PMC_PCK_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCK) MAINCK is selected */ +#define PMC_PCK_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCK) PLLACK is selected */ +#define PMC_PCK_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCK) UPLLCKDIV is selected */ +#define PMC_PCK_CSS_MCK_Val _U_(0x4) /**< (PMC_PCK) MCK is selected */ +#define PMC_PCK_CSS_SLOW_CLK (PMC_PCK_CSS_SLOW_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) SLCK is selected Position */ +#define PMC_PCK_CSS_MAIN_CLK (PMC_PCK_CSS_MAIN_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MAINCK is selected Position */ +#define PMC_PCK_CSS_PLLA_CLK (PMC_PCK_CSS_PLLA_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) PLLACK is selected Position */ +#define PMC_PCK_CSS_UPLL_CLK (PMC_PCK_CSS_UPLL_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) UPLLCKDIV is selected Position */ +#define PMC_PCK_CSS_MCK (PMC_PCK_CSS_MCK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MCK is selected Position */ +#define PMC_PCK_PRES_Pos 4 /**< (PMC_PCK) Programmable Clock Prescaler Position */ +#define PMC_PCK_PRES_Msk (_U_(0xFF) << PMC_PCK_PRES_Pos) /**< (PMC_PCK) Programmable Clock Prescaler Mask */ +#define PMC_PCK_PRES(value) (PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)) +#define PMC_PCK_MASK _U_(0xFF7) /**< \deprecated (PMC_PCK) Register MASK (Use PMC_PCK_Msk instead) */ +#define PMC_PCK_Msk _U_(0xFF7) /**< (PMC_PCK) Register Mask */ + + +/* -------- PMC_IER : (PMC Offset: 0x60) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Enable */ + uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Enable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Enable */ + uint32_t :2; /**< bit: 4..5 Reserved */ + uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Enable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Enable */ + uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Enable */ + uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Enable */ + uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Enable */ + uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Enable */ + uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Enable */ + uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Enable */ + uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Enable */ + uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Enable */ + uint32_t MOSCRCS:1; /**< bit: 17 Main RC Oscillator Status Interrupt Enable */ + uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Enable */ + uint32_t :2; /**< bit: 19..20 Reserved */ + uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Enable */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Enable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_IER_OFFSET (0x60) /**< (PMC_IER) Interrupt Enable Register Offset */ + +#define PMC_IER_MOSCXTS_Pos 0 /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCXTS_Msk (_U_(0x1) << PMC_IER_MOSCXTS_Pos) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCXTS PMC_IER_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCXTS_Msk instead */ +#define PMC_IER_LOCKA_Pos 1 /**< (PMC_IER) PLLA Lock Interrupt Enable Position */ +#define PMC_IER_LOCKA_Msk (_U_(0x1) << PMC_IER_LOCKA_Pos) /**< (PMC_IER) PLLA Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKA PMC_IER_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_LOCKA_Msk instead */ +#define PMC_IER_MCKRDY_Pos 3 /**< (PMC_IER) Master Clock Ready Interrupt Enable Position */ +#define PMC_IER_MCKRDY_Msk (_U_(0x1) << PMC_IER_MCKRDY_Pos) /**< (PMC_IER) Master Clock Ready Interrupt Enable Mask */ +#define PMC_IER_MCKRDY PMC_IER_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MCKRDY_Msk instead */ +#define PMC_IER_LOCKU_Pos 6 /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Position */ +#define PMC_IER_LOCKU_Msk (_U_(0x1) << PMC_IER_LOCKU_Pos) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKU PMC_IER_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_LOCKU_Msk instead */ +#define PMC_IER_PCKRDY0_Pos 8 /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Position */ +#define PMC_IER_PCKRDY0_Msk (_U_(0x1) << PMC_IER_PCKRDY0_Pos) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY0 PMC_IER_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY0_Msk instead */ +#define PMC_IER_PCKRDY1_Pos 9 /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Position */ +#define PMC_IER_PCKRDY1_Msk (_U_(0x1) << PMC_IER_PCKRDY1_Pos) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY1 PMC_IER_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY1_Msk instead */ +#define PMC_IER_PCKRDY2_Pos 10 /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Position */ +#define PMC_IER_PCKRDY2_Msk (_U_(0x1) << PMC_IER_PCKRDY2_Pos) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY2 PMC_IER_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY2_Msk instead */ +#define PMC_IER_PCKRDY3_Pos 11 /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Position */ +#define PMC_IER_PCKRDY3_Msk (_U_(0x1) << PMC_IER_PCKRDY3_Pos) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY3 PMC_IER_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY3_Msk instead */ +#define PMC_IER_PCKRDY4_Pos 12 /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Position */ +#define PMC_IER_PCKRDY4_Msk (_U_(0x1) << PMC_IER_PCKRDY4_Pos) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY4 PMC_IER_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY4_Msk instead */ +#define PMC_IER_PCKRDY5_Pos 13 /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Position */ +#define PMC_IER_PCKRDY5_Msk (_U_(0x1) << PMC_IER_PCKRDY5_Pos) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY5 PMC_IER_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY5_Msk instead */ +#define PMC_IER_PCKRDY6_Pos 14 /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Position */ +#define PMC_IER_PCKRDY6_Msk (_U_(0x1) << PMC_IER_PCKRDY6_Pos) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY6 PMC_IER_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY6_Msk instead */ +#define PMC_IER_PCKRDY7_Pos 15 /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Position */ +#define PMC_IER_PCKRDY7_Msk (_U_(0x1) << PMC_IER_PCKRDY7_Pos) /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY7 PMC_IER_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_PCKRDY7_Msk instead */ +#define PMC_IER_MOSCSELS_Pos 16 /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Position */ +#define PMC_IER_MOSCSELS_Msk (_U_(0x1) << PMC_IER_MOSCSELS_Pos) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Mask */ +#define PMC_IER_MOSCSELS PMC_IER_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCSELS_Msk instead */ +#define PMC_IER_MOSCRCS_Pos 17 /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCRCS_Msk (_U_(0x1) << PMC_IER_MOSCRCS_Pos) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCRCS PMC_IER_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_MOSCRCS_Msk instead */ +#define PMC_IER_CFDEV_Pos 18 /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Position */ +#define PMC_IER_CFDEV_Msk (_U_(0x1) << PMC_IER_CFDEV_Pos) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Mask */ +#define PMC_IER_CFDEV PMC_IER_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_CFDEV_Msk instead */ +#define PMC_IER_XT32KERR_Pos 21 /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Position */ +#define PMC_IER_XT32KERR_Msk (_U_(0x1) << PMC_IER_XT32KERR_Pos) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Mask */ +#define PMC_IER_XT32KERR PMC_IER_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IER_XT32KERR_Msk instead */ +#define PMC_IER_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IER) Register MASK (Use PMC_IER_Msk instead) */ +#define PMC_IER_Msk _U_(0x27FF4B) /**< (PMC_IER) Register Mask */ + +#define PMC_IER_PCKRDY_Pos 8 /**< (PMC_IER Position) Programmable Clock Ready x Interrupt Enable */ +#define PMC_IER_PCKRDY_Msk (_U_(0xFF) << PMC_IER_PCKRDY_Pos) /**< (PMC_IER Mask) PCKRDY */ +#define PMC_IER_PCKRDY(value) (PMC_IER_PCKRDY_Msk & ((value) << PMC_IER_PCKRDY_Pos)) + +/* -------- PMC_IDR : (PMC Offset: 0x64) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Disable */ + uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Disable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Disable */ + uint32_t :2; /**< bit: 4..5 Reserved */ + uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Disable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Disable */ + uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Disable */ + uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Disable */ + uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Disable */ + uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Disable */ + uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Disable */ + uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Disable */ + uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Disable */ + uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Disable */ + uint32_t MOSCRCS:1; /**< bit: 17 Main RC Status Interrupt Disable */ + uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Disable */ + uint32_t :2; /**< bit: 19..20 Reserved */ + uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Disable */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Disable */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_IDR_OFFSET (0x64) /**< (PMC_IDR) Interrupt Disable Register Offset */ + +#define PMC_IDR_MOSCXTS_Pos 0 /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Position */ +#define PMC_IDR_MOSCXTS_Msk (_U_(0x1) << PMC_IDR_MOSCXTS_Pos) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCXTS PMC_IDR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCXTS_Msk instead */ +#define PMC_IDR_LOCKA_Pos 1 /**< (PMC_IDR) PLLA Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKA_Msk (_U_(0x1) << PMC_IDR_LOCKA_Pos) /**< (PMC_IDR) PLLA Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKA PMC_IDR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_LOCKA_Msk instead */ +#define PMC_IDR_MCKRDY_Pos 3 /**< (PMC_IDR) Master Clock Ready Interrupt Disable Position */ +#define PMC_IDR_MCKRDY_Msk (_U_(0x1) << PMC_IDR_MCKRDY_Pos) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Mask */ +#define PMC_IDR_MCKRDY PMC_IDR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MCKRDY_Msk instead */ +#define PMC_IDR_LOCKU_Pos 6 /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKU_Msk (_U_(0x1) << PMC_IDR_LOCKU_Pos) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKU PMC_IDR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_LOCKU_Msk instead */ +#define PMC_IDR_PCKRDY0_Pos 8 /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY0_Msk (_U_(0x1) << PMC_IDR_PCKRDY0_Pos) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY0 PMC_IDR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY0_Msk instead */ +#define PMC_IDR_PCKRDY1_Pos 9 /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY1_Msk (_U_(0x1) << PMC_IDR_PCKRDY1_Pos) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY1 PMC_IDR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY1_Msk instead */ +#define PMC_IDR_PCKRDY2_Pos 10 /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY2_Msk (_U_(0x1) << PMC_IDR_PCKRDY2_Pos) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY2 PMC_IDR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY2_Msk instead */ +#define PMC_IDR_PCKRDY3_Pos 11 /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY3_Msk (_U_(0x1) << PMC_IDR_PCKRDY3_Pos) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY3 PMC_IDR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY3_Msk instead */ +#define PMC_IDR_PCKRDY4_Pos 12 /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY4_Msk (_U_(0x1) << PMC_IDR_PCKRDY4_Pos) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY4 PMC_IDR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY4_Msk instead */ +#define PMC_IDR_PCKRDY5_Pos 13 /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY5_Msk (_U_(0x1) << PMC_IDR_PCKRDY5_Pos) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY5 PMC_IDR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY5_Msk instead */ +#define PMC_IDR_PCKRDY6_Pos 14 /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY6_Msk (_U_(0x1) << PMC_IDR_PCKRDY6_Pos) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY6 PMC_IDR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY6_Msk instead */ +#define PMC_IDR_PCKRDY7_Pos 15 /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY7_Msk (_U_(0x1) << PMC_IDR_PCKRDY7_Pos) /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY7 PMC_IDR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_PCKRDY7_Msk instead */ +#define PMC_IDR_MOSCSELS_Pos 16 /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Position */ +#define PMC_IDR_MOSCSELS_Msk (_U_(0x1) << PMC_IDR_MOSCSELS_Pos) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCSELS PMC_IDR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCSELS_Msk instead */ +#define PMC_IDR_MOSCRCS_Pos 17 /**< (PMC_IDR) Main RC Status Interrupt Disable Position */ +#define PMC_IDR_MOSCRCS_Msk (_U_(0x1) << PMC_IDR_MOSCRCS_Pos) /**< (PMC_IDR) Main RC Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCRCS PMC_IDR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_MOSCRCS_Msk instead */ +#define PMC_IDR_CFDEV_Pos 18 /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Position */ +#define PMC_IDR_CFDEV_Msk (_U_(0x1) << PMC_IDR_CFDEV_Pos) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Mask */ +#define PMC_IDR_CFDEV PMC_IDR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_CFDEV_Msk instead */ +#define PMC_IDR_XT32KERR_Pos 21 /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Position */ +#define PMC_IDR_XT32KERR_Msk (_U_(0x1) << PMC_IDR_XT32KERR_Pos) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Mask */ +#define PMC_IDR_XT32KERR PMC_IDR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IDR_XT32KERR_Msk instead */ +#define PMC_IDR_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IDR) Register MASK (Use PMC_IDR_Msk instead) */ +#define PMC_IDR_Msk _U_(0x27FF4B) /**< (PMC_IDR) Register Mask */ + +#define PMC_IDR_PCKRDY_Pos 8 /**< (PMC_IDR Position) Programmable Clock Ready x Interrupt Disable */ +#define PMC_IDR_PCKRDY_Msk (_U_(0xFF) << PMC_IDR_PCKRDY_Pos) /**< (PMC_IDR Mask) PCKRDY */ +#define PMC_IDR_PCKRDY(value) (PMC_IDR_PCKRDY_Msk & ((value) << PMC_IDR_PCKRDY_Pos)) + +/* -------- PMC_SR : (PMC Offset: 0x68) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status */ + uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Status */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t MCKRDY:1; /**< bit: 3 Master Clock Status */ + uint32_t :2; /**< bit: 4..5 Reserved */ + uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Status */ + uint32_t OSCSELS:1; /**< bit: 7 Slow Clock Source Oscillator Selection */ + uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Status */ + uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Status */ + uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Status */ + uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Status */ + uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Status */ + uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Status */ + uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Status */ + uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Status */ + uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status */ + uint32_t MOSCRCS:1; /**< bit: 17 Main RC Oscillator Status */ + uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event */ + uint32_t CFDS:1; /**< bit: 19 Clock Failure Detector Status */ + uint32_t FOS:1; /**< bit: 20 Clock Failure Detector Fault Output Status */ + uint32_t XT32KERR:1; /**< bit: 21 Slow Crystal Oscillator Error */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Status */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SR_OFFSET (0x68) /**< (PMC_SR) Status Register Offset */ + +#define PMC_SR_MOSCXTS_Pos 0 /**< (PMC_SR) Main Crystal Oscillator Status Position */ +#define PMC_SR_MOSCXTS_Msk (_U_(0x1) << PMC_SR_MOSCXTS_Pos) /**< (PMC_SR) Main Crystal Oscillator Status Mask */ +#define PMC_SR_MOSCXTS PMC_SR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCXTS_Msk instead */ +#define PMC_SR_LOCKA_Pos 1 /**< (PMC_SR) PLLA Lock Status Position */ +#define PMC_SR_LOCKA_Msk (_U_(0x1) << PMC_SR_LOCKA_Pos) /**< (PMC_SR) PLLA Lock Status Mask */ +#define PMC_SR_LOCKA PMC_SR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_LOCKA_Msk instead */ +#define PMC_SR_MCKRDY_Pos 3 /**< (PMC_SR) Master Clock Status Position */ +#define PMC_SR_MCKRDY_Msk (_U_(0x1) << PMC_SR_MCKRDY_Pos) /**< (PMC_SR) Master Clock Status Mask */ +#define PMC_SR_MCKRDY PMC_SR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MCKRDY_Msk instead */ +#define PMC_SR_LOCKU_Pos 6 /**< (PMC_SR) UTMI PLL Lock Status Position */ +#define PMC_SR_LOCKU_Msk (_U_(0x1) << PMC_SR_LOCKU_Pos) /**< (PMC_SR) UTMI PLL Lock Status Mask */ +#define PMC_SR_LOCKU PMC_SR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_LOCKU_Msk instead */ +#define PMC_SR_OSCSELS_Pos 7 /**< (PMC_SR) Slow Clock Source Oscillator Selection Position */ +#define PMC_SR_OSCSELS_Msk (_U_(0x1) << PMC_SR_OSCSELS_Pos) /**< (PMC_SR) Slow Clock Source Oscillator Selection Mask */ +#define PMC_SR_OSCSELS PMC_SR_OSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_OSCSELS_Msk instead */ +#define PMC_SR_PCKRDY0_Pos 8 /**< (PMC_SR) Programmable Clock Ready 0 Status Position */ +#define PMC_SR_PCKRDY0_Msk (_U_(0x1) << PMC_SR_PCKRDY0_Pos) /**< (PMC_SR) Programmable Clock Ready 0 Status Mask */ +#define PMC_SR_PCKRDY0 PMC_SR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY0_Msk instead */ +#define PMC_SR_PCKRDY1_Pos 9 /**< (PMC_SR) Programmable Clock Ready 1 Status Position */ +#define PMC_SR_PCKRDY1_Msk (_U_(0x1) << PMC_SR_PCKRDY1_Pos) /**< (PMC_SR) Programmable Clock Ready 1 Status Mask */ +#define PMC_SR_PCKRDY1 PMC_SR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY1_Msk instead */ +#define PMC_SR_PCKRDY2_Pos 10 /**< (PMC_SR) Programmable Clock Ready 2 Status Position */ +#define PMC_SR_PCKRDY2_Msk (_U_(0x1) << PMC_SR_PCKRDY2_Pos) /**< (PMC_SR) Programmable Clock Ready 2 Status Mask */ +#define PMC_SR_PCKRDY2 PMC_SR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY2_Msk instead */ +#define PMC_SR_PCKRDY3_Pos 11 /**< (PMC_SR) Programmable Clock Ready 3 Status Position */ +#define PMC_SR_PCKRDY3_Msk (_U_(0x1) << PMC_SR_PCKRDY3_Pos) /**< (PMC_SR) Programmable Clock Ready 3 Status Mask */ +#define PMC_SR_PCKRDY3 PMC_SR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY3_Msk instead */ +#define PMC_SR_PCKRDY4_Pos 12 /**< (PMC_SR) Programmable Clock Ready 4 Status Position */ +#define PMC_SR_PCKRDY4_Msk (_U_(0x1) << PMC_SR_PCKRDY4_Pos) /**< (PMC_SR) Programmable Clock Ready 4 Status Mask */ +#define PMC_SR_PCKRDY4 PMC_SR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY4_Msk instead */ +#define PMC_SR_PCKRDY5_Pos 13 /**< (PMC_SR) Programmable Clock Ready 5 Status Position */ +#define PMC_SR_PCKRDY5_Msk (_U_(0x1) << PMC_SR_PCKRDY5_Pos) /**< (PMC_SR) Programmable Clock Ready 5 Status Mask */ +#define PMC_SR_PCKRDY5 PMC_SR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY5_Msk instead */ +#define PMC_SR_PCKRDY6_Pos 14 /**< (PMC_SR) Programmable Clock Ready 6 Status Position */ +#define PMC_SR_PCKRDY6_Msk (_U_(0x1) << PMC_SR_PCKRDY6_Pos) /**< (PMC_SR) Programmable Clock Ready 6 Status Mask */ +#define PMC_SR_PCKRDY6 PMC_SR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY6_Msk instead */ +#define PMC_SR_PCKRDY7_Pos 15 /**< (PMC_SR) Programmable Clock Ready 7 Status Position */ +#define PMC_SR_PCKRDY7_Msk (_U_(0x1) << PMC_SR_PCKRDY7_Pos) /**< (PMC_SR) Programmable Clock Ready 7 Status Mask */ +#define PMC_SR_PCKRDY7 PMC_SR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_PCKRDY7_Msk instead */ +#define PMC_SR_MOSCSELS_Pos 16 /**< (PMC_SR) Main Clock Source Oscillator Selection Status Position */ +#define PMC_SR_MOSCSELS_Msk (_U_(0x1) << PMC_SR_MOSCSELS_Pos) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Mask */ +#define PMC_SR_MOSCSELS PMC_SR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCSELS_Msk instead */ +#define PMC_SR_MOSCRCS_Pos 17 /**< (PMC_SR) Main RC Oscillator Status Position */ +#define PMC_SR_MOSCRCS_Msk (_U_(0x1) << PMC_SR_MOSCRCS_Pos) /**< (PMC_SR) Main RC Oscillator Status Mask */ +#define PMC_SR_MOSCRCS PMC_SR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_MOSCRCS_Msk instead */ +#define PMC_SR_CFDEV_Pos 18 /**< (PMC_SR) Clock Failure Detector Event Position */ +#define PMC_SR_CFDEV_Msk (_U_(0x1) << PMC_SR_CFDEV_Pos) /**< (PMC_SR) Clock Failure Detector Event Mask */ +#define PMC_SR_CFDEV PMC_SR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_CFDEV_Msk instead */ +#define PMC_SR_CFDS_Pos 19 /**< (PMC_SR) Clock Failure Detector Status Position */ +#define PMC_SR_CFDS_Msk (_U_(0x1) << PMC_SR_CFDS_Pos) /**< (PMC_SR) Clock Failure Detector Status Mask */ +#define PMC_SR_CFDS PMC_SR_CFDS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_CFDS_Msk instead */ +#define PMC_SR_FOS_Pos 20 /**< (PMC_SR) Clock Failure Detector Fault Output Status Position */ +#define PMC_SR_FOS_Msk (_U_(0x1) << PMC_SR_FOS_Pos) /**< (PMC_SR) Clock Failure Detector Fault Output Status Mask */ +#define PMC_SR_FOS PMC_SR_FOS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_FOS_Msk instead */ +#define PMC_SR_XT32KERR_Pos 21 /**< (PMC_SR) Slow Crystal Oscillator Error Position */ +#define PMC_SR_XT32KERR_Msk (_U_(0x1) << PMC_SR_XT32KERR_Pos) /**< (PMC_SR) Slow Crystal Oscillator Error Mask */ +#define PMC_SR_XT32KERR PMC_SR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SR_XT32KERR_Msk instead */ +#define PMC_SR_MASK _U_(0x3FFFCB) /**< \deprecated (PMC_SR) Register MASK (Use PMC_SR_Msk instead) */ +#define PMC_SR_Msk _U_(0x3FFFCB) /**< (PMC_SR) Register Mask */ + +#define PMC_SR_PCKRDY_Pos 8 /**< (PMC_SR Position) Programmable Clock Ready x Status */ +#define PMC_SR_PCKRDY_Msk (_U_(0xFF) << PMC_SR_PCKRDY_Pos) /**< (PMC_SR Mask) PCKRDY */ +#define PMC_SR_PCKRDY(value) (PMC_SR_PCKRDY_Msk & ((value) << PMC_SR_PCKRDY_Pos)) + +/* -------- PMC_IMR : (PMC Offset: 0x6c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MOSCXTS:1; /**< bit: 0 Main Crystal Oscillator Status Interrupt Mask */ + uint32_t LOCKA:1; /**< bit: 1 PLLA Lock Interrupt Mask */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t MCKRDY:1; /**< bit: 3 Master Clock Ready Interrupt Mask */ + uint32_t :2; /**< bit: 4..5 Reserved */ + uint32_t LOCKU:1; /**< bit: 6 UTMI PLL Lock Interrupt Mask */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PCKRDY0:1; /**< bit: 8 Programmable Clock Ready 0 Interrupt Mask */ + uint32_t PCKRDY1:1; /**< bit: 9 Programmable Clock Ready 1 Interrupt Mask */ + uint32_t PCKRDY2:1; /**< bit: 10 Programmable Clock Ready 2 Interrupt Mask */ + uint32_t PCKRDY3:1; /**< bit: 11 Programmable Clock Ready 3 Interrupt Mask */ + uint32_t PCKRDY4:1; /**< bit: 12 Programmable Clock Ready 4 Interrupt Mask */ + uint32_t PCKRDY5:1; /**< bit: 13 Programmable Clock Ready 5 Interrupt Mask */ + uint32_t PCKRDY6:1; /**< bit: 14 Programmable Clock Ready 6 Interrupt Mask */ + uint32_t PCKRDY7:1; /**< bit: 15 Programmable Clock Ready 7 Interrupt Mask */ + uint32_t MOSCSELS:1; /**< bit: 16 Main Clock Source Oscillator Selection Status Interrupt Mask */ + uint32_t MOSCRCS:1; /**< bit: 17 Main RC Status Interrupt Mask */ + uint32_t CFDEV:1; /**< bit: 18 Clock Failure Detector Event Interrupt Mask */ + uint32_t :2; /**< bit: 19..20 Reserved */ + uint32_t XT32KERR:1; /**< bit: 21 32.768 kHz Crystal Oscillator Error Interrupt Mask */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PCKRDY:8; /**< bit: 8..15 Programmable Clock Ready x Interrupt Mask */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_IMR_OFFSET (0x6C) /**< (PMC_IMR) Interrupt Mask Register Offset */ + +#define PMC_IMR_MOSCXTS_Pos 0 /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Position */ +#define PMC_IMR_MOSCXTS_Msk (_U_(0x1) << PMC_IMR_MOSCXTS_Pos) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCXTS PMC_IMR_MOSCXTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCXTS_Msk instead */ +#define PMC_IMR_LOCKA_Pos 1 /**< (PMC_IMR) PLLA Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKA_Msk (_U_(0x1) << PMC_IMR_LOCKA_Pos) /**< (PMC_IMR) PLLA Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKA PMC_IMR_LOCKA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_LOCKA_Msk instead */ +#define PMC_IMR_MCKRDY_Pos 3 /**< (PMC_IMR) Master Clock Ready Interrupt Mask Position */ +#define PMC_IMR_MCKRDY_Msk (_U_(0x1) << PMC_IMR_MCKRDY_Pos) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Mask */ +#define PMC_IMR_MCKRDY PMC_IMR_MCKRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MCKRDY_Msk instead */ +#define PMC_IMR_LOCKU_Pos 6 /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKU_Msk (_U_(0x1) << PMC_IMR_LOCKU_Pos) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKU PMC_IMR_LOCKU_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_LOCKU_Msk instead */ +#define PMC_IMR_PCKRDY0_Pos 8 /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY0_Msk (_U_(0x1) << PMC_IMR_PCKRDY0_Pos) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY0 PMC_IMR_PCKRDY0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY0_Msk instead */ +#define PMC_IMR_PCKRDY1_Pos 9 /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY1_Msk (_U_(0x1) << PMC_IMR_PCKRDY1_Pos) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY1 PMC_IMR_PCKRDY1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY1_Msk instead */ +#define PMC_IMR_PCKRDY2_Pos 10 /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY2_Msk (_U_(0x1) << PMC_IMR_PCKRDY2_Pos) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY2 PMC_IMR_PCKRDY2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY2_Msk instead */ +#define PMC_IMR_PCKRDY3_Pos 11 /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY3_Msk (_U_(0x1) << PMC_IMR_PCKRDY3_Pos) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY3 PMC_IMR_PCKRDY3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY3_Msk instead */ +#define PMC_IMR_PCKRDY4_Pos 12 /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY4_Msk (_U_(0x1) << PMC_IMR_PCKRDY4_Pos) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY4 PMC_IMR_PCKRDY4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY4_Msk instead */ +#define PMC_IMR_PCKRDY5_Pos 13 /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY5_Msk (_U_(0x1) << PMC_IMR_PCKRDY5_Pos) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY5 PMC_IMR_PCKRDY5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY5_Msk instead */ +#define PMC_IMR_PCKRDY6_Pos 14 /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY6_Msk (_U_(0x1) << PMC_IMR_PCKRDY6_Pos) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY6 PMC_IMR_PCKRDY6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY6_Msk instead */ +#define PMC_IMR_PCKRDY7_Pos 15 /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY7_Msk (_U_(0x1) << PMC_IMR_PCKRDY7_Pos) /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY7 PMC_IMR_PCKRDY7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_PCKRDY7_Msk instead */ +#define PMC_IMR_MOSCSELS_Pos 16 /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Position */ +#define PMC_IMR_MOSCSELS_Msk (_U_(0x1) << PMC_IMR_MOSCSELS_Pos) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCSELS PMC_IMR_MOSCSELS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCSELS_Msk instead */ +#define PMC_IMR_MOSCRCS_Pos 17 /**< (PMC_IMR) Main RC Status Interrupt Mask Position */ +#define PMC_IMR_MOSCRCS_Msk (_U_(0x1) << PMC_IMR_MOSCRCS_Pos) /**< (PMC_IMR) Main RC Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCRCS PMC_IMR_MOSCRCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_MOSCRCS_Msk instead */ +#define PMC_IMR_CFDEV_Pos 18 /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Position */ +#define PMC_IMR_CFDEV_Msk (_U_(0x1) << PMC_IMR_CFDEV_Pos) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Mask */ +#define PMC_IMR_CFDEV PMC_IMR_CFDEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_CFDEV_Msk instead */ +#define PMC_IMR_XT32KERR_Pos 21 /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Position */ +#define PMC_IMR_XT32KERR_Msk (_U_(0x1) << PMC_IMR_XT32KERR_Pos) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Mask */ +#define PMC_IMR_XT32KERR PMC_IMR_XT32KERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_IMR_XT32KERR_Msk instead */ +#define PMC_IMR_MASK _U_(0x27FF4B) /**< \deprecated (PMC_IMR) Register MASK (Use PMC_IMR_Msk instead) */ +#define PMC_IMR_Msk _U_(0x27FF4B) /**< (PMC_IMR) Register Mask */ + +#define PMC_IMR_PCKRDY_Pos 8 /**< (PMC_IMR Position) Programmable Clock Ready x Interrupt Mask */ +#define PMC_IMR_PCKRDY_Msk (_U_(0xFF) << PMC_IMR_PCKRDY_Pos) /**< (PMC_IMR Mask) PCKRDY */ +#define PMC_IMR_PCKRDY(value) (PMC_IMR_PCKRDY_Msk & ((value) << PMC_IMR_PCKRDY_Pos)) + +/* -------- PMC_FSMR : (PMC Offset: 0x70) (R/W 32) Fast Startup Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FSTT0:1; /**< bit: 0 Fast Startup Input Enable 0 */ + uint32_t FSTT1:1; /**< bit: 1 Fast Startup Input Enable 1 */ + uint32_t FSTT2:1; /**< bit: 2 Fast Startup Input Enable 2 */ + uint32_t FSTT3:1; /**< bit: 3 Fast Startup Input Enable 3 */ + uint32_t FSTT4:1; /**< bit: 4 Fast Startup Input Enable 4 */ + uint32_t FSTT5:1; /**< bit: 5 Fast Startup Input Enable 5 */ + uint32_t FSTT6:1; /**< bit: 6 Fast Startup Input Enable 6 */ + uint32_t FSTT7:1; /**< bit: 7 Fast Startup Input Enable 7 */ + uint32_t FSTT8:1; /**< bit: 8 Fast Startup Input Enable 8 */ + uint32_t FSTT9:1; /**< bit: 9 Fast Startup Input Enable 9 */ + uint32_t FSTT10:1; /**< bit: 10 Fast Startup Input Enable 10 */ + uint32_t FSTT11:1; /**< bit: 11 Fast Startup Input Enable 11 */ + uint32_t FSTT12:1; /**< bit: 12 Fast Startup Input Enable 12 */ + uint32_t FSTT13:1; /**< bit: 13 Fast Startup Input Enable 13 */ + uint32_t FSTT14:1; /**< bit: 14 Fast Startup Input Enable 14 */ + uint32_t FSTT15:1; /**< bit: 15 Fast Startup Input Enable 15 */ + uint32_t RTTAL:1; /**< bit: 16 RTT Alarm Enable */ + uint32_t RTCAL:1; /**< bit: 17 RTC Alarm Enable */ + uint32_t USBAL:1; /**< bit: 18 USB Alarm Enable */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t LPM:1; /**< bit: 20 Low-power Mode */ + uint32_t FLPM:2; /**< bit: 21..22 Flash Low-power Mode */ + uint32_t FFLPM:1; /**< bit: 23 Force Flash Low-power Mode */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t FSTT:16; /**< bit: 0..15 Fast Startup Input Enable x */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_FSMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_FSMR_OFFSET (0x70) /**< (PMC_FSMR) Fast Startup Mode Register Offset */ + +#define PMC_FSMR_FSTT0_Pos 0 /**< (PMC_FSMR) Fast Startup Input Enable 0 Position */ +#define PMC_FSMR_FSTT0_Msk (_U_(0x1) << PMC_FSMR_FSTT0_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 0 Mask */ +#define PMC_FSMR_FSTT0 PMC_FSMR_FSTT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT0_Msk instead */ +#define PMC_FSMR_FSTT1_Pos 1 /**< (PMC_FSMR) Fast Startup Input Enable 1 Position */ +#define PMC_FSMR_FSTT1_Msk (_U_(0x1) << PMC_FSMR_FSTT1_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 1 Mask */ +#define PMC_FSMR_FSTT1 PMC_FSMR_FSTT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT1_Msk instead */ +#define PMC_FSMR_FSTT2_Pos 2 /**< (PMC_FSMR) Fast Startup Input Enable 2 Position */ +#define PMC_FSMR_FSTT2_Msk (_U_(0x1) << PMC_FSMR_FSTT2_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 2 Mask */ +#define PMC_FSMR_FSTT2 PMC_FSMR_FSTT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT2_Msk instead */ +#define PMC_FSMR_FSTT3_Pos 3 /**< (PMC_FSMR) Fast Startup Input Enable 3 Position */ +#define PMC_FSMR_FSTT3_Msk (_U_(0x1) << PMC_FSMR_FSTT3_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 3 Mask */ +#define PMC_FSMR_FSTT3 PMC_FSMR_FSTT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT3_Msk instead */ +#define PMC_FSMR_FSTT4_Pos 4 /**< (PMC_FSMR) Fast Startup Input Enable 4 Position */ +#define PMC_FSMR_FSTT4_Msk (_U_(0x1) << PMC_FSMR_FSTT4_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 4 Mask */ +#define PMC_FSMR_FSTT4 PMC_FSMR_FSTT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT4_Msk instead */ +#define PMC_FSMR_FSTT5_Pos 5 /**< (PMC_FSMR) Fast Startup Input Enable 5 Position */ +#define PMC_FSMR_FSTT5_Msk (_U_(0x1) << PMC_FSMR_FSTT5_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 5 Mask */ +#define PMC_FSMR_FSTT5 PMC_FSMR_FSTT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT5_Msk instead */ +#define PMC_FSMR_FSTT6_Pos 6 /**< (PMC_FSMR) Fast Startup Input Enable 6 Position */ +#define PMC_FSMR_FSTT6_Msk (_U_(0x1) << PMC_FSMR_FSTT6_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 6 Mask */ +#define PMC_FSMR_FSTT6 PMC_FSMR_FSTT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT6_Msk instead */ +#define PMC_FSMR_FSTT7_Pos 7 /**< (PMC_FSMR) Fast Startup Input Enable 7 Position */ +#define PMC_FSMR_FSTT7_Msk (_U_(0x1) << PMC_FSMR_FSTT7_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 7 Mask */ +#define PMC_FSMR_FSTT7 PMC_FSMR_FSTT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT7_Msk instead */ +#define PMC_FSMR_FSTT8_Pos 8 /**< (PMC_FSMR) Fast Startup Input Enable 8 Position */ +#define PMC_FSMR_FSTT8_Msk (_U_(0x1) << PMC_FSMR_FSTT8_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 8 Mask */ +#define PMC_FSMR_FSTT8 PMC_FSMR_FSTT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT8_Msk instead */ +#define PMC_FSMR_FSTT9_Pos 9 /**< (PMC_FSMR) Fast Startup Input Enable 9 Position */ +#define PMC_FSMR_FSTT9_Msk (_U_(0x1) << PMC_FSMR_FSTT9_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 9 Mask */ +#define PMC_FSMR_FSTT9 PMC_FSMR_FSTT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT9_Msk instead */ +#define PMC_FSMR_FSTT10_Pos 10 /**< (PMC_FSMR) Fast Startup Input Enable 10 Position */ +#define PMC_FSMR_FSTT10_Msk (_U_(0x1) << PMC_FSMR_FSTT10_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 10 Mask */ +#define PMC_FSMR_FSTT10 PMC_FSMR_FSTT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT10_Msk instead */ +#define PMC_FSMR_FSTT11_Pos 11 /**< (PMC_FSMR) Fast Startup Input Enable 11 Position */ +#define PMC_FSMR_FSTT11_Msk (_U_(0x1) << PMC_FSMR_FSTT11_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 11 Mask */ +#define PMC_FSMR_FSTT11 PMC_FSMR_FSTT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT11_Msk instead */ +#define PMC_FSMR_FSTT12_Pos 12 /**< (PMC_FSMR) Fast Startup Input Enable 12 Position */ +#define PMC_FSMR_FSTT12_Msk (_U_(0x1) << PMC_FSMR_FSTT12_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 12 Mask */ +#define PMC_FSMR_FSTT12 PMC_FSMR_FSTT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT12_Msk instead */ +#define PMC_FSMR_FSTT13_Pos 13 /**< (PMC_FSMR) Fast Startup Input Enable 13 Position */ +#define PMC_FSMR_FSTT13_Msk (_U_(0x1) << PMC_FSMR_FSTT13_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 13 Mask */ +#define PMC_FSMR_FSTT13 PMC_FSMR_FSTT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT13_Msk instead */ +#define PMC_FSMR_FSTT14_Pos 14 /**< (PMC_FSMR) Fast Startup Input Enable 14 Position */ +#define PMC_FSMR_FSTT14_Msk (_U_(0x1) << PMC_FSMR_FSTT14_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 14 Mask */ +#define PMC_FSMR_FSTT14 PMC_FSMR_FSTT14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT14_Msk instead */ +#define PMC_FSMR_FSTT15_Pos 15 /**< (PMC_FSMR) Fast Startup Input Enable 15 Position */ +#define PMC_FSMR_FSTT15_Msk (_U_(0x1) << PMC_FSMR_FSTT15_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 15 Mask */ +#define PMC_FSMR_FSTT15 PMC_FSMR_FSTT15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FSTT15_Msk instead */ +#define PMC_FSMR_RTTAL_Pos 16 /**< (PMC_FSMR) RTT Alarm Enable Position */ +#define PMC_FSMR_RTTAL_Msk (_U_(0x1) << PMC_FSMR_RTTAL_Pos) /**< (PMC_FSMR) RTT Alarm Enable Mask */ +#define PMC_FSMR_RTTAL PMC_FSMR_RTTAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_RTTAL_Msk instead */ +#define PMC_FSMR_RTCAL_Pos 17 /**< (PMC_FSMR) RTC Alarm Enable Position */ +#define PMC_FSMR_RTCAL_Msk (_U_(0x1) << PMC_FSMR_RTCAL_Pos) /**< (PMC_FSMR) RTC Alarm Enable Mask */ +#define PMC_FSMR_RTCAL PMC_FSMR_RTCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_RTCAL_Msk instead */ +#define PMC_FSMR_USBAL_Pos 18 /**< (PMC_FSMR) USB Alarm Enable Position */ +#define PMC_FSMR_USBAL_Msk (_U_(0x1) << PMC_FSMR_USBAL_Pos) /**< (PMC_FSMR) USB Alarm Enable Mask */ +#define PMC_FSMR_USBAL PMC_FSMR_USBAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_USBAL_Msk instead */ +#define PMC_FSMR_LPM_Pos 20 /**< (PMC_FSMR) Low-power Mode Position */ +#define PMC_FSMR_LPM_Msk (_U_(0x1) << PMC_FSMR_LPM_Pos) /**< (PMC_FSMR) Low-power Mode Mask */ +#define PMC_FSMR_LPM PMC_FSMR_LPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_LPM_Msk instead */ +#define PMC_FSMR_FLPM_Pos 21 /**< (PMC_FSMR) Flash Low-power Mode Position */ +#define PMC_FSMR_FLPM_Msk (_U_(0x3) << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash Low-power Mode Mask */ +#define PMC_FSMR_FLPM(value) (PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)) +#define PMC_FSMR_FLPM_FLASH_STANDBY_Val _U_(0x0) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val _U_(0x1) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE_Val _U_(0x2) /**< (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FLPM_FLASH_STANDBY (PMC_FSMR_FLPM_FLASH_STANDBY_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_IDLE (PMC_FSMR_FLPM_FLASH_IDLE_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Idle mode Position */ +#define PMC_FSMR_FFLPM_Pos 23 /**< (PMC_FSMR) Force Flash Low-power Mode Position */ +#define PMC_FSMR_FFLPM_Msk (_U_(0x1) << PMC_FSMR_FFLPM_Pos) /**< (PMC_FSMR) Force Flash Low-power Mode Mask */ +#define PMC_FSMR_FFLPM PMC_FSMR_FFLPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSMR_FFLPM_Msk instead */ +#define PMC_FSMR_MASK _U_(0xF7FFFF) /**< \deprecated (PMC_FSMR) Register MASK (Use PMC_FSMR_Msk instead) */ +#define PMC_FSMR_Msk _U_(0xF7FFFF) /**< (PMC_FSMR) Register Mask */ + +#define PMC_FSMR_FSTT_Pos 0 /**< (PMC_FSMR Position) Fast Startup Input Enable x */ +#define PMC_FSMR_FSTT_Msk (_U_(0xFFFF) << PMC_FSMR_FSTT_Pos) /**< (PMC_FSMR Mask) FSTT */ +#define PMC_FSMR_FSTT(value) (PMC_FSMR_FSTT_Msk & ((value) << PMC_FSMR_FSTT_Pos)) + +/* -------- PMC_FSPR : (PMC Offset: 0x74) (R/W 32) Fast Startup Polarity Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FSTP0:1; /**< bit: 0 Fast Startup Input Polarity 0 */ + uint32_t FSTP1:1; /**< bit: 1 Fast Startup Input Polarity 1 */ + uint32_t FSTP2:1; /**< bit: 2 Fast Startup Input Polarity 2 */ + uint32_t FSTP3:1; /**< bit: 3 Fast Startup Input Polarity 3 */ + uint32_t FSTP4:1; /**< bit: 4 Fast Startup Input Polarity 4 */ + uint32_t FSTP5:1; /**< bit: 5 Fast Startup Input Polarity 5 */ + uint32_t FSTP6:1; /**< bit: 6 Fast Startup Input Polarity 6 */ + uint32_t FSTP7:1; /**< bit: 7 Fast Startup Input Polarity 7 */ + uint32_t FSTP8:1; /**< bit: 8 Fast Startup Input Polarity 8 */ + uint32_t FSTP9:1; /**< bit: 9 Fast Startup Input Polarity 9 */ + uint32_t FSTP10:1; /**< bit: 10 Fast Startup Input Polarity 10 */ + uint32_t FSTP11:1; /**< bit: 11 Fast Startup Input Polarity 11 */ + uint32_t FSTP12:1; /**< bit: 12 Fast Startup Input Polarity 12 */ + uint32_t FSTP13:1; /**< bit: 13 Fast Startup Input Polarity 13 */ + uint32_t FSTP14:1; /**< bit: 14 Fast Startup Input Polarity 14 */ + uint32_t FSTP15:1; /**< bit: 15 Fast Startup Input Polarity 15 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t FSTP:16; /**< bit: 0..15 Fast Startup Input Polarity x5 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_FSPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_FSPR_OFFSET (0x74) /**< (PMC_FSPR) Fast Startup Polarity Register Offset */ + +#define PMC_FSPR_FSTP0_Pos 0 /**< (PMC_FSPR) Fast Startup Input Polarity 0 Position */ +#define PMC_FSPR_FSTP0_Msk (_U_(0x1) << PMC_FSPR_FSTP0_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Mask */ +#define PMC_FSPR_FSTP0 PMC_FSPR_FSTP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP0_Msk instead */ +#define PMC_FSPR_FSTP1_Pos 1 /**< (PMC_FSPR) Fast Startup Input Polarity 1 Position */ +#define PMC_FSPR_FSTP1_Msk (_U_(0x1) << PMC_FSPR_FSTP1_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Mask */ +#define PMC_FSPR_FSTP1 PMC_FSPR_FSTP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP1_Msk instead */ +#define PMC_FSPR_FSTP2_Pos 2 /**< (PMC_FSPR) Fast Startup Input Polarity 2 Position */ +#define PMC_FSPR_FSTP2_Msk (_U_(0x1) << PMC_FSPR_FSTP2_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Mask */ +#define PMC_FSPR_FSTP2 PMC_FSPR_FSTP2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP2_Msk instead */ +#define PMC_FSPR_FSTP3_Pos 3 /**< (PMC_FSPR) Fast Startup Input Polarity 3 Position */ +#define PMC_FSPR_FSTP3_Msk (_U_(0x1) << PMC_FSPR_FSTP3_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Mask */ +#define PMC_FSPR_FSTP3 PMC_FSPR_FSTP3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP3_Msk instead */ +#define PMC_FSPR_FSTP4_Pos 4 /**< (PMC_FSPR) Fast Startup Input Polarity 4 Position */ +#define PMC_FSPR_FSTP4_Msk (_U_(0x1) << PMC_FSPR_FSTP4_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Mask */ +#define PMC_FSPR_FSTP4 PMC_FSPR_FSTP4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP4_Msk instead */ +#define PMC_FSPR_FSTP5_Pos 5 /**< (PMC_FSPR) Fast Startup Input Polarity 5 Position */ +#define PMC_FSPR_FSTP5_Msk (_U_(0x1) << PMC_FSPR_FSTP5_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Mask */ +#define PMC_FSPR_FSTP5 PMC_FSPR_FSTP5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP5_Msk instead */ +#define PMC_FSPR_FSTP6_Pos 6 /**< (PMC_FSPR) Fast Startup Input Polarity 6 Position */ +#define PMC_FSPR_FSTP6_Msk (_U_(0x1) << PMC_FSPR_FSTP6_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Mask */ +#define PMC_FSPR_FSTP6 PMC_FSPR_FSTP6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP6_Msk instead */ +#define PMC_FSPR_FSTP7_Pos 7 /**< (PMC_FSPR) Fast Startup Input Polarity 7 Position */ +#define PMC_FSPR_FSTP7_Msk (_U_(0x1) << PMC_FSPR_FSTP7_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Mask */ +#define PMC_FSPR_FSTP7 PMC_FSPR_FSTP7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP7_Msk instead */ +#define PMC_FSPR_FSTP8_Pos 8 /**< (PMC_FSPR) Fast Startup Input Polarity 8 Position */ +#define PMC_FSPR_FSTP8_Msk (_U_(0x1) << PMC_FSPR_FSTP8_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Mask */ +#define PMC_FSPR_FSTP8 PMC_FSPR_FSTP8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP8_Msk instead */ +#define PMC_FSPR_FSTP9_Pos 9 /**< (PMC_FSPR) Fast Startup Input Polarity 9 Position */ +#define PMC_FSPR_FSTP9_Msk (_U_(0x1) << PMC_FSPR_FSTP9_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Mask */ +#define PMC_FSPR_FSTP9 PMC_FSPR_FSTP9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP9_Msk instead */ +#define PMC_FSPR_FSTP10_Pos 10 /**< (PMC_FSPR) Fast Startup Input Polarity 10 Position */ +#define PMC_FSPR_FSTP10_Msk (_U_(0x1) << PMC_FSPR_FSTP10_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Mask */ +#define PMC_FSPR_FSTP10 PMC_FSPR_FSTP10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP10_Msk instead */ +#define PMC_FSPR_FSTP11_Pos 11 /**< (PMC_FSPR) Fast Startup Input Polarity 11 Position */ +#define PMC_FSPR_FSTP11_Msk (_U_(0x1) << PMC_FSPR_FSTP11_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Mask */ +#define PMC_FSPR_FSTP11 PMC_FSPR_FSTP11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP11_Msk instead */ +#define PMC_FSPR_FSTP12_Pos 12 /**< (PMC_FSPR) Fast Startup Input Polarity 12 Position */ +#define PMC_FSPR_FSTP12_Msk (_U_(0x1) << PMC_FSPR_FSTP12_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Mask */ +#define PMC_FSPR_FSTP12 PMC_FSPR_FSTP12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP12_Msk instead */ +#define PMC_FSPR_FSTP13_Pos 13 /**< (PMC_FSPR) Fast Startup Input Polarity 13 Position */ +#define PMC_FSPR_FSTP13_Msk (_U_(0x1) << PMC_FSPR_FSTP13_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Mask */ +#define PMC_FSPR_FSTP13 PMC_FSPR_FSTP13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP13_Msk instead */ +#define PMC_FSPR_FSTP14_Pos 14 /**< (PMC_FSPR) Fast Startup Input Polarity 14 Position */ +#define PMC_FSPR_FSTP14_Msk (_U_(0x1) << PMC_FSPR_FSTP14_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Mask */ +#define PMC_FSPR_FSTP14 PMC_FSPR_FSTP14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP14_Msk instead */ +#define PMC_FSPR_FSTP15_Pos 15 /**< (PMC_FSPR) Fast Startup Input Polarity 15 Position */ +#define PMC_FSPR_FSTP15_Msk (_U_(0x1) << PMC_FSPR_FSTP15_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Mask */ +#define PMC_FSPR_FSTP15 PMC_FSPR_FSTP15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FSPR_FSTP15_Msk instead */ +#define PMC_FSPR_MASK _U_(0xFFFF) /**< \deprecated (PMC_FSPR) Register MASK (Use PMC_FSPR_Msk instead) */ +#define PMC_FSPR_Msk _U_(0xFFFF) /**< (PMC_FSPR) Register Mask */ + +#define PMC_FSPR_FSTP_Pos 0 /**< (PMC_FSPR Position) Fast Startup Input Polarity x5 */ +#define PMC_FSPR_FSTP_Msk (_U_(0xFFFF) << PMC_FSPR_FSTP_Pos) /**< (PMC_FSPR Mask) FSTP */ +#define PMC_FSPR_FSTP(value) (PMC_FSPR_FSTP_Msk & ((value) << PMC_FSPR_FSTP_Pos)) + +/* -------- PMC_FOCR : (PMC Offset: 0x78) (/W 32) Fault Output Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FOCLR:1; /**< bit: 0 Fault Output Clear */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_FOCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_FOCR_OFFSET (0x78) /**< (PMC_FOCR) Fault Output Clear Register Offset */ + +#define PMC_FOCR_FOCLR_Pos 0 /**< (PMC_FOCR) Fault Output Clear Position */ +#define PMC_FOCR_FOCLR_Msk (_U_(0x1) << PMC_FOCR_FOCLR_Pos) /**< (PMC_FOCR) Fault Output Clear Mask */ +#define PMC_FOCR_FOCLR PMC_FOCR_FOCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_FOCR_FOCLR_Msk instead */ +#define PMC_FOCR_MASK _U_(0x01) /**< \deprecated (PMC_FOCR) Register MASK (Use PMC_FOCR_Msk instead) */ +#define PMC_FOCR_Msk _U_(0x01) /**< (PMC_FOCR) Register Mask */ + + +/* -------- PMC_WPMR : (PMC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_WPMR_OFFSET (0xE4) /**< (PMC_WPMR) Write Protection Mode Register Offset */ + +#define PMC_WPMR_WPEN_Pos 0 /**< (PMC_WPMR) Write Protection Enable Position */ +#define PMC_WPMR_WPEN_Msk (_U_(0x1) << PMC_WPMR_WPEN_Pos) /**< (PMC_WPMR) Write Protection Enable Mask */ +#define PMC_WPMR_WPEN PMC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_WPMR_WPEN_Msk instead */ +#define PMC_WPMR_WPKEY_Pos 8 /**< (PMC_WPMR) Write Protection Key Position */ +#define PMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Write Protection Key Mask */ +#define PMC_WPMR_WPKEY(value) (PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)) +#define PMC_WPMR_WPKEY_PASSWD_Val _U_(0x504D43) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define PMC_WPMR_WPKEY_PASSWD (PMC_WPMR_WPKEY_PASSWD_Val << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define PMC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (PMC_WPMR) Register MASK (Use PMC_WPMR_Msk instead) */ +#define PMC_WPMR_Msk _U_(0xFFFFFF01) /**< (PMC_WPMR) Register Mask */ + + +/* -------- PMC_WPSR : (PMC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_WPSR_OFFSET (0xE8) /**< (PMC_WPSR) Write Protection Status Register Offset */ + +#define PMC_WPSR_WPVS_Pos 0 /**< (PMC_WPSR) Write Protection Violation Status Position */ +#define PMC_WPSR_WPVS_Msk (_U_(0x1) << PMC_WPSR_WPVS_Pos) /**< (PMC_WPSR) Write Protection Violation Status Mask */ +#define PMC_WPSR_WPVS PMC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_WPSR_WPVS_Msk instead */ +#define PMC_WPSR_WPVSRC_Pos 8 /**< (PMC_WPSR) Write Protection Violation Source Position */ +#define PMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PMC_WPSR_WPVSRC_Pos) /**< (PMC_WPSR) Write Protection Violation Source Mask */ +#define PMC_WPSR_WPVSRC(value) (PMC_WPSR_WPVSRC_Msk & ((value) << PMC_WPSR_WPVSRC_Pos)) +#define PMC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (PMC_WPSR) Register MASK (Use PMC_WPSR_Msk instead) */ +#define PMC_WPSR_Msk _U_(0xFFFF01) /**< (PMC_WPSR) Register Mask */ + + +/* -------- PMC_PCER1 : (PMC Offset: 0x100) (/W 32) Peripheral Clock Enable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Enable */ + uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Enable */ + uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Enable */ + uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Enable */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Enable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Enable */ + uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Enable */ + uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Enable */ + uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Enable */ + uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Enable */ + uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Enable */ + uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Enable */ + uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Enable */ + uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Enable */ + uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Enable */ + uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Enable */ + uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Enable */ + uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Enable */ + uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Enable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Enable */ + uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Enable */ + uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Enable */ + uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Enable */ + uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Enable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral Clock 6x Enable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCER1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCER1_OFFSET (0x100) /**< (PMC_PCER1) Peripheral Clock Enable Register 1 Offset */ + +#define PMC_PCER1_PID32_Pos 0 /**< (PMC_PCER1) Peripheral Clock 32 Enable Position */ +#define PMC_PCER1_PID32_Msk (_U_(0x1) << PMC_PCER1_PID32_Pos) /**< (PMC_PCER1) Peripheral Clock 32 Enable Mask */ +#define PMC_PCER1_PID32 PMC_PCER1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID32_Msk instead */ +#define PMC_PCER1_PID33_Pos 1 /**< (PMC_PCER1) Peripheral Clock 33 Enable Position */ +#define PMC_PCER1_PID33_Msk (_U_(0x1) << PMC_PCER1_PID33_Pos) /**< (PMC_PCER1) Peripheral Clock 33 Enable Mask */ +#define PMC_PCER1_PID33 PMC_PCER1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID33_Msk instead */ +#define PMC_PCER1_PID34_Pos 2 /**< (PMC_PCER1) Peripheral Clock 34 Enable Position */ +#define PMC_PCER1_PID34_Msk (_U_(0x1) << PMC_PCER1_PID34_Pos) /**< (PMC_PCER1) Peripheral Clock 34 Enable Mask */ +#define PMC_PCER1_PID34 PMC_PCER1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID34_Msk instead */ +#define PMC_PCER1_PID35_Pos 3 /**< (PMC_PCER1) Peripheral Clock 35 Enable Position */ +#define PMC_PCER1_PID35_Msk (_U_(0x1) << PMC_PCER1_PID35_Pos) /**< (PMC_PCER1) Peripheral Clock 35 Enable Mask */ +#define PMC_PCER1_PID35 PMC_PCER1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID35_Msk instead */ +#define PMC_PCER1_PID37_Pos 5 /**< (PMC_PCER1) Peripheral Clock 37 Enable Position */ +#define PMC_PCER1_PID37_Msk (_U_(0x1) << PMC_PCER1_PID37_Pos) /**< (PMC_PCER1) Peripheral Clock 37 Enable Mask */ +#define PMC_PCER1_PID37 PMC_PCER1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID37_Msk instead */ +#define PMC_PCER1_PID39_Pos 7 /**< (PMC_PCER1) Peripheral Clock 39 Enable Position */ +#define PMC_PCER1_PID39_Msk (_U_(0x1) << PMC_PCER1_PID39_Pos) /**< (PMC_PCER1) Peripheral Clock 39 Enable Mask */ +#define PMC_PCER1_PID39 PMC_PCER1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID39_Msk instead */ +#define PMC_PCER1_PID40_Pos 8 /**< (PMC_PCER1) Peripheral Clock 40 Enable Position */ +#define PMC_PCER1_PID40_Msk (_U_(0x1) << PMC_PCER1_PID40_Pos) /**< (PMC_PCER1) Peripheral Clock 40 Enable Mask */ +#define PMC_PCER1_PID40 PMC_PCER1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID40_Msk instead */ +#define PMC_PCER1_PID41_Pos 9 /**< (PMC_PCER1) Peripheral Clock 41 Enable Position */ +#define PMC_PCER1_PID41_Msk (_U_(0x1) << PMC_PCER1_PID41_Pos) /**< (PMC_PCER1) Peripheral Clock 41 Enable Mask */ +#define PMC_PCER1_PID41 PMC_PCER1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID41_Msk instead */ +#define PMC_PCER1_PID42_Pos 10 /**< (PMC_PCER1) Peripheral Clock 42 Enable Position */ +#define PMC_PCER1_PID42_Msk (_U_(0x1) << PMC_PCER1_PID42_Pos) /**< (PMC_PCER1) Peripheral Clock 42 Enable Mask */ +#define PMC_PCER1_PID42 PMC_PCER1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID42_Msk instead */ +#define PMC_PCER1_PID43_Pos 11 /**< (PMC_PCER1) Peripheral Clock 43 Enable Position */ +#define PMC_PCER1_PID43_Msk (_U_(0x1) << PMC_PCER1_PID43_Pos) /**< (PMC_PCER1) Peripheral Clock 43 Enable Mask */ +#define PMC_PCER1_PID43 PMC_PCER1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID43_Msk instead */ +#define PMC_PCER1_PID44_Pos 12 /**< (PMC_PCER1) Peripheral Clock 44 Enable Position */ +#define PMC_PCER1_PID44_Msk (_U_(0x1) << PMC_PCER1_PID44_Pos) /**< (PMC_PCER1) Peripheral Clock 44 Enable Mask */ +#define PMC_PCER1_PID44 PMC_PCER1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID44_Msk instead */ +#define PMC_PCER1_PID45_Pos 13 /**< (PMC_PCER1) Peripheral Clock 45 Enable Position */ +#define PMC_PCER1_PID45_Msk (_U_(0x1) << PMC_PCER1_PID45_Pos) /**< (PMC_PCER1) Peripheral Clock 45 Enable Mask */ +#define PMC_PCER1_PID45 PMC_PCER1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID45_Msk instead */ +#define PMC_PCER1_PID46_Pos 14 /**< (PMC_PCER1) Peripheral Clock 46 Enable Position */ +#define PMC_PCER1_PID46_Msk (_U_(0x1) << PMC_PCER1_PID46_Pos) /**< (PMC_PCER1) Peripheral Clock 46 Enable Mask */ +#define PMC_PCER1_PID46 PMC_PCER1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID46_Msk instead */ +#define PMC_PCER1_PID47_Pos 15 /**< (PMC_PCER1) Peripheral Clock 47 Enable Position */ +#define PMC_PCER1_PID47_Msk (_U_(0x1) << PMC_PCER1_PID47_Pos) /**< (PMC_PCER1) Peripheral Clock 47 Enable Mask */ +#define PMC_PCER1_PID47 PMC_PCER1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID47_Msk instead */ +#define PMC_PCER1_PID48_Pos 16 /**< (PMC_PCER1) Peripheral Clock 48 Enable Position */ +#define PMC_PCER1_PID48_Msk (_U_(0x1) << PMC_PCER1_PID48_Pos) /**< (PMC_PCER1) Peripheral Clock 48 Enable Mask */ +#define PMC_PCER1_PID48 PMC_PCER1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID48_Msk instead */ +#define PMC_PCER1_PID49_Pos 17 /**< (PMC_PCER1) Peripheral Clock 49 Enable Position */ +#define PMC_PCER1_PID49_Msk (_U_(0x1) << PMC_PCER1_PID49_Pos) /**< (PMC_PCER1) Peripheral Clock 49 Enable Mask */ +#define PMC_PCER1_PID49 PMC_PCER1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID49_Msk instead */ +#define PMC_PCER1_PID50_Pos 18 /**< (PMC_PCER1) Peripheral Clock 50 Enable Position */ +#define PMC_PCER1_PID50_Msk (_U_(0x1) << PMC_PCER1_PID50_Pos) /**< (PMC_PCER1) Peripheral Clock 50 Enable Mask */ +#define PMC_PCER1_PID50 PMC_PCER1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID50_Msk instead */ +#define PMC_PCER1_PID51_Pos 19 /**< (PMC_PCER1) Peripheral Clock 51 Enable Position */ +#define PMC_PCER1_PID51_Msk (_U_(0x1) << PMC_PCER1_PID51_Pos) /**< (PMC_PCER1) Peripheral Clock 51 Enable Mask */ +#define PMC_PCER1_PID51 PMC_PCER1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID51_Msk instead */ +#define PMC_PCER1_PID52_Pos 20 /**< (PMC_PCER1) Peripheral Clock 52 Enable Position */ +#define PMC_PCER1_PID52_Msk (_U_(0x1) << PMC_PCER1_PID52_Pos) /**< (PMC_PCER1) Peripheral Clock 52 Enable Mask */ +#define PMC_PCER1_PID52 PMC_PCER1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID52_Msk instead */ +#define PMC_PCER1_PID56_Pos 24 /**< (PMC_PCER1) Peripheral Clock 56 Enable Position */ +#define PMC_PCER1_PID56_Msk (_U_(0x1) << PMC_PCER1_PID56_Pos) /**< (PMC_PCER1) Peripheral Clock 56 Enable Mask */ +#define PMC_PCER1_PID56 PMC_PCER1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID56_Msk instead */ +#define PMC_PCER1_PID57_Pos 25 /**< (PMC_PCER1) Peripheral Clock 57 Enable Position */ +#define PMC_PCER1_PID57_Msk (_U_(0x1) << PMC_PCER1_PID57_Pos) /**< (PMC_PCER1) Peripheral Clock 57 Enable Mask */ +#define PMC_PCER1_PID57 PMC_PCER1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID57_Msk instead */ +#define PMC_PCER1_PID58_Pos 26 /**< (PMC_PCER1) Peripheral Clock 58 Enable Position */ +#define PMC_PCER1_PID58_Msk (_U_(0x1) << PMC_PCER1_PID58_Pos) /**< (PMC_PCER1) Peripheral Clock 58 Enable Mask */ +#define PMC_PCER1_PID58 PMC_PCER1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID58_Msk instead */ +#define PMC_PCER1_PID59_Pos 27 /**< (PMC_PCER1) Peripheral Clock 59 Enable Position */ +#define PMC_PCER1_PID59_Msk (_U_(0x1) << PMC_PCER1_PID59_Pos) /**< (PMC_PCER1) Peripheral Clock 59 Enable Mask */ +#define PMC_PCER1_PID59 PMC_PCER1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID59_Msk instead */ +#define PMC_PCER1_PID60_Pos 28 /**< (PMC_PCER1) Peripheral Clock 60 Enable Position */ +#define PMC_PCER1_PID60_Msk (_U_(0x1) << PMC_PCER1_PID60_Pos) /**< (PMC_PCER1) Peripheral Clock 60 Enable Mask */ +#define PMC_PCER1_PID60 PMC_PCER1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCER1_PID60_Msk instead */ +#define PMC_PCER1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_PCER1) Register MASK (Use PMC_PCER1_Msk instead) */ +#define PMC_PCER1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCER1) Register Mask */ + +#define PMC_PCER1_PID_Pos 0 /**< (PMC_PCER1 Position) Peripheral Clock 6x Enable */ +#define PMC_PCER1_PID_Msk (_U_(0xFFFFFF) << PMC_PCER1_PID_Pos) /**< (PMC_PCER1 Mask) PID */ +#define PMC_PCER1_PID(value) (PMC_PCER1_PID_Msk & ((value) << PMC_PCER1_PID_Pos)) + +/* -------- PMC_PCDR1 : (PMC Offset: 0x104) (/W 32) Peripheral Clock Disable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Disable */ + uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Disable */ + uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Disable */ + uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Disable */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Disable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Disable */ + uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Disable */ + uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Disable */ + uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Disable */ + uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Disable */ + uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Disable */ + uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Disable */ + uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Disable */ + uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Disable */ + uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Disable */ + uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Disable */ + uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Disable */ + uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Disable */ + uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Disable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Disable */ + uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Disable */ + uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Disable */ + uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Disable */ + uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Disable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral Clock 6x Disable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCDR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCDR1_OFFSET (0x104) /**< (PMC_PCDR1) Peripheral Clock Disable Register 1 Offset */ + +#define PMC_PCDR1_PID32_Pos 0 /**< (PMC_PCDR1) Peripheral Clock 32 Disable Position */ +#define PMC_PCDR1_PID32_Msk (_U_(0x1) << PMC_PCDR1_PID32_Pos) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Mask */ +#define PMC_PCDR1_PID32 PMC_PCDR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID32_Msk instead */ +#define PMC_PCDR1_PID33_Pos 1 /**< (PMC_PCDR1) Peripheral Clock 33 Disable Position */ +#define PMC_PCDR1_PID33_Msk (_U_(0x1) << PMC_PCDR1_PID33_Pos) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Mask */ +#define PMC_PCDR1_PID33 PMC_PCDR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID33_Msk instead */ +#define PMC_PCDR1_PID34_Pos 2 /**< (PMC_PCDR1) Peripheral Clock 34 Disable Position */ +#define PMC_PCDR1_PID34_Msk (_U_(0x1) << PMC_PCDR1_PID34_Pos) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Mask */ +#define PMC_PCDR1_PID34 PMC_PCDR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID34_Msk instead */ +#define PMC_PCDR1_PID35_Pos 3 /**< (PMC_PCDR1) Peripheral Clock 35 Disable Position */ +#define PMC_PCDR1_PID35_Msk (_U_(0x1) << PMC_PCDR1_PID35_Pos) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Mask */ +#define PMC_PCDR1_PID35 PMC_PCDR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID35_Msk instead */ +#define PMC_PCDR1_PID37_Pos 5 /**< (PMC_PCDR1) Peripheral Clock 37 Disable Position */ +#define PMC_PCDR1_PID37_Msk (_U_(0x1) << PMC_PCDR1_PID37_Pos) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Mask */ +#define PMC_PCDR1_PID37 PMC_PCDR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID37_Msk instead */ +#define PMC_PCDR1_PID39_Pos 7 /**< (PMC_PCDR1) Peripheral Clock 39 Disable Position */ +#define PMC_PCDR1_PID39_Msk (_U_(0x1) << PMC_PCDR1_PID39_Pos) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Mask */ +#define PMC_PCDR1_PID39 PMC_PCDR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID39_Msk instead */ +#define PMC_PCDR1_PID40_Pos 8 /**< (PMC_PCDR1) Peripheral Clock 40 Disable Position */ +#define PMC_PCDR1_PID40_Msk (_U_(0x1) << PMC_PCDR1_PID40_Pos) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Mask */ +#define PMC_PCDR1_PID40 PMC_PCDR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID40_Msk instead */ +#define PMC_PCDR1_PID41_Pos 9 /**< (PMC_PCDR1) Peripheral Clock 41 Disable Position */ +#define PMC_PCDR1_PID41_Msk (_U_(0x1) << PMC_PCDR1_PID41_Pos) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Mask */ +#define PMC_PCDR1_PID41 PMC_PCDR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID41_Msk instead */ +#define PMC_PCDR1_PID42_Pos 10 /**< (PMC_PCDR1) Peripheral Clock 42 Disable Position */ +#define PMC_PCDR1_PID42_Msk (_U_(0x1) << PMC_PCDR1_PID42_Pos) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Mask */ +#define PMC_PCDR1_PID42 PMC_PCDR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID42_Msk instead */ +#define PMC_PCDR1_PID43_Pos 11 /**< (PMC_PCDR1) Peripheral Clock 43 Disable Position */ +#define PMC_PCDR1_PID43_Msk (_U_(0x1) << PMC_PCDR1_PID43_Pos) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Mask */ +#define PMC_PCDR1_PID43 PMC_PCDR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID43_Msk instead */ +#define PMC_PCDR1_PID44_Pos 12 /**< (PMC_PCDR1) Peripheral Clock 44 Disable Position */ +#define PMC_PCDR1_PID44_Msk (_U_(0x1) << PMC_PCDR1_PID44_Pos) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Mask */ +#define PMC_PCDR1_PID44 PMC_PCDR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID44_Msk instead */ +#define PMC_PCDR1_PID45_Pos 13 /**< (PMC_PCDR1) Peripheral Clock 45 Disable Position */ +#define PMC_PCDR1_PID45_Msk (_U_(0x1) << PMC_PCDR1_PID45_Pos) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Mask */ +#define PMC_PCDR1_PID45 PMC_PCDR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID45_Msk instead */ +#define PMC_PCDR1_PID46_Pos 14 /**< (PMC_PCDR1) Peripheral Clock 46 Disable Position */ +#define PMC_PCDR1_PID46_Msk (_U_(0x1) << PMC_PCDR1_PID46_Pos) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Mask */ +#define PMC_PCDR1_PID46 PMC_PCDR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID46_Msk instead */ +#define PMC_PCDR1_PID47_Pos 15 /**< (PMC_PCDR1) Peripheral Clock 47 Disable Position */ +#define PMC_PCDR1_PID47_Msk (_U_(0x1) << PMC_PCDR1_PID47_Pos) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Mask */ +#define PMC_PCDR1_PID47 PMC_PCDR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID47_Msk instead */ +#define PMC_PCDR1_PID48_Pos 16 /**< (PMC_PCDR1) Peripheral Clock 48 Disable Position */ +#define PMC_PCDR1_PID48_Msk (_U_(0x1) << PMC_PCDR1_PID48_Pos) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Mask */ +#define PMC_PCDR1_PID48 PMC_PCDR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID48_Msk instead */ +#define PMC_PCDR1_PID49_Pos 17 /**< (PMC_PCDR1) Peripheral Clock 49 Disable Position */ +#define PMC_PCDR1_PID49_Msk (_U_(0x1) << PMC_PCDR1_PID49_Pos) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Mask */ +#define PMC_PCDR1_PID49 PMC_PCDR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID49_Msk instead */ +#define PMC_PCDR1_PID50_Pos 18 /**< (PMC_PCDR1) Peripheral Clock 50 Disable Position */ +#define PMC_PCDR1_PID50_Msk (_U_(0x1) << PMC_PCDR1_PID50_Pos) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Mask */ +#define PMC_PCDR1_PID50 PMC_PCDR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID50_Msk instead */ +#define PMC_PCDR1_PID51_Pos 19 /**< (PMC_PCDR1) Peripheral Clock 51 Disable Position */ +#define PMC_PCDR1_PID51_Msk (_U_(0x1) << PMC_PCDR1_PID51_Pos) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Mask */ +#define PMC_PCDR1_PID51 PMC_PCDR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID51_Msk instead */ +#define PMC_PCDR1_PID52_Pos 20 /**< (PMC_PCDR1) Peripheral Clock 52 Disable Position */ +#define PMC_PCDR1_PID52_Msk (_U_(0x1) << PMC_PCDR1_PID52_Pos) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Mask */ +#define PMC_PCDR1_PID52 PMC_PCDR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID52_Msk instead */ +#define PMC_PCDR1_PID56_Pos 24 /**< (PMC_PCDR1) Peripheral Clock 56 Disable Position */ +#define PMC_PCDR1_PID56_Msk (_U_(0x1) << PMC_PCDR1_PID56_Pos) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Mask */ +#define PMC_PCDR1_PID56 PMC_PCDR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID56_Msk instead */ +#define PMC_PCDR1_PID57_Pos 25 /**< (PMC_PCDR1) Peripheral Clock 57 Disable Position */ +#define PMC_PCDR1_PID57_Msk (_U_(0x1) << PMC_PCDR1_PID57_Pos) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Mask */ +#define PMC_PCDR1_PID57 PMC_PCDR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID57_Msk instead */ +#define PMC_PCDR1_PID58_Pos 26 /**< (PMC_PCDR1) Peripheral Clock 58 Disable Position */ +#define PMC_PCDR1_PID58_Msk (_U_(0x1) << PMC_PCDR1_PID58_Pos) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Mask */ +#define PMC_PCDR1_PID58 PMC_PCDR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID58_Msk instead */ +#define PMC_PCDR1_PID59_Pos 27 /**< (PMC_PCDR1) Peripheral Clock 59 Disable Position */ +#define PMC_PCDR1_PID59_Msk (_U_(0x1) << PMC_PCDR1_PID59_Pos) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Mask */ +#define PMC_PCDR1_PID59 PMC_PCDR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID59_Msk instead */ +#define PMC_PCDR1_PID60_Pos 28 /**< (PMC_PCDR1) Peripheral Clock 60 Disable Position */ +#define PMC_PCDR1_PID60_Msk (_U_(0x1) << PMC_PCDR1_PID60_Pos) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Mask */ +#define PMC_PCDR1_PID60 PMC_PCDR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCDR1_PID60_Msk instead */ +#define PMC_PCDR1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_PCDR1) Register MASK (Use PMC_PCDR1_Msk instead) */ +#define PMC_PCDR1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCDR1) Register Mask */ + +#define PMC_PCDR1_PID_Pos 0 /**< (PMC_PCDR1 Position) Peripheral Clock 6x Disable */ +#define PMC_PCDR1_PID_Msk (_U_(0xFFFFFF) << PMC_PCDR1_PID_Pos) /**< (PMC_PCDR1 Mask) PID */ +#define PMC_PCDR1_PID(value) (PMC_PCDR1_PID_Msk & ((value) << PMC_PCDR1_PID_Pos)) + +/* -------- PMC_PCSR1 : (PMC Offset: 0x108) (R/ 32) Peripheral Clock Status Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral Clock 32 Status */ + uint32_t PID33:1; /**< bit: 1 Peripheral Clock 33 Status */ + uint32_t PID34:1; /**< bit: 2 Peripheral Clock 34 Status */ + uint32_t PID35:1; /**< bit: 3 Peripheral Clock 35 Status */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral Clock 37 Status */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral Clock 39 Status */ + uint32_t PID40:1; /**< bit: 8 Peripheral Clock 40 Status */ + uint32_t PID41:1; /**< bit: 9 Peripheral Clock 41 Status */ + uint32_t PID42:1; /**< bit: 10 Peripheral Clock 42 Status */ + uint32_t PID43:1; /**< bit: 11 Peripheral Clock 43 Status */ + uint32_t PID44:1; /**< bit: 12 Peripheral Clock 44 Status */ + uint32_t PID45:1; /**< bit: 13 Peripheral Clock 45 Status */ + uint32_t PID46:1; /**< bit: 14 Peripheral Clock 46 Status */ + uint32_t PID47:1; /**< bit: 15 Peripheral Clock 47 Status */ + uint32_t PID48:1; /**< bit: 16 Peripheral Clock 48 Status */ + uint32_t PID49:1; /**< bit: 17 Peripheral Clock 49 Status */ + uint32_t PID50:1; /**< bit: 18 Peripheral Clock 50 Status */ + uint32_t PID51:1; /**< bit: 19 Peripheral Clock 51 Status */ + uint32_t PID52:1; /**< bit: 20 Peripheral Clock 52 Status */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral Clock 56 Status */ + uint32_t PID57:1; /**< bit: 25 Peripheral Clock 57 Status */ + uint32_t PID58:1; /**< bit: 26 Peripheral Clock 58 Status */ + uint32_t PID59:1; /**< bit: 27 Peripheral Clock 59 Status */ + uint32_t PID60:1; /**< bit: 28 Peripheral Clock 60 Status */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral Clock 6x Status */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCSR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCSR1_OFFSET (0x108) /**< (PMC_PCSR1) Peripheral Clock Status Register 1 Offset */ + +#define PMC_PCSR1_PID32_Pos 0 /**< (PMC_PCSR1) Peripheral Clock 32 Status Position */ +#define PMC_PCSR1_PID32_Msk (_U_(0x1) << PMC_PCSR1_PID32_Pos) /**< (PMC_PCSR1) Peripheral Clock 32 Status Mask */ +#define PMC_PCSR1_PID32 PMC_PCSR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID32_Msk instead */ +#define PMC_PCSR1_PID33_Pos 1 /**< (PMC_PCSR1) Peripheral Clock 33 Status Position */ +#define PMC_PCSR1_PID33_Msk (_U_(0x1) << PMC_PCSR1_PID33_Pos) /**< (PMC_PCSR1) Peripheral Clock 33 Status Mask */ +#define PMC_PCSR1_PID33 PMC_PCSR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID33_Msk instead */ +#define PMC_PCSR1_PID34_Pos 2 /**< (PMC_PCSR1) Peripheral Clock 34 Status Position */ +#define PMC_PCSR1_PID34_Msk (_U_(0x1) << PMC_PCSR1_PID34_Pos) /**< (PMC_PCSR1) Peripheral Clock 34 Status Mask */ +#define PMC_PCSR1_PID34 PMC_PCSR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID34_Msk instead */ +#define PMC_PCSR1_PID35_Pos 3 /**< (PMC_PCSR1) Peripheral Clock 35 Status Position */ +#define PMC_PCSR1_PID35_Msk (_U_(0x1) << PMC_PCSR1_PID35_Pos) /**< (PMC_PCSR1) Peripheral Clock 35 Status Mask */ +#define PMC_PCSR1_PID35 PMC_PCSR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID35_Msk instead */ +#define PMC_PCSR1_PID37_Pos 5 /**< (PMC_PCSR1) Peripheral Clock 37 Status Position */ +#define PMC_PCSR1_PID37_Msk (_U_(0x1) << PMC_PCSR1_PID37_Pos) /**< (PMC_PCSR1) Peripheral Clock 37 Status Mask */ +#define PMC_PCSR1_PID37 PMC_PCSR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID37_Msk instead */ +#define PMC_PCSR1_PID39_Pos 7 /**< (PMC_PCSR1) Peripheral Clock 39 Status Position */ +#define PMC_PCSR1_PID39_Msk (_U_(0x1) << PMC_PCSR1_PID39_Pos) /**< (PMC_PCSR1) Peripheral Clock 39 Status Mask */ +#define PMC_PCSR1_PID39 PMC_PCSR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID39_Msk instead */ +#define PMC_PCSR1_PID40_Pos 8 /**< (PMC_PCSR1) Peripheral Clock 40 Status Position */ +#define PMC_PCSR1_PID40_Msk (_U_(0x1) << PMC_PCSR1_PID40_Pos) /**< (PMC_PCSR1) Peripheral Clock 40 Status Mask */ +#define PMC_PCSR1_PID40 PMC_PCSR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID40_Msk instead */ +#define PMC_PCSR1_PID41_Pos 9 /**< (PMC_PCSR1) Peripheral Clock 41 Status Position */ +#define PMC_PCSR1_PID41_Msk (_U_(0x1) << PMC_PCSR1_PID41_Pos) /**< (PMC_PCSR1) Peripheral Clock 41 Status Mask */ +#define PMC_PCSR1_PID41 PMC_PCSR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID41_Msk instead */ +#define PMC_PCSR1_PID42_Pos 10 /**< (PMC_PCSR1) Peripheral Clock 42 Status Position */ +#define PMC_PCSR1_PID42_Msk (_U_(0x1) << PMC_PCSR1_PID42_Pos) /**< (PMC_PCSR1) Peripheral Clock 42 Status Mask */ +#define PMC_PCSR1_PID42 PMC_PCSR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID42_Msk instead */ +#define PMC_PCSR1_PID43_Pos 11 /**< (PMC_PCSR1) Peripheral Clock 43 Status Position */ +#define PMC_PCSR1_PID43_Msk (_U_(0x1) << PMC_PCSR1_PID43_Pos) /**< (PMC_PCSR1) Peripheral Clock 43 Status Mask */ +#define PMC_PCSR1_PID43 PMC_PCSR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID43_Msk instead */ +#define PMC_PCSR1_PID44_Pos 12 /**< (PMC_PCSR1) Peripheral Clock 44 Status Position */ +#define PMC_PCSR1_PID44_Msk (_U_(0x1) << PMC_PCSR1_PID44_Pos) /**< (PMC_PCSR1) Peripheral Clock 44 Status Mask */ +#define PMC_PCSR1_PID44 PMC_PCSR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID44_Msk instead */ +#define PMC_PCSR1_PID45_Pos 13 /**< (PMC_PCSR1) Peripheral Clock 45 Status Position */ +#define PMC_PCSR1_PID45_Msk (_U_(0x1) << PMC_PCSR1_PID45_Pos) /**< (PMC_PCSR1) Peripheral Clock 45 Status Mask */ +#define PMC_PCSR1_PID45 PMC_PCSR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID45_Msk instead */ +#define PMC_PCSR1_PID46_Pos 14 /**< (PMC_PCSR1) Peripheral Clock 46 Status Position */ +#define PMC_PCSR1_PID46_Msk (_U_(0x1) << PMC_PCSR1_PID46_Pos) /**< (PMC_PCSR1) Peripheral Clock 46 Status Mask */ +#define PMC_PCSR1_PID46 PMC_PCSR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID46_Msk instead */ +#define PMC_PCSR1_PID47_Pos 15 /**< (PMC_PCSR1) Peripheral Clock 47 Status Position */ +#define PMC_PCSR1_PID47_Msk (_U_(0x1) << PMC_PCSR1_PID47_Pos) /**< (PMC_PCSR1) Peripheral Clock 47 Status Mask */ +#define PMC_PCSR1_PID47 PMC_PCSR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID47_Msk instead */ +#define PMC_PCSR1_PID48_Pos 16 /**< (PMC_PCSR1) Peripheral Clock 48 Status Position */ +#define PMC_PCSR1_PID48_Msk (_U_(0x1) << PMC_PCSR1_PID48_Pos) /**< (PMC_PCSR1) Peripheral Clock 48 Status Mask */ +#define PMC_PCSR1_PID48 PMC_PCSR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID48_Msk instead */ +#define PMC_PCSR1_PID49_Pos 17 /**< (PMC_PCSR1) Peripheral Clock 49 Status Position */ +#define PMC_PCSR1_PID49_Msk (_U_(0x1) << PMC_PCSR1_PID49_Pos) /**< (PMC_PCSR1) Peripheral Clock 49 Status Mask */ +#define PMC_PCSR1_PID49 PMC_PCSR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID49_Msk instead */ +#define PMC_PCSR1_PID50_Pos 18 /**< (PMC_PCSR1) Peripheral Clock 50 Status Position */ +#define PMC_PCSR1_PID50_Msk (_U_(0x1) << PMC_PCSR1_PID50_Pos) /**< (PMC_PCSR1) Peripheral Clock 50 Status Mask */ +#define PMC_PCSR1_PID50 PMC_PCSR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID50_Msk instead */ +#define PMC_PCSR1_PID51_Pos 19 /**< (PMC_PCSR1) Peripheral Clock 51 Status Position */ +#define PMC_PCSR1_PID51_Msk (_U_(0x1) << PMC_PCSR1_PID51_Pos) /**< (PMC_PCSR1) Peripheral Clock 51 Status Mask */ +#define PMC_PCSR1_PID51 PMC_PCSR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID51_Msk instead */ +#define PMC_PCSR1_PID52_Pos 20 /**< (PMC_PCSR1) Peripheral Clock 52 Status Position */ +#define PMC_PCSR1_PID52_Msk (_U_(0x1) << PMC_PCSR1_PID52_Pos) /**< (PMC_PCSR1) Peripheral Clock 52 Status Mask */ +#define PMC_PCSR1_PID52 PMC_PCSR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID52_Msk instead */ +#define PMC_PCSR1_PID56_Pos 24 /**< (PMC_PCSR1) Peripheral Clock 56 Status Position */ +#define PMC_PCSR1_PID56_Msk (_U_(0x1) << PMC_PCSR1_PID56_Pos) /**< (PMC_PCSR1) Peripheral Clock 56 Status Mask */ +#define PMC_PCSR1_PID56 PMC_PCSR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID56_Msk instead */ +#define PMC_PCSR1_PID57_Pos 25 /**< (PMC_PCSR1) Peripheral Clock 57 Status Position */ +#define PMC_PCSR1_PID57_Msk (_U_(0x1) << PMC_PCSR1_PID57_Pos) /**< (PMC_PCSR1) Peripheral Clock 57 Status Mask */ +#define PMC_PCSR1_PID57 PMC_PCSR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID57_Msk instead */ +#define PMC_PCSR1_PID58_Pos 26 /**< (PMC_PCSR1) Peripheral Clock 58 Status Position */ +#define PMC_PCSR1_PID58_Msk (_U_(0x1) << PMC_PCSR1_PID58_Pos) /**< (PMC_PCSR1) Peripheral Clock 58 Status Mask */ +#define PMC_PCSR1_PID58 PMC_PCSR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID58_Msk instead */ +#define PMC_PCSR1_PID59_Pos 27 /**< (PMC_PCSR1) Peripheral Clock 59 Status Position */ +#define PMC_PCSR1_PID59_Msk (_U_(0x1) << PMC_PCSR1_PID59_Pos) /**< (PMC_PCSR1) Peripheral Clock 59 Status Mask */ +#define PMC_PCSR1_PID59 PMC_PCSR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID59_Msk instead */ +#define PMC_PCSR1_PID60_Pos 28 /**< (PMC_PCSR1) Peripheral Clock 60 Status Position */ +#define PMC_PCSR1_PID60_Msk (_U_(0x1) << PMC_PCSR1_PID60_Pos) /**< (PMC_PCSR1) Peripheral Clock 60 Status Mask */ +#define PMC_PCSR1_PID60 PMC_PCSR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCSR1_PID60_Msk instead */ +#define PMC_PCSR1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_PCSR1) Register MASK (Use PMC_PCSR1_Msk instead) */ +#define PMC_PCSR1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCSR1) Register Mask */ + +#define PMC_PCSR1_PID_Pos 0 /**< (PMC_PCSR1 Position) Peripheral Clock 6x Status */ +#define PMC_PCSR1_PID_Msk (_U_(0xFFFFFF) << PMC_PCSR1_PID_Pos) /**< (PMC_PCSR1 Mask) PID */ +#define PMC_PCSR1_PID(value) (PMC_PCSR1_PID_Msk & ((value) << PMC_PCSR1_PID_Pos)) + +/* -------- PMC_PCR : (PMC Offset: 0x10c) (R/W 32) Peripheral Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID:7; /**< bit: 0..6 Peripheral ID */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t GCLKCSS:3; /**< bit: 8..10 Generic Clock Source Selection */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t CMD:1; /**< bit: 12 Command */ + uint32_t :7; /**< bit: 13..19 Reserved */ + uint32_t GCLKDIV:8; /**< bit: 20..27 Generic Clock Division Ratio */ + uint32_t EN:1; /**< bit: 28 Enable */ + uint32_t GCLKEN:1; /**< bit: 29 Generic Clock Enable */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PCR_OFFSET (0x10C) /**< (PMC_PCR) Peripheral Control Register Offset */ + +#define PMC_PCR_PID_Pos 0 /**< (PMC_PCR) Peripheral ID Position */ +#define PMC_PCR_PID_Msk (_U_(0x7F) << PMC_PCR_PID_Pos) /**< (PMC_PCR) Peripheral ID Mask */ +#define PMC_PCR_PID(value) (PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)) +#define PMC_PCR_GCLKCSS_Pos 8 /**< (PMC_PCR) Generic Clock Source Selection Position */ +#define PMC_PCR_GCLKCSS_Msk (_U_(0x7) << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Generic Clock Source Selection Mask */ +#define PMC_PCR_GCLKCSS(value) (PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)) +#define PMC_PCR_GCLKCSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCR) Slow clock is selected */ +#define PMC_PCR_GCLKCSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCR) Main clock is selected */ +#define PMC_PCR_GCLKCSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCR) PLLACK is selected */ +#define PMC_PCR_GCLKCSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCR) UPLL Clock is selected */ +#define PMC_PCR_GCLKCSS_MCK_CLK_Val _U_(0x4) /**< (PMC_PCR) Master Clock is selected */ +#define PMC_PCR_GCLKCSS_SLOW_CLK (PMC_PCR_GCLKCSS_SLOW_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Slow clock is selected Position */ +#define PMC_PCR_GCLKCSS_MAIN_CLK (PMC_PCR_GCLKCSS_MAIN_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Main clock is selected Position */ +#define PMC_PCR_GCLKCSS_PLLA_CLK (PMC_PCR_GCLKCSS_PLLA_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) PLLACK is selected Position */ +#define PMC_PCR_GCLKCSS_UPLL_CLK (PMC_PCR_GCLKCSS_UPLL_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) UPLL Clock is selected Position */ +#define PMC_PCR_GCLKCSS_MCK_CLK (PMC_PCR_GCLKCSS_MCK_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Master Clock is selected Position */ +#define PMC_PCR_CMD_Pos 12 /**< (PMC_PCR) Command Position */ +#define PMC_PCR_CMD_Msk (_U_(0x1) << PMC_PCR_CMD_Pos) /**< (PMC_PCR) Command Mask */ +#define PMC_PCR_CMD PMC_PCR_CMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_CMD_Msk instead */ +#define PMC_PCR_GCLKDIV_Pos 20 /**< (PMC_PCR) Generic Clock Division Ratio Position */ +#define PMC_PCR_GCLKDIV_Msk (_U_(0xFF) << PMC_PCR_GCLKDIV_Pos) /**< (PMC_PCR) Generic Clock Division Ratio Mask */ +#define PMC_PCR_GCLKDIV(value) (PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)) +#define PMC_PCR_EN_Pos 28 /**< (PMC_PCR) Enable Position */ +#define PMC_PCR_EN_Msk (_U_(0x1) << PMC_PCR_EN_Pos) /**< (PMC_PCR) Enable Mask */ +#define PMC_PCR_EN PMC_PCR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_EN_Msk instead */ +#define PMC_PCR_GCLKEN_Pos 29 /**< (PMC_PCR) Generic Clock Enable Position */ +#define PMC_PCR_GCLKEN_Msk (_U_(0x1) << PMC_PCR_GCLKEN_Pos) /**< (PMC_PCR) Generic Clock Enable Mask */ +#define PMC_PCR_GCLKEN PMC_PCR_GCLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_PCR_GCLKEN_Msk instead */ +#define PMC_PCR_MASK _U_(0x3FF0177F) /**< \deprecated (PMC_PCR) Register MASK (Use PMC_PCR_Msk instead) */ +#define PMC_PCR_Msk _U_(0x3FF0177F) /**< (PMC_PCR) Register Mask */ + + +/* -------- PMC_OCR : (PMC Offset: 0x110) (R/W 32) Oscillator Calibration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CAL4:7; /**< bit: 0..6 Main RC Oscillator Calibration Bits for 4 MHz */ + uint32_t SEL4:1; /**< bit: 7 Selection of Main RC Oscillator Calibration Bits for 4 MHz */ + uint32_t CAL8:7; /**< bit: 8..14 Main RC Oscillator Calibration Bits for 8 MHz */ + uint32_t SEL8:1; /**< bit: 15 Selection of Main RC Oscillator Calibration Bits for 8 MHz */ + uint32_t CAL12:7; /**< bit: 16..22 Main RC Oscillator Calibration Bits for 12 MHz */ + uint32_t SEL12:1; /**< bit: 23 Selection of Main RC Oscillator Calibration Bits for 12 MHz */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_OCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_OCR_OFFSET (0x110) /**< (PMC_OCR) Oscillator Calibration Register Offset */ + +#define PMC_OCR_CAL4_Pos 0 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_CAL4_Msk (_U_(0x7F) << PMC_OCR_CAL4_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)) +#define PMC_OCR_SEL4_Pos 7 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_SEL4_Msk (_U_(0x1) << PMC_OCR_SEL4_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_SEL4 PMC_OCR_SEL4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL4_Msk instead */ +#define PMC_OCR_CAL8_Pos 8 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_CAL8_Msk (_U_(0x7F) << PMC_OCR_CAL8_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_CAL8(value) (PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)) +#define PMC_OCR_SEL8_Pos 15 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_SEL8_Msk (_U_(0x1) << PMC_OCR_SEL8_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_SEL8 PMC_OCR_SEL8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL8_Msk instead */ +#define PMC_OCR_CAL12_Pos 16 /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_CAL12_Msk (_U_(0x7F) << PMC_OCR_CAL12_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_CAL12(value) (PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)) +#define PMC_OCR_SEL12_Pos 23 /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_SEL12_Msk (_U_(0x1) << PMC_OCR_SEL12_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_SEL12 PMC_OCR_SEL12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_OCR_SEL12_Msk instead */ +#define PMC_OCR_MASK _U_(0xFFFFFF) /**< \deprecated (PMC_OCR) Register MASK (Use PMC_OCR_Msk instead) */ +#define PMC_OCR_Msk _U_(0xFFFFFF) /**< (PMC_OCR) Register Mask */ + + +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) (/W 32) SleepWalking Enable Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Enable */ + uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Enable */ + uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Enable */ + uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Enable */ + uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Enable */ + uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Enable */ + uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Enable */ + uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Enable */ + uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Enable */ + uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Enable */ + uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Enable */ + uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Enable */ + uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Enable */ + uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Enable */ + uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Enable */ + uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Enable */ + uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Enable */ + uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Enable */ + uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Enable */ + uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Enable */ + uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Enable */ + uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Enable */ + uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Enable */ + uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Enable */ + uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_ER0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_ER0_OFFSET (0x114) /**< (PMC_SLPWK_ER0) SleepWalking Enable Register 0 Offset */ + +#define PMC_SLPWK_ER0_PID7_Pos 7 /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID7_Pos) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID7 PMC_SLPWK_ER0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID7_Msk instead */ +#define PMC_SLPWK_ER0_PID8_Pos 8 /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID8_Pos) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID8 PMC_SLPWK_ER0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID8_Msk instead */ +#define PMC_SLPWK_ER0_PID9_Pos 9 /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID9_Pos) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID9 PMC_SLPWK_ER0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID9_Msk instead */ +#define PMC_SLPWK_ER0_PID10_Pos 10 /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID10_Pos) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID10 PMC_SLPWK_ER0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID10_Msk instead */ +#define PMC_SLPWK_ER0_PID11_Pos 11 /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID11_Pos) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID11 PMC_SLPWK_ER0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID11_Msk instead */ +#define PMC_SLPWK_ER0_PID12_Pos 12 /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID12_Pos) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID12 PMC_SLPWK_ER0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID12_Msk instead */ +#define PMC_SLPWK_ER0_PID13_Pos 13 /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID13_Pos) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID13 PMC_SLPWK_ER0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID13_Msk instead */ +#define PMC_SLPWK_ER0_PID14_Pos 14 /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID14_Pos) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID14 PMC_SLPWK_ER0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID14_Msk instead */ +#define PMC_SLPWK_ER0_PID15_Pos 15 /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID15_Pos) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID15 PMC_SLPWK_ER0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID15_Msk instead */ +#define PMC_SLPWK_ER0_PID16_Pos 16 /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID16_Pos) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID16 PMC_SLPWK_ER0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID16_Msk instead */ +#define PMC_SLPWK_ER0_PID17_Pos 17 /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID17_Pos) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID17 PMC_SLPWK_ER0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID17_Msk instead */ +#define PMC_SLPWK_ER0_PID18_Pos 18 /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID18_Pos) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID18 PMC_SLPWK_ER0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID18_Msk instead */ +#define PMC_SLPWK_ER0_PID19_Pos 19 /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID19_Pos) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID19 PMC_SLPWK_ER0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID19_Msk instead */ +#define PMC_SLPWK_ER0_PID20_Pos 20 /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID20_Pos) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID20 PMC_SLPWK_ER0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID20_Msk instead */ +#define PMC_SLPWK_ER0_PID21_Pos 21 /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID21_Pos) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID21 PMC_SLPWK_ER0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID21_Msk instead */ +#define PMC_SLPWK_ER0_PID22_Pos 22 /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID22_Pos) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID22 PMC_SLPWK_ER0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID22_Msk instead */ +#define PMC_SLPWK_ER0_PID23_Pos 23 /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID23_Pos) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID23 PMC_SLPWK_ER0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID23_Msk instead */ +#define PMC_SLPWK_ER0_PID24_Pos 24 /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID24_Pos) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID24 PMC_SLPWK_ER0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID24_Msk instead */ +#define PMC_SLPWK_ER0_PID25_Pos 25 /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID25_Pos) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID25 PMC_SLPWK_ER0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID25_Msk instead */ +#define PMC_SLPWK_ER0_PID26_Pos 26 /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID26_Pos) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID26 PMC_SLPWK_ER0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID26_Msk instead */ +#define PMC_SLPWK_ER0_PID27_Pos 27 /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID27_Pos) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID27 PMC_SLPWK_ER0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID27_Msk instead */ +#define PMC_SLPWK_ER0_PID28_Pos 28 /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID28_Pos) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID28 PMC_SLPWK_ER0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID28_Msk instead */ +#define PMC_SLPWK_ER0_PID29_Pos 29 /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID29_Pos) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID29 PMC_SLPWK_ER0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID29_Msk instead */ +#define PMC_SLPWK_ER0_PID30_Pos 30 /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID30_Pos) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID30 PMC_SLPWK_ER0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID30_Msk instead */ +#define PMC_SLPWK_ER0_PID31_Pos 31 /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID31_Pos) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID31 PMC_SLPWK_ER0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER0_PID31_Msk instead */ +#define PMC_SLPWK_ER0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_ER0) Register MASK (Use PMC_SLPWK_ER0_Msk instead) */ +#define PMC_SLPWK_ER0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ER0) Register Mask */ + +#define PMC_SLPWK_ER0_PID_Pos 7 /**< (PMC_SLPWK_ER0 Position) Peripheral 3x SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER0_PID_Pos) /**< (PMC_SLPWK_ER0 Mask) PID */ +#define PMC_SLPWK_ER0_PID(value) (PMC_SLPWK_ER0_PID_Msk & ((value) << PMC_SLPWK_ER0_PID_Pos)) + +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) (/W 32) SleepWalking Disable Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Disable */ + uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Disable */ + uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Disable */ + uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Disable */ + uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Disable */ + uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Disable */ + uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Disable */ + uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Disable */ + uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Disable */ + uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Disable */ + uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Disable */ + uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Disable */ + uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Disable */ + uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Disable */ + uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Disable */ + uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Disable */ + uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Disable */ + uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Disable */ + uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Disable */ + uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Disable */ + uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Disable */ + uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Disable */ + uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Disable */ + uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Disable */ + uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_DR0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_DR0_OFFSET (0x118) /**< (PMC_SLPWK_DR0) SleepWalking Disable Register 0 Offset */ + +#define PMC_SLPWK_DR0_PID7_Pos 7 /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID7_Pos) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID7 PMC_SLPWK_DR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID7_Msk instead */ +#define PMC_SLPWK_DR0_PID8_Pos 8 /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID8_Pos) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID8 PMC_SLPWK_DR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID8_Msk instead */ +#define PMC_SLPWK_DR0_PID9_Pos 9 /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID9_Pos) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID9 PMC_SLPWK_DR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID9_Msk instead */ +#define PMC_SLPWK_DR0_PID10_Pos 10 /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID10_Pos) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID10 PMC_SLPWK_DR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID10_Msk instead */ +#define PMC_SLPWK_DR0_PID11_Pos 11 /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID11_Pos) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID11 PMC_SLPWK_DR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID11_Msk instead */ +#define PMC_SLPWK_DR0_PID12_Pos 12 /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID12_Pos) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID12 PMC_SLPWK_DR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID12_Msk instead */ +#define PMC_SLPWK_DR0_PID13_Pos 13 /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID13_Pos) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID13 PMC_SLPWK_DR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID13_Msk instead */ +#define PMC_SLPWK_DR0_PID14_Pos 14 /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID14_Pos) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID14 PMC_SLPWK_DR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID14_Msk instead */ +#define PMC_SLPWK_DR0_PID15_Pos 15 /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID15_Pos) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID15 PMC_SLPWK_DR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID15_Msk instead */ +#define PMC_SLPWK_DR0_PID16_Pos 16 /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID16_Pos) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID16 PMC_SLPWK_DR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID16_Msk instead */ +#define PMC_SLPWK_DR0_PID17_Pos 17 /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID17_Pos) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID17 PMC_SLPWK_DR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID17_Msk instead */ +#define PMC_SLPWK_DR0_PID18_Pos 18 /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID18_Pos) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID18 PMC_SLPWK_DR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID18_Msk instead */ +#define PMC_SLPWK_DR0_PID19_Pos 19 /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID19_Pos) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID19 PMC_SLPWK_DR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID19_Msk instead */ +#define PMC_SLPWK_DR0_PID20_Pos 20 /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID20_Pos) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID20 PMC_SLPWK_DR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID20_Msk instead */ +#define PMC_SLPWK_DR0_PID21_Pos 21 /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID21_Pos) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID21 PMC_SLPWK_DR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID21_Msk instead */ +#define PMC_SLPWK_DR0_PID22_Pos 22 /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID22_Pos) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID22 PMC_SLPWK_DR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID22_Msk instead */ +#define PMC_SLPWK_DR0_PID23_Pos 23 /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID23_Pos) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID23 PMC_SLPWK_DR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID23_Msk instead */ +#define PMC_SLPWK_DR0_PID24_Pos 24 /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID24_Pos) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID24 PMC_SLPWK_DR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID24_Msk instead */ +#define PMC_SLPWK_DR0_PID25_Pos 25 /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID25_Pos) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID25 PMC_SLPWK_DR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID25_Msk instead */ +#define PMC_SLPWK_DR0_PID26_Pos 26 /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID26_Pos) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID26 PMC_SLPWK_DR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID26_Msk instead */ +#define PMC_SLPWK_DR0_PID27_Pos 27 /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID27_Pos) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID27 PMC_SLPWK_DR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID27_Msk instead */ +#define PMC_SLPWK_DR0_PID28_Pos 28 /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID28_Pos) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID28 PMC_SLPWK_DR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID28_Msk instead */ +#define PMC_SLPWK_DR0_PID29_Pos 29 /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID29_Pos) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID29 PMC_SLPWK_DR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID29_Msk instead */ +#define PMC_SLPWK_DR0_PID30_Pos 30 /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID30_Pos) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID30 PMC_SLPWK_DR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID30_Msk instead */ +#define PMC_SLPWK_DR0_PID31_Pos 31 /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID31_Pos) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID31 PMC_SLPWK_DR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR0_PID31_Msk instead */ +#define PMC_SLPWK_DR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_DR0) Register MASK (Use PMC_SLPWK_DR0_Msk instead) */ +#define PMC_SLPWK_DR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_DR0) Register Mask */ + +#define PMC_SLPWK_DR0_PID_Pos 7 /**< (PMC_SLPWK_DR0 Position) Peripheral 3x SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR0_PID_Pos) /**< (PMC_SLPWK_DR0 Mask) PID */ +#define PMC_SLPWK_DR0_PID(value) (PMC_SLPWK_DR0_PID_Msk & ((value) << PMC_SLPWK_DR0_PID_Pos)) + +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11c) (R/ 32) SleepWalking Status Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral 7 SleepWalking Status */ + uint32_t PID8:1; /**< bit: 8 Peripheral 8 SleepWalking Status */ + uint32_t PID9:1; /**< bit: 9 Peripheral 9 SleepWalking Status */ + uint32_t PID10:1; /**< bit: 10 Peripheral 10 SleepWalking Status */ + uint32_t PID11:1; /**< bit: 11 Peripheral 11 SleepWalking Status */ + uint32_t PID12:1; /**< bit: 12 Peripheral 12 SleepWalking Status */ + uint32_t PID13:1; /**< bit: 13 Peripheral 13 SleepWalking Status */ + uint32_t PID14:1; /**< bit: 14 Peripheral 14 SleepWalking Status */ + uint32_t PID15:1; /**< bit: 15 Peripheral 15 SleepWalking Status */ + uint32_t PID16:1; /**< bit: 16 Peripheral 16 SleepWalking Status */ + uint32_t PID17:1; /**< bit: 17 Peripheral 17 SleepWalking Status */ + uint32_t PID18:1; /**< bit: 18 Peripheral 18 SleepWalking Status */ + uint32_t PID19:1; /**< bit: 19 Peripheral 19 SleepWalking Status */ + uint32_t PID20:1; /**< bit: 20 Peripheral 20 SleepWalking Status */ + uint32_t PID21:1; /**< bit: 21 Peripheral 21 SleepWalking Status */ + uint32_t PID22:1; /**< bit: 22 Peripheral 22 SleepWalking Status */ + uint32_t PID23:1; /**< bit: 23 Peripheral 23 SleepWalking Status */ + uint32_t PID24:1; /**< bit: 24 Peripheral 24 SleepWalking Status */ + uint32_t PID25:1; /**< bit: 25 Peripheral 25 SleepWalking Status */ + uint32_t PID26:1; /**< bit: 26 Peripheral 26 SleepWalking Status */ + uint32_t PID27:1; /**< bit: 27 Peripheral 27 SleepWalking Status */ + uint32_t PID28:1; /**< bit: 28 Peripheral 28 SleepWalking Status */ + uint32_t PID29:1; /**< bit: 29 Peripheral 29 SleepWalking Status */ + uint32_t PID30:1; /**< bit: 30 Peripheral 30 SleepWalking Status */ + uint32_t PID31:1; /**< bit: 31 Peripheral 31 SleepWalking Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral 3x SleepWalking Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_SR0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_SR0_OFFSET (0x11C) /**< (PMC_SLPWK_SR0) SleepWalking Status Register 0 Offset */ + +#define PMC_SLPWK_SR0_PID7_Pos 7 /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID7_Pos) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID7 PMC_SLPWK_SR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID7_Msk instead */ +#define PMC_SLPWK_SR0_PID8_Pos 8 /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID8_Pos) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID8 PMC_SLPWK_SR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID8_Msk instead */ +#define PMC_SLPWK_SR0_PID9_Pos 9 /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID9_Pos) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID9 PMC_SLPWK_SR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID9_Msk instead */ +#define PMC_SLPWK_SR0_PID10_Pos 10 /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID10_Pos) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID10 PMC_SLPWK_SR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID10_Msk instead */ +#define PMC_SLPWK_SR0_PID11_Pos 11 /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID11_Pos) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID11 PMC_SLPWK_SR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID11_Msk instead */ +#define PMC_SLPWK_SR0_PID12_Pos 12 /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID12_Pos) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID12 PMC_SLPWK_SR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID12_Msk instead */ +#define PMC_SLPWK_SR0_PID13_Pos 13 /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID13_Pos) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID13 PMC_SLPWK_SR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID13_Msk instead */ +#define PMC_SLPWK_SR0_PID14_Pos 14 /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID14_Pos) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID14 PMC_SLPWK_SR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID14_Msk instead */ +#define PMC_SLPWK_SR0_PID15_Pos 15 /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID15_Pos) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID15 PMC_SLPWK_SR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID15_Msk instead */ +#define PMC_SLPWK_SR0_PID16_Pos 16 /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID16_Pos) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID16 PMC_SLPWK_SR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID16_Msk instead */ +#define PMC_SLPWK_SR0_PID17_Pos 17 /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID17_Pos) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID17 PMC_SLPWK_SR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID17_Msk instead */ +#define PMC_SLPWK_SR0_PID18_Pos 18 /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID18_Pos) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID18 PMC_SLPWK_SR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID18_Msk instead */ +#define PMC_SLPWK_SR0_PID19_Pos 19 /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID19_Pos) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID19 PMC_SLPWK_SR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID19_Msk instead */ +#define PMC_SLPWK_SR0_PID20_Pos 20 /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID20_Pos) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID20 PMC_SLPWK_SR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID20_Msk instead */ +#define PMC_SLPWK_SR0_PID21_Pos 21 /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID21_Pos) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID21 PMC_SLPWK_SR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID21_Msk instead */ +#define PMC_SLPWK_SR0_PID22_Pos 22 /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID22_Pos) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID22 PMC_SLPWK_SR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID22_Msk instead */ +#define PMC_SLPWK_SR0_PID23_Pos 23 /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID23_Pos) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID23 PMC_SLPWK_SR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID23_Msk instead */ +#define PMC_SLPWK_SR0_PID24_Pos 24 /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID24_Pos) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID24 PMC_SLPWK_SR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID24_Msk instead */ +#define PMC_SLPWK_SR0_PID25_Pos 25 /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID25_Pos) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID25 PMC_SLPWK_SR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID25_Msk instead */ +#define PMC_SLPWK_SR0_PID26_Pos 26 /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID26_Pos) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID26 PMC_SLPWK_SR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID26_Msk instead */ +#define PMC_SLPWK_SR0_PID27_Pos 27 /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID27_Pos) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID27 PMC_SLPWK_SR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID27_Msk instead */ +#define PMC_SLPWK_SR0_PID28_Pos 28 /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID28_Pos) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID28 PMC_SLPWK_SR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID28_Msk instead */ +#define PMC_SLPWK_SR0_PID29_Pos 29 /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID29_Pos) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID29 PMC_SLPWK_SR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID29_Msk instead */ +#define PMC_SLPWK_SR0_PID30_Pos 30 /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID30_Pos) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID30 PMC_SLPWK_SR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID30_Msk instead */ +#define PMC_SLPWK_SR0_PID31_Pos 31 /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID31_Pos) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID31 PMC_SLPWK_SR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR0_PID31_Msk instead */ +#define PMC_SLPWK_SR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_SR0) Register MASK (Use PMC_SLPWK_SR0_Msk instead) */ +#define PMC_SLPWK_SR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_SR0) Register Mask */ + +#define PMC_SLPWK_SR0_PID_Pos 7 /**< (PMC_SLPWK_SR0 Position) Peripheral 3x SleepWalking Status */ +#define PMC_SLPWK_SR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR0_PID_Pos) /**< (PMC_SLPWK_SR0 Mask) PID */ +#define PMC_SLPWK_SR0_PID(value) (PMC_SLPWK_SR0_PID_Msk & ((value) << PMC_SLPWK_SR0_PID_Pos)) + +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) (R/ 32) SleepWalking Activity Status Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID7:1; /**< bit: 7 Peripheral 7 Activity Status */ + uint32_t PID8:1; /**< bit: 8 Peripheral 8 Activity Status */ + uint32_t PID9:1; /**< bit: 9 Peripheral 9 Activity Status */ + uint32_t PID10:1; /**< bit: 10 Peripheral 10 Activity Status */ + uint32_t PID11:1; /**< bit: 11 Peripheral 11 Activity Status */ + uint32_t PID12:1; /**< bit: 12 Peripheral 12 Activity Status */ + uint32_t PID13:1; /**< bit: 13 Peripheral 13 Activity Status */ + uint32_t PID14:1; /**< bit: 14 Peripheral 14 Activity Status */ + uint32_t PID15:1; /**< bit: 15 Peripheral 15 Activity Status */ + uint32_t PID16:1; /**< bit: 16 Peripheral 16 Activity Status */ + uint32_t PID17:1; /**< bit: 17 Peripheral 17 Activity Status */ + uint32_t PID18:1; /**< bit: 18 Peripheral 18 Activity Status */ + uint32_t PID19:1; /**< bit: 19 Peripheral 19 Activity Status */ + uint32_t PID20:1; /**< bit: 20 Peripheral 20 Activity Status */ + uint32_t PID21:1; /**< bit: 21 Peripheral 21 Activity Status */ + uint32_t PID22:1; /**< bit: 22 Peripheral 22 Activity Status */ + uint32_t PID23:1; /**< bit: 23 Peripheral 23 Activity Status */ + uint32_t PID24:1; /**< bit: 24 Peripheral 24 Activity Status */ + uint32_t PID25:1; /**< bit: 25 Peripheral 25 Activity Status */ + uint32_t PID26:1; /**< bit: 26 Peripheral 26 Activity Status */ + uint32_t PID27:1; /**< bit: 27 Peripheral 27 Activity Status */ + uint32_t PID28:1; /**< bit: 28 Peripheral 28 Activity Status */ + uint32_t PID29:1; /**< bit: 29 Peripheral 29 Activity Status */ + uint32_t PID30:1; /**< bit: 30 Peripheral 30 Activity Status */ + uint32_t PID31:1; /**< bit: 31 Peripheral 31 Activity Status */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :7; /**< bit: 0..6 Reserved */ + uint32_t PID:25; /**< bit: 7..31 Peripheral 3x Activity Status */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_ASR0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_ASR0_OFFSET (0x120) /**< (PMC_SLPWK_ASR0) SleepWalking Activity Status Register 0 Offset */ + +#define PMC_SLPWK_ASR0_PID7_Pos 7 /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID7_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID7 PMC_SLPWK_ASR0_PID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID7_Msk instead */ +#define PMC_SLPWK_ASR0_PID8_Pos 8 /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID8_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID8 PMC_SLPWK_ASR0_PID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID8_Msk instead */ +#define PMC_SLPWK_ASR0_PID9_Pos 9 /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID9_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID9 PMC_SLPWK_ASR0_PID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID9_Msk instead */ +#define PMC_SLPWK_ASR0_PID10_Pos 10 /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID10_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID10 PMC_SLPWK_ASR0_PID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID10_Msk instead */ +#define PMC_SLPWK_ASR0_PID11_Pos 11 /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID11_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID11 PMC_SLPWK_ASR0_PID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID11_Msk instead */ +#define PMC_SLPWK_ASR0_PID12_Pos 12 /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID12_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID12 PMC_SLPWK_ASR0_PID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID12_Msk instead */ +#define PMC_SLPWK_ASR0_PID13_Pos 13 /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID13_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID13 PMC_SLPWK_ASR0_PID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID13_Msk instead */ +#define PMC_SLPWK_ASR0_PID14_Pos 14 /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID14_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID14 PMC_SLPWK_ASR0_PID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID14_Msk instead */ +#define PMC_SLPWK_ASR0_PID15_Pos 15 /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID15_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID15 PMC_SLPWK_ASR0_PID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID15_Msk instead */ +#define PMC_SLPWK_ASR0_PID16_Pos 16 /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID16_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID16 PMC_SLPWK_ASR0_PID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID16_Msk instead */ +#define PMC_SLPWK_ASR0_PID17_Pos 17 /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID17_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID17 PMC_SLPWK_ASR0_PID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID17_Msk instead */ +#define PMC_SLPWK_ASR0_PID18_Pos 18 /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID18_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID18 PMC_SLPWK_ASR0_PID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID18_Msk instead */ +#define PMC_SLPWK_ASR0_PID19_Pos 19 /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID19_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID19 PMC_SLPWK_ASR0_PID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID19_Msk instead */ +#define PMC_SLPWK_ASR0_PID20_Pos 20 /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID20_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID20 PMC_SLPWK_ASR0_PID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID20_Msk instead */ +#define PMC_SLPWK_ASR0_PID21_Pos 21 /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID21_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID21 PMC_SLPWK_ASR0_PID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID21_Msk instead */ +#define PMC_SLPWK_ASR0_PID22_Pos 22 /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID22_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID22 PMC_SLPWK_ASR0_PID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID22_Msk instead */ +#define PMC_SLPWK_ASR0_PID23_Pos 23 /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID23_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID23 PMC_SLPWK_ASR0_PID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID23_Msk instead */ +#define PMC_SLPWK_ASR0_PID24_Pos 24 /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID24_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID24 PMC_SLPWK_ASR0_PID24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID24_Msk instead */ +#define PMC_SLPWK_ASR0_PID25_Pos 25 /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID25_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID25 PMC_SLPWK_ASR0_PID25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID25_Msk instead */ +#define PMC_SLPWK_ASR0_PID26_Pos 26 /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID26_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID26 PMC_SLPWK_ASR0_PID26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID26_Msk instead */ +#define PMC_SLPWK_ASR0_PID27_Pos 27 /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID27_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID27 PMC_SLPWK_ASR0_PID27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID27_Msk instead */ +#define PMC_SLPWK_ASR0_PID28_Pos 28 /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID28_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID28 PMC_SLPWK_ASR0_PID28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID28_Msk instead */ +#define PMC_SLPWK_ASR0_PID29_Pos 29 /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID29_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID29 PMC_SLPWK_ASR0_PID29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID29_Msk instead */ +#define PMC_SLPWK_ASR0_PID30_Pos 30 /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID30_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID30 PMC_SLPWK_ASR0_PID30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID30_Msk instead */ +#define PMC_SLPWK_ASR0_PID31_Pos 31 /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID31_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID31 PMC_SLPWK_ASR0_PID31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR0_PID31_Msk instead */ +#define PMC_SLPWK_ASR0_MASK _U_(0xFFFFFF80) /**< \deprecated (PMC_SLPWK_ASR0) Register MASK (Use PMC_SLPWK_ASR0_Msk instead) */ +#define PMC_SLPWK_ASR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ASR0) Register Mask */ + +#define PMC_SLPWK_ASR0_PID_Pos 7 /**< (PMC_SLPWK_ASR0 Position) Peripheral 3x Activity Status */ +#define PMC_SLPWK_ASR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR0_PID_Pos) /**< (PMC_SLPWK_ASR0 Mask) PID */ +#define PMC_SLPWK_ASR0_PID(value) (PMC_SLPWK_ASR0_PID_Msk & ((value) << PMC_SLPWK_ASR0_PID_Pos)) + +/* -------- PMC_PMMR : (PMC Offset: 0x130) (R/W 32) PLL Maximum Multiplier Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PLLA_MMAX:11; /**< bit: 0..10 PLLA Maximum Allowed Multiplier Value */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_PMMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_PMMR_OFFSET (0x130) /**< (PMC_PMMR) PLL Maximum Multiplier Value Register Offset */ + +#define PMC_PMMR_PLLA_MMAX_Pos 0 /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Position */ +#define PMC_PMMR_PLLA_MMAX_Msk (_U_(0x7FF) << PMC_PMMR_PLLA_MMAX_Pos) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Mask */ +#define PMC_PMMR_PLLA_MMAX(value) (PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)) +#define PMC_PMMR_MASK _U_(0x7FF) /**< \deprecated (PMC_PMMR) Register MASK (Use PMC_PMMR_Msk instead) */ +#define PMC_PMMR_Msk _U_(0x7FF) /**< (PMC_PMMR) Register Mask */ + + +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x134) (/W 32) SleepWalking Enable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Enable */ + uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Enable */ + uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Enable */ + uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Enable */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Enable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Enable */ + uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Enable */ + uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Enable */ + uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Enable */ + uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Enable */ + uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Enable */ + uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Enable */ + uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Enable */ + uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Enable */ + uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Enable */ + uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Enable */ + uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Enable */ + uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Enable */ + uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Enable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Enable */ + uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Enable */ + uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Enable */ + uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Enable */ + uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Enable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral 6x SleepWalking Enable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_ER1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_ER1_OFFSET (0x134) /**< (PMC_SLPWK_ER1) SleepWalking Enable Register 1 Offset */ + +#define PMC_SLPWK_ER1_PID32_Pos 0 /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID32_Pos) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID32 PMC_SLPWK_ER1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID32_Msk instead */ +#define PMC_SLPWK_ER1_PID33_Pos 1 /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID33_Pos) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID33 PMC_SLPWK_ER1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID33_Msk instead */ +#define PMC_SLPWK_ER1_PID34_Pos 2 /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID34_Pos) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID34 PMC_SLPWK_ER1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID34_Msk instead */ +#define PMC_SLPWK_ER1_PID35_Pos 3 /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID35_Pos) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID35 PMC_SLPWK_ER1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID35_Msk instead */ +#define PMC_SLPWK_ER1_PID37_Pos 5 /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID37_Pos) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID37 PMC_SLPWK_ER1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID37_Msk instead */ +#define PMC_SLPWK_ER1_PID39_Pos 7 /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID39_Pos) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID39 PMC_SLPWK_ER1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID39_Msk instead */ +#define PMC_SLPWK_ER1_PID40_Pos 8 /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID40_Pos) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID40 PMC_SLPWK_ER1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID40_Msk instead */ +#define PMC_SLPWK_ER1_PID41_Pos 9 /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID41_Pos) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID41 PMC_SLPWK_ER1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID41_Msk instead */ +#define PMC_SLPWK_ER1_PID42_Pos 10 /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID42_Pos) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID42 PMC_SLPWK_ER1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID42_Msk instead */ +#define PMC_SLPWK_ER1_PID43_Pos 11 /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID43_Pos) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID43 PMC_SLPWK_ER1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID43_Msk instead */ +#define PMC_SLPWK_ER1_PID44_Pos 12 /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID44_Pos) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID44 PMC_SLPWK_ER1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID44_Msk instead */ +#define PMC_SLPWK_ER1_PID45_Pos 13 /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID45_Pos) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID45 PMC_SLPWK_ER1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID45_Msk instead */ +#define PMC_SLPWK_ER1_PID46_Pos 14 /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID46_Pos) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID46 PMC_SLPWK_ER1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID46_Msk instead */ +#define PMC_SLPWK_ER1_PID47_Pos 15 /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID47_Pos) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID47 PMC_SLPWK_ER1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID47_Msk instead */ +#define PMC_SLPWK_ER1_PID48_Pos 16 /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID48_Pos) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID48 PMC_SLPWK_ER1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID48_Msk instead */ +#define PMC_SLPWK_ER1_PID49_Pos 17 /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID49_Pos) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID49 PMC_SLPWK_ER1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID49_Msk instead */ +#define PMC_SLPWK_ER1_PID50_Pos 18 /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID50_Pos) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID50 PMC_SLPWK_ER1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID50_Msk instead */ +#define PMC_SLPWK_ER1_PID51_Pos 19 /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID51_Pos) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID51 PMC_SLPWK_ER1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID51_Msk instead */ +#define PMC_SLPWK_ER1_PID52_Pos 20 /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID52_Pos) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID52 PMC_SLPWK_ER1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID52_Msk instead */ +#define PMC_SLPWK_ER1_PID56_Pos 24 /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID56_Pos) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID56 PMC_SLPWK_ER1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID56_Msk instead */ +#define PMC_SLPWK_ER1_PID57_Pos 25 /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID57_Pos) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID57 PMC_SLPWK_ER1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID57_Msk instead */ +#define PMC_SLPWK_ER1_PID58_Pos 26 /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID58_Pos) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID58 PMC_SLPWK_ER1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID58_Msk instead */ +#define PMC_SLPWK_ER1_PID59_Pos 27 /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID59_Pos) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID59 PMC_SLPWK_ER1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID59_Msk instead */ +#define PMC_SLPWK_ER1_PID60_Pos 28 /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID60_Pos) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID60 PMC_SLPWK_ER1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ER1_PID60_Msk instead */ +#define PMC_SLPWK_ER1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_SLPWK_ER1) Register MASK (Use PMC_SLPWK_ER1_Msk instead) */ +#define PMC_SLPWK_ER1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_ER1) Register Mask */ + +#define PMC_SLPWK_ER1_PID_Pos 0 /**< (PMC_SLPWK_ER1 Position) Peripheral 6x SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_ER1_PID_Pos) /**< (PMC_SLPWK_ER1 Mask) PID */ +#define PMC_SLPWK_ER1_PID(value) (PMC_SLPWK_ER1_PID_Msk & ((value) << PMC_SLPWK_ER1_PID_Pos)) + +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x138) (/W 32) SleepWalking Disable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Disable */ + uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Disable */ + uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Disable */ + uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Disable */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Disable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Disable */ + uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Disable */ + uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Disable */ + uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Disable */ + uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Disable */ + uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Disable */ + uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Disable */ + uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Disable */ + uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Disable */ + uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Disable */ + uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Disable */ + uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Disable */ + uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Disable */ + uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Disable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Disable */ + uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Disable */ + uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Disable */ + uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Disable */ + uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Disable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral 6x SleepWalking Disable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_DR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_DR1_OFFSET (0x138) /**< (PMC_SLPWK_DR1) SleepWalking Disable Register 1 Offset */ + +#define PMC_SLPWK_DR1_PID32_Pos 0 /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID32_Pos) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID32 PMC_SLPWK_DR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID32_Msk instead */ +#define PMC_SLPWK_DR1_PID33_Pos 1 /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID33_Pos) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID33 PMC_SLPWK_DR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID33_Msk instead */ +#define PMC_SLPWK_DR1_PID34_Pos 2 /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID34_Pos) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID34 PMC_SLPWK_DR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID34_Msk instead */ +#define PMC_SLPWK_DR1_PID35_Pos 3 /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID35_Pos) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID35 PMC_SLPWK_DR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID35_Msk instead */ +#define PMC_SLPWK_DR1_PID37_Pos 5 /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID37_Pos) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID37 PMC_SLPWK_DR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID37_Msk instead */ +#define PMC_SLPWK_DR1_PID39_Pos 7 /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID39_Pos) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID39 PMC_SLPWK_DR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID39_Msk instead */ +#define PMC_SLPWK_DR1_PID40_Pos 8 /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID40_Pos) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID40 PMC_SLPWK_DR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID40_Msk instead */ +#define PMC_SLPWK_DR1_PID41_Pos 9 /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID41_Pos) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID41 PMC_SLPWK_DR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID41_Msk instead */ +#define PMC_SLPWK_DR1_PID42_Pos 10 /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID42_Pos) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID42 PMC_SLPWK_DR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID42_Msk instead */ +#define PMC_SLPWK_DR1_PID43_Pos 11 /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID43_Pos) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID43 PMC_SLPWK_DR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID43_Msk instead */ +#define PMC_SLPWK_DR1_PID44_Pos 12 /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID44_Pos) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID44 PMC_SLPWK_DR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID44_Msk instead */ +#define PMC_SLPWK_DR1_PID45_Pos 13 /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID45_Pos) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID45 PMC_SLPWK_DR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID45_Msk instead */ +#define PMC_SLPWK_DR1_PID46_Pos 14 /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID46_Pos) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID46 PMC_SLPWK_DR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID46_Msk instead */ +#define PMC_SLPWK_DR1_PID47_Pos 15 /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID47_Pos) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID47 PMC_SLPWK_DR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID47_Msk instead */ +#define PMC_SLPWK_DR1_PID48_Pos 16 /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID48_Pos) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID48 PMC_SLPWK_DR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID48_Msk instead */ +#define PMC_SLPWK_DR1_PID49_Pos 17 /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID49_Pos) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID49 PMC_SLPWK_DR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID49_Msk instead */ +#define PMC_SLPWK_DR1_PID50_Pos 18 /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID50_Pos) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID50 PMC_SLPWK_DR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID50_Msk instead */ +#define PMC_SLPWK_DR1_PID51_Pos 19 /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID51_Pos) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID51 PMC_SLPWK_DR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID51_Msk instead */ +#define PMC_SLPWK_DR1_PID52_Pos 20 /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID52_Pos) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID52 PMC_SLPWK_DR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID52_Msk instead */ +#define PMC_SLPWK_DR1_PID56_Pos 24 /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID56_Pos) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID56 PMC_SLPWK_DR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID56_Msk instead */ +#define PMC_SLPWK_DR1_PID57_Pos 25 /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID57_Pos) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID57 PMC_SLPWK_DR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID57_Msk instead */ +#define PMC_SLPWK_DR1_PID58_Pos 26 /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID58_Pos) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID58 PMC_SLPWK_DR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID58_Msk instead */ +#define PMC_SLPWK_DR1_PID59_Pos 27 /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID59_Pos) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID59 PMC_SLPWK_DR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID59_Msk instead */ +#define PMC_SLPWK_DR1_PID60_Pos 28 /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID60_Pos) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID60 PMC_SLPWK_DR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_DR1_PID60_Msk instead */ +#define PMC_SLPWK_DR1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_SLPWK_DR1) Register MASK (Use PMC_SLPWK_DR1_Msk instead) */ +#define PMC_SLPWK_DR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_DR1) Register Mask */ + +#define PMC_SLPWK_DR1_PID_Pos 0 /**< (PMC_SLPWK_DR1 Position) Peripheral 6x SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_DR1_PID_Pos) /**< (PMC_SLPWK_DR1 Mask) PID */ +#define PMC_SLPWK_DR1_PID(value) (PMC_SLPWK_DR1_PID_Msk & ((value) << PMC_SLPWK_DR1_PID_Pos)) + +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x13c) (R/ 32) SleepWalking Status Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral 32 SleepWalking Status */ + uint32_t PID33:1; /**< bit: 1 Peripheral 33 SleepWalking Status */ + uint32_t PID34:1; /**< bit: 2 Peripheral 34 SleepWalking Status */ + uint32_t PID35:1; /**< bit: 3 Peripheral 35 SleepWalking Status */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral 37 SleepWalking Status */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral 39 SleepWalking Status */ + uint32_t PID40:1; /**< bit: 8 Peripheral 40 SleepWalking Status */ + uint32_t PID41:1; /**< bit: 9 Peripheral 41 SleepWalking Status */ + uint32_t PID42:1; /**< bit: 10 Peripheral 42 SleepWalking Status */ + uint32_t PID43:1; /**< bit: 11 Peripheral 43 SleepWalking Status */ + uint32_t PID44:1; /**< bit: 12 Peripheral 44 SleepWalking Status */ + uint32_t PID45:1; /**< bit: 13 Peripheral 45 SleepWalking Status */ + uint32_t PID46:1; /**< bit: 14 Peripheral 46 SleepWalking Status */ + uint32_t PID47:1; /**< bit: 15 Peripheral 47 SleepWalking Status */ + uint32_t PID48:1; /**< bit: 16 Peripheral 48 SleepWalking Status */ + uint32_t PID49:1; /**< bit: 17 Peripheral 49 SleepWalking Status */ + uint32_t PID50:1; /**< bit: 18 Peripheral 50 SleepWalking Status */ + uint32_t PID51:1; /**< bit: 19 Peripheral 51 SleepWalking Status */ + uint32_t PID52:1; /**< bit: 20 Peripheral 52 SleepWalking Status */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral 56 SleepWalking Status */ + uint32_t PID57:1; /**< bit: 25 Peripheral 57 SleepWalking Status */ + uint32_t PID58:1; /**< bit: 26 Peripheral 58 SleepWalking Status */ + uint32_t PID59:1; /**< bit: 27 Peripheral 59 SleepWalking Status */ + uint32_t PID60:1; /**< bit: 28 Peripheral 60 SleepWalking Status */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral 6x SleepWalking Status */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_SR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_SR1_OFFSET (0x13C) /**< (PMC_SLPWK_SR1) SleepWalking Status Register 1 Offset */ + +#define PMC_SLPWK_SR1_PID32_Pos 0 /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID32_Pos) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID32 PMC_SLPWK_SR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID32_Msk instead */ +#define PMC_SLPWK_SR1_PID33_Pos 1 /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID33_Pos) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID33 PMC_SLPWK_SR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID33_Msk instead */ +#define PMC_SLPWK_SR1_PID34_Pos 2 /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID34_Pos) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID34 PMC_SLPWK_SR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID34_Msk instead */ +#define PMC_SLPWK_SR1_PID35_Pos 3 /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID35_Pos) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID35 PMC_SLPWK_SR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID35_Msk instead */ +#define PMC_SLPWK_SR1_PID37_Pos 5 /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID37_Pos) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID37 PMC_SLPWK_SR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID37_Msk instead */ +#define PMC_SLPWK_SR1_PID39_Pos 7 /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID39_Pos) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID39 PMC_SLPWK_SR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID39_Msk instead */ +#define PMC_SLPWK_SR1_PID40_Pos 8 /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID40_Pos) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID40 PMC_SLPWK_SR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID40_Msk instead */ +#define PMC_SLPWK_SR1_PID41_Pos 9 /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID41_Pos) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID41 PMC_SLPWK_SR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID41_Msk instead */ +#define PMC_SLPWK_SR1_PID42_Pos 10 /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID42_Pos) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID42 PMC_SLPWK_SR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID42_Msk instead */ +#define PMC_SLPWK_SR1_PID43_Pos 11 /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID43_Pos) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID43 PMC_SLPWK_SR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID43_Msk instead */ +#define PMC_SLPWK_SR1_PID44_Pos 12 /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID44_Pos) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID44 PMC_SLPWK_SR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID44_Msk instead */ +#define PMC_SLPWK_SR1_PID45_Pos 13 /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID45_Pos) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID45 PMC_SLPWK_SR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID45_Msk instead */ +#define PMC_SLPWK_SR1_PID46_Pos 14 /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID46_Pos) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID46 PMC_SLPWK_SR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID46_Msk instead */ +#define PMC_SLPWK_SR1_PID47_Pos 15 /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID47_Pos) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID47 PMC_SLPWK_SR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID47_Msk instead */ +#define PMC_SLPWK_SR1_PID48_Pos 16 /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID48_Pos) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID48 PMC_SLPWK_SR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID48_Msk instead */ +#define PMC_SLPWK_SR1_PID49_Pos 17 /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID49_Pos) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID49 PMC_SLPWK_SR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID49_Msk instead */ +#define PMC_SLPWK_SR1_PID50_Pos 18 /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID50_Pos) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID50 PMC_SLPWK_SR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID50_Msk instead */ +#define PMC_SLPWK_SR1_PID51_Pos 19 /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID51_Pos) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID51 PMC_SLPWK_SR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID51_Msk instead */ +#define PMC_SLPWK_SR1_PID52_Pos 20 /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID52_Pos) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID52 PMC_SLPWK_SR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID52_Msk instead */ +#define PMC_SLPWK_SR1_PID56_Pos 24 /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID56_Pos) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID56 PMC_SLPWK_SR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID56_Msk instead */ +#define PMC_SLPWK_SR1_PID57_Pos 25 /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID57_Pos) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID57 PMC_SLPWK_SR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID57_Msk instead */ +#define PMC_SLPWK_SR1_PID58_Pos 26 /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID58_Pos) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID58 PMC_SLPWK_SR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID58_Msk instead */ +#define PMC_SLPWK_SR1_PID59_Pos 27 /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID59_Pos) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID59 PMC_SLPWK_SR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID59_Msk instead */ +#define PMC_SLPWK_SR1_PID60_Pos 28 /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID60_Pos) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID60 PMC_SLPWK_SR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_SR1_PID60_Msk instead */ +#define PMC_SLPWK_SR1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_SLPWK_SR1) Register MASK (Use PMC_SLPWK_SR1_Msk instead) */ +#define PMC_SLPWK_SR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_SR1) Register Mask */ + +#define PMC_SLPWK_SR1_PID_Pos 0 /**< (PMC_SLPWK_SR1 Position) Peripheral 6x SleepWalking Status */ +#define PMC_SLPWK_SR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_SR1_PID_Pos) /**< (PMC_SLPWK_SR1 Mask) PID */ +#define PMC_SLPWK_SR1_PID(value) (PMC_SLPWK_SR1_PID_Msk & ((value) << PMC_SLPWK_SR1_PID_Pos)) + +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x140) (R/ 32) SleepWalking Activity Status Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PID32:1; /**< bit: 0 Peripheral 32 Activity Status */ + uint32_t PID33:1; /**< bit: 1 Peripheral 33 Activity Status */ + uint32_t PID34:1; /**< bit: 2 Peripheral 34 Activity Status */ + uint32_t PID35:1; /**< bit: 3 Peripheral 35 Activity Status */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t PID37:1; /**< bit: 5 Peripheral 37 Activity Status */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t PID39:1; /**< bit: 7 Peripheral 39 Activity Status */ + uint32_t PID40:1; /**< bit: 8 Peripheral 40 Activity Status */ + uint32_t PID41:1; /**< bit: 9 Peripheral 41 Activity Status */ + uint32_t PID42:1; /**< bit: 10 Peripheral 42 Activity Status */ + uint32_t PID43:1; /**< bit: 11 Peripheral 43 Activity Status */ + uint32_t PID44:1; /**< bit: 12 Peripheral 44 Activity Status */ + uint32_t PID45:1; /**< bit: 13 Peripheral 45 Activity Status */ + uint32_t PID46:1; /**< bit: 14 Peripheral 46 Activity Status */ + uint32_t PID47:1; /**< bit: 15 Peripheral 47 Activity Status */ + uint32_t PID48:1; /**< bit: 16 Peripheral 48 Activity Status */ + uint32_t PID49:1; /**< bit: 17 Peripheral 49 Activity Status */ + uint32_t PID50:1; /**< bit: 18 Peripheral 50 Activity Status */ + uint32_t PID51:1; /**< bit: 19 Peripheral 51 Activity Status */ + uint32_t PID52:1; /**< bit: 20 Peripheral 52 Activity Status */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PID56:1; /**< bit: 24 Peripheral 56 Activity Status */ + uint32_t PID57:1; /**< bit: 25 Peripheral 57 Activity Status */ + uint32_t PID58:1; /**< bit: 26 Peripheral 58 Activity Status */ + uint32_t PID59:1; /**< bit: 27 Peripheral 59 Activity Status */ + uint32_t PID60:1; /**< bit: 28 Peripheral 60 Activity Status */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PID:24; /**< bit: 0..23 Peripheral 6x Activity Status */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_ASR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_ASR1_OFFSET (0x140) /**< (PMC_SLPWK_ASR1) SleepWalking Activity Status Register 1 Offset */ + +#define PMC_SLPWK_ASR1_PID32_Pos 0 /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID32_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID32 PMC_SLPWK_ASR1_PID32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID32_Msk instead */ +#define PMC_SLPWK_ASR1_PID33_Pos 1 /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID33_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID33 PMC_SLPWK_ASR1_PID33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID33_Msk instead */ +#define PMC_SLPWK_ASR1_PID34_Pos 2 /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID34_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID34 PMC_SLPWK_ASR1_PID34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID34_Msk instead */ +#define PMC_SLPWK_ASR1_PID35_Pos 3 /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID35_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID35 PMC_SLPWK_ASR1_PID35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID35_Msk instead */ +#define PMC_SLPWK_ASR1_PID37_Pos 5 /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID37_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID37 PMC_SLPWK_ASR1_PID37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID37_Msk instead */ +#define PMC_SLPWK_ASR1_PID39_Pos 7 /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID39_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID39 PMC_SLPWK_ASR1_PID39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID39_Msk instead */ +#define PMC_SLPWK_ASR1_PID40_Pos 8 /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID40_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID40 PMC_SLPWK_ASR1_PID40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID40_Msk instead */ +#define PMC_SLPWK_ASR1_PID41_Pos 9 /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID41_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID41 PMC_SLPWK_ASR1_PID41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID41_Msk instead */ +#define PMC_SLPWK_ASR1_PID42_Pos 10 /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID42_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID42 PMC_SLPWK_ASR1_PID42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID42_Msk instead */ +#define PMC_SLPWK_ASR1_PID43_Pos 11 /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID43_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID43 PMC_SLPWK_ASR1_PID43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID43_Msk instead */ +#define PMC_SLPWK_ASR1_PID44_Pos 12 /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID44_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID44 PMC_SLPWK_ASR1_PID44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID44_Msk instead */ +#define PMC_SLPWK_ASR1_PID45_Pos 13 /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID45_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID45 PMC_SLPWK_ASR1_PID45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID45_Msk instead */ +#define PMC_SLPWK_ASR1_PID46_Pos 14 /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID46_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID46 PMC_SLPWK_ASR1_PID46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID46_Msk instead */ +#define PMC_SLPWK_ASR1_PID47_Pos 15 /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID47_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID47 PMC_SLPWK_ASR1_PID47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID47_Msk instead */ +#define PMC_SLPWK_ASR1_PID48_Pos 16 /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID48_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID48 PMC_SLPWK_ASR1_PID48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID48_Msk instead */ +#define PMC_SLPWK_ASR1_PID49_Pos 17 /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID49_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID49 PMC_SLPWK_ASR1_PID49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID49_Msk instead */ +#define PMC_SLPWK_ASR1_PID50_Pos 18 /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID50_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID50 PMC_SLPWK_ASR1_PID50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID50_Msk instead */ +#define PMC_SLPWK_ASR1_PID51_Pos 19 /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID51_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID51 PMC_SLPWK_ASR1_PID51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID51_Msk instead */ +#define PMC_SLPWK_ASR1_PID52_Pos 20 /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID52_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID52 PMC_SLPWK_ASR1_PID52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID52_Msk instead */ +#define PMC_SLPWK_ASR1_PID56_Pos 24 /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID56_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID56 PMC_SLPWK_ASR1_PID56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID56_Msk instead */ +#define PMC_SLPWK_ASR1_PID57_Pos 25 /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID57_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID57 PMC_SLPWK_ASR1_PID57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID57_Msk instead */ +#define PMC_SLPWK_ASR1_PID58_Pos 26 /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID58_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID58 PMC_SLPWK_ASR1_PID58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID58_Msk instead */ +#define PMC_SLPWK_ASR1_PID59_Pos 27 /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID59_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID59 PMC_SLPWK_ASR1_PID59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID59_Msk instead */ +#define PMC_SLPWK_ASR1_PID60_Pos 28 /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID60_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID60 PMC_SLPWK_ASR1_PID60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_ASR1_PID60_Msk instead */ +#define PMC_SLPWK_ASR1_MASK _U_(0x1F1FFFAF) /**< \deprecated (PMC_SLPWK_ASR1) Register MASK (Use PMC_SLPWK_ASR1_Msk instead) */ +#define PMC_SLPWK_ASR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_ASR1) Register Mask */ + +#define PMC_SLPWK_ASR1_PID_Pos 0 /**< (PMC_SLPWK_ASR1 Position) Peripheral 6x Activity Status */ +#define PMC_SLPWK_ASR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_ASR1_PID_Pos) /**< (PMC_SLPWK_ASR1 Mask) PID */ +#define PMC_SLPWK_ASR1_PID(value) (PMC_SLPWK_ASR1_PID_Msk & ((value) << PMC_SLPWK_ASR1_PID_Pos)) + +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x144) (R/ 32) SleepWalking Activity In Progress Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t AIP:1; /**< bit: 0 Activity In Progress */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PMC_SLPWK_AIPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PMC_SLPWK_AIPR_OFFSET (0x144) /**< (PMC_SLPWK_AIPR) SleepWalking Activity In Progress Register Offset */ + +#define PMC_SLPWK_AIPR_AIP_Pos 0 /**< (PMC_SLPWK_AIPR) Activity In Progress Position */ +#define PMC_SLPWK_AIPR_AIP_Msk (_U_(0x1) << PMC_SLPWK_AIPR_AIP_Pos) /**< (PMC_SLPWK_AIPR) Activity In Progress Mask */ +#define PMC_SLPWK_AIPR_AIP PMC_SLPWK_AIPR_AIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PMC_SLPWK_AIPR_AIP_Msk instead */ +#define PMC_SLPWK_AIPR_MASK _U_(0x01) /**< \deprecated (PMC_SLPWK_AIPR) Register MASK (Use PMC_SLPWK_AIPR_Msk instead) */ +#define PMC_SLPWK_AIPR_Msk _U_(0x01) /**< (PMC_SLPWK_AIPR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief PMC hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< (PMC Offset: 0x00) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< (PMC Offset: 0x04) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< (PMC Offset: 0x08) System Clock Status Register */ + __I uint8_t Reserved1[4]; + __O uint32_t PMC_PCER0; /**< (PMC Offset: 0x10) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< (PMC Offset: 0x14) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< (PMC Offset: 0x18) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< (PMC Offset: 0x1C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< (PMC Offset: 0x20) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< (PMC Offset: 0x24) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< (PMC Offset: 0x28) PLLA Register */ + __I uint8_t Reserved2[4]; + __IO uint32_t PMC_MCKR; /**< (PMC Offset: 0x30) Master Clock Register */ + __I uint8_t Reserved3[4]; + __IO uint32_t PMC_USB; /**< (PMC Offset: 0x38) USB Clock Register */ + __I uint8_t Reserved4[4]; + __IO uint32_t PMC_PCK[8]; /**< (PMC Offset: 0x40) Programmable Clock Register */ + __O uint32_t PMC_IER; /**< (PMC Offset: 0x60) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< (PMC Offset: 0x64) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< (PMC Offset: 0x68) Status Register */ + __I uint32_t PMC_IMR; /**< (PMC Offset: 0x6C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< (PMC Offset: 0x70) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< (PMC Offset: 0x74) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< (PMC Offset: 0x78) Fault Output Clear Register */ + __I uint8_t Reserved5[104]; + __IO uint32_t PMC_WPMR; /**< (PMC Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< (PMC Offset: 0xE8) Write Protection Status Register */ + __I uint8_t Reserved6[20]; + __O uint32_t PMC_PCER1; /**< (PMC Offset: 0x100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< (PMC Offset: 0x104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< (PMC Offset: 0x108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< (PMC Offset: 0x10C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< (PMC Offset: 0x110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< (PMC Offset: 0x114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< (PMC Offset: 0x118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< (PMC Offset: 0x11C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< (PMC Offset: 0x120) SleepWalking Activity Status Register 0 */ + __I uint8_t Reserved7[12]; + __IO uint32_t PMC_PMMR; /**< (PMC Offset: 0x130) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< (PMC Offset: 0x134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< (PMC Offset: 0x138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< (PMC Offset: 0x13C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< (PMC Offset: 0x140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< (PMC Offset: 0x144) SleepWalking Activity In Progress Register */ +} Pmc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief PMC hardware registers */ +typedef struct { + __O PMC_SCER_Type PMC_SCER; /**< Offset: 0x00 ( /W 32) System Clock Enable Register */ + __O PMC_SCDR_Type PMC_SCDR; /**< Offset: 0x04 ( /W 32) System Clock Disable Register */ + __I PMC_SCSR_Type PMC_SCSR; /**< Offset: 0x08 (R/ 32) System Clock Status Register */ + __I uint8_t Reserved1[4]; + __O PMC_PCER0_Type PMC_PCER0; /**< Offset: 0x10 ( /W 32) Peripheral Clock Enable Register 0 */ + __O PMC_PCDR0_Type PMC_PCDR0; /**< Offset: 0x14 ( /W 32) Peripheral Clock Disable Register 0 */ + __I PMC_PCSR0_Type PMC_PCSR0; /**< Offset: 0x18 (R/ 32) Peripheral Clock Status Register 0 */ + __IO CKGR_UCKR_Type CKGR_UCKR; /**< Offset: 0x1C (R/W 32) UTMI Clock Register */ + __IO CKGR_MOR_Type CKGR_MOR; /**< Offset: 0x20 (R/W 32) Main Oscillator Register */ + __IO CKGR_MCFR_Type CKGR_MCFR; /**< Offset: 0x24 (R/W 32) Main Clock Frequency Register */ + __IO CKGR_PLLAR_Type CKGR_PLLAR; /**< Offset: 0x28 (R/W 32) PLLA Register */ + __I uint8_t Reserved2[4]; + __IO PMC_MCKR_Type PMC_MCKR; /**< Offset: 0x30 (R/W 32) Master Clock Register */ + __I uint8_t Reserved3[4]; + __IO PMC_USB_Type PMC_USB; /**< Offset: 0x38 (R/W 32) USB Clock Register */ + __I uint8_t Reserved4[4]; + __IO PMC_PCK_Type PMC_PCK[8]; /**< Offset: 0x40 (R/W 32) Programmable Clock Register */ + __O PMC_IER_Type PMC_IER; /**< Offset: 0x60 ( /W 32) Interrupt Enable Register */ + __O PMC_IDR_Type PMC_IDR; /**< Offset: 0x64 ( /W 32) Interrupt Disable Register */ + __I PMC_SR_Type PMC_SR; /**< Offset: 0x68 (R/ 32) Status Register */ + __I PMC_IMR_Type PMC_IMR; /**< Offset: 0x6C (R/ 32) Interrupt Mask Register */ + __IO PMC_FSMR_Type PMC_FSMR; /**< Offset: 0x70 (R/W 32) Fast Startup Mode Register */ + __IO PMC_FSPR_Type PMC_FSPR; /**< Offset: 0x74 (R/W 32) Fast Startup Polarity Register */ + __O PMC_FOCR_Type PMC_FOCR; /**< Offset: 0x78 ( /W 32) Fault Output Clear Register */ + __I uint8_t Reserved5[104]; + __IO PMC_WPMR_Type PMC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I PMC_WPSR_Type PMC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved6[20]; + __O PMC_PCER1_Type PMC_PCER1; /**< Offset: 0x100 ( /W 32) Peripheral Clock Enable Register 1 */ + __O PMC_PCDR1_Type PMC_PCDR1; /**< Offset: 0x104 ( /W 32) Peripheral Clock Disable Register 1 */ + __I PMC_PCSR1_Type PMC_PCSR1; /**< Offset: 0x108 (R/ 32) Peripheral Clock Status Register 1 */ + __IO PMC_PCR_Type PMC_PCR; /**< Offset: 0x10C (R/W 32) Peripheral Control Register */ + __IO PMC_OCR_Type PMC_OCR; /**< Offset: 0x110 (R/W 32) Oscillator Calibration Register */ + __O PMC_SLPWK_ER0_Type PMC_SLPWK_ER0; /**< Offset: 0x114 ( /W 32) SleepWalking Enable Register 0 */ + __O PMC_SLPWK_DR0_Type PMC_SLPWK_DR0; /**< Offset: 0x118 ( /W 32) SleepWalking Disable Register 0 */ + __I PMC_SLPWK_SR0_Type PMC_SLPWK_SR0; /**< Offset: 0x11C (R/ 32) SleepWalking Status Register 0 */ + __I PMC_SLPWK_ASR0_Type PMC_SLPWK_ASR0; /**< Offset: 0x120 (R/ 32) SleepWalking Activity Status Register 0 */ + __I uint8_t Reserved7[12]; + __IO PMC_PMMR_Type PMC_PMMR; /**< Offset: 0x130 (R/W 32) PLL Maximum Multiplier Value Register */ + __O PMC_SLPWK_ER1_Type PMC_SLPWK_ER1; /**< Offset: 0x134 ( /W 32) SleepWalking Enable Register 1 */ + __O PMC_SLPWK_DR1_Type PMC_SLPWK_DR1; /**< Offset: 0x138 ( /W 32) SleepWalking Disable Register 1 */ + __I PMC_SLPWK_SR1_Type PMC_SLPWK_SR1; /**< Offset: 0x13C (R/ 32) SleepWalking Status Register 1 */ + __I PMC_SLPWK_ASR1_Type PMC_SLPWK_ASR1; /**< Offset: 0x140 (R/ 32) SleepWalking Activity Status Register 1 */ + __I PMC_SLPWK_AIPR_Type PMC_SLPWK_AIPR; /**< Offset: 0x144 (R/ 32) SleepWalking Activity In Progress Register */ +} Pmc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Power Management Controller */ + +#endif /* _SAME70_PMC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/pwm.h b/bsp/microchip/same70/bsp/same70b/include/component/pwm.h new file mode 100644 index 0000000000..32a566d313 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/pwm.h @@ -0,0 +1,2873 @@ +/** + * \file + * + * \brief Component description for PWM + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PWM_COMPONENT_H_ +#define _SAME70_PWM_COMPONENT_H_ +#define _SAME70_PWM_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Pulse Width Modulation Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR PWM */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define PWM_6343 /**< (PWM) Module ID */ +#define REV_PWM Y /**< (PWM) Module revision */ + +/* -------- PWM_CMR : (PWM Offset: 0x00) (R/W 32) PWM Channel Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CPRE:4; /**< bit: 0..3 Channel Pre-scaler */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CALG:1; /**< bit: 8 Channel Alignment */ + uint32_t CPOL:1; /**< bit: 9 Channel Polarity */ + uint32_t CES:1; /**< bit: 10 Counter Event Selection */ + uint32_t UPDS:1; /**< bit: 11 Update Selection */ + uint32_t DPOLI:1; /**< bit: 12 Disabled Polarity Inverted */ + uint32_t TCTS:1; /**< bit: 13 Timer Counter Trigger Selection */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t DTE:1; /**< bit: 16 Dead-Time Generator Enable */ + uint32_t DTHI:1; /**< bit: 17 Dead-Time PWMHx Output Inverted */ + uint32_t DTLI:1; /**< bit: 18 Dead-Time PWMLx Output Inverted */ + uint32_t PPM:1; /**< bit: 19 Push-Pull Mode */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMR_OFFSET (0x00) /**< (PWM_CMR) PWM Channel Mode Register Offset */ + +#define PWM_CMR_CPRE_Pos 0 /**< (PWM_CMR) Channel Pre-scaler Position */ +#define PWM_CMR_CPRE_Msk (_U_(0xF) << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Channel Pre-scaler Mask */ +#define PWM_CMR_CPRE(value) (PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)) +#define PWM_CMR_CPRE_MCK_Val _U_(0x0) /**< (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2_Val _U_(0x1) /**< (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4_Val _U_(0x2) /**< (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8_Val _U_(0x3) /**< (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16_Val _U_(0x4) /**< (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32_Val _U_(0x5) /**< (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64_Val _U_(0x6) /**< (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128_Val _U_(0x7) /**< (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256_Val _U_(0x8) /**< (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512_Val _U_(0x9) /**< (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024_Val _U_(0xA) /**< (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA_Val _U_(0xB) /**< (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB_Val _U_(0xC) /**< (PWM_CMR) Clock B */ +#define PWM_CMR_CPRE_MCK (PWM_CMR_CPRE_MCK_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock Position */ +#define PWM_CMR_CPRE_MCK_DIV_2 (PWM_CMR_CPRE_MCK_DIV_2_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/2 Position */ +#define PWM_CMR_CPRE_MCK_DIV_4 (PWM_CMR_CPRE_MCK_DIV_4_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/4 Position */ +#define PWM_CMR_CPRE_MCK_DIV_8 (PWM_CMR_CPRE_MCK_DIV_8_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/8 Position */ +#define PWM_CMR_CPRE_MCK_DIV_16 (PWM_CMR_CPRE_MCK_DIV_16_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/16 Position */ +#define PWM_CMR_CPRE_MCK_DIV_32 (PWM_CMR_CPRE_MCK_DIV_32_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/32 Position */ +#define PWM_CMR_CPRE_MCK_DIV_64 (PWM_CMR_CPRE_MCK_DIV_64_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/64 Position */ +#define PWM_CMR_CPRE_MCK_DIV_128 (PWM_CMR_CPRE_MCK_DIV_128_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/128 Position */ +#define PWM_CMR_CPRE_MCK_DIV_256 (PWM_CMR_CPRE_MCK_DIV_256_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/256 Position */ +#define PWM_CMR_CPRE_MCK_DIV_512 (PWM_CMR_CPRE_MCK_DIV_512_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/512 Position */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (PWM_CMR_CPRE_MCK_DIV_1024_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/1024 Position */ +#define PWM_CMR_CPRE_CLKA (PWM_CMR_CPRE_CLKA_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock A Position */ +#define PWM_CMR_CPRE_CLKB (PWM_CMR_CPRE_CLKB_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock B Position */ +#define PWM_CMR_CALG_Pos 8 /**< (PWM_CMR) Channel Alignment Position */ +#define PWM_CMR_CALG_Msk (_U_(0x1) << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Channel Alignment Mask */ +#define PWM_CMR_CALG PWM_CMR_CALG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_CALG_Msk instead */ +#define PWM_CMR_CALG_LEFT_ALIGNED_Val _U_(0x0) /**< (PWM_CMR) Left aligned */ +#define PWM_CMR_CALG_CENTER_ALIGNED_Val _U_(0x1) /**< (PWM_CMR) Center aligned */ +#define PWM_CMR_CALG_LEFT_ALIGNED (PWM_CMR_CALG_LEFT_ALIGNED_Val << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Left aligned Position */ +#define PWM_CMR_CALG_CENTER_ALIGNED (PWM_CMR_CALG_CENTER_ALIGNED_Val << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Center aligned Position */ +#define PWM_CMR_CPOL_Pos 9 /**< (PWM_CMR) Channel Polarity Position */ +#define PWM_CMR_CPOL_Msk (_U_(0x1) << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Channel Polarity Mask */ +#define PWM_CMR_CPOL PWM_CMR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_CPOL_Msk instead */ +#define PWM_CMR_CPOL_LOW_POLARITY_Val _U_(0x0) /**< (PWM_CMR) Waveform starts at low level */ +#define PWM_CMR_CPOL_HIGH_POLARITY_Val _U_(0x1) /**< (PWM_CMR) Waveform starts at high level */ +#define PWM_CMR_CPOL_LOW_POLARITY (PWM_CMR_CPOL_LOW_POLARITY_Val << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Waveform starts at low level Position */ +#define PWM_CMR_CPOL_HIGH_POLARITY (PWM_CMR_CPOL_HIGH_POLARITY_Val << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Waveform starts at high level Position */ +#define PWM_CMR_CES_Pos 10 /**< (PWM_CMR) Counter Event Selection Position */ +#define PWM_CMR_CES_Msk (_U_(0x1) << PWM_CMR_CES_Pos) /**< (PWM_CMR) Counter Event Selection Mask */ +#define PWM_CMR_CES PWM_CMR_CES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_CES_Msk instead */ +#define PWM_CMR_CES_SINGLE_EVENT_Val _U_(0x0) /**< (PWM_CMR) At the end of PWM period */ +#define PWM_CMR_CES_DOUBLE_EVENT_Val _U_(0x1) /**< (PWM_CMR) At half of PWM period AND at the end of PWM period */ +#define PWM_CMR_CES_SINGLE_EVENT (PWM_CMR_CES_SINGLE_EVENT_Val << PWM_CMR_CES_Pos) /**< (PWM_CMR) At the end of PWM period Position */ +#define PWM_CMR_CES_DOUBLE_EVENT (PWM_CMR_CES_DOUBLE_EVENT_Val << PWM_CMR_CES_Pos) /**< (PWM_CMR) At half of PWM period AND at the end of PWM period Position */ +#define PWM_CMR_UPDS_Pos 11 /**< (PWM_CMR) Update Selection Position */ +#define PWM_CMR_UPDS_Msk (_U_(0x1) << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) Update Selection Mask */ +#define PWM_CMR_UPDS PWM_CMR_UPDS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_UPDS_Msk instead */ +#define PWM_CMR_UPDS_UPDATE_AT_PERIOD_Val _U_(0x0) /**< (PWM_CMR) At the next end of PWM period */ +#define PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD_Val _U_(0x1) /**< (PWM_CMR) At the next end of Half PWM period */ +#define PWM_CMR_UPDS_UPDATE_AT_PERIOD (PWM_CMR_UPDS_UPDATE_AT_PERIOD_Val << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) At the next end of PWM period Position */ +#define PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD (PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD_Val << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) At the next end of Half PWM period Position */ +#define PWM_CMR_DPOLI_Pos 12 /**< (PWM_CMR) Disabled Polarity Inverted Position */ +#define PWM_CMR_DPOLI_Msk (_U_(0x1) << PWM_CMR_DPOLI_Pos) /**< (PWM_CMR) Disabled Polarity Inverted Mask */ +#define PWM_CMR_DPOLI PWM_CMR_DPOLI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_DPOLI_Msk instead */ +#define PWM_CMR_TCTS_Pos 13 /**< (PWM_CMR) Timer Counter Trigger Selection Position */ +#define PWM_CMR_TCTS_Msk (_U_(0x1) << PWM_CMR_TCTS_Pos) /**< (PWM_CMR) Timer Counter Trigger Selection Mask */ +#define PWM_CMR_TCTS PWM_CMR_TCTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_TCTS_Msk instead */ +#define PWM_CMR_DTE_Pos 16 /**< (PWM_CMR) Dead-Time Generator Enable Position */ +#define PWM_CMR_DTE_Msk (_U_(0x1) << PWM_CMR_DTE_Pos) /**< (PWM_CMR) Dead-Time Generator Enable Mask */ +#define PWM_CMR_DTE PWM_CMR_DTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_DTE_Msk instead */ +#define PWM_CMR_DTHI_Pos 17 /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Position */ +#define PWM_CMR_DTHI_Msk (_U_(0x1) << PWM_CMR_DTHI_Pos) /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Mask */ +#define PWM_CMR_DTHI PWM_CMR_DTHI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_DTHI_Msk instead */ +#define PWM_CMR_DTLI_Pos 18 /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Position */ +#define PWM_CMR_DTLI_Msk (_U_(0x1) << PWM_CMR_DTLI_Pos) /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Mask */ +#define PWM_CMR_DTLI PWM_CMR_DTLI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_DTLI_Msk instead */ +#define PWM_CMR_PPM_Pos 19 /**< (PWM_CMR) Push-Pull Mode Position */ +#define PWM_CMR_PPM_Msk (_U_(0x1) << PWM_CMR_PPM_Pos) /**< (PWM_CMR) Push-Pull Mode Mask */ +#define PWM_CMR_PPM PWM_CMR_PPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMR_PPM_Msk instead */ +#define PWM_CMR_MASK _U_(0xF3F0F) /**< \deprecated (PWM_CMR) Register MASK (Use PWM_CMR_Msk instead) */ +#define PWM_CMR_Msk _U_(0xF3F0F) /**< (PWM_CMR) Register Mask */ + + +/* -------- PWM_CDTY : (PWM Offset: 0x04) (R/W 32) PWM Channel Duty Cycle Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CDTY:24; /**< bit: 0..23 Channel Duty-Cycle */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CDTY_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CDTY_OFFSET (0x04) /**< (PWM_CDTY) PWM Channel Duty Cycle Register Offset */ + +#define PWM_CDTY_CDTY_Pos 0 /**< (PWM_CDTY) Channel Duty-Cycle Position */ +#define PWM_CDTY_CDTY_Msk (_U_(0xFFFFFF) << PWM_CDTY_CDTY_Pos) /**< (PWM_CDTY) Channel Duty-Cycle Mask */ +#define PWM_CDTY_CDTY(value) (PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)) +#define PWM_CDTY_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_CDTY) Register MASK (Use PWM_CDTY_Msk instead) */ +#define PWM_CDTY_Msk _U_(0xFFFFFF) /**< (PWM_CDTY) Register Mask */ + + +/* -------- PWM_CDTYUPD : (PWM Offset: 0x08) (/W 32) PWM Channel Duty Cycle Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CDTYUPD:24; /**< bit: 0..23 Channel Duty-Cycle Update */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CDTYUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CDTYUPD_OFFSET (0x08) /**< (PWM_CDTYUPD) PWM Channel Duty Cycle Update Register Offset */ + +#define PWM_CDTYUPD_CDTYUPD_Pos 0 /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Position */ +#define PWM_CDTYUPD_CDTYUPD_Msk (_U_(0xFFFFFF) << PWM_CDTYUPD_CDTYUPD_Pos) /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Mask */ +#define PWM_CDTYUPD_CDTYUPD(value) (PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)) +#define PWM_CDTYUPD_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_CDTYUPD) Register MASK (Use PWM_CDTYUPD_Msk instead) */ +#define PWM_CDTYUPD_Msk _U_(0xFFFFFF) /**< (PWM_CDTYUPD) Register Mask */ + + +/* -------- PWM_CPRD : (PWM Offset: 0x0c) (R/W 32) PWM Channel Period Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CPRD:24; /**< bit: 0..23 Channel Period */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CPRD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CPRD_OFFSET (0x0C) /**< (PWM_CPRD) PWM Channel Period Register Offset */ + +#define PWM_CPRD_CPRD_Pos 0 /**< (PWM_CPRD) Channel Period Position */ +#define PWM_CPRD_CPRD_Msk (_U_(0xFFFFFF) << PWM_CPRD_CPRD_Pos) /**< (PWM_CPRD) Channel Period Mask */ +#define PWM_CPRD_CPRD(value) (PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)) +#define PWM_CPRD_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_CPRD) Register MASK (Use PWM_CPRD_Msk instead) */ +#define PWM_CPRD_Msk _U_(0xFFFFFF) /**< (PWM_CPRD) Register Mask */ + + +/* -------- PWM_CPRDUPD : (PWM Offset: 0x10) (/W 32) PWM Channel Period Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CPRDUPD:24; /**< bit: 0..23 Channel Period Update */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CPRDUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CPRDUPD_OFFSET (0x10) /**< (PWM_CPRDUPD) PWM Channel Period Update Register Offset */ + +#define PWM_CPRDUPD_CPRDUPD_Pos 0 /**< (PWM_CPRDUPD) Channel Period Update Position */ +#define PWM_CPRDUPD_CPRDUPD_Msk (_U_(0xFFFFFF) << PWM_CPRDUPD_CPRDUPD_Pos) /**< (PWM_CPRDUPD) Channel Period Update Mask */ +#define PWM_CPRDUPD_CPRDUPD(value) (PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)) +#define PWM_CPRDUPD_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_CPRDUPD) Register MASK (Use PWM_CPRDUPD_Msk instead) */ +#define PWM_CPRDUPD_Msk _U_(0xFFFFFF) /**< (PWM_CPRDUPD) Register Mask */ + + +/* -------- PWM_CCNT : (PWM Offset: 0x14) (R/ 32) PWM Channel Counter Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CNT:24; /**< bit: 0..23 Channel Counter Register */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CCNT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CCNT_OFFSET (0x14) /**< (PWM_CCNT) PWM Channel Counter Register Offset */ + +#define PWM_CCNT_CNT_Pos 0 /**< (PWM_CCNT) Channel Counter Register Position */ +#define PWM_CCNT_CNT_Msk (_U_(0xFFFFFF) << PWM_CCNT_CNT_Pos) /**< (PWM_CCNT) Channel Counter Register Mask */ +#define PWM_CCNT_CNT(value) (PWM_CCNT_CNT_Msk & ((value) << PWM_CCNT_CNT_Pos)) +#define PWM_CCNT_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_CCNT) Register MASK (Use PWM_CCNT_Msk instead) */ +#define PWM_CCNT_Msk _U_(0xFFFFFF) /**< (PWM_CCNT) Register Mask */ + + +/* -------- PWM_DT : (PWM Offset: 0x18) (R/W 32) PWM Channel Dead Time Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DTH:16; /**< bit: 0..15 Dead-Time Value for PWMHx Output */ + uint32_t DTL:16; /**< bit: 16..31 Dead-Time Value for PWMLx Output */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_DT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_DT_OFFSET (0x18) /**< (PWM_DT) PWM Channel Dead Time Register Offset */ + +#define PWM_DT_DTH_Pos 0 /**< (PWM_DT) Dead-Time Value for PWMHx Output Position */ +#define PWM_DT_DTH_Msk (_U_(0xFFFF) << PWM_DT_DTH_Pos) /**< (PWM_DT) Dead-Time Value for PWMHx Output Mask */ +#define PWM_DT_DTH(value) (PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)) +#define PWM_DT_DTL_Pos 16 /**< (PWM_DT) Dead-Time Value for PWMLx Output Position */ +#define PWM_DT_DTL_Msk (_U_(0xFFFF) << PWM_DT_DTL_Pos) /**< (PWM_DT) Dead-Time Value for PWMLx Output Mask */ +#define PWM_DT_DTL(value) (PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)) +#define PWM_DT_MASK _U_(0xFFFFFFFF) /**< \deprecated (PWM_DT) Register MASK (Use PWM_DT_Msk instead) */ +#define PWM_DT_Msk _U_(0xFFFFFFFF) /**< (PWM_DT) Register Mask */ + + +/* -------- PWM_DTUPD : (PWM Offset: 0x1c) (/W 32) PWM Channel Dead Time Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DTHUPD:16; /**< bit: 0..15 Dead-Time Value Update for PWMHx Output */ + uint32_t DTLUPD:16; /**< bit: 16..31 Dead-Time Value Update for PWMLx Output */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_DTUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_DTUPD_OFFSET (0x1C) /**< (PWM_DTUPD) PWM Channel Dead Time Update Register Offset */ + +#define PWM_DTUPD_DTHUPD_Pos 0 /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Position */ +#define PWM_DTUPD_DTHUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTHUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Mask */ +#define PWM_DTUPD_DTHUPD(value) (PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)) +#define PWM_DTUPD_DTLUPD_Pos 16 /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Position */ +#define PWM_DTUPD_DTLUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTLUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Mask */ +#define PWM_DTUPD_DTLUPD(value) (PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)) +#define PWM_DTUPD_MASK _U_(0xFFFFFFFF) /**< \deprecated (PWM_DTUPD) Register MASK (Use PWM_DTUPD_Msk instead) */ +#define PWM_DTUPD_Msk _U_(0xFFFFFFFF) /**< (PWM_DTUPD) Register Mask */ + + +/* -------- PWM_CMPV : (PWM Offset: 0x00) (R/W 32) PWM Comparison 0 Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CV:24; /**< bit: 0..23 Comparison x Value */ + uint32_t CVM:1; /**< bit: 24 Comparison x Value Mode */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMPV_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMPV_OFFSET (0x00) /**< (PWM_CMPV) PWM Comparison 0 Value Register Offset */ + +#define PWM_CMPV_CV_Pos 0 /**< (PWM_CMPV) Comparison x Value Position */ +#define PWM_CMPV_CV_Msk (_U_(0xFFFFFF) << PWM_CMPV_CV_Pos) /**< (PWM_CMPV) Comparison x Value Mask */ +#define PWM_CMPV_CV(value) (PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)) +#define PWM_CMPV_CVM_Pos 24 /**< (PWM_CMPV) Comparison x Value Mode Position */ +#define PWM_CMPV_CVM_Msk (_U_(0x1) << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Comparison x Value Mode Mask */ +#define PWM_CMPV_CVM PWM_CMPV_CVM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMPV_CVM_Msk instead */ +#define PWM_CMPV_CVM_COMPARE_AT_INCREMENT_Val _U_(0x0) /**< (PWM_CMPV) Compare when counter is incrementing */ +#define PWM_CMPV_CVM_COMPARE_AT_DECREMENT_Val _U_(0x1) /**< (PWM_CMPV) Compare when counter is decrementing */ +#define PWM_CMPV_CVM_COMPARE_AT_INCREMENT (PWM_CMPV_CVM_COMPARE_AT_INCREMENT_Val << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Compare when counter is incrementing Position */ +#define PWM_CMPV_CVM_COMPARE_AT_DECREMENT (PWM_CMPV_CVM_COMPARE_AT_DECREMENT_Val << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Compare when counter is decrementing Position */ +#define PWM_CMPV_MASK _U_(0x1FFFFFF) /**< \deprecated (PWM_CMPV) Register MASK (Use PWM_CMPV_Msk instead) */ +#define PWM_CMPV_Msk _U_(0x1FFFFFF) /**< (PWM_CMPV) Register Mask */ + + +/* -------- PWM_CMPVUPD : (PWM Offset: 0x04) (/W 32) PWM Comparison 0 Value Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CVUPD:24; /**< bit: 0..23 Comparison x Value Update */ + uint32_t CVMUPD:1; /**< bit: 24 Comparison x Value Mode Update */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMPVUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMPVUPD_OFFSET (0x04) /**< (PWM_CMPVUPD) PWM Comparison 0 Value Update Register Offset */ + +#define PWM_CMPVUPD_CVUPD_Pos 0 /**< (PWM_CMPVUPD) Comparison x Value Update Position */ +#define PWM_CMPVUPD_CVUPD_Msk (_U_(0xFFFFFF) << PWM_CMPVUPD_CVUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Update Mask */ +#define PWM_CMPVUPD_CVUPD(value) (PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)) +#define PWM_CMPVUPD_CVMUPD_Pos 24 /**< (PWM_CMPVUPD) Comparison x Value Mode Update Position */ +#define PWM_CMPVUPD_CVMUPD_Msk (_U_(0x1) << PWM_CMPVUPD_CVMUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Mode Update Mask */ +#define PWM_CMPVUPD_CVMUPD PWM_CMPVUPD_CVMUPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMPVUPD_CVMUPD_Msk instead */ +#define PWM_CMPVUPD_MASK _U_(0x1FFFFFF) /**< \deprecated (PWM_CMPVUPD) Register MASK (Use PWM_CMPVUPD_Msk instead) */ +#define PWM_CMPVUPD_Msk _U_(0x1FFFFFF) /**< (PWM_CMPVUPD) Register Mask */ + + +/* -------- PWM_CMPM : (PWM Offset: 0x08) (R/W 32) PWM Comparison 0 Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CEN:1; /**< bit: 0 Comparison x Enable */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t CTR:4; /**< bit: 4..7 Comparison x Trigger */ + uint32_t CPR:4; /**< bit: 8..11 Comparison x Period */ + uint32_t CPRCNT:4; /**< bit: 12..15 Comparison x Period Counter */ + uint32_t CUPR:4; /**< bit: 16..19 Comparison x Update Period */ + uint32_t CUPRCNT:4; /**< bit: 20..23 Comparison x Update Period Counter */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMPM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMPM_OFFSET (0x08) /**< (PWM_CMPM) PWM Comparison 0 Mode Register Offset */ + +#define PWM_CMPM_CEN_Pos 0 /**< (PWM_CMPM) Comparison x Enable Position */ +#define PWM_CMPM_CEN_Msk (_U_(0x1) << PWM_CMPM_CEN_Pos) /**< (PWM_CMPM) Comparison x Enable Mask */ +#define PWM_CMPM_CEN PWM_CMPM_CEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMPM_CEN_Msk instead */ +#define PWM_CMPM_CTR_Pos 4 /**< (PWM_CMPM) Comparison x Trigger Position */ +#define PWM_CMPM_CTR_Msk (_U_(0xF) << PWM_CMPM_CTR_Pos) /**< (PWM_CMPM) Comparison x Trigger Mask */ +#define PWM_CMPM_CTR(value) (PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)) +#define PWM_CMPM_CPR_Pos 8 /**< (PWM_CMPM) Comparison x Period Position */ +#define PWM_CMPM_CPR_Msk (_U_(0xF) << PWM_CMPM_CPR_Pos) /**< (PWM_CMPM) Comparison x Period Mask */ +#define PWM_CMPM_CPR(value) (PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)) +#define PWM_CMPM_CPRCNT_Pos 12 /**< (PWM_CMPM) Comparison x Period Counter Position */ +#define PWM_CMPM_CPRCNT_Msk (_U_(0xF) << PWM_CMPM_CPRCNT_Pos) /**< (PWM_CMPM) Comparison x Period Counter Mask */ +#define PWM_CMPM_CPRCNT(value) (PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)) +#define PWM_CMPM_CUPR_Pos 16 /**< (PWM_CMPM) Comparison x Update Period Position */ +#define PWM_CMPM_CUPR_Msk (_U_(0xF) << PWM_CMPM_CUPR_Pos) /**< (PWM_CMPM) Comparison x Update Period Mask */ +#define PWM_CMPM_CUPR(value) (PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)) +#define PWM_CMPM_CUPRCNT_Pos 20 /**< (PWM_CMPM) Comparison x Update Period Counter Position */ +#define PWM_CMPM_CUPRCNT_Msk (_U_(0xF) << PWM_CMPM_CUPRCNT_Pos) /**< (PWM_CMPM) Comparison x Update Period Counter Mask */ +#define PWM_CMPM_CUPRCNT(value) (PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)) +#define PWM_CMPM_MASK _U_(0xFFFFF1) /**< \deprecated (PWM_CMPM) Register MASK (Use PWM_CMPM_Msk instead) */ +#define PWM_CMPM_Msk _U_(0xFFFFF1) /**< (PWM_CMPM) Register Mask */ + + +/* -------- PWM_CMPMUPD : (PWM Offset: 0x0c) (/W 32) PWM Comparison 0 Mode Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CENUPD:1; /**< bit: 0 Comparison x Enable Update */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t CTRUPD:4; /**< bit: 4..7 Comparison x Trigger Update */ + uint32_t CPRUPD:4; /**< bit: 8..11 Comparison x Period Update */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t CUPRUPD:4; /**< bit: 16..19 Comparison x Update Period Update */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMPMUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMPMUPD_OFFSET (0x0C) /**< (PWM_CMPMUPD) PWM Comparison 0 Mode Update Register Offset */ + +#define PWM_CMPMUPD_CENUPD_Pos 0 /**< (PWM_CMPMUPD) Comparison x Enable Update Position */ +#define PWM_CMPMUPD_CENUPD_Msk (_U_(0x1) << PWM_CMPMUPD_CENUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Enable Update Mask */ +#define PWM_CMPMUPD_CENUPD PWM_CMPMUPD_CENUPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMPMUPD_CENUPD_Msk instead */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 /**< (PWM_CMPMUPD) Comparison x Trigger Update Position */ +#define PWM_CMPMUPD_CTRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CTRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Trigger Update Mask */ +#define PWM_CMPMUPD_CTRUPD(value) (PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)) +#define PWM_CMPMUPD_CPRUPD_Pos 8 /**< (PWM_CMPMUPD) Comparison x Period Update Position */ +#define PWM_CMPMUPD_CPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Period Update Mask */ +#define PWM_CMPMUPD_CPRUPD(value) (PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 /**< (PWM_CMPMUPD) Comparison x Update Period Update Position */ +#define PWM_CMPMUPD_CUPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CUPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Update Period Update Mask */ +#define PWM_CMPMUPD_CUPRUPD(value) (PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)) +#define PWM_CMPMUPD_MASK _U_(0xF0FF1) /**< \deprecated (PWM_CMPMUPD) Register MASK (Use PWM_CMPMUPD_Msk instead) */ +#define PWM_CMPMUPD_Msk _U_(0xF0FF1) /**< (PWM_CMPMUPD) Register Mask */ + + +/* -------- PWM_CLK : (PWM Offset: 0x00) (R/W 32) PWM Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DIVA:8; /**< bit: 0..7 CLKA Divide Factor */ + uint32_t PREA:4; /**< bit: 8..11 CLKA Source Clock Selection */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t DIVB:8; /**< bit: 16..23 CLKB Divide Factor */ + uint32_t PREB:4; /**< bit: 24..27 CLKB Source Clock Selection */ + uint32_t :4; /**< bit: 28..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CLK_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CLK_OFFSET (0x00) /**< (PWM_CLK) PWM Clock Register Offset */ + +#define PWM_CLK_DIVA_Pos 0 /**< (PWM_CLK) CLKA Divide Factor Position */ +#define PWM_CLK_DIVA_Msk (_U_(0xFF) << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA Divide Factor Mask */ +#define PWM_CLK_DIVA(value) (PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)) +#define PWM_CLK_DIVA_CLKA_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA_Val _U_(0x1) /**< (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_DIVA_CLKA_POFF (PWM_CLK_DIVA_CLKA_POFF_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is turned off Position */ +#define PWM_CLK_DIVA_PREA (PWM_CLK_DIVA_PREA_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is clock selected by PREA Position */ +#define PWM_CLK_PREA_Pos 8 /**< (PWM_CLK) CLKA Source Clock Selection Position */ +#define PWM_CLK_PREA_Msk (_U_(0xF) << PWM_CLK_PREA_Pos) /**< (PWM_CLK) CLKA Source Clock Selection Mask */ +#define PWM_CLK_PREA(value) (PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)) +#define PWM_CLK_PREA_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREA_CLK (PWM_CLK_PREA_CLK_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREA_CLK_DIV2 (PWM_CLK_PREA_CLK_DIV2_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREA_CLK_DIV4 (PWM_CLK_PREA_CLK_DIV4_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREA_CLK_DIV8 (PWM_CLK_PREA_CLK_DIV8_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREA_CLK_DIV16 (PWM_CLK_PREA_CLK_DIV16_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREA_CLK_DIV32 (PWM_CLK_PREA_CLK_DIV32_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREA_CLK_DIV64 (PWM_CLK_PREA_CLK_DIV64_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREA_CLK_DIV128 (PWM_CLK_PREA_CLK_DIV128_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREA_CLK_DIV256 (PWM_CLK_PREA_CLK_DIV256_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREA_CLK_DIV512 (PWM_CLK_PREA_CLK_DIV512_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREA_CLK_DIV1024 (PWM_CLK_PREA_CLK_DIV1024_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_DIVB_Pos 16 /**< (PWM_CLK) CLKB Divide Factor Position */ +#define PWM_CLK_DIVB_Msk (_U_(0xFF) << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB Divide Factor Mask */ +#define PWM_CLK_DIVB(value) (PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)) +#define PWM_CLK_DIVB_CLKB_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB_Val _U_(0x1) /**< (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_DIVB_CLKB_POFF (PWM_CLK_DIVB_CLKB_POFF_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is turned off Position */ +#define PWM_CLK_DIVB_PREB (PWM_CLK_DIVB_PREB_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is clock selected by PREB Position */ +#define PWM_CLK_PREB_Pos 24 /**< (PWM_CLK) CLKB Source Clock Selection Position */ +#define PWM_CLK_PREB_Msk (_U_(0xF) << PWM_CLK_PREB_Pos) /**< (PWM_CLK) CLKB Source Clock Selection Mask */ +#define PWM_CLK_PREB(value) (PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)) +#define PWM_CLK_PREB_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREB_CLK (PWM_CLK_PREB_CLK_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREB_CLK_DIV2 (PWM_CLK_PREB_CLK_DIV2_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREB_CLK_DIV4 (PWM_CLK_PREB_CLK_DIV4_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREB_CLK_DIV8 (PWM_CLK_PREB_CLK_DIV8_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREB_CLK_DIV16 (PWM_CLK_PREB_CLK_DIV16_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREB_CLK_DIV32 (PWM_CLK_PREB_CLK_DIV32_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREB_CLK_DIV64 (PWM_CLK_PREB_CLK_DIV64_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREB_CLK_DIV128 (PWM_CLK_PREB_CLK_DIV128_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREB_CLK_DIV256 (PWM_CLK_PREB_CLK_DIV256_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREB_CLK_DIV512 (PWM_CLK_PREB_CLK_DIV512_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREB_CLK_DIV1024 (PWM_CLK_PREB_CLK_DIV1024_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_MASK _U_(0xFFF0FFF) /**< \deprecated (PWM_CLK) Register MASK (Use PWM_CLK_Msk instead) */ +#define PWM_CLK_Msk _U_(0xFFF0FFF) /**< (PWM_CLK) Register Mask */ + + +/* -------- PWM_ENA : (PWM Offset: 0x04) (/W 32) PWM Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Channel ID */ + uint32_t CHID1:1; /**< bit: 1 Channel ID */ + uint32_t CHID2:1; /**< bit: 2 Channel ID */ + uint32_t CHID3:1; /**< bit: 3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ENA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ENA_OFFSET (0x04) /**< (PWM_ENA) PWM Enable Register Offset */ + +#define PWM_ENA_CHID0_Pos 0 /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID0_Msk (_U_(0x1) << PWM_ENA_CHID0_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID0 PWM_ENA_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ENA_CHID0_Msk instead */ +#define PWM_ENA_CHID1_Pos 1 /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID1_Msk (_U_(0x1) << PWM_ENA_CHID1_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID1 PWM_ENA_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ENA_CHID1_Msk instead */ +#define PWM_ENA_CHID2_Pos 2 /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID2_Msk (_U_(0x1) << PWM_ENA_CHID2_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID2 PWM_ENA_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ENA_CHID2_Msk instead */ +#define PWM_ENA_CHID3_Pos 3 /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID3_Msk (_U_(0x1) << PWM_ENA_CHID3_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID3 PWM_ENA_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ENA_CHID3_Msk instead */ +#define PWM_ENA_MASK _U_(0x0F) /**< \deprecated (PWM_ENA) Register MASK (Use PWM_ENA_Msk instead) */ +#define PWM_ENA_Msk _U_(0x0F) /**< (PWM_ENA) Register Mask */ + +#define PWM_ENA_CHID_Pos 0 /**< (PWM_ENA Position) Channel ID */ +#define PWM_ENA_CHID_Msk (_U_(0xF) << PWM_ENA_CHID_Pos) /**< (PWM_ENA Mask) CHID */ +#define PWM_ENA_CHID(value) (PWM_ENA_CHID_Msk & ((value) << PWM_ENA_CHID_Pos)) + +/* -------- PWM_DIS : (PWM Offset: 0x08) (/W 32) PWM Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Channel ID */ + uint32_t CHID1:1; /**< bit: 1 Channel ID */ + uint32_t CHID2:1; /**< bit: 2 Channel ID */ + uint32_t CHID3:1; /**< bit: 3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_DIS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_DIS_OFFSET (0x08) /**< (PWM_DIS) PWM Disable Register Offset */ + +#define PWM_DIS_CHID0_Pos 0 /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID0_Msk (_U_(0x1) << PWM_DIS_CHID0_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID0 PWM_DIS_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_DIS_CHID0_Msk instead */ +#define PWM_DIS_CHID1_Pos 1 /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID1_Msk (_U_(0x1) << PWM_DIS_CHID1_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID1 PWM_DIS_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_DIS_CHID1_Msk instead */ +#define PWM_DIS_CHID2_Pos 2 /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID2_Msk (_U_(0x1) << PWM_DIS_CHID2_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID2 PWM_DIS_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_DIS_CHID2_Msk instead */ +#define PWM_DIS_CHID3_Pos 3 /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID3_Msk (_U_(0x1) << PWM_DIS_CHID3_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID3 PWM_DIS_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_DIS_CHID3_Msk instead */ +#define PWM_DIS_MASK _U_(0x0F) /**< \deprecated (PWM_DIS) Register MASK (Use PWM_DIS_Msk instead) */ +#define PWM_DIS_Msk _U_(0x0F) /**< (PWM_DIS) Register Mask */ + +#define PWM_DIS_CHID_Pos 0 /**< (PWM_DIS Position) Channel ID */ +#define PWM_DIS_CHID_Msk (_U_(0xF) << PWM_DIS_CHID_Pos) /**< (PWM_DIS Mask) CHID */ +#define PWM_DIS_CHID(value) (PWM_DIS_CHID_Msk & ((value) << PWM_DIS_CHID_Pos)) + +/* -------- PWM_SR : (PWM Offset: 0x0c) (R/ 32) PWM Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Channel ID */ + uint32_t CHID1:1; /**< bit: 1 Channel ID */ + uint32_t CHID2:1; /**< bit: 2 Channel ID */ + uint32_t CHID3:1; /**< bit: 3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Channel ID */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SR_OFFSET (0x0C) /**< (PWM_SR) PWM Status Register Offset */ + +#define PWM_SR_CHID0_Pos 0 /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID0_Msk (_U_(0x1) << PWM_SR_CHID0_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID0 PWM_SR_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SR_CHID0_Msk instead */ +#define PWM_SR_CHID1_Pos 1 /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID1_Msk (_U_(0x1) << PWM_SR_CHID1_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID1 PWM_SR_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SR_CHID1_Msk instead */ +#define PWM_SR_CHID2_Pos 2 /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID2_Msk (_U_(0x1) << PWM_SR_CHID2_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID2 PWM_SR_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SR_CHID2_Msk instead */ +#define PWM_SR_CHID3_Pos 3 /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID3_Msk (_U_(0x1) << PWM_SR_CHID3_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID3 PWM_SR_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SR_CHID3_Msk instead */ +#define PWM_SR_MASK _U_(0x0F) /**< \deprecated (PWM_SR) Register MASK (Use PWM_SR_Msk instead) */ +#define PWM_SR_Msk _U_(0x0F) /**< (PWM_SR) Register Mask */ + +#define PWM_SR_CHID_Pos 0 /**< (PWM_SR Position) Channel ID */ +#define PWM_SR_CHID_Msk (_U_(0xF) << PWM_SR_CHID_Pos) /**< (PWM_SR Mask) CHID */ +#define PWM_SR_CHID(value) (PWM_SR_CHID_Msk & ((value) << PWM_SR_CHID_Pos)) + +/* -------- PWM_IER1 : (PWM Offset: 0x10) (/W 32) PWM Interrupt Enable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Counter Event on Channel 0 Interrupt Enable */ + uint32_t CHID1:1; /**< bit: 1 Counter Event on Channel 1 Interrupt Enable */ + uint32_t CHID2:1; /**< bit: 2 Counter Event on Channel 2 Interrupt Enable */ + uint32_t CHID3:1; /**< bit: 3 Counter Event on Channel 3 Interrupt Enable */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID0:1; /**< bit: 16 Fault Protection Trigger on Channel 0 Interrupt Enable */ + uint32_t FCHID1:1; /**< bit: 17 Fault Protection Trigger on Channel 1 Interrupt Enable */ + uint32_t FCHID2:1; /**< bit: 18 Fault Protection Trigger on Channel 2 Interrupt Enable */ + uint32_t FCHID3:1; /**< bit: 19 Fault Protection Trigger on Channel 3 Interrupt Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Counter Event on Channel x Interrupt Enable */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID:4; /**< bit: 16..19 Fault Protection Trigger on Channel 3 Interrupt Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IER1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IER1_OFFSET (0x10) /**< (PWM_IER1) PWM Interrupt Enable Register 1 Offset */ + +#define PWM_IER1_CHID0_Pos 0 /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_CHID0_Msk (_U_(0x1) << PWM_IER1_CHID0_Pos) /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_CHID0 PWM_IER1_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_CHID0_Msk instead */ +#define PWM_IER1_CHID1_Pos 1 /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_CHID1_Msk (_U_(0x1) << PWM_IER1_CHID1_Pos) /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_CHID1 PWM_IER1_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_CHID1_Msk instead */ +#define PWM_IER1_CHID2_Pos 2 /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_CHID2_Msk (_U_(0x1) << PWM_IER1_CHID2_Pos) /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_CHID2 PWM_IER1_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_CHID2_Msk instead */ +#define PWM_IER1_CHID3_Pos 3 /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_CHID3_Msk (_U_(0x1) << PWM_IER1_CHID3_Pos) /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_CHID3 PWM_IER1_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_CHID3_Msk instead */ +#define PWM_IER1_FCHID0_Pos 16 /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_FCHID0_Msk (_U_(0x1) << PWM_IER1_FCHID0_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_FCHID0 PWM_IER1_FCHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_FCHID0_Msk instead */ +#define PWM_IER1_FCHID1_Pos 17 /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_FCHID1_Msk (_U_(0x1) << PWM_IER1_FCHID1_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_FCHID1 PWM_IER1_FCHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_FCHID1_Msk instead */ +#define PWM_IER1_FCHID2_Pos 18 /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_FCHID2_Msk (_U_(0x1) << PWM_IER1_FCHID2_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_FCHID2 PWM_IER1_FCHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_FCHID2_Msk instead */ +#define PWM_IER1_FCHID3_Pos 19 /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_FCHID3_Msk (_U_(0x1) << PWM_IER1_FCHID3_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_FCHID3 PWM_IER1_FCHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER1_FCHID3_Msk instead */ +#define PWM_IER1_MASK _U_(0xF000F) /**< \deprecated (PWM_IER1) Register MASK (Use PWM_IER1_Msk instead) */ +#define PWM_IER1_Msk _U_(0xF000F) /**< (PWM_IER1) Register Mask */ + +#define PWM_IER1_CHID_Pos 0 /**< (PWM_IER1 Position) Counter Event on Channel x Interrupt Enable */ +#define PWM_IER1_CHID_Msk (_U_(0xF) << PWM_IER1_CHID_Pos) /**< (PWM_IER1 Mask) CHID */ +#define PWM_IER1_CHID(value) (PWM_IER1_CHID_Msk & ((value) << PWM_IER1_CHID_Pos)) +#define PWM_IER1_FCHID_Pos 16 /**< (PWM_IER1 Position) Fault Protection Trigger on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID_Msk (_U_(0xF) << PWM_IER1_FCHID_Pos) /**< (PWM_IER1 Mask) FCHID */ +#define PWM_IER1_FCHID(value) (PWM_IER1_FCHID_Msk & ((value) << PWM_IER1_FCHID_Pos)) + +/* -------- PWM_IDR1 : (PWM Offset: 0x14) (/W 32) PWM Interrupt Disable Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Counter Event on Channel 0 Interrupt Disable */ + uint32_t CHID1:1; /**< bit: 1 Counter Event on Channel 1 Interrupt Disable */ + uint32_t CHID2:1; /**< bit: 2 Counter Event on Channel 2 Interrupt Disable */ + uint32_t CHID3:1; /**< bit: 3 Counter Event on Channel 3 Interrupt Disable */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID0:1; /**< bit: 16 Fault Protection Trigger on Channel 0 Interrupt Disable */ + uint32_t FCHID1:1; /**< bit: 17 Fault Protection Trigger on Channel 1 Interrupt Disable */ + uint32_t FCHID2:1; /**< bit: 18 Fault Protection Trigger on Channel 2 Interrupt Disable */ + uint32_t FCHID3:1; /**< bit: 19 Fault Protection Trigger on Channel 3 Interrupt Disable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Counter Event on Channel x Interrupt Disable */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID:4; /**< bit: 16..19 Fault Protection Trigger on Channel 3 Interrupt Disable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IDR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IDR1_OFFSET (0x14) /**< (PWM_IDR1) PWM Interrupt Disable Register 1 Offset */ + +#define PWM_IDR1_CHID0_Pos 0 /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_CHID0_Msk (_U_(0x1) << PWM_IDR1_CHID0_Pos) /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_CHID0 PWM_IDR1_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_CHID0_Msk instead */ +#define PWM_IDR1_CHID1_Pos 1 /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_CHID1_Msk (_U_(0x1) << PWM_IDR1_CHID1_Pos) /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_CHID1 PWM_IDR1_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_CHID1_Msk instead */ +#define PWM_IDR1_CHID2_Pos 2 /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_CHID2_Msk (_U_(0x1) << PWM_IDR1_CHID2_Pos) /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_CHID2 PWM_IDR1_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_CHID2_Msk instead */ +#define PWM_IDR1_CHID3_Pos 3 /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_CHID3_Msk (_U_(0x1) << PWM_IDR1_CHID3_Pos) /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_CHID3 PWM_IDR1_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_CHID3_Msk instead */ +#define PWM_IDR1_FCHID0_Pos 16 /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_FCHID0_Msk (_U_(0x1) << PWM_IDR1_FCHID0_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID0 PWM_IDR1_FCHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_FCHID0_Msk instead */ +#define PWM_IDR1_FCHID1_Pos 17 /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_FCHID1_Msk (_U_(0x1) << PWM_IDR1_FCHID1_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID1 PWM_IDR1_FCHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_FCHID1_Msk instead */ +#define PWM_IDR1_FCHID2_Pos 18 /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_FCHID2_Msk (_U_(0x1) << PWM_IDR1_FCHID2_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID2 PWM_IDR1_FCHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_FCHID2_Msk instead */ +#define PWM_IDR1_FCHID3_Pos 19 /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_FCHID3_Msk (_U_(0x1) << PWM_IDR1_FCHID3_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID3 PWM_IDR1_FCHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR1_FCHID3_Msk instead */ +#define PWM_IDR1_MASK _U_(0xF000F) /**< \deprecated (PWM_IDR1) Register MASK (Use PWM_IDR1_Msk instead) */ +#define PWM_IDR1_Msk _U_(0xF000F) /**< (PWM_IDR1) Register Mask */ + +#define PWM_IDR1_CHID_Pos 0 /**< (PWM_IDR1 Position) Counter Event on Channel x Interrupt Disable */ +#define PWM_IDR1_CHID_Msk (_U_(0xF) << PWM_IDR1_CHID_Pos) /**< (PWM_IDR1 Mask) CHID */ +#define PWM_IDR1_CHID(value) (PWM_IDR1_CHID_Msk & ((value) << PWM_IDR1_CHID_Pos)) +#define PWM_IDR1_FCHID_Pos 16 /**< (PWM_IDR1 Position) Fault Protection Trigger on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID_Msk (_U_(0xF) << PWM_IDR1_FCHID_Pos) /**< (PWM_IDR1 Mask) FCHID */ +#define PWM_IDR1_FCHID(value) (PWM_IDR1_FCHID_Msk & ((value) << PWM_IDR1_FCHID_Pos)) + +/* -------- PWM_IMR1 : (PWM Offset: 0x18) (R/ 32) PWM Interrupt Mask Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Counter Event on Channel 0 Interrupt Mask */ + uint32_t CHID1:1; /**< bit: 1 Counter Event on Channel 1 Interrupt Mask */ + uint32_t CHID2:1; /**< bit: 2 Counter Event on Channel 2 Interrupt Mask */ + uint32_t CHID3:1; /**< bit: 3 Counter Event on Channel 3 Interrupt Mask */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID0:1; /**< bit: 16 Fault Protection Trigger on Channel 0 Interrupt Mask */ + uint32_t FCHID1:1; /**< bit: 17 Fault Protection Trigger on Channel 1 Interrupt Mask */ + uint32_t FCHID2:1; /**< bit: 18 Fault Protection Trigger on Channel 2 Interrupt Mask */ + uint32_t FCHID3:1; /**< bit: 19 Fault Protection Trigger on Channel 3 Interrupt Mask */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Counter Event on Channel x Interrupt Mask */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID:4; /**< bit: 16..19 Fault Protection Trigger on Channel 3 Interrupt Mask */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IMR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IMR1_OFFSET (0x18) /**< (PWM_IMR1) PWM Interrupt Mask Register 1 Offset */ + +#define PWM_IMR1_CHID0_Pos 0 /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_CHID0_Msk (_U_(0x1) << PWM_IMR1_CHID0_Pos) /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_CHID0 PWM_IMR1_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_CHID0_Msk instead */ +#define PWM_IMR1_CHID1_Pos 1 /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_CHID1_Msk (_U_(0x1) << PWM_IMR1_CHID1_Pos) /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_CHID1 PWM_IMR1_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_CHID1_Msk instead */ +#define PWM_IMR1_CHID2_Pos 2 /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_CHID2_Msk (_U_(0x1) << PWM_IMR1_CHID2_Pos) /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_CHID2 PWM_IMR1_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_CHID2_Msk instead */ +#define PWM_IMR1_CHID3_Pos 3 /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_CHID3_Msk (_U_(0x1) << PWM_IMR1_CHID3_Pos) /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_CHID3 PWM_IMR1_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_CHID3_Msk instead */ +#define PWM_IMR1_FCHID0_Pos 16 /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_FCHID0_Msk (_U_(0x1) << PWM_IMR1_FCHID0_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID0 PWM_IMR1_FCHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_FCHID0_Msk instead */ +#define PWM_IMR1_FCHID1_Pos 17 /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_FCHID1_Msk (_U_(0x1) << PWM_IMR1_FCHID1_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID1 PWM_IMR1_FCHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_FCHID1_Msk instead */ +#define PWM_IMR1_FCHID2_Pos 18 /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_FCHID2_Msk (_U_(0x1) << PWM_IMR1_FCHID2_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID2 PWM_IMR1_FCHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_FCHID2_Msk instead */ +#define PWM_IMR1_FCHID3_Pos 19 /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_FCHID3_Msk (_U_(0x1) << PWM_IMR1_FCHID3_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID3 PWM_IMR1_FCHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR1_FCHID3_Msk instead */ +#define PWM_IMR1_MASK _U_(0xF000F) /**< \deprecated (PWM_IMR1) Register MASK (Use PWM_IMR1_Msk instead) */ +#define PWM_IMR1_Msk _U_(0xF000F) /**< (PWM_IMR1) Register Mask */ + +#define PWM_IMR1_CHID_Pos 0 /**< (PWM_IMR1 Position) Counter Event on Channel x Interrupt Mask */ +#define PWM_IMR1_CHID_Msk (_U_(0xF) << PWM_IMR1_CHID_Pos) /**< (PWM_IMR1 Mask) CHID */ +#define PWM_IMR1_CHID(value) (PWM_IMR1_CHID_Msk & ((value) << PWM_IMR1_CHID_Pos)) +#define PWM_IMR1_FCHID_Pos 16 /**< (PWM_IMR1 Position) Fault Protection Trigger on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID_Msk (_U_(0xF) << PWM_IMR1_FCHID_Pos) /**< (PWM_IMR1 Mask) FCHID */ +#define PWM_IMR1_FCHID(value) (PWM_IMR1_FCHID_Msk & ((value) << PWM_IMR1_FCHID_Pos)) + +/* -------- PWM_ISR1 : (PWM Offset: 0x1c) (R/ 32) PWM Interrupt Status Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHID0:1; /**< bit: 0 Counter Event on Channel 0 */ + uint32_t CHID1:1; /**< bit: 1 Counter Event on Channel 1 */ + uint32_t CHID2:1; /**< bit: 2 Counter Event on Channel 2 */ + uint32_t CHID3:1; /**< bit: 3 Counter Event on Channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID0:1; /**< bit: 16 Fault Protection Trigger on Channel 0 */ + uint32_t FCHID1:1; /**< bit: 17 Fault Protection Trigger on Channel 1 */ + uint32_t FCHID2:1; /**< bit: 18 Fault Protection Trigger on Channel 2 */ + uint32_t FCHID3:1; /**< bit: 19 Fault Protection Trigger on Channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CHID:4; /**< bit: 0..3 Counter Event on Channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FCHID:4; /**< bit: 16..19 Fault Protection Trigger on Channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ISR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ISR1_OFFSET (0x1C) /**< (PWM_ISR1) PWM Interrupt Status Register 1 Offset */ + +#define PWM_ISR1_CHID0_Pos 0 /**< (PWM_ISR1) Counter Event on Channel 0 Position */ +#define PWM_ISR1_CHID0_Msk (_U_(0x1) << PWM_ISR1_CHID0_Pos) /**< (PWM_ISR1) Counter Event on Channel 0 Mask */ +#define PWM_ISR1_CHID0 PWM_ISR1_CHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_CHID0_Msk instead */ +#define PWM_ISR1_CHID1_Pos 1 /**< (PWM_ISR1) Counter Event on Channel 1 Position */ +#define PWM_ISR1_CHID1_Msk (_U_(0x1) << PWM_ISR1_CHID1_Pos) /**< (PWM_ISR1) Counter Event on Channel 1 Mask */ +#define PWM_ISR1_CHID1 PWM_ISR1_CHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_CHID1_Msk instead */ +#define PWM_ISR1_CHID2_Pos 2 /**< (PWM_ISR1) Counter Event on Channel 2 Position */ +#define PWM_ISR1_CHID2_Msk (_U_(0x1) << PWM_ISR1_CHID2_Pos) /**< (PWM_ISR1) Counter Event on Channel 2 Mask */ +#define PWM_ISR1_CHID2 PWM_ISR1_CHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_CHID2_Msk instead */ +#define PWM_ISR1_CHID3_Pos 3 /**< (PWM_ISR1) Counter Event on Channel 3 Position */ +#define PWM_ISR1_CHID3_Msk (_U_(0x1) << PWM_ISR1_CHID3_Pos) /**< (PWM_ISR1) Counter Event on Channel 3 Mask */ +#define PWM_ISR1_CHID3 PWM_ISR1_CHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_CHID3_Msk instead */ +#define PWM_ISR1_FCHID0_Pos 16 /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Position */ +#define PWM_ISR1_FCHID0_Msk (_U_(0x1) << PWM_ISR1_FCHID0_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Mask */ +#define PWM_ISR1_FCHID0 PWM_ISR1_FCHID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_FCHID0_Msk instead */ +#define PWM_ISR1_FCHID1_Pos 17 /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Position */ +#define PWM_ISR1_FCHID1_Msk (_U_(0x1) << PWM_ISR1_FCHID1_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Mask */ +#define PWM_ISR1_FCHID1 PWM_ISR1_FCHID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_FCHID1_Msk instead */ +#define PWM_ISR1_FCHID2_Pos 18 /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Position */ +#define PWM_ISR1_FCHID2_Msk (_U_(0x1) << PWM_ISR1_FCHID2_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Mask */ +#define PWM_ISR1_FCHID2 PWM_ISR1_FCHID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_FCHID2_Msk instead */ +#define PWM_ISR1_FCHID3_Pos 19 /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Position */ +#define PWM_ISR1_FCHID3_Msk (_U_(0x1) << PWM_ISR1_FCHID3_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Mask */ +#define PWM_ISR1_FCHID3 PWM_ISR1_FCHID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR1_FCHID3_Msk instead */ +#define PWM_ISR1_MASK _U_(0xF000F) /**< \deprecated (PWM_ISR1) Register MASK (Use PWM_ISR1_Msk instead) */ +#define PWM_ISR1_Msk _U_(0xF000F) /**< (PWM_ISR1) Register Mask */ + +#define PWM_ISR1_CHID_Pos 0 /**< (PWM_ISR1 Position) Counter Event on Channel x */ +#define PWM_ISR1_CHID_Msk (_U_(0xF) << PWM_ISR1_CHID_Pos) /**< (PWM_ISR1 Mask) CHID */ +#define PWM_ISR1_CHID(value) (PWM_ISR1_CHID_Msk & ((value) << PWM_ISR1_CHID_Pos)) +#define PWM_ISR1_FCHID_Pos 16 /**< (PWM_ISR1 Position) Fault Protection Trigger on Channel 3 */ +#define PWM_ISR1_FCHID_Msk (_U_(0xF) << PWM_ISR1_FCHID_Pos) /**< (PWM_ISR1 Mask) FCHID */ +#define PWM_ISR1_FCHID(value) (PWM_ISR1_FCHID_Msk & ((value) << PWM_ISR1_FCHID_Pos)) + +/* -------- PWM_SCM : (PWM Offset: 0x20) (R/W 32) PWM Sync Channels Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SYNC0:1; /**< bit: 0 Synchronous Channel 0 */ + uint32_t SYNC1:1; /**< bit: 1 Synchronous Channel 1 */ + uint32_t SYNC2:1; /**< bit: 2 Synchronous Channel 2 */ + uint32_t SYNC3:1; /**< bit: 3 Synchronous Channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t UPDM:2; /**< bit: 16..17 Synchronous Channels Update Mode */ + uint32_t :2; /**< bit: 18..19 Reserved */ + uint32_t PTRM:1; /**< bit: 20 DMA Controller Transfer Request Mode */ + uint32_t PTRCS:3; /**< bit: 21..23 DMA Controller Transfer Request Comparison Selection */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SYNC:4; /**< bit: 0..3 Synchronous Channel x */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SCM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SCM_OFFSET (0x20) /**< (PWM_SCM) PWM Sync Channels Mode Register Offset */ + +#define PWM_SCM_SYNC0_Pos 0 /**< (PWM_SCM) Synchronous Channel 0 Position */ +#define PWM_SCM_SYNC0_Msk (_U_(0x1) << PWM_SCM_SYNC0_Pos) /**< (PWM_SCM) Synchronous Channel 0 Mask */ +#define PWM_SCM_SYNC0 PWM_SCM_SYNC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCM_SYNC0_Msk instead */ +#define PWM_SCM_SYNC1_Pos 1 /**< (PWM_SCM) Synchronous Channel 1 Position */ +#define PWM_SCM_SYNC1_Msk (_U_(0x1) << PWM_SCM_SYNC1_Pos) /**< (PWM_SCM) Synchronous Channel 1 Mask */ +#define PWM_SCM_SYNC1 PWM_SCM_SYNC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCM_SYNC1_Msk instead */ +#define PWM_SCM_SYNC2_Pos 2 /**< (PWM_SCM) Synchronous Channel 2 Position */ +#define PWM_SCM_SYNC2_Msk (_U_(0x1) << PWM_SCM_SYNC2_Pos) /**< (PWM_SCM) Synchronous Channel 2 Mask */ +#define PWM_SCM_SYNC2 PWM_SCM_SYNC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCM_SYNC2_Msk instead */ +#define PWM_SCM_SYNC3_Pos 3 /**< (PWM_SCM) Synchronous Channel 3 Position */ +#define PWM_SCM_SYNC3_Msk (_U_(0x1) << PWM_SCM_SYNC3_Pos) /**< (PWM_SCM) Synchronous Channel 3 Mask */ +#define PWM_SCM_SYNC3 PWM_SCM_SYNC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCM_SYNC3_Msk instead */ +#define PWM_SCM_UPDM_Pos 16 /**< (PWM_SCM) Synchronous Channels Update Mode Position */ +#define PWM_SCM_UPDM_Msk (_U_(0x3) << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Synchronous Channels Update Mode Mask */ +#define PWM_SCM_UPDM(value) (PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)) +#define PWM_SCM_UPDM_MODE0_Val _U_(0x0) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1_Val _U_(0x1) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2_Val _U_(0x2) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE0 (PWM_SCM_UPDM_MODE0_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE1 (PWM_SCM_UPDM_MODE1_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE2 (PWM_SCM_UPDM_MODE2_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels Position */ +#define PWM_SCM_PTRM_Pos 20 /**< (PWM_SCM) DMA Controller Transfer Request Mode Position */ +#define PWM_SCM_PTRM_Msk (_U_(0x1) << PWM_SCM_PTRM_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Mode Mask */ +#define PWM_SCM_PTRM PWM_SCM_PTRM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCM_PTRM_Msk instead */ +#define PWM_SCM_PTRCS_Pos 21 /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Position */ +#define PWM_SCM_PTRCS_Msk (_U_(0x7) << PWM_SCM_PTRCS_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Mask */ +#define PWM_SCM_PTRCS(value) (PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)) +#define PWM_SCM_MASK _U_(0xF3000F) /**< \deprecated (PWM_SCM) Register MASK (Use PWM_SCM_Msk instead) */ +#define PWM_SCM_Msk _U_(0xF3000F) /**< (PWM_SCM) Register Mask */ + +#define PWM_SCM_SYNC_Pos 0 /**< (PWM_SCM Position) Synchronous Channel x */ +#define PWM_SCM_SYNC_Msk (_U_(0xF) << PWM_SCM_SYNC_Pos) /**< (PWM_SCM Mask) SYNC */ +#define PWM_SCM_SYNC(value) (PWM_SCM_SYNC_Msk & ((value) << PWM_SCM_SYNC_Pos)) + +/* -------- PWM_DMAR : (PWM Offset: 0x24) (/W 32) PWM DMA Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DMADUTY:24; /**< bit: 0..23 Duty-Cycle Holding Register for DMA Access */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_DMAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_DMAR_OFFSET (0x24) /**< (PWM_DMAR) PWM DMA Register Offset */ + +#define PWM_DMAR_DMADUTY_Pos 0 /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Position */ +#define PWM_DMAR_DMADUTY_Msk (_U_(0xFFFFFF) << PWM_DMAR_DMADUTY_Pos) /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Mask */ +#define PWM_DMAR_DMADUTY(value) (PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)) +#define PWM_DMAR_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_DMAR) Register MASK (Use PWM_DMAR_Msk instead) */ +#define PWM_DMAR_Msk _U_(0xFFFFFF) /**< (PWM_DMAR) Register Mask */ + + +/* -------- PWM_SCUC : (PWM Offset: 0x28) (R/W 32) PWM Sync Channels Update Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UPDULOCK:1; /**< bit: 0 Synchronous Channels Update Unlock */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SCUC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SCUC_OFFSET (0x28) /**< (PWM_SCUC) PWM Sync Channels Update Control Register Offset */ + +#define PWM_SCUC_UPDULOCK_Pos 0 /**< (PWM_SCUC) Synchronous Channels Update Unlock Position */ +#define PWM_SCUC_UPDULOCK_Msk (_U_(0x1) << PWM_SCUC_UPDULOCK_Pos) /**< (PWM_SCUC) Synchronous Channels Update Unlock Mask */ +#define PWM_SCUC_UPDULOCK PWM_SCUC_UPDULOCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SCUC_UPDULOCK_Msk instead */ +#define PWM_SCUC_MASK _U_(0x01) /**< \deprecated (PWM_SCUC) Register MASK (Use PWM_SCUC_Msk instead) */ +#define PWM_SCUC_Msk _U_(0x01) /**< (PWM_SCUC) Register Mask */ + + +/* -------- PWM_SCUP : (PWM Offset: 0x2c) (R/W 32) PWM Sync Channels Update Period Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UPR:4; /**< bit: 0..3 Update Period */ + uint32_t UPRCNT:4; /**< bit: 4..7 Update Period Counter */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SCUP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SCUP_OFFSET (0x2C) /**< (PWM_SCUP) PWM Sync Channels Update Period Register Offset */ + +#define PWM_SCUP_UPR_Pos 0 /**< (PWM_SCUP) Update Period Position */ +#define PWM_SCUP_UPR_Msk (_U_(0xF) << PWM_SCUP_UPR_Pos) /**< (PWM_SCUP) Update Period Mask */ +#define PWM_SCUP_UPR(value) (PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)) +#define PWM_SCUP_UPRCNT_Pos 4 /**< (PWM_SCUP) Update Period Counter Position */ +#define PWM_SCUP_UPRCNT_Msk (_U_(0xF) << PWM_SCUP_UPRCNT_Pos) /**< (PWM_SCUP) Update Period Counter Mask */ +#define PWM_SCUP_UPRCNT(value) (PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)) +#define PWM_SCUP_MASK _U_(0xFF) /**< \deprecated (PWM_SCUP) Register MASK (Use PWM_SCUP_Msk instead) */ +#define PWM_SCUP_Msk _U_(0xFF) /**< (PWM_SCUP) Register Mask */ + + +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) (/W 32) PWM Sync Channels Update Period Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UPRUPD:4; /**< bit: 0..3 Update Period Update */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SCUPUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SCUPUPD_OFFSET (0x30) /**< (PWM_SCUPUPD) PWM Sync Channels Update Period Update Register Offset */ + +#define PWM_SCUPUPD_UPRUPD_Pos 0 /**< (PWM_SCUPUPD) Update Period Update Position */ +#define PWM_SCUPUPD_UPRUPD_Msk (_U_(0xF) << PWM_SCUPUPD_UPRUPD_Pos) /**< (PWM_SCUPUPD) Update Period Update Mask */ +#define PWM_SCUPUPD_UPRUPD(value) (PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)) +#define PWM_SCUPUPD_MASK _U_(0x0F) /**< \deprecated (PWM_SCUPUPD) Register MASK (Use PWM_SCUPUPD_Msk instead) */ +#define PWM_SCUPUPD_Msk _U_(0x0F) /**< (PWM_SCUPUPD) Register Mask */ + + +/* -------- PWM_IER2 : (PWM Offset: 0x34) (/W 32) PWM Interrupt Enable Register 2 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WRDY:1; /**< bit: 0 Write Ready for Synchronous Channels Update Interrupt Enable */ + uint32_t :2; /**< bit: 1..2 Reserved */ + uint32_t UNRE:1; /**< bit: 3 Synchronous Channels Update Underrun Error Interrupt Enable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CMPM0:1; /**< bit: 8 Comparison 0 Match Interrupt Enable */ + uint32_t CMPM1:1; /**< bit: 9 Comparison 1 Match Interrupt Enable */ + uint32_t CMPM2:1; /**< bit: 10 Comparison 2 Match Interrupt Enable */ + uint32_t CMPM3:1; /**< bit: 11 Comparison 3 Match Interrupt Enable */ + uint32_t CMPM4:1; /**< bit: 12 Comparison 4 Match Interrupt Enable */ + uint32_t CMPM5:1; /**< bit: 13 Comparison 5 Match Interrupt Enable */ + uint32_t CMPM6:1; /**< bit: 14 Comparison 6 Match Interrupt Enable */ + uint32_t CMPM7:1; /**< bit: 15 Comparison 7 Match Interrupt Enable */ + uint32_t CMPU0:1; /**< bit: 16 Comparison 0 Update Interrupt Enable */ + uint32_t CMPU1:1; /**< bit: 17 Comparison 1 Update Interrupt Enable */ + uint32_t CMPU2:1; /**< bit: 18 Comparison 2 Update Interrupt Enable */ + uint32_t CMPU3:1; /**< bit: 19 Comparison 3 Update Interrupt Enable */ + uint32_t CMPU4:1; /**< bit: 20 Comparison 4 Update Interrupt Enable */ + uint32_t CMPU5:1; /**< bit: 21 Comparison 5 Update Interrupt Enable */ + uint32_t CMPU6:1; /**< bit: 22 Comparison 6 Update Interrupt Enable */ + uint32_t CMPU7:1; /**< bit: 23 Comparison 7 Update Interrupt Enable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CMPM:8; /**< bit: 8..15 Comparison x Match Interrupt Enable */ + uint32_t CMPU:8; /**< bit: 16..23 Comparison 7 Update Interrupt Enable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IER2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IER2_OFFSET (0x34) /**< (PWM_IER2) PWM Interrupt Enable Register 2 Offset */ + +#define PWM_IER2_WRDY_Pos 0 /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Position */ +#define PWM_IER2_WRDY_Msk (_U_(0x1) << PWM_IER2_WRDY_Pos) /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Mask */ +#define PWM_IER2_WRDY PWM_IER2_WRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_WRDY_Msk instead */ +#define PWM_IER2_UNRE_Pos 3 /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Position */ +#define PWM_IER2_UNRE_Msk (_U_(0x1) << PWM_IER2_UNRE_Pos) /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Mask */ +#define PWM_IER2_UNRE PWM_IER2_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_UNRE_Msk instead */ +#define PWM_IER2_CMPM0_Pos 8 /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM0_Msk (_U_(0x1) << PWM_IER2_CMPM0_Pos) /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM0 PWM_IER2_CMPM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM0_Msk instead */ +#define PWM_IER2_CMPM1_Pos 9 /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM1_Msk (_U_(0x1) << PWM_IER2_CMPM1_Pos) /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM1 PWM_IER2_CMPM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM1_Msk instead */ +#define PWM_IER2_CMPM2_Pos 10 /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM2_Msk (_U_(0x1) << PWM_IER2_CMPM2_Pos) /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM2 PWM_IER2_CMPM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM2_Msk instead */ +#define PWM_IER2_CMPM3_Pos 11 /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM3_Msk (_U_(0x1) << PWM_IER2_CMPM3_Pos) /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM3 PWM_IER2_CMPM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM3_Msk instead */ +#define PWM_IER2_CMPM4_Pos 12 /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM4_Msk (_U_(0x1) << PWM_IER2_CMPM4_Pos) /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM4 PWM_IER2_CMPM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM4_Msk instead */ +#define PWM_IER2_CMPM5_Pos 13 /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM5_Msk (_U_(0x1) << PWM_IER2_CMPM5_Pos) /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM5 PWM_IER2_CMPM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM5_Msk instead */ +#define PWM_IER2_CMPM6_Pos 14 /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM6_Msk (_U_(0x1) << PWM_IER2_CMPM6_Pos) /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM6 PWM_IER2_CMPM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM6_Msk instead */ +#define PWM_IER2_CMPM7_Pos 15 /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM7_Msk (_U_(0x1) << PWM_IER2_CMPM7_Pos) /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM7 PWM_IER2_CMPM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPM7_Msk instead */ +#define PWM_IER2_CMPU0_Pos 16 /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU0_Msk (_U_(0x1) << PWM_IER2_CMPU0_Pos) /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU0 PWM_IER2_CMPU0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU0_Msk instead */ +#define PWM_IER2_CMPU1_Pos 17 /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU1_Msk (_U_(0x1) << PWM_IER2_CMPU1_Pos) /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU1 PWM_IER2_CMPU1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU1_Msk instead */ +#define PWM_IER2_CMPU2_Pos 18 /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU2_Msk (_U_(0x1) << PWM_IER2_CMPU2_Pos) /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU2 PWM_IER2_CMPU2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU2_Msk instead */ +#define PWM_IER2_CMPU3_Pos 19 /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU3_Msk (_U_(0x1) << PWM_IER2_CMPU3_Pos) /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU3 PWM_IER2_CMPU3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU3_Msk instead */ +#define PWM_IER2_CMPU4_Pos 20 /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU4_Msk (_U_(0x1) << PWM_IER2_CMPU4_Pos) /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU4 PWM_IER2_CMPU4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU4_Msk instead */ +#define PWM_IER2_CMPU5_Pos 21 /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU5_Msk (_U_(0x1) << PWM_IER2_CMPU5_Pos) /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU5 PWM_IER2_CMPU5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU5_Msk instead */ +#define PWM_IER2_CMPU6_Pos 22 /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU6_Msk (_U_(0x1) << PWM_IER2_CMPU6_Pos) /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU6 PWM_IER2_CMPU6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU6_Msk instead */ +#define PWM_IER2_CMPU7_Pos 23 /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU7_Msk (_U_(0x1) << PWM_IER2_CMPU7_Pos) /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU7 PWM_IER2_CMPU7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IER2_CMPU7_Msk instead */ +#define PWM_IER2_MASK _U_(0xFFFF09) /**< \deprecated (PWM_IER2) Register MASK (Use PWM_IER2_Msk instead) */ +#define PWM_IER2_Msk _U_(0xFFFF09) /**< (PWM_IER2) Register Mask */ + +#define PWM_IER2_CMPM_Pos 8 /**< (PWM_IER2 Position) Comparison x Match Interrupt Enable */ +#define PWM_IER2_CMPM_Msk (_U_(0xFF) << PWM_IER2_CMPM_Pos) /**< (PWM_IER2 Mask) CMPM */ +#define PWM_IER2_CMPM(value) (PWM_IER2_CMPM_Msk & ((value) << PWM_IER2_CMPM_Pos)) +#define PWM_IER2_CMPU_Pos 16 /**< (PWM_IER2 Position) Comparison 7 Update Interrupt Enable */ +#define PWM_IER2_CMPU_Msk (_U_(0xFF) << PWM_IER2_CMPU_Pos) /**< (PWM_IER2 Mask) CMPU */ +#define PWM_IER2_CMPU(value) (PWM_IER2_CMPU_Msk & ((value) << PWM_IER2_CMPU_Pos)) + +/* -------- PWM_IDR2 : (PWM Offset: 0x38) (/W 32) PWM Interrupt Disable Register 2 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WRDY:1; /**< bit: 0 Write Ready for Synchronous Channels Update Interrupt Disable */ + uint32_t :2; /**< bit: 1..2 Reserved */ + uint32_t UNRE:1; /**< bit: 3 Synchronous Channels Update Underrun Error Interrupt Disable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CMPM0:1; /**< bit: 8 Comparison 0 Match Interrupt Disable */ + uint32_t CMPM1:1; /**< bit: 9 Comparison 1 Match Interrupt Disable */ + uint32_t CMPM2:1; /**< bit: 10 Comparison 2 Match Interrupt Disable */ + uint32_t CMPM3:1; /**< bit: 11 Comparison 3 Match Interrupt Disable */ + uint32_t CMPM4:1; /**< bit: 12 Comparison 4 Match Interrupt Disable */ + uint32_t CMPM5:1; /**< bit: 13 Comparison 5 Match Interrupt Disable */ + uint32_t CMPM6:1; /**< bit: 14 Comparison 6 Match Interrupt Disable */ + uint32_t CMPM7:1; /**< bit: 15 Comparison 7 Match Interrupt Disable */ + uint32_t CMPU0:1; /**< bit: 16 Comparison 0 Update Interrupt Disable */ + uint32_t CMPU1:1; /**< bit: 17 Comparison 1 Update Interrupt Disable */ + uint32_t CMPU2:1; /**< bit: 18 Comparison 2 Update Interrupt Disable */ + uint32_t CMPU3:1; /**< bit: 19 Comparison 3 Update Interrupt Disable */ + uint32_t CMPU4:1; /**< bit: 20 Comparison 4 Update Interrupt Disable */ + uint32_t CMPU5:1; /**< bit: 21 Comparison 5 Update Interrupt Disable */ + uint32_t CMPU6:1; /**< bit: 22 Comparison 6 Update Interrupt Disable */ + uint32_t CMPU7:1; /**< bit: 23 Comparison 7 Update Interrupt Disable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CMPM:8; /**< bit: 8..15 Comparison x Match Interrupt Disable */ + uint32_t CMPU:8; /**< bit: 16..23 Comparison 7 Update Interrupt Disable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IDR2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IDR2_OFFSET (0x38) /**< (PWM_IDR2) PWM Interrupt Disable Register 2 Offset */ + +#define PWM_IDR2_WRDY_Pos 0 /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Position */ +#define PWM_IDR2_WRDY_Msk (_U_(0x1) << PWM_IDR2_WRDY_Pos) /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Mask */ +#define PWM_IDR2_WRDY PWM_IDR2_WRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_WRDY_Msk instead */ +#define PWM_IDR2_UNRE_Pos 3 /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Position */ +#define PWM_IDR2_UNRE_Msk (_U_(0x1) << PWM_IDR2_UNRE_Pos) /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Mask */ +#define PWM_IDR2_UNRE PWM_IDR2_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_UNRE_Msk instead */ +#define PWM_IDR2_CMPM0_Pos 8 /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM0_Msk (_U_(0x1) << PWM_IDR2_CMPM0_Pos) /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM0 PWM_IDR2_CMPM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM0_Msk instead */ +#define PWM_IDR2_CMPM1_Pos 9 /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM1_Msk (_U_(0x1) << PWM_IDR2_CMPM1_Pos) /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM1 PWM_IDR2_CMPM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM1_Msk instead */ +#define PWM_IDR2_CMPM2_Pos 10 /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM2_Msk (_U_(0x1) << PWM_IDR2_CMPM2_Pos) /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM2 PWM_IDR2_CMPM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM2_Msk instead */ +#define PWM_IDR2_CMPM3_Pos 11 /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM3_Msk (_U_(0x1) << PWM_IDR2_CMPM3_Pos) /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM3 PWM_IDR2_CMPM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM3_Msk instead */ +#define PWM_IDR2_CMPM4_Pos 12 /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM4_Msk (_U_(0x1) << PWM_IDR2_CMPM4_Pos) /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM4 PWM_IDR2_CMPM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM4_Msk instead */ +#define PWM_IDR2_CMPM5_Pos 13 /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM5_Msk (_U_(0x1) << PWM_IDR2_CMPM5_Pos) /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM5 PWM_IDR2_CMPM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM5_Msk instead */ +#define PWM_IDR2_CMPM6_Pos 14 /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM6_Msk (_U_(0x1) << PWM_IDR2_CMPM6_Pos) /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM6 PWM_IDR2_CMPM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM6_Msk instead */ +#define PWM_IDR2_CMPM7_Pos 15 /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM7_Msk (_U_(0x1) << PWM_IDR2_CMPM7_Pos) /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM7 PWM_IDR2_CMPM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPM7_Msk instead */ +#define PWM_IDR2_CMPU0_Pos 16 /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU0_Msk (_U_(0x1) << PWM_IDR2_CMPU0_Pos) /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU0 PWM_IDR2_CMPU0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU0_Msk instead */ +#define PWM_IDR2_CMPU1_Pos 17 /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU1_Msk (_U_(0x1) << PWM_IDR2_CMPU1_Pos) /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU1 PWM_IDR2_CMPU1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU1_Msk instead */ +#define PWM_IDR2_CMPU2_Pos 18 /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU2_Msk (_U_(0x1) << PWM_IDR2_CMPU2_Pos) /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU2 PWM_IDR2_CMPU2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU2_Msk instead */ +#define PWM_IDR2_CMPU3_Pos 19 /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU3_Msk (_U_(0x1) << PWM_IDR2_CMPU3_Pos) /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU3 PWM_IDR2_CMPU3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU3_Msk instead */ +#define PWM_IDR2_CMPU4_Pos 20 /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU4_Msk (_U_(0x1) << PWM_IDR2_CMPU4_Pos) /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU4 PWM_IDR2_CMPU4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU4_Msk instead */ +#define PWM_IDR2_CMPU5_Pos 21 /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU5_Msk (_U_(0x1) << PWM_IDR2_CMPU5_Pos) /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU5 PWM_IDR2_CMPU5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU5_Msk instead */ +#define PWM_IDR2_CMPU6_Pos 22 /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU6_Msk (_U_(0x1) << PWM_IDR2_CMPU6_Pos) /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU6 PWM_IDR2_CMPU6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU6_Msk instead */ +#define PWM_IDR2_CMPU7_Pos 23 /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU7_Msk (_U_(0x1) << PWM_IDR2_CMPU7_Pos) /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU7 PWM_IDR2_CMPU7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IDR2_CMPU7_Msk instead */ +#define PWM_IDR2_MASK _U_(0xFFFF09) /**< \deprecated (PWM_IDR2) Register MASK (Use PWM_IDR2_Msk instead) */ +#define PWM_IDR2_Msk _U_(0xFFFF09) /**< (PWM_IDR2) Register Mask */ + +#define PWM_IDR2_CMPM_Pos 8 /**< (PWM_IDR2 Position) Comparison x Match Interrupt Disable */ +#define PWM_IDR2_CMPM_Msk (_U_(0xFF) << PWM_IDR2_CMPM_Pos) /**< (PWM_IDR2 Mask) CMPM */ +#define PWM_IDR2_CMPM(value) (PWM_IDR2_CMPM_Msk & ((value) << PWM_IDR2_CMPM_Pos)) +#define PWM_IDR2_CMPU_Pos 16 /**< (PWM_IDR2 Position) Comparison 7 Update Interrupt Disable */ +#define PWM_IDR2_CMPU_Msk (_U_(0xFF) << PWM_IDR2_CMPU_Pos) /**< (PWM_IDR2 Mask) CMPU */ +#define PWM_IDR2_CMPU(value) (PWM_IDR2_CMPU_Msk & ((value) << PWM_IDR2_CMPU_Pos)) + +/* -------- PWM_IMR2 : (PWM Offset: 0x3c) (R/ 32) PWM Interrupt Mask Register 2 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WRDY:1; /**< bit: 0 Write Ready for Synchronous Channels Update Interrupt Mask */ + uint32_t :2; /**< bit: 1..2 Reserved */ + uint32_t UNRE:1; /**< bit: 3 Synchronous Channels Update Underrun Error Interrupt Mask */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CMPM0:1; /**< bit: 8 Comparison 0 Match Interrupt Mask */ + uint32_t CMPM1:1; /**< bit: 9 Comparison 1 Match Interrupt Mask */ + uint32_t CMPM2:1; /**< bit: 10 Comparison 2 Match Interrupt Mask */ + uint32_t CMPM3:1; /**< bit: 11 Comparison 3 Match Interrupt Mask */ + uint32_t CMPM4:1; /**< bit: 12 Comparison 4 Match Interrupt Mask */ + uint32_t CMPM5:1; /**< bit: 13 Comparison 5 Match Interrupt Mask */ + uint32_t CMPM6:1; /**< bit: 14 Comparison 6 Match Interrupt Mask */ + uint32_t CMPM7:1; /**< bit: 15 Comparison 7 Match Interrupt Mask */ + uint32_t CMPU0:1; /**< bit: 16 Comparison 0 Update Interrupt Mask */ + uint32_t CMPU1:1; /**< bit: 17 Comparison 1 Update Interrupt Mask */ + uint32_t CMPU2:1; /**< bit: 18 Comparison 2 Update Interrupt Mask */ + uint32_t CMPU3:1; /**< bit: 19 Comparison 3 Update Interrupt Mask */ + uint32_t CMPU4:1; /**< bit: 20 Comparison 4 Update Interrupt Mask */ + uint32_t CMPU5:1; /**< bit: 21 Comparison 5 Update Interrupt Mask */ + uint32_t CMPU6:1; /**< bit: 22 Comparison 6 Update Interrupt Mask */ + uint32_t CMPU7:1; /**< bit: 23 Comparison 7 Update Interrupt Mask */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CMPM:8; /**< bit: 8..15 Comparison x Match Interrupt Mask */ + uint32_t CMPU:8; /**< bit: 16..23 Comparison 7 Update Interrupt Mask */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_IMR2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_IMR2_OFFSET (0x3C) /**< (PWM_IMR2) PWM Interrupt Mask Register 2 Offset */ + +#define PWM_IMR2_WRDY_Pos 0 /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Position */ +#define PWM_IMR2_WRDY_Msk (_U_(0x1) << PWM_IMR2_WRDY_Pos) /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Mask */ +#define PWM_IMR2_WRDY PWM_IMR2_WRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_WRDY_Msk instead */ +#define PWM_IMR2_UNRE_Pos 3 /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Position */ +#define PWM_IMR2_UNRE_Msk (_U_(0x1) << PWM_IMR2_UNRE_Pos) /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Mask */ +#define PWM_IMR2_UNRE PWM_IMR2_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_UNRE_Msk instead */ +#define PWM_IMR2_CMPM0_Pos 8 /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM0_Msk (_U_(0x1) << PWM_IMR2_CMPM0_Pos) /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM0 PWM_IMR2_CMPM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM0_Msk instead */ +#define PWM_IMR2_CMPM1_Pos 9 /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM1_Msk (_U_(0x1) << PWM_IMR2_CMPM1_Pos) /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM1 PWM_IMR2_CMPM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM1_Msk instead */ +#define PWM_IMR2_CMPM2_Pos 10 /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM2_Msk (_U_(0x1) << PWM_IMR2_CMPM2_Pos) /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM2 PWM_IMR2_CMPM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM2_Msk instead */ +#define PWM_IMR2_CMPM3_Pos 11 /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM3_Msk (_U_(0x1) << PWM_IMR2_CMPM3_Pos) /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM3 PWM_IMR2_CMPM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM3_Msk instead */ +#define PWM_IMR2_CMPM4_Pos 12 /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM4_Msk (_U_(0x1) << PWM_IMR2_CMPM4_Pos) /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM4 PWM_IMR2_CMPM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM4_Msk instead */ +#define PWM_IMR2_CMPM5_Pos 13 /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM5_Msk (_U_(0x1) << PWM_IMR2_CMPM5_Pos) /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM5 PWM_IMR2_CMPM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM5_Msk instead */ +#define PWM_IMR2_CMPM6_Pos 14 /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM6_Msk (_U_(0x1) << PWM_IMR2_CMPM6_Pos) /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM6 PWM_IMR2_CMPM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM6_Msk instead */ +#define PWM_IMR2_CMPM7_Pos 15 /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM7_Msk (_U_(0x1) << PWM_IMR2_CMPM7_Pos) /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM7 PWM_IMR2_CMPM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPM7_Msk instead */ +#define PWM_IMR2_CMPU0_Pos 16 /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU0_Msk (_U_(0x1) << PWM_IMR2_CMPU0_Pos) /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU0 PWM_IMR2_CMPU0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU0_Msk instead */ +#define PWM_IMR2_CMPU1_Pos 17 /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU1_Msk (_U_(0x1) << PWM_IMR2_CMPU1_Pos) /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU1 PWM_IMR2_CMPU1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU1_Msk instead */ +#define PWM_IMR2_CMPU2_Pos 18 /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU2_Msk (_U_(0x1) << PWM_IMR2_CMPU2_Pos) /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU2 PWM_IMR2_CMPU2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU2_Msk instead */ +#define PWM_IMR2_CMPU3_Pos 19 /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU3_Msk (_U_(0x1) << PWM_IMR2_CMPU3_Pos) /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU3 PWM_IMR2_CMPU3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU3_Msk instead */ +#define PWM_IMR2_CMPU4_Pos 20 /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU4_Msk (_U_(0x1) << PWM_IMR2_CMPU4_Pos) /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU4 PWM_IMR2_CMPU4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU4_Msk instead */ +#define PWM_IMR2_CMPU5_Pos 21 /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU5_Msk (_U_(0x1) << PWM_IMR2_CMPU5_Pos) /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU5 PWM_IMR2_CMPU5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU5_Msk instead */ +#define PWM_IMR2_CMPU6_Pos 22 /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU6_Msk (_U_(0x1) << PWM_IMR2_CMPU6_Pos) /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU6 PWM_IMR2_CMPU6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU6_Msk instead */ +#define PWM_IMR2_CMPU7_Pos 23 /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU7_Msk (_U_(0x1) << PWM_IMR2_CMPU7_Pos) /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU7 PWM_IMR2_CMPU7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_IMR2_CMPU7_Msk instead */ +#define PWM_IMR2_MASK _U_(0xFFFF09) /**< \deprecated (PWM_IMR2) Register MASK (Use PWM_IMR2_Msk instead) */ +#define PWM_IMR2_Msk _U_(0xFFFF09) /**< (PWM_IMR2) Register Mask */ + +#define PWM_IMR2_CMPM_Pos 8 /**< (PWM_IMR2 Position) Comparison x Match Interrupt Mask */ +#define PWM_IMR2_CMPM_Msk (_U_(0xFF) << PWM_IMR2_CMPM_Pos) /**< (PWM_IMR2 Mask) CMPM */ +#define PWM_IMR2_CMPM(value) (PWM_IMR2_CMPM_Msk & ((value) << PWM_IMR2_CMPM_Pos)) +#define PWM_IMR2_CMPU_Pos 16 /**< (PWM_IMR2 Position) Comparison 7 Update Interrupt Mask */ +#define PWM_IMR2_CMPU_Msk (_U_(0xFF) << PWM_IMR2_CMPU_Pos) /**< (PWM_IMR2 Mask) CMPU */ +#define PWM_IMR2_CMPU(value) (PWM_IMR2_CMPU_Msk & ((value) << PWM_IMR2_CMPU_Pos)) + +/* -------- PWM_ISR2 : (PWM Offset: 0x40) (R/ 32) PWM Interrupt Status Register 2 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WRDY:1; /**< bit: 0 Write Ready for Synchronous Channels Update */ + uint32_t :2; /**< bit: 1..2 Reserved */ + uint32_t UNRE:1; /**< bit: 3 Synchronous Channels Update Underrun Error */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CMPM0:1; /**< bit: 8 Comparison 0 Match */ + uint32_t CMPM1:1; /**< bit: 9 Comparison 1 Match */ + uint32_t CMPM2:1; /**< bit: 10 Comparison 2 Match */ + uint32_t CMPM3:1; /**< bit: 11 Comparison 3 Match */ + uint32_t CMPM4:1; /**< bit: 12 Comparison 4 Match */ + uint32_t CMPM5:1; /**< bit: 13 Comparison 5 Match */ + uint32_t CMPM6:1; /**< bit: 14 Comparison 6 Match */ + uint32_t CMPM7:1; /**< bit: 15 Comparison 7 Match */ + uint32_t CMPU0:1; /**< bit: 16 Comparison 0 Update */ + uint32_t CMPU1:1; /**< bit: 17 Comparison 1 Update */ + uint32_t CMPU2:1; /**< bit: 18 Comparison 2 Update */ + uint32_t CMPU3:1; /**< bit: 19 Comparison 3 Update */ + uint32_t CMPU4:1; /**< bit: 20 Comparison 4 Update */ + uint32_t CMPU5:1; /**< bit: 21 Comparison 5 Update */ + uint32_t CMPU6:1; /**< bit: 22 Comparison 6 Update */ + uint32_t CMPU7:1; /**< bit: 23 Comparison 7 Update */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CMPM:8; /**< bit: 8..15 Comparison x Match */ + uint32_t CMPU:8; /**< bit: 16..23 Comparison 7 Update */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ISR2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ISR2_OFFSET (0x40) /**< (PWM_ISR2) PWM Interrupt Status Register 2 Offset */ + +#define PWM_ISR2_WRDY_Pos 0 /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Position */ +#define PWM_ISR2_WRDY_Msk (_U_(0x1) << PWM_ISR2_WRDY_Pos) /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Mask */ +#define PWM_ISR2_WRDY PWM_ISR2_WRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_WRDY_Msk instead */ +#define PWM_ISR2_UNRE_Pos 3 /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Position */ +#define PWM_ISR2_UNRE_Msk (_U_(0x1) << PWM_ISR2_UNRE_Pos) /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Mask */ +#define PWM_ISR2_UNRE PWM_ISR2_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_UNRE_Msk instead */ +#define PWM_ISR2_CMPM0_Pos 8 /**< (PWM_ISR2) Comparison 0 Match Position */ +#define PWM_ISR2_CMPM0_Msk (_U_(0x1) << PWM_ISR2_CMPM0_Pos) /**< (PWM_ISR2) Comparison 0 Match Mask */ +#define PWM_ISR2_CMPM0 PWM_ISR2_CMPM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM0_Msk instead */ +#define PWM_ISR2_CMPM1_Pos 9 /**< (PWM_ISR2) Comparison 1 Match Position */ +#define PWM_ISR2_CMPM1_Msk (_U_(0x1) << PWM_ISR2_CMPM1_Pos) /**< (PWM_ISR2) Comparison 1 Match Mask */ +#define PWM_ISR2_CMPM1 PWM_ISR2_CMPM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM1_Msk instead */ +#define PWM_ISR2_CMPM2_Pos 10 /**< (PWM_ISR2) Comparison 2 Match Position */ +#define PWM_ISR2_CMPM2_Msk (_U_(0x1) << PWM_ISR2_CMPM2_Pos) /**< (PWM_ISR2) Comparison 2 Match Mask */ +#define PWM_ISR2_CMPM2 PWM_ISR2_CMPM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM2_Msk instead */ +#define PWM_ISR2_CMPM3_Pos 11 /**< (PWM_ISR2) Comparison 3 Match Position */ +#define PWM_ISR2_CMPM3_Msk (_U_(0x1) << PWM_ISR2_CMPM3_Pos) /**< (PWM_ISR2) Comparison 3 Match Mask */ +#define PWM_ISR2_CMPM3 PWM_ISR2_CMPM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM3_Msk instead */ +#define PWM_ISR2_CMPM4_Pos 12 /**< (PWM_ISR2) Comparison 4 Match Position */ +#define PWM_ISR2_CMPM4_Msk (_U_(0x1) << PWM_ISR2_CMPM4_Pos) /**< (PWM_ISR2) Comparison 4 Match Mask */ +#define PWM_ISR2_CMPM4 PWM_ISR2_CMPM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM4_Msk instead */ +#define PWM_ISR2_CMPM5_Pos 13 /**< (PWM_ISR2) Comparison 5 Match Position */ +#define PWM_ISR2_CMPM5_Msk (_U_(0x1) << PWM_ISR2_CMPM5_Pos) /**< (PWM_ISR2) Comparison 5 Match Mask */ +#define PWM_ISR2_CMPM5 PWM_ISR2_CMPM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM5_Msk instead */ +#define PWM_ISR2_CMPM6_Pos 14 /**< (PWM_ISR2) Comparison 6 Match Position */ +#define PWM_ISR2_CMPM6_Msk (_U_(0x1) << PWM_ISR2_CMPM6_Pos) /**< (PWM_ISR2) Comparison 6 Match Mask */ +#define PWM_ISR2_CMPM6 PWM_ISR2_CMPM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM6_Msk instead */ +#define PWM_ISR2_CMPM7_Pos 15 /**< (PWM_ISR2) Comparison 7 Match Position */ +#define PWM_ISR2_CMPM7_Msk (_U_(0x1) << PWM_ISR2_CMPM7_Pos) /**< (PWM_ISR2) Comparison 7 Match Mask */ +#define PWM_ISR2_CMPM7 PWM_ISR2_CMPM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPM7_Msk instead */ +#define PWM_ISR2_CMPU0_Pos 16 /**< (PWM_ISR2) Comparison 0 Update Position */ +#define PWM_ISR2_CMPU0_Msk (_U_(0x1) << PWM_ISR2_CMPU0_Pos) /**< (PWM_ISR2) Comparison 0 Update Mask */ +#define PWM_ISR2_CMPU0 PWM_ISR2_CMPU0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU0_Msk instead */ +#define PWM_ISR2_CMPU1_Pos 17 /**< (PWM_ISR2) Comparison 1 Update Position */ +#define PWM_ISR2_CMPU1_Msk (_U_(0x1) << PWM_ISR2_CMPU1_Pos) /**< (PWM_ISR2) Comparison 1 Update Mask */ +#define PWM_ISR2_CMPU1 PWM_ISR2_CMPU1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU1_Msk instead */ +#define PWM_ISR2_CMPU2_Pos 18 /**< (PWM_ISR2) Comparison 2 Update Position */ +#define PWM_ISR2_CMPU2_Msk (_U_(0x1) << PWM_ISR2_CMPU2_Pos) /**< (PWM_ISR2) Comparison 2 Update Mask */ +#define PWM_ISR2_CMPU2 PWM_ISR2_CMPU2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU2_Msk instead */ +#define PWM_ISR2_CMPU3_Pos 19 /**< (PWM_ISR2) Comparison 3 Update Position */ +#define PWM_ISR2_CMPU3_Msk (_U_(0x1) << PWM_ISR2_CMPU3_Pos) /**< (PWM_ISR2) Comparison 3 Update Mask */ +#define PWM_ISR2_CMPU3 PWM_ISR2_CMPU3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU3_Msk instead */ +#define PWM_ISR2_CMPU4_Pos 20 /**< (PWM_ISR2) Comparison 4 Update Position */ +#define PWM_ISR2_CMPU4_Msk (_U_(0x1) << PWM_ISR2_CMPU4_Pos) /**< (PWM_ISR2) Comparison 4 Update Mask */ +#define PWM_ISR2_CMPU4 PWM_ISR2_CMPU4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU4_Msk instead */ +#define PWM_ISR2_CMPU5_Pos 21 /**< (PWM_ISR2) Comparison 5 Update Position */ +#define PWM_ISR2_CMPU5_Msk (_U_(0x1) << PWM_ISR2_CMPU5_Pos) /**< (PWM_ISR2) Comparison 5 Update Mask */ +#define PWM_ISR2_CMPU5 PWM_ISR2_CMPU5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU5_Msk instead */ +#define PWM_ISR2_CMPU6_Pos 22 /**< (PWM_ISR2) Comparison 6 Update Position */ +#define PWM_ISR2_CMPU6_Msk (_U_(0x1) << PWM_ISR2_CMPU6_Pos) /**< (PWM_ISR2) Comparison 6 Update Mask */ +#define PWM_ISR2_CMPU6 PWM_ISR2_CMPU6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU6_Msk instead */ +#define PWM_ISR2_CMPU7_Pos 23 /**< (PWM_ISR2) Comparison 7 Update Position */ +#define PWM_ISR2_CMPU7_Msk (_U_(0x1) << PWM_ISR2_CMPU7_Pos) /**< (PWM_ISR2) Comparison 7 Update Mask */ +#define PWM_ISR2_CMPU7 PWM_ISR2_CMPU7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ISR2_CMPU7_Msk instead */ +#define PWM_ISR2_MASK _U_(0xFFFF09) /**< \deprecated (PWM_ISR2) Register MASK (Use PWM_ISR2_Msk instead) */ +#define PWM_ISR2_Msk _U_(0xFFFF09) /**< (PWM_ISR2) Register Mask */ + +#define PWM_ISR2_CMPM_Pos 8 /**< (PWM_ISR2 Position) Comparison x Match */ +#define PWM_ISR2_CMPM_Msk (_U_(0xFF) << PWM_ISR2_CMPM_Pos) /**< (PWM_ISR2 Mask) CMPM */ +#define PWM_ISR2_CMPM(value) (PWM_ISR2_CMPM_Msk & ((value) << PWM_ISR2_CMPM_Pos)) +#define PWM_ISR2_CMPU_Pos 16 /**< (PWM_ISR2 Position) Comparison 7 Update */ +#define PWM_ISR2_CMPU_Msk (_U_(0xFF) << PWM_ISR2_CMPU_Pos) /**< (PWM_ISR2 Mask) CMPU */ +#define PWM_ISR2_CMPU(value) (PWM_ISR2_CMPU_Msk & ((value) << PWM_ISR2_CMPU_Pos)) + +/* -------- PWM_OOV : (PWM Offset: 0x44) (R/W 32) PWM Output Override Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OOVH0:1; /**< bit: 0 Output Override Value for PWMH output of the channel 0 */ + uint32_t OOVH1:1; /**< bit: 1 Output Override Value for PWMH output of the channel 1 */ + uint32_t OOVH2:1; /**< bit: 2 Output Override Value for PWMH output of the channel 2 */ + uint32_t OOVH3:1; /**< bit: 3 Output Override Value for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OOVL0:1; /**< bit: 16 Output Override Value for PWML output of the channel 0 */ + uint32_t OOVL1:1; /**< bit: 17 Output Override Value for PWML output of the channel 1 */ + uint32_t OOVL2:1; /**< bit: 18 Output Override Value for PWML output of the channel 2 */ + uint32_t OOVL3:1; /**< bit: 19 Output Override Value for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OOVH:4; /**< bit: 0..3 Output Override Value for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OOVL:4; /**< bit: 16..19 Output Override Value for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OOV_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OOV_OFFSET (0x44) /**< (PWM_OOV) PWM Output Override Value Register Offset */ + +#define PWM_OOV_OOVH0_Pos 0 /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Position */ +#define PWM_OOV_OOVH0_Msk (_U_(0x1) << PWM_OOV_OOVH0_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Mask */ +#define PWM_OOV_OOVH0 PWM_OOV_OOVH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVH0_Msk instead */ +#define PWM_OOV_OOVH1_Pos 1 /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Position */ +#define PWM_OOV_OOVH1_Msk (_U_(0x1) << PWM_OOV_OOVH1_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Mask */ +#define PWM_OOV_OOVH1 PWM_OOV_OOVH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVH1_Msk instead */ +#define PWM_OOV_OOVH2_Pos 2 /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Position */ +#define PWM_OOV_OOVH2_Msk (_U_(0x1) << PWM_OOV_OOVH2_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Mask */ +#define PWM_OOV_OOVH2 PWM_OOV_OOVH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVH2_Msk instead */ +#define PWM_OOV_OOVH3_Pos 3 /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Position */ +#define PWM_OOV_OOVH3_Msk (_U_(0x1) << PWM_OOV_OOVH3_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Mask */ +#define PWM_OOV_OOVH3 PWM_OOV_OOVH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVH3_Msk instead */ +#define PWM_OOV_OOVL0_Pos 16 /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Position */ +#define PWM_OOV_OOVL0_Msk (_U_(0x1) << PWM_OOV_OOVL0_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Mask */ +#define PWM_OOV_OOVL0 PWM_OOV_OOVL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVL0_Msk instead */ +#define PWM_OOV_OOVL1_Pos 17 /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Position */ +#define PWM_OOV_OOVL1_Msk (_U_(0x1) << PWM_OOV_OOVL1_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Mask */ +#define PWM_OOV_OOVL1 PWM_OOV_OOVL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVL1_Msk instead */ +#define PWM_OOV_OOVL2_Pos 18 /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Position */ +#define PWM_OOV_OOVL2_Msk (_U_(0x1) << PWM_OOV_OOVL2_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Mask */ +#define PWM_OOV_OOVL2 PWM_OOV_OOVL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVL2_Msk instead */ +#define PWM_OOV_OOVL3_Pos 19 /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Position */ +#define PWM_OOV_OOVL3_Msk (_U_(0x1) << PWM_OOV_OOVL3_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Mask */ +#define PWM_OOV_OOVL3 PWM_OOV_OOVL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OOV_OOVL3_Msk instead */ +#define PWM_OOV_MASK _U_(0xF000F) /**< \deprecated (PWM_OOV) Register MASK (Use PWM_OOV_Msk instead) */ +#define PWM_OOV_Msk _U_(0xF000F) /**< (PWM_OOV) Register Mask */ + +#define PWM_OOV_OOVH_Pos 0 /**< (PWM_OOV Position) Output Override Value for PWMH output of the channel x */ +#define PWM_OOV_OOVH_Msk (_U_(0xF) << PWM_OOV_OOVH_Pos) /**< (PWM_OOV Mask) OOVH */ +#define PWM_OOV_OOVH(value) (PWM_OOV_OOVH_Msk & ((value) << PWM_OOV_OOVH_Pos)) +#define PWM_OOV_OOVL_Pos 16 /**< (PWM_OOV Position) Output Override Value for PWML output of the channel 3 */ +#define PWM_OOV_OOVL_Msk (_U_(0xF) << PWM_OOV_OOVL_Pos) /**< (PWM_OOV Mask) OOVL */ +#define PWM_OOV_OOVL(value) (PWM_OOV_OOVL_Msk & ((value) << PWM_OOV_OOVL_Pos)) + +/* -------- PWM_OS : (PWM Offset: 0x48) (R/W 32) PWM Output Selection Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OSH0:1; /**< bit: 0 Output Selection for PWMH output of the channel 0 */ + uint32_t OSH1:1; /**< bit: 1 Output Selection for PWMH output of the channel 1 */ + uint32_t OSH2:1; /**< bit: 2 Output Selection for PWMH output of the channel 2 */ + uint32_t OSH3:1; /**< bit: 3 Output Selection for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSL0:1; /**< bit: 16 Output Selection for PWML output of the channel 0 */ + uint32_t OSL1:1; /**< bit: 17 Output Selection for PWML output of the channel 1 */ + uint32_t OSL2:1; /**< bit: 18 Output Selection for PWML output of the channel 2 */ + uint32_t OSL3:1; /**< bit: 19 Output Selection for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OSH:4; /**< bit: 0..3 Output Selection for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSL:4; /**< bit: 16..19 Output Selection for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OS_OFFSET (0x48) /**< (PWM_OS) PWM Output Selection Register Offset */ + +#define PWM_OS_OSH0_Pos 0 /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Position */ +#define PWM_OS_OSH0_Msk (_U_(0x1) << PWM_OS_OSH0_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Mask */ +#define PWM_OS_OSH0 PWM_OS_OSH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSH0_Msk instead */ +#define PWM_OS_OSH1_Pos 1 /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Position */ +#define PWM_OS_OSH1_Msk (_U_(0x1) << PWM_OS_OSH1_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Mask */ +#define PWM_OS_OSH1 PWM_OS_OSH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSH1_Msk instead */ +#define PWM_OS_OSH2_Pos 2 /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Position */ +#define PWM_OS_OSH2_Msk (_U_(0x1) << PWM_OS_OSH2_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Mask */ +#define PWM_OS_OSH2 PWM_OS_OSH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSH2_Msk instead */ +#define PWM_OS_OSH3_Pos 3 /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Position */ +#define PWM_OS_OSH3_Msk (_U_(0x1) << PWM_OS_OSH3_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Mask */ +#define PWM_OS_OSH3 PWM_OS_OSH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSH3_Msk instead */ +#define PWM_OS_OSL0_Pos 16 /**< (PWM_OS) Output Selection for PWML output of the channel 0 Position */ +#define PWM_OS_OSL0_Msk (_U_(0x1) << PWM_OS_OSL0_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 0 Mask */ +#define PWM_OS_OSL0 PWM_OS_OSL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSL0_Msk instead */ +#define PWM_OS_OSL1_Pos 17 /**< (PWM_OS) Output Selection for PWML output of the channel 1 Position */ +#define PWM_OS_OSL1_Msk (_U_(0x1) << PWM_OS_OSL1_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 1 Mask */ +#define PWM_OS_OSL1 PWM_OS_OSL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSL1_Msk instead */ +#define PWM_OS_OSL2_Pos 18 /**< (PWM_OS) Output Selection for PWML output of the channel 2 Position */ +#define PWM_OS_OSL2_Msk (_U_(0x1) << PWM_OS_OSL2_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 2 Mask */ +#define PWM_OS_OSL2 PWM_OS_OSL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSL2_Msk instead */ +#define PWM_OS_OSL3_Pos 19 /**< (PWM_OS) Output Selection for PWML output of the channel 3 Position */ +#define PWM_OS_OSL3_Msk (_U_(0x1) << PWM_OS_OSL3_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 3 Mask */ +#define PWM_OS_OSL3 PWM_OS_OSL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OS_OSL3_Msk instead */ +#define PWM_OS_MASK _U_(0xF000F) /**< \deprecated (PWM_OS) Register MASK (Use PWM_OS_Msk instead) */ +#define PWM_OS_Msk _U_(0xF000F) /**< (PWM_OS) Register Mask */ + +#define PWM_OS_OSH_Pos 0 /**< (PWM_OS Position) Output Selection for PWMH output of the channel x */ +#define PWM_OS_OSH_Msk (_U_(0xF) << PWM_OS_OSH_Pos) /**< (PWM_OS Mask) OSH */ +#define PWM_OS_OSH(value) (PWM_OS_OSH_Msk & ((value) << PWM_OS_OSH_Pos)) +#define PWM_OS_OSL_Pos 16 /**< (PWM_OS Position) Output Selection for PWML output of the channel 3 */ +#define PWM_OS_OSL_Msk (_U_(0xF) << PWM_OS_OSL_Pos) /**< (PWM_OS Mask) OSL */ +#define PWM_OS_OSL(value) (PWM_OS_OSL_Msk & ((value) << PWM_OS_OSL_Pos)) + +/* -------- PWM_OSS : (PWM Offset: 0x4c) (/W 32) PWM Output Selection Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OSSH0:1; /**< bit: 0 Output Selection Set for PWMH output of the channel 0 */ + uint32_t OSSH1:1; /**< bit: 1 Output Selection Set for PWMH output of the channel 1 */ + uint32_t OSSH2:1; /**< bit: 2 Output Selection Set for PWMH output of the channel 2 */ + uint32_t OSSH3:1; /**< bit: 3 Output Selection Set for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSSL0:1; /**< bit: 16 Output Selection Set for PWML output of the channel 0 */ + uint32_t OSSL1:1; /**< bit: 17 Output Selection Set for PWML output of the channel 1 */ + uint32_t OSSL2:1; /**< bit: 18 Output Selection Set for PWML output of the channel 2 */ + uint32_t OSSL3:1; /**< bit: 19 Output Selection Set for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OSSH:4; /**< bit: 0..3 Output Selection Set for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSSL:4; /**< bit: 16..19 Output Selection Set for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OSS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OSS_OFFSET (0x4C) /**< (PWM_OSS) PWM Output Selection Set Register Offset */ + +#define PWM_OSS_OSSH0_Pos 0 /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSS_OSSH0_Msk (_U_(0x1) << PWM_OSS_OSSH0_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSS_OSSH0 PWM_OSS_OSSH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSH0_Msk instead */ +#define PWM_OSS_OSSH1_Pos 1 /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSS_OSSH1_Msk (_U_(0x1) << PWM_OSS_OSSH1_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSS_OSSH1 PWM_OSS_OSSH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSH1_Msk instead */ +#define PWM_OSS_OSSH2_Pos 2 /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSS_OSSH2_Msk (_U_(0x1) << PWM_OSS_OSSH2_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSS_OSSH2 PWM_OSS_OSSH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSH2_Msk instead */ +#define PWM_OSS_OSSH3_Pos 3 /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSS_OSSH3_Msk (_U_(0x1) << PWM_OSS_OSSH3_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSS_OSSH3 PWM_OSS_OSSH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSH3_Msk instead */ +#define PWM_OSS_OSSL0_Pos 16 /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSS_OSSL0_Msk (_U_(0x1) << PWM_OSS_OSSL0_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSS_OSSL0 PWM_OSS_OSSL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSL0_Msk instead */ +#define PWM_OSS_OSSL1_Pos 17 /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSS_OSSL1_Msk (_U_(0x1) << PWM_OSS_OSSL1_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSS_OSSL1 PWM_OSS_OSSL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSL1_Msk instead */ +#define PWM_OSS_OSSL2_Pos 18 /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSS_OSSL2_Msk (_U_(0x1) << PWM_OSS_OSSL2_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSS_OSSL2 PWM_OSS_OSSL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSL2_Msk instead */ +#define PWM_OSS_OSSL3_Pos 19 /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSS_OSSL3_Msk (_U_(0x1) << PWM_OSS_OSSL3_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSS_OSSL3 PWM_OSS_OSSL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSS_OSSL3_Msk instead */ +#define PWM_OSS_MASK _U_(0xF000F) /**< \deprecated (PWM_OSS) Register MASK (Use PWM_OSS_Msk instead) */ +#define PWM_OSS_Msk _U_(0xF000F) /**< (PWM_OSS) Register Mask */ + +#define PWM_OSS_OSSH_Pos 0 /**< (PWM_OSS Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSS_OSSH_Msk (_U_(0xF) << PWM_OSS_OSSH_Pos) /**< (PWM_OSS Mask) OSSH */ +#define PWM_OSS_OSSH(value) (PWM_OSS_OSSH_Msk & ((value) << PWM_OSS_OSSH_Pos)) +#define PWM_OSS_OSSL_Pos 16 /**< (PWM_OSS Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSS_OSSL_Msk (_U_(0xF) << PWM_OSS_OSSL_Pos) /**< (PWM_OSS Mask) OSSL */ +#define PWM_OSS_OSSL(value) (PWM_OSS_OSSL_Msk & ((value) << PWM_OSS_OSSL_Pos)) + +/* -------- PWM_OSC : (PWM Offset: 0x50) (/W 32) PWM Output Selection Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OSCH0:1; /**< bit: 0 Output Selection Clear for PWMH output of the channel 0 */ + uint32_t OSCH1:1; /**< bit: 1 Output Selection Clear for PWMH output of the channel 1 */ + uint32_t OSCH2:1; /**< bit: 2 Output Selection Clear for PWMH output of the channel 2 */ + uint32_t OSCH3:1; /**< bit: 3 Output Selection Clear for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSCL0:1; /**< bit: 16 Output Selection Clear for PWML output of the channel 0 */ + uint32_t OSCL1:1; /**< bit: 17 Output Selection Clear for PWML output of the channel 1 */ + uint32_t OSCL2:1; /**< bit: 18 Output Selection Clear for PWML output of the channel 2 */ + uint32_t OSCL3:1; /**< bit: 19 Output Selection Clear for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OSCH:4; /**< bit: 0..3 Output Selection Clear for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSCL:4; /**< bit: 16..19 Output Selection Clear for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OSC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OSC_OFFSET (0x50) /**< (PWM_OSC) PWM Output Selection Clear Register Offset */ + +#define PWM_OSC_OSCH0_Pos 0 /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSC_OSCH0_Msk (_U_(0x1) << PWM_OSC_OSCH0_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSC_OSCH0 PWM_OSC_OSCH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCH0_Msk instead */ +#define PWM_OSC_OSCH1_Pos 1 /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSC_OSCH1_Msk (_U_(0x1) << PWM_OSC_OSCH1_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSC_OSCH1 PWM_OSC_OSCH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCH1_Msk instead */ +#define PWM_OSC_OSCH2_Pos 2 /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSC_OSCH2_Msk (_U_(0x1) << PWM_OSC_OSCH2_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSC_OSCH2 PWM_OSC_OSCH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCH2_Msk instead */ +#define PWM_OSC_OSCH3_Pos 3 /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSC_OSCH3_Msk (_U_(0x1) << PWM_OSC_OSCH3_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSC_OSCH3 PWM_OSC_OSCH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCH3_Msk instead */ +#define PWM_OSC_OSCL0_Pos 16 /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSC_OSCL0_Msk (_U_(0x1) << PWM_OSC_OSCL0_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSC_OSCL0 PWM_OSC_OSCL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCL0_Msk instead */ +#define PWM_OSC_OSCL1_Pos 17 /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSC_OSCL1_Msk (_U_(0x1) << PWM_OSC_OSCL1_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSC_OSCL1 PWM_OSC_OSCL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCL1_Msk instead */ +#define PWM_OSC_OSCL2_Pos 18 /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSC_OSCL2_Msk (_U_(0x1) << PWM_OSC_OSCL2_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSC_OSCL2 PWM_OSC_OSCL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCL2_Msk instead */ +#define PWM_OSC_OSCL3_Pos 19 /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSC_OSCL3_Msk (_U_(0x1) << PWM_OSC_OSCL3_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSC_OSCL3 PWM_OSC_OSCL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSC_OSCL3_Msk instead */ +#define PWM_OSC_MASK _U_(0xF000F) /**< \deprecated (PWM_OSC) Register MASK (Use PWM_OSC_Msk instead) */ +#define PWM_OSC_Msk _U_(0xF000F) /**< (PWM_OSC) Register Mask */ + +#define PWM_OSC_OSCH_Pos 0 /**< (PWM_OSC Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSC_OSCH_Msk (_U_(0xF) << PWM_OSC_OSCH_Pos) /**< (PWM_OSC Mask) OSCH */ +#define PWM_OSC_OSCH(value) (PWM_OSC_OSCH_Msk & ((value) << PWM_OSC_OSCH_Pos)) +#define PWM_OSC_OSCL_Pos 16 /**< (PWM_OSC Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSC_OSCL_Msk (_U_(0xF) << PWM_OSC_OSCL_Pos) /**< (PWM_OSC Mask) OSCL */ +#define PWM_OSC_OSCL(value) (PWM_OSC_OSCL_Msk & ((value) << PWM_OSC_OSCL_Pos)) + +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) (/W 32) PWM Output Selection Set Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OSSUPH0:1; /**< bit: 0 Output Selection Set for PWMH output of the channel 0 */ + uint32_t OSSUPH1:1; /**< bit: 1 Output Selection Set for PWMH output of the channel 1 */ + uint32_t OSSUPH2:1; /**< bit: 2 Output Selection Set for PWMH output of the channel 2 */ + uint32_t OSSUPH3:1; /**< bit: 3 Output Selection Set for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSSUPL0:1; /**< bit: 16 Output Selection Set for PWML output of the channel 0 */ + uint32_t OSSUPL1:1; /**< bit: 17 Output Selection Set for PWML output of the channel 1 */ + uint32_t OSSUPL2:1; /**< bit: 18 Output Selection Set for PWML output of the channel 2 */ + uint32_t OSSUPL3:1; /**< bit: 19 Output Selection Set for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OSSUPH:4; /**< bit: 0..3 Output Selection Set for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSSUPL:4; /**< bit: 16..19 Output Selection Set for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OSSUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OSSUPD_OFFSET (0x54) /**< (PWM_OSSUPD) PWM Output Selection Set Update Register Offset */ + +#define PWM_OSSUPD_OSSUPH0_Pos 0 /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPH0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPH0 PWM_OSSUPD_OSSUPH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPH0_Msk instead */ +#define PWM_OSSUPD_OSSUPH1_Pos 1 /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPH1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPH1 PWM_OSSUPD_OSSUPH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPH1_Msk instead */ +#define PWM_OSSUPD_OSSUPH2_Pos 2 /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPH2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPH2 PWM_OSSUPD_OSSUPH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPH2_Msk instead */ +#define PWM_OSSUPD_OSSUPH3_Pos 3 /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPH3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPH3 PWM_OSSUPD_OSSUPH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPH3_Msk instead */ +#define PWM_OSSUPD_OSSUPL0_Pos 16 /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPL0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPL0 PWM_OSSUPD_OSSUPL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPL0_Msk instead */ +#define PWM_OSSUPD_OSSUPL1_Pos 17 /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPL1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPL1 PWM_OSSUPD_OSSUPL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPL1_Msk instead */ +#define PWM_OSSUPD_OSSUPL2_Pos 18 /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPL2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPL2 PWM_OSSUPD_OSSUPL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPL2_Msk instead */ +#define PWM_OSSUPD_OSSUPL3_Pos 19 /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPL3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPL3 PWM_OSSUPD_OSSUPL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSSUPD_OSSUPL3_Msk instead */ +#define PWM_OSSUPD_MASK _U_(0xF000F) /**< \deprecated (PWM_OSSUPD) Register MASK (Use PWM_OSSUPD_Msk instead) */ +#define PWM_OSSUPD_Msk _U_(0xF000F) /**< (PWM_OSSUPD) Register Mask */ + +#define PWM_OSSUPD_OSSUPH_Pos 0 /**< (PWM_OSSUPD Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSSUPD_OSSUPH_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPH_Pos) /**< (PWM_OSSUPD Mask) OSSUPH */ +#define PWM_OSSUPD_OSSUPH(value) (PWM_OSSUPD_OSSUPH_Msk & ((value) << PWM_OSSUPD_OSSUPH_Pos)) +#define PWM_OSSUPD_OSSUPL_Pos 16 /**< (PWM_OSSUPD Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPL_Pos) /**< (PWM_OSSUPD Mask) OSSUPL */ +#define PWM_OSSUPD_OSSUPL(value) (PWM_OSSUPD_OSSUPL_Msk & ((value) << PWM_OSSUPD_OSSUPL_Pos)) + +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) (/W 32) PWM Output Selection Clear Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t OSCUPH0:1; /**< bit: 0 Output Selection Clear for PWMH output of the channel 0 */ + uint32_t OSCUPH1:1; /**< bit: 1 Output Selection Clear for PWMH output of the channel 1 */ + uint32_t OSCUPH2:1; /**< bit: 2 Output Selection Clear for PWMH output of the channel 2 */ + uint32_t OSCUPH3:1; /**< bit: 3 Output Selection Clear for PWMH output of the channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSCUPL0:1; /**< bit: 16 Output Selection Clear for PWML output of the channel 0 */ + uint32_t OSCUPL1:1; /**< bit: 17 Output Selection Clear for PWML output of the channel 1 */ + uint32_t OSCUPL2:1; /**< bit: 18 Output Selection Clear for PWML output of the channel 2 */ + uint32_t OSCUPL3:1; /**< bit: 19 Output Selection Clear for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t OSCUPH:4; /**< bit: 0..3 Output Selection Clear for PWMH output of the channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t OSCUPL:4; /**< bit: 16..19 Output Selection Clear for PWML output of the channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_OSCUPD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_OSCUPD_OFFSET (0x58) /**< (PWM_OSCUPD) PWM Output Selection Clear Update Register Offset */ + +#define PWM_OSCUPD_OSCUPH0_Pos 0 /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPH0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPH0 PWM_OSCUPD_OSCUPH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPH0_Msk instead */ +#define PWM_OSCUPD_OSCUPH1_Pos 1 /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPH1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPH1 PWM_OSCUPD_OSCUPH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPH1_Msk instead */ +#define PWM_OSCUPD_OSCUPH2_Pos 2 /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPH2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPH2 PWM_OSCUPD_OSCUPH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPH2_Msk instead */ +#define PWM_OSCUPD_OSCUPH3_Pos 3 /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPH3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPH3 PWM_OSCUPD_OSCUPH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPH3_Msk instead */ +#define PWM_OSCUPD_OSCUPL0_Pos 16 /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPL0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPL0 PWM_OSCUPD_OSCUPL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPL0_Msk instead */ +#define PWM_OSCUPD_OSCUPL1_Pos 17 /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPL1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPL1 PWM_OSCUPD_OSCUPL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPL1_Msk instead */ +#define PWM_OSCUPD_OSCUPL2_Pos 18 /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPL2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPL2 PWM_OSCUPD_OSCUPL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPL2_Msk instead */ +#define PWM_OSCUPD_OSCUPL3_Pos 19 /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPL3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPL3 PWM_OSCUPD_OSCUPL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_OSCUPD_OSCUPL3_Msk instead */ +#define PWM_OSCUPD_MASK _U_(0xF000F) /**< \deprecated (PWM_OSCUPD) Register MASK (Use PWM_OSCUPD_Msk instead) */ +#define PWM_OSCUPD_Msk _U_(0xF000F) /**< (PWM_OSCUPD) Register Mask */ + +#define PWM_OSCUPD_OSCUPH_Pos 0 /**< (PWM_OSCUPD Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSCUPD_OSCUPH_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPH_Pos) /**< (PWM_OSCUPD Mask) OSCUPH */ +#define PWM_OSCUPD_OSCUPH(value) (PWM_OSCUPD_OSCUPH_Msk & ((value) << PWM_OSCUPD_OSCUPH_Pos)) +#define PWM_OSCUPD_OSCUPL_Pos 16 /**< (PWM_OSCUPD Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPL_Pos) /**< (PWM_OSCUPD Mask) OSCUPL */ +#define PWM_OSCUPD_OSCUPL(value) (PWM_OSCUPD_OSCUPL_Msk & ((value) << PWM_OSCUPD_OSCUPL_Pos)) + +/* -------- PWM_FMR : (PWM Offset: 0x5c) (R/W 32) PWM Fault Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FPOL:8; /**< bit: 0..7 Fault Polarity */ + uint32_t FMOD:8; /**< bit: 8..15 Fault Activation Mode */ + uint32_t FFIL:8; /**< bit: 16..23 Fault Filtering */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FMR_OFFSET (0x5C) /**< (PWM_FMR) PWM Fault Mode Register Offset */ + +#define PWM_FMR_FPOL_Pos 0 /**< (PWM_FMR) Fault Polarity Position */ +#define PWM_FMR_FPOL_Msk (_U_(0xFF) << PWM_FMR_FPOL_Pos) /**< (PWM_FMR) Fault Polarity Mask */ +#define PWM_FMR_FPOL(value) (PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)) +#define PWM_FMR_FMOD_Pos 8 /**< (PWM_FMR) Fault Activation Mode Position */ +#define PWM_FMR_FMOD_Msk (_U_(0xFF) << PWM_FMR_FMOD_Pos) /**< (PWM_FMR) Fault Activation Mode Mask */ +#define PWM_FMR_FMOD(value) (PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)) +#define PWM_FMR_FFIL_Pos 16 /**< (PWM_FMR) Fault Filtering Position */ +#define PWM_FMR_FFIL_Msk (_U_(0xFF) << PWM_FMR_FFIL_Pos) /**< (PWM_FMR) Fault Filtering Mask */ +#define PWM_FMR_FFIL(value) (PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)) +#define PWM_FMR_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_FMR) Register MASK (Use PWM_FMR_Msk instead) */ +#define PWM_FMR_Msk _U_(0xFFFFFF) /**< (PWM_FMR) Register Mask */ + + +/* -------- PWM_FSR : (PWM Offset: 0x60) (R/ 32) PWM Fault Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FIV:8; /**< bit: 0..7 Fault Input Value */ + uint32_t FS:8; /**< bit: 8..15 Fault Status */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FSR_OFFSET (0x60) /**< (PWM_FSR) PWM Fault Status Register Offset */ + +#define PWM_FSR_FIV_Pos 0 /**< (PWM_FSR) Fault Input Value Position */ +#define PWM_FSR_FIV_Msk (_U_(0xFF) << PWM_FSR_FIV_Pos) /**< (PWM_FSR) Fault Input Value Mask */ +#define PWM_FSR_FIV(value) (PWM_FSR_FIV_Msk & ((value) << PWM_FSR_FIV_Pos)) +#define PWM_FSR_FS_Pos 8 /**< (PWM_FSR) Fault Status Position */ +#define PWM_FSR_FS_Msk (_U_(0xFF) << PWM_FSR_FS_Pos) /**< (PWM_FSR) Fault Status Mask */ +#define PWM_FSR_FS(value) (PWM_FSR_FS_Msk & ((value) << PWM_FSR_FS_Pos)) +#define PWM_FSR_MASK _U_(0xFFFF) /**< \deprecated (PWM_FSR) Register MASK (Use PWM_FSR_Msk instead) */ +#define PWM_FSR_Msk _U_(0xFFFF) /**< (PWM_FSR) Register Mask */ + + +/* -------- PWM_FCR : (PWM Offset: 0x64) (/W 32) PWM Fault Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FCLR:8; /**< bit: 0..7 Fault Clear */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FCR_OFFSET (0x64) /**< (PWM_FCR) PWM Fault Clear Register Offset */ + +#define PWM_FCR_FCLR_Pos 0 /**< (PWM_FCR) Fault Clear Position */ +#define PWM_FCR_FCLR_Msk (_U_(0xFF) << PWM_FCR_FCLR_Pos) /**< (PWM_FCR) Fault Clear Mask */ +#define PWM_FCR_FCLR(value) (PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)) +#define PWM_FCR_MASK _U_(0xFF) /**< \deprecated (PWM_FCR) Register MASK (Use PWM_FCR_Msk instead) */ +#define PWM_FCR_Msk _U_(0xFF) /**< (PWM_FCR) Register Mask */ + + +/* -------- PWM_FPV1 : (PWM Offset: 0x68) (R/W 32) PWM Fault Protection Value Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FPVH0:1; /**< bit: 0 Fault Protection Value for PWMH output on channel 0 */ + uint32_t FPVH1:1; /**< bit: 1 Fault Protection Value for PWMH output on channel 1 */ + uint32_t FPVH2:1; /**< bit: 2 Fault Protection Value for PWMH output on channel 2 */ + uint32_t FPVH3:1; /**< bit: 3 Fault Protection Value for PWMH output on channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FPVL0:1; /**< bit: 16 Fault Protection Value for PWML output on channel 0 */ + uint32_t FPVL1:1; /**< bit: 17 Fault Protection Value for PWML output on channel 1 */ + uint32_t FPVL2:1; /**< bit: 18 Fault Protection Value for PWML output on channel 2 */ + uint32_t FPVL3:1; /**< bit: 19 Fault Protection Value for PWML output on channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t FPVH:4; /**< bit: 0..3 Fault Protection Value for PWMH output on channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FPVL:4; /**< bit: 16..19 Fault Protection Value for PWML output on channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FPV1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FPV1_OFFSET (0x68) /**< (PWM_FPV1) PWM Fault Protection Value Register 1 Offset */ + +#define PWM_FPV1_FPVH0_Pos 0 /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Position */ +#define PWM_FPV1_FPVH0_Msk (_U_(0x1) << PWM_FPV1_FPVH0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Mask */ +#define PWM_FPV1_FPVH0 PWM_FPV1_FPVH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVH0_Msk instead */ +#define PWM_FPV1_FPVH1_Pos 1 /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Position */ +#define PWM_FPV1_FPVH1_Msk (_U_(0x1) << PWM_FPV1_FPVH1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Mask */ +#define PWM_FPV1_FPVH1 PWM_FPV1_FPVH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVH1_Msk instead */ +#define PWM_FPV1_FPVH2_Pos 2 /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Position */ +#define PWM_FPV1_FPVH2_Msk (_U_(0x1) << PWM_FPV1_FPVH2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Mask */ +#define PWM_FPV1_FPVH2 PWM_FPV1_FPVH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVH2_Msk instead */ +#define PWM_FPV1_FPVH3_Pos 3 /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Position */ +#define PWM_FPV1_FPVH3_Msk (_U_(0x1) << PWM_FPV1_FPVH3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Mask */ +#define PWM_FPV1_FPVH3 PWM_FPV1_FPVH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVH3_Msk instead */ +#define PWM_FPV1_FPVL0_Pos 16 /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Position */ +#define PWM_FPV1_FPVL0_Msk (_U_(0x1) << PWM_FPV1_FPVL0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Mask */ +#define PWM_FPV1_FPVL0 PWM_FPV1_FPVL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVL0_Msk instead */ +#define PWM_FPV1_FPVL1_Pos 17 /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Position */ +#define PWM_FPV1_FPVL1_Msk (_U_(0x1) << PWM_FPV1_FPVL1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Mask */ +#define PWM_FPV1_FPVL1 PWM_FPV1_FPVL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVL1_Msk instead */ +#define PWM_FPV1_FPVL2_Pos 18 /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Position */ +#define PWM_FPV1_FPVL2_Msk (_U_(0x1) << PWM_FPV1_FPVL2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Mask */ +#define PWM_FPV1_FPVL2 PWM_FPV1_FPVL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVL2_Msk instead */ +#define PWM_FPV1_FPVL3_Pos 19 /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Position */ +#define PWM_FPV1_FPVL3_Msk (_U_(0x1) << PWM_FPV1_FPVL3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Mask */ +#define PWM_FPV1_FPVL3 PWM_FPV1_FPVL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV1_FPVL3_Msk instead */ +#define PWM_FPV1_MASK _U_(0xF000F) /**< \deprecated (PWM_FPV1) Register MASK (Use PWM_FPV1_Msk instead) */ +#define PWM_FPV1_Msk _U_(0xF000F) /**< (PWM_FPV1) Register Mask */ + +#define PWM_FPV1_FPVH_Pos 0 /**< (PWM_FPV1 Position) Fault Protection Value for PWMH output on channel x */ +#define PWM_FPV1_FPVH_Msk (_U_(0xF) << PWM_FPV1_FPVH_Pos) /**< (PWM_FPV1 Mask) FPVH */ +#define PWM_FPV1_FPVH(value) (PWM_FPV1_FPVH_Msk & ((value) << PWM_FPV1_FPVH_Pos)) +#define PWM_FPV1_FPVL_Pos 16 /**< (PWM_FPV1 Position) Fault Protection Value for PWML output on channel 3 */ +#define PWM_FPV1_FPVL_Msk (_U_(0xF) << PWM_FPV1_FPVL_Pos) /**< (PWM_FPV1 Mask) FPVL */ +#define PWM_FPV1_FPVL(value) (PWM_FPV1_FPVL_Msk & ((value) << PWM_FPV1_FPVL_Pos)) + +/* -------- PWM_FPE : (PWM Offset: 0x6c) (R/W 32) PWM Fault Protection Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FPE0:8; /**< bit: 0..7 Fault Protection Enable for channel 0 */ + uint32_t FPE1:8; /**< bit: 8..15 Fault Protection Enable for channel 1 */ + uint32_t FPE2:8; /**< bit: 16..23 Fault Protection Enable for channel 2 */ + uint32_t FPE3:8; /**< bit: 24..31 Fault Protection Enable for channel 3 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FPE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FPE_OFFSET (0x6C) /**< (PWM_FPE) PWM Fault Protection Enable Register Offset */ + +#define PWM_FPE_FPE0_Pos 0 /**< (PWM_FPE) Fault Protection Enable for channel 0 Position */ +#define PWM_FPE_FPE0_Msk (_U_(0xFF) << PWM_FPE_FPE0_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 0 Mask */ +#define PWM_FPE_FPE0(value) (PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)) +#define PWM_FPE_FPE1_Pos 8 /**< (PWM_FPE) Fault Protection Enable for channel 1 Position */ +#define PWM_FPE_FPE1_Msk (_U_(0xFF) << PWM_FPE_FPE1_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 1 Mask */ +#define PWM_FPE_FPE1(value) (PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)) +#define PWM_FPE_FPE2_Pos 16 /**< (PWM_FPE) Fault Protection Enable for channel 2 Position */ +#define PWM_FPE_FPE2_Msk (_U_(0xFF) << PWM_FPE_FPE2_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 2 Mask */ +#define PWM_FPE_FPE2(value) (PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)) +#define PWM_FPE_FPE3_Pos 24 /**< (PWM_FPE) Fault Protection Enable for channel 3 Position */ +#define PWM_FPE_FPE3_Msk (_U_(0xFF) << PWM_FPE_FPE3_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 3 Mask */ +#define PWM_FPE_FPE3(value) (PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)) +#define PWM_FPE_MASK _U_(0xFFFFFFFF) /**< \deprecated (PWM_FPE) Register MASK (Use PWM_FPE_Msk instead) */ +#define PWM_FPE_Msk _U_(0xFFFFFFFF) /**< (PWM_FPE) Register Mask */ + + +/* -------- PWM_ELMR : (PWM Offset: 0x7c) (R/W 32) PWM Event Line 0 Mode Register 0 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CSEL0:1; /**< bit: 0 Comparison 0 Selection */ + uint32_t CSEL1:1; /**< bit: 1 Comparison 1 Selection */ + uint32_t CSEL2:1; /**< bit: 2 Comparison 2 Selection */ + uint32_t CSEL3:1; /**< bit: 3 Comparison 3 Selection */ + uint32_t CSEL4:1; /**< bit: 4 Comparison 4 Selection */ + uint32_t CSEL5:1; /**< bit: 5 Comparison 5 Selection */ + uint32_t CSEL6:1; /**< bit: 6 Comparison 6 Selection */ + uint32_t CSEL7:1; /**< bit: 7 Comparison 7 Selection */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t CSEL:8; /**< bit: 0..7 Comparison 7 Selection */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ELMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ELMR_OFFSET (0x7C) /**< (PWM_ELMR) PWM Event Line 0 Mode Register 0 Offset */ + +#define PWM_ELMR_CSEL0_Pos 0 /**< (PWM_ELMR) Comparison 0 Selection Position */ +#define PWM_ELMR_CSEL0_Msk (_U_(0x1) << PWM_ELMR_CSEL0_Pos) /**< (PWM_ELMR) Comparison 0 Selection Mask */ +#define PWM_ELMR_CSEL0 PWM_ELMR_CSEL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL0_Msk instead */ +#define PWM_ELMR_CSEL1_Pos 1 /**< (PWM_ELMR) Comparison 1 Selection Position */ +#define PWM_ELMR_CSEL1_Msk (_U_(0x1) << PWM_ELMR_CSEL1_Pos) /**< (PWM_ELMR) Comparison 1 Selection Mask */ +#define PWM_ELMR_CSEL1 PWM_ELMR_CSEL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL1_Msk instead */ +#define PWM_ELMR_CSEL2_Pos 2 /**< (PWM_ELMR) Comparison 2 Selection Position */ +#define PWM_ELMR_CSEL2_Msk (_U_(0x1) << PWM_ELMR_CSEL2_Pos) /**< (PWM_ELMR) Comparison 2 Selection Mask */ +#define PWM_ELMR_CSEL2 PWM_ELMR_CSEL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL2_Msk instead */ +#define PWM_ELMR_CSEL3_Pos 3 /**< (PWM_ELMR) Comparison 3 Selection Position */ +#define PWM_ELMR_CSEL3_Msk (_U_(0x1) << PWM_ELMR_CSEL3_Pos) /**< (PWM_ELMR) Comparison 3 Selection Mask */ +#define PWM_ELMR_CSEL3 PWM_ELMR_CSEL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL3_Msk instead */ +#define PWM_ELMR_CSEL4_Pos 4 /**< (PWM_ELMR) Comparison 4 Selection Position */ +#define PWM_ELMR_CSEL4_Msk (_U_(0x1) << PWM_ELMR_CSEL4_Pos) /**< (PWM_ELMR) Comparison 4 Selection Mask */ +#define PWM_ELMR_CSEL4 PWM_ELMR_CSEL4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL4_Msk instead */ +#define PWM_ELMR_CSEL5_Pos 5 /**< (PWM_ELMR) Comparison 5 Selection Position */ +#define PWM_ELMR_CSEL5_Msk (_U_(0x1) << PWM_ELMR_CSEL5_Pos) /**< (PWM_ELMR) Comparison 5 Selection Mask */ +#define PWM_ELMR_CSEL5 PWM_ELMR_CSEL5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL5_Msk instead */ +#define PWM_ELMR_CSEL6_Pos 6 /**< (PWM_ELMR) Comparison 6 Selection Position */ +#define PWM_ELMR_CSEL6_Msk (_U_(0x1) << PWM_ELMR_CSEL6_Pos) /**< (PWM_ELMR) Comparison 6 Selection Mask */ +#define PWM_ELMR_CSEL6 PWM_ELMR_CSEL6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL6_Msk instead */ +#define PWM_ELMR_CSEL7_Pos 7 /**< (PWM_ELMR) Comparison 7 Selection Position */ +#define PWM_ELMR_CSEL7_Msk (_U_(0x1) << PWM_ELMR_CSEL7_Pos) /**< (PWM_ELMR) Comparison 7 Selection Mask */ +#define PWM_ELMR_CSEL7 PWM_ELMR_CSEL7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ELMR_CSEL7_Msk instead */ +#define PWM_ELMR_MASK _U_(0xFF) /**< \deprecated (PWM_ELMR) Register MASK (Use PWM_ELMR_Msk instead) */ +#define PWM_ELMR_Msk _U_(0xFF) /**< (PWM_ELMR) Register Mask */ + +#define PWM_ELMR_CSEL_Pos 0 /**< (PWM_ELMR Position) Comparison 7 Selection */ +#define PWM_ELMR_CSEL_Msk (_U_(0xFF) << PWM_ELMR_CSEL_Pos) /**< (PWM_ELMR Mask) CSEL */ +#define PWM_ELMR_CSEL(value) (PWM_ELMR_CSEL_Msk & ((value) << PWM_ELMR_CSEL_Pos)) + +/* -------- PWM_SSPR : (PWM Offset: 0xa0) (R/W 32) PWM Spread Spectrum Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SPRD:24; /**< bit: 0..23 Spread Spectrum Limit Value */ + uint32_t SPRDM:1; /**< bit: 24 Spread Spectrum Counter Mode */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SSPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SSPR_OFFSET (0xA0) /**< (PWM_SSPR) PWM Spread Spectrum Register Offset */ + +#define PWM_SSPR_SPRD_Pos 0 /**< (PWM_SSPR) Spread Spectrum Limit Value Position */ +#define PWM_SSPR_SPRD_Msk (_U_(0xFFFFFF) << PWM_SSPR_SPRD_Pos) /**< (PWM_SSPR) Spread Spectrum Limit Value Mask */ +#define PWM_SSPR_SPRD(value) (PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)) +#define PWM_SSPR_SPRDM_Pos 24 /**< (PWM_SSPR) Spread Spectrum Counter Mode Position */ +#define PWM_SSPR_SPRDM_Msk (_U_(0x1) << PWM_SSPR_SPRDM_Pos) /**< (PWM_SSPR) Spread Spectrum Counter Mode Mask */ +#define PWM_SSPR_SPRDM PWM_SSPR_SPRDM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SSPR_SPRDM_Msk instead */ +#define PWM_SSPR_MASK _U_(0x1FFFFFF) /**< \deprecated (PWM_SSPR) Register MASK (Use PWM_SSPR_Msk instead) */ +#define PWM_SSPR_Msk _U_(0x1FFFFFF) /**< (PWM_SSPR) Register Mask */ + + +/* -------- PWM_SSPUP : (PWM Offset: 0xa4) (/W 32) PWM Spread Spectrum Update Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SPRDUP:24; /**< bit: 0..23 Spread Spectrum Limit Value Update */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SSPUP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SSPUP_OFFSET (0xA4) /**< (PWM_SSPUP) PWM Spread Spectrum Update Register Offset */ + +#define PWM_SSPUP_SPRDUP_Pos 0 /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Position */ +#define PWM_SSPUP_SPRDUP_Msk (_U_(0xFFFFFF) << PWM_SSPUP_SPRDUP_Pos) /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Mask */ +#define PWM_SSPUP_SPRDUP(value) (PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)) +#define PWM_SSPUP_MASK _U_(0xFFFFFF) /**< \deprecated (PWM_SSPUP) Register MASK (Use PWM_SSPUP_Msk instead) */ +#define PWM_SSPUP_Msk _U_(0xFFFFFF) /**< (PWM_SSPUP) Register Mask */ + + +/* -------- PWM_SMMR : (PWM Offset: 0xb0) (R/W 32) PWM Stepper Motor Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t GCEN0:1; /**< bit: 0 Gray Count ENable */ + uint32_t GCEN1:1; /**< bit: 1 Gray Count ENable */ + uint32_t :14; /**< bit: 2..15 Reserved */ + uint32_t DOWN0:1; /**< bit: 16 DOWN Count */ + uint32_t DOWN1:1; /**< bit: 17 DOWN Count */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t GCEN:2; /**< bit: 0..1 Gray Count ENable */ + uint32_t :14; /**< bit: 2..15 Reserved */ + uint32_t DOWN:2; /**< bit: 16..17 DOWN Count */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_SMMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_SMMR_OFFSET (0xB0) /**< (PWM_SMMR) PWM Stepper Motor Mode Register Offset */ + +#define PWM_SMMR_GCEN0_Pos 0 /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN0_Msk (_U_(0x1) << PWM_SMMR_GCEN0_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN0 PWM_SMMR_GCEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SMMR_GCEN0_Msk instead */ +#define PWM_SMMR_GCEN1_Pos 1 /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN1_Msk (_U_(0x1) << PWM_SMMR_GCEN1_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN1 PWM_SMMR_GCEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SMMR_GCEN1_Msk instead */ +#define PWM_SMMR_DOWN0_Pos 16 /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN0_Msk (_U_(0x1) << PWM_SMMR_DOWN0_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN0 PWM_SMMR_DOWN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SMMR_DOWN0_Msk instead */ +#define PWM_SMMR_DOWN1_Pos 17 /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN1_Msk (_U_(0x1) << PWM_SMMR_DOWN1_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN1 PWM_SMMR_DOWN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_SMMR_DOWN1_Msk instead */ +#define PWM_SMMR_MASK _U_(0x30003) /**< \deprecated (PWM_SMMR) Register MASK (Use PWM_SMMR_Msk instead) */ +#define PWM_SMMR_Msk _U_(0x30003) /**< (PWM_SMMR) Register Mask */ + +#define PWM_SMMR_GCEN_Pos 0 /**< (PWM_SMMR Position) Gray Count ENable */ +#define PWM_SMMR_GCEN_Msk (_U_(0x3) << PWM_SMMR_GCEN_Pos) /**< (PWM_SMMR Mask) GCEN */ +#define PWM_SMMR_GCEN(value) (PWM_SMMR_GCEN_Msk & ((value) << PWM_SMMR_GCEN_Pos)) +#define PWM_SMMR_DOWN_Pos 16 /**< (PWM_SMMR Position) DOWN Count */ +#define PWM_SMMR_DOWN_Msk (_U_(0x3) << PWM_SMMR_DOWN_Pos) /**< (PWM_SMMR Mask) DOWN */ +#define PWM_SMMR_DOWN(value) (PWM_SMMR_DOWN_Msk & ((value) << PWM_SMMR_DOWN_Pos)) + +/* -------- PWM_FPV2 : (PWM Offset: 0xc0) (R/W 32) PWM Fault Protection Value 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FPZH0:1; /**< bit: 0 Fault Protection to Hi-Z for PWMH output on channel 0 */ + uint32_t FPZH1:1; /**< bit: 1 Fault Protection to Hi-Z for PWMH output on channel 1 */ + uint32_t FPZH2:1; /**< bit: 2 Fault Protection to Hi-Z for PWMH output on channel 2 */ + uint32_t FPZH3:1; /**< bit: 3 Fault Protection to Hi-Z for PWMH output on channel 3 */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FPZL0:1; /**< bit: 16 Fault Protection to Hi-Z for PWML output on channel 0 */ + uint32_t FPZL1:1; /**< bit: 17 Fault Protection to Hi-Z for PWML output on channel 1 */ + uint32_t FPZL2:1; /**< bit: 18 Fault Protection to Hi-Z for PWML output on channel 2 */ + uint32_t FPZL3:1; /**< bit: 19 Fault Protection to Hi-Z for PWML output on channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t FPZH:4; /**< bit: 0..3 Fault Protection to Hi-Z for PWMH output on channel x */ + uint32_t :12; /**< bit: 4..15 Reserved */ + uint32_t FPZL:4; /**< bit: 16..19 Fault Protection to Hi-Z for PWML output on channel 3 */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_FPV2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_FPV2_OFFSET (0xC0) /**< (PWM_FPV2) PWM Fault Protection Value 2 Register Offset */ + +#define PWM_FPV2_FPZH0_Pos 0 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Position */ +#define PWM_FPV2_FPZH0_Msk (_U_(0x1) << PWM_FPV2_FPZH0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Mask */ +#define PWM_FPV2_FPZH0 PWM_FPV2_FPZH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZH0_Msk instead */ +#define PWM_FPV2_FPZH1_Pos 1 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Position */ +#define PWM_FPV2_FPZH1_Msk (_U_(0x1) << PWM_FPV2_FPZH1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Mask */ +#define PWM_FPV2_FPZH1 PWM_FPV2_FPZH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZH1_Msk instead */ +#define PWM_FPV2_FPZH2_Pos 2 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Position */ +#define PWM_FPV2_FPZH2_Msk (_U_(0x1) << PWM_FPV2_FPZH2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Mask */ +#define PWM_FPV2_FPZH2 PWM_FPV2_FPZH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZH2_Msk instead */ +#define PWM_FPV2_FPZH3_Pos 3 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Position */ +#define PWM_FPV2_FPZH3_Msk (_U_(0x1) << PWM_FPV2_FPZH3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Mask */ +#define PWM_FPV2_FPZH3 PWM_FPV2_FPZH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZH3_Msk instead */ +#define PWM_FPV2_FPZL0_Pos 16 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Position */ +#define PWM_FPV2_FPZL0_Msk (_U_(0x1) << PWM_FPV2_FPZL0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Mask */ +#define PWM_FPV2_FPZL0 PWM_FPV2_FPZL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZL0_Msk instead */ +#define PWM_FPV2_FPZL1_Pos 17 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Position */ +#define PWM_FPV2_FPZL1_Msk (_U_(0x1) << PWM_FPV2_FPZL1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Mask */ +#define PWM_FPV2_FPZL1 PWM_FPV2_FPZL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZL1_Msk instead */ +#define PWM_FPV2_FPZL2_Pos 18 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Position */ +#define PWM_FPV2_FPZL2_Msk (_U_(0x1) << PWM_FPV2_FPZL2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Mask */ +#define PWM_FPV2_FPZL2 PWM_FPV2_FPZL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZL2_Msk instead */ +#define PWM_FPV2_FPZL3_Pos 19 /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Position */ +#define PWM_FPV2_FPZL3_Msk (_U_(0x1) << PWM_FPV2_FPZL3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Mask */ +#define PWM_FPV2_FPZL3 PWM_FPV2_FPZL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_FPV2_FPZL3_Msk instead */ +#define PWM_FPV2_MASK _U_(0xF000F) /**< \deprecated (PWM_FPV2) Register MASK (Use PWM_FPV2_Msk instead) */ +#define PWM_FPV2_Msk _U_(0xF000F) /**< (PWM_FPV2) Register Mask */ + +#define PWM_FPV2_FPZH_Pos 0 /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWMH output on channel x */ +#define PWM_FPV2_FPZH_Msk (_U_(0xF) << PWM_FPV2_FPZH_Pos) /**< (PWM_FPV2 Mask) FPZH */ +#define PWM_FPV2_FPZH(value) (PWM_FPV2_FPZH_Msk & ((value) << PWM_FPV2_FPZH_Pos)) +#define PWM_FPV2_FPZL_Pos 16 /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWML output on channel 3 */ +#define PWM_FPV2_FPZL_Msk (_U_(0xF) << PWM_FPV2_FPZL_Pos) /**< (PWM_FPV2 Mask) FPZL */ +#define PWM_FPV2_FPZL(value) (PWM_FPV2_FPZL_Msk & ((value) << PWM_FPV2_FPZL_Pos)) + +/* -------- PWM_WPCR : (PWM Offset: 0xe4) (/W 32) PWM Write Protection Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPCMD:2; /**< bit: 0..1 Write Protection Command */ + uint32_t WPRG0:1; /**< bit: 2 Write Protection Register Group 0 */ + uint32_t WPRG1:1; /**< bit: 3 Write Protection Register Group 1 */ + uint32_t WPRG2:1; /**< bit: 4 Write Protection Register Group 2 */ + uint32_t WPRG3:1; /**< bit: 5 Write Protection Register Group 3 */ + uint32_t WPRG4:1; /**< bit: 6 Write Protection Register Group 4 */ + uint32_t WPRG5:1; /**< bit: 7 Write Protection Register Group 5 */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t WPRG:6; /**< bit: 2..7 Write Protection Register Group x */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_WPCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_WPCR_OFFSET (0xE4) /**< (PWM_WPCR) PWM Write Protection Control Register Offset */ + +#define PWM_WPCR_WPCMD_Pos 0 /**< (PWM_WPCR) Write Protection Command Position */ +#define PWM_WPCR_WPCMD_Msk (_U_(0x3) << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Write Protection Command Mask */ +#define PWM_WPCR_WPCMD(value) (PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val _U_(0x0) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val _U_(0x1) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val _U_(0x2) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. Position */ +#define PWM_WPCR_WPRG0_Pos 2 /**< (PWM_WPCR) Write Protection Register Group 0 Position */ +#define PWM_WPCR_WPRG0_Msk (_U_(0x1) << PWM_WPCR_WPRG0_Pos) /**< (PWM_WPCR) Write Protection Register Group 0 Mask */ +#define PWM_WPCR_WPRG0 PWM_WPCR_WPRG0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG0_Msk instead */ +#define PWM_WPCR_WPRG1_Pos 3 /**< (PWM_WPCR) Write Protection Register Group 1 Position */ +#define PWM_WPCR_WPRG1_Msk (_U_(0x1) << PWM_WPCR_WPRG1_Pos) /**< (PWM_WPCR) Write Protection Register Group 1 Mask */ +#define PWM_WPCR_WPRG1 PWM_WPCR_WPRG1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG1_Msk instead */ +#define PWM_WPCR_WPRG2_Pos 4 /**< (PWM_WPCR) Write Protection Register Group 2 Position */ +#define PWM_WPCR_WPRG2_Msk (_U_(0x1) << PWM_WPCR_WPRG2_Pos) /**< (PWM_WPCR) Write Protection Register Group 2 Mask */ +#define PWM_WPCR_WPRG2 PWM_WPCR_WPRG2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG2_Msk instead */ +#define PWM_WPCR_WPRG3_Pos 5 /**< (PWM_WPCR) Write Protection Register Group 3 Position */ +#define PWM_WPCR_WPRG3_Msk (_U_(0x1) << PWM_WPCR_WPRG3_Pos) /**< (PWM_WPCR) Write Protection Register Group 3 Mask */ +#define PWM_WPCR_WPRG3 PWM_WPCR_WPRG3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG3_Msk instead */ +#define PWM_WPCR_WPRG4_Pos 6 /**< (PWM_WPCR) Write Protection Register Group 4 Position */ +#define PWM_WPCR_WPRG4_Msk (_U_(0x1) << PWM_WPCR_WPRG4_Pos) /**< (PWM_WPCR) Write Protection Register Group 4 Mask */ +#define PWM_WPCR_WPRG4 PWM_WPCR_WPRG4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG4_Msk instead */ +#define PWM_WPCR_WPRG5_Pos 7 /**< (PWM_WPCR) Write Protection Register Group 5 Position */ +#define PWM_WPCR_WPRG5_Msk (_U_(0x1) << PWM_WPCR_WPRG5_Pos) /**< (PWM_WPCR) Write Protection Register Group 5 Mask */ +#define PWM_WPCR_WPRG5 PWM_WPCR_WPRG5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPCR_WPRG5_Msk instead */ +#define PWM_WPCR_WPKEY_Pos 8 /**< (PWM_WPCR) Write Protection Key Position */ +#define PWM_WPCR_WPKEY_Msk (_U_(0xFFFFFF) << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Write Protection Key Mask */ +#define PWM_WPCR_WPKEY(value) (PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)) +#define PWM_WPCR_WPKEY_PASSWD_Val _U_(0x50574D) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +#define PWM_WPCR_WPKEY_PASSWD (PWM_WPCR_WPKEY_PASSWD_Val << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 Position */ +#define PWM_WPCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (PWM_WPCR) Register MASK (Use PWM_WPCR_Msk instead) */ +#define PWM_WPCR_Msk _U_(0xFFFFFFFF) /**< (PWM_WPCR) Register Mask */ + +#define PWM_WPCR_WPRG_Pos 2 /**< (PWM_WPCR Position) Write Protection Register Group x */ +#define PWM_WPCR_WPRG_Msk (_U_(0x3F) << PWM_WPCR_WPRG_Pos) /**< (PWM_WPCR Mask) WPRG */ +#define PWM_WPCR_WPRG(value) (PWM_WPCR_WPRG_Msk & ((value) << PWM_WPCR_WPRG_Pos)) + +/* -------- PWM_WPSR : (PWM Offset: 0xe8) (R/ 32) PWM Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPSWS0:1; /**< bit: 0 Write Protect SW Status */ + uint32_t WPSWS1:1; /**< bit: 1 Write Protect SW Status */ + uint32_t WPSWS2:1; /**< bit: 2 Write Protect SW Status */ + uint32_t WPSWS3:1; /**< bit: 3 Write Protect SW Status */ + uint32_t WPSWS4:1; /**< bit: 4 Write Protect SW Status */ + uint32_t WPSWS5:1; /**< bit: 5 Write Protect SW Status */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t WPVS:1; /**< bit: 7 Write Protect Violation Status */ + uint32_t WPHWS0:1; /**< bit: 8 Write Protect HW Status */ + uint32_t WPHWS1:1; /**< bit: 9 Write Protect HW Status */ + uint32_t WPHWS2:1; /**< bit: 10 Write Protect HW Status */ + uint32_t WPHWS3:1; /**< bit: 11 Write Protect HW Status */ + uint32_t WPHWS4:1; /**< bit: 12 Write Protect HW Status */ + uint32_t WPHWS5:1; /**< bit: 13 Write Protect HW Status */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t WPVSRC:16; /**< bit: 16..31 Write Protect Violation Source */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t WPSWS:6; /**< bit: 0..5 Write Protect SW Status */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t WPHWS:6; /**< bit: 8..13 Write Protect HW Status */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} PWM_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_WPSR_OFFSET (0xE8) /**< (PWM_WPSR) PWM Write Protection Status Register Offset */ + +#define PWM_WPSR_WPSWS0_Pos 0 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS0_Msk (_U_(0x1) << PWM_WPSR_WPSWS0_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS0 PWM_WPSR_WPSWS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS0_Msk instead */ +#define PWM_WPSR_WPSWS1_Pos 1 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS1_Msk (_U_(0x1) << PWM_WPSR_WPSWS1_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS1 PWM_WPSR_WPSWS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS1_Msk instead */ +#define PWM_WPSR_WPSWS2_Pos 2 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS2_Msk (_U_(0x1) << PWM_WPSR_WPSWS2_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS2 PWM_WPSR_WPSWS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS2_Msk instead */ +#define PWM_WPSR_WPSWS3_Pos 3 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS3_Msk (_U_(0x1) << PWM_WPSR_WPSWS3_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS3 PWM_WPSR_WPSWS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS3_Msk instead */ +#define PWM_WPSR_WPSWS4_Pos 4 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS4_Msk (_U_(0x1) << PWM_WPSR_WPSWS4_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS4 PWM_WPSR_WPSWS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS4_Msk instead */ +#define PWM_WPSR_WPSWS5_Pos 5 /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS5_Msk (_U_(0x1) << PWM_WPSR_WPSWS5_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS5 PWM_WPSR_WPSWS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPSWS5_Msk instead */ +#define PWM_WPSR_WPVS_Pos 7 /**< (PWM_WPSR) Write Protect Violation Status Position */ +#define PWM_WPSR_WPVS_Msk (_U_(0x1) << PWM_WPSR_WPVS_Pos) /**< (PWM_WPSR) Write Protect Violation Status Mask */ +#define PWM_WPSR_WPVS PWM_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPVS_Msk instead */ +#define PWM_WPSR_WPHWS0_Pos 8 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS0_Msk (_U_(0x1) << PWM_WPSR_WPHWS0_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS0 PWM_WPSR_WPHWS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS0_Msk instead */ +#define PWM_WPSR_WPHWS1_Pos 9 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS1_Msk (_U_(0x1) << PWM_WPSR_WPHWS1_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS1 PWM_WPSR_WPHWS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS1_Msk instead */ +#define PWM_WPSR_WPHWS2_Pos 10 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS2_Msk (_U_(0x1) << PWM_WPSR_WPHWS2_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS2 PWM_WPSR_WPHWS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS2_Msk instead */ +#define PWM_WPSR_WPHWS3_Pos 11 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS3_Msk (_U_(0x1) << PWM_WPSR_WPHWS3_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS3 PWM_WPSR_WPHWS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS3_Msk instead */ +#define PWM_WPSR_WPHWS4_Pos 12 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS4_Msk (_U_(0x1) << PWM_WPSR_WPHWS4_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS4 PWM_WPSR_WPHWS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS4_Msk instead */ +#define PWM_WPSR_WPHWS5_Pos 13 /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS5_Msk (_U_(0x1) << PWM_WPSR_WPHWS5_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS5 PWM_WPSR_WPHWS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_WPSR_WPHWS5_Msk instead */ +#define PWM_WPSR_WPVSRC_Pos 16 /**< (PWM_WPSR) Write Protect Violation Source Position */ +#define PWM_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PWM_WPSR_WPVSRC_Pos) /**< (PWM_WPSR) Write Protect Violation Source Mask */ +#define PWM_WPSR_WPVSRC(value) (PWM_WPSR_WPVSRC_Msk & ((value) << PWM_WPSR_WPVSRC_Pos)) +#define PWM_WPSR_MASK _U_(0xFFFF3FBF) /**< \deprecated (PWM_WPSR) Register MASK (Use PWM_WPSR_Msk instead) */ +#define PWM_WPSR_Msk _U_(0xFFFF3FBF) /**< (PWM_WPSR) Register Mask */ + +#define PWM_WPSR_WPSWS_Pos 0 /**< (PWM_WPSR Position) Write Protect SW Status */ +#define PWM_WPSR_WPSWS_Msk (_U_(0x3F) << PWM_WPSR_WPSWS_Pos) /**< (PWM_WPSR Mask) WPSWS */ +#define PWM_WPSR_WPSWS(value) (PWM_WPSR_WPSWS_Msk & ((value) << PWM_WPSR_WPSWS_Pos)) +#define PWM_WPSR_WPHWS_Pos 8 /**< (PWM_WPSR Position) Write Protect HW Status */ +#define PWM_WPSR_WPHWS_Msk (_U_(0x3F) << PWM_WPSR_WPHWS_Pos) /**< (PWM_WPSR Mask) WPHWS */ +#define PWM_WPSR_WPHWS(value) (PWM_WPSR_WPHWS_Msk & ((value) << PWM_WPSR_WPHWS_Pos)) + +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) (/W 32) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :9; /**< bit: 0..8 Reserved */ + uint32_t CPOLUP:1; /**< bit: 9 Channel Polarity Update */ + uint32_t :3; /**< bit: 10..12 Reserved */ + uint32_t CPOLINVUP:1; /**< bit: 13 Channel Polarity Inversion Update */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMUPD0_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMUPD0_OFFSET (0x400) /**< (PWM_CMUPD0) PWM Channel Mode Update Register (ch_num = 0) Offset */ + +#define PWM_CMUPD0_CPOLUP_Pos 9 /**< (PWM_CMUPD0) Channel Polarity Update Position */ +#define PWM_CMUPD0_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Update Mask */ +#define PWM_CMUPD0_CPOLUP PWM_CMUPD0_CPOLUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD0_CPOLUP_Msk instead */ +#define PWM_CMUPD0_CPOLINVUP_Pos 13 /**< (PWM_CMUPD0) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD0_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLINVUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD0_CPOLINVUP PWM_CMUPD0_CPOLINVUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD0_CPOLINVUP_Msk instead */ +#define PWM_CMUPD0_MASK _U_(0x2200) /**< \deprecated (PWM_CMUPD0) Register MASK (Use PWM_CMUPD0_Msk instead) */ +#define PWM_CMUPD0_Msk _U_(0x2200) /**< (PWM_CMUPD0) Register Mask */ + + +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) (/W 32) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :9; /**< bit: 0..8 Reserved */ + uint32_t CPOLUP:1; /**< bit: 9 Channel Polarity Update */ + uint32_t :3; /**< bit: 10..12 Reserved */ + uint32_t CPOLINVUP:1; /**< bit: 13 Channel Polarity Inversion Update */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMUPD1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMUPD1_OFFSET (0x420) /**< (PWM_CMUPD1) PWM Channel Mode Update Register (ch_num = 1) Offset */ + +#define PWM_CMUPD1_CPOLUP_Pos 9 /**< (PWM_CMUPD1) Channel Polarity Update Position */ +#define PWM_CMUPD1_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Update Mask */ +#define PWM_CMUPD1_CPOLUP PWM_CMUPD1_CPOLUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD1_CPOLUP_Msk instead */ +#define PWM_CMUPD1_CPOLINVUP_Pos 13 /**< (PWM_CMUPD1) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD1_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLINVUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD1_CPOLINVUP PWM_CMUPD1_CPOLINVUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD1_CPOLINVUP_Msk instead */ +#define PWM_CMUPD1_MASK _U_(0x2200) /**< \deprecated (PWM_CMUPD1) Register MASK (Use PWM_CMUPD1_Msk instead) */ +#define PWM_CMUPD1_Msk _U_(0x2200) /**< (PWM_CMUPD1) Register Mask */ + + +/* -------- PWM_ETRG1 : (PWM Offset: 0x42c) (R/W 32) PWM External Trigger Register (trg_num = 1) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MAXCNT:24; /**< bit: 0..23 Maximum Counter value */ + uint32_t TRGMODE:2; /**< bit: 24..25 External Trigger Mode */ + uint32_t :2; /**< bit: 26..27 Reserved */ + uint32_t TRGEDGE:1; /**< bit: 28 Edge Selection */ + uint32_t TRGFILT:1; /**< bit: 29 Filtered input */ + uint32_t TRGSRC:1; /**< bit: 30 Trigger Source */ + uint32_t RFEN:1; /**< bit: 31 Recoverable Fault Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ETRG1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ETRG1_OFFSET (0x42C) /**< (PWM_ETRG1) PWM External Trigger Register (trg_num = 1) Offset */ + +#define PWM_ETRG1_MAXCNT_Pos 0 /**< (PWM_ETRG1) Maximum Counter value Position */ +#define PWM_ETRG1_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG1_MAXCNT_Pos) /**< (PWM_ETRG1) Maximum Counter value Mask */ +#define PWM_ETRG1_MAXCNT(value) (PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)) +#define PWM_ETRG1_TRGMODE_Pos 24 /**< (PWM_ETRG1) External Trigger Mode Position */ +#define PWM_ETRG1_TRGMODE_Msk (_U_(0x3) << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External Trigger Mode Mask */ +#define PWM_ETRG1_TRGMODE(value) (PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)) +#define PWM_ETRG1_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGMODE_OFF (PWM_ETRG1_TRGMODE_OFF_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External trigger is not enabled. Position */ +#define PWM_ETRG1_TRGMODE_MODE1 (PWM_ETRG1_TRGMODE_MODE1_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Reset Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE2 (PWM_ETRG1_TRGMODE_MODE2_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Start Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE3 (PWM_ETRG1_TRGMODE_MODE3_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG1_TRGEDGE_Pos 28 /**< (PWM_ETRG1) Edge Selection Position */ +#define PWM_ETRG1_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) Edge Selection Mask */ +#define PWM_ETRG1_TRGEDGE PWM_ETRG1_TRGEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG1_TRGEDGE_Msk instead */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (PWM_ETRG1_TRGEDGE_RISING_ONE_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG1_TRGFILT_Pos 29 /**< (PWM_ETRG1) Filtered input Position */ +#define PWM_ETRG1_TRGFILT_Msk (_U_(0x1) << PWM_ETRG1_TRGFILT_Pos) /**< (PWM_ETRG1) Filtered input Mask */ +#define PWM_ETRG1_TRGFILT PWM_ETRG1_TRGFILT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG1_TRGFILT_Msk instead */ +#define PWM_ETRG1_TRGSRC_Pos 30 /**< (PWM_ETRG1) Trigger Source Position */ +#define PWM_ETRG1_TRGSRC_Msk (_U_(0x1) << PWM_ETRG1_TRGSRC_Pos) /**< (PWM_ETRG1) Trigger Source Mask */ +#define PWM_ETRG1_TRGSRC PWM_ETRG1_TRGSRC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG1_TRGSRC_Msk instead */ +#define PWM_ETRG1_RFEN_Pos 31 /**< (PWM_ETRG1) Recoverable Fault Enable Position */ +#define PWM_ETRG1_RFEN_Msk (_U_(0x1) << PWM_ETRG1_RFEN_Pos) /**< (PWM_ETRG1) Recoverable Fault Enable Mask */ +#define PWM_ETRG1_RFEN PWM_ETRG1_RFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG1_RFEN_Msk instead */ +#define PWM_ETRG1_MASK _U_(0xF3FFFFFF) /**< \deprecated (PWM_ETRG1) Register MASK (Use PWM_ETRG1_Msk instead) */ +#define PWM_ETRG1_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG1) Register Mask */ + + +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LEBDELAY:7; /**< bit: 0..6 Leading-Edge Blanking Delay for TRGINx */ + uint32_t :9; /**< bit: 7..15 Reserved */ + uint32_t PWMLFEN:1; /**< bit: 16 PWML Falling Edge Enable */ + uint32_t PWMLREN:1; /**< bit: 17 PWML Rising Edge Enable */ + uint32_t PWMHFEN:1; /**< bit: 18 PWMH Falling Edge Enable */ + uint32_t PWMHREN:1; /**< bit: 19 PWMH Rising Edge Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_LEBR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_LEBR1_OFFSET (0x430) /**< (PWM_LEBR1) PWM Leading-Edge Blanking Register (trg_num = 1) Offset */ + +#define PWM_LEBR1_LEBDELAY_Pos 0 /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR1_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR1_LEBDELAY_Pos) /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR1_LEBDELAY(value) (PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)) +#define PWM_LEBR1_PWMLFEN_Pos 16 /**< (PWM_LEBR1) PWML Falling Edge Enable Position */ +#define PWM_LEBR1_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMLFEN_Pos) /**< (PWM_LEBR1) PWML Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMLFEN PWM_LEBR1_PWMLFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR1_PWMLFEN_Msk instead */ +#define PWM_LEBR1_PWMLREN_Pos 17 /**< (PWM_LEBR1) PWML Rising Edge Enable Position */ +#define PWM_LEBR1_PWMLREN_Msk (_U_(0x1) << PWM_LEBR1_PWMLREN_Pos) /**< (PWM_LEBR1) PWML Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMLREN PWM_LEBR1_PWMLREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR1_PWMLREN_Msk instead */ +#define PWM_LEBR1_PWMHFEN_Pos 18 /**< (PWM_LEBR1) PWMH Falling Edge Enable Position */ +#define PWM_LEBR1_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMHFEN_Pos) /**< (PWM_LEBR1) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMHFEN PWM_LEBR1_PWMHFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR1_PWMHFEN_Msk instead */ +#define PWM_LEBR1_PWMHREN_Pos 19 /**< (PWM_LEBR1) PWMH Rising Edge Enable Position */ +#define PWM_LEBR1_PWMHREN_Msk (_U_(0x1) << PWM_LEBR1_PWMHREN_Pos) /**< (PWM_LEBR1) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMHREN PWM_LEBR1_PWMHREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR1_PWMHREN_Msk instead */ +#define PWM_LEBR1_MASK _U_(0xF007F) /**< \deprecated (PWM_LEBR1) Register MASK (Use PWM_LEBR1_Msk instead) */ +#define PWM_LEBR1_Msk _U_(0xF007F) /**< (PWM_LEBR1) Register Mask */ + + +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) (/W 32) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :9; /**< bit: 0..8 Reserved */ + uint32_t CPOLUP:1; /**< bit: 9 Channel Polarity Update */ + uint32_t :3; /**< bit: 10..12 Reserved */ + uint32_t CPOLINVUP:1; /**< bit: 13 Channel Polarity Inversion Update */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMUPD2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMUPD2_OFFSET (0x440) /**< (PWM_CMUPD2) PWM Channel Mode Update Register (ch_num = 2) Offset */ + +#define PWM_CMUPD2_CPOLUP_Pos 9 /**< (PWM_CMUPD2) Channel Polarity Update Position */ +#define PWM_CMUPD2_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Update Mask */ +#define PWM_CMUPD2_CPOLUP PWM_CMUPD2_CPOLUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD2_CPOLUP_Msk instead */ +#define PWM_CMUPD2_CPOLINVUP_Pos 13 /**< (PWM_CMUPD2) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD2_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLINVUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD2_CPOLINVUP PWM_CMUPD2_CPOLINVUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD2_CPOLINVUP_Msk instead */ +#define PWM_CMUPD2_MASK _U_(0x2200) /**< \deprecated (PWM_CMUPD2) Register MASK (Use PWM_CMUPD2_Msk instead) */ +#define PWM_CMUPD2_Msk _U_(0x2200) /**< (PWM_CMUPD2) Register Mask */ + + +/* -------- PWM_ETRG2 : (PWM Offset: 0x44c) (R/W 32) PWM External Trigger Register (trg_num = 2) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MAXCNT:24; /**< bit: 0..23 Maximum Counter value */ + uint32_t TRGMODE:2; /**< bit: 24..25 External Trigger Mode */ + uint32_t :2; /**< bit: 26..27 Reserved */ + uint32_t TRGEDGE:1; /**< bit: 28 Edge Selection */ + uint32_t TRGFILT:1; /**< bit: 29 Filtered input */ + uint32_t TRGSRC:1; /**< bit: 30 Trigger Source */ + uint32_t RFEN:1; /**< bit: 31 Recoverable Fault Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_ETRG2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_ETRG2_OFFSET (0x44C) /**< (PWM_ETRG2) PWM External Trigger Register (trg_num = 2) Offset */ + +#define PWM_ETRG2_MAXCNT_Pos 0 /**< (PWM_ETRG2) Maximum Counter value Position */ +#define PWM_ETRG2_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG2_MAXCNT_Pos) /**< (PWM_ETRG2) Maximum Counter value Mask */ +#define PWM_ETRG2_MAXCNT(value) (PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)) +#define PWM_ETRG2_TRGMODE_Pos 24 /**< (PWM_ETRG2) External Trigger Mode Position */ +#define PWM_ETRG2_TRGMODE_Msk (_U_(0x3) << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External Trigger Mode Mask */ +#define PWM_ETRG2_TRGMODE(value) (PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)) +#define PWM_ETRG2_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGMODE_OFF (PWM_ETRG2_TRGMODE_OFF_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External trigger is not enabled. Position */ +#define PWM_ETRG2_TRGMODE_MODE1 (PWM_ETRG2_TRGMODE_MODE1_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Reset Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE2 (PWM_ETRG2_TRGMODE_MODE2_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Start Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE3 (PWM_ETRG2_TRGMODE_MODE3_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG2_TRGEDGE_Pos 28 /**< (PWM_ETRG2) Edge Selection Position */ +#define PWM_ETRG2_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) Edge Selection Mask */ +#define PWM_ETRG2_TRGEDGE PWM_ETRG2_TRGEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG2_TRGEDGE_Msk instead */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (PWM_ETRG2_TRGEDGE_RISING_ONE_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG2_TRGFILT_Pos 29 /**< (PWM_ETRG2) Filtered input Position */ +#define PWM_ETRG2_TRGFILT_Msk (_U_(0x1) << PWM_ETRG2_TRGFILT_Pos) /**< (PWM_ETRG2) Filtered input Mask */ +#define PWM_ETRG2_TRGFILT PWM_ETRG2_TRGFILT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG2_TRGFILT_Msk instead */ +#define PWM_ETRG2_TRGSRC_Pos 30 /**< (PWM_ETRG2) Trigger Source Position */ +#define PWM_ETRG2_TRGSRC_Msk (_U_(0x1) << PWM_ETRG2_TRGSRC_Pos) /**< (PWM_ETRG2) Trigger Source Mask */ +#define PWM_ETRG2_TRGSRC PWM_ETRG2_TRGSRC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG2_TRGSRC_Msk instead */ +#define PWM_ETRG2_RFEN_Pos 31 /**< (PWM_ETRG2) Recoverable Fault Enable Position */ +#define PWM_ETRG2_RFEN_Msk (_U_(0x1) << PWM_ETRG2_RFEN_Pos) /**< (PWM_ETRG2) Recoverable Fault Enable Mask */ +#define PWM_ETRG2_RFEN PWM_ETRG2_RFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_ETRG2_RFEN_Msk instead */ +#define PWM_ETRG2_MASK _U_(0xF3FFFFFF) /**< \deprecated (PWM_ETRG2) Register MASK (Use PWM_ETRG2_Msk instead) */ +#define PWM_ETRG2_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG2) Register Mask */ + + +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LEBDELAY:7; /**< bit: 0..6 Leading-Edge Blanking Delay for TRGINx */ + uint32_t :9; /**< bit: 7..15 Reserved */ + uint32_t PWMLFEN:1; /**< bit: 16 PWML Falling Edge Enable */ + uint32_t PWMLREN:1; /**< bit: 17 PWML Rising Edge Enable */ + uint32_t PWMHFEN:1; /**< bit: 18 PWMH Falling Edge Enable */ + uint32_t PWMHREN:1; /**< bit: 19 PWMH Rising Edge Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_LEBR2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_LEBR2_OFFSET (0x450) /**< (PWM_LEBR2) PWM Leading-Edge Blanking Register (trg_num = 2) Offset */ + +#define PWM_LEBR2_LEBDELAY_Pos 0 /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR2_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR2_LEBDELAY_Pos) /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR2_LEBDELAY(value) (PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)) +#define PWM_LEBR2_PWMLFEN_Pos 16 /**< (PWM_LEBR2) PWML Falling Edge Enable Position */ +#define PWM_LEBR2_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMLFEN_Pos) /**< (PWM_LEBR2) PWML Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMLFEN PWM_LEBR2_PWMLFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR2_PWMLFEN_Msk instead */ +#define PWM_LEBR2_PWMLREN_Pos 17 /**< (PWM_LEBR2) PWML Rising Edge Enable Position */ +#define PWM_LEBR2_PWMLREN_Msk (_U_(0x1) << PWM_LEBR2_PWMLREN_Pos) /**< (PWM_LEBR2) PWML Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMLREN PWM_LEBR2_PWMLREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR2_PWMLREN_Msk instead */ +#define PWM_LEBR2_PWMHFEN_Pos 18 /**< (PWM_LEBR2) PWMH Falling Edge Enable Position */ +#define PWM_LEBR2_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMHFEN_Pos) /**< (PWM_LEBR2) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMHFEN PWM_LEBR2_PWMHFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR2_PWMHFEN_Msk instead */ +#define PWM_LEBR2_PWMHREN_Pos 19 /**< (PWM_LEBR2) PWMH Rising Edge Enable Position */ +#define PWM_LEBR2_PWMHREN_Msk (_U_(0x1) << PWM_LEBR2_PWMHREN_Pos) /**< (PWM_LEBR2) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMHREN PWM_LEBR2_PWMHREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_LEBR2_PWMHREN_Msk instead */ +#define PWM_LEBR2_MASK _U_(0xF007F) /**< \deprecated (PWM_LEBR2) Register MASK (Use PWM_LEBR2_Msk instead) */ +#define PWM_LEBR2_Msk _U_(0xF007F) /**< (PWM_LEBR2) Register Mask */ + + +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) (/W 32) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :9; /**< bit: 0..8 Reserved */ + uint32_t CPOLUP:1; /**< bit: 9 Channel Polarity Update */ + uint32_t :3; /**< bit: 10..12 Reserved */ + uint32_t CPOLINVUP:1; /**< bit: 13 Channel Polarity Inversion Update */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} PWM_CMUPD3_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define PWM_CMUPD3_OFFSET (0x460) /**< (PWM_CMUPD3) PWM Channel Mode Update Register (ch_num = 3) Offset */ + +#define PWM_CMUPD3_CPOLUP_Pos 9 /**< (PWM_CMUPD3) Channel Polarity Update Position */ +#define PWM_CMUPD3_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Update Mask */ +#define PWM_CMUPD3_CPOLUP PWM_CMUPD3_CPOLUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD3_CPOLUP_Msk instead */ +#define PWM_CMUPD3_CPOLINVUP_Pos 13 /**< (PWM_CMUPD3) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD3_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLINVUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD3_CPOLINVUP PWM_CMUPD3_CPOLINVUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PWM_CMUPD3_CPOLINVUP_Msk instead */ +#define PWM_CMUPD3_MASK _U_(0x2200) /**< \deprecated (PWM_CMUPD3) Register MASK (Use PWM_CMUPD3_Msk instead) */ +#define PWM_CMUPD3_Msk _U_(0x2200) /**< (PWM_CMUPD3) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief PWM_CH_NUM hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< (PWM_CH_NUM Offset: 0x00) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< (PWM_CH_NUM Offset: 0x04) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< (PWM_CH_NUM Offset: 0x08) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< (PWM_CH_NUM Offset: 0x0C) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< (PWM_CH_NUM Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< (PWM_CH_NUM Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< (PWM_CH_NUM Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< (PWM_CH_NUM Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmChNum; + +/** \brief PWM_CMP hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< (PWM_CMP Offset: 0x00) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< (PWM_CMP Offset: 0x04) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< (PWM_CMP Offset: 0x08) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< (PWM_CMP Offset: 0x0C) PWM Comparison 0 Mode Update Register */ +} PwmCmp; + +#define PWMCMP_NUMBER 8 +#define PWMCHNUM_NUMBER 4 +/** \brief PWM hardware registers */ +typedef struct { + __IO uint32_t PWM_CLK; /**< (PWM Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< (PWM Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< (PWM Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< (PWM Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< (PWM Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< (PWM Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< (PWM Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< (PWM Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< (PWM Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< (PWM Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< (PWM Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< (PWM Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< (PWM Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< (PWM Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< (PWM Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< (PWM Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< (PWM Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< (PWM Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< (PWM Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< (PWM Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< (PWM Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< (PWM Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< (PWM Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< (PWM Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< (PWM Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< (PWM Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint8_t Reserved1[12]; + __IO uint32_t PWM_ELMR[2]; /**< (PWM Offset: 0x7C) PWM Event Line 0 Mode Register 0 */ + __I uint8_t Reserved2[28]; + __IO uint32_t PWM_SSPR; /**< (PWM Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< (PWM Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint8_t Reserved3[8]; + __IO uint32_t PWM_SMMR; /**< (PWM Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint8_t Reserved4[12]; + __IO uint32_t PWM_FPV2; /**< (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint8_t Reserved5[32]; + __O uint32_t PWM_WPCR; /**< (PWM Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< (PWM Offset: 0xE8) PWM Write Protection Status Register */ + __I uint8_t Reserved6[68]; + PwmCmp PwmCmp[PWMCMP_NUMBER]; /**< Offset: 0x130 PWM Comparison 0 Value Register */ + __I uint8_t Reserved7[80]; + PwmChNum PwmChNum[PWMCHNUM_NUMBER]; /**< Offset: 0x200 PWM Channel Mode Register */ + __I uint8_t Reserved8[384]; + __O uint32_t PWM_CMUPD0; /**< (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint8_t Reserved9[28]; + __O uint32_t PWM_CMUPD1; /**< (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint8_t Reserved10[8]; + __IO uint32_t PWM_ETRG1; /**< (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint8_t Reserved11[12]; + __O uint32_t PWM_CMUPD2; /**< (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint8_t Reserved12[8]; + __IO uint32_t PWM_ETRG2; /**< (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint8_t Reserved13[12]; + __O uint32_t PWM_CMUPD3; /**< (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief PWM_CH_NUM hardware registers */ +typedef struct { + __IO PWM_CMR_Type PWM_CMR; /**< Offset: 0x00 (R/W 32) PWM Channel Mode Register */ + __IO PWM_CDTY_Type PWM_CDTY; /**< Offset: 0x04 (R/W 32) PWM Channel Duty Cycle Register */ + __O PWM_CDTYUPD_Type PWM_CDTYUPD; /**< Offset: 0x08 ( /W 32) PWM Channel Duty Cycle Update Register */ + __IO PWM_CPRD_Type PWM_CPRD; /**< Offset: 0x0C (R/W 32) PWM Channel Period Register */ + __O PWM_CPRDUPD_Type PWM_CPRDUPD; /**< Offset: 0x10 ( /W 32) PWM Channel Period Update Register */ + __I PWM_CCNT_Type PWM_CCNT; /**< Offset: 0x14 (R/ 32) PWM Channel Counter Register */ + __IO PWM_DT_Type PWM_DT; /**< Offset: 0x18 (R/W 32) PWM Channel Dead Time Register */ + __O PWM_DTUPD_Type PWM_DTUPD; /**< Offset: 0x1C ( /W 32) PWM Channel Dead Time Update Register */ +} PwmChNum; + +/** \brief PWM_CMP hardware registers */ +typedef struct { + __IO PWM_CMPV_Type PWM_CMPV; /**< Offset: 0x00 (R/W 32) PWM Comparison 0 Value Register */ + __O PWM_CMPVUPD_Type PWM_CMPVUPD; /**< Offset: 0x04 ( /W 32) PWM Comparison 0 Value Update Register */ + __IO PWM_CMPM_Type PWM_CMPM; /**< Offset: 0x08 (R/W 32) PWM Comparison 0 Mode Register */ + __O PWM_CMPMUPD_Type PWM_CMPMUPD; /**< Offset: 0x0C ( /W 32) PWM Comparison 0 Mode Update Register */ +} PwmCmp; + +/** \brief PWM hardware registers */ +typedef struct { + __IO PWM_CLK_Type PWM_CLK; /**< Offset: 0x00 (R/W 32) PWM Clock Register */ + __O PWM_ENA_Type PWM_ENA; /**< Offset: 0x04 ( /W 32) PWM Enable Register */ + __O PWM_DIS_Type PWM_DIS; /**< Offset: 0x08 ( /W 32) PWM Disable Register */ + __I PWM_SR_Type PWM_SR; /**< Offset: 0x0C (R/ 32) PWM Status Register */ + __O PWM_IER1_Type PWM_IER1; /**< Offset: 0x10 ( /W 32) PWM Interrupt Enable Register 1 */ + __O PWM_IDR1_Type PWM_IDR1; /**< Offset: 0x14 ( /W 32) PWM Interrupt Disable Register 1 */ + __I PWM_IMR1_Type PWM_IMR1; /**< Offset: 0x18 (R/ 32) PWM Interrupt Mask Register 1 */ + __I PWM_ISR1_Type PWM_ISR1; /**< Offset: 0x1C (R/ 32) PWM Interrupt Status Register 1 */ + __IO PWM_SCM_Type PWM_SCM; /**< Offset: 0x20 (R/W 32) PWM Sync Channels Mode Register */ + __O PWM_DMAR_Type PWM_DMAR; /**< Offset: 0x24 ( /W 32) PWM DMA Register */ + __IO PWM_SCUC_Type PWM_SCUC; /**< Offset: 0x28 (R/W 32) PWM Sync Channels Update Control Register */ + __IO PWM_SCUP_Type PWM_SCUP; /**< Offset: 0x2C (R/W 32) PWM Sync Channels Update Period Register */ + __O PWM_SCUPUPD_Type PWM_SCUPUPD; /**< Offset: 0x30 ( /W 32) PWM Sync Channels Update Period Update Register */ + __O PWM_IER2_Type PWM_IER2; /**< Offset: 0x34 ( /W 32) PWM Interrupt Enable Register 2 */ + __O PWM_IDR2_Type PWM_IDR2; /**< Offset: 0x38 ( /W 32) PWM Interrupt Disable Register 2 */ + __I PWM_IMR2_Type PWM_IMR2; /**< Offset: 0x3C (R/ 32) PWM Interrupt Mask Register 2 */ + __I PWM_ISR2_Type PWM_ISR2; /**< Offset: 0x40 (R/ 32) PWM Interrupt Status Register 2 */ + __IO PWM_OOV_Type PWM_OOV; /**< Offset: 0x44 (R/W 32) PWM Output Override Value Register */ + __IO PWM_OS_Type PWM_OS; /**< Offset: 0x48 (R/W 32) PWM Output Selection Register */ + __O PWM_OSS_Type PWM_OSS; /**< Offset: 0x4C ( /W 32) PWM Output Selection Set Register */ + __O PWM_OSC_Type PWM_OSC; /**< Offset: 0x50 ( /W 32) PWM Output Selection Clear Register */ + __O PWM_OSSUPD_Type PWM_OSSUPD; /**< Offset: 0x54 ( /W 32) PWM Output Selection Set Update Register */ + __O PWM_OSCUPD_Type PWM_OSCUPD; /**< Offset: 0x58 ( /W 32) PWM Output Selection Clear Update Register */ + __IO PWM_FMR_Type PWM_FMR; /**< Offset: 0x5C (R/W 32) PWM Fault Mode Register */ + __I PWM_FSR_Type PWM_FSR; /**< Offset: 0x60 (R/ 32) PWM Fault Status Register */ + __O PWM_FCR_Type PWM_FCR; /**< Offset: 0x64 ( /W 32) PWM Fault Clear Register */ + __IO PWM_FPV1_Type PWM_FPV1; /**< Offset: 0x68 (R/W 32) PWM Fault Protection Value Register 1 */ + __IO PWM_FPE_Type PWM_FPE; /**< Offset: 0x6C (R/W 32) PWM Fault Protection Enable Register */ + __I uint8_t Reserved1[12]; + __IO PWM_ELMR_Type PWM_ELMR[2]; /**< Offset: 0x7C (R/W 32) PWM Event Line 0 Mode Register 0 */ + __I uint8_t Reserved2[28]; + __IO PWM_SSPR_Type PWM_SSPR; /**< Offset: 0xA0 (R/W 32) PWM Spread Spectrum Register */ + __O PWM_SSPUP_Type PWM_SSPUP; /**< Offset: 0xA4 ( /W 32) PWM Spread Spectrum Update Register */ + __I uint8_t Reserved3[8]; + __IO PWM_SMMR_Type PWM_SMMR; /**< Offset: 0xB0 (R/W 32) PWM Stepper Motor Mode Register */ + __I uint8_t Reserved4[12]; + __IO PWM_FPV2_Type PWM_FPV2; /**< Offset: 0xC0 (R/W 32) PWM Fault Protection Value 2 Register */ + __I uint8_t Reserved5[32]; + __O PWM_WPCR_Type PWM_WPCR; /**< Offset: 0xE4 ( /W 32) PWM Write Protection Control Register */ + __I PWM_WPSR_Type PWM_WPSR; /**< Offset: 0xE8 (R/ 32) PWM Write Protection Status Register */ + __I uint8_t Reserved6[68]; + PwmCmp PwmCmp[8]; /**< Offset: 0x130 PWM Comparison 0 Value Register */ + __I uint8_t Reserved7[80]; + PwmChNum PwmChNum[4]; /**< Offset: 0x200 PWM Channel Mode Register */ + __I uint8_t Reserved8[384]; + __O PWM_CMUPD0_Type PWM_CMUPD0; /**< Offset: 0x400 ( /W 32) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint8_t Reserved9[28]; + __O PWM_CMUPD1_Type PWM_CMUPD1; /**< Offset: 0x420 ( /W 32) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint8_t Reserved10[8]; + __IO PWM_ETRG1_Type PWM_ETRG1; /**< Offset: 0x42C (R/W 32) PWM External Trigger Register (trg_num = 1) */ + __IO PWM_LEBR1_Type PWM_LEBR1; /**< Offset: 0x430 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint8_t Reserved11[12]; + __O PWM_CMUPD2_Type PWM_CMUPD2; /**< Offset: 0x440 ( /W 32) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint8_t Reserved12[8]; + __IO PWM_ETRG2_Type PWM_ETRG2; /**< Offset: 0x44C (R/W 32) PWM External Trigger Register (trg_num = 2) */ + __IO PWM_LEBR2_Type PWM_LEBR2; /**< Offset: 0x450 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint8_t Reserved13[12]; + __O PWM_CMUPD3_Type PWM_CMUPD3; /**< Offset: 0x460 ( /W 32) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Pulse Width Modulation Controller */ + +#endif /* _SAME70_PWM_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/qspi.h b/bsp/microchip/same70/bsp/same70b/include/component/qspi.h new file mode 100644 index 0000000000..d0ea1f4ca1 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/qspi.h @@ -0,0 +1,735 @@ +/** + * \file + * + * \brief Component description for QSPI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_QSPI_COMPONENT_H_ +#define _SAME70_QSPI_COMPONENT_H_ +#define _SAME70_QSPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Quad Serial Peripheral Interface + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR QSPI */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define QSPI_11171 /**< (QSPI) Module ID */ +#define REV_QSPI J /**< (QSPI) Module revision */ + +/* -------- QSPI_CR : (QSPI Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t QSPIEN:1; /**< bit: 0 QSPI Enable */ + uint32_t QSPIDIS:1; /**< bit: 1 QSPI Disable */ + uint32_t :5; /**< bit: 2..6 Reserved */ + uint32_t SWRST:1; /**< bit: 7 QSPI Software Reset */ + uint32_t :16; /**< bit: 8..23 Reserved */ + uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_CR_OFFSET (0x00) /**< (QSPI_CR) Control Register Offset */ + +#define QSPI_CR_QSPIEN_Pos 0 /**< (QSPI_CR) QSPI Enable Position */ +#define QSPI_CR_QSPIEN_Msk (_U_(0x1) << QSPI_CR_QSPIEN_Pos) /**< (QSPI_CR) QSPI Enable Mask */ +#define QSPI_CR_QSPIEN QSPI_CR_QSPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIEN_Msk instead */ +#define QSPI_CR_QSPIDIS_Pos 1 /**< (QSPI_CR) QSPI Disable Position */ +#define QSPI_CR_QSPIDIS_Msk (_U_(0x1) << QSPI_CR_QSPIDIS_Pos) /**< (QSPI_CR) QSPI Disable Mask */ +#define QSPI_CR_QSPIDIS QSPI_CR_QSPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_QSPIDIS_Msk instead */ +#define QSPI_CR_SWRST_Pos 7 /**< (QSPI_CR) QSPI Software Reset Position */ +#define QSPI_CR_SWRST_Msk (_U_(0x1) << QSPI_CR_SWRST_Pos) /**< (QSPI_CR) QSPI Software Reset Mask */ +#define QSPI_CR_SWRST QSPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_SWRST_Msk instead */ +#define QSPI_CR_LASTXFER_Pos 24 /**< (QSPI_CR) Last Transfer Position */ +#define QSPI_CR_LASTXFER_Msk (_U_(0x1) << QSPI_CR_LASTXFER_Pos) /**< (QSPI_CR) Last Transfer Mask */ +#define QSPI_CR_LASTXFER QSPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_CR_LASTXFER_Msk instead */ +#define QSPI_CR_MASK _U_(0x1000083) /**< \deprecated (QSPI_CR) Register MASK (Use QSPI_CR_Msk instead) */ +#define QSPI_CR_Msk _U_(0x1000083) /**< (QSPI_CR) Register Mask */ + + +/* -------- QSPI_MR : (QSPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SMM:1; /**< bit: 0 Serial Memory Mode */ + uint32_t LLB:1; /**< bit: 1 Local Loopback Enable */ + uint32_t WDRBT:1; /**< bit: 2 Wait Data Read Before Transfer */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t CSMODE:2; /**< bit: 4..5 Chip Select Mode */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t NBBITS:4; /**< bit: 8..11 Number Of Bits Per Transfer */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t DLYBCT:8; /**< bit: 16..23 Delay Between Consecutive Transfers */ + uint32_t DLYCS:8; /**< bit: 24..31 Minimum Inactive QCS Delay */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_MR_OFFSET (0x04) /**< (QSPI_MR) Mode Register Offset */ + +#define QSPI_MR_SMM_Pos 0 /**< (QSPI_MR) Serial Memory Mode Position */ +#define QSPI_MR_SMM_Msk (_U_(0x1) << QSPI_MR_SMM_Pos) /**< (QSPI_MR) Serial Memory Mode Mask */ +#define QSPI_MR_SMM QSPI_MR_SMM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_SMM_Msk instead */ +#define QSPI_MR_SMM_SPI_Val _U_(0x0) /**< (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY_Val _U_(0x1) /**< (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_SMM_SPI (QSPI_MR_SMM_SPI_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in SPI mode. Position */ +#define QSPI_MR_SMM_MEMORY (QSPI_MR_SMM_MEMORY_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in Serial Memory mode. Position */ +#define QSPI_MR_LLB_Pos 1 /**< (QSPI_MR) Local Loopback Enable Position */ +#define QSPI_MR_LLB_Msk (_U_(0x1) << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local Loopback Enable Mask */ +#define QSPI_MR_LLB QSPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_LLB_Msk instead */ +#define QSPI_MR_LLB_DISABLED_Val _U_(0x0) /**< (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED_Val _U_(0x1) /**< (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_LLB_DISABLED (QSPI_MR_LLB_DISABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path disabled. Position */ +#define QSPI_MR_LLB_ENABLED (QSPI_MR_LLB_ENABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path enabled. Position */ +#define QSPI_MR_WDRBT_Pos 2 /**< (QSPI_MR) Wait Data Read Before Transfer Position */ +#define QSPI_MR_WDRBT_Msk (_U_(0x1) << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) Wait Data Read Before Transfer Mask */ +#define QSPI_MR_WDRBT QSPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_MR_WDRBT_Msk instead */ +#define QSPI_MR_WDRBT_DISABLED_Val _U_(0x0) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED_Val _U_(0x1) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_WDRBT_DISABLED (QSPI_MR_WDRBT_DISABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. Position */ +#define QSPI_MR_WDRBT_ENABLED (QSPI_MR_WDRBT_ENABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. Position */ +#define QSPI_MR_CSMODE_Pos 4 /**< (QSPI_MR) Chip Select Mode Position */ +#define QSPI_MR_CSMODE_Msk (_U_(0x3) << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) Chip Select Mode Mask */ +#define QSPI_MR_CSMODE(value) (QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)) +#define QSPI_MR_CSMODE_NOT_RELOADED_Val _U_(0x0) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_CSMODE_NOT_RELOADED (QSPI_MR_CSMODE_NOT_RELOADED_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. Position */ +#define QSPI_MR_CSMODE_LASTXFER (QSPI_MR_CSMODE_LASTXFER_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. Position */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (QSPI_MR_CSMODE_SYSTEMATICALLY_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. Position */ +#define QSPI_MR_NBBITS_Pos 8 /**< (QSPI_MR) Number Of Bits Per Transfer Position */ +#define QSPI_MR_NBBITS_Msk (_U_(0xF) << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) Number Of Bits Per Transfer Mask */ +#define QSPI_MR_NBBITS(value) (QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)) +#define QSPI_MR_NBBITS_8_BIT_Val _U_(0x0) /**< (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT_Val _U_(0x8) /**< (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_NBBITS_8_BIT (QSPI_MR_NBBITS_8_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 8 bits for transfer Position */ +#define QSPI_MR_NBBITS_16_BIT (QSPI_MR_NBBITS_16_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 16 bits for transfer Position */ +#define QSPI_MR_DLYBCT_Pos 16 /**< (QSPI_MR) Delay Between Consecutive Transfers Position */ +#define QSPI_MR_DLYBCT_Msk (_U_(0xFF) << QSPI_MR_DLYBCT_Pos) /**< (QSPI_MR) Delay Between Consecutive Transfers Mask */ +#define QSPI_MR_DLYBCT(value) (QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)) +#define QSPI_MR_DLYCS_Pos 24 /**< (QSPI_MR) Minimum Inactive QCS Delay Position */ +#define QSPI_MR_DLYCS_Msk (_U_(0xFF) << QSPI_MR_DLYCS_Pos) /**< (QSPI_MR) Minimum Inactive QCS Delay Mask */ +#define QSPI_MR_DLYCS(value) (QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)) +#define QSPI_MR_MASK _U_(0xFFFF0F37) /**< \deprecated (QSPI_MR) Register MASK (Use QSPI_MR_Msk instead) */ +#define QSPI_MR_Msk _U_(0xFFFF0F37) /**< (QSPI_MR) Register Mask */ + + +/* -------- QSPI_RDR : (QSPI Offset: 0x08) (R/ 32) Receive Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RD:16; /**< bit: 0..15 Receive Data */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_RDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_RDR_OFFSET (0x08) /**< (QSPI_RDR) Receive Data Register Offset */ + +#define QSPI_RDR_RD_Pos 0 /**< (QSPI_RDR) Receive Data Position */ +#define QSPI_RDR_RD_Msk (_U_(0xFFFF) << QSPI_RDR_RD_Pos) /**< (QSPI_RDR) Receive Data Mask */ +#define QSPI_RDR_RD(value) (QSPI_RDR_RD_Msk & ((value) << QSPI_RDR_RD_Pos)) +#define QSPI_RDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_RDR) Register MASK (Use QSPI_RDR_Msk instead) */ +#define QSPI_RDR_Msk _U_(0xFFFF) /**< (QSPI_RDR) Register Mask */ + + +/* -------- QSPI_TDR : (QSPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TD:16; /**< bit: 0..15 Transmit Data */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_TDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_TDR_OFFSET (0x0C) /**< (QSPI_TDR) Transmit Data Register Offset */ + +#define QSPI_TDR_TD_Pos 0 /**< (QSPI_TDR) Transmit Data Position */ +#define QSPI_TDR_TD_Msk (_U_(0xFFFF) << QSPI_TDR_TD_Pos) /**< (QSPI_TDR) Transmit Data Mask */ +#define QSPI_TDR_TD(value) (QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)) +#define QSPI_TDR_MASK _U_(0xFFFF) /**< \deprecated (QSPI_TDR) Register MASK (Use QSPI_TDR_Msk instead) */ +#define QSPI_TDR_Msk _U_(0xFFFF) /**< (QSPI_TDR) Register Mask */ + + +/* -------- QSPI_SR : (QSPI Offset: 0x10) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */ + uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */ + uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty (cleared by writing SPI_TDR) */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CSR:1; /**< bit: 8 Chip Select Rise (cleared on read) */ + uint32_t CSS:1; /**< bit: 9 Chip Select Status */ + uint32_t INSTRE:1; /**< bit: 10 Instruction End Status (cleared on read) */ + uint32_t :13; /**< bit: 11..23 Reserved */ + uint32_t QSPIENS:1; /**< bit: 24 QSPI Enable Status */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_SR_OFFSET (0x10) /**< (QSPI_SR) Status Register Offset */ + +#define QSPI_SR_RDRF_Pos 0 /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define QSPI_SR_RDRF_Msk (_U_(0x1) << QSPI_SR_RDRF_Pos) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define QSPI_SR_RDRF QSPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_RDRF_Msk instead */ +#define QSPI_SR_TDRE_Pos 1 /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TDRE_Msk (_U_(0x1) << QSPI_SR_TDRE_Pos) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TDRE QSPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TDRE_Msk instead */ +#define QSPI_SR_TXEMPTY_Pos 2 /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TXEMPTY_Msk (_U_(0x1) << QSPI_SR_TXEMPTY_Pos) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TXEMPTY QSPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_TXEMPTY_Msk instead */ +#define QSPI_SR_OVRES_Pos 3 /**< (QSPI_SR) Overrun Error Status (cleared on read) Position */ +#define QSPI_SR_OVRES_Msk (_U_(0x1) << QSPI_SR_OVRES_Pos) /**< (QSPI_SR) Overrun Error Status (cleared on read) Mask */ +#define QSPI_SR_OVRES QSPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_OVRES_Msk instead */ +#define QSPI_SR_CSR_Pos 8 /**< (QSPI_SR) Chip Select Rise (cleared on read) Position */ +#define QSPI_SR_CSR_Msk (_U_(0x1) << QSPI_SR_CSR_Pos) /**< (QSPI_SR) Chip Select Rise (cleared on read) Mask */ +#define QSPI_SR_CSR QSPI_SR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSR_Msk instead */ +#define QSPI_SR_CSS_Pos 9 /**< (QSPI_SR) Chip Select Status Position */ +#define QSPI_SR_CSS_Msk (_U_(0x1) << QSPI_SR_CSS_Pos) /**< (QSPI_SR) Chip Select Status Mask */ +#define QSPI_SR_CSS QSPI_SR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_CSS_Msk instead */ +#define QSPI_SR_INSTRE_Pos 10 /**< (QSPI_SR) Instruction End Status (cleared on read) Position */ +#define QSPI_SR_INSTRE_Msk (_U_(0x1) << QSPI_SR_INSTRE_Pos) /**< (QSPI_SR) Instruction End Status (cleared on read) Mask */ +#define QSPI_SR_INSTRE QSPI_SR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_INSTRE_Msk instead */ +#define QSPI_SR_QSPIENS_Pos 24 /**< (QSPI_SR) QSPI Enable Status Position */ +#define QSPI_SR_QSPIENS_Msk (_U_(0x1) << QSPI_SR_QSPIENS_Pos) /**< (QSPI_SR) QSPI Enable Status Mask */ +#define QSPI_SR_QSPIENS QSPI_SR_QSPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SR_QSPIENS_Msk instead */ +#define QSPI_SR_MASK _U_(0x100070F) /**< \deprecated (QSPI_SR) Register MASK (Use QSPI_SR_Msk instead) */ +#define QSPI_SR_Msk _U_(0x100070F) /**< (QSPI_SR) Register Mask */ + + +/* -------- QSPI_IER : (QSPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */ + uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Enable */ + uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Enable */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Enable */ + uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Enable */ + uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Enable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_IER_OFFSET (0x14) /**< (QSPI_IER) Interrupt Enable Register Offset */ + +#define QSPI_IER_RDRF_Pos 0 /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define QSPI_IER_RDRF_Msk (_U_(0x1) << QSPI_IER_RDRF_Pos) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define QSPI_IER_RDRF QSPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_RDRF_Msk instead */ +#define QSPI_IER_TDRE_Pos 1 /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Position */ +#define QSPI_IER_TDRE_Msk (_U_(0x1) << QSPI_IER_TDRE_Pos) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Mask */ +#define QSPI_IER_TDRE QSPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TDRE_Msk instead */ +#define QSPI_IER_TXEMPTY_Pos 2 /**< (QSPI_IER) Transmission Registers Empty Enable Position */ +#define QSPI_IER_TXEMPTY_Msk (_U_(0x1) << QSPI_IER_TXEMPTY_Pos) /**< (QSPI_IER) Transmission Registers Empty Enable Mask */ +#define QSPI_IER_TXEMPTY QSPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_TXEMPTY_Msk instead */ +#define QSPI_IER_OVRES_Pos 3 /**< (QSPI_IER) Overrun Error Interrupt Enable Position */ +#define QSPI_IER_OVRES_Msk (_U_(0x1) << QSPI_IER_OVRES_Pos) /**< (QSPI_IER) Overrun Error Interrupt Enable Mask */ +#define QSPI_IER_OVRES QSPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_OVRES_Msk instead */ +#define QSPI_IER_CSR_Pos 8 /**< (QSPI_IER) Chip Select Rise Interrupt Enable Position */ +#define QSPI_IER_CSR_Msk (_U_(0x1) << QSPI_IER_CSR_Pos) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Mask */ +#define QSPI_IER_CSR QSPI_IER_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSR_Msk instead */ +#define QSPI_IER_CSS_Pos 9 /**< (QSPI_IER) Chip Select Status Interrupt Enable Position */ +#define QSPI_IER_CSS_Msk (_U_(0x1) << QSPI_IER_CSS_Pos) /**< (QSPI_IER) Chip Select Status Interrupt Enable Mask */ +#define QSPI_IER_CSS QSPI_IER_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_CSS_Msk instead */ +#define QSPI_IER_INSTRE_Pos 10 /**< (QSPI_IER) Instruction End Interrupt Enable Position */ +#define QSPI_IER_INSTRE_Msk (_U_(0x1) << QSPI_IER_INSTRE_Pos) /**< (QSPI_IER) Instruction End Interrupt Enable Mask */ +#define QSPI_IER_INSTRE QSPI_IER_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IER_INSTRE_Msk instead */ +#define QSPI_IER_MASK _U_(0x70F) /**< \deprecated (QSPI_IER) Register MASK (Use QSPI_IER_Msk instead) */ +#define QSPI_IER_Msk _U_(0x70F) /**< (QSPI_IER) Register Mask */ + + +/* -------- QSPI_IDR : (QSPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */ + uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Disable */ + uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Disable */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Disable */ + uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Disable */ + uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Disable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_IDR_OFFSET (0x18) /**< (QSPI_IDR) Interrupt Disable Register Offset */ + +#define QSPI_IDR_RDRF_Pos 0 /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define QSPI_IDR_RDRF_Msk (_U_(0x1) << QSPI_IDR_RDRF_Pos) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define QSPI_IDR_RDRF QSPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_RDRF_Msk instead */ +#define QSPI_IDR_TDRE_Pos 1 /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Position */ +#define QSPI_IDR_TDRE_Msk (_U_(0x1) << QSPI_IDR_TDRE_Pos) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Mask */ +#define QSPI_IDR_TDRE QSPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TDRE_Msk instead */ +#define QSPI_IDR_TXEMPTY_Pos 2 /**< (QSPI_IDR) Transmission Registers Empty Disable Position */ +#define QSPI_IDR_TXEMPTY_Msk (_U_(0x1) << QSPI_IDR_TXEMPTY_Pos) /**< (QSPI_IDR) Transmission Registers Empty Disable Mask */ +#define QSPI_IDR_TXEMPTY QSPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_TXEMPTY_Msk instead */ +#define QSPI_IDR_OVRES_Pos 3 /**< (QSPI_IDR) Overrun Error Interrupt Disable Position */ +#define QSPI_IDR_OVRES_Msk (_U_(0x1) << QSPI_IDR_OVRES_Pos) /**< (QSPI_IDR) Overrun Error Interrupt Disable Mask */ +#define QSPI_IDR_OVRES QSPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_OVRES_Msk instead */ +#define QSPI_IDR_CSR_Pos 8 /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Position */ +#define QSPI_IDR_CSR_Msk (_U_(0x1) << QSPI_IDR_CSR_Pos) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Mask */ +#define QSPI_IDR_CSR QSPI_IDR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSR_Msk instead */ +#define QSPI_IDR_CSS_Pos 9 /**< (QSPI_IDR) Chip Select Status Interrupt Disable Position */ +#define QSPI_IDR_CSS_Msk (_U_(0x1) << QSPI_IDR_CSS_Pos) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Mask */ +#define QSPI_IDR_CSS QSPI_IDR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_CSS_Msk instead */ +#define QSPI_IDR_INSTRE_Pos 10 /**< (QSPI_IDR) Instruction End Interrupt Disable Position */ +#define QSPI_IDR_INSTRE_Msk (_U_(0x1) << QSPI_IDR_INSTRE_Pos) /**< (QSPI_IDR) Instruction End Interrupt Disable Mask */ +#define QSPI_IDR_INSTRE QSPI_IDR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IDR_INSTRE_Msk instead */ +#define QSPI_IDR_MASK _U_(0x70F) /**< \deprecated (QSPI_IDR) Register MASK (Use QSPI_IDR_Msk instead) */ +#define QSPI_IDR_Msk _U_(0x70F) /**< (QSPI_IDR) Register Mask */ + + +/* -------- QSPI_IMR : (QSPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */ + uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty Interrupt Mask */ + uint32_t TXEMPTY:1; /**< bit: 2 Transmission Registers Empty Mask */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t CSR:1; /**< bit: 8 Chip Select Rise Interrupt Mask */ + uint32_t CSS:1; /**< bit: 9 Chip Select Status Interrupt Mask */ + uint32_t INSTRE:1; /**< bit: 10 Instruction End Interrupt Mask */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_IMR_OFFSET (0x1C) /**< (QSPI_IMR) Interrupt Mask Register Offset */ + +#define QSPI_IMR_RDRF_Pos 0 /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define QSPI_IMR_RDRF_Msk (_U_(0x1) << QSPI_IMR_RDRF_Pos) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define QSPI_IMR_RDRF QSPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_RDRF_Msk instead */ +#define QSPI_IMR_TDRE_Pos 1 /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Position */ +#define QSPI_IMR_TDRE_Msk (_U_(0x1) << QSPI_IMR_TDRE_Pos) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Mask */ +#define QSPI_IMR_TDRE QSPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TDRE_Msk instead */ +#define QSPI_IMR_TXEMPTY_Pos 2 /**< (QSPI_IMR) Transmission Registers Empty Mask Position */ +#define QSPI_IMR_TXEMPTY_Msk (_U_(0x1) << QSPI_IMR_TXEMPTY_Pos) /**< (QSPI_IMR) Transmission Registers Empty Mask Mask */ +#define QSPI_IMR_TXEMPTY QSPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_TXEMPTY_Msk instead */ +#define QSPI_IMR_OVRES_Pos 3 /**< (QSPI_IMR) Overrun Error Interrupt Mask Position */ +#define QSPI_IMR_OVRES_Msk (_U_(0x1) << QSPI_IMR_OVRES_Pos) /**< (QSPI_IMR) Overrun Error Interrupt Mask Mask */ +#define QSPI_IMR_OVRES QSPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_OVRES_Msk instead */ +#define QSPI_IMR_CSR_Pos 8 /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Position */ +#define QSPI_IMR_CSR_Msk (_U_(0x1) << QSPI_IMR_CSR_Pos) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Mask */ +#define QSPI_IMR_CSR QSPI_IMR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSR_Msk instead */ +#define QSPI_IMR_CSS_Pos 9 /**< (QSPI_IMR) Chip Select Status Interrupt Mask Position */ +#define QSPI_IMR_CSS_Msk (_U_(0x1) << QSPI_IMR_CSS_Pos) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Mask */ +#define QSPI_IMR_CSS QSPI_IMR_CSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_CSS_Msk instead */ +#define QSPI_IMR_INSTRE_Pos 10 /**< (QSPI_IMR) Instruction End Interrupt Mask Position */ +#define QSPI_IMR_INSTRE_Msk (_U_(0x1) << QSPI_IMR_INSTRE_Pos) /**< (QSPI_IMR) Instruction End Interrupt Mask Mask */ +#define QSPI_IMR_INSTRE QSPI_IMR_INSTRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IMR_INSTRE_Msk instead */ +#define QSPI_IMR_MASK _U_(0x70F) /**< \deprecated (QSPI_IMR) Register MASK (Use QSPI_IMR_Msk instead) */ +#define QSPI_IMR_Msk _U_(0x70F) /**< (QSPI_IMR) Register Mask */ + + +/* -------- QSPI_SCR : (QSPI Offset: 0x20) (R/W 32) Serial Clock Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CPOL:1; /**< bit: 0 Clock Polarity */ + uint32_t CPHA:1; /**< bit: 1 Clock Phase */ + uint32_t :6; /**< bit: 2..7 Reserved */ + uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Baud Rate */ + uint32_t DLYBS:8; /**< bit: 16..23 Delay Before QSCK */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_SCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_SCR_OFFSET (0x20) /**< (QSPI_SCR) Serial Clock Register Offset */ + +#define QSPI_SCR_CPOL_Pos 0 /**< (QSPI_SCR) Clock Polarity Position */ +#define QSPI_SCR_CPOL_Msk (_U_(0x1) << QSPI_SCR_CPOL_Pos) /**< (QSPI_SCR) Clock Polarity Mask */ +#define QSPI_SCR_CPOL QSPI_SCR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPOL_Msk instead */ +#define QSPI_SCR_CPHA_Pos 1 /**< (QSPI_SCR) Clock Phase Position */ +#define QSPI_SCR_CPHA_Msk (_U_(0x1) << QSPI_SCR_CPHA_Pos) /**< (QSPI_SCR) Clock Phase Mask */ +#define QSPI_SCR_CPHA QSPI_SCR_CPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SCR_CPHA_Msk instead */ +#define QSPI_SCR_SCBR_Pos 8 /**< (QSPI_SCR) Serial Clock Baud Rate Position */ +#define QSPI_SCR_SCBR_Msk (_U_(0xFF) << QSPI_SCR_SCBR_Pos) /**< (QSPI_SCR) Serial Clock Baud Rate Mask */ +#define QSPI_SCR_SCBR(value) (QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)) +#define QSPI_SCR_DLYBS_Pos 16 /**< (QSPI_SCR) Delay Before QSCK Position */ +#define QSPI_SCR_DLYBS_Msk (_U_(0xFF) << QSPI_SCR_DLYBS_Pos) /**< (QSPI_SCR) Delay Before QSCK Mask */ +#define QSPI_SCR_DLYBS(value) (QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)) +#define QSPI_SCR_MASK _U_(0xFFFF03) /**< \deprecated (QSPI_SCR) Register MASK (Use QSPI_SCR_Msk instead) */ +#define QSPI_SCR_Msk _U_(0xFFFF03) /**< (QSPI_SCR) Register Mask */ + + +/* -------- QSPI_IAR : (QSPI Offset: 0x30) (R/W 32) Instruction Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ADDR:32; /**< bit: 0..31 Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_IAR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_IAR_OFFSET (0x30) /**< (QSPI_IAR) Instruction Address Register Offset */ + +#define QSPI_IAR_ADDR_Pos 0 /**< (QSPI_IAR) Address Position */ +#define QSPI_IAR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_IAR_ADDR_Pos) /**< (QSPI_IAR) Address Mask */ +#define QSPI_IAR_ADDR(value) (QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)) +#define QSPI_IAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_IAR) Register MASK (Use QSPI_IAR_Msk instead) */ +#define QSPI_IAR_Msk _U_(0xFFFFFFFF) /**< (QSPI_IAR) Register Mask */ + + +/* -------- QSPI_ICR : (QSPI Offset: 0x34) (R/W 32) Instruction Code Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t INST:8; /**< bit: 0..7 Instruction Code */ + uint32_t :8; /**< bit: 8..15 Reserved */ + uint32_t OPT:8; /**< bit: 16..23 Option Code */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_ICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_ICR_OFFSET (0x34) /**< (QSPI_ICR) Instruction Code Register Offset */ + +#define QSPI_ICR_INST_Pos 0 /**< (QSPI_ICR) Instruction Code Position */ +#define QSPI_ICR_INST_Msk (_U_(0xFF) << QSPI_ICR_INST_Pos) /**< (QSPI_ICR) Instruction Code Mask */ +#define QSPI_ICR_INST(value) (QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)) +#define QSPI_ICR_OPT_Pos 16 /**< (QSPI_ICR) Option Code Position */ +#define QSPI_ICR_OPT_Msk (_U_(0xFF) << QSPI_ICR_OPT_Pos) /**< (QSPI_ICR) Option Code Mask */ +#define QSPI_ICR_OPT(value) (QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)) +#define QSPI_ICR_MASK _U_(0xFF00FF) /**< \deprecated (QSPI_ICR) Register MASK (Use QSPI_ICR_Msk instead) */ +#define QSPI_ICR_Msk _U_(0xFF00FF) /**< (QSPI_ICR) Register Mask */ + + +/* -------- QSPI_IFR : (QSPI Offset: 0x38) (R/W 32) Instruction Frame Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WIDTH:3; /**< bit: 0..2 Width of Instruction Code, Address, Option Code and Data */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t INSTEN:1; /**< bit: 4 Instruction Enable */ + uint32_t ADDREN:1; /**< bit: 5 Address Enable */ + uint32_t OPTEN:1; /**< bit: 6 Option Enable */ + uint32_t DATAEN:1; /**< bit: 7 Data Enable */ + uint32_t OPTL:2; /**< bit: 8..9 Option Code Length */ + uint32_t ADDRL:1; /**< bit: 10 Address Length */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t TFRTYP:2; /**< bit: 12..13 Data Transfer Type */ + uint32_t CRM:1; /**< bit: 14 Continuous Read Mode */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t NBDUM:5; /**< bit: 16..20 Number Of Dummy Cycles */ + uint32_t :11; /**< bit: 21..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_IFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_IFR_OFFSET (0x38) /**< (QSPI_IFR) Instruction Frame Register Offset */ + +#define QSPI_IFR_WIDTH_Pos 0 /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Position */ +#define QSPI_IFR_WIDTH_Msk (_U_(0x7) << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Mask */ +#define QSPI_IFR_WIDTH(value) (QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (QSPI_IFR_WIDTH_DUAL_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (QSPI_IFR_WIDTH_QUAD_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_IO (QSPI_IFR_WIDTH_DUAL_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_IO (QSPI_IFR_WIDTH_QUAD_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_CMD (QSPI_IFR_WIDTH_DUAL_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_CMD (QSPI_IFR_WIDTH_QUAD_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_INSTEN_Pos 4 /**< (QSPI_IFR) Instruction Enable Position */ +#define QSPI_IFR_INSTEN_Msk (_U_(0x1) << QSPI_IFR_INSTEN_Pos) /**< (QSPI_IFR) Instruction Enable Mask */ +#define QSPI_IFR_INSTEN QSPI_IFR_INSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_INSTEN_Msk instead */ +#define QSPI_IFR_ADDREN_Pos 5 /**< (QSPI_IFR) Address Enable Position */ +#define QSPI_IFR_ADDREN_Msk (_U_(0x1) << QSPI_IFR_ADDREN_Pos) /**< (QSPI_IFR) Address Enable Mask */ +#define QSPI_IFR_ADDREN QSPI_IFR_ADDREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDREN_Msk instead */ +#define QSPI_IFR_OPTEN_Pos 6 /**< (QSPI_IFR) Option Enable Position */ +#define QSPI_IFR_OPTEN_Msk (_U_(0x1) << QSPI_IFR_OPTEN_Pos) /**< (QSPI_IFR) Option Enable Mask */ +#define QSPI_IFR_OPTEN QSPI_IFR_OPTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_OPTEN_Msk instead */ +#define QSPI_IFR_DATAEN_Pos 7 /**< (QSPI_IFR) Data Enable Position */ +#define QSPI_IFR_DATAEN_Msk (_U_(0x1) << QSPI_IFR_DATAEN_Pos) /**< (QSPI_IFR) Data Enable Mask */ +#define QSPI_IFR_DATAEN QSPI_IFR_DATAEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_DATAEN_Msk instead */ +#define QSPI_IFR_OPTL_Pos 8 /**< (QSPI_IFR) Option Code Length Position */ +#define QSPI_IFR_OPTL_Msk (_U_(0x3) << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) Option Code Length Mask */ +#define QSPI_IFR_OPTL(value) (QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)) +#define QSPI_IFR_OPTL_OPTION_1BIT_Val _U_(0x0) /**< (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT_Val _U_(0x1) /**< (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT_Val _U_(0x2) /**< (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT_Val _U_(0x3) /**< (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_OPTL_OPTION_1BIT (QSPI_IFR_OPTL_OPTION_1BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 1 bit long. Position */ +#define QSPI_IFR_OPTL_OPTION_2BIT (QSPI_IFR_OPTL_OPTION_2BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 2 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_4BIT (QSPI_IFR_OPTL_OPTION_4BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 4 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_8BIT (QSPI_IFR_OPTL_OPTION_8BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 8 bits long. Position */ +#define QSPI_IFR_ADDRL_Pos 10 /**< (QSPI_IFR) Address Length Position */ +#define QSPI_IFR_ADDRL_Msk (_U_(0x1) << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) Address Length Mask */ +#define QSPI_IFR_ADDRL QSPI_IFR_ADDRL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_ADDRL_Msk instead */ +#define QSPI_IFR_ADDRL_24_BIT_Val _U_(0x0) /**< (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT_Val _U_(0x1) /**< (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_ADDRL_24_BIT (QSPI_IFR_ADDRL_24_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 24 bits long. Position */ +#define QSPI_IFR_ADDRL_32_BIT (QSPI_IFR_ADDRL_32_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 32 bits long. Position */ +#define QSPI_IFR_TFRTYP_Pos 12 /**< (QSPI_IFR) Data Transfer Type Position */ +#define QSPI_IFR_TFRTYP_Msk (_U_(0x3) << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Data Transfer Type Mask */ +#define QSPI_IFR_TFRTYP(value) (QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)) +#define QSPI_IFR_TFRTYP_TRSFR_READ_Val _U_(0x0) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val _U_(0x1) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_Val _U_(0x2) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val _U_(0x3) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ (QSPI_IFR_TFRTYP_TRSFR_READ_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (QSPI_IFR_TFRTYP_TRSFR_WRITE_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */ +#define QSPI_IFR_CRM_Pos 14 /**< (QSPI_IFR) Continuous Read Mode Position */ +#define QSPI_IFR_CRM_Msk (_U_(0x1) << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) Continuous Read Mode Mask */ +#define QSPI_IFR_CRM QSPI_IFR_CRM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_IFR_CRM_Msk instead */ +#define QSPI_IFR_CRM_DISABLED_Val _U_(0x0) /**< (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED_Val _U_(0x1) /**< (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_CRM_DISABLED (QSPI_IFR_CRM_DISABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is disabled. Position */ +#define QSPI_IFR_CRM_ENABLED (QSPI_IFR_CRM_ENABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is enabled. Position */ +#define QSPI_IFR_NBDUM_Pos 16 /**< (QSPI_IFR) Number Of Dummy Cycles Position */ +#define QSPI_IFR_NBDUM_Msk (_U_(0x1F) << QSPI_IFR_NBDUM_Pos) /**< (QSPI_IFR) Number Of Dummy Cycles Mask */ +#define QSPI_IFR_NBDUM(value) (QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)) +#define QSPI_IFR_MASK _U_(0x1F77F7) /**< \deprecated (QSPI_IFR) Register MASK (Use QSPI_IFR_Msk instead) */ +#define QSPI_IFR_Msk _U_(0x1F77F7) /**< (QSPI_IFR) Register Mask */ + + +/* -------- QSPI_SMR : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SCREN:1; /**< bit: 0 Scrambling/Unscrambling Enable */ + uint32_t RVDIS:1; /**< bit: 1 Scrambling/Unscrambling Random Value Disable */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_SMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_SMR_OFFSET (0x40) /**< (QSPI_SMR) Scrambling Mode Register Offset */ + +#define QSPI_SMR_SCREN_Pos 0 /**< (QSPI_SMR) Scrambling/Unscrambling Enable Position */ +#define QSPI_SMR_SCREN_Msk (_U_(0x1) << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Mask */ +#define QSPI_SMR_SCREN QSPI_SMR_SCREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_SCREN_Msk instead */ +#define QSPI_SMR_SCREN_DISABLED_Val _U_(0x0) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED_Val _U_(0x1) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_SCREN_DISABLED (QSPI_SMR_SCREN_DISABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. Position */ +#define QSPI_SMR_SCREN_ENABLED (QSPI_SMR_SCREN_ENABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. Position */ +#define QSPI_SMR_RVDIS_Pos 1 /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Position */ +#define QSPI_SMR_RVDIS_Msk (_U_(0x1) << QSPI_SMR_RVDIS_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Mask */ +#define QSPI_SMR_RVDIS QSPI_SMR_RVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_SMR_RVDIS_Msk instead */ +#define QSPI_SMR_MASK _U_(0x03) /**< \deprecated (QSPI_SMR) Register MASK (Use QSPI_SMR_Msk instead) */ +#define QSPI_SMR_Msk _U_(0x03) /**< (QSPI_SMR) Register Mask */ + + +/* -------- QSPI_SKR : (QSPI Offset: 0x44) (/W 32) Scrambling Key Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t USRK:32; /**< bit: 0..31 User Scrambling Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_SKR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_SKR_OFFSET (0x44) /**< (QSPI_SKR) Scrambling Key Register Offset */ + +#define QSPI_SKR_USRK_Pos 0 /**< (QSPI_SKR) User Scrambling Key Position */ +#define QSPI_SKR_USRK_Msk (_U_(0xFFFFFFFF) << QSPI_SKR_USRK_Pos) /**< (QSPI_SKR) User Scrambling Key Mask */ +#define QSPI_SKR_USRK(value) (QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)) +#define QSPI_SKR_MASK _U_(0xFFFFFFFF) /**< \deprecated (QSPI_SKR) Register MASK (Use QSPI_SKR_Msk instead) */ +#define QSPI_SKR_Msk _U_(0xFFFFFFFF) /**< (QSPI_SKR) Register Mask */ + + +/* -------- QSPI_WPMR : (QSPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_WPMR_OFFSET (0xE4) /**< (QSPI_WPMR) Write Protection Mode Register Offset */ + +#define QSPI_WPMR_WPEN_Pos 0 /**< (QSPI_WPMR) Write Protection Enable Position */ +#define QSPI_WPMR_WPEN_Msk (_U_(0x1) << QSPI_WPMR_WPEN_Pos) /**< (QSPI_WPMR) Write Protection Enable Mask */ +#define QSPI_WPMR_WPEN QSPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPMR_WPEN_Msk instead */ +#define QSPI_WPMR_WPKEY_Pos 8 /**< (QSPI_WPMR) Write Protection Key Position */ +#define QSPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Write Protection Key Mask */ +#define QSPI_WPMR_WPKEY(value) (QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)) +#define QSPI_WPMR_WPKEY_PASSWD_Val _U_(0x515350) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define QSPI_WPMR_WPKEY_PASSWD (QSPI_WPMR_WPKEY_PASSWD_Val << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define QSPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (QSPI_WPMR) Register MASK (Use QSPI_WPMR_Msk instead) */ +#define QSPI_WPMR_Msk _U_(0xFFFFFF01) /**< (QSPI_WPMR) Register Mask */ + + +/* -------- QSPI_WPSR : (QSPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} QSPI_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define QSPI_WPSR_OFFSET (0xE8) /**< (QSPI_WPSR) Write Protection Status Register Offset */ + +#define QSPI_WPSR_WPVS_Pos 0 /**< (QSPI_WPSR) Write Protection Violation Status Position */ +#define QSPI_WPSR_WPVS_Msk (_U_(0x1) << QSPI_WPSR_WPVS_Pos) /**< (QSPI_WPSR) Write Protection Violation Status Mask */ +#define QSPI_WPSR_WPVS QSPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use QSPI_WPSR_WPVS_Msk instead */ +#define QSPI_WPSR_WPVSRC_Pos 8 /**< (QSPI_WPSR) Write Protection Violation Source Position */ +#define QSPI_WPSR_WPVSRC_Msk (_U_(0xFF) << QSPI_WPSR_WPVSRC_Pos) /**< (QSPI_WPSR) Write Protection Violation Source Mask */ +#define QSPI_WPSR_WPVSRC(value) (QSPI_WPSR_WPVSRC_Msk & ((value) << QSPI_WPSR_WPVSRC_Pos)) +#define QSPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (QSPI_WPSR) Register MASK (Use QSPI_WPSR_Msk instead) */ +#define QSPI_WPSR_Msk _U_(0xFF01) /**< (QSPI_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief QSPI hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< (QSPI Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< (QSPI Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< (QSPI Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< (QSPI Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< (QSPI Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< (QSPI Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< (QSPI Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< (QSPI Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< (QSPI Offset: 0x20) Serial Clock Register */ + __I uint8_t Reserved1[12]; + __IO uint32_t QSPI_IAR; /**< (QSPI Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< (QSPI Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< (QSPI Offset: 0x38) Instruction Frame Register */ + __I uint8_t Reserved2[4]; + __IO uint32_t QSPI_SMR; /**< (QSPI Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< (QSPI Offset: 0x44) Scrambling Key Register */ + __I uint8_t Reserved3[156]; + __IO uint32_t QSPI_WPMR; /**< (QSPI Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< (QSPI Offset: 0xE8) Write Protection Status Register */ +} Qspi; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief QSPI hardware registers */ +typedef struct { + __O QSPI_CR_Type QSPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO QSPI_MR_Type QSPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I QSPI_RDR_Type QSPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O QSPI_TDR_Type QSPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I QSPI_SR_Type QSPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O QSPI_IER_Type QSPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O QSPI_IDR_Type QSPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I QSPI_IMR_Type QSPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __IO QSPI_SCR_Type QSPI_SCR; /**< Offset: 0x20 (R/W 32) Serial Clock Register */ + __I uint8_t Reserved1[12]; + __IO QSPI_IAR_Type QSPI_IAR; /**< Offset: 0x30 (R/W 32) Instruction Address Register */ + __IO QSPI_ICR_Type QSPI_ICR; /**< Offset: 0x34 (R/W 32) Instruction Code Register */ + __IO QSPI_IFR_Type QSPI_IFR; /**< Offset: 0x38 (R/W 32) Instruction Frame Register */ + __I uint8_t Reserved2[4]; + __IO QSPI_SMR_Type QSPI_SMR; /**< Offset: 0x40 (R/W 32) Scrambling Mode Register */ + __O QSPI_SKR_Type QSPI_SKR; /**< Offset: 0x44 ( /W 32) Scrambling Key Register */ + __I uint8_t Reserved3[156]; + __IO QSPI_WPMR_Type QSPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I QSPI_WPSR_Type QSPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Qspi; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Quad Serial Peripheral Interface */ + +#endif /* _SAME70_QSPI_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/rstc.h b/bsp/microchip/same70/bsp/same70b/include/component/rstc.h new file mode 100644 index 0000000000..a0bbf5abe3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/rstc.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief Component description for RSTC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RSTC_COMPONENT_H_ +#define _SAME70_RSTC_COMPONENT_H_ +#define _SAME70_RSTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Reset Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RSTC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define RSTC_11009 /**< (RSTC) Module ID */ +#define REV_RSTC N /**< (RSTC) Module revision */ + +/* -------- RSTC_CR : (RSTC Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PROCRST:1; /**< bit: 0 Processor Reset */ + uint32_t :2; /**< bit: 1..2 Reserved */ + uint32_t EXTRST:1; /**< bit: 3 External Reset */ + uint32_t :20; /**< bit: 4..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 System Reset Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSTC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_CR_OFFSET (0x00) /**< (RSTC_CR) Control Register Offset */ + +#define RSTC_CR_PROCRST_Pos 0 /**< (RSTC_CR) Processor Reset Position */ +#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */ +#define RSTC_CR_PROCRST RSTC_CR_PROCRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_PROCRST_Msk instead */ +#define RSTC_CR_EXTRST_Pos 3 /**< (RSTC_CR) External Reset Position */ +#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */ +#define RSTC_CR_EXTRST RSTC_CR_EXTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_CR_EXTRST_Msk instead */ +#define RSTC_CR_KEY_Pos 24 /**< (RSTC_CR) System Reset Key Position */ +#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */ +#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)) +#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */ +#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSTC_CR_MASK _U_(0xFF000009) /**< \deprecated (RSTC_CR) Register MASK (Use RSTC_CR_Msk instead) */ +#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */ + + +/* -------- RSTC_SR : (RSTC Offset: 0x04) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t URSTS:1; /**< bit: 0 User Reset Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t RSTTYP:3; /**< bit: 8..10 Reset Type */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t NRSTL:1; /**< bit: 16 NRST Pin Level */ + uint32_t SRCMP:1; /**< bit: 17 Software Reset Command in Progress */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSTC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_SR_OFFSET (0x04) /**< (RSTC_SR) Status Register Offset */ + +#define RSTC_SR_URSTS_Pos 0 /**< (RSTC_SR) User Reset Status Position */ +#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */ +#define RSTC_SR_URSTS RSTC_SR_URSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_URSTS_Msk instead */ +#define RSTC_SR_RSTTYP_Pos 8 /**< (RSTC_SR) Reset Type Position */ +#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */ +#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos)) +#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */ +#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */ +#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */ +#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */ +#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */ +#define RSTC_SR_NRSTL_Pos 16 /**< (RSTC_SR) NRST Pin Level Position */ +#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */ +#define RSTC_SR_NRSTL RSTC_SR_NRSTL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_NRSTL_Msk instead */ +#define RSTC_SR_SRCMP_Pos 17 /**< (RSTC_SR) Software Reset Command in Progress Position */ +#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */ +#define RSTC_SR_SRCMP RSTC_SR_SRCMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_SR_SRCMP_Msk instead */ +#define RSTC_SR_MASK _U_(0x30701) /**< \deprecated (RSTC_SR) Register MASK (Use RSTC_SR_Msk instead) */ +#define RSTC_SR_Msk _U_(0x30701) /**< (RSTC_SR) Register Mask */ + + +/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t URSTEN:1; /**< bit: 0 User Reset Enable */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t URSTIEN:1; /**< bit: 4 User Reset Interrupt Enable */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t ERSTL:4; /**< bit: 8..11 External Reset Length */ + uint32_t :12; /**< bit: 12..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 Write Access Password */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSTC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSTC_MR_OFFSET (0x08) /**< (RSTC_MR) Mode Register Offset */ + +#define RSTC_MR_URSTEN_Pos 0 /**< (RSTC_MR) User Reset Enable Position */ +#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */ +#define RSTC_MR_URSTEN RSTC_MR_URSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTEN_Msk instead */ +#define RSTC_MR_URSTIEN_Pos 4 /**< (RSTC_MR) User Reset Interrupt Enable Position */ +#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */ +#define RSTC_MR_URSTIEN RSTC_MR_URSTIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSTC_MR_URSTIEN_Msk instead */ +#define RSTC_MR_ERSTL_Pos 8 /**< (RSTC_MR) External Reset Length Position */ +#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */ +#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)) +#define RSTC_MR_KEY_Pos 24 /**< (RSTC_MR) Write Access Password Position */ +#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */ +#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)) +#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define RSTC_MR_MASK _U_(0xFF000F11) /**< \deprecated (RSTC_MR) Register MASK (Use RSTC_MR_Msk instead) */ +#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief RSTC hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< (RSTC Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< (RSTC Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< (RSTC Offset: 0x08) Mode Register */ +} Rstc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief RSTC hardware registers */ +typedef struct { + __O RSTC_CR_Type RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I RSTC_SR_Type RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */ + __IO RSTC_MR_Type RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */ +} Rstc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Reset Controller */ + +#endif /* _SAME70_RSTC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/rswdt.h b/bsp/microchip/same70/bsp/same70b/include/component/rswdt.h new file mode 100644 index 0000000000..f850948e9c --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/rswdt.h @@ -0,0 +1,169 @@ +/** + * \file + * + * \brief Component description for RSWDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RSWDT_COMPONENT_H_ +#define _SAME70_RSWDT_COMPONENT_H_ +#define _SAME70_RSWDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Reinforced Safety Watchdog Timer + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RSWDT */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define RSWDT_11110 /**< (RSWDT) Module ID */ +#define REV_RSWDT G /**< (RSWDT) Module revision */ + +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */ + uint32_t :23; /**< bit: 1..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 Password */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSWDT_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSWDT_CR_OFFSET (0x00) /**< (RSWDT_CR) Control Register Offset */ + +#define RSWDT_CR_WDRSTT_Pos 0 /**< (RSWDT_CR) Watchdog Restart Position */ +#define RSWDT_CR_WDRSTT_Msk (_U_(0x1) << RSWDT_CR_WDRSTT_Pos) /**< (RSWDT_CR) Watchdog Restart Mask */ +#define RSWDT_CR_WDRSTT RSWDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_CR_WDRSTT_Msk instead */ +#define RSWDT_CR_KEY_Pos 24 /**< (RSWDT_CR) Password Position */ +#define RSWDT_CR_KEY_Msk (_U_(0xFF) << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Password Mask */ +#define RSWDT_CR_KEY(value) (RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)) +#define RSWDT_CR_KEY_PASSWD_Val _U_(0xC4) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +#define RSWDT_CR_KEY_PASSWD (RSWDT_CR_KEY_PASSWD_Val << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSWDT_CR_MASK _U_(0xFF000001) /**< \deprecated (RSWDT_CR) Register MASK (Use RSWDT_CR_Msk instead) */ +#define RSWDT_CR_Msk _U_(0xFF000001) /**< (RSWDT_CR) Register Mask */ + + +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */ + uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */ + uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */ + uint32_t :1; /**< bit: 14 Reserved */ + uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */ + uint32_t ALLONES:12; /**< bit: 16..27 Must Always Be Written with 0xFFF */ + uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */ + uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSWDT_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSWDT_MR_OFFSET (0x04) /**< (RSWDT_MR) Mode Register Offset */ + +#define RSWDT_MR_WDV_Pos 0 /**< (RSWDT_MR) Watchdog Counter Value Position */ +#define RSWDT_MR_WDV_Msk (_U_(0xFFF) << RSWDT_MR_WDV_Pos) /**< (RSWDT_MR) Watchdog Counter Value Mask */ +#define RSWDT_MR_WDV(value) (RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)) +#define RSWDT_MR_WDFIEN_Pos 12 /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Position */ +#define RSWDT_MR_WDFIEN_Msk (_U_(0x1) << RSWDT_MR_WDFIEN_Pos) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define RSWDT_MR_WDFIEN RSWDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDFIEN_Msk instead */ +#define RSWDT_MR_WDRSTEN_Pos 13 /**< (RSWDT_MR) Watchdog Reset Enable Position */ +#define RSWDT_MR_WDRSTEN_Msk (_U_(0x1) << RSWDT_MR_WDRSTEN_Pos) /**< (RSWDT_MR) Watchdog Reset Enable Mask */ +#define RSWDT_MR_WDRSTEN RSWDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDRSTEN_Msk instead */ +#define RSWDT_MR_WDDIS_Pos 15 /**< (RSWDT_MR) Watchdog Disable Position */ +#define RSWDT_MR_WDDIS_Msk (_U_(0x1) << RSWDT_MR_WDDIS_Pos) /**< (RSWDT_MR) Watchdog Disable Mask */ +#define RSWDT_MR_WDDIS RSWDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDIS_Msk instead */ +#define RSWDT_MR_ALLONES_Pos 16 /**< (RSWDT_MR) Must Always Be Written with 0xFFF Position */ +#define RSWDT_MR_ALLONES_Msk (_U_(0xFFF) << RSWDT_MR_ALLONES_Pos) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Mask */ +#define RSWDT_MR_ALLONES(value) (RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)) +#define RSWDT_MR_WDDBGHLT_Pos 28 /**< (RSWDT_MR) Watchdog Debug Halt Position */ +#define RSWDT_MR_WDDBGHLT_Msk (_U_(0x1) << RSWDT_MR_WDDBGHLT_Pos) /**< (RSWDT_MR) Watchdog Debug Halt Mask */ +#define RSWDT_MR_WDDBGHLT RSWDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDBGHLT_Msk instead */ +#define RSWDT_MR_WDIDLEHLT_Pos 29 /**< (RSWDT_MR) Watchdog Idle Halt Position */ +#define RSWDT_MR_WDIDLEHLT_Msk (_U_(0x1) << RSWDT_MR_WDIDLEHLT_Pos) /**< (RSWDT_MR) Watchdog Idle Halt Mask */ +#define RSWDT_MR_WDIDLEHLT RSWDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDIDLEHLT_Msk instead */ +#define RSWDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (RSWDT_MR) Register MASK (Use RSWDT_MR_Msk instead) */ +#define RSWDT_MR_Msk _U_(0x3FFFBFFF) /**< (RSWDT_MR) Register Mask */ + + +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RSWDT_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RSWDT_SR_OFFSET (0x08) /**< (RSWDT_SR) Status Register Offset */ + +#define RSWDT_SR_WDUNF_Pos 0 /**< (RSWDT_SR) Watchdog Underflow Position */ +#define RSWDT_SR_WDUNF_Msk (_U_(0x1) << RSWDT_SR_WDUNF_Pos) /**< (RSWDT_SR) Watchdog Underflow Mask */ +#define RSWDT_SR_WDUNF RSWDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_SR_WDUNF_Msk instead */ +#define RSWDT_SR_MASK _U_(0x01) /**< \deprecated (RSWDT_SR) Register MASK (Use RSWDT_SR_Msk instead) */ +#define RSWDT_SR_Msk _U_(0x01) /**< (RSWDT_SR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief RSWDT hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< (RSWDT Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< (RSWDT Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< (RSWDT Offset: 0x08) Status Register */ +} Rswdt; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief RSWDT hardware registers */ +typedef struct { + __O RSWDT_CR_Type RSWDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO RSWDT_MR_Type RSWDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I RSWDT_SR_Type RSWDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} Rswdt; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Reinforced Safety Watchdog Timer */ + +#endif /* _SAME70_RSWDT_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/rtc.h b/bsp/microchip/same70/bsp/same70b/include/component/rtc.h new file mode 100644 index 0000000000..e4695a18cb --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/rtc.h @@ -0,0 +1,680 @@ +/** + * \file + * + * \brief Component description for RTC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RTC_COMPONENT_H_ +#define _SAME70_RTC_COMPONENT_H_ +#define _SAME70_RTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Real-time Clock + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RTC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define RTC_6056 /**< (RTC) Module ID */ +#define REV_RTC ZB /**< (RTC) Module revision */ + +/* -------- RTC_CR : (RTC Offset: 0x00) (R/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UPDTIM:1; /**< bit: 0 Update Request Time Register */ + uint32_t UPDCAL:1; /**< bit: 1 Update Request Calendar Register */ + uint32_t :6; /**< bit: 2..7 Reserved */ + uint32_t TIMEVSEL:2; /**< bit: 8..9 Time Event Selection */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t CALEVSEL:2; /**< bit: 16..17 Calendar Event Selection */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_CR_OFFSET (0x00) /**< (RTC_CR) Control Register Offset */ + +#define RTC_CR_UPDTIM_Pos 0 /**< (RTC_CR) Update Request Time Register Position */ +#define RTC_CR_UPDTIM_Msk (_U_(0x1) << RTC_CR_UPDTIM_Pos) /**< (RTC_CR) Update Request Time Register Mask */ +#define RTC_CR_UPDTIM RTC_CR_UPDTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDTIM_Msk instead */ +#define RTC_CR_UPDCAL_Pos 1 /**< (RTC_CR) Update Request Calendar Register Position */ +#define RTC_CR_UPDCAL_Msk (_U_(0x1) << RTC_CR_UPDCAL_Pos) /**< (RTC_CR) Update Request Calendar Register Mask */ +#define RTC_CR_UPDCAL RTC_CR_UPDCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDCAL_Msk instead */ +#define RTC_CR_TIMEVSEL_Pos 8 /**< (RTC_CR) Time Event Selection Position */ +#define RTC_CR_TIMEVSEL_Msk (_U_(0x3) << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Time Event Selection Mask */ +#define RTC_CR_TIMEVSEL(value) (RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)) +#define RTC_CR_TIMEVSEL_MINUTE_Val _U_(0x0) /**< (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR_Val _U_(0x1) /**< (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT_Val _U_(0x2) /**< (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON_Val _U_(0x3) /**< (RTC_CR) Every day at noon */ +#define RTC_CR_TIMEVSEL_MINUTE (RTC_CR_TIMEVSEL_MINUTE_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Minute change Position */ +#define RTC_CR_TIMEVSEL_HOUR (RTC_CR_TIMEVSEL_HOUR_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Hour change Position */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (RTC_CR_TIMEVSEL_MIDNIGHT_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at midnight Position */ +#define RTC_CR_TIMEVSEL_NOON (RTC_CR_TIMEVSEL_NOON_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at noon Position */ +#define RTC_CR_CALEVSEL_Pos 16 /**< (RTC_CR) Calendar Event Selection Position */ +#define RTC_CR_CALEVSEL_Msk (_U_(0x3) << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Calendar Event Selection Mask */ +#define RTC_CR_CALEVSEL(value) (RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)) +#define RTC_CR_CALEVSEL_WEEK_Val _U_(0x0) /**< (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH_Val _U_(0x1) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR_Val _U_(0x2) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) */ +#define RTC_CR_CALEVSEL_WEEK (RTC_CR_CALEVSEL_WEEK_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Week change (every Monday at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_MONTH (RTC_CR_CALEVSEL_MONTH_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_YEAR (RTC_CR_CALEVSEL_YEAR_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) Position */ +#define RTC_CR_MASK _U_(0x30303) /**< \deprecated (RTC_CR) Register MASK (Use RTC_CR_Msk instead) */ +#define RTC_CR_Msk _U_(0x30303) /**< (RTC_CR) Register Mask */ + + +/* -------- RTC_MR : (RTC Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HRMOD:1; /**< bit: 0 12-/24-hour Mode */ + uint32_t PERSIAN:1; /**< bit: 1 PERSIAN Calendar */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t NEGPPM:1; /**< bit: 4 NEGative PPM Correction */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t CORRECTION:7; /**< bit: 8..14 Slow Clock Correction */ + uint32_t HIGHPPM:1; /**< bit: 15 HIGH PPM Correction */ + uint32_t OUT0:3; /**< bit: 16..18 RTCOUT0 OutputSource Selection */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t OUT1:3; /**< bit: 20..22 RTCOUT1 Output Source Selection */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t THIGH:3; /**< bit: 24..26 High Duration of the Output Pulse */ + uint32_t :1; /**< bit: 27 Reserved */ + uint32_t TPERIOD:2; /**< bit: 28..29 Period of the Output Pulse */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_MR_OFFSET (0x04) /**< (RTC_MR) Mode Register Offset */ + +#define RTC_MR_HRMOD_Pos 0 /**< (RTC_MR) 12-/24-hour Mode Position */ +#define RTC_MR_HRMOD_Msk (_U_(0x1) << RTC_MR_HRMOD_Pos) /**< (RTC_MR) 12-/24-hour Mode Mask */ +#define RTC_MR_HRMOD RTC_MR_HRMOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HRMOD_Msk instead */ +#define RTC_MR_PERSIAN_Pos 1 /**< (RTC_MR) PERSIAN Calendar Position */ +#define RTC_MR_PERSIAN_Msk (_U_(0x1) << RTC_MR_PERSIAN_Pos) /**< (RTC_MR) PERSIAN Calendar Mask */ +#define RTC_MR_PERSIAN RTC_MR_PERSIAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_PERSIAN_Msk instead */ +#define RTC_MR_NEGPPM_Pos 4 /**< (RTC_MR) NEGative PPM Correction Position */ +#define RTC_MR_NEGPPM_Msk (_U_(0x1) << RTC_MR_NEGPPM_Pos) /**< (RTC_MR) NEGative PPM Correction Mask */ +#define RTC_MR_NEGPPM RTC_MR_NEGPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_NEGPPM_Msk instead */ +#define RTC_MR_CORRECTION_Pos 8 /**< (RTC_MR) Slow Clock Correction Position */ +#define RTC_MR_CORRECTION_Msk (_U_(0x7F) << RTC_MR_CORRECTION_Pos) /**< (RTC_MR) Slow Clock Correction Mask */ +#define RTC_MR_CORRECTION(value) (RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)) +#define RTC_MR_HIGHPPM_Pos 15 /**< (RTC_MR) HIGH PPM Correction Position */ +#define RTC_MR_HIGHPPM_Msk (_U_(0x1) << RTC_MR_HIGHPPM_Pos) /**< (RTC_MR) HIGH PPM Correction Mask */ +#define RTC_MR_HIGHPPM RTC_MR_HIGHPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HIGHPPM_Msk instead */ +#define RTC_MR_OUT0_Pos 16 /**< (RTC_MR) RTCOUT0 OutputSource Selection Position */ +#define RTC_MR_OUT0_Msk (_U_(0x7) << RTC_MR_OUT0_Pos) /**< (RTC_MR) RTCOUT0 OutputSource Selection Mask */ +#define RTC_MR_OUT0(value) (RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)) +#define RTC_MR_OUT0_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT0_NO_WAVE (RTC_MR_OUT0_NO_WAVE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT0_FREQ1HZ (RTC_MR_OUT0_FREQ1HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ32HZ (RTC_MR_OUT0_FREQ32HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ64HZ (RTC_MR_OUT0_FREQ64HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ512HZ (RTC_MR_OUT0_FREQ512HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT0_ALARM_TOGGLE (RTC_MR_OUT0_ALARM_TOGGLE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT0_ALARM_FLAG (RTC_MR_OUT0_ALARM_FLAG_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT0_PROG_PULSE (RTC_MR_OUT0_PROG_PULSE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_OUT1_Pos 20 /**< (RTC_MR) RTCOUT1 Output Source Selection Position */ +#define RTC_MR_OUT1_Msk (_U_(0x7) << RTC_MR_OUT1_Pos) /**< (RTC_MR) RTCOUT1 Output Source Selection Mask */ +#define RTC_MR_OUT1(value) (RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)) +#define RTC_MR_OUT1_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_NO_WAVE (RTC_MR_OUT1_NO_WAVE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT1_FREQ1HZ (RTC_MR_OUT1_FREQ1HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ32HZ (RTC_MR_OUT1_FREQ32HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ64HZ (RTC_MR_OUT1_FREQ64HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ512HZ (RTC_MR_OUT1_FREQ512HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT1_ALARM_TOGGLE (RTC_MR_OUT1_ALARM_TOGGLE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT1_ALARM_FLAG (RTC_MR_OUT1_ALARM_FLAG_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT1_PROG_PULSE (RTC_MR_OUT1_PROG_PULSE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_THIGH_Pos 24 /**< (RTC_MR) High Duration of the Output Pulse Position */ +#define RTC_MR_THIGH_Msk (_U_(0x7) << RTC_MR_THIGH_Pos) /**< (RTC_MR) High Duration of the Output Pulse Mask */ +#define RTC_MR_THIGH(value) (RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)) +#define RTC_MR_THIGH_H_31MS_Val _U_(0x0) /**< (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS_Val _U_(0x1) /**< (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS_Val _U_(0x2) /**< (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US_Val _U_(0x3) /**< (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US_Val _U_(0x4) /**< (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US_Val _U_(0x5) /**< (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US_Val _U_(0x6) /**< (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US_Val _U_(0x7) /**< (RTC_MR) 15.2 us */ +#define RTC_MR_THIGH_H_31MS (RTC_MR_THIGH_H_31MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 31.2 ms Position */ +#define RTC_MR_THIGH_H_16MS (RTC_MR_THIGH_H_16MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.6 ms Position */ +#define RTC_MR_THIGH_H_4MS (RTC_MR_THIGH_H_4MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 3.91 ms Position */ +#define RTC_MR_THIGH_H_976US (RTC_MR_THIGH_H_976US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 976 us Position */ +#define RTC_MR_THIGH_H_488US (RTC_MR_THIGH_H_488US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 488 us Position */ +#define RTC_MR_THIGH_H_122US (RTC_MR_THIGH_H_122US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 122 us Position */ +#define RTC_MR_THIGH_H_30US (RTC_MR_THIGH_H_30US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 30.5 us Position */ +#define RTC_MR_THIGH_H_15US (RTC_MR_THIGH_H_15US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.2 us Position */ +#define RTC_MR_TPERIOD_Pos 28 /**< (RTC_MR) Period of the Output Pulse Position */ +#define RTC_MR_TPERIOD_Msk (_U_(0x3) << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) Period of the Output Pulse Mask */ +#define RTC_MR_TPERIOD(value) (RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)) +#define RTC_MR_TPERIOD_P_1S_Val _U_(0x0) /**< (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS_Val _U_(0x1) /**< (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS_Val _U_(0x2) /**< (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS_Val _U_(0x3) /**< (RTC_MR) 125 ms */ +#define RTC_MR_TPERIOD_P_1S (RTC_MR_TPERIOD_P_1S_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 1 second Position */ +#define RTC_MR_TPERIOD_P_500MS (RTC_MR_TPERIOD_P_500MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 500 ms Position */ +#define RTC_MR_TPERIOD_P_250MS (RTC_MR_TPERIOD_P_250MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 250 ms Position */ +#define RTC_MR_TPERIOD_P_125MS (RTC_MR_TPERIOD_P_125MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 125 ms Position */ +#define RTC_MR_MASK _U_(0x3777FF13) /**< \deprecated (RTC_MR) Register MASK (Use RTC_MR_Msk instead) */ +#define RTC_MR_Msk _U_(0x3777FF13) /**< (RTC_MR) Register Mask */ + + +/* -------- RTC_TIMR : (RTC Offset: 0x08) (R/W 32) Time Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SEC:7; /**< bit: 0..6 Current Second */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MIN:7; /**< bit: 8..14 Current Minute */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t HOUR:6; /**< bit: 16..21 Current Hour */ + uint32_t AMPM:1; /**< bit: 22 Ante Meridiem Post Meridiem Indicator */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_TIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_TIMR_OFFSET (0x08) /**< (RTC_TIMR) Time Register Offset */ + +#define RTC_TIMR_SEC_Pos 0 /**< (RTC_TIMR) Current Second Position */ +#define RTC_TIMR_SEC_Msk (_U_(0x7F) << RTC_TIMR_SEC_Pos) /**< (RTC_TIMR) Current Second Mask */ +#define RTC_TIMR_SEC(value) (RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)) +#define RTC_TIMR_MIN_Pos 8 /**< (RTC_TIMR) Current Minute Position */ +#define RTC_TIMR_MIN_Msk (_U_(0x7F) << RTC_TIMR_MIN_Pos) /**< (RTC_TIMR) Current Minute Mask */ +#define RTC_TIMR_MIN(value) (RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)) +#define RTC_TIMR_HOUR_Pos 16 /**< (RTC_TIMR) Current Hour Position */ +#define RTC_TIMR_HOUR_Msk (_U_(0x3F) << RTC_TIMR_HOUR_Pos) /**< (RTC_TIMR) Current Hour Mask */ +#define RTC_TIMR_HOUR(value) (RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)) +#define RTC_TIMR_AMPM_Pos 22 /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Position */ +#define RTC_TIMR_AMPM_Msk (_U_(0x1) << RTC_TIMR_AMPM_Pos) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Mask */ +#define RTC_TIMR_AMPM RTC_TIMR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMR_AMPM_Msk instead */ +#define RTC_TIMR_MASK _U_(0x7F7F7F) /**< \deprecated (RTC_TIMR) Register MASK (Use RTC_TIMR_Msk instead) */ +#define RTC_TIMR_Msk _U_(0x7F7F7F) /**< (RTC_TIMR) Register Mask */ + + +/* -------- RTC_CALR : (RTC Offset: 0x0c) (R/W 32) Calendar Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CENT:7; /**< bit: 0..6 Current Century */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t YEAR:8; /**< bit: 8..15 Current Year */ + uint32_t MONTH:5; /**< bit: 16..20 Current Month */ + uint32_t DAY:3; /**< bit: 21..23 Current Day in Current Week */ + uint32_t DATE:6; /**< bit: 24..29 Current Day in Current Month */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_CALR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_CALR_OFFSET (0x0C) /**< (RTC_CALR) Calendar Register Offset */ + +#define RTC_CALR_CENT_Pos 0 /**< (RTC_CALR) Current Century Position */ +#define RTC_CALR_CENT_Msk (_U_(0x7F) << RTC_CALR_CENT_Pos) /**< (RTC_CALR) Current Century Mask */ +#define RTC_CALR_CENT(value) (RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)) +#define RTC_CALR_YEAR_Pos 8 /**< (RTC_CALR) Current Year Position */ +#define RTC_CALR_YEAR_Msk (_U_(0xFF) << RTC_CALR_YEAR_Pos) /**< (RTC_CALR) Current Year Mask */ +#define RTC_CALR_YEAR(value) (RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)) +#define RTC_CALR_MONTH_Pos 16 /**< (RTC_CALR) Current Month Position */ +#define RTC_CALR_MONTH_Msk (_U_(0x1F) << RTC_CALR_MONTH_Pos) /**< (RTC_CALR) Current Month Mask */ +#define RTC_CALR_MONTH(value) (RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)) +#define RTC_CALR_DAY_Pos 21 /**< (RTC_CALR) Current Day in Current Week Position */ +#define RTC_CALR_DAY_Msk (_U_(0x7) << RTC_CALR_DAY_Pos) /**< (RTC_CALR) Current Day in Current Week Mask */ +#define RTC_CALR_DAY(value) (RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)) +#define RTC_CALR_DATE_Pos 24 /**< (RTC_CALR) Current Day in Current Month Position */ +#define RTC_CALR_DATE_Msk (_U_(0x3F) << RTC_CALR_DATE_Pos) /**< (RTC_CALR) Current Day in Current Month Mask */ +#define RTC_CALR_DATE(value) (RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)) +#define RTC_CALR_MASK _U_(0x3FFFFF7F) /**< \deprecated (RTC_CALR) Register MASK (Use RTC_CALR_Msk instead) */ +#define RTC_CALR_Msk _U_(0x3FFFFF7F) /**< (RTC_CALR) Register Mask */ + + +/* -------- RTC_TIMALR : (RTC Offset: 0x10) (R/W 32) Time Alarm Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SEC:7; /**< bit: 0..6 Second Alarm */ + uint32_t SECEN:1; /**< bit: 7 Second Alarm Enable */ + uint32_t MIN:7; /**< bit: 8..14 Minute Alarm */ + uint32_t MINEN:1; /**< bit: 15 Minute Alarm Enable */ + uint32_t HOUR:6; /**< bit: 16..21 Hour Alarm */ + uint32_t AMPM:1; /**< bit: 22 AM/PM Indicator */ + uint32_t HOUREN:1; /**< bit: 23 Hour Alarm Enable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_TIMALR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_TIMALR_OFFSET (0x10) /**< (RTC_TIMALR) Time Alarm Register Offset */ + +#define RTC_TIMALR_SEC_Pos 0 /**< (RTC_TIMALR) Second Alarm Position */ +#define RTC_TIMALR_SEC_Msk (_U_(0x7F) << RTC_TIMALR_SEC_Pos) /**< (RTC_TIMALR) Second Alarm Mask */ +#define RTC_TIMALR_SEC(value) (RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)) +#define RTC_TIMALR_SECEN_Pos 7 /**< (RTC_TIMALR) Second Alarm Enable Position */ +#define RTC_TIMALR_SECEN_Msk (_U_(0x1) << RTC_TIMALR_SECEN_Pos) /**< (RTC_TIMALR) Second Alarm Enable Mask */ +#define RTC_TIMALR_SECEN RTC_TIMALR_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_SECEN_Msk instead */ +#define RTC_TIMALR_MIN_Pos 8 /**< (RTC_TIMALR) Minute Alarm Position */ +#define RTC_TIMALR_MIN_Msk (_U_(0x7F) << RTC_TIMALR_MIN_Pos) /**< (RTC_TIMALR) Minute Alarm Mask */ +#define RTC_TIMALR_MIN(value) (RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)) +#define RTC_TIMALR_MINEN_Pos 15 /**< (RTC_TIMALR) Minute Alarm Enable Position */ +#define RTC_TIMALR_MINEN_Msk (_U_(0x1) << RTC_TIMALR_MINEN_Pos) /**< (RTC_TIMALR) Minute Alarm Enable Mask */ +#define RTC_TIMALR_MINEN RTC_TIMALR_MINEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_MINEN_Msk instead */ +#define RTC_TIMALR_HOUR_Pos 16 /**< (RTC_TIMALR) Hour Alarm Position */ +#define RTC_TIMALR_HOUR_Msk (_U_(0x3F) << RTC_TIMALR_HOUR_Pos) /**< (RTC_TIMALR) Hour Alarm Mask */ +#define RTC_TIMALR_HOUR(value) (RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)) +#define RTC_TIMALR_AMPM_Pos 22 /**< (RTC_TIMALR) AM/PM Indicator Position */ +#define RTC_TIMALR_AMPM_Msk (_U_(0x1) << RTC_TIMALR_AMPM_Pos) /**< (RTC_TIMALR) AM/PM Indicator Mask */ +#define RTC_TIMALR_AMPM RTC_TIMALR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_AMPM_Msk instead */ +#define RTC_TIMALR_HOUREN_Pos 23 /**< (RTC_TIMALR) Hour Alarm Enable Position */ +#define RTC_TIMALR_HOUREN_Msk (_U_(0x1) << RTC_TIMALR_HOUREN_Pos) /**< (RTC_TIMALR) Hour Alarm Enable Mask */ +#define RTC_TIMALR_HOUREN RTC_TIMALR_HOUREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_HOUREN_Msk instead */ +#define RTC_TIMALR_MASK _U_(0xFFFFFF) /**< \deprecated (RTC_TIMALR) Register MASK (Use RTC_TIMALR_Msk instead) */ +#define RTC_TIMALR_Msk _U_(0xFFFFFF) /**< (RTC_TIMALR) Register Mask */ + + +/* -------- RTC_CALALR : (RTC Offset: 0x14) (R/W 32) Calendar Alarm Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :16; /**< bit: 0..15 Reserved */ + uint32_t MONTH:5; /**< bit: 16..20 Month Alarm */ + uint32_t :2; /**< bit: 21..22 Reserved */ + uint32_t MTHEN:1; /**< bit: 23 Month Alarm Enable */ + uint32_t DATE:6; /**< bit: 24..29 Date Alarm */ + uint32_t :1; /**< bit: 30 Reserved */ + uint32_t DATEEN:1; /**< bit: 31 Date Alarm Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_CALALR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_CALALR_OFFSET (0x14) /**< (RTC_CALALR) Calendar Alarm Register Offset */ + +#define RTC_CALALR_MONTH_Pos 16 /**< (RTC_CALALR) Month Alarm Position */ +#define RTC_CALALR_MONTH_Msk (_U_(0x1F) << RTC_CALALR_MONTH_Pos) /**< (RTC_CALALR) Month Alarm Mask */ +#define RTC_CALALR_MONTH(value) (RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)) +#define RTC_CALALR_MTHEN_Pos 23 /**< (RTC_CALALR) Month Alarm Enable Position */ +#define RTC_CALALR_MTHEN_Msk (_U_(0x1) << RTC_CALALR_MTHEN_Pos) /**< (RTC_CALALR) Month Alarm Enable Mask */ +#define RTC_CALALR_MTHEN RTC_CALALR_MTHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_MTHEN_Msk instead */ +#define RTC_CALALR_DATE_Pos 24 /**< (RTC_CALALR) Date Alarm Position */ +#define RTC_CALALR_DATE_Msk (_U_(0x3F) << RTC_CALALR_DATE_Pos) /**< (RTC_CALALR) Date Alarm Mask */ +#define RTC_CALALR_DATE(value) (RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)) +#define RTC_CALALR_DATEEN_Pos 31 /**< (RTC_CALALR) Date Alarm Enable Position */ +#define RTC_CALALR_DATEEN_Msk (_U_(0x1) << RTC_CALALR_DATEEN_Pos) /**< (RTC_CALALR) Date Alarm Enable Mask */ +#define RTC_CALALR_DATEEN RTC_CALALR_DATEEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_DATEEN_Msk instead */ +#define RTC_CALALR_MASK _U_(0xBF9F0000) /**< \deprecated (RTC_CALALR) Register MASK (Use RTC_CALALR_Msk instead) */ +#define RTC_CALALR_Msk _U_(0xBF9F0000) /**< (RTC_CALALR) Register Mask */ + + +/* -------- RTC_SR : (RTC Offset: 0x18) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ACKUPD:1; /**< bit: 0 Acknowledge for Update */ + uint32_t ALARM:1; /**< bit: 1 Alarm Flag */ + uint32_t SEC:1; /**< bit: 2 Second Event */ + uint32_t TIMEV:1; /**< bit: 3 Time Event */ + uint32_t CALEV:1; /**< bit: 4 Calendar Event */ + uint32_t TDERR:1; /**< bit: 5 Time and/or Date Free Running Error */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_SR_OFFSET (0x18) /**< (RTC_SR) Status Register Offset */ + +#define RTC_SR_ACKUPD_Pos 0 /**< (RTC_SR) Acknowledge for Update Position */ +#define RTC_SR_ACKUPD_Msk (_U_(0x1) << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Acknowledge for Update Mask */ +#define RTC_SR_ACKUPD RTC_SR_ACKUPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ACKUPD_Msk instead */ +#define RTC_SR_ACKUPD_FREERUN_Val _U_(0x0) /**< (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE_Val _U_(0x1) /**< (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ACKUPD_FREERUN (RTC_SR_ACKUPD_FREERUN_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers cannot be updated. Position */ +#define RTC_SR_ACKUPD_UPDATE (RTC_SR_ACKUPD_UPDATE_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers can be updated. Position */ +#define RTC_SR_ALARM_Pos 1 /**< (RTC_SR) Alarm Flag Position */ +#define RTC_SR_ALARM_Msk (_U_(0x1) << RTC_SR_ALARM_Pos) /**< (RTC_SR) Alarm Flag Mask */ +#define RTC_SR_ALARM RTC_SR_ALARM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ALARM_Msk instead */ +#define RTC_SR_ALARM_NO_ALARMEVENT_Val _U_(0x0) /**< (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT_Val _U_(0x1) /**< (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_ALARM_NO_ALARMEVENT (RTC_SR_ALARM_NO_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) No alarm matching condition occurred. Position */ +#define RTC_SR_ALARM_ALARMEVENT (RTC_SR_ALARM_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) An alarm matching condition has occurred. Position */ +#define RTC_SR_SEC_Pos 2 /**< (RTC_SR) Second Event Position */ +#define RTC_SR_SEC_Msk (_U_(0x1) << RTC_SR_SEC_Pos) /**< (RTC_SR) Second Event Mask */ +#define RTC_SR_SEC RTC_SR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_SEC_Msk instead */ +#define RTC_SR_SEC_NO_SECEVENT_Val _U_(0x0) /**< (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT_Val _U_(0x1) /**< (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_SEC_NO_SECEVENT (RTC_SR_SEC_NO_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) No second event has occurred since the last clear. Position */ +#define RTC_SR_SEC_SECEVENT (RTC_SR_SEC_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) At least one second event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_Pos 3 /**< (RTC_SR) Time Event Position */ +#define RTC_SR_TIMEV_Msk (_U_(0x1) << RTC_SR_TIMEV_Pos) /**< (RTC_SR) Time Event Mask */ +#define RTC_SR_TIMEV RTC_SR_TIMEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TIMEV_Msk instead */ +#define RTC_SR_TIMEV_NO_TIMEVENT_Val _U_(0x0) /**< (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT_Val _U_(0x1) /**< (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_NO_TIMEVENT (RTC_SR_TIMEV_NO_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) No time event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_TIMEVENT (RTC_SR_TIMEV_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) At least one time event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_Pos 4 /**< (RTC_SR) Calendar Event Position */ +#define RTC_SR_CALEV_Msk (_U_(0x1) << RTC_SR_CALEV_Pos) /**< (RTC_SR) Calendar Event Mask */ +#define RTC_SR_CALEV RTC_SR_CALEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_CALEV_Msk instead */ +#define RTC_SR_CALEV_NO_CALEVENT_Val _U_(0x0) /**< (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT_Val _U_(0x1) /**< (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_NO_CALEVENT (RTC_SR_CALEV_NO_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) No calendar event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_CALEVENT (RTC_SR_CALEV_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) At least one calendar event has occurred since the last clear. Position */ +#define RTC_SR_TDERR_Pos 5 /**< (RTC_SR) Time and/or Date Free Running Error Position */ +#define RTC_SR_TDERR_Msk (_U_(0x1) << RTC_SR_TDERR_Pos) /**< (RTC_SR) Time and/or Date Free Running Error Mask */ +#define RTC_SR_TDERR RTC_SR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TDERR_Msk instead */ +#define RTC_SR_TDERR_CORRECT_Val _U_(0x0) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE_Val _U_(0x1) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +#define RTC_SR_TDERR_CORRECT (RTC_SR_TDERR_CORRECT_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). Position */ +#define RTC_SR_TDERR_ERR_TIMEDATE (RTC_SR_TDERR_ERR_TIMEDATE_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. Position */ +#define RTC_SR_MASK _U_(0x3F) /**< \deprecated (RTC_SR) Register MASK (Use RTC_SR_Msk instead) */ +#define RTC_SR_Msk _U_(0x3F) /**< (RTC_SR) Register Mask */ + + +/* -------- RTC_SCCR : (RTC Offset: 0x1c) (/W 32) Status Clear Command Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ACKCLR:1; /**< bit: 0 Acknowledge Clear */ + uint32_t ALRCLR:1; /**< bit: 1 Alarm Clear */ + uint32_t SECCLR:1; /**< bit: 2 Second Clear */ + uint32_t TIMCLR:1; /**< bit: 3 Time Clear */ + uint32_t CALCLR:1; /**< bit: 4 Calendar Clear */ + uint32_t TDERRCLR:1; /**< bit: 5 Time and/or Date Free Running Error Clear */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_SCCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_SCCR_OFFSET (0x1C) /**< (RTC_SCCR) Status Clear Command Register Offset */ + +#define RTC_SCCR_ACKCLR_Pos 0 /**< (RTC_SCCR) Acknowledge Clear Position */ +#define RTC_SCCR_ACKCLR_Msk (_U_(0x1) << RTC_SCCR_ACKCLR_Pos) /**< (RTC_SCCR) Acknowledge Clear Mask */ +#define RTC_SCCR_ACKCLR RTC_SCCR_ACKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ACKCLR_Msk instead */ +#define RTC_SCCR_ALRCLR_Pos 1 /**< (RTC_SCCR) Alarm Clear Position */ +#define RTC_SCCR_ALRCLR_Msk (_U_(0x1) << RTC_SCCR_ALRCLR_Pos) /**< (RTC_SCCR) Alarm Clear Mask */ +#define RTC_SCCR_ALRCLR RTC_SCCR_ALRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ALRCLR_Msk instead */ +#define RTC_SCCR_SECCLR_Pos 2 /**< (RTC_SCCR) Second Clear Position */ +#define RTC_SCCR_SECCLR_Msk (_U_(0x1) << RTC_SCCR_SECCLR_Pos) /**< (RTC_SCCR) Second Clear Mask */ +#define RTC_SCCR_SECCLR RTC_SCCR_SECCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_SECCLR_Msk instead */ +#define RTC_SCCR_TIMCLR_Pos 3 /**< (RTC_SCCR) Time Clear Position */ +#define RTC_SCCR_TIMCLR_Msk (_U_(0x1) << RTC_SCCR_TIMCLR_Pos) /**< (RTC_SCCR) Time Clear Mask */ +#define RTC_SCCR_TIMCLR RTC_SCCR_TIMCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TIMCLR_Msk instead */ +#define RTC_SCCR_CALCLR_Pos 4 /**< (RTC_SCCR) Calendar Clear Position */ +#define RTC_SCCR_CALCLR_Msk (_U_(0x1) << RTC_SCCR_CALCLR_Pos) /**< (RTC_SCCR) Calendar Clear Mask */ +#define RTC_SCCR_CALCLR RTC_SCCR_CALCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_CALCLR_Msk instead */ +#define RTC_SCCR_TDERRCLR_Pos 5 /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Position */ +#define RTC_SCCR_TDERRCLR_Msk (_U_(0x1) << RTC_SCCR_TDERRCLR_Pos) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Mask */ +#define RTC_SCCR_TDERRCLR RTC_SCCR_TDERRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TDERRCLR_Msk instead */ +#define RTC_SCCR_MASK _U_(0x3F) /**< \deprecated (RTC_SCCR) Register MASK (Use RTC_SCCR_Msk instead) */ +#define RTC_SCCR_Msk _U_(0x3F) /**< (RTC_SCCR) Register Mask */ + + +/* -------- RTC_IER : (RTC Offset: 0x20) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ACKEN:1; /**< bit: 0 Acknowledge Update Interrupt Enable */ + uint32_t ALREN:1; /**< bit: 1 Alarm Interrupt Enable */ + uint32_t SECEN:1; /**< bit: 2 Second Event Interrupt Enable */ + uint32_t TIMEN:1; /**< bit: 3 Time Event Interrupt Enable */ + uint32_t CALEN:1; /**< bit: 4 Calendar Event Interrupt Enable */ + uint32_t TDERREN:1; /**< bit: 5 Time and/or Date Error Interrupt Enable */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_IER_OFFSET (0x20) /**< (RTC_IER) Interrupt Enable Register Offset */ + +#define RTC_IER_ACKEN_Pos 0 /**< (RTC_IER) Acknowledge Update Interrupt Enable Position */ +#define RTC_IER_ACKEN_Msk (_U_(0x1) << RTC_IER_ACKEN_Pos) /**< (RTC_IER) Acknowledge Update Interrupt Enable Mask */ +#define RTC_IER_ACKEN RTC_IER_ACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ACKEN_Msk instead */ +#define RTC_IER_ALREN_Pos 1 /**< (RTC_IER) Alarm Interrupt Enable Position */ +#define RTC_IER_ALREN_Msk (_U_(0x1) << RTC_IER_ALREN_Pos) /**< (RTC_IER) Alarm Interrupt Enable Mask */ +#define RTC_IER_ALREN RTC_IER_ALREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ALREN_Msk instead */ +#define RTC_IER_SECEN_Pos 2 /**< (RTC_IER) Second Event Interrupt Enable Position */ +#define RTC_IER_SECEN_Msk (_U_(0x1) << RTC_IER_SECEN_Pos) /**< (RTC_IER) Second Event Interrupt Enable Mask */ +#define RTC_IER_SECEN RTC_IER_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_SECEN_Msk instead */ +#define RTC_IER_TIMEN_Pos 3 /**< (RTC_IER) Time Event Interrupt Enable Position */ +#define RTC_IER_TIMEN_Msk (_U_(0x1) << RTC_IER_TIMEN_Pos) /**< (RTC_IER) Time Event Interrupt Enable Mask */ +#define RTC_IER_TIMEN RTC_IER_TIMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TIMEN_Msk instead */ +#define RTC_IER_CALEN_Pos 4 /**< (RTC_IER) Calendar Event Interrupt Enable Position */ +#define RTC_IER_CALEN_Msk (_U_(0x1) << RTC_IER_CALEN_Pos) /**< (RTC_IER) Calendar Event Interrupt Enable Mask */ +#define RTC_IER_CALEN RTC_IER_CALEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_CALEN_Msk instead */ +#define RTC_IER_TDERREN_Pos 5 /**< (RTC_IER) Time and/or Date Error Interrupt Enable Position */ +#define RTC_IER_TDERREN_Msk (_U_(0x1) << RTC_IER_TDERREN_Pos) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Mask */ +#define RTC_IER_TDERREN RTC_IER_TDERREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TDERREN_Msk instead */ +#define RTC_IER_MASK _U_(0x3F) /**< \deprecated (RTC_IER) Register MASK (Use RTC_IER_Msk instead) */ +#define RTC_IER_Msk _U_(0x3F) /**< (RTC_IER) Register Mask */ + + +/* -------- RTC_IDR : (RTC Offset: 0x24) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ACKDIS:1; /**< bit: 0 Acknowledge Update Interrupt Disable */ + uint32_t ALRDIS:1; /**< bit: 1 Alarm Interrupt Disable */ + uint32_t SECDIS:1; /**< bit: 2 Second Event Interrupt Disable */ + uint32_t TIMDIS:1; /**< bit: 3 Time Event Interrupt Disable */ + uint32_t CALDIS:1; /**< bit: 4 Calendar Event Interrupt Disable */ + uint32_t TDERRDIS:1; /**< bit: 5 Time and/or Date Error Interrupt Disable */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_IDR_OFFSET (0x24) /**< (RTC_IDR) Interrupt Disable Register Offset */ + +#define RTC_IDR_ACKDIS_Pos 0 /**< (RTC_IDR) Acknowledge Update Interrupt Disable Position */ +#define RTC_IDR_ACKDIS_Msk (_U_(0x1) << RTC_IDR_ACKDIS_Pos) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Mask */ +#define RTC_IDR_ACKDIS RTC_IDR_ACKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ACKDIS_Msk instead */ +#define RTC_IDR_ALRDIS_Pos 1 /**< (RTC_IDR) Alarm Interrupt Disable Position */ +#define RTC_IDR_ALRDIS_Msk (_U_(0x1) << RTC_IDR_ALRDIS_Pos) /**< (RTC_IDR) Alarm Interrupt Disable Mask */ +#define RTC_IDR_ALRDIS RTC_IDR_ALRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ALRDIS_Msk instead */ +#define RTC_IDR_SECDIS_Pos 2 /**< (RTC_IDR) Second Event Interrupt Disable Position */ +#define RTC_IDR_SECDIS_Msk (_U_(0x1) << RTC_IDR_SECDIS_Pos) /**< (RTC_IDR) Second Event Interrupt Disable Mask */ +#define RTC_IDR_SECDIS RTC_IDR_SECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_SECDIS_Msk instead */ +#define RTC_IDR_TIMDIS_Pos 3 /**< (RTC_IDR) Time Event Interrupt Disable Position */ +#define RTC_IDR_TIMDIS_Msk (_U_(0x1) << RTC_IDR_TIMDIS_Pos) /**< (RTC_IDR) Time Event Interrupt Disable Mask */ +#define RTC_IDR_TIMDIS RTC_IDR_TIMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TIMDIS_Msk instead */ +#define RTC_IDR_CALDIS_Pos 4 /**< (RTC_IDR) Calendar Event Interrupt Disable Position */ +#define RTC_IDR_CALDIS_Msk (_U_(0x1) << RTC_IDR_CALDIS_Pos) /**< (RTC_IDR) Calendar Event Interrupt Disable Mask */ +#define RTC_IDR_CALDIS RTC_IDR_CALDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_CALDIS_Msk instead */ +#define RTC_IDR_TDERRDIS_Pos 5 /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Position */ +#define RTC_IDR_TDERRDIS_Msk (_U_(0x1) << RTC_IDR_TDERRDIS_Pos) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Mask */ +#define RTC_IDR_TDERRDIS RTC_IDR_TDERRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TDERRDIS_Msk instead */ +#define RTC_IDR_MASK _U_(0x3F) /**< \deprecated (RTC_IDR) Register MASK (Use RTC_IDR_Msk instead) */ +#define RTC_IDR_Msk _U_(0x3F) /**< (RTC_IDR) Register Mask */ + + +/* -------- RTC_IMR : (RTC Offset: 0x28) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ACK:1; /**< bit: 0 Acknowledge Update Interrupt Mask */ + uint32_t ALR:1; /**< bit: 1 Alarm Interrupt Mask */ + uint32_t SEC:1; /**< bit: 2 Second Event Interrupt Mask */ + uint32_t TIM:1; /**< bit: 3 Time Event Interrupt Mask */ + uint32_t CAL:1; /**< bit: 4 Calendar Event Interrupt Mask */ + uint32_t TDERR:1; /**< bit: 5 Time and/or Date Error Mask */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_IMR_OFFSET (0x28) /**< (RTC_IMR) Interrupt Mask Register Offset */ + +#define RTC_IMR_ACK_Pos 0 /**< (RTC_IMR) Acknowledge Update Interrupt Mask Position */ +#define RTC_IMR_ACK_Msk (_U_(0x1) << RTC_IMR_ACK_Pos) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Mask */ +#define RTC_IMR_ACK RTC_IMR_ACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ACK_Msk instead */ +#define RTC_IMR_ALR_Pos 1 /**< (RTC_IMR) Alarm Interrupt Mask Position */ +#define RTC_IMR_ALR_Msk (_U_(0x1) << RTC_IMR_ALR_Pos) /**< (RTC_IMR) Alarm Interrupt Mask Mask */ +#define RTC_IMR_ALR RTC_IMR_ALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ALR_Msk instead */ +#define RTC_IMR_SEC_Pos 2 /**< (RTC_IMR) Second Event Interrupt Mask Position */ +#define RTC_IMR_SEC_Msk (_U_(0x1) << RTC_IMR_SEC_Pos) /**< (RTC_IMR) Second Event Interrupt Mask Mask */ +#define RTC_IMR_SEC RTC_IMR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_SEC_Msk instead */ +#define RTC_IMR_TIM_Pos 3 /**< (RTC_IMR) Time Event Interrupt Mask Position */ +#define RTC_IMR_TIM_Msk (_U_(0x1) << RTC_IMR_TIM_Pos) /**< (RTC_IMR) Time Event Interrupt Mask Mask */ +#define RTC_IMR_TIM RTC_IMR_TIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TIM_Msk instead */ +#define RTC_IMR_CAL_Pos 4 /**< (RTC_IMR) Calendar Event Interrupt Mask Position */ +#define RTC_IMR_CAL_Msk (_U_(0x1) << RTC_IMR_CAL_Pos) /**< (RTC_IMR) Calendar Event Interrupt Mask Mask */ +#define RTC_IMR_CAL RTC_IMR_CAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_CAL_Msk instead */ +#define RTC_IMR_TDERR_Pos 5 /**< (RTC_IMR) Time and/or Date Error Mask Position */ +#define RTC_IMR_TDERR_Msk (_U_(0x1) << RTC_IMR_TDERR_Pos) /**< (RTC_IMR) Time and/or Date Error Mask Mask */ +#define RTC_IMR_TDERR RTC_IMR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TDERR_Msk instead */ +#define RTC_IMR_MASK _U_(0x3F) /**< \deprecated (RTC_IMR) Register MASK (Use RTC_IMR_Msk instead) */ +#define RTC_IMR_Msk _U_(0x3F) /**< (RTC_IMR) Register Mask */ + + +/* -------- RTC_VER : (RTC Offset: 0x2c) (R/ 32) Valid Entry Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NVTIM:1; /**< bit: 0 Non-valid Time */ + uint32_t NVCAL:1; /**< bit: 1 Non-valid Calendar */ + uint32_t NVTIMALR:1; /**< bit: 2 Non-valid Time Alarm */ + uint32_t NVCALALR:1; /**< bit: 3 Non-valid Calendar Alarm */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTC_VER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTC_VER_OFFSET (0x2C) /**< (RTC_VER) Valid Entry Register Offset */ + +#define RTC_VER_NVTIM_Pos 0 /**< (RTC_VER) Non-valid Time Position */ +#define RTC_VER_NVTIM_Msk (_U_(0x1) << RTC_VER_NVTIM_Pos) /**< (RTC_VER) Non-valid Time Mask */ +#define RTC_VER_NVTIM RTC_VER_NVTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIM_Msk instead */ +#define RTC_VER_NVCAL_Pos 1 /**< (RTC_VER) Non-valid Calendar Position */ +#define RTC_VER_NVCAL_Msk (_U_(0x1) << RTC_VER_NVCAL_Pos) /**< (RTC_VER) Non-valid Calendar Mask */ +#define RTC_VER_NVCAL RTC_VER_NVCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCAL_Msk instead */ +#define RTC_VER_NVTIMALR_Pos 2 /**< (RTC_VER) Non-valid Time Alarm Position */ +#define RTC_VER_NVTIMALR_Msk (_U_(0x1) << RTC_VER_NVTIMALR_Pos) /**< (RTC_VER) Non-valid Time Alarm Mask */ +#define RTC_VER_NVTIMALR RTC_VER_NVTIMALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIMALR_Msk instead */ +#define RTC_VER_NVCALALR_Pos 3 /**< (RTC_VER) Non-valid Calendar Alarm Position */ +#define RTC_VER_NVCALALR_Msk (_U_(0x1) << RTC_VER_NVCALALR_Pos) /**< (RTC_VER) Non-valid Calendar Alarm Mask */ +#define RTC_VER_NVCALALR RTC_VER_NVCALALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCALALR_Msk instead */ +#define RTC_VER_MASK _U_(0x0F) /**< \deprecated (RTC_VER) Register MASK (Use RTC_VER_Msk instead) */ +#define RTC_VER_Msk _U_(0x0F) /**< (RTC_VER) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief RTC hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< (RTC Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< (RTC Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< (RTC Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< (RTC Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< (RTC Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< (RTC Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< (RTC Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< (RTC Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< (RTC Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< (RTC Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< (RTC Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< (RTC Offset: 0x2C) Valid Entry Register */ +} Rtc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief RTC hardware registers */ +typedef struct { + __IO RTC_CR_Type RTC_CR; /**< Offset: 0x00 (R/W 32) Control Register */ + __IO RTC_MR_Type RTC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO RTC_TIMR_Type RTC_TIMR; /**< Offset: 0x08 (R/W 32) Time Register */ + __IO RTC_CALR_Type RTC_CALR; /**< Offset: 0x0C (R/W 32) Calendar Register */ + __IO RTC_TIMALR_Type RTC_TIMALR; /**< Offset: 0x10 (R/W 32) Time Alarm Register */ + __IO RTC_CALALR_Type RTC_CALALR; /**< Offset: 0x14 (R/W 32) Calendar Alarm Register */ + __I RTC_SR_Type RTC_SR; /**< Offset: 0x18 (R/ 32) Status Register */ + __O RTC_SCCR_Type RTC_SCCR; /**< Offset: 0x1C ( /W 32) Status Clear Command Register */ + __O RTC_IER_Type RTC_IER; /**< Offset: 0x20 ( /W 32) Interrupt Enable Register */ + __O RTC_IDR_Type RTC_IDR; /**< Offset: 0x24 ( /W 32) Interrupt Disable Register */ + __I RTC_IMR_Type RTC_IMR; /**< Offset: 0x28 (R/ 32) Interrupt Mask Register */ + __I RTC_VER_Type RTC_VER; /**< Offset: 0x2C (R/ 32) Valid Entry Register */ +} Rtc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Real-time Clock */ + +#endif /* _SAME70_RTC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/rtt.h b/bsp/microchip/same70/bsp/same70b/include/component/rtt.h new file mode 100644 index 0000000000..758082d9db --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/rtt.h @@ -0,0 +1,186 @@ +/** + * \file + * + * \brief Component description for RTT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RTT_COMPONENT_H_ +#define _SAME70_RTT_COMPONENT_H_ +#define _SAME70_RTT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Real-time Timer + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR RTT */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define RTT_6081 /**< (RTT) Module ID */ +#define REV_RTT M /**< (RTT) Module revision */ + +/* -------- RTT_MR : (RTT Offset: 0x00) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RTPRES:16; /**< bit: 0..15 Real-time Timer Prescaler Value */ + uint32_t ALMIEN:1; /**< bit: 16 Alarm Interrupt Enable */ + uint32_t RTTINCIEN:1; /**< bit: 17 Real-time Timer Increment Interrupt Enable */ + uint32_t RTTRST:1; /**< bit: 18 Real-time Timer Restart */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t RTTDIS:1; /**< bit: 20 Real-time Timer Disable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t RTC1HZ:1; /**< bit: 24 Real-Time Clock 1Hz Clock Selection */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTT_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTT_MR_OFFSET (0x00) /**< (RTT_MR) Mode Register Offset */ + +#define RTT_MR_RTPRES_Pos 0 /**< (RTT_MR) Real-time Timer Prescaler Value Position */ +#define RTT_MR_RTPRES_Msk (_U_(0xFFFF) << RTT_MR_RTPRES_Pos) /**< (RTT_MR) Real-time Timer Prescaler Value Mask */ +#define RTT_MR_RTPRES(value) (RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)) +#define RTT_MR_ALMIEN_Pos 16 /**< (RTT_MR) Alarm Interrupt Enable Position */ +#define RTT_MR_ALMIEN_Msk (_U_(0x1) << RTT_MR_ALMIEN_Pos) /**< (RTT_MR) Alarm Interrupt Enable Mask */ +#define RTT_MR_ALMIEN RTT_MR_ALMIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_ALMIEN_Msk instead */ +#define RTT_MR_RTTINCIEN_Pos 17 /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Position */ +#define RTT_MR_RTTINCIEN_Msk (_U_(0x1) << RTT_MR_RTTINCIEN_Pos) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Mask */ +#define RTT_MR_RTTINCIEN RTT_MR_RTTINCIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTINCIEN_Msk instead */ +#define RTT_MR_RTTRST_Pos 18 /**< (RTT_MR) Real-time Timer Restart Position */ +#define RTT_MR_RTTRST_Msk (_U_(0x1) << RTT_MR_RTTRST_Pos) /**< (RTT_MR) Real-time Timer Restart Mask */ +#define RTT_MR_RTTRST RTT_MR_RTTRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTRST_Msk instead */ +#define RTT_MR_RTTDIS_Pos 20 /**< (RTT_MR) Real-time Timer Disable Position */ +#define RTT_MR_RTTDIS_Msk (_U_(0x1) << RTT_MR_RTTDIS_Pos) /**< (RTT_MR) Real-time Timer Disable Mask */ +#define RTT_MR_RTTDIS RTT_MR_RTTDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTTDIS_Msk instead */ +#define RTT_MR_RTC1HZ_Pos 24 /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Position */ +#define RTT_MR_RTC1HZ_Msk (_U_(0x1) << RTT_MR_RTC1HZ_Pos) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Mask */ +#define RTT_MR_RTC1HZ RTT_MR_RTC1HZ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_MR_RTC1HZ_Msk instead */ +#define RTT_MR_MASK _U_(0x117FFFF) /**< \deprecated (RTT_MR) Register MASK (Use RTT_MR_Msk instead) */ +#define RTT_MR_Msk _U_(0x117FFFF) /**< (RTT_MR) Register Mask */ + + +/* -------- RTT_AR : (RTT Offset: 0x04) (R/W 32) Alarm Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ALMV:32; /**< bit: 0..31 Alarm Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTT_AR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTT_AR_OFFSET (0x04) /**< (RTT_AR) Alarm Register Offset */ + +#define RTT_AR_ALMV_Pos 0 /**< (RTT_AR) Alarm Value Position */ +#define RTT_AR_ALMV_Msk (_U_(0xFFFFFFFF) << RTT_AR_ALMV_Pos) /**< (RTT_AR) Alarm Value Mask */ +#define RTT_AR_ALMV(value) (RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)) +#define RTT_AR_MASK _U_(0xFFFFFFFF) /**< \deprecated (RTT_AR) Register MASK (Use RTT_AR_Msk instead) */ +#define RTT_AR_Msk _U_(0xFFFFFFFF) /**< (RTT_AR) Register Mask */ + + +/* -------- RTT_VR : (RTT Offset: 0x08) (R/ 32) Value Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CRTV:32; /**< bit: 0..31 Current Real-time Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTT_VR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTT_VR_OFFSET (0x08) /**< (RTT_VR) Value Register Offset */ + +#define RTT_VR_CRTV_Pos 0 /**< (RTT_VR) Current Real-time Value Position */ +#define RTT_VR_CRTV_Msk (_U_(0xFFFFFFFF) << RTT_VR_CRTV_Pos) /**< (RTT_VR) Current Real-time Value Mask */ +#define RTT_VR_CRTV(value) (RTT_VR_CRTV_Msk & ((value) << RTT_VR_CRTV_Pos)) +#define RTT_VR_MASK _U_(0xFFFFFFFF) /**< \deprecated (RTT_VR) Register MASK (Use RTT_VR_Msk instead) */ +#define RTT_VR_Msk _U_(0xFFFFFFFF) /**< (RTT_VR) Register Mask */ + + +/* -------- RTT_SR : (RTT Offset: 0x0c) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ALMS:1; /**< bit: 0 Real-time Alarm Status (cleared on read) */ + uint32_t RTTINC:1; /**< bit: 1 Prescaler Roll-over Status (cleared on read) */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} RTT_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define RTT_SR_OFFSET (0x0C) /**< (RTT_SR) Status Register Offset */ + +#define RTT_SR_ALMS_Pos 0 /**< (RTT_SR) Real-time Alarm Status (cleared on read) Position */ +#define RTT_SR_ALMS_Msk (_U_(0x1) << RTT_SR_ALMS_Pos) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Mask */ +#define RTT_SR_ALMS RTT_SR_ALMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_SR_ALMS_Msk instead */ +#define RTT_SR_RTTINC_Pos 1 /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Position */ +#define RTT_SR_RTTINC_Msk (_U_(0x1) << RTT_SR_RTTINC_Pos) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Mask */ +#define RTT_SR_RTTINC RTT_SR_RTTINC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTT_SR_RTTINC_Msk instead */ +#define RTT_SR_MASK _U_(0x03) /**< \deprecated (RTT_SR) Register MASK (Use RTT_SR_Msk instead) */ +#define RTT_SR_Msk _U_(0x03) /**< (RTT_SR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief RTT hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< (RTT Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< (RTT Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< (RTT Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< (RTT Offset: 0x0C) Status Register */ +} Rtt; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief RTT hardware registers */ +typedef struct { + __IO RTT_MR_Type RTT_MR; /**< Offset: 0x00 (R/W 32) Mode Register */ + __IO RTT_AR_Type RTT_AR; /**< Offset: 0x04 (R/W 32) Alarm Register */ + __I RTT_VR_Type RTT_VR; /**< Offset: 0x08 (R/ 32) Value Register */ + __I RTT_SR_Type RTT_SR; /**< Offset: 0x0C (R/ 32) Status Register */ +} Rtt; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Real-time Timer */ + +#endif /* _SAME70_RTT_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/sdramc.h b/bsp/microchip/same70/bsp/same70b/include/component/sdramc.h new file mode 100644 index 0000000000..98e24ceafd --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/sdramc.h @@ -0,0 +1,500 @@ +/** + * \file + * + * \brief Component description for SDRAMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SDRAMC_COMPONENT_H_ +#define _SAME70_SDRAMC_COMPONENT_H_ +#define _SAME70_SDRAMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 SDRAM Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SDRAMC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define SDRAMC_6100 /**< (SDRAMC) Module ID */ +#define REV_SDRAMC U /**< (SDRAMC) Module revision */ + +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) (R/W 32) SDRAMC Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MODE:3; /**< bit: 0..2 SDRAMC Command Mode */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_MR_OFFSET (0x00) /**< (SDRAMC_MR) SDRAMC Mode Register Offset */ + +#define SDRAMC_MR_MODE_Pos 0 /**< (SDRAMC_MR) SDRAMC Command Mode Position */ +#define SDRAMC_MR_MODE_Msk (_U_(0x7) << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) SDRAMC Command Mode Mask */ +#define SDRAMC_MR_MODE(value) (SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)) +#define SDRAMC_MR_MODE_NORMAL_Val _U_(0x0) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP_Val _U_(0x1) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val _U_(0x2) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG_Val _U_(0x3) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH_Val _U_(0x4) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val _U_(0x5) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN_Val _U_(0x6) /**< (SDRAMC_MR) Deep Power-down mode. Enters Deep Power-down mode. */ +#define SDRAMC_MR_MODE_NORMAL (SDRAMC_MR_MODE_NORMAL_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_NOP (SDRAMC_MR_MODE_NOP_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (SDRAMC_MR_MODE_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (SDRAMC_MR_MODE_AUTO_REFRESH_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. Position */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (SDRAMC_MR_MODE_DEEP_POWERDOWN_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Deep Power-down mode. Enters Deep Power-down mode. Position */ +#define SDRAMC_MR_MASK _U_(0x07) /**< \deprecated (SDRAMC_MR) Register MASK (Use SDRAMC_MR_Msk instead) */ +#define SDRAMC_MR_Msk _U_(0x07) /**< (SDRAMC_MR) Register Mask */ + + +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) (R/W 32) SDRAMC Refresh Timer Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COUNT:12; /**< bit: 0..11 SDRAMC Refresh Timer Count */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_TR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_TR_OFFSET (0x04) /**< (SDRAMC_TR) SDRAMC Refresh Timer Register Offset */ + +#define SDRAMC_TR_COUNT_Pos 0 /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Position */ +#define SDRAMC_TR_COUNT_Msk (_U_(0xFFF) << SDRAMC_TR_COUNT_Pos) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Mask */ +#define SDRAMC_TR_COUNT(value) (SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)) +#define SDRAMC_TR_MASK _U_(0xFFF) /**< \deprecated (SDRAMC_TR) Register MASK (Use SDRAMC_TR_Msk instead) */ +#define SDRAMC_TR_Msk _U_(0xFFF) /**< (SDRAMC_TR) Register Mask */ + + +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) (R/W 32) SDRAMC Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NC:2; /**< bit: 0..1 Number of Column Bits */ + uint32_t NR:2; /**< bit: 2..3 Number of Row Bits */ + uint32_t NB:1; /**< bit: 4 Number of Banks */ + uint32_t CAS:2; /**< bit: 5..6 CAS Latency */ + uint32_t DBW:1; /**< bit: 7 Data Bus Width */ + uint32_t TWR:4; /**< bit: 8..11 Write Recovery Delay */ + uint32_t TRC_TRFC:4; /**< bit: 12..15 Row Cycle Delay and Row Refresh Cycle */ + uint32_t TRP:4; /**< bit: 16..19 Row Precharge Delay */ + uint32_t TRCD:4; /**< bit: 20..23 Row to Column Delay */ + uint32_t TRAS:4; /**< bit: 24..27 Active to Precharge Delay */ + uint32_t TXSR:4; /**< bit: 28..31 Exit Self-Refresh to Active Delay */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_CR_OFFSET (0x08) /**< (SDRAMC_CR) SDRAMC Configuration Register Offset */ + +#define SDRAMC_CR_NC_Pos 0 /**< (SDRAMC_CR) Number of Column Bits Position */ +#define SDRAMC_CR_NC_Msk (_U_(0x3) << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) Number of Column Bits Mask */ +#define SDRAMC_CR_NC(value) (SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)) +#define SDRAMC_CR_NC_COL8_Val _U_(0x0) /**< (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9_Val _U_(0x1) /**< (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10_Val _U_(0x2) /**< (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11_Val _U_(0x3) /**< (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NC_COL8 (SDRAMC_CR_NC_COL8_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 8 column bits Position */ +#define SDRAMC_CR_NC_COL9 (SDRAMC_CR_NC_COL9_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 9 column bits Position */ +#define SDRAMC_CR_NC_COL10 (SDRAMC_CR_NC_COL10_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 10 column bits Position */ +#define SDRAMC_CR_NC_COL11 (SDRAMC_CR_NC_COL11_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 11 column bits Position */ +#define SDRAMC_CR_NR_Pos 2 /**< (SDRAMC_CR) Number of Row Bits Position */ +#define SDRAMC_CR_NR_Msk (_U_(0x3) << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) Number of Row Bits Mask */ +#define SDRAMC_CR_NR(value) (SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)) +#define SDRAMC_CR_NR_ROW11_Val _U_(0x0) /**< (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12_Val _U_(0x1) /**< (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13_Val _U_(0x2) /**< (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NR_ROW11 (SDRAMC_CR_NR_ROW11_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 11 row bits Position */ +#define SDRAMC_CR_NR_ROW12 (SDRAMC_CR_NR_ROW12_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 12 row bits Position */ +#define SDRAMC_CR_NR_ROW13 (SDRAMC_CR_NR_ROW13_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 13 row bits Position */ +#define SDRAMC_CR_NB_Pos 4 /**< (SDRAMC_CR) Number of Banks Position */ +#define SDRAMC_CR_NB_Msk (_U_(0x1) << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) Number of Banks Mask */ +#define SDRAMC_CR_NB SDRAMC_CR_NB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CR_NB_Msk instead */ +#define SDRAMC_CR_NB_BANK2_Val _U_(0x0) /**< (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4_Val _U_(0x1) /**< (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_NB_BANK2 (SDRAMC_CR_NB_BANK2_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 2 banks Position */ +#define SDRAMC_CR_NB_BANK4 (SDRAMC_CR_NB_BANK4_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 4 banks Position */ +#define SDRAMC_CR_CAS_Pos 5 /**< (SDRAMC_CR) CAS Latency Position */ +#define SDRAMC_CR_CAS_Msk (_U_(0x3) << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) CAS Latency Mask */ +#define SDRAMC_CR_CAS(value) (SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)) +#define SDRAMC_CR_CAS_LATENCY1_Val _U_(0x1) /**< (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2_Val _U_(0x2) /**< (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3_Val _U_(0x3) /**< (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY1 (SDRAMC_CR_CAS_LATENCY1_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 1 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY2 (SDRAMC_CR_CAS_LATENCY2_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 2 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY3 (SDRAMC_CR_CAS_LATENCY3_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 3 cycle CAS latency Position */ +#define SDRAMC_CR_DBW_Pos 7 /**< (SDRAMC_CR) Data Bus Width Position */ +#define SDRAMC_CR_DBW_Msk (_U_(0x1) << SDRAMC_CR_DBW_Pos) /**< (SDRAMC_CR) Data Bus Width Mask */ +#define SDRAMC_CR_DBW SDRAMC_CR_DBW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CR_DBW_Msk instead */ +#define SDRAMC_CR_TWR_Pos 8 /**< (SDRAMC_CR) Write Recovery Delay Position */ +#define SDRAMC_CR_TWR_Msk (_U_(0xF) << SDRAMC_CR_TWR_Pos) /**< (SDRAMC_CR) Write Recovery Delay Mask */ +#define SDRAMC_CR_TWR(value) (SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)) +#define SDRAMC_CR_TRC_TRFC_Pos 12 /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Position */ +#define SDRAMC_CR_TRC_TRFC_Msk (_U_(0xF) << SDRAMC_CR_TRC_TRFC_Pos) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Mask */ +#define SDRAMC_CR_TRC_TRFC(value) (SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)) +#define SDRAMC_CR_TRP_Pos 16 /**< (SDRAMC_CR) Row Precharge Delay Position */ +#define SDRAMC_CR_TRP_Msk (_U_(0xF) << SDRAMC_CR_TRP_Pos) /**< (SDRAMC_CR) Row Precharge Delay Mask */ +#define SDRAMC_CR_TRP(value) (SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)) +#define SDRAMC_CR_TRCD_Pos 20 /**< (SDRAMC_CR) Row to Column Delay Position */ +#define SDRAMC_CR_TRCD_Msk (_U_(0xF) << SDRAMC_CR_TRCD_Pos) /**< (SDRAMC_CR) Row to Column Delay Mask */ +#define SDRAMC_CR_TRCD(value) (SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)) +#define SDRAMC_CR_TRAS_Pos 24 /**< (SDRAMC_CR) Active to Precharge Delay Position */ +#define SDRAMC_CR_TRAS_Msk (_U_(0xF) << SDRAMC_CR_TRAS_Pos) /**< (SDRAMC_CR) Active to Precharge Delay Mask */ +#define SDRAMC_CR_TRAS(value) (SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)) +#define SDRAMC_CR_TXSR_Pos 28 /**< (SDRAMC_CR) Exit Self-Refresh to Active Delay Position */ +#define SDRAMC_CR_TXSR_Msk (_U_(0xF) << SDRAMC_CR_TXSR_Pos) /**< (SDRAMC_CR) Exit Self-Refresh to Active Delay Mask */ +#define SDRAMC_CR_TXSR(value) (SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)) +#define SDRAMC_CR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_CR) Register MASK (Use SDRAMC_CR_Msk instead) */ +#define SDRAMC_CR_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_CR) Register Mask */ + + +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) (R/W 32) SDRAMC Low Power Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LPCB:2; /**< bit: 0..1 Low-power Configuration Bits */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t PASR:3; /**< bit: 4..6 Partial Array Self-refresh (only for low-power SDRAM) */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t TCSR:2; /**< bit: 8..9 Temperature Compensated Self-Refresh (only for low-power SDRAM) */ + uint32_t DS:2; /**< bit: 10..11 Drive Strength (only for low-power SDRAM) */ + uint32_t TIMEOUT:2; /**< bit: 12..13 Time to Define When Low-power Mode Is Enabled */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_LPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_LPR_OFFSET (0x10) /**< (SDRAMC_LPR) SDRAMC Low Power Register Offset */ + +#define SDRAMC_LPR_LPCB_Pos 0 /**< (SDRAMC_LPR) Low-power Configuration Bits Position */ +#define SDRAMC_LPR_LPCB_Msk (_U_(0x3) << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low-power Configuration Bits Mask */ +#define SDRAMC_LPR_LPCB(value) (SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)) +#define SDRAMC_LPR_LPCB_DISABLED_Val _U_(0x0) /**< (SDRAMC_LPR) The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val _U_(0x3) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_LPCB_DISABLED (SDRAMC_LPR_LPCB_DISABLED_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. Position */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (SDRAMC_LPR_LPCB_SELF_REFRESH_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (SDRAMC_LPR_LPCB_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. Position */ +#define SDRAMC_LPR_PASR_Pos 4 /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_PASR_Msk (_U_(0x7) << SDRAMC_LPR_PASR_Pos) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_PASR(value) (SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)) +#define SDRAMC_LPR_TCSR_Pos 8 /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_TCSR_Msk (_U_(0x3) << SDRAMC_LPR_TCSR_Pos) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_TCSR(value) (SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)) +#define SDRAMC_LPR_DS_Pos 10 /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_DS_Msk (_U_(0x3) << SDRAMC_LPR_DS_Pos) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_DS(value) (SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)) +#define SDRAMC_LPR_TIMEOUT_Pos 12 /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Position */ +#define SDRAMC_LPR_TIMEOUT_Msk (_U_(0x3) << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Mask */ +#define SDRAMC_LPR_TIMEOUT(value) (SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val _U_(0x0) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_MASK _U_(0x3F73) /**< \deprecated (SDRAMC_LPR) Register MASK (Use SDRAMC_LPR_Msk instead) */ +#define SDRAMC_LPR_Msk _U_(0x3F73) /**< (SDRAMC_LPR) Register Mask */ + + +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) (/W 32) SDRAMC Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RES:1; /**< bit: 0 Refresh Error Interrupt Enable */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_IER_OFFSET (0x14) /**< (SDRAMC_IER) SDRAMC Interrupt Enable Register Offset */ + +#define SDRAMC_IER_RES_Pos 0 /**< (SDRAMC_IER) Refresh Error Interrupt Enable Position */ +#define SDRAMC_IER_RES_Msk (_U_(0x1) << SDRAMC_IER_RES_Pos) /**< (SDRAMC_IER) Refresh Error Interrupt Enable Mask */ +#define SDRAMC_IER_RES SDRAMC_IER_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IER_RES_Msk instead */ +#define SDRAMC_IER_MASK _U_(0x01) /**< \deprecated (SDRAMC_IER) Register MASK (Use SDRAMC_IER_Msk instead) */ +#define SDRAMC_IER_Msk _U_(0x01) /**< (SDRAMC_IER) Register Mask */ + + +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) (/W 32) SDRAMC Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RES:1; /**< bit: 0 Refresh Error Interrupt Disable */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_IDR_OFFSET (0x18) /**< (SDRAMC_IDR) SDRAMC Interrupt Disable Register Offset */ + +#define SDRAMC_IDR_RES_Pos 0 /**< (SDRAMC_IDR) Refresh Error Interrupt Disable Position */ +#define SDRAMC_IDR_RES_Msk (_U_(0x1) << SDRAMC_IDR_RES_Pos) /**< (SDRAMC_IDR) Refresh Error Interrupt Disable Mask */ +#define SDRAMC_IDR_RES SDRAMC_IDR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IDR_RES_Msk instead */ +#define SDRAMC_IDR_MASK _U_(0x01) /**< \deprecated (SDRAMC_IDR) Register MASK (Use SDRAMC_IDR_Msk instead) */ +#define SDRAMC_IDR_Msk _U_(0x01) /**< (SDRAMC_IDR) Register Mask */ + + +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) (R/ 32) SDRAMC Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RES:1; /**< bit: 0 Refresh Error Interrupt Mask */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_IMR_OFFSET (0x1C) /**< (SDRAMC_IMR) SDRAMC Interrupt Mask Register Offset */ + +#define SDRAMC_IMR_RES_Pos 0 /**< (SDRAMC_IMR) Refresh Error Interrupt Mask Position */ +#define SDRAMC_IMR_RES_Msk (_U_(0x1) << SDRAMC_IMR_RES_Pos) /**< (SDRAMC_IMR) Refresh Error Interrupt Mask Mask */ +#define SDRAMC_IMR_RES SDRAMC_IMR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_IMR_RES_Msk instead */ +#define SDRAMC_IMR_MASK _U_(0x01) /**< \deprecated (SDRAMC_IMR) Register MASK (Use SDRAMC_IMR_Msk instead) */ +#define SDRAMC_IMR_Msk _U_(0x01) /**< (SDRAMC_IMR) Register Mask */ + + +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) (R/ 32) SDRAMC Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RES:1; /**< bit: 0 Refresh Error Status (cleared on read) */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_ISR_OFFSET (0x20) /**< (SDRAMC_ISR) SDRAMC Interrupt Status Register Offset */ + +#define SDRAMC_ISR_RES_Pos 0 /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Position */ +#define SDRAMC_ISR_RES_Msk (_U_(0x1) << SDRAMC_ISR_RES_Pos) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Mask */ +#define SDRAMC_ISR_RES SDRAMC_ISR_RES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_ISR_RES_Msk instead */ +#define SDRAMC_ISR_MASK _U_(0x01) /**< \deprecated (SDRAMC_ISR) Register MASK (Use SDRAMC_ISR_Msk instead) */ +#define SDRAMC_ISR_Msk _U_(0x01) /**< (SDRAMC_ISR) Register Mask */ + + +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) (R/W 32) SDRAMC Memory Device Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MD:2; /**< bit: 0..1 Memory Device Type */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_MDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_MDR_OFFSET (0x24) /**< (SDRAMC_MDR) SDRAMC Memory Device Register Offset */ + +#define SDRAMC_MDR_MD_Pos 0 /**< (SDRAMC_MDR) Memory Device Type Position */ +#define SDRAMC_MDR_MD_Msk (_U_(0x3) << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Memory Device Type Mask */ +#define SDRAMC_MDR_MD(value) (SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)) +#define SDRAMC_MDR_MD_SDRAM_Val _U_(0x0) /**< (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM_Val _U_(0x1) /**< (SDRAMC_MDR) Low-power SDRAM */ +#define SDRAMC_MDR_MD_SDRAM (SDRAMC_MDR_MD_SDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) SDRAM Position */ +#define SDRAMC_MDR_MD_LPSDRAM (SDRAMC_MDR_MD_LPSDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Low-power SDRAM Position */ +#define SDRAMC_MDR_MASK _U_(0x03) /**< \deprecated (SDRAMC_MDR) Register MASK (Use SDRAMC_MDR_Msk instead) */ +#define SDRAMC_MDR_Msk _U_(0x03) /**< (SDRAMC_MDR) Register Mask */ + + +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) (R/W 32) SDRAMC Configuration Register 1 -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TMRD:4; /**< bit: 0..3 Load Mode Register Command to Active or Refresh Command */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t UNAL:1; /**< bit: 8 Support Unaligned Access */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_CFR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_CFR1_OFFSET (0x28) /**< (SDRAMC_CFR1) SDRAMC Configuration Register 1 Offset */ + +#define SDRAMC_CFR1_TMRD_Pos 0 /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Position */ +#define SDRAMC_CFR1_TMRD_Msk (_U_(0xF) << SDRAMC_CFR1_TMRD_Pos) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Mask */ +#define SDRAMC_CFR1_TMRD(value) (SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)) +#define SDRAMC_CFR1_UNAL_Pos 8 /**< (SDRAMC_CFR1) Support Unaligned Access Position */ +#define SDRAMC_CFR1_UNAL_Msk (_U_(0x1) << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Support Unaligned Access Mask */ +#define SDRAMC_CFR1_UNAL SDRAMC_CFR1_UNAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_CFR1_UNAL_Msk instead */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED_Val _U_(0x0) /**< (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED_Val _U_(0x1) /**< (SDRAMC_CFR1) Unaligned access is supported. */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (SDRAMC_CFR1_UNAL_UNSUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is not supported. Position */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (SDRAMC_CFR1_UNAL_SUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is supported. Position */ +#define SDRAMC_CFR1_MASK _U_(0x10F) /**< \deprecated (SDRAMC_CFR1) Register MASK (Use SDRAMC_CFR1_Msk instead) */ +#define SDRAMC_CFR1_Msk _U_(0x10F) /**< (SDRAMC_CFR1) Register Mask */ + + +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2c) (R/W 32) SDRAMC OCMS Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SDR_SE:1; /**< bit: 0 SDRAM Memory Controller Scrambling Enable */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_OCMS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_OCMS_OFFSET (0x2C) /**< (SDRAMC_OCMS) SDRAMC OCMS Register Offset */ + +#define SDRAMC_OCMS_SDR_SE_Pos 0 /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Position */ +#define SDRAMC_OCMS_SDR_SE_Msk (_U_(0x1) << SDRAMC_OCMS_SDR_SE_Pos) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Mask */ +#define SDRAMC_OCMS_SDR_SE SDRAMC_OCMS_SDR_SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SDRAMC_OCMS_SDR_SE_Msk instead */ +#define SDRAMC_OCMS_MASK _U_(0x01) /**< \deprecated (SDRAMC_OCMS) Register MASK (Use SDRAMC_OCMS_Msk instead) */ +#define SDRAMC_OCMS_Msk _U_(0x01) /**< (SDRAMC_OCMS) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) (/W 32) SDRAMC OCMS KEY1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t KEY1:32; /**< bit: 0..31 Off-chip Memory Scrambling (OCMS) Key Part 1 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_OCMS_KEY1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_OCMS_KEY1_OFFSET (0x30) /**< (SDRAMC_OCMS_KEY1) SDRAMC OCMS KEY1 Register Offset */ + +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SDRAMC_OCMS_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SDRAMC_OCMS_KEY1_KEY1(value) (SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)) +#define SDRAMC_OCMS_KEY1_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_OCMS_KEY1) Register MASK (Use SDRAMC_OCMS_KEY1_Msk instead) */ +#define SDRAMC_OCMS_KEY1_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY1) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) (/W 32) SDRAMC OCMS KEY2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t KEY2:32; /**< bit: 0..31 Off-chip Memory Scrambling (OCMS) Key Part 2 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SDRAMC_OCMS_KEY2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDRAMC_OCMS_KEY2_OFFSET (0x34) /**< (SDRAMC_OCMS_KEY2) SDRAMC OCMS KEY2 Register Offset */ + +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SDRAMC_OCMS_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SDRAMC_OCMS_KEY2_KEY2(value) (SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)) +#define SDRAMC_OCMS_KEY2_MASK _U_(0xFFFFFFFF) /**< \deprecated (SDRAMC_OCMS_KEY2) Register MASK (Use SDRAMC_OCMS_KEY2_Msk instead) */ +#define SDRAMC_OCMS_KEY2_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY2) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief SDRAMC hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< (SDRAMC Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< (SDRAMC Offset: 0x08) SDRAMC Configuration Register */ + __I uint8_t Reserved1[4]; + __IO uint32_t SDRAMC_LPR; /**< (SDRAMC Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< (SDRAMC Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< (SDRAMC Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief SDRAMC hardware registers */ +typedef struct { + __IO SDRAMC_MR_Type SDRAMC_MR; /**< Offset: 0x00 (R/W 32) SDRAMC Mode Register */ + __IO SDRAMC_TR_Type SDRAMC_TR; /**< Offset: 0x04 (R/W 32) SDRAMC Refresh Timer Register */ + __IO SDRAMC_CR_Type SDRAMC_CR; /**< Offset: 0x08 (R/W 32) SDRAMC Configuration Register */ + __I uint8_t Reserved1[4]; + __IO SDRAMC_LPR_Type SDRAMC_LPR; /**< Offset: 0x10 (R/W 32) SDRAMC Low Power Register */ + __O SDRAMC_IER_Type SDRAMC_IER; /**< Offset: 0x14 ( /W 32) SDRAMC Interrupt Enable Register */ + __O SDRAMC_IDR_Type SDRAMC_IDR; /**< Offset: 0x18 ( /W 32) SDRAMC Interrupt Disable Register */ + __I SDRAMC_IMR_Type SDRAMC_IMR; /**< Offset: 0x1C (R/ 32) SDRAMC Interrupt Mask Register */ + __I SDRAMC_ISR_Type SDRAMC_ISR; /**< Offset: 0x20 (R/ 32) SDRAMC Interrupt Status Register */ + __IO SDRAMC_MDR_Type SDRAMC_MDR; /**< Offset: 0x24 (R/W 32) SDRAMC Memory Device Register */ + __IO SDRAMC_CFR1_Type SDRAMC_CFR1; /**< Offset: 0x28 (R/W 32) SDRAMC Configuration Register 1 */ + __IO SDRAMC_OCMS_Type SDRAMC_OCMS; /**< Offset: 0x2C (R/W 32) SDRAMC OCMS Register */ + __O SDRAMC_OCMS_KEY1_Type SDRAMC_OCMS_KEY1; /**< Offset: 0x30 ( /W 32) SDRAMC OCMS KEY1 Register */ + __O SDRAMC_OCMS_KEY2_Type SDRAMC_OCMS_KEY2; /**< Offset: 0x34 ( /W 32) SDRAMC OCMS KEY2 Register */ +} Sdramc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of SDRAM Controller */ + +#endif /* _SAME70_SDRAMC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/smc.h b/bsp/microchip/same70/bsp/same70b/include/component/smc.h new file mode 100644 index 0000000000..fff04aa07e --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/smc.h @@ -0,0 +1,418 @@ +/** + * \file + * + * \brief Component description for SMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SMC_COMPONENT_H_ +#define _SAME70_SMC_COMPONENT_H_ +#define _SAME70_SMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Static Memory Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SMC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define SMC_6498 /**< (SMC) Module ID */ +#define REV_SMC J /**< (SMC) Module revision */ + +/* -------- SMC_SETUP : (SMC Offset: 0x00) (R/W 32) SMC Setup Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NWE_SETUP:6; /**< bit: 0..5 NWE Setup Length */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t NCS_WR_SETUP:6; /**< bit: 8..13 NCS Setup Length in WRITE Access */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t NRD_SETUP:6; /**< bit: 16..21 NRD Setup Length */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t NCS_RD_SETUP:6; /**< bit: 24..29 NCS Setup Length in READ Access */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_SETUP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_SETUP_OFFSET (0x00) /**< (SMC_SETUP) SMC Setup Register Offset */ + +#define SMC_SETUP_NWE_SETUP_Pos 0 /**< (SMC_SETUP) NWE Setup Length Position */ +#define SMC_SETUP_NWE_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NWE_SETUP_Pos) /**< (SMC_SETUP) NWE Setup Length Mask */ +#define SMC_SETUP_NWE_SETUP(value) (SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 /**< (SMC_SETUP) NCS Setup Length in WRITE Access Position */ +#define SMC_SETUP_NCS_WR_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_WR_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Mask */ +#define SMC_SETUP_NCS_WR_SETUP(value) (SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)) +#define SMC_SETUP_NRD_SETUP_Pos 16 /**< (SMC_SETUP) NRD Setup Length Position */ +#define SMC_SETUP_NRD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NRD_SETUP_Pos) /**< (SMC_SETUP) NRD Setup Length Mask */ +#define SMC_SETUP_NRD_SETUP(value) (SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 /**< (SMC_SETUP) NCS Setup Length in READ Access Position */ +#define SMC_SETUP_NCS_RD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_RD_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in READ Access Mask */ +#define SMC_SETUP_NCS_RD_SETUP(value) (SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)) +#define SMC_SETUP_MASK _U_(0x3F3F3F3F) /**< \deprecated (SMC_SETUP) Register MASK (Use SMC_SETUP_Msk instead) */ +#define SMC_SETUP_Msk _U_(0x3F3F3F3F) /**< (SMC_SETUP) Register Mask */ + + +/* -------- SMC_PULSE : (SMC Offset: 0x04) (R/W 32) SMC Pulse Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NWE_PULSE:7; /**< bit: 0..6 NWE Pulse Length */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t NCS_WR_PULSE:7; /**< bit: 8..14 NCS Pulse Length in WRITE Access */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t NRD_PULSE:7; /**< bit: 16..22 NRD Pulse Length */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t NCS_RD_PULSE:7; /**< bit: 24..30 NCS Pulse Length in READ Access */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_PULSE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_PULSE_OFFSET (0x04) /**< (SMC_PULSE) SMC Pulse Register Offset */ + +#define SMC_PULSE_NWE_PULSE_Pos 0 /**< (SMC_PULSE) NWE Pulse Length Position */ +#define SMC_PULSE_NWE_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NWE_PULSE_Pos) /**< (SMC_PULSE) NWE Pulse Length Mask */ +#define SMC_PULSE_NWE_PULSE(value) (SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Position */ +#define SMC_PULSE_NCS_WR_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_WR_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Mask */ +#define SMC_PULSE_NCS_WR_PULSE(value) (SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)) +#define SMC_PULSE_NRD_PULSE_Pos 16 /**< (SMC_PULSE) NRD Pulse Length Position */ +#define SMC_PULSE_NRD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NRD_PULSE_Pos) /**< (SMC_PULSE) NRD Pulse Length Mask */ +#define SMC_PULSE_NRD_PULSE(value) (SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 /**< (SMC_PULSE) NCS Pulse Length in READ Access Position */ +#define SMC_PULSE_NCS_RD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_RD_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in READ Access Mask */ +#define SMC_PULSE_NCS_RD_PULSE(value) (SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)) +#define SMC_PULSE_MASK _U_(0x7F7F7F7F) /**< \deprecated (SMC_PULSE) Register MASK (Use SMC_PULSE_Msk instead) */ +#define SMC_PULSE_Msk _U_(0x7F7F7F7F) /**< (SMC_PULSE) Register Mask */ + + +/* -------- SMC_CYCLE : (SMC Offset: 0x08) (R/W 32) SMC Cycle Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NWE_CYCLE:9; /**< bit: 0..8 Total Write Cycle Length */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t NRD_CYCLE:9; /**< bit: 16..24 Total Read Cycle Length */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_CYCLE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_CYCLE_OFFSET (0x08) /**< (SMC_CYCLE) SMC Cycle Register Offset */ + +#define SMC_CYCLE_NWE_CYCLE_Pos 0 /**< (SMC_CYCLE) Total Write Cycle Length Position */ +#define SMC_CYCLE_NWE_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NWE_CYCLE_Pos) /**< (SMC_CYCLE) Total Write Cycle Length Mask */ +#define SMC_CYCLE_NWE_CYCLE(value) (SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 /**< (SMC_CYCLE) Total Read Cycle Length Position */ +#define SMC_CYCLE_NRD_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NRD_CYCLE_Pos) /**< (SMC_CYCLE) Total Read Cycle Length Mask */ +#define SMC_CYCLE_NRD_CYCLE(value) (SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)) +#define SMC_CYCLE_MASK _U_(0x1FF01FF) /**< \deprecated (SMC_CYCLE) Register MASK (Use SMC_CYCLE_Msk instead) */ +#define SMC_CYCLE_Msk _U_(0x1FF01FF) /**< (SMC_CYCLE) Register Mask */ + + +/* -------- SMC_MODE : (SMC Offset: 0x0c) (R/W 32) SMC Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t READ_MODE:1; /**< bit: 0 Read Mode */ + uint32_t WRITE_MODE:1; /**< bit: 1 Write Mode */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t EXNW_MODE:2; /**< bit: 4..5 NWAIT Mode */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t BAT:1; /**< bit: 8 Byte Access Type */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t DBW:1; /**< bit: 12 Data Bus Width */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t TDF_CYCLES:4; /**< bit: 16..19 Data Float Time */ + uint32_t TDF_MODE:1; /**< bit: 20 TDF Optimization */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t PMEN:1; /**< bit: 24 Page Mode Enabled */ + uint32_t :3; /**< bit: 25..27 Reserved */ + uint32_t PS:2; /**< bit: 28..29 Page Size */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_MODE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_MODE_OFFSET (0x0C) /**< (SMC_MODE) SMC Mode Register Offset */ + +#define SMC_MODE_READ_MODE_Pos 0 /**< (SMC_MODE) Read Mode Position */ +#define SMC_MODE_READ_MODE_Msk (_U_(0x1) << SMC_MODE_READ_MODE_Pos) /**< (SMC_MODE) Read Mode Mask */ +#define SMC_MODE_READ_MODE SMC_MODE_READ_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_READ_MODE_Msk instead */ +#define SMC_MODE_WRITE_MODE_Pos 1 /**< (SMC_MODE) Write Mode Position */ +#define SMC_MODE_WRITE_MODE_Msk (_U_(0x1) << SMC_MODE_WRITE_MODE_Pos) /**< (SMC_MODE) Write Mode Mask */ +#define SMC_MODE_WRITE_MODE SMC_MODE_WRITE_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_WRITE_MODE_Msk instead */ +#define SMC_MODE_EXNW_MODE_Pos 4 /**< (SMC_MODE) NWAIT Mode Position */ +#define SMC_MODE_EXNW_MODE_Msk (_U_(0x3) << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) NWAIT Mode Mask */ +#define SMC_MODE_EXNW_MODE(value) (SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)) +#define SMC_MODE_EXNW_MODE_DISABLED_Val _U_(0x0) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. */ +#define SMC_MODE_EXNW_MODE_FROZEN_Val _U_(0x2) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */ +#define SMC_MODE_EXNW_MODE_READY_Val _U_(0x3) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */ +#define SMC_MODE_EXNW_MODE_DISABLED (SMC_MODE_EXNW_MODE_DISABLED_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. Position */ +#define SMC_MODE_EXNW_MODE_FROZEN (SMC_MODE_EXNW_MODE_FROZEN_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. Position */ +#define SMC_MODE_EXNW_MODE_READY (SMC_MODE_EXNW_MODE_READY_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. Position */ +#define SMC_MODE_BAT_Pos 8 /**< (SMC_MODE) Byte Access Type Position */ +#define SMC_MODE_BAT_Msk (_U_(0x1) << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte Access Type Mask */ +#define SMC_MODE_BAT SMC_MODE_BAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_BAT_Msk instead */ +#define SMC_MODE_BAT_BYTE_SELECT_Val _U_(0x0) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE_Val _U_(0x1) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_BAT_BYTE_SELECT (SMC_MODE_BAT_BYTE_SELECT_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. Position */ +#define SMC_MODE_BAT_BYTE_WRITE (SMC_MODE_BAT_BYTE_WRITE_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. Position */ +#define SMC_MODE_DBW_Pos 12 /**< (SMC_MODE) Data Bus Width Position */ +#define SMC_MODE_DBW_Msk (_U_(0x1) << SMC_MODE_DBW_Pos) /**< (SMC_MODE) Data Bus Width Mask */ +#define SMC_MODE_DBW SMC_MODE_DBW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_DBW_Msk instead */ +#define SMC_MODE_DBW_8_BIT_Val _U_(0x0) /**< (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT_Val _U_(0x1) /**< (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_DBW_8_BIT (SMC_MODE_DBW_8_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 8-bit Data Bus Position */ +#define SMC_MODE_DBW_16_BIT (SMC_MODE_DBW_16_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 16-bit Data Bus Position */ +#define SMC_MODE_TDF_CYCLES_Pos 16 /**< (SMC_MODE) Data Float Time Position */ +#define SMC_MODE_TDF_CYCLES_Msk (_U_(0xF) << SMC_MODE_TDF_CYCLES_Pos) /**< (SMC_MODE) Data Float Time Mask */ +#define SMC_MODE_TDF_CYCLES(value) (SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)) +#define SMC_MODE_TDF_MODE_Pos 20 /**< (SMC_MODE) TDF Optimization Position */ +#define SMC_MODE_TDF_MODE_Msk (_U_(0x1) << SMC_MODE_TDF_MODE_Pos) /**< (SMC_MODE) TDF Optimization Mask */ +#define SMC_MODE_TDF_MODE SMC_MODE_TDF_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_TDF_MODE_Msk instead */ +#define SMC_MODE_PMEN_Pos 24 /**< (SMC_MODE) Page Mode Enabled Position */ +#define SMC_MODE_PMEN_Msk (_U_(0x1) << SMC_MODE_PMEN_Pos) /**< (SMC_MODE) Page Mode Enabled Mask */ +#define SMC_MODE_PMEN SMC_MODE_PMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_PMEN_Msk instead */ +#define SMC_MODE_PS_Pos 28 /**< (SMC_MODE) Page Size Position */ +#define SMC_MODE_PS_Msk (_U_(0x3) << SMC_MODE_PS_Pos) /**< (SMC_MODE) Page Size Mask */ +#define SMC_MODE_PS(value) (SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)) +#define SMC_MODE_PS_4_BYTE_Val _U_(0x0) /**< (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE_Val _U_(0x1) /**< (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE_Val _U_(0x2) /**< (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE_Val _U_(0x3) /**< (SMC_MODE) 32-byte page */ +#define SMC_MODE_PS_4_BYTE (SMC_MODE_PS_4_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 4-byte page Position */ +#define SMC_MODE_PS_8_BYTE (SMC_MODE_PS_8_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 8-byte page Position */ +#define SMC_MODE_PS_16_BYTE (SMC_MODE_PS_16_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 16-byte page Position */ +#define SMC_MODE_PS_32_BYTE (SMC_MODE_PS_32_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 32-byte page Position */ +#define SMC_MODE_MASK _U_(0x311F1133) /**< \deprecated (SMC_MODE) Register MASK (Use SMC_MODE_Msk instead) */ +#define SMC_MODE_Msk _U_(0x311F1133) /**< (SMC_MODE) Register Mask */ + + +/* -------- SMC_OCMS : (SMC Offset: 0x80) (R/W 32) SMC Off-Chip Memory Scrambling Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SMSE:1; /**< bit: 0 Static Memory Controller Scrambling Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t CS0SE:1; /**< bit: 8 Chip Select (x = 0 to 3) Scrambling Enable */ + uint32_t CS1SE:1; /**< bit: 9 Chip Select (x = 0 to 3) Scrambling Enable */ + uint32_t CS2SE:1; /**< bit: 10 Chip Select (x = 0 to 3) Scrambling Enable */ + uint32_t CS3SE:1; /**< bit: 11 Chip Select (x = 0 to 3) Scrambling Enable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_OCMS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_OCMS_OFFSET (0x80) /**< (SMC_OCMS) SMC Off-Chip Memory Scrambling Register Offset */ + +#define SMC_OCMS_SMSE_Pos 0 /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Position */ +#define SMC_OCMS_SMSE_Msk (_U_(0x1) << SMC_OCMS_SMSE_Pos) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Mask */ +#define SMC_OCMS_SMSE SMC_OCMS_SMSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_SMSE_Msk instead */ +#define SMC_OCMS_CS0SE_Pos 8 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS0SE_Msk (_U_(0x1) << SMC_OCMS_CS0SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS0SE SMC_OCMS_CS0SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS0SE_Msk instead */ +#define SMC_OCMS_CS1SE_Pos 9 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS1SE_Msk (_U_(0x1) << SMC_OCMS_CS1SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS1SE SMC_OCMS_CS1SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS1SE_Msk instead */ +#define SMC_OCMS_CS2SE_Pos 10 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS2SE_Msk (_U_(0x1) << SMC_OCMS_CS2SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS2SE SMC_OCMS_CS2SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS2SE_Msk instead */ +#define SMC_OCMS_CS3SE_Pos 11 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS3SE_Msk (_U_(0x1) << SMC_OCMS_CS3SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS3SE SMC_OCMS_CS3SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS3SE_Msk instead */ +#define SMC_OCMS_MASK _U_(0xF01) /**< \deprecated (SMC_OCMS) Register MASK (Use SMC_OCMS_Msk instead) */ +#define SMC_OCMS_Msk _U_(0xF01) /**< (SMC_OCMS) Register Mask */ + + +/* -------- SMC_KEY1 : (SMC Offset: 0x84) (/W 32) SMC Off-Chip Memory Scrambling KEY1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t KEY1:32; /**< bit: 0..31 Off-Chip Memory Scrambling (OCMS) Key Part 1 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_KEY1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_KEY1_OFFSET (0x84) /**< (SMC_KEY1) SMC Off-Chip Memory Scrambling KEY1 Register Offset */ + +#define SMC_KEY1_KEY1_Pos 0 /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SMC_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SMC_KEY1_KEY1_Pos) /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SMC_KEY1_KEY1(value) (SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)) +#define SMC_KEY1_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY1) Register MASK (Use SMC_KEY1_Msk instead) */ +#define SMC_KEY1_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY1) Register Mask */ + + +/* -------- SMC_KEY2 : (SMC Offset: 0x88) (/W 32) SMC Off-Chip Memory Scrambling KEY2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t KEY2:32; /**< bit: 0..31 Off-Chip Memory Scrambling (OCMS) Key Part 2 */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_KEY2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_KEY2_OFFSET (0x88) /**< (SMC_KEY2) SMC Off-Chip Memory Scrambling KEY2 Register Offset */ + +#define SMC_KEY2_KEY2_Pos 0 /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SMC_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SMC_KEY2_KEY2_Pos) /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SMC_KEY2_KEY2(value) (SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)) +#define SMC_KEY2_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY2) Register MASK (Use SMC_KEY2_Msk instead) */ +#define SMC_KEY2_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY2) Register Mask */ + + +/* -------- SMC_WPMR : (SMC Offset: 0xe4) (R/W 32) SMC Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protect Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_WPMR_OFFSET (0xE4) /**< (SMC_WPMR) SMC Write Protection Mode Register Offset */ + +#define SMC_WPMR_WPEN_Pos 0 /**< (SMC_WPMR) Write Protect Enable Position */ +#define SMC_WPMR_WPEN_Msk (_U_(0x1) << SMC_WPMR_WPEN_Pos) /**< (SMC_WPMR) Write Protect Enable Mask */ +#define SMC_WPMR_WPEN SMC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPMR_WPEN_Msk instead */ +#define SMC_WPMR_WPKEY_Pos 8 /**< (SMC_WPMR) Write Protection Key Position */ +#define SMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Write Protection Key Mask */ +#define SMC_WPMR_WPKEY(value) (SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)) +#define SMC_WPMR_WPKEY_PASSWD_Val _U_(0x534D43) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define SMC_WPMR_WPKEY_PASSWD (SMC_WPMR_WPKEY_PASSWD_Val << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define SMC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SMC_WPMR) Register MASK (Use SMC_WPMR_Msk instead) */ +#define SMC_WPMR_Msk _U_(0xFFFFFF01) /**< (SMC_WPMR) Register Mask */ + + +/* -------- SMC_WPSR : (SMC Offset: 0xe8) (R/ 32) SMC Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SMC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SMC_WPSR_OFFSET (0xE8) /**< (SMC_WPSR) SMC Write Protection Status Register Offset */ + +#define SMC_WPSR_WPVS_Pos 0 /**< (SMC_WPSR) Write Protection Violation Status Position */ +#define SMC_WPSR_WPVS_Msk (_U_(0x1) << SMC_WPSR_WPVS_Pos) /**< (SMC_WPSR) Write Protection Violation Status Mask */ +#define SMC_WPSR_WPVS SMC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPSR_WPVS_Msk instead */ +#define SMC_WPSR_WPVSRC_Pos 8 /**< (SMC_WPSR) Write Protection Violation Source Position */ +#define SMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SMC_WPSR_WPVSRC_Pos) /**< (SMC_WPSR) Write Protection Violation Source Mask */ +#define SMC_WPSR_WPVSRC(value) (SMC_WPSR_WPVSRC_Msk & ((value) << SMC_WPSR_WPVSRC_Pos)) +#define SMC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SMC_WPSR) Register MASK (Use SMC_WPSR_Msk instead) */ +#define SMC_WPSR_Msk _U_(0xFFFF01) /**< (SMC_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief SMC_CS_NUMBER hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< (SMC_CS_NUMBER Offset: 0x00) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register */ +} SmcCsNumber; + +#define SMCCSNUMBER_NUMBER 4 +/** \brief SMC hardware registers */ +typedef struct { + SmcCsNumber SmcCsNumber[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */ + __I uint8_t Reserved1[64]; + __IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */ + __O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */ + __O uint32_t SMC_KEY2; /**< (SMC Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register */ + __I uint8_t Reserved2[88]; + __IO uint32_t SMC_WPMR; /**< (SMC Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< (SMC Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief SMC_CS_NUMBER hardware registers */ +typedef struct { + __IO SMC_SETUP_Type SMC_SETUP; /**< Offset: 0x00 (R/W 32) SMC Setup Register */ + __IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register */ + __IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register */ + __IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register */ +} SmcCsNumber; + +/** \brief SMC hardware registers */ +typedef struct { + SmcCsNumber SmcCsNumber[4]; /**< Offset: 0x00 SMC Setup Register */ + __I uint8_t Reserved1[64]; + __IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */ + __O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */ + __O SMC_KEY2_Type SMC_KEY2; /**< Offset: 0x88 ( /W 32) SMC Off-Chip Memory Scrambling KEY2 Register */ + __I uint8_t Reserved2[88]; + __IO SMC_WPMR_Type SMC_WPMR; /**< Offset: 0xE4 (R/W 32) SMC Write Protection Mode Register */ + __I SMC_WPSR_Type SMC_WPSR; /**< Offset: 0xE8 (R/ 32) SMC Write Protection Status Register */ +} Smc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Static Memory Controller */ + +#endif /* _SAME70_SMC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/spi.h b/bsp/microchip/same70/bsp/same70b/include/component/spi.h new file mode 100644 index 0000000000..2344a1d8a7 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/spi.h @@ -0,0 +1,586 @@ +/** + * \file + * + * \brief Component description for SPI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SPI_COMPONENT_H_ +#define _SAME70_SPI_COMPONENT_H_ +#define _SAME70_SPI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Serial Peripheral Interface + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SPI */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define SPI_6088 /**< (SPI) Module ID */ +#define REV_SPI ZM /**< (SPI) Module revision */ + +/* -------- SPI_CR : (SPI Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SPIEN:1; /**< bit: 0 SPI Enable */ + uint32_t SPIDIS:1; /**< bit: 1 SPI Disable */ + uint32_t :5; /**< bit: 2..6 Reserved */ + uint32_t SWRST:1; /**< bit: 7 SPI Software Reset */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t REQCLR:1; /**< bit: 12 Request to Clear the Comparison Trigger */ + uint32_t :11; /**< bit: 13..23 Reserved */ + uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_CR_OFFSET (0x00) /**< (SPI_CR) Control Register Offset */ + +#define SPI_CR_SPIEN_Pos 0 /**< (SPI_CR) SPI Enable Position */ +#define SPI_CR_SPIEN_Msk (_U_(0x1) << SPI_CR_SPIEN_Pos) /**< (SPI_CR) SPI Enable Mask */ +#define SPI_CR_SPIEN SPI_CR_SPIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIEN_Msk instead */ +#define SPI_CR_SPIDIS_Pos 1 /**< (SPI_CR) SPI Disable Position */ +#define SPI_CR_SPIDIS_Msk (_U_(0x1) << SPI_CR_SPIDIS_Pos) /**< (SPI_CR) SPI Disable Mask */ +#define SPI_CR_SPIDIS SPI_CR_SPIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SPIDIS_Msk instead */ +#define SPI_CR_SWRST_Pos 7 /**< (SPI_CR) SPI Software Reset Position */ +#define SPI_CR_SWRST_Msk (_U_(0x1) << SPI_CR_SWRST_Pos) /**< (SPI_CR) SPI Software Reset Mask */ +#define SPI_CR_SWRST SPI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_SWRST_Msk instead */ +#define SPI_CR_REQCLR_Pos 12 /**< (SPI_CR) Request to Clear the Comparison Trigger Position */ +#define SPI_CR_REQCLR_Msk (_U_(0x1) << SPI_CR_REQCLR_Pos) /**< (SPI_CR) Request to Clear the Comparison Trigger Mask */ +#define SPI_CR_REQCLR SPI_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_REQCLR_Msk instead */ +#define SPI_CR_LASTXFER_Pos 24 /**< (SPI_CR) Last Transfer Position */ +#define SPI_CR_LASTXFER_Msk (_U_(0x1) << SPI_CR_LASTXFER_Pos) /**< (SPI_CR) Last Transfer Mask */ +#define SPI_CR_LASTXFER SPI_CR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CR_LASTXFER_Msk instead */ +#define SPI_CR_MASK _U_(0x1001083) /**< \deprecated (SPI_CR) Register MASK (Use SPI_CR_Msk instead) */ +#define SPI_CR_Msk _U_(0x1001083) /**< (SPI_CR) Register Mask */ + + +/* -------- SPI_MR : (SPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MSTR:1; /**< bit: 0 Master/Slave Mode */ + uint32_t PS:1; /**< bit: 1 Peripheral Select */ + uint32_t PCSDEC:1; /**< bit: 2 Chip Select Decode */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t MODFDIS:1; /**< bit: 4 Mode Fault Detection */ + uint32_t WDRBT:1; /**< bit: 5 Wait Data Read Before Transfer */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t LLB:1; /**< bit: 7 Local Loopback Enable */ + uint32_t :8; /**< bit: 8..15 Reserved */ + uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t DLYBCS:8; /**< bit: 24..31 Delay Between Chip Selects */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_MR_OFFSET (0x04) /**< (SPI_MR) Mode Register Offset */ + +#define SPI_MR_MSTR_Pos 0 /**< (SPI_MR) Master/Slave Mode Position */ +#define SPI_MR_MSTR_Msk (_U_(0x1) << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master/Slave Mode Mask */ +#define SPI_MR_MSTR SPI_MR_MSTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MSTR_Msk instead */ +#define SPI_MR_MSTR_MASTER_Val _U_(0x1) /**< (SPI_MR) Master */ +#define SPI_MR_MSTR_SLAVE_Val _U_(0x0) /**< (SPI_MR) Slave */ +#define SPI_MR_MSTR_MASTER (SPI_MR_MSTR_MASTER_Val << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master Position */ +#define SPI_MR_MSTR_SLAVE (SPI_MR_MSTR_SLAVE_Val << SPI_MR_MSTR_Pos) /**< (SPI_MR) Slave Position */ +#define SPI_MR_PS_Pos 1 /**< (SPI_MR) Peripheral Select Position */ +#define SPI_MR_PS_Msk (_U_(0x1) << SPI_MR_PS_Pos) /**< (SPI_MR) Peripheral Select Mask */ +#define SPI_MR_PS SPI_MR_PS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PS_Msk instead */ +#define SPI_MR_PCSDEC_Pos 2 /**< (SPI_MR) Chip Select Decode Position */ +#define SPI_MR_PCSDEC_Msk (_U_(0x1) << SPI_MR_PCSDEC_Pos) /**< (SPI_MR) Chip Select Decode Mask */ +#define SPI_MR_PCSDEC SPI_MR_PCSDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_PCSDEC_Msk instead */ +#define SPI_MR_MODFDIS_Pos 4 /**< (SPI_MR) Mode Fault Detection Position */ +#define SPI_MR_MODFDIS_Msk (_U_(0x1) << SPI_MR_MODFDIS_Pos) /**< (SPI_MR) Mode Fault Detection Mask */ +#define SPI_MR_MODFDIS SPI_MR_MODFDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_MODFDIS_Msk instead */ +#define SPI_MR_WDRBT_Pos 5 /**< (SPI_MR) Wait Data Read Before Transfer Position */ +#define SPI_MR_WDRBT_Msk (_U_(0x1) << SPI_MR_WDRBT_Pos) /**< (SPI_MR) Wait Data Read Before Transfer Mask */ +#define SPI_MR_WDRBT SPI_MR_WDRBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_WDRBT_Msk instead */ +#define SPI_MR_LLB_Pos 7 /**< (SPI_MR) Local Loopback Enable Position */ +#define SPI_MR_LLB_Msk (_U_(0x1) << SPI_MR_LLB_Pos) /**< (SPI_MR) Local Loopback Enable Mask */ +#define SPI_MR_LLB SPI_MR_LLB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_MR_LLB_Msk instead */ +#define SPI_MR_PCS_Pos 16 /**< (SPI_MR) Peripheral Chip Select Position */ +#define SPI_MR_PCS_Msk (_U_(0xF) << SPI_MR_PCS_Pos) /**< (SPI_MR) Peripheral Chip Select Mask */ +#define SPI_MR_PCS(value) (SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)) +#define SPI_MR_PCS_NPCS0_Val _U_(0xE) /**< (SPI_MR) NPCS0 as Chip Select */ +#define SPI_MR_PCS_NPCS1_Val _U_(0xD) /**< (SPI_MR) NPCS1 as Chip Select */ +#define SPI_MR_PCS_NPCS2_Val _U_(0xB) /**< (SPI_MR) NPCS2 as Chip Select */ +#define SPI_MR_PCS_NPCS3_Val _U_(0x7) /**< (SPI_MR) NPCS3 as Chip Select */ +#define SPI_MR_PCS_NPCS0 (SPI_MR_PCS_NPCS0_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS0 as Chip Select Position */ +#define SPI_MR_PCS_NPCS1 (SPI_MR_PCS_NPCS1_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS1 as Chip Select Position */ +#define SPI_MR_PCS_NPCS2 (SPI_MR_PCS_NPCS2_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS2 as Chip Select Position */ +#define SPI_MR_PCS_NPCS3 (SPI_MR_PCS_NPCS3_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS3 as Chip Select Position */ +#define SPI_MR_DLYBCS_Pos 24 /**< (SPI_MR) Delay Between Chip Selects Position */ +#define SPI_MR_DLYBCS_Msk (_U_(0xFF) << SPI_MR_DLYBCS_Pos) /**< (SPI_MR) Delay Between Chip Selects Mask */ +#define SPI_MR_DLYBCS(value) (SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)) +#define SPI_MR_MASK _U_(0xFF0F00B7) /**< \deprecated (SPI_MR) Register MASK (Use SPI_MR_Msk instead) */ +#define SPI_MR_Msk _U_(0xFF0F00B7) /**< (SPI_MR) Register Mask */ + + +/* -------- SPI_RDR : (SPI Offset: 0x08) (R/ 32) Receive Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RD:16; /**< bit: 0..15 Receive Data */ + uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_RDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_RDR_OFFSET (0x08) /**< (SPI_RDR) Receive Data Register Offset */ + +#define SPI_RDR_RD_Pos 0 /**< (SPI_RDR) Receive Data Position */ +#define SPI_RDR_RD_Msk (_U_(0xFFFF) << SPI_RDR_RD_Pos) /**< (SPI_RDR) Receive Data Mask */ +#define SPI_RDR_RD(value) (SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos)) +#define SPI_RDR_PCS_Pos 16 /**< (SPI_RDR) Peripheral Chip Select Position */ +#define SPI_RDR_PCS_Msk (_U_(0xF) << SPI_RDR_PCS_Pos) /**< (SPI_RDR) Peripheral Chip Select Mask */ +#define SPI_RDR_PCS(value) (SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos)) +#define SPI_RDR_MASK _U_(0xFFFFF) /**< \deprecated (SPI_RDR) Register MASK (Use SPI_RDR_Msk instead) */ +#define SPI_RDR_Msk _U_(0xFFFFF) /**< (SPI_RDR) Register Mask */ + + +/* -------- SPI_TDR : (SPI Offset: 0x0c) (/W 32) Transmit Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TD:16; /**< bit: 0..15 Transmit Data */ + uint32_t PCS:4; /**< bit: 16..19 Peripheral Chip Select */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t LASTXFER:1; /**< bit: 24 Last Transfer */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_TDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_TDR_OFFSET (0x0C) /**< (SPI_TDR) Transmit Data Register Offset */ + +#define SPI_TDR_TD_Pos 0 /**< (SPI_TDR) Transmit Data Position */ +#define SPI_TDR_TD_Msk (_U_(0xFFFF) << SPI_TDR_TD_Pos) /**< (SPI_TDR) Transmit Data Mask */ +#define SPI_TDR_TD(value) (SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)) +#define SPI_TDR_PCS_Pos 16 /**< (SPI_TDR) Peripheral Chip Select Position */ +#define SPI_TDR_PCS_Msk (_U_(0xF) << SPI_TDR_PCS_Pos) /**< (SPI_TDR) Peripheral Chip Select Mask */ +#define SPI_TDR_PCS(value) (SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)) +#define SPI_TDR_PCS_NPCS0_Val _U_(0xE) /**< (SPI_TDR) NPCS0 as Chip Select */ +#define SPI_TDR_PCS_NPCS1_Val _U_(0xD) /**< (SPI_TDR) NPCS1 as Chip Select */ +#define SPI_TDR_PCS_NPCS2_Val _U_(0xB) /**< (SPI_TDR) NPCS2 as Chip Select */ +#define SPI_TDR_PCS_NPCS3_Val _U_(0x7) /**< (SPI_TDR) NPCS3 as Chip Select */ +#define SPI_TDR_PCS_NPCS0 (SPI_TDR_PCS_NPCS0_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS0 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS1 (SPI_TDR_PCS_NPCS1_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS1 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS2 (SPI_TDR_PCS_NPCS2_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS2 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS3 (SPI_TDR_PCS_NPCS3_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS3 as Chip Select Position */ +#define SPI_TDR_LASTXFER_Pos 24 /**< (SPI_TDR) Last Transfer Position */ +#define SPI_TDR_LASTXFER_Msk (_U_(0x1) << SPI_TDR_LASTXFER_Pos) /**< (SPI_TDR) Last Transfer Mask */ +#define SPI_TDR_LASTXFER SPI_TDR_LASTXFER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_TDR_LASTXFER_Msk instead */ +#define SPI_TDR_MASK _U_(0x10FFFFF) /**< \deprecated (SPI_TDR) Register MASK (Use SPI_TDR_Msk instead) */ +#define SPI_TDR_Msk _U_(0x10FFFFF) /**< (SPI_TDR) Register Mask */ + + +/* -------- SPI_SR : (SPI Offset: 0x10) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full (cleared by reading SPI_RDR) */ + uint32_t TDRE:1; /**< bit: 1 Transmit Data Register Empty (cleared by writing SPI_TDR) */ + uint32_t MODF:1; /**< bit: 2 Mode Fault Error (cleared on read) */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Status (cleared on read) */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t NSSR:1; /**< bit: 8 NSS Rising (cleared on read) */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty (cleared by writing SPI_TDR) */ + uint32_t UNDES:1; /**< bit: 10 Underrun Error Status (Slave mode only) (cleared on read) */ + uint32_t :5; /**< bit: 11..15 Reserved */ + uint32_t SPIENS:1; /**< bit: 16 SPI Enable Status */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_SR_OFFSET (0x10) /**< (SPI_SR) Status Register Offset */ + +#define SPI_SR_RDRF_Pos 0 /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define SPI_SR_RDRF_Msk (_U_(0x1) << SPI_SR_RDRF_Pos) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define SPI_SR_RDRF SPI_SR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_RDRF_Msk instead */ +#define SPI_SR_TDRE_Pos 1 /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TDRE_Msk (_U_(0x1) << SPI_SR_TDRE_Pos) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TDRE SPI_SR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TDRE_Msk instead */ +#define SPI_SR_MODF_Pos 2 /**< (SPI_SR) Mode Fault Error (cleared on read) Position */ +#define SPI_SR_MODF_Msk (_U_(0x1) << SPI_SR_MODF_Pos) /**< (SPI_SR) Mode Fault Error (cleared on read) Mask */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_MODF_Msk instead */ +#define SPI_SR_OVRES_Pos 3 /**< (SPI_SR) Overrun Error Status (cleared on read) Position */ +#define SPI_SR_OVRES_Msk (_U_(0x1) << SPI_SR_OVRES_Pos) /**< (SPI_SR) Overrun Error Status (cleared on read) Mask */ +#define SPI_SR_OVRES SPI_SR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_OVRES_Msk instead */ +#define SPI_SR_NSSR_Pos 8 /**< (SPI_SR) NSS Rising (cleared on read) Position */ +#define SPI_SR_NSSR_Msk (_U_(0x1) << SPI_SR_NSSR_Pos) /**< (SPI_SR) NSS Rising (cleared on read) Mask */ +#define SPI_SR_NSSR SPI_SR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_NSSR_Msk instead */ +#define SPI_SR_TXEMPTY_Pos 9 /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TXEMPTY_Msk (_U_(0x1) << SPI_SR_TXEMPTY_Pos) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TXEMPTY SPI_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_TXEMPTY_Msk instead */ +#define SPI_SR_UNDES_Pos 10 /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Position */ +#define SPI_SR_UNDES_Msk (_U_(0x1) << SPI_SR_UNDES_Pos) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Mask */ +#define SPI_SR_UNDES SPI_SR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_UNDES_Msk instead */ +#define SPI_SR_SPIENS_Pos 16 /**< (SPI_SR) SPI Enable Status Position */ +#define SPI_SR_SPIENS_Msk (_U_(0x1) << SPI_SR_SPIENS_Pos) /**< (SPI_SR) SPI Enable Status Mask */ +#define SPI_SR_SPIENS SPI_SR_SPIENS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_SR_SPIENS_Msk instead */ +#define SPI_SR_MASK _U_(0x1070F) /**< \deprecated (SPI_SR) Register MASK (Use SPI_SR_Msk instead) */ +#define SPI_SR_Msk _U_(0x1070F) /**< (SPI_SR) Register Mask */ + + +/* -------- SPI_IER : (SPI Offset: 0x14) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Enable */ + uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Enable */ + uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Enable */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Enable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Enable */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Enable */ + uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Enable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_IER_OFFSET (0x14) /**< (SPI_IER) Interrupt Enable Register Offset */ + +#define SPI_IER_RDRF_Pos 0 /**< (SPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define SPI_IER_RDRF_Msk (_U_(0x1) << SPI_IER_RDRF_Pos) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define SPI_IER_RDRF SPI_IER_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_RDRF_Msk instead */ +#define SPI_IER_TDRE_Pos 1 /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Position */ +#define SPI_IER_TDRE_Msk (_U_(0x1) << SPI_IER_TDRE_Pos) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Mask */ +#define SPI_IER_TDRE SPI_IER_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TDRE_Msk instead */ +#define SPI_IER_MODF_Pos 2 /**< (SPI_IER) Mode Fault Error Interrupt Enable Position */ +#define SPI_IER_MODF_Msk (_U_(0x1) << SPI_IER_MODF_Pos) /**< (SPI_IER) Mode Fault Error Interrupt Enable Mask */ +#define SPI_IER_MODF SPI_IER_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_MODF_Msk instead */ +#define SPI_IER_OVRES_Pos 3 /**< (SPI_IER) Overrun Error Interrupt Enable Position */ +#define SPI_IER_OVRES_Msk (_U_(0x1) << SPI_IER_OVRES_Pos) /**< (SPI_IER) Overrun Error Interrupt Enable Mask */ +#define SPI_IER_OVRES SPI_IER_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_OVRES_Msk instead */ +#define SPI_IER_NSSR_Pos 8 /**< (SPI_IER) NSS Rising Interrupt Enable Position */ +#define SPI_IER_NSSR_Msk (_U_(0x1) << SPI_IER_NSSR_Pos) /**< (SPI_IER) NSS Rising Interrupt Enable Mask */ +#define SPI_IER_NSSR SPI_IER_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_NSSR_Msk instead */ +#define SPI_IER_TXEMPTY_Pos 9 /**< (SPI_IER) Transmission Registers Empty Enable Position */ +#define SPI_IER_TXEMPTY_Msk (_U_(0x1) << SPI_IER_TXEMPTY_Pos) /**< (SPI_IER) Transmission Registers Empty Enable Mask */ +#define SPI_IER_TXEMPTY SPI_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_TXEMPTY_Msk instead */ +#define SPI_IER_UNDES_Pos 10 /**< (SPI_IER) Underrun Error Interrupt Enable Position */ +#define SPI_IER_UNDES_Msk (_U_(0x1) << SPI_IER_UNDES_Pos) /**< (SPI_IER) Underrun Error Interrupt Enable Mask */ +#define SPI_IER_UNDES SPI_IER_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IER_UNDES_Msk instead */ +#define SPI_IER_MASK _U_(0x70F) /**< \deprecated (SPI_IER) Register MASK (Use SPI_IER_Msk instead) */ +#define SPI_IER_Msk _U_(0x70F) /**< (SPI_IER) Register Mask */ + + +/* -------- SPI_IDR : (SPI Offset: 0x18) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Disable */ + uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Disable */ + uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Disable */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Disable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Disable */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Disable */ + uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Disable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_IDR_OFFSET (0x18) /**< (SPI_IDR) Interrupt Disable Register Offset */ + +#define SPI_IDR_RDRF_Pos 0 /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define SPI_IDR_RDRF_Msk (_U_(0x1) << SPI_IDR_RDRF_Pos) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define SPI_IDR_RDRF SPI_IDR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_RDRF_Msk instead */ +#define SPI_IDR_TDRE_Pos 1 /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Position */ +#define SPI_IDR_TDRE_Msk (_U_(0x1) << SPI_IDR_TDRE_Pos) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Mask */ +#define SPI_IDR_TDRE SPI_IDR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TDRE_Msk instead */ +#define SPI_IDR_MODF_Pos 2 /**< (SPI_IDR) Mode Fault Error Interrupt Disable Position */ +#define SPI_IDR_MODF_Msk (_U_(0x1) << SPI_IDR_MODF_Pos) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Mask */ +#define SPI_IDR_MODF SPI_IDR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_MODF_Msk instead */ +#define SPI_IDR_OVRES_Pos 3 /**< (SPI_IDR) Overrun Error Interrupt Disable Position */ +#define SPI_IDR_OVRES_Msk (_U_(0x1) << SPI_IDR_OVRES_Pos) /**< (SPI_IDR) Overrun Error Interrupt Disable Mask */ +#define SPI_IDR_OVRES SPI_IDR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_OVRES_Msk instead */ +#define SPI_IDR_NSSR_Pos 8 /**< (SPI_IDR) NSS Rising Interrupt Disable Position */ +#define SPI_IDR_NSSR_Msk (_U_(0x1) << SPI_IDR_NSSR_Pos) /**< (SPI_IDR) NSS Rising Interrupt Disable Mask */ +#define SPI_IDR_NSSR SPI_IDR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_NSSR_Msk instead */ +#define SPI_IDR_TXEMPTY_Pos 9 /**< (SPI_IDR) Transmission Registers Empty Disable Position */ +#define SPI_IDR_TXEMPTY_Msk (_U_(0x1) << SPI_IDR_TXEMPTY_Pos) /**< (SPI_IDR) Transmission Registers Empty Disable Mask */ +#define SPI_IDR_TXEMPTY SPI_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_TXEMPTY_Msk instead */ +#define SPI_IDR_UNDES_Pos 10 /**< (SPI_IDR) Underrun Error Interrupt Disable Position */ +#define SPI_IDR_UNDES_Msk (_U_(0x1) << SPI_IDR_UNDES_Pos) /**< (SPI_IDR) Underrun Error Interrupt Disable Mask */ +#define SPI_IDR_UNDES SPI_IDR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IDR_UNDES_Msk instead */ +#define SPI_IDR_MASK _U_(0x70F) /**< \deprecated (SPI_IDR) Register MASK (Use SPI_IDR_Msk instead) */ +#define SPI_IDR_Msk _U_(0x70F) /**< (SPI_IDR) Register Mask */ + + +/* -------- SPI_IMR : (SPI Offset: 0x1c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDRF:1; /**< bit: 0 Receive Data Register Full Interrupt Mask */ + uint32_t TDRE:1; /**< bit: 1 SPI Transmit Data Register Empty Interrupt Mask */ + uint32_t MODF:1; /**< bit: 2 Mode Fault Error Interrupt Mask */ + uint32_t OVRES:1; /**< bit: 3 Overrun Error Interrupt Mask */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t NSSR:1; /**< bit: 8 NSS Rising Interrupt Mask */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmission Registers Empty Mask */ + uint32_t UNDES:1; /**< bit: 10 Underrun Error Interrupt Mask */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_IMR_OFFSET (0x1C) /**< (SPI_IMR) Interrupt Mask Register Offset */ + +#define SPI_IMR_RDRF_Pos 0 /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define SPI_IMR_RDRF_Msk (_U_(0x1) << SPI_IMR_RDRF_Pos) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define SPI_IMR_RDRF SPI_IMR_RDRF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_RDRF_Msk instead */ +#define SPI_IMR_TDRE_Pos 1 /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Position */ +#define SPI_IMR_TDRE_Msk (_U_(0x1) << SPI_IMR_TDRE_Pos) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Mask */ +#define SPI_IMR_TDRE SPI_IMR_TDRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TDRE_Msk instead */ +#define SPI_IMR_MODF_Pos 2 /**< (SPI_IMR) Mode Fault Error Interrupt Mask Position */ +#define SPI_IMR_MODF_Msk (_U_(0x1) << SPI_IMR_MODF_Pos) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Mask */ +#define SPI_IMR_MODF SPI_IMR_MODF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_MODF_Msk instead */ +#define SPI_IMR_OVRES_Pos 3 /**< (SPI_IMR) Overrun Error Interrupt Mask Position */ +#define SPI_IMR_OVRES_Msk (_U_(0x1) << SPI_IMR_OVRES_Pos) /**< (SPI_IMR) Overrun Error Interrupt Mask Mask */ +#define SPI_IMR_OVRES SPI_IMR_OVRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_OVRES_Msk instead */ +#define SPI_IMR_NSSR_Pos 8 /**< (SPI_IMR) NSS Rising Interrupt Mask Position */ +#define SPI_IMR_NSSR_Msk (_U_(0x1) << SPI_IMR_NSSR_Pos) /**< (SPI_IMR) NSS Rising Interrupt Mask Mask */ +#define SPI_IMR_NSSR SPI_IMR_NSSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_NSSR_Msk instead */ +#define SPI_IMR_TXEMPTY_Pos 9 /**< (SPI_IMR) Transmission Registers Empty Mask Position */ +#define SPI_IMR_TXEMPTY_Msk (_U_(0x1) << SPI_IMR_TXEMPTY_Pos) /**< (SPI_IMR) Transmission Registers Empty Mask Mask */ +#define SPI_IMR_TXEMPTY SPI_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_TXEMPTY_Msk instead */ +#define SPI_IMR_UNDES_Pos 10 /**< (SPI_IMR) Underrun Error Interrupt Mask Position */ +#define SPI_IMR_UNDES_Msk (_U_(0x1) << SPI_IMR_UNDES_Pos) /**< (SPI_IMR) Underrun Error Interrupt Mask Mask */ +#define SPI_IMR_UNDES SPI_IMR_UNDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_IMR_UNDES_Msk instead */ +#define SPI_IMR_MASK _U_(0x70F) /**< \deprecated (SPI_IMR) Register MASK (Use SPI_IMR_Msk instead) */ +#define SPI_IMR_Msk _U_(0x70F) /**< (SPI_IMR) Register Mask */ + + +/* -------- SPI_CSR : (SPI Offset: 0x30) (R/W 32) Chip Select Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CPOL:1; /**< bit: 0 Clock Polarity */ + uint32_t NCPHA:1; /**< bit: 1 Clock Phase */ + uint32_t CSNAAT:1; /**< bit: 2 Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ + uint32_t CSAAT:1; /**< bit: 3 Chip Select Active After Transfer */ + uint32_t BITS:4; /**< bit: 4..7 Bits Per Transfer */ + uint32_t SCBR:8; /**< bit: 8..15 Serial Clock Bit Rate */ + uint32_t DLYBS:8; /**< bit: 16..23 Delay Before SPCK */ + uint32_t DLYBCT:8; /**< bit: 24..31 Delay Between Consecutive Transfers */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_CSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_CSR_OFFSET (0x30) /**< (SPI_CSR) Chip Select Register Offset */ + +#define SPI_CSR_CPOL_Pos 0 /**< (SPI_CSR) Clock Polarity Position */ +#define SPI_CSR_CPOL_Msk (_U_(0x1) << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock Polarity Mask */ +#define SPI_CSR_CPOL SPI_CSR_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CPOL_Msk instead */ +#define SPI_CSR_CPOL_IDLE_LOW_Val _U_(0x0) /**< (SPI_CSR) Clock is low when inactive (CPOL=0) */ +#define SPI_CSR_CPOL_IDLE_HIGH_Val _U_(0x1) /**< (SPI_CSR) Clock is high when inactive (CPOL=1) */ +#define SPI_CSR_CPOL_IDLE_LOW (SPI_CSR_CPOL_IDLE_LOW_Val << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock is low when inactive (CPOL=0) Position */ +#define SPI_CSR_CPOL_IDLE_HIGH (SPI_CSR_CPOL_IDLE_HIGH_Val << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock is high when inactive (CPOL=1) Position */ +#define SPI_CSR_NCPHA_Pos 1 /**< (SPI_CSR) Clock Phase Position */ +#define SPI_CSR_NCPHA_Msk (_U_(0x1) << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Clock Phase Mask */ +#define SPI_CSR_NCPHA SPI_CSR_NCPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_NCPHA_Msk instead */ +#define SPI_CSR_NCPHA_VALID_LEADING_EDGE_Val _U_(0x1) /**< (SPI_CSR) Data is valid on clock leading edge (CPHA=0) */ +#define SPI_CSR_NCPHA_VALID_TRAILING_EDGE_Val _U_(0x0) /**< (SPI_CSR) Data is valid on clock trailing edge (CPHA=1) */ +#define SPI_CSR_NCPHA_VALID_LEADING_EDGE (SPI_CSR_NCPHA_VALID_LEADING_EDGE_Val << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Data is valid on clock leading edge (CPHA=0) Position */ +#define SPI_CSR_NCPHA_VALID_TRAILING_EDGE (SPI_CSR_NCPHA_VALID_TRAILING_EDGE_Val << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Data is valid on clock trailing edge (CPHA=1) Position */ +#define SPI_CSR_CSNAAT_Pos 2 /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Position */ +#define SPI_CSR_CSNAAT_Msk (_U_(0x1) << SPI_CSR_CSNAAT_Pos) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Mask */ +#define SPI_CSR_CSNAAT SPI_CSR_CSNAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSNAAT_Msk instead */ +#define SPI_CSR_CSAAT_Pos 3 /**< (SPI_CSR) Chip Select Active After Transfer Position */ +#define SPI_CSR_CSAAT_Msk (_U_(0x1) << SPI_CSR_CSAAT_Pos) /**< (SPI_CSR) Chip Select Active After Transfer Mask */ +#define SPI_CSR_CSAAT SPI_CSR_CSAAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_CSR_CSAAT_Msk instead */ +#define SPI_CSR_BITS_Pos 4 /**< (SPI_CSR) Bits Per Transfer Position */ +#define SPI_CSR_BITS_Msk (_U_(0xF) << SPI_CSR_BITS_Pos) /**< (SPI_CSR) Bits Per Transfer Mask */ +#define SPI_CSR_BITS(value) (SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)) +#define SPI_CSR_BITS_8_BIT_Val _U_(0x0) /**< (SPI_CSR) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT_Val _U_(0x1) /**< (SPI_CSR) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT_Val _U_(0x2) /**< (SPI_CSR) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT_Val _U_(0x3) /**< (SPI_CSR) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT_Val _U_(0x4) /**< (SPI_CSR) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT_Val _U_(0x5) /**< (SPI_CSR) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT_Val _U_(0x6) /**< (SPI_CSR) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT_Val _U_(0x7) /**< (SPI_CSR) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT_Val _U_(0x8) /**< (SPI_CSR) 16 bits for transfer */ +#define SPI_CSR_BITS_8_BIT (SPI_CSR_BITS_8_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 8 bits for transfer Position */ +#define SPI_CSR_BITS_9_BIT (SPI_CSR_BITS_9_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 9 bits for transfer Position */ +#define SPI_CSR_BITS_10_BIT (SPI_CSR_BITS_10_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 10 bits for transfer Position */ +#define SPI_CSR_BITS_11_BIT (SPI_CSR_BITS_11_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 11 bits for transfer Position */ +#define SPI_CSR_BITS_12_BIT (SPI_CSR_BITS_12_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 12 bits for transfer Position */ +#define SPI_CSR_BITS_13_BIT (SPI_CSR_BITS_13_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 13 bits for transfer Position */ +#define SPI_CSR_BITS_14_BIT (SPI_CSR_BITS_14_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 14 bits for transfer Position */ +#define SPI_CSR_BITS_15_BIT (SPI_CSR_BITS_15_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 15 bits for transfer Position */ +#define SPI_CSR_BITS_16_BIT (SPI_CSR_BITS_16_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 16 bits for transfer Position */ +#define SPI_CSR_SCBR_Pos 8 /**< (SPI_CSR) Serial Clock Bit Rate Position */ +#define SPI_CSR_SCBR_Msk (_U_(0xFF) << SPI_CSR_SCBR_Pos) /**< (SPI_CSR) Serial Clock Bit Rate Mask */ +#define SPI_CSR_SCBR(value) (SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)) +#define SPI_CSR_DLYBS_Pos 16 /**< (SPI_CSR) Delay Before SPCK Position */ +#define SPI_CSR_DLYBS_Msk (_U_(0xFF) << SPI_CSR_DLYBS_Pos) /**< (SPI_CSR) Delay Before SPCK Mask */ +#define SPI_CSR_DLYBS(value) (SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)) +#define SPI_CSR_DLYBCT_Pos 24 /**< (SPI_CSR) Delay Between Consecutive Transfers Position */ +#define SPI_CSR_DLYBCT_Msk (_U_(0xFF) << SPI_CSR_DLYBCT_Pos) /**< (SPI_CSR) Delay Between Consecutive Transfers Mask */ +#define SPI_CSR_DLYBCT(value) (SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)) +#define SPI_CSR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SPI_CSR) Register MASK (Use SPI_CSR_Msk instead) */ +#define SPI_CSR_Msk _U_(0xFFFFFFFF) /**< (SPI_CSR) Register Mask */ + + +/* -------- SPI_WPMR : (SPI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_WPMR_OFFSET (0xE4) /**< (SPI_WPMR) Write Protection Mode Register Offset */ + +#define SPI_WPMR_WPEN_Pos 0 /**< (SPI_WPMR) Write Protection Enable Position */ +#define SPI_WPMR_WPEN_Msk (_U_(0x1) << SPI_WPMR_WPEN_Pos) /**< (SPI_WPMR) Write Protection Enable Mask */ +#define SPI_WPMR_WPEN SPI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPMR_WPEN_Msk instead */ +#define SPI_WPMR_WPKEY_Pos 8 /**< (SPI_WPMR) Write Protection Key Position */ +#define SPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Write Protection Key Mask */ +#define SPI_WPMR_WPKEY(value) (SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)) +#define SPI_WPMR_WPKEY_PASSWD_Val _U_(0x535049) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SPI_WPMR_WPKEY_PASSWD (SPI_WPMR_WPKEY_PASSWD_Val << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SPI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SPI_WPMR) Register MASK (Use SPI_WPMR_Msk instead) */ +#define SPI_WPMR_Msk _U_(0xFFFFFF01) /**< (SPI_WPMR) Register Mask */ + + +/* -------- SPI_WPSR : (SPI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:8; /**< bit: 8..15 Write Protection Violation Source */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SPI_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SPI_WPSR_OFFSET (0xE8) /**< (SPI_WPSR) Write Protection Status Register Offset */ + +#define SPI_WPSR_WPVS_Pos 0 /**< (SPI_WPSR) Write Protection Violation Status Position */ +#define SPI_WPSR_WPVS_Msk (_U_(0x1) << SPI_WPSR_WPVS_Pos) /**< (SPI_WPSR) Write Protection Violation Status Mask */ +#define SPI_WPSR_WPVS SPI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SPI_WPSR_WPVS_Msk instead */ +#define SPI_WPSR_WPVSRC_Pos 8 /**< (SPI_WPSR) Write Protection Violation Source Position */ +#define SPI_WPSR_WPVSRC_Msk (_U_(0xFF) << SPI_WPSR_WPVSRC_Pos) /**< (SPI_WPSR) Write Protection Violation Source Mask */ +#define SPI_WPSR_WPVSRC(value) (SPI_WPSR_WPVSRC_Msk & ((value) << SPI_WPSR_WPVSRC_Pos)) +#define SPI_WPSR_MASK _U_(0xFF01) /**< \deprecated (SPI_WPSR) Register MASK (Use SPI_WPSR_Msk instead) */ +#define SPI_WPSR_Msk _U_(0xFF01) /**< (SPI_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief SPI hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< (SPI Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< (SPI Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< (SPI Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< (SPI Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< (SPI Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< (SPI Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< (SPI Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< (SPI Offset: 0x1C) Interrupt Mask Register */ + __I uint8_t Reserved1[16]; + __IO uint32_t SPI_CSR[4]; /**< (SPI Offset: 0x30) Chip Select Register */ + __I uint8_t Reserved2[164]; + __IO uint32_t SPI_WPMR; /**< (SPI Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< (SPI Offset: 0xE8) Write Protection Status Register */ +} Spi; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief SPI hardware registers */ +typedef struct { + __O SPI_CR_Type SPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO SPI_MR_Type SPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I SPI_RDR_Type SPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O SPI_TDR_Type SPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I SPI_SR_Type SPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O SPI_IER_Type SPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O SPI_IDR_Type SPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I SPI_IMR_Type SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved1[16]; + __IO SPI_CSR_Type SPI_CSR[4]; /**< Offset: 0x30 (R/W 32) Chip Select Register */ + __I uint8_t Reserved2[164]; + __IO SPI_WPMR_Type SPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I SPI_WPSR_Type SPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Spi; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Serial Peripheral Interface */ + +#endif /* _SAME70_SPI_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/ssc.h b/bsp/microchip/same70/bsp/same70b/include/component/ssc.h new file mode 100644 index 0000000000..2856e21215 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/ssc.h @@ -0,0 +1,911 @@ +/** + * \file + * + * \brief Component description for SSC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SSC_COMPONENT_H_ +#define _SAME70_SSC_COMPONENT_H_ +#define _SAME70_SSC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Synchronous Serial Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SSC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define SSC_6078 /**< (SSC) Module ID */ +#define REV_SSC Q /**< (SSC) Module revision */ + +/* -------- SSC_CR : (SSC Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXEN:1; /**< bit: 0 Receive Enable */ + uint32_t RXDIS:1; /**< bit: 1 Receive Disable */ + uint32_t :6; /**< bit: 2..7 Reserved */ + uint32_t TXEN:1; /**< bit: 8 Transmit Enable */ + uint32_t TXDIS:1; /**< bit: 9 Transmit Disable */ + uint32_t :5; /**< bit: 10..14 Reserved */ + uint32_t SWRST:1; /**< bit: 15 Software Reset */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_CR_OFFSET (0x00) /**< (SSC_CR) Control Register Offset */ + +#define SSC_CR_RXEN_Pos 0 /**< (SSC_CR) Receive Enable Position */ +#define SSC_CR_RXEN_Msk (_U_(0x1) << SSC_CR_RXEN_Pos) /**< (SSC_CR) Receive Enable Mask */ +#define SSC_CR_RXEN SSC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXEN_Msk instead */ +#define SSC_CR_RXDIS_Pos 1 /**< (SSC_CR) Receive Disable Position */ +#define SSC_CR_RXDIS_Msk (_U_(0x1) << SSC_CR_RXDIS_Pos) /**< (SSC_CR) Receive Disable Mask */ +#define SSC_CR_RXDIS SSC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXDIS_Msk instead */ +#define SSC_CR_TXEN_Pos 8 /**< (SSC_CR) Transmit Enable Position */ +#define SSC_CR_TXEN_Msk (_U_(0x1) << SSC_CR_TXEN_Pos) /**< (SSC_CR) Transmit Enable Mask */ +#define SSC_CR_TXEN SSC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXEN_Msk instead */ +#define SSC_CR_TXDIS_Pos 9 /**< (SSC_CR) Transmit Disable Position */ +#define SSC_CR_TXDIS_Msk (_U_(0x1) << SSC_CR_TXDIS_Pos) /**< (SSC_CR) Transmit Disable Mask */ +#define SSC_CR_TXDIS SSC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXDIS_Msk instead */ +#define SSC_CR_SWRST_Pos 15 /**< (SSC_CR) Software Reset Position */ +#define SSC_CR_SWRST_Msk (_U_(0x1) << SSC_CR_SWRST_Pos) /**< (SSC_CR) Software Reset Mask */ +#define SSC_CR_SWRST SSC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_SWRST_Msk instead */ +#define SSC_CR_MASK _U_(0x8303) /**< \deprecated (SSC_CR) Register MASK (Use SSC_CR_Msk instead) */ +#define SSC_CR_Msk _U_(0x8303) /**< (SSC_CR) Register Mask */ + + +/* -------- SSC_CMR : (SSC Offset: 0x04) (R/W 32) Clock Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DIV:12; /**< bit: 0..11 Clock Divider */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_CMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_CMR_OFFSET (0x04) /**< (SSC_CMR) Clock Mode Register Offset */ + +#define SSC_CMR_DIV_Pos 0 /**< (SSC_CMR) Clock Divider Position */ +#define SSC_CMR_DIV_Msk (_U_(0xFFF) << SSC_CMR_DIV_Pos) /**< (SSC_CMR) Clock Divider Mask */ +#define SSC_CMR_DIV(value) (SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)) +#define SSC_CMR_MASK _U_(0xFFF) /**< \deprecated (SSC_CMR) Register MASK (Use SSC_CMR_Msk instead) */ +#define SSC_CMR_Msk _U_(0xFFF) /**< (SSC_CMR) Register Mask */ + + +/* -------- SSC_RCMR : (SSC Offset: 0x10) (R/W 32) Receive Clock Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CKS:2; /**< bit: 0..1 Receive Clock Selection */ + uint32_t CKO:3; /**< bit: 2..4 Receive Clock Output Mode Selection */ + uint32_t CKI:1; /**< bit: 5 Receive Clock Inversion */ + uint32_t CKG:2; /**< bit: 6..7 Receive Clock Gating Selection */ + uint32_t START:4; /**< bit: 8..11 Receive Start Selection */ + uint32_t STOP:1; /**< bit: 12 Receive Stop Selection */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t STTDLY:8; /**< bit: 16..23 Receive Start Delay */ + uint32_t PERIOD:8; /**< bit: 24..31 Receive Period Divider Selection */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RCMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RCMR_OFFSET (0x10) /**< (SSC_RCMR) Receive Clock Mode Register Offset */ + +#define SSC_RCMR_CKS_Pos 0 /**< (SSC_RCMR) Receive Clock Selection Position */ +#define SSC_RCMR_CKS_Msk (_U_(0x3) << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Receive Clock Selection Mask */ +#define SSC_RCMR_CKS(value) (SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)) +#define SSC_RCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK_Val _U_(0x1) /**< (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK_Val _U_(0x2) /**< (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKS_MCK (SSC_RCMR_CKS_MCK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Divided Clock Position */ +#define SSC_RCMR_CKS_TK (SSC_RCMR_CKS_TK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) TK Clock signal Position */ +#define SSC_RCMR_CKS_RK (SSC_RCMR_CKS_RK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) RK pin Position */ +#define SSC_RCMR_CKO_Pos 2 /**< (SSC_RCMR) Receive Clock Output Mode Selection Position */ +#define SSC_RCMR_CKO_Msk (_U_(0x7) << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock Output Mode Selection Mask */ +#define SSC_RCMR_CKO(value) (SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)) +#define SSC_RCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKO_NONE (SSC_RCMR_CKO_NONE_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) None, RK pin is an input Position */ +#define SSC_RCMR_CKO_CONTINUOUS (SSC_RCMR_CKO_CONTINUOUS_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output Position */ +#define SSC_RCMR_CKO_TRANSFER (SSC_RCMR_CKO_TRANSFER_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output Position */ +#define SSC_RCMR_CKI_Pos 5 /**< (SSC_RCMR) Receive Clock Inversion Position */ +#define SSC_RCMR_CKI_Msk (_U_(0x1) << SSC_RCMR_CKI_Pos) /**< (SSC_RCMR) Receive Clock Inversion Mask */ +#define SSC_RCMR_CKI SSC_RCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_CKI_Msk instead */ +#define SSC_RCMR_CKG_Pos 6 /**< (SSC_RCMR) Receive Clock Gating Selection Position */ +#define SSC_RCMR_CKG_Msk (_U_(0x3) << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock Gating Selection Mask */ +#define SSC_RCMR_CKG(value) (SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)) +#define SSC_RCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW_Val _U_(0x1) /**< (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_CKG_CONTINUOUS (SSC_RCMR_CKG_CONTINUOUS_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) None Position */ +#define SSC_RCMR_CKG_EN_RF_LOW (SSC_RCMR_CKG_EN_RF_LOW_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF Low Position */ +#define SSC_RCMR_CKG_EN_RF_HIGH (SSC_RCMR_CKG_EN_RF_HIGH_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF High Position */ +#define SSC_RCMR_START_Pos 8 /**< (SSC_RCMR) Receive Start Selection Position */ +#define SSC_RCMR_START_Msk (_U_(0xF) << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Receive Start Selection Mask */ +#define SSC_RCMR_START(value) (SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)) +#define SSC_RCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT_Val _U_(0x1) /**< (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW_Val _U_(0x2) /**< (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH_Val _U_(0x3) /**< (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING_Val _U_(0x4) /**< (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING_Val _U_(0x5) /**< (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL_Val _U_(0x6) /**< (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE_Val _U_(0x7) /**< (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0_Val _U_(0x8) /**< (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_START_CONTINUOUS (SSC_RCMR_START_CONTINUOUS_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Position */ +#define SSC_RCMR_START_TRANSMIT (SSC_RCMR_START_TRANSMIT_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Transmit start Position */ +#define SSC_RCMR_START_RF_LOW (SSC_RCMR_START_RF_LOW_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a low level on RF signal Position */ +#define SSC_RCMR_START_RF_HIGH (SSC_RCMR_START_RF_HIGH_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a high level on RF signal Position */ +#define SSC_RCMR_START_RF_FALLING (SSC_RCMR_START_RF_FALLING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a falling edge on RF signal Position */ +#define SSC_RCMR_START_RF_RISING (SSC_RCMR_START_RF_RISING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a rising edge on RF signal Position */ +#define SSC_RCMR_START_RF_LEVEL (SSC_RCMR_START_RF_LEVEL_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any level change on RF signal Position */ +#define SSC_RCMR_START_RF_EDGE (SSC_RCMR_START_RF_EDGE_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any edge on RF signal Position */ +#define SSC_RCMR_START_CMP_0 (SSC_RCMR_START_CMP_0_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Compare 0 Position */ +#define SSC_RCMR_STOP_Pos 12 /**< (SSC_RCMR) Receive Stop Selection Position */ +#define SSC_RCMR_STOP_Msk (_U_(0x1) << SSC_RCMR_STOP_Pos) /**< (SSC_RCMR) Receive Stop Selection Mask */ +#define SSC_RCMR_STOP SSC_RCMR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_STOP_Msk instead */ +#define SSC_RCMR_STTDLY_Pos 16 /**< (SSC_RCMR) Receive Start Delay Position */ +#define SSC_RCMR_STTDLY_Msk (_U_(0xFF) << SSC_RCMR_STTDLY_Pos) /**< (SSC_RCMR) Receive Start Delay Mask */ +#define SSC_RCMR_STTDLY(value) (SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)) +#define SSC_RCMR_PERIOD_Pos 24 /**< (SSC_RCMR) Receive Period Divider Selection Position */ +#define SSC_RCMR_PERIOD_Msk (_U_(0xFF) << SSC_RCMR_PERIOD_Pos) /**< (SSC_RCMR) Receive Period Divider Selection Mask */ +#define SSC_RCMR_PERIOD(value) (SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)) +#define SSC_RCMR_MASK _U_(0xFFFF1FFF) /**< \deprecated (SSC_RCMR) Register MASK (Use SSC_RCMR_Msk instead) */ +#define SSC_RCMR_Msk _U_(0xFFFF1FFF) /**< (SSC_RCMR) Register Mask */ + + +/* -------- SSC_RFMR : (SSC Offset: 0x14) (R/W 32) Receive Frame Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATLEN:5; /**< bit: 0..4 Data Length */ + uint32_t LOOP:1; /**< bit: 5 Loop Mode */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */ + uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t FSLEN:4; /**< bit: 16..19 Receive Frame Sync Length */ + uint32_t FSOS:3; /**< bit: 20..22 Receive Frame Sync Output Selection */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */ + uint32_t :3; /**< bit: 25..27 Reserved */ + uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RFMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RFMR_OFFSET (0x14) /**< (SSC_RFMR) Receive Frame Mode Register Offset */ + +#define SSC_RFMR_DATLEN_Pos 0 /**< (SSC_RFMR) Data Length Position */ +#define SSC_RFMR_DATLEN_Msk (_U_(0x1F) << SSC_RFMR_DATLEN_Pos) /**< (SSC_RFMR) Data Length Mask */ +#define SSC_RFMR_DATLEN(value) (SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)) +#define SSC_RFMR_LOOP_Pos 5 /**< (SSC_RFMR) Loop Mode Position */ +#define SSC_RFMR_LOOP_Msk (_U_(0x1) << SSC_RFMR_LOOP_Pos) /**< (SSC_RFMR) Loop Mode Mask */ +#define SSC_RFMR_LOOP SSC_RFMR_LOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_LOOP_Msk instead */ +#define SSC_RFMR_MSBF_Pos 7 /**< (SSC_RFMR) Most Significant Bit First Position */ +#define SSC_RFMR_MSBF_Msk (_U_(0x1) << SSC_RFMR_MSBF_Pos) /**< (SSC_RFMR) Most Significant Bit First Mask */ +#define SSC_RFMR_MSBF SSC_RFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_MSBF_Msk instead */ +#define SSC_RFMR_DATNB_Pos 8 /**< (SSC_RFMR) Data Number per Frame Position */ +#define SSC_RFMR_DATNB_Msk (_U_(0xF) << SSC_RFMR_DATNB_Pos) /**< (SSC_RFMR) Data Number per Frame Mask */ +#define SSC_RFMR_DATNB(value) (SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)) +#define SSC_RFMR_FSLEN_Pos 16 /**< (SSC_RFMR) Receive Frame Sync Length Position */ +#define SSC_RFMR_FSLEN_Msk (_U_(0xF) << SSC_RFMR_FSLEN_Pos) /**< (SSC_RFMR) Receive Frame Sync Length Mask */ +#define SSC_RFMR_FSLEN(value) (SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)) +#define SSC_RFMR_FSOS_Pos 20 /**< (SSC_RFMR) Receive Frame Sync Output Selection Position */ +#define SSC_RFMR_FSOS_Msk (_U_(0x7) << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Receive Frame Sync Output Selection Mask */ +#define SSC_RFMR_FSOS(value) (SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)) +#define SSC_RFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_NONE (SSC_RFMR_FSOS_NONE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) None, RF pin is an input Position */ +#define SSC_RFMR_FSOS_NEGATIVE (SSC_RFMR_FSOS_NEGATIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Negative Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_POSITIVE (SSC_RFMR_FSOS_POSITIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Positive Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_LOW (SSC_RFMR_FSOS_LOW_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_HIGH (SSC_RFMR_FSOS_HIGH_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_TOGGLING (SSC_RFMR_FSOS_TOGGLING_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSEDGE_Pos 24 /**< (SSC_RFMR) Frame Sync Edge Detection Position */ +#define SSC_RFMR_FSEDGE_Msk (_U_(0x1) << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Frame Sync Edge Detection Mask */ +#define SSC_RFMR_FSEDGE SSC_RFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_FSEDGE_Msk instead */ +#define SSC_RFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (SSC_RFMR_FSEDGE_POSITIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Positive Edge Detection Position */ +#define SSC_RFMR_FSEDGE_NEGATIVE (SSC_RFMR_FSEDGE_NEGATIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Negative Edge Detection Position */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 /**< (SSC_RFMR) FSLEN Field Extension Position */ +#define SSC_RFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_RFMR_FSLEN_EXT_Pos) /**< (SSC_RFMR) FSLEN Field Extension Mask */ +#define SSC_RFMR_FSLEN_EXT(value) (SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)) +#define SSC_RFMR_MASK _U_(0xF17F0FBF) /**< \deprecated (SSC_RFMR) Register MASK (Use SSC_RFMR_Msk instead) */ +#define SSC_RFMR_Msk _U_(0xF17F0FBF) /**< (SSC_RFMR) Register Mask */ + + +/* -------- SSC_TCMR : (SSC Offset: 0x18) (R/W 32) Transmit Clock Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CKS:2; /**< bit: 0..1 Transmit Clock Selection */ + uint32_t CKO:3; /**< bit: 2..4 Transmit Clock Output Mode Selection */ + uint32_t CKI:1; /**< bit: 5 Transmit Clock Inversion */ + uint32_t CKG:2; /**< bit: 6..7 Transmit Clock Gating Selection */ + uint32_t START:4; /**< bit: 8..11 Transmit Start Selection */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t STTDLY:8; /**< bit: 16..23 Transmit Start Delay */ + uint32_t PERIOD:8; /**< bit: 24..31 Transmit Period Divider Selection */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_TCMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_TCMR_OFFSET (0x18) /**< (SSC_TCMR) Transmit Clock Mode Register Offset */ + +#define SSC_TCMR_CKS_Pos 0 /**< (SSC_TCMR) Transmit Clock Selection Position */ +#define SSC_TCMR_CKS_Msk (_U_(0x3) << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Transmit Clock Selection Mask */ +#define SSC_TCMR_CKS(value) (SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)) +#define SSC_TCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK_Val _U_(0x1) /**< (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK_Val _U_(0x2) /**< (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKS_MCK (SSC_TCMR_CKS_MCK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Divided Clock Position */ +#define SSC_TCMR_CKS_RK (SSC_TCMR_CKS_RK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) RK Clock signal Position */ +#define SSC_TCMR_CKS_TK (SSC_TCMR_CKS_TK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) TK pin Position */ +#define SSC_TCMR_CKO_Pos 2 /**< (SSC_TCMR) Transmit Clock Output Mode Selection Position */ +#define SSC_TCMR_CKO_Msk (_U_(0x7) << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Mask */ +#define SSC_TCMR_CKO(value) (SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)) +#define SSC_TCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKO_NONE (SSC_TCMR_CKO_NONE_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) None, TK pin is an input Position */ +#define SSC_TCMR_CKO_CONTINUOUS (SSC_TCMR_CKO_CONTINUOUS_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output Position */ +#define SSC_TCMR_CKO_TRANSFER (SSC_TCMR_CKO_TRANSFER_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output Position */ +#define SSC_TCMR_CKI_Pos 5 /**< (SSC_TCMR) Transmit Clock Inversion Position */ +#define SSC_TCMR_CKI_Msk (_U_(0x1) << SSC_TCMR_CKI_Pos) /**< (SSC_TCMR) Transmit Clock Inversion Mask */ +#define SSC_TCMR_CKI SSC_TCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TCMR_CKI_Msk instead */ +#define SSC_TCMR_CKG_Pos 6 /**< (SSC_TCMR) Transmit Clock Gating Selection Position */ +#define SSC_TCMR_CKG_Msk (_U_(0x3) << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock Gating Selection Mask */ +#define SSC_TCMR_CKG(value) (SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)) +#define SSC_TCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW_Val _U_(0x1) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_CKG_CONTINUOUS (SSC_TCMR_CKG_CONTINUOUS_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) None Position */ +#define SSC_TCMR_CKG_EN_TF_LOW (SSC_TCMR_CKG_EN_TF_LOW_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low Position */ +#define SSC_TCMR_CKG_EN_TF_HIGH (SSC_TCMR_CKG_EN_TF_HIGH_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF High Position */ +#define SSC_TCMR_START_Pos 8 /**< (SSC_TCMR) Transmit Start Selection Position */ +#define SSC_TCMR_START_Msk (_U_(0xF) << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Transmit Start Selection Mask */ +#define SSC_TCMR_START(value) (SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)) +#define SSC_TCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE_Val _U_(0x1) /**< (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW_Val _U_(0x2) /**< (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH_Val _U_(0x3) /**< (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING_Val _U_(0x4) /**< (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING_Val _U_(0x5) /**< (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL_Val _U_(0x6) /**< (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE_Val _U_(0x7) /**< (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CONTINUOUS (SSC_TCMR_START_CONTINUOUS_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data Position */ +#define SSC_TCMR_START_RECEIVE (SSC_TCMR_START_RECEIVE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Receive start Position */ +#define SSC_TCMR_START_TF_LOW (SSC_TCMR_START_TF_LOW_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a low level on TF signal Position */ +#define SSC_TCMR_START_TF_HIGH (SSC_TCMR_START_TF_HIGH_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a high level on TF signal Position */ +#define SSC_TCMR_START_TF_FALLING (SSC_TCMR_START_TF_FALLING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a falling edge on TF signal Position */ +#define SSC_TCMR_START_TF_RISING (SSC_TCMR_START_TF_RISING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a rising edge on TF signal Position */ +#define SSC_TCMR_START_TF_LEVEL (SSC_TCMR_START_TF_LEVEL_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any level change on TF signal Position */ +#define SSC_TCMR_START_TF_EDGE (SSC_TCMR_START_TF_EDGE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any edge on TF signal Position */ +#define SSC_TCMR_STTDLY_Pos 16 /**< (SSC_TCMR) Transmit Start Delay Position */ +#define SSC_TCMR_STTDLY_Msk (_U_(0xFF) << SSC_TCMR_STTDLY_Pos) /**< (SSC_TCMR) Transmit Start Delay Mask */ +#define SSC_TCMR_STTDLY(value) (SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)) +#define SSC_TCMR_PERIOD_Pos 24 /**< (SSC_TCMR) Transmit Period Divider Selection Position */ +#define SSC_TCMR_PERIOD_Msk (_U_(0xFF) << SSC_TCMR_PERIOD_Pos) /**< (SSC_TCMR) Transmit Period Divider Selection Mask */ +#define SSC_TCMR_PERIOD(value) (SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)) +#define SSC_TCMR_MASK _U_(0xFFFF0FFF) /**< \deprecated (SSC_TCMR) Register MASK (Use SSC_TCMR_Msk instead) */ +#define SSC_TCMR_Msk _U_(0xFFFF0FFF) /**< (SSC_TCMR) Register Mask */ + + +/* -------- SSC_TFMR : (SSC Offset: 0x1c) (R/W 32) Transmit Frame Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATLEN:5; /**< bit: 0..4 Data Length */ + uint32_t DATDEF:1; /**< bit: 5 Data Default Value */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */ + uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t FSLEN:4; /**< bit: 16..19 Transmit Frame Sync Length */ + uint32_t FSOS:3; /**< bit: 20..22 Transmit Frame Sync Output Selection */ + uint32_t FSDEN:1; /**< bit: 23 Frame Sync Data Enable */ + uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */ + uint32_t :3; /**< bit: 25..27 Reserved */ + uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_TFMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_TFMR_OFFSET (0x1C) /**< (SSC_TFMR) Transmit Frame Mode Register Offset */ + +#define SSC_TFMR_DATLEN_Pos 0 /**< (SSC_TFMR) Data Length Position */ +#define SSC_TFMR_DATLEN_Msk (_U_(0x1F) << SSC_TFMR_DATLEN_Pos) /**< (SSC_TFMR) Data Length Mask */ +#define SSC_TFMR_DATLEN(value) (SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)) +#define SSC_TFMR_DATDEF_Pos 5 /**< (SSC_TFMR) Data Default Value Position */ +#define SSC_TFMR_DATDEF_Msk (_U_(0x1) << SSC_TFMR_DATDEF_Pos) /**< (SSC_TFMR) Data Default Value Mask */ +#define SSC_TFMR_DATDEF SSC_TFMR_DATDEF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_DATDEF_Msk instead */ +#define SSC_TFMR_MSBF_Pos 7 /**< (SSC_TFMR) Most Significant Bit First Position */ +#define SSC_TFMR_MSBF_Msk (_U_(0x1) << SSC_TFMR_MSBF_Pos) /**< (SSC_TFMR) Most Significant Bit First Mask */ +#define SSC_TFMR_MSBF SSC_TFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_MSBF_Msk instead */ +#define SSC_TFMR_DATNB_Pos 8 /**< (SSC_TFMR) Data Number per Frame Position */ +#define SSC_TFMR_DATNB_Msk (_U_(0xF) << SSC_TFMR_DATNB_Pos) /**< (SSC_TFMR) Data Number per Frame Mask */ +#define SSC_TFMR_DATNB(value) (SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)) +#define SSC_TFMR_FSLEN_Pos 16 /**< (SSC_TFMR) Transmit Frame Sync Length Position */ +#define SSC_TFMR_FSLEN_Msk (_U_(0xF) << SSC_TFMR_FSLEN_Pos) /**< (SSC_TFMR) Transmit Frame Sync Length Mask */ +#define SSC_TFMR_FSLEN(value) (SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)) +#define SSC_TFMR_FSOS_Pos 20 /**< (SSC_TFMR) Transmit Frame Sync Output Selection Position */ +#define SSC_TFMR_FSOS_Msk (_U_(0x7) << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Mask */ +#define SSC_TFMR_FSOS(value) (SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)) +#define SSC_TFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSOS_NONE (SSC_TFMR_FSOS_NONE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) None, TF pin is an input Position */ +#define SSC_TFMR_FSOS_NEGATIVE (SSC_TFMR_FSOS_NEGATIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Negative Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_POSITIVE (SSC_TFMR_FSOS_POSITIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Positive Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_LOW (SSC_TFMR_FSOS_LOW_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven Low during data transfer Position */ +#define SSC_TFMR_FSOS_HIGH (SSC_TFMR_FSOS_HIGH_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven High during data transfer Position */ +#define SSC_TFMR_FSOS_TOGGLING (SSC_TFMR_FSOS_TOGGLING_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Toggling at each start of data transfer Position */ +#define SSC_TFMR_FSDEN_Pos 23 /**< (SSC_TFMR) Frame Sync Data Enable Position */ +#define SSC_TFMR_FSDEN_Msk (_U_(0x1) << SSC_TFMR_FSDEN_Pos) /**< (SSC_TFMR) Frame Sync Data Enable Mask */ +#define SSC_TFMR_FSDEN SSC_TFMR_FSDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSDEN_Msk instead */ +#define SSC_TFMR_FSEDGE_Pos 24 /**< (SSC_TFMR) Frame Sync Edge Detection Position */ +#define SSC_TFMR_FSEDGE_Msk (_U_(0x1) << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Frame Sync Edge Detection Mask */ +#define SSC_TFMR_FSEDGE SSC_TFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSEDGE_Msk instead */ +#define SSC_TFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (SSC_TFMR_FSEDGE_POSITIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Positive Edge Detection Position */ +#define SSC_TFMR_FSEDGE_NEGATIVE (SSC_TFMR_FSEDGE_NEGATIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Negative Edge Detection Position */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 /**< (SSC_TFMR) FSLEN Field Extension Position */ +#define SSC_TFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_TFMR_FSLEN_EXT_Pos) /**< (SSC_TFMR) FSLEN Field Extension Mask */ +#define SSC_TFMR_FSLEN_EXT(value) (SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)) +#define SSC_TFMR_MASK _U_(0xF1FF0FBF) /**< \deprecated (SSC_TFMR) Register MASK (Use SSC_TFMR_Msk instead) */ +#define SSC_TFMR_Msk _U_(0xF1FF0FBF) /**< (SSC_TFMR) Register Mask */ + + +/* -------- SSC_RHR : (SSC Offset: 0x20) (R/ 32) Receive Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RDAT:32; /**< bit: 0..31 Receive Data */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RHR_OFFSET (0x20) /**< (SSC_RHR) Receive Holding Register Offset */ + +#define SSC_RHR_RDAT_Pos 0 /**< (SSC_RHR) Receive Data Position */ +#define SSC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << SSC_RHR_RDAT_Pos) /**< (SSC_RHR) Receive Data Mask */ +#define SSC_RHR_RDAT(value) (SSC_RHR_RDAT_Msk & ((value) << SSC_RHR_RDAT_Pos)) +#define SSC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_RHR) Register MASK (Use SSC_RHR_Msk instead) */ +#define SSC_RHR_Msk _U_(0xFFFFFFFF) /**< (SSC_RHR) Register Mask */ + + +/* -------- SSC_THR : (SSC Offset: 0x24) (/W 32) Transmit Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TDAT:32; /**< bit: 0..31 Transmit Data */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_THR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_THR_OFFSET (0x24) /**< (SSC_THR) Transmit Holding Register Offset */ + +#define SSC_THR_TDAT_Pos 0 /**< (SSC_THR) Transmit Data Position */ +#define SSC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << SSC_THR_TDAT_Pos) /**< (SSC_THR) Transmit Data Mask */ +#define SSC_THR_TDAT(value) (SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)) +#define SSC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_THR) Register MASK (Use SSC_THR_Msk instead) */ +#define SSC_THR_Msk _U_(0xFFFFFFFF) /**< (SSC_THR) Register Mask */ + + +/* -------- SSC_RSHR : (SSC Offset: 0x30) (R/ 32) Receive Sync. Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RSDAT:16; /**< bit: 0..15 Receive Synchronization Data */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RSHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RSHR_OFFSET (0x30) /**< (SSC_RSHR) Receive Sync. Holding Register Offset */ + +#define SSC_RSHR_RSDAT_Pos 0 /**< (SSC_RSHR) Receive Synchronization Data Position */ +#define SSC_RSHR_RSDAT_Msk (_U_(0xFFFF) << SSC_RSHR_RSDAT_Pos) /**< (SSC_RSHR) Receive Synchronization Data Mask */ +#define SSC_RSHR_RSDAT(value) (SSC_RSHR_RSDAT_Msk & ((value) << SSC_RSHR_RSDAT_Pos)) +#define SSC_RSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_RSHR) Register MASK (Use SSC_RSHR_Msk instead) */ +#define SSC_RSHR_Msk _U_(0xFFFF) /**< (SSC_RSHR) Register Mask */ + + +/* -------- SSC_TSHR : (SSC Offset: 0x34) (R/W 32) Transmit Sync. Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TSDAT:16; /**< bit: 0..15 Transmit Synchronization Data */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_TSHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_TSHR_OFFSET (0x34) /**< (SSC_TSHR) Transmit Sync. Holding Register Offset */ + +#define SSC_TSHR_TSDAT_Pos 0 /**< (SSC_TSHR) Transmit Synchronization Data Position */ +#define SSC_TSHR_TSDAT_Msk (_U_(0xFFFF) << SSC_TSHR_TSDAT_Pos) /**< (SSC_TSHR) Transmit Synchronization Data Mask */ +#define SSC_TSHR_TSDAT(value) (SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)) +#define SSC_TSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_TSHR) Register MASK (Use SSC_TSHR_Msk instead) */ +#define SSC_TSHR_Msk _U_(0xFFFF) /**< (SSC_TSHR) Register Mask */ + + +/* -------- SSC_RC0R : (SSC Offset: 0x38) (R/W 32) Receive Compare 0 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CP0:16; /**< bit: 0..15 Receive Compare Data 0 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RC0R_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RC0R_OFFSET (0x38) /**< (SSC_RC0R) Receive Compare 0 Register Offset */ + +#define SSC_RC0R_CP0_Pos 0 /**< (SSC_RC0R) Receive Compare Data 0 Position */ +#define SSC_RC0R_CP0_Msk (_U_(0xFFFF) << SSC_RC0R_CP0_Pos) /**< (SSC_RC0R) Receive Compare Data 0 Mask */ +#define SSC_RC0R_CP0(value) (SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)) +#define SSC_RC0R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC0R) Register MASK (Use SSC_RC0R_Msk instead) */ +#define SSC_RC0R_Msk _U_(0xFFFF) /**< (SSC_RC0R) Register Mask */ + + +/* -------- SSC_RC1R : (SSC Offset: 0x3c) (R/W 32) Receive Compare 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CP1:16; /**< bit: 0..15 Receive Compare Data 1 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_RC1R_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_RC1R_OFFSET (0x3C) /**< (SSC_RC1R) Receive Compare 1 Register Offset */ + +#define SSC_RC1R_CP1_Pos 0 /**< (SSC_RC1R) Receive Compare Data 1 Position */ +#define SSC_RC1R_CP1_Msk (_U_(0xFFFF) << SSC_RC1R_CP1_Pos) /**< (SSC_RC1R) Receive Compare Data 1 Mask */ +#define SSC_RC1R_CP1(value) (SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)) +#define SSC_RC1R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC1R) Register MASK (Use SSC_RC1R_Msk instead) */ +#define SSC_RC1R_Msk _U_(0xFFFF) /**< (SSC_RC1R) Register Mask */ + + +/* -------- SSC_SR : (SSC Offset: 0x40) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY:1; /**< bit: 0 Transmit Ready */ + uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t RXRDY:1; /**< bit: 4 Receive Ready */ + uint32_t OVRUN:1; /**< bit: 5 Receive Overrun */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t CP0:1; /**< bit: 8 Compare 0 */ + uint32_t CP1:1; /**< bit: 9 Compare 1 */ + uint32_t TXSYN:1; /**< bit: 10 Transmit Sync */ + uint32_t RXSYN:1; /**< bit: 11 Receive Sync */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t TXEN:1; /**< bit: 16 Transmit Enable */ + uint32_t RXEN:1; /**< bit: 17 Receive Enable */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CP:2; /**< bit: 8..9 Compare x */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SSC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_SR_OFFSET (0x40) /**< (SSC_SR) Status Register Offset */ + +#define SSC_SR_TXRDY_Pos 0 /**< (SSC_SR) Transmit Ready Position */ +#define SSC_SR_TXRDY_Msk (_U_(0x1) << SSC_SR_TXRDY_Pos) /**< (SSC_SR) Transmit Ready Mask */ +#define SSC_SR_TXRDY SSC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXRDY_Msk instead */ +#define SSC_SR_TXEMPTY_Pos 1 /**< (SSC_SR) Transmit Empty Position */ +#define SSC_SR_TXEMPTY_Msk (_U_(0x1) << SSC_SR_TXEMPTY_Pos) /**< (SSC_SR) Transmit Empty Mask */ +#define SSC_SR_TXEMPTY SSC_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEMPTY_Msk instead */ +#define SSC_SR_RXRDY_Pos 4 /**< (SSC_SR) Receive Ready Position */ +#define SSC_SR_RXRDY_Msk (_U_(0x1) << SSC_SR_RXRDY_Pos) /**< (SSC_SR) Receive Ready Mask */ +#define SSC_SR_RXRDY SSC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXRDY_Msk instead */ +#define SSC_SR_OVRUN_Pos 5 /**< (SSC_SR) Receive Overrun Position */ +#define SSC_SR_OVRUN_Msk (_U_(0x1) << SSC_SR_OVRUN_Pos) /**< (SSC_SR) Receive Overrun Mask */ +#define SSC_SR_OVRUN SSC_SR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_OVRUN_Msk instead */ +#define SSC_SR_CP0_Pos 8 /**< (SSC_SR) Compare 0 Position */ +#define SSC_SR_CP0_Msk (_U_(0x1) << SSC_SR_CP0_Pos) /**< (SSC_SR) Compare 0 Mask */ +#define SSC_SR_CP0 SSC_SR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP0_Msk instead */ +#define SSC_SR_CP1_Pos 9 /**< (SSC_SR) Compare 1 Position */ +#define SSC_SR_CP1_Msk (_U_(0x1) << SSC_SR_CP1_Pos) /**< (SSC_SR) Compare 1 Mask */ +#define SSC_SR_CP1 SSC_SR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP1_Msk instead */ +#define SSC_SR_TXSYN_Pos 10 /**< (SSC_SR) Transmit Sync Position */ +#define SSC_SR_TXSYN_Msk (_U_(0x1) << SSC_SR_TXSYN_Pos) /**< (SSC_SR) Transmit Sync Mask */ +#define SSC_SR_TXSYN SSC_SR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXSYN_Msk instead */ +#define SSC_SR_RXSYN_Pos 11 /**< (SSC_SR) Receive Sync Position */ +#define SSC_SR_RXSYN_Msk (_U_(0x1) << SSC_SR_RXSYN_Pos) /**< (SSC_SR) Receive Sync Mask */ +#define SSC_SR_RXSYN SSC_SR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXSYN_Msk instead */ +#define SSC_SR_TXEN_Pos 16 /**< (SSC_SR) Transmit Enable Position */ +#define SSC_SR_TXEN_Msk (_U_(0x1) << SSC_SR_TXEN_Pos) /**< (SSC_SR) Transmit Enable Mask */ +#define SSC_SR_TXEN SSC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEN_Msk instead */ +#define SSC_SR_RXEN_Pos 17 /**< (SSC_SR) Receive Enable Position */ +#define SSC_SR_RXEN_Msk (_U_(0x1) << SSC_SR_RXEN_Pos) /**< (SSC_SR) Receive Enable Mask */ +#define SSC_SR_RXEN SSC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXEN_Msk instead */ +#define SSC_SR_MASK _U_(0x30F33) /**< \deprecated (SSC_SR) Register MASK (Use SSC_SR_Msk instead) */ +#define SSC_SR_Msk _U_(0x30F33) /**< (SSC_SR) Register Mask */ + +#define SSC_SR_CP_Pos 8 /**< (SSC_SR Position) Compare x */ +#define SSC_SR_CP_Msk (_U_(0x3) << SSC_SR_CP_Pos) /**< (SSC_SR Mask) CP */ +#define SSC_SR_CP(value) (SSC_SR_CP_Msk & ((value) << SSC_SR_CP_Pos)) + +/* -------- SSC_IER : (SSC Offset: 0x44) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Enable */ + uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Enable */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Enable */ + uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Enable */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Enable */ + uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Enable */ + uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */ + uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Enable */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SSC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_IER_OFFSET (0x44) /**< (SSC_IER) Interrupt Enable Register Offset */ + +#define SSC_IER_TXRDY_Pos 0 /**< (SSC_IER) Transmit Ready Interrupt Enable Position */ +#define SSC_IER_TXRDY_Msk (_U_(0x1) << SSC_IER_TXRDY_Pos) /**< (SSC_IER) Transmit Ready Interrupt Enable Mask */ +#define SSC_IER_TXRDY SSC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXRDY_Msk instead */ +#define SSC_IER_TXEMPTY_Pos 1 /**< (SSC_IER) Transmit Empty Interrupt Enable Position */ +#define SSC_IER_TXEMPTY_Msk (_U_(0x1) << SSC_IER_TXEMPTY_Pos) /**< (SSC_IER) Transmit Empty Interrupt Enable Mask */ +#define SSC_IER_TXEMPTY SSC_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXEMPTY_Msk instead */ +#define SSC_IER_RXRDY_Pos 4 /**< (SSC_IER) Receive Ready Interrupt Enable Position */ +#define SSC_IER_RXRDY_Msk (_U_(0x1) << SSC_IER_RXRDY_Pos) /**< (SSC_IER) Receive Ready Interrupt Enable Mask */ +#define SSC_IER_RXRDY SSC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXRDY_Msk instead */ +#define SSC_IER_OVRUN_Pos 5 /**< (SSC_IER) Receive Overrun Interrupt Enable Position */ +#define SSC_IER_OVRUN_Msk (_U_(0x1) << SSC_IER_OVRUN_Pos) /**< (SSC_IER) Receive Overrun Interrupt Enable Mask */ +#define SSC_IER_OVRUN SSC_IER_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_OVRUN_Msk instead */ +#define SSC_IER_CP0_Pos 8 /**< (SSC_IER) Compare 0 Interrupt Enable Position */ +#define SSC_IER_CP0_Msk (_U_(0x1) << SSC_IER_CP0_Pos) /**< (SSC_IER) Compare 0 Interrupt Enable Mask */ +#define SSC_IER_CP0 SSC_IER_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP0_Msk instead */ +#define SSC_IER_CP1_Pos 9 /**< (SSC_IER) Compare 1 Interrupt Enable Position */ +#define SSC_IER_CP1_Msk (_U_(0x1) << SSC_IER_CP1_Pos) /**< (SSC_IER) Compare 1 Interrupt Enable Mask */ +#define SSC_IER_CP1 SSC_IER_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP1_Msk instead */ +#define SSC_IER_TXSYN_Pos 10 /**< (SSC_IER) Tx Sync Interrupt Enable Position */ +#define SSC_IER_TXSYN_Msk (_U_(0x1) << SSC_IER_TXSYN_Pos) /**< (SSC_IER) Tx Sync Interrupt Enable Mask */ +#define SSC_IER_TXSYN SSC_IER_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXSYN_Msk instead */ +#define SSC_IER_RXSYN_Pos 11 /**< (SSC_IER) Rx Sync Interrupt Enable Position */ +#define SSC_IER_RXSYN_Msk (_U_(0x1) << SSC_IER_RXSYN_Pos) /**< (SSC_IER) Rx Sync Interrupt Enable Mask */ +#define SSC_IER_RXSYN SSC_IER_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXSYN_Msk instead */ +#define SSC_IER_MASK _U_(0xF33) /**< \deprecated (SSC_IER) Register MASK (Use SSC_IER_Msk instead) */ +#define SSC_IER_Msk _U_(0xF33) /**< (SSC_IER) Register Mask */ + +#define SSC_IER_CP_Pos 8 /**< (SSC_IER Position) Compare x Interrupt Enable */ +#define SSC_IER_CP_Msk (_U_(0x3) << SSC_IER_CP_Pos) /**< (SSC_IER Mask) CP */ +#define SSC_IER_CP(value) (SSC_IER_CP_Msk & ((value) << SSC_IER_CP_Pos)) + +/* -------- SSC_IDR : (SSC Offset: 0x48) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Disable */ + uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Disable */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Disable */ + uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Disable */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Disable */ + uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Disable */ + uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */ + uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Disable */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SSC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_IDR_OFFSET (0x48) /**< (SSC_IDR) Interrupt Disable Register Offset */ + +#define SSC_IDR_TXRDY_Pos 0 /**< (SSC_IDR) Transmit Ready Interrupt Disable Position */ +#define SSC_IDR_TXRDY_Msk (_U_(0x1) << SSC_IDR_TXRDY_Pos) /**< (SSC_IDR) Transmit Ready Interrupt Disable Mask */ +#define SSC_IDR_TXRDY SSC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXRDY_Msk instead */ +#define SSC_IDR_TXEMPTY_Pos 1 /**< (SSC_IDR) Transmit Empty Interrupt Disable Position */ +#define SSC_IDR_TXEMPTY_Msk (_U_(0x1) << SSC_IDR_TXEMPTY_Pos) /**< (SSC_IDR) Transmit Empty Interrupt Disable Mask */ +#define SSC_IDR_TXEMPTY SSC_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXEMPTY_Msk instead */ +#define SSC_IDR_RXRDY_Pos 4 /**< (SSC_IDR) Receive Ready Interrupt Disable Position */ +#define SSC_IDR_RXRDY_Msk (_U_(0x1) << SSC_IDR_RXRDY_Pos) /**< (SSC_IDR) Receive Ready Interrupt Disable Mask */ +#define SSC_IDR_RXRDY SSC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXRDY_Msk instead */ +#define SSC_IDR_OVRUN_Pos 5 /**< (SSC_IDR) Receive Overrun Interrupt Disable Position */ +#define SSC_IDR_OVRUN_Msk (_U_(0x1) << SSC_IDR_OVRUN_Pos) /**< (SSC_IDR) Receive Overrun Interrupt Disable Mask */ +#define SSC_IDR_OVRUN SSC_IDR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_OVRUN_Msk instead */ +#define SSC_IDR_CP0_Pos 8 /**< (SSC_IDR) Compare 0 Interrupt Disable Position */ +#define SSC_IDR_CP0_Msk (_U_(0x1) << SSC_IDR_CP0_Pos) /**< (SSC_IDR) Compare 0 Interrupt Disable Mask */ +#define SSC_IDR_CP0 SSC_IDR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP0_Msk instead */ +#define SSC_IDR_CP1_Pos 9 /**< (SSC_IDR) Compare 1 Interrupt Disable Position */ +#define SSC_IDR_CP1_Msk (_U_(0x1) << SSC_IDR_CP1_Pos) /**< (SSC_IDR) Compare 1 Interrupt Disable Mask */ +#define SSC_IDR_CP1 SSC_IDR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP1_Msk instead */ +#define SSC_IDR_TXSYN_Pos 10 /**< (SSC_IDR) Tx Sync Interrupt Enable Position */ +#define SSC_IDR_TXSYN_Msk (_U_(0x1) << SSC_IDR_TXSYN_Pos) /**< (SSC_IDR) Tx Sync Interrupt Enable Mask */ +#define SSC_IDR_TXSYN SSC_IDR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXSYN_Msk instead */ +#define SSC_IDR_RXSYN_Pos 11 /**< (SSC_IDR) Rx Sync Interrupt Enable Position */ +#define SSC_IDR_RXSYN_Msk (_U_(0x1) << SSC_IDR_RXSYN_Pos) /**< (SSC_IDR) Rx Sync Interrupt Enable Mask */ +#define SSC_IDR_RXSYN SSC_IDR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXSYN_Msk instead */ +#define SSC_IDR_MASK _U_(0xF33) /**< \deprecated (SSC_IDR) Register MASK (Use SSC_IDR_Msk instead) */ +#define SSC_IDR_Msk _U_(0xF33) /**< (SSC_IDR) Register Mask */ + +#define SSC_IDR_CP_Pos 8 /**< (SSC_IDR Position) Compare x Interrupt Disable */ +#define SSC_IDR_CP_Msk (_U_(0x3) << SSC_IDR_CP_Pos) /**< (SSC_IDR Mask) CP */ +#define SSC_IDR_CP(value) (SSC_IDR_CP_Msk & ((value) << SSC_IDR_CP_Pos)) + +/* -------- SSC_IMR : (SSC Offset: 0x4c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Mask */ + uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Mask */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Mask */ + uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Mask */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Mask */ + uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Mask */ + uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Mask */ + uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Mask */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Mask */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SSC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_IMR_OFFSET (0x4C) /**< (SSC_IMR) Interrupt Mask Register Offset */ + +#define SSC_IMR_TXRDY_Pos 0 /**< (SSC_IMR) Transmit Ready Interrupt Mask Position */ +#define SSC_IMR_TXRDY_Msk (_U_(0x1) << SSC_IMR_TXRDY_Pos) /**< (SSC_IMR) Transmit Ready Interrupt Mask Mask */ +#define SSC_IMR_TXRDY SSC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXRDY_Msk instead */ +#define SSC_IMR_TXEMPTY_Pos 1 /**< (SSC_IMR) Transmit Empty Interrupt Mask Position */ +#define SSC_IMR_TXEMPTY_Msk (_U_(0x1) << SSC_IMR_TXEMPTY_Pos) /**< (SSC_IMR) Transmit Empty Interrupt Mask Mask */ +#define SSC_IMR_TXEMPTY SSC_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXEMPTY_Msk instead */ +#define SSC_IMR_RXRDY_Pos 4 /**< (SSC_IMR) Receive Ready Interrupt Mask Position */ +#define SSC_IMR_RXRDY_Msk (_U_(0x1) << SSC_IMR_RXRDY_Pos) /**< (SSC_IMR) Receive Ready Interrupt Mask Mask */ +#define SSC_IMR_RXRDY SSC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXRDY_Msk instead */ +#define SSC_IMR_OVRUN_Pos 5 /**< (SSC_IMR) Receive Overrun Interrupt Mask Position */ +#define SSC_IMR_OVRUN_Msk (_U_(0x1) << SSC_IMR_OVRUN_Pos) /**< (SSC_IMR) Receive Overrun Interrupt Mask Mask */ +#define SSC_IMR_OVRUN SSC_IMR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_OVRUN_Msk instead */ +#define SSC_IMR_CP0_Pos 8 /**< (SSC_IMR) Compare 0 Interrupt Mask Position */ +#define SSC_IMR_CP0_Msk (_U_(0x1) << SSC_IMR_CP0_Pos) /**< (SSC_IMR) Compare 0 Interrupt Mask Mask */ +#define SSC_IMR_CP0 SSC_IMR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP0_Msk instead */ +#define SSC_IMR_CP1_Pos 9 /**< (SSC_IMR) Compare 1 Interrupt Mask Position */ +#define SSC_IMR_CP1_Msk (_U_(0x1) << SSC_IMR_CP1_Pos) /**< (SSC_IMR) Compare 1 Interrupt Mask Mask */ +#define SSC_IMR_CP1 SSC_IMR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP1_Msk instead */ +#define SSC_IMR_TXSYN_Pos 10 /**< (SSC_IMR) Tx Sync Interrupt Mask Position */ +#define SSC_IMR_TXSYN_Msk (_U_(0x1) << SSC_IMR_TXSYN_Pos) /**< (SSC_IMR) Tx Sync Interrupt Mask Mask */ +#define SSC_IMR_TXSYN SSC_IMR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXSYN_Msk instead */ +#define SSC_IMR_RXSYN_Pos 11 /**< (SSC_IMR) Rx Sync Interrupt Mask Position */ +#define SSC_IMR_RXSYN_Msk (_U_(0x1) << SSC_IMR_RXSYN_Pos) /**< (SSC_IMR) Rx Sync Interrupt Mask Mask */ +#define SSC_IMR_RXSYN SSC_IMR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXSYN_Msk instead */ +#define SSC_IMR_MASK _U_(0xF33) /**< \deprecated (SSC_IMR) Register MASK (Use SSC_IMR_Msk instead) */ +#define SSC_IMR_Msk _U_(0xF33) /**< (SSC_IMR) Register Mask */ + +#define SSC_IMR_CP_Pos 8 /**< (SSC_IMR Position) Compare x Interrupt Mask */ +#define SSC_IMR_CP_Msk (_U_(0x3) << SSC_IMR_CP_Pos) /**< (SSC_IMR Mask) CP */ +#define SSC_IMR_CP(value) (SSC_IMR_CP_Msk & ((value) << SSC_IMR_CP_Pos)) + +/* -------- SSC_WPMR : (SSC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_WPMR_OFFSET (0xE4) /**< (SSC_WPMR) Write Protection Mode Register Offset */ + +#define SSC_WPMR_WPEN_Pos 0 /**< (SSC_WPMR) Write Protection Enable Position */ +#define SSC_WPMR_WPEN_Msk (_U_(0x1) << SSC_WPMR_WPEN_Pos) /**< (SSC_WPMR) Write Protection Enable Mask */ +#define SSC_WPMR_WPEN SSC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPMR_WPEN_Msk instead */ +#define SSC_WPMR_WPKEY_Pos 8 /**< (SSC_WPMR) Write Protection Key Position */ +#define SSC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Write Protection Key Mask */ +#define SSC_WPMR_WPKEY(value) (SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)) +#define SSC_WPMR_WPKEY_PASSWD_Val _U_(0x535343) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SSC_WPMR_WPKEY_PASSWD (SSC_WPMR_WPKEY_PASSWD_Val << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SSC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SSC_WPMR) Register MASK (Use SSC_WPMR_Msk instead) */ +#define SSC_WPMR_Msk _U_(0xFFFFFF01) /**< (SSC_WPMR) Register Mask */ + + +/* -------- SSC_WPSR : (SSC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protect Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SSC_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SSC_WPSR_OFFSET (0xE8) /**< (SSC_WPSR) Write Protection Status Register Offset */ + +#define SSC_WPSR_WPVS_Pos 0 /**< (SSC_WPSR) Write Protection Violation Status Position */ +#define SSC_WPSR_WPVS_Msk (_U_(0x1) << SSC_WPSR_WPVS_Pos) /**< (SSC_WPSR) Write Protection Violation Status Mask */ +#define SSC_WPSR_WPVS SSC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPSR_WPVS_Msk instead */ +#define SSC_WPSR_WPVSRC_Pos 8 /**< (SSC_WPSR) Write Protect Violation Source Position */ +#define SSC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SSC_WPSR_WPVSRC_Pos) /**< (SSC_WPSR) Write Protect Violation Source Mask */ +#define SSC_WPSR_WPVSRC(value) (SSC_WPSR_WPVSRC_Msk & ((value) << SSC_WPSR_WPVSRC_Pos)) +#define SSC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SSC_WPSR) Register MASK (Use SSC_WPSR_Msk instead) */ +#define SSC_WPSR_Msk _U_(0xFFFF01) /**< (SSC_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief SSC hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< (SSC Offset: 0x00) Control Register */ + __IO uint32_t SSC_CMR; /**< (SSC Offset: 0x04) Clock Mode Register */ + __I uint8_t Reserved1[8]; + __IO uint32_t SSC_RCMR; /**< (SSC Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< (SSC Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< (SSC Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< (SSC Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< (SSC Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< (SSC Offset: 0x24) Transmit Holding Register */ + __I uint8_t Reserved2[8]; + __I uint32_t SSC_RSHR; /**< (SSC Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< (SSC Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< (SSC Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< (SSC Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< (SSC Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< (SSC Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< (SSC Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< (SSC Offset: 0x4C) Interrupt Mask Register */ + __I uint8_t Reserved3[148]; + __IO uint32_t SSC_WPMR; /**< (SSC Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< (SSC Offset: 0xE8) Write Protection Status Register */ +} Ssc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief SSC hardware registers */ +typedef struct { + __O SSC_CR_Type SSC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO SSC_CMR_Type SSC_CMR; /**< Offset: 0x04 (R/W 32) Clock Mode Register */ + __I uint8_t Reserved1[8]; + __IO SSC_RCMR_Type SSC_RCMR; /**< Offset: 0x10 (R/W 32) Receive Clock Mode Register */ + __IO SSC_RFMR_Type SSC_RFMR; /**< Offset: 0x14 (R/W 32) Receive Frame Mode Register */ + __IO SSC_TCMR_Type SSC_TCMR; /**< Offset: 0x18 (R/W 32) Transmit Clock Mode Register */ + __IO SSC_TFMR_Type SSC_TFMR; /**< Offset: 0x1C (R/W 32) Transmit Frame Mode Register */ + __I SSC_RHR_Type SSC_RHR; /**< Offset: 0x20 (R/ 32) Receive Holding Register */ + __O SSC_THR_Type SSC_THR; /**< Offset: 0x24 ( /W 32) Transmit Holding Register */ + __I uint8_t Reserved2[8]; + __I SSC_RSHR_Type SSC_RSHR; /**< Offset: 0x30 (R/ 32) Receive Sync. Holding Register */ + __IO SSC_TSHR_Type SSC_TSHR; /**< Offset: 0x34 (R/W 32) Transmit Sync. Holding Register */ + __IO SSC_RC0R_Type SSC_RC0R; /**< Offset: 0x38 (R/W 32) Receive Compare 0 Register */ + __IO SSC_RC1R_Type SSC_RC1R; /**< Offset: 0x3C (R/W 32) Receive Compare 1 Register */ + __I SSC_SR_Type SSC_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O SSC_IER_Type SSC_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O SSC_IDR_Type SSC_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I SSC_IMR_Type SSC_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved3[148]; + __IO SSC_WPMR_Type SSC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I SSC_WPSR_Type SSC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Ssc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Synchronous Serial Controller */ + +#endif /* _SAME70_SSC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/supc.h b/bsp/microchip/same70/bsp/same70b/include/component/supc.h new file mode 100644 index 0000000000..0eb44b8765 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/supc.h @@ -0,0 +1,823 @@ +/** + * \file + * + * \brief Component description for SUPC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SUPC_COMPONENT_H_ +#define _SAME70_SUPC_COMPONENT_H_ +#define _SAME70_SUPC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Supply Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SUPC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define SUPC_6452 /**< (SUPC) Module ID */ +#define REV_SUPC ZE /**< (SUPC) Module revision */ + +/* -------- SUPC_CR : (SUPC Offset: 0x00) (/W 32) Supply Controller Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t VROFF:1; /**< bit: 2 Voltage Regulator Off */ + uint32_t XTALSEL:1; /**< bit: 3 Crystal Oscillator Select */ + uint32_t :20; /**< bit: 4..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 Password */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_CR_OFFSET (0x00) /**< (SUPC_CR) Supply Controller Control Register Offset */ + +#define SUPC_CR_VROFF_Pos 2 /**< (SUPC_CR) Voltage Regulator Off Position */ +#define SUPC_CR_VROFF_Msk (_U_(0x1) << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) Voltage Regulator Off Mask */ +#define SUPC_CR_VROFF SUPC_CR_VROFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_VROFF_Msk instead */ +#define SUPC_CR_VROFF_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_VROFF_NO_EFFECT (SUPC_CR_VROFF_NO_EFFECT_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_VROFF_STOP_VREG (SUPC_CR_VROFF_STOP_VREG_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Position */ +#define SUPC_CR_XTALSEL_Pos 3 /**< (SUPC_CR) Crystal Oscillator Select Position */ +#define SUPC_CR_XTALSEL_Msk (_U_(0x1) << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) Crystal Oscillator Select Mask */ +#define SUPC_CR_XTALSEL SUPC_CR_XTALSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_XTALSEL_Msk instead */ +#define SUPC_CR_XTALSEL_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_XTALSEL_NO_EFFECT (SUPC_CR_XTALSEL_NO_EFFECT_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (SUPC_CR_XTALSEL_CRYSTAL_SEL_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Position */ +#define SUPC_CR_KEY_Pos 24 /**< (SUPC_CR) Password Position */ +#define SUPC_CR_KEY_Msk (_U_(0xFF) << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Password Mask */ +#define SUPC_CR_KEY(value) (SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)) +#define SUPC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. */ +#define SUPC_CR_KEY_PASSWD (SUPC_CR_KEY_PASSWD_Val << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_CR_MASK _U_(0xFF00000C) /**< \deprecated (SUPC_CR) Register MASK (Use SUPC_CR_Msk instead) */ +#define SUPC_CR_Msk _U_(0xFF00000C) /**< (SUPC_CR) Register Mask */ + + +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) (R/W 32) Supply Controller Supply Monitor Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SMTH:4; /**< bit: 0..3 Supply Monitor Threshold */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t SMSMPL:3; /**< bit: 8..10 Supply Monitor Sampling Period */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t SMRSTEN:1; /**< bit: 12 Supply Monitor Reset Enable */ + uint32_t SMIEN:1; /**< bit: 13 Supply Monitor Interrupt Enable */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_SMMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_SMMR_OFFSET (0x04) /**< (SUPC_SMMR) Supply Controller Supply Monitor Mode Register Offset */ + +#define SUPC_SMMR_SMTH_Pos 0 /**< (SUPC_SMMR) Supply Monitor Threshold Position */ +#define SUPC_SMMR_SMTH_Msk (_U_(0xF) << SUPC_SMMR_SMTH_Pos) /**< (SUPC_SMMR) Supply Monitor Threshold Mask */ +#define SUPC_SMMR_SMTH(value) (SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)) +#define SUPC_SMMR_SMSMPL_Pos 8 /**< (SUPC_SMMR) Supply Monitor Sampling Period Position */ +#define SUPC_SMMR_SMSMPL_Msk (_U_(0x7) << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor Sampling Period Mask */ +#define SUPC_SMMR_SMSMPL(value) (SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)) +#define SUPC_SMMR_SMSMPL_SMD_Val _U_(0x0) /**< (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM_Val _U_(0x1) /**< (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK_Val _U_(0x2) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK_Val _U_(0x3) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK_Val _U_(0x4) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMSMPL_SMD (SUPC_SMMR_SMSMPL_SMD_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor disabled Position */ +#define SUPC_SMMR_SMSMPL_CSM (SUPC_SMMR_SMSMPL_CSM_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Continuous Supply Monitor Position */ +#define SUPC_SMMR_SMSMPL_32SLCK (SUPC_SMMR_SMSMPL_32SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_256SLCK (SUPC_SMMR_SMSMPL_256SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_2048SLCK (SUPC_SMMR_SMSMPL_2048SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods Position */ +#define SUPC_SMMR_SMRSTEN_Pos 12 /**< (SUPC_SMMR) Supply Monitor Reset Enable Position */ +#define SUPC_SMMR_SMRSTEN_Msk (_U_(0x1) << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) Supply Monitor Reset Enable Mask */ +#define SUPC_SMMR_SMRSTEN SUPC_SMMR_SMRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMRSTEN_Msk instead */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMRSTEN_ENABLE (SUPC_SMMR_SMRSTEN_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_Pos 13 /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Position */ +#define SUPC_SMMR_SMIEN_Msk (_U_(0x1) << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Mask */ +#define SUPC_SMMR_SMIEN SUPC_SMMR_SMIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMIEN_Msk instead */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (SUPC_SMMR_SMIEN_NOT_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_ENABLE (SUPC_SMMR_SMIEN_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_MASK _U_(0x370F) /**< \deprecated (SUPC_SMMR) Register MASK (Use SUPC_SMMR_Msk instead) */ +#define SUPC_SMMR_Msk _U_(0x370F) /**< (SUPC_SMMR) Register Mask */ + + +/* -------- SUPC_MR : (SUPC Offset: 0x08) (R/W 32) Supply Controller Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :12; /**< bit: 0..11 Reserved */ + uint32_t BODRSTEN:1; /**< bit: 12 Brownout Detector Reset Enable */ + uint32_t BODDIS:1; /**< bit: 13 Brownout Detector Disable */ + uint32_t ONREG:1; /**< bit: 14 Voltage Regulator Enable */ + uint32_t :2; /**< bit: 15..16 Reserved */ + uint32_t BKUPRETON:1; /**< bit: 17 SRAM On In Backup Mode */ + uint32_t :2; /**< bit: 18..19 Reserved */ + uint32_t OSCBYPASS:1; /**< bit: 20 Oscillator Bypass */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 Password Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_MR_OFFSET (0x08) /**< (SUPC_MR) Supply Controller Mode Register Offset */ + +#define SUPC_MR_BODRSTEN_Pos 12 /**< (SUPC_MR) Brownout Detector Reset Enable Position */ +#define SUPC_MR_BODRSTEN_Msk (_U_(0x1) << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) Brownout Detector Reset Enable Mask */ +#define SUPC_MR_BODRSTEN SUPC_MR_BODRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODRSTEN_Msk instead */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (SUPC_MR_BODRSTEN_NOT_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. Position */ +#define SUPC_MR_BODRSTEN_ENABLE (SUPC_MR_BODRSTEN_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Position */ +#define SUPC_MR_BODDIS_Pos 13 /**< (SUPC_MR) Brownout Detector Disable Position */ +#define SUPC_MR_BODDIS_Msk (_U_(0x1) << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) Brownout Detector Disable Mask */ +#define SUPC_MR_BODDIS SUPC_MR_BODDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODDIS_Msk instead */ +#define SUPC_MR_BODDIS_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE_Val _U_(0x1) /**< (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_BODDIS_ENABLE (SUPC_MR_BODDIS_ENABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is enabled. Position */ +#define SUPC_MR_BODDIS_DISABLE (SUPC_MR_BODDIS_DISABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is disabled. Position */ +#define SUPC_MR_ONREG_Pos 14 /**< (SUPC_MR) Voltage Regulator Enable Position */ +#define SUPC_MR_ONREG_Msk (_U_(0x1) << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Voltage Regulator Enable Mask */ +#define SUPC_MR_ONREG SUPC_MR_ONREG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_ONREG_Msk instead */ +#define SUPC_MR_ONREG_ONREG_UNUSED_Val _U_(0x0) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED_Val _U_(0x1) /**< (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_ONREG_ONREG_UNUSED (SUPC_MR_ONREG_ONREG_UNUSED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). Position */ +#define SUPC_MR_ONREG_ONREG_USED (SUPC_MR_ONREG_ONREG_USED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is used. Position */ +#define SUPC_MR_BKUPRETON_Pos 17 /**< (SUPC_MR) SRAM On In Backup Mode Position */ +#define SUPC_MR_BKUPRETON_Msk (_U_(0x1) << SUPC_MR_BKUPRETON_Pos) /**< (SUPC_MR) SRAM On In Backup Mode Mask */ +#define SUPC_MR_BKUPRETON SUPC_MR_BKUPRETON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BKUPRETON_Msk instead */ +#define SUPC_MR_OSCBYPASS_Pos 20 /**< (SUPC_MR) Oscillator Bypass Position */ +#define SUPC_MR_OSCBYPASS_Msk (_U_(0x1) << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) Oscillator Bypass Mask */ +#define SUPC_MR_OSCBYPASS SUPC_MR_OSCBYPASS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_OSCBYPASS_Msk instead */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT_Val _U_(0x0) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS_Val _U_(0x1) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (SUPC_MR_OSCBYPASS_NO_EFFECT_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). Position */ +#define SUPC_MR_OSCBYPASS_BYPASS (SUPC_MR_OSCBYPASS_BYPASS_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Position */ +#define SUPC_MR_KEY_Pos 24 /**< (SUPC_MR) Password Key Position */ +#define SUPC_MR_KEY_Msk (_U_(0xFF) << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Password Key Mask */ +#define SUPC_MR_KEY(value) (SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)) +#define SUPC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. */ +#define SUPC_MR_KEY_PASSWD (SUPC_MR_KEY_PASSWD_Val << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_MR_MASK _U_(0xFF127000) /**< \deprecated (SUPC_MR) Register MASK (Use SUPC_MR_Msk instead) */ +#define SUPC_MR_Msk _U_(0xFF127000) /**< (SUPC_MR) Register Mask */ + + +/* -------- SUPC_WUMR : (SUPC Offset: 0x0c) (R/W 32) Supply Controller Wake-up Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t SMEN:1; /**< bit: 1 Supply Monitor Wake-up Enable */ + uint32_t RTTEN:1; /**< bit: 2 Real-time Timer Wake-up Enable */ + uint32_t RTCEN:1; /**< bit: 3 Real-time Clock Wake-up Enable */ + uint32_t :1; /**< bit: 4 Reserved */ + uint32_t LPDBCEN0:1; /**< bit: 5 Low-power Debouncer Enable WKUP0 */ + uint32_t LPDBCEN1:1; /**< bit: 6 Low-power Debouncer Enable WKUP1 */ + uint32_t LPDBCCLR:1; /**< bit: 7 Low-power Debouncer Clear */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t WKUPDBC:3; /**< bit: 12..14 Wake-up Inputs Debouncer Period */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t LPDBC:3; /**< bit: 16..18 Low-power Debouncer Period */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :5; /**< bit: 0..4 Reserved */ + uint32_t LPDBCEN:2; /**< bit: 5..6 Low-power Debouncer Enable WKUPx */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_WUMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_WUMR_OFFSET (0x0C) /**< (SUPC_WUMR) Supply Controller Wake-up Mode Register Offset */ + +#define SUPC_WUMR_SMEN_Pos 1 /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Position */ +#define SUPC_WUMR_SMEN_Msk (_U_(0x1) << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Mask */ +#define SUPC_WUMR_SMEN SUPC_WUMR_SMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_SMEN_Msk instead */ +#define SUPC_WUMR_SMEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (SUPC_WUMR_SMEN_NOT_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. Position */ +#define SUPC_WUMR_SMEN_ENABLE (SUPC_WUMR_SMEN_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTTEN_Pos 2 /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Position */ +#define SUPC_WUMR_RTTEN_Msk (_U_(0x1) << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Mask */ +#define SUPC_WUMR_RTTEN SUPC_WUMR_RTTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTTEN_Msk instead */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (SUPC_WUMR_RTTEN_NOT_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTTEN_ENABLE (SUPC_WUMR_RTTEN_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTCEN_Pos 3 /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Position */ +#define SUPC_WUMR_RTCEN_Msk (_U_(0x1) << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Mask */ +#define SUPC_WUMR_RTCEN SUPC_WUMR_RTCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTCEN_Msk instead */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (SUPC_WUMR_RTCEN_NOT_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTCEN_ENABLE (SUPC_WUMR_RTCEN_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_LPDBCEN0_Pos 5 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Position */ +#define SUPC_WUMR_LPDBCEN0_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Mask */ +#define SUPC_WUMR_LPDBCEN0 SUPC_WUMR_LPDBCEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN0_Msk instead */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (SUPC_WUMR_LPDBCEN0_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCEN1_Pos 6 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Position */ +#define SUPC_WUMR_LPDBCEN1_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Mask */ +#define SUPC_WUMR_LPDBCEN1 SUPC_WUMR_LPDBCEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN1_Msk instead */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (SUPC_WUMR_LPDBCEN1_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCCLR_Pos 7 /**< (SUPC_WUMR) Low-power Debouncer Clear Position */ +#define SUPC_WUMR_LPDBCCLR_Msk (_U_(0x1) << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) Low-power Debouncer Clear Mask */ +#define SUPC_WUMR_LPDBCCLR SUPC_WUMR_LPDBCCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCCLR_Msk instead */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (SUPC_WUMR_LPDBCCLR_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_WKUPDBC_Pos 12 /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Position */ +#define SUPC_WUMR_WKUPDBC_Msk (_U_(0x7) << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Mask */ +#define SUPC_WUMR_WKUPDBC(value) (SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE_Val _U_(0x0) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK_Val _U_(0x1) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK_Val _U_(0x2) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK_Val _U_(0x3) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK_Val _U_(0x4) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK_Val _U_(0x5) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (SUPC_WUMR_WKUPDBC_IMMEDIATE_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. Position */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (SUPC_WUMR_WKUPDBC_3_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (SUPC_WUMR_WKUPDBC_32_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (SUPC_WUMR_WKUPDBC_512_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (SUPC_WUMR_WKUPDBC_4096_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (SUPC_WUMR_WKUPDBC_32768_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods Position */ +#define SUPC_WUMR_LPDBC_Pos 16 /**< (SUPC_WUMR) Low-power Debouncer Period Position */ +#define SUPC_WUMR_LPDBC_Msk (_U_(0x7) << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Low-power Debouncer Period Mask */ +#define SUPC_WUMR_LPDBC(value) (SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)) +#define SUPC_WUMR_LPDBC_DISABLE_Val _U_(0x0) /**< (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT_Val _U_(0x1) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT_Val _U_(0x2) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT_Val _U_(0x3) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT_Val _U_(0x4) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT_Val _U_(0x5) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT_Val _U_(0x6) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT_Val _U_(0x7) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_DISABLE (SUPC_WUMR_LPDBC_DISABLE_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Disable the low-power debouncers. Position */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (SUPC_WUMR_LPDBC_2_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (SUPC_WUMR_LPDBC_3_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (SUPC_WUMR_LPDBC_4_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (SUPC_WUMR_LPDBC_5_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (SUPC_WUMR_LPDBC_6_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (SUPC_WUMR_LPDBC_7_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (SUPC_WUMR_LPDBC_8_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods Position */ +#define SUPC_WUMR_MASK _U_(0x770EE) /**< \deprecated (SUPC_WUMR) Register MASK (Use SUPC_WUMR_Msk instead) */ +#define SUPC_WUMR_Msk _U_(0x770EE) /**< (SUPC_WUMR) Register Mask */ + +#define SUPC_WUMR_LPDBCEN_Pos 5 /**< (SUPC_WUMR Position) Low-power Debouncer Enable WKUPx */ +#define SUPC_WUMR_LPDBCEN_Msk (_U_(0x3) << SUPC_WUMR_LPDBCEN_Pos) /**< (SUPC_WUMR Mask) LPDBCEN */ +#define SUPC_WUMR_LPDBCEN(value) (SUPC_WUMR_LPDBCEN_Msk & ((value) << SUPC_WUMR_LPDBCEN_Pos)) + +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) (R/W 32) Supply Controller Wake-up Inputs Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WKUPEN0:1; /**< bit: 0 Wake-up Input Enable 0 to 0 */ + uint32_t WKUPEN1:1; /**< bit: 1 Wake-up Input Enable 0 to 1 */ + uint32_t WKUPEN2:1; /**< bit: 2 Wake-up Input Enable 0 to 2 */ + uint32_t WKUPEN3:1; /**< bit: 3 Wake-up Input Enable 0 to 3 */ + uint32_t WKUPEN4:1; /**< bit: 4 Wake-up Input Enable 0 to 4 */ + uint32_t WKUPEN5:1; /**< bit: 5 Wake-up Input Enable 0 to 5 */ + uint32_t WKUPEN6:1; /**< bit: 6 Wake-up Input Enable 0 to 6 */ + uint32_t WKUPEN7:1; /**< bit: 7 Wake-up Input Enable 0 to 7 */ + uint32_t WKUPEN8:1; /**< bit: 8 Wake-up Input Enable 0 to 8 */ + uint32_t WKUPEN9:1; /**< bit: 9 Wake-up Input Enable 0 to 9 */ + uint32_t WKUPEN10:1; /**< bit: 10 Wake-up Input Enable 0 to 10 */ + uint32_t WKUPEN11:1; /**< bit: 11 Wake-up Input Enable 0 to 11 */ + uint32_t WKUPEN12:1; /**< bit: 12 Wake-up Input Enable 0 to 12 */ + uint32_t WKUPEN13:1; /**< bit: 13 Wake-up Input Enable 0 to 13 */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t WKUPT0:1; /**< bit: 16 Wake-up Input Type 0 to 0 */ + uint32_t WKUPT1:1; /**< bit: 17 Wake-up Input Type 0 to 1 */ + uint32_t WKUPT2:1; /**< bit: 18 Wake-up Input Type 0 to 2 */ + uint32_t WKUPT3:1; /**< bit: 19 Wake-up Input Type 0 to 3 */ + uint32_t WKUPT4:1; /**< bit: 20 Wake-up Input Type 0 to 4 */ + uint32_t WKUPT5:1; /**< bit: 21 Wake-up Input Type 0 to 5 */ + uint32_t WKUPT6:1; /**< bit: 22 Wake-up Input Type 0 to 6 */ + uint32_t WKUPT7:1; /**< bit: 23 Wake-up Input Type 0 to 7 */ + uint32_t WKUPT8:1; /**< bit: 24 Wake-up Input Type 0 to 8 */ + uint32_t WKUPT9:1; /**< bit: 25 Wake-up Input Type 0 to 9 */ + uint32_t WKUPT10:1; /**< bit: 26 Wake-up Input Type 0 to 10 */ + uint32_t WKUPT11:1; /**< bit: 27 Wake-up Input Type 0 to 11 */ + uint32_t WKUPT12:1; /**< bit: 28 Wake-up Input Type 0 to 12 */ + uint32_t WKUPT13:1; /**< bit: 29 Wake-up Input Type 0 to 13 */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t WKUPEN:14; /**< bit: 0..13 Wake-up Input Enable x to x */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t WKUPT:14; /**< bit: 16..29 Wake-up Input Type x to x3 */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_WUIR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_WUIR_OFFSET (0x10) /**< (SUPC_WUIR) Supply Controller Wake-up Inputs Register Offset */ + +#define SUPC_WUIR_WKUPEN0_Pos 0 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Position */ +#define SUPC_WUIR_WKUPEN0_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Mask */ +#define SUPC_WUIR_WKUPEN0 SUPC_WUIR_WKUPEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN0_Msk instead */ +#define SUPC_WUIR_WKUPEN0_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN0_DISABLE (SUPC_WUIR_WKUPEN0_DISABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN0_ENABLE (SUPC_WUIR_WKUPEN0_ENABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN1_Pos 1 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Position */ +#define SUPC_WUIR_WKUPEN1_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Mask */ +#define SUPC_WUIR_WKUPEN1 SUPC_WUIR_WKUPEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN1_Msk instead */ +#define SUPC_WUIR_WKUPEN1_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1_DISABLE (SUPC_WUIR_WKUPEN1_DISABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN1_ENABLE (SUPC_WUIR_WKUPEN1_ENABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN2_Pos 2 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Position */ +#define SUPC_WUIR_WKUPEN2_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Mask */ +#define SUPC_WUIR_WKUPEN2 SUPC_WUIR_WKUPEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN2_Msk instead */ +#define SUPC_WUIR_WKUPEN2_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2_DISABLE (SUPC_WUIR_WKUPEN2_DISABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN2_ENABLE (SUPC_WUIR_WKUPEN2_ENABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN3_Pos 3 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Position */ +#define SUPC_WUIR_WKUPEN3_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Mask */ +#define SUPC_WUIR_WKUPEN3 SUPC_WUIR_WKUPEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN3_Msk instead */ +#define SUPC_WUIR_WKUPEN3_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3_DISABLE (SUPC_WUIR_WKUPEN3_DISABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN3_ENABLE (SUPC_WUIR_WKUPEN3_ENABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN4_Pos 4 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Position */ +#define SUPC_WUIR_WKUPEN4_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Mask */ +#define SUPC_WUIR_WKUPEN4 SUPC_WUIR_WKUPEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN4_Msk instead */ +#define SUPC_WUIR_WKUPEN4_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4_DISABLE (SUPC_WUIR_WKUPEN4_DISABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN4_ENABLE (SUPC_WUIR_WKUPEN4_ENABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN5_Pos 5 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Position */ +#define SUPC_WUIR_WKUPEN5_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Mask */ +#define SUPC_WUIR_WKUPEN5 SUPC_WUIR_WKUPEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN5_Msk instead */ +#define SUPC_WUIR_WKUPEN5_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5_DISABLE (SUPC_WUIR_WKUPEN5_DISABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN5_ENABLE (SUPC_WUIR_WKUPEN5_ENABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN6_Pos 6 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Position */ +#define SUPC_WUIR_WKUPEN6_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Mask */ +#define SUPC_WUIR_WKUPEN6 SUPC_WUIR_WKUPEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN6_Msk instead */ +#define SUPC_WUIR_WKUPEN6_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6_DISABLE (SUPC_WUIR_WKUPEN6_DISABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN6_ENABLE (SUPC_WUIR_WKUPEN6_ENABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN7_Pos 7 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Position */ +#define SUPC_WUIR_WKUPEN7_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Mask */ +#define SUPC_WUIR_WKUPEN7 SUPC_WUIR_WKUPEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN7_Msk instead */ +#define SUPC_WUIR_WKUPEN7_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7_DISABLE (SUPC_WUIR_WKUPEN7_DISABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN7_ENABLE (SUPC_WUIR_WKUPEN7_ENABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN8_Pos 8 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Position */ +#define SUPC_WUIR_WKUPEN8_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Mask */ +#define SUPC_WUIR_WKUPEN8 SUPC_WUIR_WKUPEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN8_Msk instead */ +#define SUPC_WUIR_WKUPEN8_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8_DISABLE (SUPC_WUIR_WKUPEN8_DISABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN8_ENABLE (SUPC_WUIR_WKUPEN8_ENABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN9_Pos 9 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Position */ +#define SUPC_WUIR_WKUPEN9_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Mask */ +#define SUPC_WUIR_WKUPEN9 SUPC_WUIR_WKUPEN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN9_Msk instead */ +#define SUPC_WUIR_WKUPEN9_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9_DISABLE (SUPC_WUIR_WKUPEN9_DISABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN9_ENABLE (SUPC_WUIR_WKUPEN9_ENABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN10_Pos 10 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Position */ +#define SUPC_WUIR_WKUPEN10_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Mask */ +#define SUPC_WUIR_WKUPEN10 SUPC_WUIR_WKUPEN10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN10_Msk instead */ +#define SUPC_WUIR_WKUPEN10_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10_DISABLE (SUPC_WUIR_WKUPEN10_DISABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN10_ENABLE (SUPC_WUIR_WKUPEN10_ENABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN11_Pos 11 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Position */ +#define SUPC_WUIR_WKUPEN11_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Mask */ +#define SUPC_WUIR_WKUPEN11 SUPC_WUIR_WKUPEN11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN11_Msk instead */ +#define SUPC_WUIR_WKUPEN11_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11_DISABLE (SUPC_WUIR_WKUPEN11_DISABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN11_ENABLE (SUPC_WUIR_WKUPEN11_ENABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN12_Pos 12 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Position */ +#define SUPC_WUIR_WKUPEN12_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Mask */ +#define SUPC_WUIR_WKUPEN12 SUPC_WUIR_WKUPEN12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN12_Msk instead */ +#define SUPC_WUIR_WKUPEN12_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12_DISABLE (SUPC_WUIR_WKUPEN12_DISABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN12_ENABLE (SUPC_WUIR_WKUPEN12_ENABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN13_Pos 13 /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Position */ +#define SUPC_WUIR_WKUPEN13_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Mask */ +#define SUPC_WUIR_WKUPEN13 SUPC_WUIR_WKUPEN13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN13_Msk instead */ +#define SUPC_WUIR_WKUPEN13_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13_DISABLE (SUPC_WUIR_WKUPEN13_DISABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN13_ENABLE (SUPC_WUIR_WKUPEN13_ENABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_Pos 16 /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Position */ +#define SUPC_WUIR_WKUPT0_Msk (_U_(0x1) << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Mask */ +#define SUPC_WUIR_WKUPT0 SUPC_WUIR_WKUPT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT0_Msk instead */ +#define SUPC_WUIR_WKUPT0_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW (SUPC_WUIR_WKUPT0_LOW_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_HIGH (SUPC_WUIR_WKUPT0_HIGH_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_Pos 17 /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Position */ +#define SUPC_WUIR_WKUPT1_Msk (_U_(0x1) << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Mask */ +#define SUPC_WUIR_WKUPT1 SUPC_WUIR_WKUPT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT1_Msk instead */ +#define SUPC_WUIR_WKUPT1_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW (SUPC_WUIR_WKUPT1_LOW_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_HIGH (SUPC_WUIR_WKUPT1_HIGH_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_Pos 18 /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Position */ +#define SUPC_WUIR_WKUPT2_Msk (_U_(0x1) << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Mask */ +#define SUPC_WUIR_WKUPT2 SUPC_WUIR_WKUPT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT2_Msk instead */ +#define SUPC_WUIR_WKUPT2_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW (SUPC_WUIR_WKUPT2_LOW_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_HIGH (SUPC_WUIR_WKUPT2_HIGH_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_Pos 19 /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Position */ +#define SUPC_WUIR_WKUPT3_Msk (_U_(0x1) << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Mask */ +#define SUPC_WUIR_WKUPT3 SUPC_WUIR_WKUPT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT3_Msk instead */ +#define SUPC_WUIR_WKUPT3_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW (SUPC_WUIR_WKUPT3_LOW_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_HIGH (SUPC_WUIR_WKUPT3_HIGH_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_Pos 20 /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Position */ +#define SUPC_WUIR_WKUPT4_Msk (_U_(0x1) << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Mask */ +#define SUPC_WUIR_WKUPT4 SUPC_WUIR_WKUPT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT4_Msk instead */ +#define SUPC_WUIR_WKUPT4_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW (SUPC_WUIR_WKUPT4_LOW_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_HIGH (SUPC_WUIR_WKUPT4_HIGH_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_Pos 21 /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Position */ +#define SUPC_WUIR_WKUPT5_Msk (_U_(0x1) << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Mask */ +#define SUPC_WUIR_WKUPT5 SUPC_WUIR_WKUPT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT5_Msk instead */ +#define SUPC_WUIR_WKUPT5_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW (SUPC_WUIR_WKUPT5_LOW_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_HIGH (SUPC_WUIR_WKUPT5_HIGH_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_Pos 22 /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Position */ +#define SUPC_WUIR_WKUPT6_Msk (_U_(0x1) << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Mask */ +#define SUPC_WUIR_WKUPT6 SUPC_WUIR_WKUPT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT6_Msk instead */ +#define SUPC_WUIR_WKUPT6_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW (SUPC_WUIR_WKUPT6_LOW_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_HIGH (SUPC_WUIR_WKUPT6_HIGH_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_Pos 23 /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Position */ +#define SUPC_WUIR_WKUPT7_Msk (_U_(0x1) << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Mask */ +#define SUPC_WUIR_WKUPT7 SUPC_WUIR_WKUPT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT7_Msk instead */ +#define SUPC_WUIR_WKUPT7_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW (SUPC_WUIR_WKUPT7_LOW_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_HIGH (SUPC_WUIR_WKUPT7_HIGH_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_Pos 24 /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Position */ +#define SUPC_WUIR_WKUPT8_Msk (_U_(0x1) << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Mask */ +#define SUPC_WUIR_WKUPT8 SUPC_WUIR_WKUPT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT8_Msk instead */ +#define SUPC_WUIR_WKUPT8_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW (SUPC_WUIR_WKUPT8_LOW_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_HIGH (SUPC_WUIR_WKUPT8_HIGH_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_Pos 25 /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Position */ +#define SUPC_WUIR_WKUPT9_Msk (_U_(0x1) << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Mask */ +#define SUPC_WUIR_WKUPT9 SUPC_WUIR_WKUPT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT9_Msk instead */ +#define SUPC_WUIR_WKUPT9_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW (SUPC_WUIR_WKUPT9_LOW_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_HIGH (SUPC_WUIR_WKUPT9_HIGH_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_Pos 26 /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Position */ +#define SUPC_WUIR_WKUPT10_Msk (_U_(0x1) << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Mask */ +#define SUPC_WUIR_WKUPT10 SUPC_WUIR_WKUPT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT10_Msk instead */ +#define SUPC_WUIR_WKUPT10_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW (SUPC_WUIR_WKUPT10_LOW_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_HIGH (SUPC_WUIR_WKUPT10_HIGH_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_Pos 27 /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Position */ +#define SUPC_WUIR_WKUPT11_Msk (_U_(0x1) << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Mask */ +#define SUPC_WUIR_WKUPT11 SUPC_WUIR_WKUPT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT11_Msk instead */ +#define SUPC_WUIR_WKUPT11_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW (SUPC_WUIR_WKUPT11_LOW_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_HIGH (SUPC_WUIR_WKUPT11_HIGH_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_Pos 28 /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Position */ +#define SUPC_WUIR_WKUPT12_Msk (_U_(0x1) << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Mask */ +#define SUPC_WUIR_WKUPT12 SUPC_WUIR_WKUPT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT12_Msk instead */ +#define SUPC_WUIR_WKUPT12_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW (SUPC_WUIR_WKUPT12_LOW_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_HIGH (SUPC_WUIR_WKUPT12_HIGH_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_Pos 29 /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Position */ +#define SUPC_WUIR_WKUPT13_Msk (_U_(0x1) << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Mask */ +#define SUPC_WUIR_WKUPT13 SUPC_WUIR_WKUPT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT13_Msk instead */ +#define SUPC_WUIR_WKUPT13_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW (SUPC_WUIR_WKUPT13_LOW_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_HIGH (SUPC_WUIR_WKUPT13_HIGH_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_MASK _U_(0x3FFF3FFF) /**< \deprecated (SUPC_WUIR) Register MASK (Use SUPC_WUIR_Msk instead) */ +#define SUPC_WUIR_Msk _U_(0x3FFF3FFF) /**< (SUPC_WUIR) Register Mask */ + +#define SUPC_WUIR_WKUPEN_Pos 0 /**< (SUPC_WUIR Position) Wake-up Input Enable x to x */ +#define SUPC_WUIR_WKUPEN_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPEN_Pos) /**< (SUPC_WUIR Mask) WKUPEN */ +#define SUPC_WUIR_WKUPEN(value) (SUPC_WUIR_WKUPEN_Msk & ((value) << SUPC_WUIR_WKUPEN_Pos)) +#define SUPC_WUIR_WKUPT_Pos 16 /**< (SUPC_WUIR Position) Wake-up Input Type x to x3 */ +#define SUPC_WUIR_WKUPT_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPT_Pos) /**< (SUPC_WUIR Mask) WKUPT */ +#define SUPC_WUIR_WKUPT(value) (SUPC_WUIR_WKUPT_Msk & ((value) << SUPC_WUIR_WKUPT_Pos)) + +/* -------- SUPC_SR : (SUPC Offset: 0x14) (R/ 32) Supply Controller Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t WKUPS:1; /**< bit: 1 WKUP Wake-up Status (cleared on read) */ + uint32_t SMWS:1; /**< bit: 2 Supply Monitor Detection Wake-up Status (cleared on read) */ + uint32_t BODRSTS:1; /**< bit: 3 Brownout Detector Reset Status (cleared on read) */ + uint32_t SMRSTS:1; /**< bit: 4 Supply Monitor Reset Status (cleared on read) */ + uint32_t SMS:1; /**< bit: 5 Supply Monitor Status (cleared on read) */ + uint32_t SMOS:1; /**< bit: 6 Supply Monitor Output Status */ + uint32_t OSCSEL:1; /**< bit: 7 32-kHz Oscillator Selection Status */ + uint32_t :5; /**< bit: 8..12 Reserved */ + uint32_t LPDBCS0:1; /**< bit: 13 Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ + uint32_t LPDBCS1:1; /**< bit: 14 Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t WKUPIS0:1; /**< bit: 16 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS1:1; /**< bit: 17 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS2:1; /**< bit: 18 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS3:1; /**< bit: 19 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS4:1; /**< bit: 20 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS5:1; /**< bit: 21 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS6:1; /**< bit: 22 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS7:1; /**< bit: 23 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS8:1; /**< bit: 24 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS9:1; /**< bit: 25 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS10:1; /**< bit: 26 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS11:1; /**< bit: 27 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS12:1; /**< bit: 28 WKUPx Input Status (cleared on read) */ + uint32_t WKUPIS13:1; /**< bit: 29 WKUPx Input Status (cleared on read) */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t LPDBCS:2; /**< bit: 13..14 Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t WKUPIS:14; /**< bit: 16..29 WKUPx Input Status (cleared on read) */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} SUPC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SUPC_SR_OFFSET (0x14) /**< (SUPC_SR) Supply Controller Status Register Offset */ + +#define SUPC_SR_WKUPS_Pos 1 /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Position */ +#define SUPC_SR_WKUPS_Msk (_U_(0x1) << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_WKUPS SUPC_SR_WKUPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPS_Msk instead */ +#define SUPC_SR_WKUPS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_NO (SUPC_SR_WKUPS_NO_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPS_PRESENT (SUPC_SR_WKUPS_PRESENT_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_Pos 2 /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Position */ +#define SUPC_SR_SMWS_Msk (_U_(0x1) << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_SMWS SUPC_SR_SMWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMWS_Msk instead */ +#define SUPC_SR_SMWS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_NO (SUPC_SR_SMWS_NO_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_PRESENT (SUPC_SR_SMWS_PRESENT_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_Pos 3 /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Position */ +#define SUPC_SR_BODRSTS_Msk (_U_(0x1) << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Mask */ +#define SUPC_SR_BODRSTS SUPC_SR_BODRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_BODRSTS_Msk instead */ +#define SUPC_SR_BODRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_NO (SUPC_SR_BODRSTS_NO_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_PRESENT (SUPC_SR_BODRSTS_PRESENT_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_Pos 4 /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Position */ +#define SUPC_SR_SMRSTS_Msk (_U_(0x1) << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Mask */ +#define SUPC_SR_SMRSTS SUPC_SR_SMRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMRSTS_Msk instead */ +#define SUPC_SR_SMRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_NO (SUPC_SR_SMRSTS_NO_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_PRESENT (SUPC_SR_SMRSTS_PRESENT_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMS_Pos 5 /**< (SUPC_SR) Supply Monitor Status (cleared on read) Position */ +#define SUPC_SR_SMS_Msk (_U_(0x1) << SUPC_SR_SMS_Pos) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Mask */ +#define SUPC_SR_SMS SUPC_SR_SMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMS_Msk instead */ +#define SUPC_SR_SMS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_NO (SUPC_SR_SMS_NO_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMS_PRESENT (SUPC_SR_SMS_PRESENT_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMOS_Pos 6 /**< (SUPC_SR) Supply Monitor Output Status Position */ +#define SUPC_SR_SMOS_Msk (_U_(0x1) << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) Supply Monitor Output Status Mask */ +#define SUPC_SR_SMOS SUPC_SR_SMOS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMOS_Msk instead */ +#define SUPC_SR_SMOS_HIGH_Val _U_(0x0) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW_Val _U_(0x1) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_HIGH (SUPC_SR_SMOS_HIGH_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. Position */ +#define SUPC_SR_SMOS_LOW (SUPC_SR_SMOS_LOW_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. Position */ +#define SUPC_SR_OSCSEL_Pos 7 /**< (SUPC_SR) 32-kHz Oscillator Selection Status Position */ +#define SUPC_SR_OSCSEL_Msk (_U_(0x1) << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Mask */ +#define SUPC_SR_OSCSEL SUPC_SR_OSCSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_OSCSEL_Msk instead */ +#define SUPC_SR_OSCSEL_RC_Val _U_(0x0) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST_Val _U_(0x1) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_OSCSEL_RC (SUPC_SR_OSCSEL_RC_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. Position */ +#define SUPC_SR_OSCSEL_CRYST (SUPC_SR_OSCSEL_CRYST_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. Position */ +#define SUPC_SR_LPDBCS0_Pos 13 /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Position */ +#define SUPC_SR_LPDBCS0_Msk (_U_(0x1) << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS0 SUPC_SR_LPDBCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS0_Msk instead */ +#define SUPC_SR_LPDBCS0_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_NO (SUPC_SR_LPDBCS0_NO_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS0_PRESENT (SUPC_SR_LPDBCS0_PRESENT_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_Pos 14 /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Position */ +#define SUPC_SR_LPDBCS1_Msk (_U_(0x1) << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS1 SUPC_SR_LPDBCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS1_Msk instead */ +#define SUPC_SR_LPDBCS1_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_NO (SUPC_SR_LPDBCS1_NO_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_PRESENT (SUPC_SR_LPDBCS1_PRESENT_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS0_Pos 16 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS0_Msk (_U_(0x1) << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS0 SUPC_SR_WKUPIS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS0_Msk instead */ +#define SUPC_SR_WKUPIS0_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0_DIS (SUPC_SR_WKUPIS0_DIS_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS0_EN (SUPC_SR_WKUPIS0_EN_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS1_Pos 17 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS1_Msk (_U_(0x1) << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS1 SUPC_SR_WKUPIS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS1_Msk instead */ +#define SUPC_SR_WKUPIS1_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1_DIS (SUPC_SR_WKUPIS1_DIS_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS1_EN (SUPC_SR_WKUPIS1_EN_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS2_Pos 18 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS2_Msk (_U_(0x1) << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS2 SUPC_SR_WKUPIS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS2_Msk instead */ +#define SUPC_SR_WKUPIS2_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2_DIS (SUPC_SR_WKUPIS2_DIS_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS2_EN (SUPC_SR_WKUPIS2_EN_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS3_Pos 19 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS3_Msk (_U_(0x1) << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS3 SUPC_SR_WKUPIS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS3_Msk instead */ +#define SUPC_SR_WKUPIS3_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3_DIS (SUPC_SR_WKUPIS3_DIS_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS3_EN (SUPC_SR_WKUPIS3_EN_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS4_Pos 20 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS4_Msk (_U_(0x1) << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS4 SUPC_SR_WKUPIS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS4_Msk instead */ +#define SUPC_SR_WKUPIS4_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4_DIS (SUPC_SR_WKUPIS4_DIS_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS4_EN (SUPC_SR_WKUPIS4_EN_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS5_Pos 21 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS5_Msk (_U_(0x1) << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS5 SUPC_SR_WKUPIS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS5_Msk instead */ +#define SUPC_SR_WKUPIS5_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5_DIS (SUPC_SR_WKUPIS5_DIS_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS5_EN (SUPC_SR_WKUPIS5_EN_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS6_Pos 22 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS6_Msk (_U_(0x1) << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS6 SUPC_SR_WKUPIS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS6_Msk instead */ +#define SUPC_SR_WKUPIS6_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6_DIS (SUPC_SR_WKUPIS6_DIS_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS6_EN (SUPC_SR_WKUPIS6_EN_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS7_Pos 23 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS7_Msk (_U_(0x1) << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS7 SUPC_SR_WKUPIS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS7_Msk instead */ +#define SUPC_SR_WKUPIS7_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7_DIS (SUPC_SR_WKUPIS7_DIS_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS7_EN (SUPC_SR_WKUPIS7_EN_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS8_Pos 24 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS8_Msk (_U_(0x1) << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS8 SUPC_SR_WKUPIS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS8_Msk instead */ +#define SUPC_SR_WKUPIS8_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8_DIS (SUPC_SR_WKUPIS8_DIS_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS8_EN (SUPC_SR_WKUPIS8_EN_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS9_Pos 25 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS9_Msk (_U_(0x1) << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS9 SUPC_SR_WKUPIS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS9_Msk instead */ +#define SUPC_SR_WKUPIS9_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9_DIS (SUPC_SR_WKUPIS9_DIS_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS9_EN (SUPC_SR_WKUPIS9_EN_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS10_Pos 26 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS10_Msk (_U_(0x1) << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS10 SUPC_SR_WKUPIS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS10_Msk instead */ +#define SUPC_SR_WKUPIS10_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10_DIS (SUPC_SR_WKUPIS10_DIS_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS10_EN (SUPC_SR_WKUPIS10_EN_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS11_Pos 27 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS11_Msk (_U_(0x1) << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS11 SUPC_SR_WKUPIS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS11_Msk instead */ +#define SUPC_SR_WKUPIS11_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11_DIS (SUPC_SR_WKUPIS11_DIS_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS11_EN (SUPC_SR_WKUPIS11_EN_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS12_Pos 28 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS12_Msk (_U_(0x1) << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS12 SUPC_SR_WKUPIS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS12_Msk instead */ +#define SUPC_SR_WKUPIS12_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12_DIS (SUPC_SR_WKUPIS12_DIS_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS12_EN (SUPC_SR_WKUPIS12_EN_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS13_Pos 29 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS13_Msk (_U_(0x1) << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS13 SUPC_SR_WKUPIS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS13_Msk instead */ +#define SUPC_SR_WKUPIS13_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13_DIS (SUPC_SR_WKUPIS13_DIS_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS13_EN (SUPC_SR_WKUPIS13_EN_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_MASK _U_(0x3FFF60FE) /**< \deprecated (SUPC_SR) Register MASK (Use SUPC_SR_Msk instead) */ +#define SUPC_SR_Msk _U_(0x3FFF60FE) /**< (SUPC_SR) Register Mask */ + +#define SUPC_SR_LPDBCS_Pos 13 /**< (SUPC_SR Position) Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */ +#define SUPC_SR_LPDBCS_Msk (_U_(0x3) << SUPC_SR_LPDBCS_Pos) /**< (SUPC_SR Mask) LPDBCS */ +#define SUPC_SR_LPDBCS(value) (SUPC_SR_LPDBCS_Msk & ((value) << SUPC_SR_LPDBCS_Pos)) +#define SUPC_SR_WKUPIS_Pos 16 /**< (SUPC_SR Position) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS_Msk (_U_(0x3FFF) << SUPC_SR_WKUPIS_Pos) /**< (SUPC_SR Mask) WKUPIS */ +#define SUPC_SR_WKUPIS(value) (SUPC_SR_WKUPIS_Msk & ((value) << SUPC_SR_WKUPIS_Pos)) + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief SUPC hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< (SUPC Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< (SUPC Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< (SUPC Offset: 0x14) Supply Controller Status Register */ +} Supc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief SUPC hardware registers */ +typedef struct { + __O SUPC_CR_Type SUPC_CR; /**< Offset: 0x00 ( /W 32) Supply Controller Control Register */ + __IO SUPC_SMMR_Type SUPC_SMMR; /**< Offset: 0x04 (R/W 32) Supply Controller Supply Monitor Mode Register */ + __IO SUPC_MR_Type SUPC_MR; /**< Offset: 0x08 (R/W 32) Supply Controller Mode Register */ + __IO SUPC_WUMR_Type SUPC_WUMR; /**< Offset: 0x0C (R/W 32) Supply Controller Wake-up Mode Register */ + __IO SUPC_WUIR_Type SUPC_WUIR; /**< Offset: 0x10 (R/W 32) Supply Controller Wake-up Inputs Register */ + __I SUPC_SR_Type SUPC_SR; /**< Offset: 0x14 (R/ 32) Supply Controller Status Register */ +} Supc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Supply Controller */ + +#endif /* _SAME70_SUPC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/tc.h b/bsp/microchip/same70/bsp/same70b/include/component/tc.h new file mode 100644 index 0000000000..9bf07cd199 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/tc.h @@ -0,0 +1,1153 @@ +/** + * \file + * + * \brief Component description for TC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TC_COMPONENT_H_ +#define _SAME70_TC_COMPONENT_H_ +#define _SAME70_TC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Timer Counter + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define TC_6082 /**< (TC) Module ID */ +#define REV_TC ZL /**< (TC) Module revision */ + +/* -------- TC_CCR : (TC Offset: 0x00) (/W 32) Channel Control Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CLKEN:1; /**< bit: 0 Counter Clock Enable Command */ + uint32_t CLKDIS:1; /**< bit: 1 Counter Clock Disable Command */ + uint32_t SWTRG:1; /**< bit: 2 Software Trigger Command */ + uint32_t :29; /**< bit: 3..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_CCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CCR_OFFSET (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */ + +#define TC_CCR_CLKEN_Pos 0 /**< (TC_CCR) Counter Clock Enable Command Position */ +#define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */ +#define TC_CCR_CLKEN TC_CCR_CLKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKEN_Msk instead */ +#define TC_CCR_CLKDIS_Pos 1 /**< (TC_CCR) Counter Clock Disable Command Position */ +#define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */ +#define TC_CCR_CLKDIS TC_CCR_CLKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_CLKDIS_Msk instead */ +#define TC_CCR_SWTRG_Pos 2 /**< (TC_CCR) Software Trigger Command Position */ +#define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */ +#define TC_CCR_SWTRG TC_CCR_SWTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CCR_SWTRG_Msk instead */ +#define TC_CCR_MASK _U_(0x07) /**< \deprecated (TC_CCR) Register MASK (Use TC_CCR_Msk instead) */ +#define TC_CCR_Msk _U_(0x07) /**< (TC_CCR) Register Mask */ + + +/* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TCCLKS:3; /**< bit: 0..2 Clock Selection */ + uint32_t CLKI:1; /**< bit: 3 Clock Invert */ + uint32_t BURST:2; /**< bit: 4..5 Burst Signal Selection */ + uint32_t :9; /**< bit: 6..14 Reserved */ + uint32_t WAVE:1; /**< bit: 15 Waveform Mode */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CAPTURE mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t LDBSTOP:1; /**< bit: 6 Counter Clock Stopped with RB Loading */ + uint32_t LDBDIS:1; /**< bit: 7 Counter Clock Disable with RB Loading */ + uint32_t ETRGEDG:2; /**< bit: 8..9 External Trigger Edge Selection */ + uint32_t ABETRG:1; /**< bit: 10 TIOAx or TIOBx External Trigger Selection */ + uint32_t :3; /**< bit: 11..13 Reserved */ + uint32_t CPCTRG:1; /**< bit: 14 RC Compare Trigger Enable */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t LDRA:2; /**< bit: 16..17 RA Loading Edge Selection */ + uint32_t LDRB:2; /**< bit: 18..19 RB Loading Edge Selection */ + uint32_t SBSMPLR:3; /**< bit: 20..22 Loading Edge Subsampling Ratio */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } CAPTURE; /**< Structure used for CAPTURE mode access */ + struct { // WAVEFORM mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t CPCSTOP:1; /**< bit: 6 Counter Clock Stopped with RC Compare */ + uint32_t CPCDIS:1; /**< bit: 7 Counter Clock Disable with RC Loading */ + uint32_t EEVTEDG:2; /**< bit: 8..9 External Event Edge Selection */ + uint32_t EEVT:2; /**< bit: 10..11 External Event Selection */ + uint32_t ENETRG:1; /**< bit: 12 External Event Trigger Enable */ + uint32_t WAVSEL:2; /**< bit: 13..14 Waveform Selection */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t ACPA:2; /**< bit: 16..17 RA Compare Effect on TIOAx */ + uint32_t ACPC:2; /**< bit: 18..19 RC Compare Effect on TIOAx */ + uint32_t AEEVT:2; /**< bit: 20..21 External Event Effect on TIOAx */ + uint32_t ASWTRG:2; /**< bit: 22..23 Software Trigger Effect on TIOAx */ + uint32_t BCPB:2; /**< bit: 24..25 RB Compare Effect on TIOBx */ + uint32_t BCPC:2; /**< bit: 26..27 RC Compare Effect on TIOBx */ + uint32_t BEEVT:2; /**< bit: 28..29 External Event Effect on TIOBx */ + uint32_t BSWTRG:2; /**< bit: 30..31 Software Trigger Effect on TIOBx */ + } WAVEFORM; /**< Structure used for WAVEFORM mode access */ + uint32_t reg; /**< Type used for register access */ +} TC_CMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CMR_OFFSET (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */ + +#define TC_CMR_TCCLKS_Pos 0 /**< (TC_CMR) Clock Selection Position */ +#define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */ +#define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) +#define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */ +#define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */ +#define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */ +#define TC_CMR_CLKI_Pos 3 /**< (TC_CMR) Clock Invert Position */ +#define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */ +#define TC_CMR_CLKI TC_CMR_CLKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CLKI_Msk instead */ +#define TC_CMR_BURST_Pos 4 /**< (TC_CMR) Burst Signal Selection Position */ +#define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */ +#define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) +#define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ +#define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */ +#define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ +#define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */ +#define TC_CMR_MASK _U_(0x803F) /**< \deprecated (TC_CMR) Register MASK (Use TC_CMR_Msk instead) */ +#define TC_CMR_Msk _U_(0x803F) /**< (TC_CMR) Register Mask */ + +/* CAPTURE mode */ +#define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ +#define TC_CMR_CAPTURE_LDBSTOP_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ +#define TC_CMR_CAPTURE_LDBSTOP TC_CMR_CAPTURE_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBSTOP_Msk instead */ +#define TC_CMR_CAPTURE_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ +#define TC_CMR_CAPTURE_LDBDIS_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ +#define TC_CMR_CAPTURE_LDBDIS TC_CMR_CAPTURE_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_LDBDIS_Msk instead */ +#define TC_CMR_CAPTURE_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ +#define TC_CMR_CAPTURE_ETRGEDG_Msk (_U_(0x3) << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ +#define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) +#define TC_CMR_CAPTURE_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE The clock is not gated by an external signal. */ +#define TC_CMR_CAPTURE_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge */ +#define TC_CMR_CAPTURE_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge */ +#define TC_CMR_CAPTURE_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge */ +#define TC_CMR_CAPTURE_ETRGEDG_NONE (TC_CMR_CAPTURE_ETRGEDG_NONE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_CAPTURE_ETRGEDG_RISING (TC_CMR_CAPTURE_ETRGEDG_RISING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_CAPTURE_ETRGEDG_FALLING (TC_CMR_CAPTURE_ETRGEDG_FALLING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_CAPTURE_ETRGEDG_EDGE (TC_CMR_CAPTURE_ETRGEDG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ +#define TC_CMR_CAPTURE_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ +#define TC_CMR_CAPTURE_ABETRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ +#define TC_CMR_CAPTURE_ABETRG TC_CMR_CAPTURE_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_ABETRG_Msk instead */ +#define TC_CMR_CAPTURE_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ +#define TC_CMR_CAPTURE_CPCTRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ +#define TC_CMR_CAPTURE_CPCTRG TC_CMR_CAPTURE_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CAPTURE_CPCTRG_Msk instead */ +#define TC_CMR_CAPTURE_LDRA_Pos 16 /**< (TC_CMR) RA Loading Edge Selection Position */ +#define TC_CMR_CAPTURE_LDRA_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ +#define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) +#define TC_CMR_CAPTURE_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ +#define TC_CMR_CAPTURE_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_NONE (TC_CMR_CAPTURE_LDRA_NONE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_CAPTURE_LDRA_RISING (TC_CMR_CAPTURE_LDRA_RISING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRA_FALLING (TC_CMR_CAPTURE_LDRA_FALLING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRA_EDGE (TC_CMR_CAPTURE_LDRA_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_Pos 18 /**< (TC_CMR) RB Loading Edge Selection Position */ +#define TC_CMR_CAPTURE_LDRB_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ +#define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) +#define TC_CMR_CAPTURE_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE None */ +#define TC_CMR_CAPTURE_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) CAPTURE Rising edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) CAPTURE Falling edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) CAPTURE Each edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_NONE (TC_CMR_CAPTURE_LDRB_NONE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_CAPTURE_LDRB_RISING (TC_CMR_CAPTURE_LDRB_RISING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_FALLING (TC_CMR_CAPTURE_LDRB_FALLING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_EDGE (TC_CMR_CAPTURE_LDRB_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_CAPTURE_SBSMPLR_Pos 20 /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ +#define TC_CMR_CAPTURE_SBSMPLR_Msk (_U_(0x7) << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ +#define TC_CMR_CAPTURE_SBSMPLR(value) (TC_CMR_CAPTURE_SBSMPLR_Msk & ((value) << TC_CMR_CAPTURE_SBSMPLR_Pos)) +#define TC_CMR_CAPTURE_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) CAPTURE Load a Capture Register each selected edge */ +#define TC_CMR_CAPTURE_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) CAPTURE Load a Capture Register every 2 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) CAPTURE Load a Capture Register every 4 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) CAPTURE Load a Capture Register every 8 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) CAPTURE Load a Capture Register every 16 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_ONE (TC_CMR_CAPTURE_SBSMPLR_ONE_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ +#define TC_CMR_CAPTURE_SBSMPLR_HALF (TC_CMR_CAPTURE_SBSMPLR_HALF_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_FOURTH (TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_EIGHTH (TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH (TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ +#define TC_CMR_CAPTURE_MASK _U_(0x7F47C0) /**< \deprecated (TC_CMR_CAPTURE) Register MASK (Use TC_CMR_CAPTURE_Msk instead) */ +#define TC_CMR_CAPTURE_Msk _U_(0x7F47C0) /**< (TC_CMR_CAPTURE) Register Mask */ + +/* WAVEFORM mode */ +#define TC_CMR_WAVEFORM_CPCSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RC Compare Position */ +#define TC_CMR_WAVEFORM_CPCSTOP_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RC Compare Mask */ +#define TC_CMR_WAVEFORM_CPCSTOP TC_CMR_WAVEFORM_CPCSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCSTOP_Msk instead */ +#define TC_CMR_WAVEFORM_CPCDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RC Loading Position */ +#define TC_CMR_WAVEFORM_CPCDIS_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RC Loading Mask */ +#define TC_CMR_WAVEFORM_CPCDIS TC_CMR_WAVEFORM_CPCDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_CPCDIS_Msk instead */ +#define TC_CMR_WAVEFORM_EEVTEDG_Pos 8 /**< (TC_CMR) External Event Edge Selection Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) External Event Edge Selection Mask */ +#define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) +#define TC_CMR_WAVEFORM_EEVTEDG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM None */ +#define TC_CMR_WAVEFORM_EEVTEDG_RISING_Val _U_(0x1) /**< (TC_CMR) WAVEFORM Rising edge */ +#define TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) WAVEFORM Falling edge */ +#define TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM Each edges */ +#define TC_CMR_WAVEFORM_EEVTEDG_NONE (TC_CMR_WAVEFORM_EEVTEDG_NONE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_RISING (TC_CMR_WAVEFORM_EEVTEDG_RISING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_FALLING (TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Each edges Position */ +#define TC_CMR_WAVEFORM_EEVT_Pos 10 /**< (TC_CMR) External Event Selection Position */ +#define TC_CMR_WAVEFORM_EEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) External Event Selection Mask */ +#define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) +#define TC_CMR_WAVEFORM_EEVT_TIOB_Val _U_(0x0) /**< (TC_CMR) WAVEFORM TIOB */ +#define TC_CMR_WAVEFORM_EEVT_XC0_Val _U_(0x1) /**< (TC_CMR) WAVEFORM XC0 */ +#define TC_CMR_WAVEFORM_EEVT_XC1_Val _U_(0x2) /**< (TC_CMR) WAVEFORM XC1 */ +#define TC_CMR_WAVEFORM_EEVT_XC2_Val _U_(0x3) /**< (TC_CMR) WAVEFORM XC2 */ +#define TC_CMR_WAVEFORM_EEVT_TIOB (TC_CMR_WAVEFORM_EEVT_TIOB_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) TIOB Position */ +#define TC_CMR_WAVEFORM_EEVT_XC0 (TC_CMR_WAVEFORM_EEVT_XC0_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC0 Position */ +#define TC_CMR_WAVEFORM_EEVT_XC1 (TC_CMR_WAVEFORM_EEVT_XC1_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC1 Position */ +#define TC_CMR_WAVEFORM_EEVT_XC2 (TC_CMR_WAVEFORM_EEVT_XC2_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC2 Position */ +#define TC_CMR_WAVEFORM_ENETRG_Pos 12 /**< (TC_CMR) External Event Trigger Enable Position */ +#define TC_CMR_WAVEFORM_ENETRG_Msk (_U_(0x1) << TC_CMR_WAVEFORM_ENETRG_Pos) /**< (TC_CMR) External Event Trigger Enable Mask */ +#define TC_CMR_WAVEFORM_ENETRG TC_CMR_WAVEFORM_ENETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVEFORM_ENETRG_Msk instead */ +#define TC_CMR_WAVEFORM_WAVSEL_Pos 13 /**< (TC_CMR) Waveform Selection Position */ +#define TC_CMR_WAVEFORM_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) Waveform Selection Mask */ +#define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) +#define TC_CMR_WAVEFORM_WAVSEL_UP_Val _U_(0x0) /**< (TC_CMR) WAVEFORM UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val _U_(0x1) /**< (TC_CMR) WAVEFORM UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val _U_(0x2) /**< (TC_CMR) WAVEFORM UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val _U_(0x3) /**< (TC_CMR) WAVEFORM UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_ACPA_Pos 16 /**< (TC_CMR) RA Compare Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ACPA_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) RA Compare Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) +#define TC_CMR_WAVEFORM_ACPA_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_ACPA_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_ACPA_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_ACPC_Pos 18 /**< (TC_CMR) RC Compare Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ACPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) +#define TC_CMR_WAVEFORM_ACPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_ACPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_ACPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_AEEVT_Pos 20 /**< (TC_CMR) External Event Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_AEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) +#define TC_CMR_WAVEFORM_AEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_AEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_ASWTRG_Pos 22 /**< (TC_CMR) Software Trigger Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ASWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) +#define TC_CMR_WAVEFORM_ASWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_ASWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BCPB_Pos 24 /**< (TC_CMR) RB Compare Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BCPB_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) RB Compare Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) +#define TC_CMR_WAVEFORM_BCPB_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_BCPB_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_BCPB_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BCPC_Pos 26 /**< (TC_CMR) RC Compare Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BCPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) +#define TC_CMR_WAVEFORM_BCPC_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_BCPC_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_BCPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BEEVT_Pos 28 /**< (TC_CMR) External Event Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) +#define TC_CMR_WAVEFORM_BEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_BEEVT_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BSWTRG_Pos 30 /**< (TC_CMR) Software Trigger Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BSWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) +#define TC_CMR_WAVEFORM_BSWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) WAVEFORM NONE */ +#define TC_CMR_WAVEFORM_BSWTRG_SET_Val _U_(0x1) /**< (TC_CMR) WAVEFORM SET */ +#define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) WAVEFORM CLEAR */ +#define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) WAVEFORM TOGGLE */ +#define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_MASK _U_(0xFFFF7FC0) /**< \deprecated (TC_CMR_WAVEFORM) Register MASK (Use TC_CMR_WAVEFORM_Msk instead) */ +#define TC_CMR_WAVEFORM_Msk _U_(0xFFFF7FC0) /**< (TC_CMR_WAVEFORM) Register Mask */ + + +/* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t GCEN:1; /**< bit: 0 Gray Count Enable */ + uint32_t DOWN:1; /**< bit: 1 Down Count */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_SMMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_SMMR_OFFSET (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */ + +#define TC_SMMR_GCEN_Pos 0 /**< (TC_SMMR) Gray Count Enable Position */ +#define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */ +#define TC_SMMR_GCEN TC_SMMR_GCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_GCEN_Msk instead */ +#define TC_SMMR_DOWN_Pos 1 /**< (TC_SMMR) Down Count Position */ +#define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */ +#define TC_SMMR_DOWN TC_SMMR_DOWN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SMMR_DOWN_Msk instead */ +#define TC_SMMR_MASK _U_(0x03) /**< \deprecated (TC_SMMR) Register MASK (Use TC_SMMR_Msk instead) */ +#define TC_SMMR_Msk _U_(0x03) /**< (TC_SMMR) Register Mask */ + + +/* -------- TC_RAB : (TC Offset: 0x0c) (R/ 32) Register AB (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RAB:32; /**< bit: 0..31 Register A or Register B */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_RAB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_RAB_OFFSET (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */ + +#define TC_RAB_RAB_Pos 0 /**< (TC_RAB) Register A or Register B Position */ +#define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */ +#define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos)) +#define TC_RAB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RAB) Register MASK (Use TC_RAB_Msk instead) */ +#define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */ + + +/* -------- TC_CV : (TC Offset: 0x10) (R/ 32) Counter Value (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CV:32; /**< bit: 0..31 Counter Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_CV_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CV_OFFSET (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */ + +#define TC_CV_CV_Pos 0 /**< (TC_CV) Counter Value Position */ +#define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */ +#define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) +#define TC_CV_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_CV) Register MASK (Use TC_CV_Msk instead) */ +#define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */ + + +/* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RA:32; /**< bit: 0..31 Register A */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_RA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_RA_OFFSET (0x14) /**< (TC_RA) Register A (channel = 0) Offset */ + +#define TC_RA_RA_Pos 0 /**< (TC_RA) Register A Position */ +#define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */ +#define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) +#define TC_RA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RA) Register MASK (Use TC_RA_Msk instead) */ +#define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */ + + +/* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RB:32; /**< bit: 0..31 Register B */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_RB_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_RB_OFFSET (0x18) /**< (TC_RB) Register B (channel = 0) Offset */ + +#define TC_RB_RB_Pos 0 /**< (TC_RB) Register B Position */ +#define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */ +#define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) +#define TC_RB_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RB) Register MASK (Use TC_RB_Msk instead) */ +#define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */ + + +/* -------- TC_RC : (TC Offset: 0x1c) (R/W 32) Register C (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RC:32; /**< bit: 0..31 Register C */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_RC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_RC_OFFSET (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */ + +#define TC_RC_RC_Pos 0 /**< (TC_RC) Register C Position */ +#define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */ +#define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) +#define TC_RC_MASK _U_(0xFFFFFFFF) /**< \deprecated (TC_RC) Register MASK (Use TC_RC_Msk instead) */ +#define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */ + + +/* -------- TC_SR : (TC Offset: 0x20) (R/ 32) Status Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COVFS:1; /**< bit: 0 Counter Overflow Status (cleared on read) */ + uint32_t LOVRS:1; /**< bit: 1 Load Overrun Status (cleared on read) */ + uint32_t CPAS:1; /**< bit: 2 RA Compare Status (cleared on read) */ + uint32_t CPBS:1; /**< bit: 3 RB Compare Status (cleared on read) */ + uint32_t CPCS:1; /**< bit: 4 RC Compare Status (cleared on read) */ + uint32_t LDRAS:1; /**< bit: 5 RA Loading Status (cleared on read) */ + uint32_t LDRBS:1; /**< bit: 6 RB Loading Status (cleared on read) */ + uint32_t ETRGS:1; /**< bit: 7 External Trigger Status (cleared on read) */ + uint32_t :8; /**< bit: 8..15 Reserved */ + uint32_t CLKSTA:1; /**< bit: 16 Clock Enabling Status */ + uint32_t MTIOA:1; /**< bit: 17 TIOAx Mirror */ + uint32_t MTIOB:1; /**< bit: 18 TIOBx Mirror */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_SR_OFFSET (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */ + +#define TC_SR_COVFS_Pos 0 /**< (TC_SR) Counter Overflow Status (cleared on read) Position */ +#define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */ +#define TC_SR_COVFS TC_SR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_COVFS_Msk instead */ +#define TC_SR_LOVRS_Pos 1 /**< (TC_SR) Load Overrun Status (cleared on read) Position */ +#define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */ +#define TC_SR_LOVRS TC_SR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LOVRS_Msk instead */ +#define TC_SR_CPAS_Pos 2 /**< (TC_SR) RA Compare Status (cleared on read) Position */ +#define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */ +#define TC_SR_CPAS TC_SR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPAS_Msk instead */ +#define TC_SR_CPBS_Pos 3 /**< (TC_SR) RB Compare Status (cleared on read) Position */ +#define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */ +#define TC_SR_CPBS TC_SR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPBS_Msk instead */ +#define TC_SR_CPCS_Pos 4 /**< (TC_SR) RC Compare Status (cleared on read) Position */ +#define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */ +#define TC_SR_CPCS TC_SR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CPCS_Msk instead */ +#define TC_SR_LDRAS_Pos 5 /**< (TC_SR) RA Loading Status (cleared on read) Position */ +#define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */ +#define TC_SR_LDRAS TC_SR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRAS_Msk instead */ +#define TC_SR_LDRBS_Pos 6 /**< (TC_SR) RB Loading Status (cleared on read) Position */ +#define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */ +#define TC_SR_LDRBS TC_SR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_LDRBS_Msk instead */ +#define TC_SR_ETRGS_Pos 7 /**< (TC_SR) External Trigger Status (cleared on read) Position */ +#define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */ +#define TC_SR_ETRGS TC_SR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_ETRGS_Msk instead */ +#define TC_SR_CLKSTA_Pos 16 /**< (TC_SR) Clock Enabling Status Position */ +#define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */ +#define TC_SR_CLKSTA TC_SR_CLKSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_CLKSTA_Msk instead */ +#define TC_SR_MTIOA_Pos 17 /**< (TC_SR) TIOAx Mirror Position */ +#define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */ +#define TC_SR_MTIOA TC_SR_MTIOA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOA_Msk instead */ +#define TC_SR_MTIOB_Pos 18 /**< (TC_SR) TIOBx Mirror Position */ +#define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */ +#define TC_SR_MTIOB TC_SR_MTIOB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_SR_MTIOB_Msk instead */ +#define TC_SR_MASK _U_(0x700FF) /**< \deprecated (TC_SR) Register MASK (Use TC_SR_Msk instead) */ +#define TC_SR_Msk _U_(0x700FF) /**< (TC_SR) Register Mask */ + + +/* -------- TC_IER : (TC Offset: 0x24) (/W 32) Interrupt Enable Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ + uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ + uint32_t CPAS:1; /**< bit: 2 RA Compare */ + uint32_t CPBS:1; /**< bit: 3 RB Compare */ + uint32_t CPCS:1; /**< bit: 4 RC Compare */ + uint32_t LDRAS:1; /**< bit: 5 RA Loading */ + uint32_t LDRBS:1; /**< bit: 6 RB Loading */ + uint32_t ETRGS:1; /**< bit: 7 External Trigger */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_IER_OFFSET (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */ + +#define TC_IER_COVFS_Pos 0 /**< (TC_IER) Counter Overflow Position */ +#define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */ +#define TC_IER_COVFS TC_IER_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_COVFS_Msk instead */ +#define TC_IER_LOVRS_Pos 1 /**< (TC_IER) Load Overrun Position */ +#define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */ +#define TC_IER_LOVRS TC_IER_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LOVRS_Msk instead */ +#define TC_IER_CPAS_Pos 2 /**< (TC_IER) RA Compare Position */ +#define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */ +#define TC_IER_CPAS TC_IER_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPAS_Msk instead */ +#define TC_IER_CPBS_Pos 3 /**< (TC_IER) RB Compare Position */ +#define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */ +#define TC_IER_CPBS TC_IER_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPBS_Msk instead */ +#define TC_IER_CPCS_Pos 4 /**< (TC_IER) RC Compare Position */ +#define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */ +#define TC_IER_CPCS TC_IER_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_CPCS_Msk instead */ +#define TC_IER_LDRAS_Pos 5 /**< (TC_IER) RA Loading Position */ +#define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */ +#define TC_IER_LDRAS TC_IER_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRAS_Msk instead */ +#define TC_IER_LDRBS_Pos 6 /**< (TC_IER) RB Loading Position */ +#define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */ +#define TC_IER_LDRBS TC_IER_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_LDRBS_Msk instead */ +#define TC_IER_ETRGS_Pos 7 /**< (TC_IER) External Trigger Position */ +#define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */ +#define TC_IER_ETRGS TC_IER_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IER_ETRGS_Msk instead */ +#define TC_IER_MASK _U_(0xFF) /**< \deprecated (TC_IER) Register MASK (Use TC_IER_Msk instead) */ +#define TC_IER_Msk _U_(0xFF) /**< (TC_IER) Register Mask */ + + +/* -------- TC_IDR : (TC Offset: 0x28) (/W 32) Interrupt Disable Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ + uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ + uint32_t CPAS:1; /**< bit: 2 RA Compare */ + uint32_t CPBS:1; /**< bit: 3 RB Compare */ + uint32_t CPCS:1; /**< bit: 4 RC Compare */ + uint32_t LDRAS:1; /**< bit: 5 RA Loading */ + uint32_t LDRBS:1; /**< bit: 6 RB Loading */ + uint32_t ETRGS:1; /**< bit: 7 External Trigger */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_IDR_OFFSET (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */ + +#define TC_IDR_COVFS_Pos 0 /**< (TC_IDR) Counter Overflow Position */ +#define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */ +#define TC_IDR_COVFS TC_IDR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_COVFS_Msk instead */ +#define TC_IDR_LOVRS_Pos 1 /**< (TC_IDR) Load Overrun Position */ +#define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */ +#define TC_IDR_LOVRS TC_IDR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LOVRS_Msk instead */ +#define TC_IDR_CPAS_Pos 2 /**< (TC_IDR) RA Compare Position */ +#define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */ +#define TC_IDR_CPAS TC_IDR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPAS_Msk instead */ +#define TC_IDR_CPBS_Pos 3 /**< (TC_IDR) RB Compare Position */ +#define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */ +#define TC_IDR_CPBS TC_IDR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPBS_Msk instead */ +#define TC_IDR_CPCS_Pos 4 /**< (TC_IDR) RC Compare Position */ +#define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */ +#define TC_IDR_CPCS TC_IDR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_CPCS_Msk instead */ +#define TC_IDR_LDRAS_Pos 5 /**< (TC_IDR) RA Loading Position */ +#define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */ +#define TC_IDR_LDRAS TC_IDR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRAS_Msk instead */ +#define TC_IDR_LDRBS_Pos 6 /**< (TC_IDR) RB Loading Position */ +#define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */ +#define TC_IDR_LDRBS TC_IDR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_LDRBS_Msk instead */ +#define TC_IDR_ETRGS_Pos 7 /**< (TC_IDR) External Trigger Position */ +#define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */ +#define TC_IDR_ETRGS TC_IDR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IDR_ETRGS_Msk instead */ +#define TC_IDR_MASK _U_(0xFF) /**< \deprecated (TC_IDR) Register MASK (Use TC_IDR_Msk instead) */ +#define TC_IDR_Msk _U_(0xFF) /**< (TC_IDR) Register Mask */ + + +/* -------- TC_IMR : (TC Offset: 0x2c) (R/ 32) Interrupt Mask Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COVFS:1; /**< bit: 0 Counter Overflow */ + uint32_t LOVRS:1; /**< bit: 1 Load Overrun */ + uint32_t CPAS:1; /**< bit: 2 RA Compare */ + uint32_t CPBS:1; /**< bit: 3 RB Compare */ + uint32_t CPCS:1; /**< bit: 4 RC Compare */ + uint32_t LDRAS:1; /**< bit: 5 RA Loading */ + uint32_t LDRBS:1; /**< bit: 6 RB Loading */ + uint32_t ETRGS:1; /**< bit: 7 External Trigger */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_IMR_OFFSET (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */ + +#define TC_IMR_COVFS_Pos 0 /**< (TC_IMR) Counter Overflow Position */ +#define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */ +#define TC_IMR_COVFS TC_IMR_COVFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_COVFS_Msk instead */ +#define TC_IMR_LOVRS_Pos 1 /**< (TC_IMR) Load Overrun Position */ +#define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */ +#define TC_IMR_LOVRS TC_IMR_LOVRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LOVRS_Msk instead */ +#define TC_IMR_CPAS_Pos 2 /**< (TC_IMR) RA Compare Position */ +#define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */ +#define TC_IMR_CPAS TC_IMR_CPAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPAS_Msk instead */ +#define TC_IMR_CPBS_Pos 3 /**< (TC_IMR) RB Compare Position */ +#define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */ +#define TC_IMR_CPBS TC_IMR_CPBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPBS_Msk instead */ +#define TC_IMR_CPCS_Pos 4 /**< (TC_IMR) RC Compare Position */ +#define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */ +#define TC_IMR_CPCS TC_IMR_CPCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_CPCS_Msk instead */ +#define TC_IMR_LDRAS_Pos 5 /**< (TC_IMR) RA Loading Position */ +#define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */ +#define TC_IMR_LDRAS TC_IMR_LDRAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRAS_Msk instead */ +#define TC_IMR_LDRBS_Pos 6 /**< (TC_IMR) RB Loading Position */ +#define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */ +#define TC_IMR_LDRBS TC_IMR_LDRBS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_LDRBS_Msk instead */ +#define TC_IMR_ETRGS_Pos 7 /**< (TC_IMR) External Trigger Position */ +#define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */ +#define TC_IMR_ETRGS TC_IMR_ETRGS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_IMR_ETRGS_Msk instead */ +#define TC_IMR_MASK _U_(0xFF) /**< \deprecated (TC_IMR) Register MASK (Use TC_IMR_Msk instead) */ +#define TC_IMR_Msk _U_(0xFF) /**< (TC_IMR) Register Mask */ + + +/* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TRIGSRCA:2; /**< bit: 0..1 Trigger Source for Input A */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t TRIGSRCB:2; /**< bit: 4..5 Trigger Source for Input B */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t NODIVCLK:1; /**< bit: 8 No Divided Clock */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_EMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_EMR_OFFSET (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */ + +#define TC_EMR_TRIGSRCA_Pos 0 /**< (TC_EMR) Trigger Source for Input A Position */ +#define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */ +#define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */ +#define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */ +#define TC_EMR_TRIGSRCB_Pos 4 /**< (TC_EMR) Trigger Source for Input B Position */ +#define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */ +#define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */ +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */ +#define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */ +#define TC_EMR_NODIVCLK_Pos 8 /**< (TC_EMR) No Divided Clock Position */ +#define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */ +#define TC_EMR_NODIVCLK TC_EMR_NODIVCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_EMR_NODIVCLK_Msk instead */ +#define TC_EMR_MASK _U_(0x133) /**< \deprecated (TC_EMR) Register MASK (Use TC_EMR_Msk instead) */ +#define TC_EMR_Msk _U_(0x133) /**< (TC_EMR) Register Mask */ + + +/* -------- TC_BCR : (TC Offset: 0xc0) (/W 32) Block Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SYNC:1; /**< bit: 0 Synchro Command */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_BCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_BCR_OFFSET (0xC0) /**< (TC_BCR) Block Control Register Offset */ + +#define TC_BCR_SYNC_Pos 0 /**< (TC_BCR) Synchro Command Position */ +#define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */ +#define TC_BCR_SYNC TC_BCR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BCR_SYNC_Msk instead */ +#define TC_BCR_MASK _U_(0x01) /**< \deprecated (TC_BCR) Register MASK (Use TC_BCR_Msk instead) */ +#define TC_BCR_Msk _U_(0x01) /**< (TC_BCR) Register Mask */ + + +/* -------- TC_BMR : (TC Offset: 0xc4) (R/W 32) Block Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TC0XC0S:2; /**< bit: 0..1 External Clock Signal 0 Selection */ + uint32_t TC1XC1S:2; /**< bit: 2..3 External Clock Signal 1 Selection */ + uint32_t TC2XC2S:2; /**< bit: 4..5 External Clock Signal 2 Selection */ + uint32_t :2; /**< bit: 6..7 Reserved */ + uint32_t QDEN:1; /**< bit: 8 Quadrature Decoder Enabled */ + uint32_t POSEN:1; /**< bit: 9 Position Enabled */ + uint32_t SPEEDEN:1; /**< bit: 10 Speed Enabled */ + uint32_t QDTRANS:1; /**< bit: 11 Quadrature Decoding Transparent */ + uint32_t EDGPHA:1; /**< bit: 12 Edge on PHA Count Mode */ + uint32_t INVA:1; /**< bit: 13 Inverted PHA */ + uint32_t INVB:1; /**< bit: 14 Inverted PHB */ + uint32_t INVIDX:1; /**< bit: 15 Inverted Index */ + uint32_t SWAP:1; /**< bit: 16 Swap PHA and PHB */ + uint32_t IDXPHB:1; /**< bit: 17 Index Pin is PHB Pin */ + uint32_t AUTOC:1; /**< bit: 18 AutoCorrection of missing pulses */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t MAXFILT:6; /**< bit: 20..25 Maximum Filter */ + uint32_t MAXCMP:4; /**< bit: 26..29 Maximum Consecutive Missing Pulses */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_BMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_BMR_OFFSET (0xC4) /**< (TC_BMR) Block Mode Register Offset */ + +#define TC_BMR_TC0XC0S_Pos 0 /**< (TC_BMR) External Clock Signal 0 Selection Position */ +#define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */ +#define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) +#define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */ +#define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */ +#define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */ +#define TC_BMR_TC1XC1S_Pos 2 /**< (TC_BMR) External Clock Signal 1 Selection Position */ +#define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */ +#define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) +#define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */ +#define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */ +#define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */ +#define TC_BMR_TC2XC2S_Pos 4 /**< (TC_BMR) External Clock Signal 2 Selection Position */ +#define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */ +#define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) +#define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */ +#define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */ +#define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */ +#define TC_BMR_QDEN_Pos 8 /**< (TC_BMR) Quadrature Decoder Enabled Position */ +#define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */ +#define TC_BMR_QDEN TC_BMR_QDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDEN_Msk instead */ +#define TC_BMR_POSEN_Pos 9 /**< (TC_BMR) Position Enabled Position */ +#define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */ +#define TC_BMR_POSEN TC_BMR_POSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_POSEN_Msk instead */ +#define TC_BMR_SPEEDEN_Pos 10 /**< (TC_BMR) Speed Enabled Position */ +#define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */ +#define TC_BMR_SPEEDEN TC_BMR_SPEEDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SPEEDEN_Msk instead */ +#define TC_BMR_QDTRANS_Pos 11 /**< (TC_BMR) Quadrature Decoding Transparent Position */ +#define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */ +#define TC_BMR_QDTRANS TC_BMR_QDTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_QDTRANS_Msk instead */ +#define TC_BMR_EDGPHA_Pos 12 /**< (TC_BMR) Edge on PHA Count Mode Position */ +#define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */ +#define TC_BMR_EDGPHA TC_BMR_EDGPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_EDGPHA_Msk instead */ +#define TC_BMR_INVA_Pos 13 /**< (TC_BMR) Inverted PHA Position */ +#define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */ +#define TC_BMR_INVA TC_BMR_INVA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVA_Msk instead */ +#define TC_BMR_INVB_Pos 14 /**< (TC_BMR) Inverted PHB Position */ +#define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */ +#define TC_BMR_INVB TC_BMR_INVB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVB_Msk instead */ +#define TC_BMR_INVIDX_Pos 15 /**< (TC_BMR) Inverted Index Position */ +#define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */ +#define TC_BMR_INVIDX TC_BMR_INVIDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_INVIDX_Msk instead */ +#define TC_BMR_SWAP_Pos 16 /**< (TC_BMR) Swap PHA and PHB Position */ +#define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */ +#define TC_BMR_SWAP TC_BMR_SWAP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_SWAP_Msk instead */ +#define TC_BMR_IDXPHB_Pos 17 /**< (TC_BMR) Index Pin is PHB Pin Position */ +#define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */ +#define TC_BMR_IDXPHB TC_BMR_IDXPHB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_IDXPHB_Msk instead */ +#define TC_BMR_AUTOC_Pos 18 /**< (TC_BMR) AutoCorrection of missing pulses Position */ +#define TC_BMR_AUTOC_Msk (_U_(0x1) << TC_BMR_AUTOC_Pos) /**< (TC_BMR) AutoCorrection of missing pulses Mask */ +#define TC_BMR_AUTOC TC_BMR_AUTOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_BMR_AUTOC_Msk instead */ +#define TC_BMR_MAXFILT_Pos 20 /**< (TC_BMR) Maximum Filter Position */ +#define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */ +#define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)) +#define TC_BMR_MAXCMP_Pos 26 /**< (TC_BMR) Maximum Consecutive Missing Pulses Position */ +#define TC_BMR_MAXCMP_Msk (_U_(0xF) << TC_BMR_MAXCMP_Pos) /**< (TC_BMR) Maximum Consecutive Missing Pulses Mask */ +#define TC_BMR_MAXCMP(value) (TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)) +#define TC_BMR_MASK _U_(0x3FF7FF3F) /**< \deprecated (TC_BMR) Register MASK (Use TC_BMR_Msk instead) */ +#define TC_BMR_Msk _U_(0x3FF7FF3F) /**< (TC_BMR) Register Mask */ + + +/* -------- TC_QIER : (TC Offset: 0xc8) (/W 32) QDEC Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDX:1; /**< bit: 0 Index */ + uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ + uint32_t QERR:1; /**< bit: 2 Quadrature Error */ + uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_QIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_QIER_OFFSET (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */ + +#define TC_QIER_IDX_Pos 0 /**< (TC_QIER) Index Position */ +#define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */ +#define TC_QIER_IDX TC_QIER_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_IDX_Msk instead */ +#define TC_QIER_DIRCHG_Pos 1 /**< (TC_QIER) Direction Change Position */ +#define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */ +#define TC_QIER_DIRCHG TC_QIER_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_DIRCHG_Msk instead */ +#define TC_QIER_QERR_Pos 2 /**< (TC_QIER) Quadrature Error Position */ +#define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */ +#define TC_QIER_QERR TC_QIER_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_QERR_Msk instead */ +#define TC_QIER_MPE_Pos 3 /**< (TC_QIER) Consecutive Missing Pulse Error Position */ +#define TC_QIER_MPE_Msk (_U_(0x1) << TC_QIER_MPE_Pos) /**< (TC_QIER) Consecutive Missing Pulse Error Mask */ +#define TC_QIER_MPE TC_QIER_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIER_MPE_Msk instead */ +#define TC_QIER_MASK _U_(0x0F) /**< \deprecated (TC_QIER) Register MASK (Use TC_QIER_Msk instead) */ +#define TC_QIER_Msk _U_(0x0F) /**< (TC_QIER) Register Mask */ + + +/* -------- TC_QIDR : (TC Offset: 0xcc) (/W 32) QDEC Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDX:1; /**< bit: 0 Index */ + uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ + uint32_t QERR:1; /**< bit: 2 Quadrature Error */ + uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_QIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_QIDR_OFFSET (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */ + +#define TC_QIDR_IDX_Pos 0 /**< (TC_QIDR) Index Position */ +#define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */ +#define TC_QIDR_IDX TC_QIDR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_IDX_Msk instead */ +#define TC_QIDR_DIRCHG_Pos 1 /**< (TC_QIDR) Direction Change Position */ +#define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */ +#define TC_QIDR_DIRCHG TC_QIDR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_DIRCHG_Msk instead */ +#define TC_QIDR_QERR_Pos 2 /**< (TC_QIDR) Quadrature Error Position */ +#define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */ +#define TC_QIDR_QERR TC_QIDR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_QERR_Msk instead */ +#define TC_QIDR_MPE_Pos 3 /**< (TC_QIDR) Consecutive Missing Pulse Error Position */ +#define TC_QIDR_MPE_Msk (_U_(0x1) << TC_QIDR_MPE_Pos) /**< (TC_QIDR) Consecutive Missing Pulse Error Mask */ +#define TC_QIDR_MPE TC_QIDR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIDR_MPE_Msk instead */ +#define TC_QIDR_MASK _U_(0x0F) /**< \deprecated (TC_QIDR) Register MASK (Use TC_QIDR_Msk instead) */ +#define TC_QIDR_Msk _U_(0x0F) /**< (TC_QIDR) Register Mask */ + + +/* -------- TC_QIMR : (TC Offset: 0xd0) (R/ 32) QDEC Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDX:1; /**< bit: 0 Index */ + uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ + uint32_t QERR:1; /**< bit: 2 Quadrature Error */ + uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_QIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_QIMR_OFFSET (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */ + +#define TC_QIMR_IDX_Pos 0 /**< (TC_QIMR) Index Position */ +#define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */ +#define TC_QIMR_IDX TC_QIMR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_IDX_Msk instead */ +#define TC_QIMR_DIRCHG_Pos 1 /**< (TC_QIMR) Direction Change Position */ +#define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */ +#define TC_QIMR_DIRCHG TC_QIMR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_DIRCHG_Msk instead */ +#define TC_QIMR_QERR_Pos 2 /**< (TC_QIMR) Quadrature Error Position */ +#define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */ +#define TC_QIMR_QERR TC_QIMR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_QERR_Msk instead */ +#define TC_QIMR_MPE_Pos 3 /**< (TC_QIMR) Consecutive Missing Pulse Error Position */ +#define TC_QIMR_MPE_Msk (_U_(0x1) << TC_QIMR_MPE_Pos) /**< (TC_QIMR) Consecutive Missing Pulse Error Mask */ +#define TC_QIMR_MPE TC_QIMR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QIMR_MPE_Msk instead */ +#define TC_QIMR_MASK _U_(0x0F) /**< \deprecated (TC_QIMR) Register MASK (Use TC_QIMR_Msk instead) */ +#define TC_QIMR_Msk _U_(0x0F) /**< (TC_QIMR) Register Mask */ + + +/* -------- TC_QISR : (TC Offset: 0xd4) (R/ 32) QDEC Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDX:1; /**< bit: 0 Index */ + uint32_t DIRCHG:1; /**< bit: 1 Direction Change */ + uint32_t QERR:1; /**< bit: 2 Quadrature Error */ + uint32_t MPE:1; /**< bit: 3 Consecutive Missing Pulse Error */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t DIR:1; /**< bit: 8 Direction */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_QISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_QISR_OFFSET (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */ + +#define TC_QISR_IDX_Pos 0 /**< (TC_QISR) Index Position */ +#define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */ +#define TC_QISR_IDX TC_QISR_IDX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_IDX_Msk instead */ +#define TC_QISR_DIRCHG_Pos 1 /**< (TC_QISR) Direction Change Position */ +#define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */ +#define TC_QISR_DIRCHG TC_QISR_DIRCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIRCHG_Msk instead */ +#define TC_QISR_QERR_Pos 2 /**< (TC_QISR) Quadrature Error Position */ +#define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */ +#define TC_QISR_QERR TC_QISR_QERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_QERR_Msk instead */ +#define TC_QISR_MPE_Pos 3 /**< (TC_QISR) Consecutive Missing Pulse Error Position */ +#define TC_QISR_MPE_Msk (_U_(0x1) << TC_QISR_MPE_Pos) /**< (TC_QISR) Consecutive Missing Pulse Error Mask */ +#define TC_QISR_MPE TC_QISR_MPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_MPE_Msk instead */ +#define TC_QISR_DIR_Pos 8 /**< (TC_QISR) Direction Position */ +#define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */ +#define TC_QISR_DIR TC_QISR_DIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_QISR_DIR_Msk instead */ +#define TC_QISR_MASK _U_(0x10F) /**< \deprecated (TC_QISR) Register MASK (Use TC_QISR_Msk instead) */ +#define TC_QISR_Msk _U_(0x10F) /**< (TC_QISR) Register Mask */ + + +/* -------- TC_FMR : (TC Offset: 0xd8) (R/W 32) Fault Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ENCF0:1; /**< bit: 0 Enable Compare Fault Channel 0 */ + uint32_t ENCF1:1; /**< bit: 1 Enable Compare Fault Channel 1 */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ENCF:2; /**< bit: 0..1 Enable Compare Fault Channel x */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} TC_FMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_FMR_OFFSET (0xD8) /**< (TC_FMR) Fault Mode Register Offset */ + +#define TC_FMR_ENCF0_Pos 0 /**< (TC_FMR) Enable Compare Fault Channel 0 Position */ +#define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */ +#define TC_FMR_ENCF0 TC_FMR_ENCF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF0_Msk instead */ +#define TC_FMR_ENCF1_Pos 1 /**< (TC_FMR) Enable Compare Fault Channel 1 Position */ +#define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */ +#define TC_FMR_ENCF1 TC_FMR_ENCF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_FMR_ENCF1_Msk instead */ +#define TC_FMR_MASK _U_(0x03) /**< \deprecated (TC_FMR) Register MASK (Use TC_FMR_Msk instead) */ +#define TC_FMR_Msk _U_(0x03) /**< (TC_FMR) Register Mask */ + +#define TC_FMR_ENCF_Pos 0 /**< (TC_FMR Position) Enable Compare Fault Channel x */ +#define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */ +#define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos)) + +/* -------- TC_WPMR : (TC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TC_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_WPMR_OFFSET (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */ + +#define TC_WPMR_WPEN_Pos 0 /**< (TC_WPMR) Write Protection Enable Position */ +#define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */ +#define TC_WPMR_WPEN TC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_WPMR_WPEN_Msk instead */ +#define TC_WPMR_WPKEY_Pos 8 /**< (TC_WPMR) Write Protection Key Position */ +#define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */ +#define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) +#define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define TC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TC_WPMR) Register MASK (Use TC_WPMR_Msk instead) */ +#define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief TC_CHANNEL hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< (TC_CHANNEL Offset: 0x00) Channel Control Register (channel = 0) */ + __IO uint32_t TC_CMR; /**< (TC_CHANNEL Offset: 0x04) Channel Mode Register (channel = 0) */ + __IO uint32_t TC_SMMR; /**< (TC_CHANNEL Offset: 0x08) Stepper Motor Mode Register (channel = 0) */ + __I uint32_t TC_RAB; /**< (TC_CHANNEL Offset: 0x0C) Register AB (channel = 0) */ + __I uint32_t TC_CV; /**< (TC_CHANNEL Offset: 0x10) Counter Value (channel = 0) */ + __IO uint32_t TC_RA; /**< (TC_CHANNEL Offset: 0x14) Register A (channel = 0) */ + __IO uint32_t TC_RB; /**< (TC_CHANNEL Offset: 0x18) Register B (channel = 0) */ + __IO uint32_t TC_RC; /**< (TC_CHANNEL Offset: 0x1C) Register C (channel = 0) */ + __I uint32_t TC_SR; /**< (TC_CHANNEL Offset: 0x20) Status Register (channel = 0) */ + __O uint32_t TC_IER; /**< (TC_CHANNEL Offset: 0x24) Interrupt Enable Register (channel = 0) */ + __O uint32_t TC_IDR; /**< (TC_CHANNEL Offset: 0x28) Interrupt Disable Register (channel = 0) */ + __I uint32_t TC_IMR; /**< (TC_CHANNEL Offset: 0x2C) Interrupt Mask Register (channel = 0) */ + __IO uint32_t TC_EMR; /**< (TC_CHANNEL Offset: 0x30) Extended Mode Register (channel = 0) */ + __I uint8_t Reserved1[12]; +} TcChannel; + +#define TCCHANNEL_NUMBER 3 +/** \brief TC hardware registers */ +typedef struct { + TcChannel TcChannel[TCCHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ + __O uint32_t TC_BCR; /**< (TC Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< (TC Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< (TC Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< (TC Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< (TC Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< (TC Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< (TC Offset: 0xD8) Fault Mode Register */ + __I uint8_t Reserved1[8]; + __IO uint32_t TC_WPMR; /**< (TC Offset: 0xE4) Write Protection Mode Register */ +} Tc; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief TC_CHANNEL hardware registers */ +typedef struct { + __O TC_CCR_Type TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */ + __IO TC_CMR_Type TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */ + __IO TC_SMMR_Type TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */ + __I TC_RAB_Type TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */ + __I TC_CV_Type TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */ + __IO TC_RA_Type TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */ + __IO TC_RB_Type TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */ + __IO TC_RC_Type TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */ + __I TC_SR_Type TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */ + __O TC_IER_Type TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */ + __O TC_IDR_Type TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */ + __I TC_IMR_Type TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */ + __IO TC_EMR_Type TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */ + __I uint8_t Reserved1[12]; +} TcChannel; + +/** \brief TC hardware registers */ +typedef struct { + TcChannel TcChannel[3]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ + __O TC_BCR_Type TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */ + __IO TC_BMR_Type TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */ + __O TC_QIER_Type TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */ + __O TC_QIDR_Type TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */ + __I TC_QIMR_Type TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */ + __I TC_QISR_Type TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */ + __IO TC_FMR_Type TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */ + __I uint8_t Reserved1[8]; + __IO TC_WPMR_Type TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} Tc; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Timer Counter */ + +#if !(defined(DO_NOT_USE_DEPRECATED_MACROS)) +#include "deprecated/tc.h" +#endif /* DO_NOT_USE_DEPRECATED_MACROS */ +#endif /* _SAME70_TC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/trng.h b/bsp/microchip/same70/bsp/same70b/include/component/trng.h new file mode 100644 index 0000000000..3ab7899e1f --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/trng.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Component description for TRNG + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TRNG_COMPONENT_H_ +#define _SAME70_TRNG_COMPONENT_H_ +#define _SAME70_TRNG_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 True Random Number Generator + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TRNG */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define TRNG_6334 /**< (TRNG) Module ID */ +#define REV_TRNG G /**< (TRNG) Module revision */ + +/* -------- TRNG_CR : (TRNG Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ENABLE:1; /**< bit: 0 Enables the TRNG to Provide Random Values */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t KEY:24; /**< bit: 8..31 Security Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_CR_OFFSET (0x00) /**< (TRNG_CR) Control Register Offset */ + +#define TRNG_CR_ENABLE_Pos 0 /**< (TRNG_CR) Enables the TRNG to Provide Random Values Position */ +#define TRNG_CR_ENABLE_Msk (_U_(0x1) << TRNG_CR_ENABLE_Pos) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Mask */ +#define TRNG_CR_ENABLE TRNG_CR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_CR_ENABLE_Msk instead */ +#define TRNG_CR_KEY_Pos 8 /**< (TRNG_CR) Security Key Position */ +#define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Security Key Mask */ +#define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)) +#define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */ +#define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */ +#define TRNG_CR_MASK _U_(0xFFFFFF01) /**< \deprecated (TRNG_CR) Register MASK (Use TRNG_CR_Msk instead) */ +#define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */ + + +/* -------- TRNG_IER : (TRNG Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_IER_OFFSET (0x10) /**< (TRNG_IER) Interrupt Enable Register Offset */ + +#define TRNG_IER_DATRDY_Pos 0 /**< (TRNG_IER) Data Ready Interrupt Enable Position */ +#define TRNG_IER_DATRDY_Msk (_U_(0x1) << TRNG_IER_DATRDY_Pos) /**< (TRNG_IER) Data Ready Interrupt Enable Mask */ +#define TRNG_IER_DATRDY TRNG_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IER_DATRDY_Msk instead */ +#define TRNG_IER_MASK _U_(0x01) /**< \deprecated (TRNG_IER) Register MASK (Use TRNG_IER_Msk instead) */ +#define TRNG_IER_Msk _U_(0x01) /**< (TRNG_IER) Register Mask */ + + +/* -------- TRNG_IDR : (TRNG Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_IDR_OFFSET (0x14) /**< (TRNG_IDR) Interrupt Disable Register Offset */ + +#define TRNG_IDR_DATRDY_Pos 0 /**< (TRNG_IDR) Data Ready Interrupt Disable Position */ +#define TRNG_IDR_DATRDY_Msk (_U_(0x1) << TRNG_IDR_DATRDY_Pos) /**< (TRNG_IDR) Data Ready Interrupt Disable Mask */ +#define TRNG_IDR_DATRDY TRNG_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IDR_DATRDY_Msk instead */ +#define TRNG_IDR_MASK _U_(0x01) /**< \deprecated (TRNG_IDR) Register MASK (Use TRNG_IDR_Msk instead) */ +#define TRNG_IDR_Msk _U_(0x01) /**< (TRNG_IDR) Register Mask */ + + +/* -------- TRNG_IMR : (TRNG Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_IMR_OFFSET (0x18) /**< (TRNG_IMR) Interrupt Mask Register Offset */ + +#define TRNG_IMR_DATRDY_Pos 0 /**< (TRNG_IMR) Data Ready Interrupt Mask Position */ +#define TRNG_IMR_DATRDY_Msk (_U_(0x1) << TRNG_IMR_DATRDY_Pos) /**< (TRNG_IMR) Data Ready Interrupt Mask Mask */ +#define TRNG_IMR_DATRDY TRNG_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_IMR_DATRDY_Msk instead */ +#define TRNG_IMR_MASK _U_(0x01) /**< \deprecated (TRNG_IMR) Register MASK (Use TRNG_IMR_Msk instead) */ +#define TRNG_IMR_Msk _U_(0x01) /**< (TRNG_IMR) Register Mask */ + + +/* -------- TRNG_ISR : (TRNG Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATRDY:1; /**< bit: 0 Data Ready */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_ISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_ISR_OFFSET (0x1C) /**< (TRNG_ISR) Interrupt Status Register Offset */ + +#define TRNG_ISR_DATRDY_Pos 0 /**< (TRNG_ISR) Data Ready Position */ +#define TRNG_ISR_DATRDY_Msk (_U_(0x1) << TRNG_ISR_DATRDY_Pos) /**< (TRNG_ISR) Data Ready Mask */ +#define TRNG_ISR_DATRDY TRNG_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TRNG_ISR_DATRDY_Msk instead */ +#define TRNG_ISR_MASK _U_(0x01) /**< \deprecated (TRNG_ISR) Register MASK (Use TRNG_ISR_Msk instead) */ +#define TRNG_ISR_Msk _U_(0x01) /**< (TRNG_ISR) Register Mask */ + + +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) (R/ 32) Output Data Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ODATA:32; /**< bit: 0..31 Output Data */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TRNG_ODATA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TRNG_ODATA_OFFSET (0x50) /**< (TRNG_ODATA) Output Data Register Offset */ + +#define TRNG_ODATA_ODATA_Pos 0 /**< (TRNG_ODATA) Output Data Position */ +#define TRNG_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << TRNG_ODATA_ODATA_Pos) /**< (TRNG_ODATA) Output Data Mask */ +#define TRNG_ODATA_ODATA(value) (TRNG_ODATA_ODATA_Msk & ((value) << TRNG_ODATA_ODATA_Pos)) +#define TRNG_ODATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (TRNG_ODATA) Register MASK (Use TRNG_ODATA_Msk instead) */ +#define TRNG_ODATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_ODATA) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief TRNG hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< (TRNG Offset: 0x00) Control Register */ + __I uint8_t Reserved1[12]; + __O uint32_t TRNG_IER; /**< (TRNG Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< (TRNG Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< (TRNG Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< (TRNG Offset: 0x1C) Interrupt Status Register */ + __I uint8_t Reserved2[48]; + __I uint32_t TRNG_ODATA; /**< (TRNG Offset: 0x50) Output Data Register */ +} Trng; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief TRNG hardware registers */ +typedef struct { + __O TRNG_CR_Type TRNG_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I uint8_t Reserved1[12]; + __O TRNG_IER_Type TRNG_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O TRNG_IDR_Type TRNG_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I TRNG_IMR_Type TRNG_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I TRNG_ISR_Type TRNG_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[48]; + __I TRNG_ODATA_Type TRNG_ODATA; /**< Offset: 0x50 (R/ 32) Output Data Register */ +} Trng; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of True Random Number Generator */ + +#endif /* _SAME70_TRNG_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/twihs.h b/bsp/microchip/same70/bsp/same70b/include/component/twihs.h new file mode 100644 index 0000000000..76ee56a9d1 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/twihs.h @@ -0,0 +1,929 @@ +/** + * \file + * + * \brief Component description for TWIHS + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TWIHS_COMPONENT_H_ +#define _SAME70_TWIHS_COMPONENT_H_ +#define _SAME70_TWIHS_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Two-wire Interface High Speed + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TWIHS */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define TWIHS_11210 /**< (TWIHS) Module ID */ +#define REV_TWIHS Z /**< (TWIHS) Module revision */ + +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t START:1; /**< bit: 0 Send a START Condition */ + uint32_t STOP:1; /**< bit: 1 Send a STOP Condition */ + uint32_t MSEN:1; /**< bit: 2 TWIHS Master Mode Enabled */ + uint32_t MSDIS:1; /**< bit: 3 TWIHS Master Mode Disabled */ + uint32_t SVEN:1; /**< bit: 4 TWIHS Slave Mode Enabled */ + uint32_t SVDIS:1; /**< bit: 5 TWIHS Slave Mode Disabled */ + uint32_t QUICK:1; /**< bit: 6 SMBus Quick Command */ + uint32_t SWRST:1; /**< bit: 7 Software Reset */ + uint32_t HSEN:1; /**< bit: 8 TWIHS High-Speed Mode Enabled */ + uint32_t HSDIS:1; /**< bit: 9 TWIHS High-Speed Mode Disabled */ + uint32_t SMBEN:1; /**< bit: 10 SMBus Mode Enabled */ + uint32_t SMBDIS:1; /**< bit: 11 SMBus Mode Disabled */ + uint32_t PECEN:1; /**< bit: 12 Packet Error Checking Enable */ + uint32_t PECDIS:1; /**< bit: 13 Packet Error Checking Disable */ + uint32_t PECRQ:1; /**< bit: 14 PEC Request */ + uint32_t CLEAR:1; /**< bit: 15 Bus CLEAR Command */ + uint32_t ACMEN:1; /**< bit: 16 Alternative Command Mode Enable */ + uint32_t ACMDIS:1; /**< bit: 17 Alternative Command Mode Disable */ + uint32_t :6; /**< bit: 18..23 Reserved */ + uint32_t THRCLR:1; /**< bit: 24 Transmit Holding Register Clear */ + uint32_t :1; /**< bit: 25 Reserved */ + uint32_t LOCKCLR:1; /**< bit: 26 Lock Clear */ + uint32_t :1; /**< bit: 27 Reserved */ + uint32_t FIFOEN:1; /**< bit: 28 FIFO Enable */ + uint32_t FIFODIS:1; /**< bit: 29 FIFO Disable */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_CR_OFFSET (0x00) /**< (TWIHS_CR) Control Register Offset */ + +#define TWIHS_CR_START_Pos 0 /**< (TWIHS_CR) Send a START Condition Position */ +#define TWIHS_CR_START_Msk (_U_(0x1) << TWIHS_CR_START_Pos) /**< (TWIHS_CR) Send a START Condition Mask */ +#define TWIHS_CR_START TWIHS_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_START_Msk instead */ +#define TWIHS_CR_STOP_Pos 1 /**< (TWIHS_CR) Send a STOP Condition Position */ +#define TWIHS_CR_STOP_Msk (_U_(0x1) << TWIHS_CR_STOP_Pos) /**< (TWIHS_CR) Send a STOP Condition Mask */ +#define TWIHS_CR_STOP TWIHS_CR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_STOP_Msk instead */ +#define TWIHS_CR_MSEN_Pos 2 /**< (TWIHS_CR) TWIHS Master Mode Enabled Position */ +#define TWIHS_CR_MSEN_Msk (_U_(0x1) << TWIHS_CR_MSEN_Pos) /**< (TWIHS_CR) TWIHS Master Mode Enabled Mask */ +#define TWIHS_CR_MSEN TWIHS_CR_MSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSEN_Msk instead */ +#define TWIHS_CR_MSDIS_Pos 3 /**< (TWIHS_CR) TWIHS Master Mode Disabled Position */ +#define TWIHS_CR_MSDIS_Msk (_U_(0x1) << TWIHS_CR_MSDIS_Pos) /**< (TWIHS_CR) TWIHS Master Mode Disabled Mask */ +#define TWIHS_CR_MSDIS TWIHS_CR_MSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_MSDIS_Msk instead */ +#define TWIHS_CR_SVEN_Pos 4 /**< (TWIHS_CR) TWIHS Slave Mode Enabled Position */ +#define TWIHS_CR_SVEN_Msk (_U_(0x1) << TWIHS_CR_SVEN_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Mask */ +#define TWIHS_CR_SVEN TWIHS_CR_SVEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVEN_Msk instead */ +#define TWIHS_CR_SVDIS_Pos 5 /**< (TWIHS_CR) TWIHS Slave Mode Disabled Position */ +#define TWIHS_CR_SVDIS_Msk (_U_(0x1) << TWIHS_CR_SVDIS_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Mask */ +#define TWIHS_CR_SVDIS TWIHS_CR_SVDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SVDIS_Msk instead */ +#define TWIHS_CR_QUICK_Pos 6 /**< (TWIHS_CR) SMBus Quick Command Position */ +#define TWIHS_CR_QUICK_Msk (_U_(0x1) << TWIHS_CR_QUICK_Pos) /**< (TWIHS_CR) SMBus Quick Command Mask */ +#define TWIHS_CR_QUICK TWIHS_CR_QUICK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_QUICK_Msk instead */ +#define TWIHS_CR_SWRST_Pos 7 /**< (TWIHS_CR) Software Reset Position */ +#define TWIHS_CR_SWRST_Msk (_U_(0x1) << TWIHS_CR_SWRST_Pos) /**< (TWIHS_CR) Software Reset Mask */ +#define TWIHS_CR_SWRST TWIHS_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SWRST_Msk instead */ +#define TWIHS_CR_HSEN_Pos 8 /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Position */ +#define TWIHS_CR_HSEN_Msk (_U_(0x1) << TWIHS_CR_HSEN_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Mask */ +#define TWIHS_CR_HSEN TWIHS_CR_HSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSEN_Msk instead */ +#define TWIHS_CR_HSDIS_Pos 9 /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Position */ +#define TWIHS_CR_HSDIS_Msk (_U_(0x1) << TWIHS_CR_HSDIS_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Mask */ +#define TWIHS_CR_HSDIS TWIHS_CR_HSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_HSDIS_Msk instead */ +#define TWIHS_CR_SMBEN_Pos 10 /**< (TWIHS_CR) SMBus Mode Enabled Position */ +#define TWIHS_CR_SMBEN_Msk (_U_(0x1) << TWIHS_CR_SMBEN_Pos) /**< (TWIHS_CR) SMBus Mode Enabled Mask */ +#define TWIHS_CR_SMBEN TWIHS_CR_SMBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBEN_Msk instead */ +#define TWIHS_CR_SMBDIS_Pos 11 /**< (TWIHS_CR) SMBus Mode Disabled Position */ +#define TWIHS_CR_SMBDIS_Msk (_U_(0x1) << TWIHS_CR_SMBDIS_Pos) /**< (TWIHS_CR) SMBus Mode Disabled Mask */ +#define TWIHS_CR_SMBDIS TWIHS_CR_SMBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_SMBDIS_Msk instead */ +#define TWIHS_CR_PECEN_Pos 12 /**< (TWIHS_CR) Packet Error Checking Enable Position */ +#define TWIHS_CR_PECEN_Msk (_U_(0x1) << TWIHS_CR_PECEN_Pos) /**< (TWIHS_CR) Packet Error Checking Enable Mask */ +#define TWIHS_CR_PECEN TWIHS_CR_PECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECEN_Msk instead */ +#define TWIHS_CR_PECDIS_Pos 13 /**< (TWIHS_CR) Packet Error Checking Disable Position */ +#define TWIHS_CR_PECDIS_Msk (_U_(0x1) << TWIHS_CR_PECDIS_Pos) /**< (TWIHS_CR) Packet Error Checking Disable Mask */ +#define TWIHS_CR_PECDIS TWIHS_CR_PECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECDIS_Msk instead */ +#define TWIHS_CR_PECRQ_Pos 14 /**< (TWIHS_CR) PEC Request Position */ +#define TWIHS_CR_PECRQ_Msk (_U_(0x1) << TWIHS_CR_PECRQ_Pos) /**< (TWIHS_CR) PEC Request Mask */ +#define TWIHS_CR_PECRQ TWIHS_CR_PECRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_PECRQ_Msk instead */ +#define TWIHS_CR_CLEAR_Pos 15 /**< (TWIHS_CR) Bus CLEAR Command Position */ +#define TWIHS_CR_CLEAR_Msk (_U_(0x1) << TWIHS_CR_CLEAR_Pos) /**< (TWIHS_CR) Bus CLEAR Command Mask */ +#define TWIHS_CR_CLEAR TWIHS_CR_CLEAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_CLEAR_Msk instead */ +#define TWIHS_CR_ACMEN_Pos 16 /**< (TWIHS_CR) Alternative Command Mode Enable Position */ +#define TWIHS_CR_ACMEN_Msk (_U_(0x1) << TWIHS_CR_ACMEN_Pos) /**< (TWIHS_CR) Alternative Command Mode Enable Mask */ +#define TWIHS_CR_ACMEN TWIHS_CR_ACMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMEN_Msk instead */ +#define TWIHS_CR_ACMDIS_Pos 17 /**< (TWIHS_CR) Alternative Command Mode Disable Position */ +#define TWIHS_CR_ACMDIS_Msk (_U_(0x1) << TWIHS_CR_ACMDIS_Pos) /**< (TWIHS_CR) Alternative Command Mode Disable Mask */ +#define TWIHS_CR_ACMDIS TWIHS_CR_ACMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_ACMDIS_Msk instead */ +#define TWIHS_CR_THRCLR_Pos 24 /**< (TWIHS_CR) Transmit Holding Register Clear Position */ +#define TWIHS_CR_THRCLR_Msk (_U_(0x1) << TWIHS_CR_THRCLR_Pos) /**< (TWIHS_CR) Transmit Holding Register Clear Mask */ +#define TWIHS_CR_THRCLR TWIHS_CR_THRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_THRCLR_Msk instead */ +#define TWIHS_CR_LOCKCLR_Pos 26 /**< (TWIHS_CR) Lock Clear Position */ +#define TWIHS_CR_LOCKCLR_Msk (_U_(0x1) << TWIHS_CR_LOCKCLR_Pos) /**< (TWIHS_CR) Lock Clear Mask */ +#define TWIHS_CR_LOCKCLR TWIHS_CR_LOCKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_LOCKCLR_Msk instead */ +#define TWIHS_CR_FIFOEN_Pos 28 /**< (TWIHS_CR) FIFO Enable Position */ +#define TWIHS_CR_FIFOEN_Msk (_U_(0x1) << TWIHS_CR_FIFOEN_Pos) /**< (TWIHS_CR) FIFO Enable Mask */ +#define TWIHS_CR_FIFOEN TWIHS_CR_FIFOEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFOEN_Msk instead */ +#define TWIHS_CR_FIFODIS_Pos 29 /**< (TWIHS_CR) FIFO Disable Position */ +#define TWIHS_CR_FIFODIS_Msk (_U_(0x1) << TWIHS_CR_FIFODIS_Pos) /**< (TWIHS_CR) FIFO Disable Mask */ +#define TWIHS_CR_FIFODIS TWIHS_CR_FIFODIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_CR_FIFODIS_Msk instead */ +#define TWIHS_CR_MASK _U_(0x3503FFFF) /**< \deprecated (TWIHS_CR) Register MASK (Use TWIHS_CR_Msk instead) */ +#define TWIHS_CR_Msk _U_(0x3503FFFF) /**< (TWIHS_CR) Register Mask */ + + +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) (R/W 32) Master Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t IADRSZ:2; /**< bit: 8..9 Internal Device Address Size */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t MREAD:1; /**< bit: 12 Master Read Direction */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t DADR:7; /**< bit: 16..22 Device Address */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_MMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_MMR_OFFSET (0x04) /**< (TWIHS_MMR) Master Mode Register Offset */ + +#define TWIHS_MMR_IADRSZ_Pos 8 /**< (TWIHS_MMR) Internal Device Address Size Position */ +#define TWIHS_MMR_IADRSZ_Msk (_U_(0x3) << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Internal Device Address Size Mask */ +#define TWIHS_MMR_IADRSZ(value) (TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)) +#define TWIHS_MMR_IADRSZ_NONE_Val _U_(0x0) /**< (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE_Val _U_(0x1) /**< (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE_Val _U_(0x2) /**< (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE_Val _U_(0x3) /**< (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_IADRSZ_NONE (TWIHS_MMR_IADRSZ_NONE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) No internal device address Position */ +#define TWIHS_MMR_IADRSZ_1_BYTE (TWIHS_MMR_IADRSZ_1_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) One-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_2_BYTE (TWIHS_MMR_IADRSZ_2_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Two-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_3_BYTE (TWIHS_MMR_IADRSZ_3_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Three-byte internal device address Position */ +#define TWIHS_MMR_MREAD_Pos 12 /**< (TWIHS_MMR) Master Read Direction Position */ +#define TWIHS_MMR_MREAD_Msk (_U_(0x1) << TWIHS_MMR_MREAD_Pos) /**< (TWIHS_MMR) Master Read Direction Mask */ +#define TWIHS_MMR_MREAD TWIHS_MMR_MREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_MMR_MREAD_Msk instead */ +#define TWIHS_MMR_DADR_Pos 16 /**< (TWIHS_MMR) Device Address Position */ +#define TWIHS_MMR_DADR_Msk (_U_(0x7F) << TWIHS_MMR_DADR_Pos) /**< (TWIHS_MMR) Device Address Mask */ +#define TWIHS_MMR_DADR(value) (TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)) +#define TWIHS_MMR_MASK _U_(0x7F1300) /**< \deprecated (TWIHS_MMR) Register MASK (Use TWIHS_MMR_Msk instead) */ +#define TWIHS_MMR_Msk _U_(0x7F1300) /**< (TWIHS_MMR) Register Mask */ + + +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) (R/W 32) Slave Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NACKEN:1; /**< bit: 0 Slave Receiver Data Phase NACK enable */ + uint32_t :1; /**< bit: 1 Reserved */ + uint32_t SMDA:1; /**< bit: 2 SMBus Default Address */ + uint32_t SMHH:1; /**< bit: 3 SMBus Host Header */ + uint32_t :2; /**< bit: 4..5 Reserved */ + uint32_t SCLWSDIS:1; /**< bit: 6 Clock Wait State Disable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MASK:7; /**< bit: 8..14 Slave Address Mask */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t SADR:7; /**< bit: 16..22 Slave Address */ + uint32_t :5; /**< bit: 23..27 Reserved */ + uint32_t SADR1EN:1; /**< bit: 28 Slave Address 1 Enable */ + uint32_t SADR2EN:1; /**< bit: 29 Slave Address 2 Enable */ + uint32_t SADR3EN:1; /**< bit: 30 Slave Address 3 Enable */ + uint32_t DATAMEN:1; /**< bit: 31 Data Matching Enable */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_SMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_SMR_OFFSET (0x08) /**< (TWIHS_SMR) Slave Mode Register Offset */ + +#define TWIHS_SMR_NACKEN_Pos 0 /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Position */ +#define TWIHS_SMR_NACKEN_Msk (_U_(0x1) << TWIHS_SMR_NACKEN_Pos) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Mask */ +#define TWIHS_SMR_NACKEN TWIHS_SMR_NACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_NACKEN_Msk instead */ +#define TWIHS_SMR_SMDA_Pos 2 /**< (TWIHS_SMR) SMBus Default Address Position */ +#define TWIHS_SMR_SMDA_Msk (_U_(0x1) << TWIHS_SMR_SMDA_Pos) /**< (TWIHS_SMR) SMBus Default Address Mask */ +#define TWIHS_SMR_SMDA TWIHS_SMR_SMDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMDA_Msk instead */ +#define TWIHS_SMR_SMHH_Pos 3 /**< (TWIHS_SMR) SMBus Host Header Position */ +#define TWIHS_SMR_SMHH_Msk (_U_(0x1) << TWIHS_SMR_SMHH_Pos) /**< (TWIHS_SMR) SMBus Host Header Mask */ +#define TWIHS_SMR_SMHH TWIHS_SMR_SMHH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SMHH_Msk instead */ +#define TWIHS_SMR_SCLWSDIS_Pos 6 /**< (TWIHS_SMR) Clock Wait State Disable Position */ +#define TWIHS_SMR_SCLWSDIS_Msk (_U_(0x1) << TWIHS_SMR_SCLWSDIS_Pos) /**< (TWIHS_SMR) Clock Wait State Disable Mask */ +#define TWIHS_SMR_SCLWSDIS TWIHS_SMR_SCLWSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SCLWSDIS_Msk instead */ +#define TWIHS_SMR_MASK_Pos 8 /**< (TWIHS_SMR) Slave Address Mask Position */ +#define TWIHS_SMR_MASK_Msk (_U_(0x7F) << TWIHS_SMR_MASK_Pos) /**< (TWIHS_SMR) Slave Address Mask Mask */ +#define TWIHS_SMR_MASK(value) (TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)) +#define TWIHS_SMR_SADR_Pos 16 /**< (TWIHS_SMR) Slave Address Position */ +#define TWIHS_SMR_SADR_Msk (_U_(0x7F) << TWIHS_SMR_SADR_Pos) /**< (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_SADR(value) (TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)) +#define TWIHS_SMR_SADR1EN_Pos 28 /**< (TWIHS_SMR) Slave Address 1 Enable Position */ +#define TWIHS_SMR_SADR1EN_Msk (_U_(0x1) << TWIHS_SMR_SADR1EN_Pos) /**< (TWIHS_SMR) Slave Address 1 Enable Mask */ +#define TWIHS_SMR_SADR1EN TWIHS_SMR_SADR1EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR1EN_Msk instead */ +#define TWIHS_SMR_SADR2EN_Pos 29 /**< (TWIHS_SMR) Slave Address 2 Enable Position */ +#define TWIHS_SMR_SADR2EN_Msk (_U_(0x1) << TWIHS_SMR_SADR2EN_Pos) /**< (TWIHS_SMR) Slave Address 2 Enable Mask */ +#define TWIHS_SMR_SADR2EN TWIHS_SMR_SADR2EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR2EN_Msk instead */ +#define TWIHS_SMR_SADR3EN_Pos 30 /**< (TWIHS_SMR) Slave Address 3 Enable Position */ +#define TWIHS_SMR_SADR3EN_Msk (_U_(0x1) << TWIHS_SMR_SADR3EN_Pos) /**< (TWIHS_SMR) Slave Address 3 Enable Mask */ +#define TWIHS_SMR_SADR3EN TWIHS_SMR_SADR3EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_SADR3EN_Msk instead */ +#define TWIHS_SMR_DATAMEN_Pos 31 /**< (TWIHS_SMR) Data Matching Enable Position */ +#define TWIHS_SMR_DATAMEN_Msk (_U_(0x1) << TWIHS_SMR_DATAMEN_Pos) /**< (TWIHS_SMR) Data Matching Enable Mask */ +#define TWIHS_SMR_DATAMEN TWIHS_SMR_DATAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SMR_DATAMEN_Msk instead */ +#define TWIHS_SMR_Msk _U_(0xF07F7F4D) /**< (TWIHS_SMR) Register Mask */ + + +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0c) (R/W 32) Internal Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IADR:24; /**< bit: 0..23 Internal Address */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_IADR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_IADR_OFFSET (0x0C) /**< (TWIHS_IADR) Internal Address Register Offset */ + +#define TWIHS_IADR_IADR_Pos 0 /**< (TWIHS_IADR) Internal Address Position */ +#define TWIHS_IADR_IADR_Msk (_U_(0xFFFFFF) << TWIHS_IADR_IADR_Pos) /**< (TWIHS_IADR) Internal Address Mask */ +#define TWIHS_IADR_IADR(value) (TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)) +#define TWIHS_IADR_MASK _U_(0xFFFFFF) /**< \deprecated (TWIHS_IADR) Register MASK (Use TWIHS_IADR_Msk instead) */ +#define TWIHS_IADR_Msk _U_(0xFFFFFF) /**< (TWIHS_IADR) Register Mask */ + + +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) (R/W 32) Clock Waveform Generator Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CLDIV:8; /**< bit: 0..7 Clock Low Divider */ + uint32_t CHDIV:8; /**< bit: 8..15 Clock High Divider */ + uint32_t CKDIV:3; /**< bit: 16..18 Clock Divider */ + uint32_t :5; /**< bit: 19..23 Reserved */ + uint32_t HOLD:6; /**< bit: 24..29 TWD Hold Time Versus TWCK Falling */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_CWGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_CWGR_OFFSET (0x10) /**< (TWIHS_CWGR) Clock Waveform Generator Register Offset */ + +#define TWIHS_CWGR_CLDIV_Pos 0 /**< (TWIHS_CWGR) Clock Low Divider Position */ +#define TWIHS_CWGR_CLDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CLDIV_Pos) /**< (TWIHS_CWGR) Clock Low Divider Mask */ +#define TWIHS_CWGR_CLDIV(value) (TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)) +#define TWIHS_CWGR_CHDIV_Pos 8 /**< (TWIHS_CWGR) Clock High Divider Position */ +#define TWIHS_CWGR_CHDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CHDIV_Pos) /**< (TWIHS_CWGR) Clock High Divider Mask */ +#define TWIHS_CWGR_CHDIV(value) (TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)) +#define TWIHS_CWGR_CKDIV_Pos 16 /**< (TWIHS_CWGR) Clock Divider Position */ +#define TWIHS_CWGR_CKDIV_Msk (_U_(0x7) << TWIHS_CWGR_CKDIV_Pos) /**< (TWIHS_CWGR) Clock Divider Mask */ +#define TWIHS_CWGR_CKDIV(value) (TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)) +#define TWIHS_CWGR_HOLD_Pos 24 /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Position */ +#define TWIHS_CWGR_HOLD_Msk (_U_(0x3F) << TWIHS_CWGR_HOLD_Pos) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Mask */ +#define TWIHS_CWGR_HOLD(value) (TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)) +#define TWIHS_CWGR_MASK _U_(0x3F07FFFF) /**< \deprecated (TWIHS_CWGR) Register MASK (Use TWIHS_CWGR_Msk instead) */ +#define TWIHS_CWGR_Msk _U_(0x3F07FFFF) /**< (TWIHS_CWGR) Register Mask */ + + +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed (cleared by writing TWIHS_THR) */ + uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ + uint32_t SVREAD:1; /**< bit: 3 Slave Read */ + uint32_t SVACC:1; /**< bit: 4 Slave Access */ + uint32_t GACC:1; /**< bit: 5 General Call Access (cleared on read) */ + uint32_t OVRE:1; /**< bit: 6 Overrun Error (cleared on read) */ + uint32_t UNRE:1; /**< bit: 7 Underrun Error (cleared on read) */ + uint32_t NACK:1; /**< bit: 8 Not Acknowledged (cleared on read) */ + uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost (cleared on read) */ + uint32_t SCLWS:1; /**< bit: 10 Clock Wait State */ + uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access (cleared on read) */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge (cleared on read) */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t TOUT:1; /**< bit: 18 Timeout Error (cleared on read) */ + uint32_t PECERR:1; /**< bit: 19 PEC Error (cleared on read) */ + uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match (cleared on read) */ + uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match (cleared on read) */ + uint32_t :2; /**< bit: 22..23 Reserved */ + uint32_t SCL:1; /**< bit: 24 SCL Line Value */ + uint32_t SDA:1; /**< bit: 25 SDA Line Value */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_SR_OFFSET (0x20) /**< (TWIHS_SR) Status Register Offset */ + +#define TWIHS_SR_TXCOMP_Pos 0 /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXCOMP_Msk (_U_(0x1) << TWIHS_SR_TXCOMP_Pos) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXCOMP TWIHS_SR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXCOMP_Msk instead */ +#define TWIHS_SR_RXRDY_Pos 1 /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Position */ +#define TWIHS_SR_RXRDY_Msk (_U_(0x1) << TWIHS_SR_RXRDY_Pos) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Mask */ +#define TWIHS_SR_RXRDY TWIHS_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_RXRDY_Msk instead */ +#define TWIHS_SR_TXRDY_Pos 2 /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXRDY_Msk (_U_(0x1) << TWIHS_SR_TXRDY_Pos) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXRDY TWIHS_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TXRDY_Msk instead */ +#define TWIHS_SR_SVREAD_Pos 3 /**< (TWIHS_SR) Slave Read Position */ +#define TWIHS_SR_SVREAD_Msk (_U_(0x1) << TWIHS_SR_SVREAD_Pos) /**< (TWIHS_SR) Slave Read Mask */ +#define TWIHS_SR_SVREAD TWIHS_SR_SVREAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVREAD_Msk instead */ +#define TWIHS_SR_SVACC_Pos 4 /**< (TWIHS_SR) Slave Access Position */ +#define TWIHS_SR_SVACC_Msk (_U_(0x1) << TWIHS_SR_SVACC_Pos) /**< (TWIHS_SR) Slave Access Mask */ +#define TWIHS_SR_SVACC TWIHS_SR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SVACC_Msk instead */ +#define TWIHS_SR_GACC_Pos 5 /**< (TWIHS_SR) General Call Access (cleared on read) Position */ +#define TWIHS_SR_GACC_Msk (_U_(0x1) << TWIHS_SR_GACC_Pos) /**< (TWIHS_SR) General Call Access (cleared on read) Mask */ +#define TWIHS_SR_GACC TWIHS_SR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_GACC_Msk instead */ +#define TWIHS_SR_OVRE_Pos 6 /**< (TWIHS_SR) Overrun Error (cleared on read) Position */ +#define TWIHS_SR_OVRE_Msk (_U_(0x1) << TWIHS_SR_OVRE_Pos) /**< (TWIHS_SR) Overrun Error (cleared on read) Mask */ +#define TWIHS_SR_OVRE TWIHS_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_OVRE_Msk instead */ +#define TWIHS_SR_UNRE_Pos 7 /**< (TWIHS_SR) Underrun Error (cleared on read) Position */ +#define TWIHS_SR_UNRE_Msk (_U_(0x1) << TWIHS_SR_UNRE_Pos) /**< (TWIHS_SR) Underrun Error (cleared on read) Mask */ +#define TWIHS_SR_UNRE TWIHS_SR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_UNRE_Msk instead */ +#define TWIHS_SR_NACK_Pos 8 /**< (TWIHS_SR) Not Acknowledged (cleared on read) Position */ +#define TWIHS_SR_NACK_Msk (_U_(0x1) << TWIHS_SR_NACK_Pos) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Mask */ +#define TWIHS_SR_NACK TWIHS_SR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_NACK_Msk instead */ +#define TWIHS_SR_ARBLST_Pos 9 /**< (TWIHS_SR) Arbitration Lost (cleared on read) Position */ +#define TWIHS_SR_ARBLST_Msk (_U_(0x1) << TWIHS_SR_ARBLST_Pos) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Mask */ +#define TWIHS_SR_ARBLST TWIHS_SR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_ARBLST_Msk instead */ +#define TWIHS_SR_SCLWS_Pos 10 /**< (TWIHS_SR) Clock Wait State Position */ +#define TWIHS_SR_SCLWS_Msk (_U_(0x1) << TWIHS_SR_SCLWS_Pos) /**< (TWIHS_SR) Clock Wait State Mask */ +#define TWIHS_SR_SCLWS TWIHS_SR_SCLWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCLWS_Msk instead */ +#define TWIHS_SR_EOSACC_Pos 11 /**< (TWIHS_SR) End Of Slave Access (cleared on read) Position */ +#define TWIHS_SR_EOSACC_Msk (_U_(0x1) << TWIHS_SR_EOSACC_Pos) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Mask */ +#define TWIHS_SR_EOSACC TWIHS_SR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_EOSACC_Msk instead */ +#define TWIHS_SR_MCACK_Pos 16 /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Position */ +#define TWIHS_SR_MCACK_Msk (_U_(0x1) << TWIHS_SR_MCACK_Pos) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Mask */ +#define TWIHS_SR_MCACK TWIHS_SR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_MCACK_Msk instead */ +#define TWIHS_SR_TOUT_Pos 18 /**< (TWIHS_SR) Timeout Error (cleared on read) Position */ +#define TWIHS_SR_TOUT_Msk (_U_(0x1) << TWIHS_SR_TOUT_Pos) /**< (TWIHS_SR) Timeout Error (cleared on read) Mask */ +#define TWIHS_SR_TOUT TWIHS_SR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_TOUT_Msk instead */ +#define TWIHS_SR_PECERR_Pos 19 /**< (TWIHS_SR) PEC Error (cleared on read) Position */ +#define TWIHS_SR_PECERR_Msk (_U_(0x1) << TWIHS_SR_PECERR_Pos) /**< (TWIHS_SR) PEC Error (cleared on read) Mask */ +#define TWIHS_SR_PECERR TWIHS_SR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_PECERR_Msk instead */ +#define TWIHS_SR_SMBDAM_Pos 20 /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBDAM_Msk (_U_(0x1) << TWIHS_SR_SMBDAM_Pos) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBDAM TWIHS_SR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBDAM_Msk instead */ +#define TWIHS_SR_SMBHHM_Pos 21 /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBHHM_Msk (_U_(0x1) << TWIHS_SR_SMBHHM_Pos) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBHHM TWIHS_SR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SMBHHM_Msk instead */ +#define TWIHS_SR_SCL_Pos 24 /**< (TWIHS_SR) SCL Line Value Position */ +#define TWIHS_SR_SCL_Msk (_U_(0x1) << TWIHS_SR_SCL_Pos) /**< (TWIHS_SR) SCL Line Value Mask */ +#define TWIHS_SR_SCL TWIHS_SR_SCL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SCL_Msk instead */ +#define TWIHS_SR_SDA_Pos 25 /**< (TWIHS_SR) SDA Line Value Position */ +#define TWIHS_SR_SDA_Msk (_U_(0x1) << TWIHS_SR_SDA_Pos) /**< (TWIHS_SR) SDA Line Value Mask */ +#define TWIHS_SR_SDA TWIHS_SR_SDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_SR_SDA_Msk instead */ +#define TWIHS_SR_MASK _U_(0x33D0FFF) /**< \deprecated (TWIHS_SR) Register MASK (Use TWIHS_SR_Msk instead) */ +#define TWIHS_SR_Msk _U_(0x33D0FFF) /**< (TWIHS_SR) Register Mask */ + + +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Enable */ + uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Enable */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Enable */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Enable */ + uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Enable */ + uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Enable */ + uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Enable */ + uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Enable */ + uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Enable */ + uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Enable */ + uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Enable */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Enable */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Enable */ + uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Enable */ + uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Enable */ + uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Enable */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_IER_OFFSET (0x24) /**< (TWIHS_IER) Interrupt Enable Register Offset */ + +#define TWIHS_IER_TXCOMP_Pos 0 /**< (TWIHS_IER) Transmission Completed Interrupt Enable Position */ +#define TWIHS_IER_TXCOMP_Msk (_U_(0x1) << TWIHS_IER_TXCOMP_Pos) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Mask */ +#define TWIHS_IER_TXCOMP TWIHS_IER_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXCOMP_Msk instead */ +#define TWIHS_IER_RXRDY_Pos 1 /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_RXRDY_Msk (_U_(0x1) << TWIHS_IER_RXRDY_Pos) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_RXRDY TWIHS_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_RXRDY_Msk instead */ +#define TWIHS_IER_TXRDY_Pos 2 /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_TXRDY_Msk (_U_(0x1) << TWIHS_IER_TXRDY_Pos) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_TXRDY TWIHS_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TXRDY_Msk instead */ +#define TWIHS_IER_SVACC_Pos 4 /**< (TWIHS_IER) Slave Access Interrupt Enable Position */ +#define TWIHS_IER_SVACC_Msk (_U_(0x1) << TWIHS_IER_SVACC_Pos) /**< (TWIHS_IER) Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_SVACC TWIHS_IER_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SVACC_Msk instead */ +#define TWIHS_IER_GACC_Pos 5 /**< (TWIHS_IER) General Call Access Interrupt Enable Position */ +#define TWIHS_IER_GACC_Msk (_U_(0x1) << TWIHS_IER_GACC_Pos) /**< (TWIHS_IER) General Call Access Interrupt Enable Mask */ +#define TWIHS_IER_GACC TWIHS_IER_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_GACC_Msk instead */ +#define TWIHS_IER_OVRE_Pos 6 /**< (TWIHS_IER) Overrun Error Interrupt Enable Position */ +#define TWIHS_IER_OVRE_Msk (_U_(0x1) << TWIHS_IER_OVRE_Pos) /**< (TWIHS_IER) Overrun Error Interrupt Enable Mask */ +#define TWIHS_IER_OVRE TWIHS_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_OVRE_Msk instead */ +#define TWIHS_IER_UNRE_Pos 7 /**< (TWIHS_IER) Underrun Error Interrupt Enable Position */ +#define TWIHS_IER_UNRE_Msk (_U_(0x1) << TWIHS_IER_UNRE_Pos) /**< (TWIHS_IER) Underrun Error Interrupt Enable Mask */ +#define TWIHS_IER_UNRE TWIHS_IER_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_UNRE_Msk instead */ +#define TWIHS_IER_NACK_Pos 8 /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_NACK_Msk (_U_(0x1) << TWIHS_IER_NACK_Pos) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_NACK TWIHS_IER_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_NACK_Msk instead */ +#define TWIHS_IER_ARBLST_Pos 9 /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Position */ +#define TWIHS_IER_ARBLST_Msk (_U_(0x1) << TWIHS_IER_ARBLST_Pos) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Mask */ +#define TWIHS_IER_ARBLST TWIHS_IER_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_ARBLST_Msk instead */ +#define TWIHS_IER_SCL_WS_Pos 10 /**< (TWIHS_IER) Clock Wait State Interrupt Enable Position */ +#define TWIHS_IER_SCL_WS_Msk (_U_(0x1) << TWIHS_IER_SCL_WS_Pos) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Mask */ +#define TWIHS_IER_SCL_WS TWIHS_IER_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SCL_WS_Msk instead */ +#define TWIHS_IER_EOSACC_Pos 11 /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Position */ +#define TWIHS_IER_EOSACC_Msk (_U_(0x1) << TWIHS_IER_EOSACC_Pos) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_EOSACC TWIHS_IER_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_EOSACC_Msk instead */ +#define TWIHS_IER_MCACK_Pos 16 /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_MCACK_Msk (_U_(0x1) << TWIHS_IER_MCACK_Pos) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_MCACK TWIHS_IER_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_MCACK_Msk instead */ +#define TWIHS_IER_TOUT_Pos 18 /**< (TWIHS_IER) Timeout Error Interrupt Enable Position */ +#define TWIHS_IER_TOUT_Msk (_U_(0x1) << TWIHS_IER_TOUT_Pos) /**< (TWIHS_IER) Timeout Error Interrupt Enable Mask */ +#define TWIHS_IER_TOUT TWIHS_IER_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_TOUT_Msk instead */ +#define TWIHS_IER_PECERR_Pos 19 /**< (TWIHS_IER) PEC Error Interrupt Enable Position */ +#define TWIHS_IER_PECERR_Msk (_U_(0x1) << TWIHS_IER_PECERR_Pos) /**< (TWIHS_IER) PEC Error Interrupt Enable Mask */ +#define TWIHS_IER_PECERR TWIHS_IER_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_PECERR_Msk instead */ +#define TWIHS_IER_SMBDAM_Pos 20 /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBDAM_Msk (_U_(0x1) << TWIHS_IER_SMBDAM_Pos) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBDAM TWIHS_IER_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBDAM_Msk instead */ +#define TWIHS_IER_SMBHHM_Pos 21 /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBHHM_Msk (_U_(0x1) << TWIHS_IER_SMBHHM_Pos) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBHHM TWIHS_IER_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IER_SMBHHM_Msk instead */ +#define TWIHS_IER_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IER) Register MASK (Use TWIHS_IER_Msk instead) */ +#define TWIHS_IER_Msk _U_(0x3D0FF7) /**< (TWIHS_IER) Register Mask */ + + +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Disable */ + uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Disable */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Disable */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Disable */ + uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Disable */ + uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Disable */ + uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Disable */ + uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Disable */ + uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Disable */ + uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Disable */ + uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Disable */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Disable */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Disable */ + uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Disable */ + uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Disable */ + uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Disable */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_IDR_OFFSET (0x28) /**< (TWIHS_IDR) Interrupt Disable Register Offset */ + +#define TWIHS_IDR_TXCOMP_Pos 0 /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Position */ +#define TWIHS_IDR_TXCOMP_Msk (_U_(0x1) << TWIHS_IDR_TXCOMP_Pos) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Mask */ +#define TWIHS_IDR_TXCOMP TWIHS_IDR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXCOMP_Msk instead */ +#define TWIHS_IDR_RXRDY_Pos 1 /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_RXRDY_Msk (_U_(0x1) << TWIHS_IDR_RXRDY_Pos) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_RXRDY TWIHS_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_RXRDY_Msk instead */ +#define TWIHS_IDR_TXRDY_Pos 2 /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_TXRDY_Msk (_U_(0x1) << TWIHS_IDR_TXRDY_Pos) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_TXRDY TWIHS_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TXRDY_Msk instead */ +#define TWIHS_IDR_SVACC_Pos 4 /**< (TWIHS_IDR) Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_SVACC_Msk (_U_(0x1) << TWIHS_IDR_SVACC_Pos) /**< (TWIHS_IDR) Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_SVACC TWIHS_IDR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SVACC_Msk instead */ +#define TWIHS_IDR_GACC_Pos 5 /**< (TWIHS_IDR) General Call Access Interrupt Disable Position */ +#define TWIHS_IDR_GACC_Msk (_U_(0x1) << TWIHS_IDR_GACC_Pos) /**< (TWIHS_IDR) General Call Access Interrupt Disable Mask */ +#define TWIHS_IDR_GACC TWIHS_IDR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_GACC_Msk instead */ +#define TWIHS_IDR_OVRE_Pos 6 /**< (TWIHS_IDR) Overrun Error Interrupt Disable Position */ +#define TWIHS_IDR_OVRE_Msk (_U_(0x1) << TWIHS_IDR_OVRE_Pos) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_OVRE TWIHS_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_OVRE_Msk instead */ +#define TWIHS_IDR_UNRE_Pos 7 /**< (TWIHS_IDR) Underrun Error Interrupt Disable Position */ +#define TWIHS_IDR_UNRE_Msk (_U_(0x1) << TWIHS_IDR_UNRE_Pos) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_UNRE TWIHS_IDR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_UNRE_Msk instead */ +#define TWIHS_IDR_NACK_Pos 8 /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_NACK_Msk (_U_(0x1) << TWIHS_IDR_NACK_Pos) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_NACK TWIHS_IDR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_NACK_Msk instead */ +#define TWIHS_IDR_ARBLST_Pos 9 /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Position */ +#define TWIHS_IDR_ARBLST_Msk (_U_(0x1) << TWIHS_IDR_ARBLST_Pos) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Mask */ +#define TWIHS_IDR_ARBLST TWIHS_IDR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_ARBLST_Msk instead */ +#define TWIHS_IDR_SCL_WS_Pos 10 /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Position */ +#define TWIHS_IDR_SCL_WS_Msk (_U_(0x1) << TWIHS_IDR_SCL_WS_Pos) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Mask */ +#define TWIHS_IDR_SCL_WS TWIHS_IDR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SCL_WS_Msk instead */ +#define TWIHS_IDR_EOSACC_Pos 11 /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_EOSACC_Msk (_U_(0x1) << TWIHS_IDR_EOSACC_Pos) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_EOSACC TWIHS_IDR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_EOSACC_Msk instead */ +#define TWIHS_IDR_MCACK_Pos 16 /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_MCACK_Msk (_U_(0x1) << TWIHS_IDR_MCACK_Pos) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_MCACK TWIHS_IDR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_MCACK_Msk instead */ +#define TWIHS_IDR_TOUT_Pos 18 /**< (TWIHS_IDR) Timeout Error Interrupt Disable Position */ +#define TWIHS_IDR_TOUT_Msk (_U_(0x1) << TWIHS_IDR_TOUT_Pos) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Mask */ +#define TWIHS_IDR_TOUT TWIHS_IDR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_TOUT_Msk instead */ +#define TWIHS_IDR_PECERR_Pos 19 /**< (TWIHS_IDR) PEC Error Interrupt Disable Position */ +#define TWIHS_IDR_PECERR_Msk (_U_(0x1) << TWIHS_IDR_PECERR_Pos) /**< (TWIHS_IDR) PEC Error Interrupt Disable Mask */ +#define TWIHS_IDR_PECERR TWIHS_IDR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_PECERR_Msk instead */ +#define TWIHS_IDR_SMBDAM_Pos 20 /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBDAM_Msk (_U_(0x1) << TWIHS_IDR_SMBDAM_Pos) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBDAM TWIHS_IDR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBDAM_Msk instead */ +#define TWIHS_IDR_SMBHHM_Pos 21 /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBHHM_Msk (_U_(0x1) << TWIHS_IDR_SMBHHM_Pos) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBHHM TWIHS_IDR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IDR_SMBHHM_Msk instead */ +#define TWIHS_IDR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IDR) Register MASK (Use TWIHS_IDR_Msk instead) */ +#define TWIHS_IDR_Msk _U_(0x3D0FF7) /**< (TWIHS_IDR) Register Mask */ + + +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCOMP:1; /**< bit: 0 Transmission Completed Interrupt Mask */ + uint32_t RXRDY:1; /**< bit: 1 Receive Holding Register Ready Interrupt Mask */ + uint32_t TXRDY:1; /**< bit: 2 Transmit Holding Register Ready Interrupt Mask */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t SVACC:1; /**< bit: 4 Slave Access Interrupt Mask */ + uint32_t GACC:1; /**< bit: 5 General Call Access Interrupt Mask */ + uint32_t OVRE:1; /**< bit: 6 Overrun Error Interrupt Mask */ + uint32_t UNRE:1; /**< bit: 7 Underrun Error Interrupt Mask */ + uint32_t NACK:1; /**< bit: 8 Not Acknowledge Interrupt Mask */ + uint32_t ARBLST:1; /**< bit: 9 Arbitration Lost Interrupt Mask */ + uint32_t SCL_WS:1; /**< bit: 10 Clock Wait State Interrupt Mask */ + uint32_t EOSACC:1; /**< bit: 11 End Of Slave Access Interrupt Mask */ + uint32_t :4; /**< bit: 12..15 Reserved */ + uint32_t MCACK:1; /**< bit: 16 Master Code Acknowledge Interrupt Mask */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t TOUT:1; /**< bit: 18 Timeout Error Interrupt Mask */ + uint32_t PECERR:1; /**< bit: 19 PEC Error Interrupt Mask */ + uint32_t SMBDAM:1; /**< bit: 20 SMBus Default Address Match Interrupt Mask */ + uint32_t SMBHHM:1; /**< bit: 21 SMBus Host Header Address Match Interrupt Mask */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_IMR_OFFSET (0x2C) /**< (TWIHS_IMR) Interrupt Mask Register Offset */ + +#define TWIHS_IMR_TXCOMP_Pos 0 /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Position */ +#define TWIHS_IMR_TXCOMP_Msk (_U_(0x1) << TWIHS_IMR_TXCOMP_Pos) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Mask */ +#define TWIHS_IMR_TXCOMP TWIHS_IMR_TXCOMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXCOMP_Msk instead */ +#define TWIHS_IMR_RXRDY_Pos 1 /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_RXRDY_Msk (_U_(0x1) << TWIHS_IMR_RXRDY_Pos) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_RXRDY TWIHS_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_RXRDY_Msk instead */ +#define TWIHS_IMR_TXRDY_Pos 2 /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_TXRDY_Msk (_U_(0x1) << TWIHS_IMR_TXRDY_Pos) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_TXRDY TWIHS_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TXRDY_Msk instead */ +#define TWIHS_IMR_SVACC_Pos 4 /**< (TWIHS_IMR) Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_SVACC_Msk (_U_(0x1) << TWIHS_IMR_SVACC_Pos) /**< (TWIHS_IMR) Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_SVACC TWIHS_IMR_SVACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SVACC_Msk instead */ +#define TWIHS_IMR_GACC_Pos 5 /**< (TWIHS_IMR) General Call Access Interrupt Mask Position */ +#define TWIHS_IMR_GACC_Msk (_U_(0x1) << TWIHS_IMR_GACC_Pos) /**< (TWIHS_IMR) General Call Access Interrupt Mask Mask */ +#define TWIHS_IMR_GACC TWIHS_IMR_GACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_GACC_Msk instead */ +#define TWIHS_IMR_OVRE_Pos 6 /**< (TWIHS_IMR) Overrun Error Interrupt Mask Position */ +#define TWIHS_IMR_OVRE_Msk (_U_(0x1) << TWIHS_IMR_OVRE_Pos) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_OVRE TWIHS_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_OVRE_Msk instead */ +#define TWIHS_IMR_UNRE_Pos 7 /**< (TWIHS_IMR) Underrun Error Interrupt Mask Position */ +#define TWIHS_IMR_UNRE_Msk (_U_(0x1) << TWIHS_IMR_UNRE_Pos) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_UNRE TWIHS_IMR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_UNRE_Msk instead */ +#define TWIHS_IMR_NACK_Pos 8 /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_NACK_Msk (_U_(0x1) << TWIHS_IMR_NACK_Pos) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_NACK TWIHS_IMR_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_NACK_Msk instead */ +#define TWIHS_IMR_ARBLST_Pos 9 /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Position */ +#define TWIHS_IMR_ARBLST_Msk (_U_(0x1) << TWIHS_IMR_ARBLST_Pos) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Mask */ +#define TWIHS_IMR_ARBLST TWIHS_IMR_ARBLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_ARBLST_Msk instead */ +#define TWIHS_IMR_SCL_WS_Pos 10 /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Position */ +#define TWIHS_IMR_SCL_WS_Msk (_U_(0x1) << TWIHS_IMR_SCL_WS_Pos) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Mask */ +#define TWIHS_IMR_SCL_WS TWIHS_IMR_SCL_WS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SCL_WS_Msk instead */ +#define TWIHS_IMR_EOSACC_Pos 11 /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_EOSACC_Msk (_U_(0x1) << TWIHS_IMR_EOSACC_Pos) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_EOSACC TWIHS_IMR_EOSACC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_EOSACC_Msk instead */ +#define TWIHS_IMR_MCACK_Pos 16 /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_MCACK_Msk (_U_(0x1) << TWIHS_IMR_MCACK_Pos) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_MCACK TWIHS_IMR_MCACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_MCACK_Msk instead */ +#define TWIHS_IMR_TOUT_Pos 18 /**< (TWIHS_IMR) Timeout Error Interrupt Mask Position */ +#define TWIHS_IMR_TOUT_Msk (_U_(0x1) << TWIHS_IMR_TOUT_Pos) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Mask */ +#define TWIHS_IMR_TOUT TWIHS_IMR_TOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_TOUT_Msk instead */ +#define TWIHS_IMR_PECERR_Pos 19 /**< (TWIHS_IMR) PEC Error Interrupt Mask Position */ +#define TWIHS_IMR_PECERR_Msk (_U_(0x1) << TWIHS_IMR_PECERR_Pos) /**< (TWIHS_IMR) PEC Error Interrupt Mask Mask */ +#define TWIHS_IMR_PECERR TWIHS_IMR_PECERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_PECERR_Msk instead */ +#define TWIHS_IMR_SMBDAM_Pos 20 /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBDAM_Msk (_U_(0x1) << TWIHS_IMR_SMBDAM_Pos) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBDAM TWIHS_IMR_SMBDAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBDAM_Msk instead */ +#define TWIHS_IMR_SMBHHM_Pos 21 /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBHHM_Msk (_U_(0x1) << TWIHS_IMR_SMBHHM_Pos) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBHHM TWIHS_IMR_SMBHHM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_IMR_SMBHHM_Msk instead */ +#define TWIHS_IMR_MASK _U_(0x3D0FF7) /**< \deprecated (TWIHS_IMR) Register MASK (Use TWIHS_IMR_Msk instead) */ +#define TWIHS_IMR_Msk _U_(0x3D0FF7) /**< (TWIHS_IMR) Register Mask */ + + +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) (R/ 32) Receive Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXDATA:8; /**< bit: 0..7 Master or Slave Receive Holding Data */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_RHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_RHR_OFFSET (0x30) /**< (TWIHS_RHR) Receive Holding Register Offset */ + +#define TWIHS_RHR_RXDATA_Pos 0 /**< (TWIHS_RHR) Master or Slave Receive Holding Data Position */ +#define TWIHS_RHR_RXDATA_Msk (_U_(0xFF) << TWIHS_RHR_RXDATA_Pos) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Mask */ +#define TWIHS_RHR_RXDATA(value) (TWIHS_RHR_RXDATA_Msk & ((value) << TWIHS_RHR_RXDATA_Pos)) +#define TWIHS_RHR_MASK _U_(0xFF) /**< \deprecated (TWIHS_RHR) Register MASK (Use TWIHS_RHR_Msk instead) */ +#define TWIHS_RHR_Msk _U_(0xFF) /**< (TWIHS_RHR) Register Mask */ + + +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) (/W 32) Transmit Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXDATA:8; /**< bit: 0..7 Master or Slave Transmit Holding Data */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_THR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_THR_OFFSET (0x34) /**< (TWIHS_THR) Transmit Holding Register Offset */ + +#define TWIHS_THR_TXDATA_Pos 0 /**< (TWIHS_THR) Master or Slave Transmit Holding Data Position */ +#define TWIHS_THR_TXDATA_Msk (_U_(0xFF) << TWIHS_THR_TXDATA_Pos) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Mask */ +#define TWIHS_THR_TXDATA(value) (TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)) +#define TWIHS_THR_MASK _U_(0xFF) /**< \deprecated (TWIHS_THR) Register MASK (Use TWIHS_THR_Msk instead) */ +#define TWIHS_THR_Msk _U_(0xFF) /**< (TWIHS_THR) Register Mask */ + + +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) (R/W 32) SMBus Timing Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PRESC:4; /**< bit: 0..3 SMBus Clock Prescaler */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t TLOWS:8; /**< bit: 8..15 Slave Clock Stretch Maximum Cycles */ + uint32_t TLOWM:8; /**< bit: 16..23 Master Clock Stretch Maximum Cycles */ + uint32_t THMAX:8; /**< bit: 24..31 Clock High Maximum Cycles */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_SMBTR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_SMBTR_OFFSET (0x38) /**< (TWIHS_SMBTR) SMBus Timing Register Offset */ + +#define TWIHS_SMBTR_PRESC_Pos 0 /**< (TWIHS_SMBTR) SMBus Clock Prescaler Position */ +#define TWIHS_SMBTR_PRESC_Msk (_U_(0xF) << TWIHS_SMBTR_PRESC_Pos) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Mask */ +#define TWIHS_SMBTR_PRESC(value) (TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)) +#define TWIHS_SMBTR_TLOWS_Pos 8 /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWS_Pos) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWS(value) (TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)) +#define TWIHS_SMBTR_TLOWM_Pos 16 /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWM_Pos) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWM(value) (TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)) +#define TWIHS_SMBTR_THMAX_Pos 24 /**< (TWIHS_SMBTR) Clock High Maximum Cycles Position */ +#define TWIHS_SMBTR_THMAX_Msk (_U_(0xFF) << TWIHS_SMBTR_THMAX_Pos) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Mask */ +#define TWIHS_SMBTR_THMAX(value) (TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)) +#define TWIHS_SMBTR_MASK _U_(0xFFFFFF0F) /**< \deprecated (TWIHS_SMBTR) Register MASK (Use TWIHS_SMBTR_Msk instead) */ +#define TWIHS_SMBTR_Msk _U_(0xFFFFFF0F) /**< (TWIHS_SMBTR) Register Mask */ + + +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) (R/W 32) Filter Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FILT:1; /**< bit: 0 RX Digital Filter */ + uint32_t PADFEN:1; /**< bit: 1 PAD Filter Enable */ + uint32_t PADFCFG:1; /**< bit: 2 PAD Filter Config */ + uint32_t :5; /**< bit: 3..7 Reserved */ + uint32_t THRES:3; /**< bit: 8..10 Digital Filter Threshold */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_FILTR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_FILTR_OFFSET (0x44) /**< (TWIHS_FILTR) Filter Register Offset */ + +#define TWIHS_FILTR_FILT_Pos 0 /**< (TWIHS_FILTR) RX Digital Filter Position */ +#define TWIHS_FILTR_FILT_Msk (_U_(0x1) << TWIHS_FILTR_FILT_Pos) /**< (TWIHS_FILTR) RX Digital Filter Mask */ +#define TWIHS_FILTR_FILT TWIHS_FILTR_FILT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_FILT_Msk instead */ +#define TWIHS_FILTR_PADFEN_Pos 1 /**< (TWIHS_FILTR) PAD Filter Enable Position */ +#define TWIHS_FILTR_PADFEN_Msk (_U_(0x1) << TWIHS_FILTR_PADFEN_Pos) /**< (TWIHS_FILTR) PAD Filter Enable Mask */ +#define TWIHS_FILTR_PADFEN TWIHS_FILTR_PADFEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFEN_Msk instead */ +#define TWIHS_FILTR_PADFCFG_Pos 2 /**< (TWIHS_FILTR) PAD Filter Config Position */ +#define TWIHS_FILTR_PADFCFG_Msk (_U_(0x1) << TWIHS_FILTR_PADFCFG_Pos) /**< (TWIHS_FILTR) PAD Filter Config Mask */ +#define TWIHS_FILTR_PADFCFG TWIHS_FILTR_PADFCFG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_FILTR_PADFCFG_Msk instead */ +#define TWIHS_FILTR_THRES_Pos 8 /**< (TWIHS_FILTR) Digital Filter Threshold Position */ +#define TWIHS_FILTR_THRES_Msk (_U_(0x7) << TWIHS_FILTR_THRES_Pos) /**< (TWIHS_FILTR) Digital Filter Threshold Mask */ +#define TWIHS_FILTR_THRES(value) (TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)) +#define TWIHS_FILTR_MASK _U_(0x707) /**< \deprecated (TWIHS_FILTR) Register MASK (Use TWIHS_FILTR_Msk instead) */ +#define TWIHS_FILTR_Msk _U_(0x707) /**< (TWIHS_FILTR) Register Mask */ + + +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4c) (R/W 32) SleepWalking Matching Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SADR1:7; /**< bit: 0..6 Slave Address 1 */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t SADR2:7; /**< bit: 8..14 Slave Address 2 */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t SADR3:7; /**< bit: 16..22 Slave Address 3 */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t DATAM:8; /**< bit: 24..31 Data Match */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_SWMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_SWMR_OFFSET (0x4C) /**< (TWIHS_SWMR) SleepWalking Matching Register Offset */ + +#define TWIHS_SWMR_SADR1_Pos 0 /**< (TWIHS_SWMR) Slave Address 1 Position */ +#define TWIHS_SWMR_SADR1_Msk (_U_(0x7F) << TWIHS_SWMR_SADR1_Pos) /**< (TWIHS_SWMR) Slave Address 1 Mask */ +#define TWIHS_SWMR_SADR1(value) (TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)) +#define TWIHS_SWMR_SADR2_Pos 8 /**< (TWIHS_SWMR) Slave Address 2 Position */ +#define TWIHS_SWMR_SADR2_Msk (_U_(0x7F) << TWIHS_SWMR_SADR2_Pos) /**< (TWIHS_SWMR) Slave Address 2 Mask */ +#define TWIHS_SWMR_SADR2(value) (TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)) +#define TWIHS_SWMR_SADR3_Pos 16 /**< (TWIHS_SWMR) Slave Address 3 Position */ +#define TWIHS_SWMR_SADR3_Msk (_U_(0x7F) << TWIHS_SWMR_SADR3_Pos) /**< (TWIHS_SWMR) Slave Address 3 Mask */ +#define TWIHS_SWMR_SADR3(value) (TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)) +#define TWIHS_SWMR_DATAM_Pos 24 /**< (TWIHS_SWMR) Data Match Position */ +#define TWIHS_SWMR_DATAM_Msk (_U_(0xFF) << TWIHS_SWMR_DATAM_Pos) /**< (TWIHS_SWMR) Data Match Mask */ +#define TWIHS_SWMR_DATAM(value) (TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)) +#define TWIHS_SWMR_MASK _U_(0xFF7F7F7F) /**< \deprecated (TWIHS_SWMR) Register MASK (Use TWIHS_SWMR_Msk instead) */ +#define TWIHS_SWMR_Msk _U_(0xFF7F7F7F) /**< (TWIHS_SWMR) Register Mask */ + + +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_WPMR_OFFSET (0xE4) /**< (TWIHS_WPMR) Write Protection Mode Register Offset */ + +#define TWIHS_WPMR_WPEN_Pos 0 /**< (TWIHS_WPMR) Write Protection Enable Position */ +#define TWIHS_WPMR_WPEN_Msk (_U_(0x1) << TWIHS_WPMR_WPEN_Pos) /**< (TWIHS_WPMR) Write Protection Enable Mask */ +#define TWIHS_WPMR_WPEN TWIHS_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPMR_WPEN_Msk instead */ +#define TWIHS_WPMR_WPKEY_Pos 8 /**< (TWIHS_WPMR) Write Protection Key Position */ +#define TWIHS_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Write Protection Key Mask */ +#define TWIHS_WPMR_WPKEY(value) (TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)) +#define TWIHS_WPMR_WPKEY_PASSWD_Val _U_(0x545749) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +#define TWIHS_WPMR_WPKEY_PASSWD (TWIHS_WPMR_WPKEY_PASSWD_Val << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 Position */ +#define TWIHS_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPMR) Register MASK (Use TWIHS_WPMR_Msk instead) */ +#define TWIHS_WPMR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPMR) Register Mask */ + + +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:24; /**< bit: 8..31 Write Protection Violation Source */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} TWIHS_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TWIHS_WPSR_OFFSET (0xE8) /**< (TWIHS_WPSR) Write Protection Status Register Offset */ + +#define TWIHS_WPSR_WPVS_Pos 0 /**< (TWIHS_WPSR) Write Protection Violation Status Position */ +#define TWIHS_WPSR_WPVS_Msk (_U_(0x1) << TWIHS_WPSR_WPVS_Pos) /**< (TWIHS_WPSR) Write Protection Violation Status Mask */ +#define TWIHS_WPSR_WPVS TWIHS_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TWIHS_WPSR_WPVS_Msk instead */ +#define TWIHS_WPSR_WPVSRC_Pos 8 /**< (TWIHS_WPSR) Write Protection Violation Source Position */ +#define TWIHS_WPSR_WPVSRC_Msk (_U_(0xFFFFFF) << TWIHS_WPSR_WPVSRC_Pos) /**< (TWIHS_WPSR) Write Protection Violation Source Mask */ +#define TWIHS_WPSR_WPVSRC(value) (TWIHS_WPSR_WPVSRC_Msk & ((value) << TWIHS_WPSR_WPVSRC_Pos)) +#define TWIHS_WPSR_MASK _U_(0xFFFFFF01) /**< \deprecated (TWIHS_WPSR) Register MASK (Use TWIHS_WPSR_Msk instead) */ +#define TWIHS_WPSR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief TWIHS hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< (TWIHS Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< (TWIHS Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< (TWIHS Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< (TWIHS Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< (TWIHS Offset: 0x10) Clock Waveform Generator Register */ + __I uint8_t Reserved1[12]; + __I uint32_t TWIHS_SR; /**< (TWIHS Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< (TWIHS Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< (TWIHS Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< (TWIHS Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< (TWIHS Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< (TWIHS Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< (TWIHS Offset: 0x38) SMBus Timing Register */ + __I uint8_t Reserved2[8]; + __IO uint32_t TWIHS_FILTR; /**< (TWIHS Offset: 0x44) Filter Register */ + __I uint8_t Reserved3[4]; + __IO uint32_t TWIHS_SWMR; /**< (TWIHS Offset: 0x4C) SleepWalking Matching Register */ + __I uint8_t Reserved4[148]; + __IO uint32_t TWIHS_WPMR; /**< (TWIHS Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< (TWIHS Offset: 0xE8) Write Protection Status Register */ +} Twihs; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief TWIHS hardware registers */ +typedef struct { + __O TWIHS_CR_Type TWIHS_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO TWIHS_MMR_Type TWIHS_MMR; /**< Offset: 0x04 (R/W 32) Master Mode Register */ + __IO TWIHS_SMR_Type TWIHS_SMR; /**< Offset: 0x08 (R/W 32) Slave Mode Register */ + __IO TWIHS_IADR_Type TWIHS_IADR; /**< Offset: 0x0C (R/W 32) Internal Address Register */ + __IO TWIHS_CWGR_Type TWIHS_CWGR; /**< Offset: 0x10 (R/W 32) Clock Waveform Generator Register */ + __I uint8_t Reserved1[12]; + __I TWIHS_SR_Type TWIHS_SR; /**< Offset: 0x20 (R/ 32) Status Register */ + __O TWIHS_IER_Type TWIHS_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O TWIHS_IDR_Type TWIHS_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I TWIHS_IMR_Type TWIHS_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I TWIHS_RHR_Type TWIHS_RHR; /**< Offset: 0x30 (R/ 32) Receive Holding Register */ + __O TWIHS_THR_Type TWIHS_THR; /**< Offset: 0x34 ( /W 32) Transmit Holding Register */ + __IO TWIHS_SMBTR_Type TWIHS_SMBTR; /**< Offset: 0x38 (R/W 32) SMBus Timing Register */ + __I uint8_t Reserved2[8]; + __IO TWIHS_FILTR_Type TWIHS_FILTR; /**< Offset: 0x44 (R/W 32) Filter Register */ + __I uint8_t Reserved3[4]; + __IO TWIHS_SWMR_Type TWIHS_SWMR; /**< Offset: 0x4C (R/W 32) SleepWalking Matching Register */ + __I uint8_t Reserved4[148]; + __IO TWIHS_WPMR_Type TWIHS_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I TWIHS_WPSR_Type TWIHS_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Twihs; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Two-wire Interface High Speed */ + +#endif /* _SAME70_TWIHS_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/uart.h b/bsp/microchip/same70/bsp/same70b/include/component/uart.h new file mode 100644 index 0000000000..2fbc679a0e --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/uart.h @@ -0,0 +1,536 @@ +/** + * \file + * + * \brief Component description for UART + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART_COMPONENT_H_ +#define _SAME70_UART_COMPONENT_H_ +#define _SAME70_UART_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Universal Asynchronous Receiver Transmitter + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR UART */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define UART_6418 /**< (UART) Module ID */ +#define REV_UART R /**< (UART) Module revision */ + +/* -------- UART_CR : (UART Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RSTRX:1; /**< bit: 2 Reset Receiver */ + uint32_t RSTTX:1; /**< bit: 3 Reset Transmitter */ + uint32_t RXEN:1; /**< bit: 4 Receiver Enable */ + uint32_t RXDIS:1; /**< bit: 5 Receiver Disable */ + uint32_t TXEN:1; /**< bit: 6 Transmitter Enable */ + uint32_t TXDIS:1; /**< bit: 7 Transmitter Disable */ + uint32_t RSTSTA:1; /**< bit: 8 Reset Status */ + uint32_t :3; /**< bit: 9..11 Reserved */ + uint32_t REQCLR:1; /**< bit: 12 Request Clear */ + uint32_t :19; /**< bit: 13..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_CR_OFFSET (0x00) /**< (UART_CR) Control Register Offset */ + +#define UART_CR_RSTRX_Pos 2 /**< (UART_CR) Reset Receiver Position */ +#define UART_CR_RSTRX_Msk (_U_(0x1) << UART_CR_RSTRX_Pos) /**< (UART_CR) Reset Receiver Mask */ +#define UART_CR_RSTRX UART_CR_RSTRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTRX_Msk instead */ +#define UART_CR_RSTTX_Pos 3 /**< (UART_CR) Reset Transmitter Position */ +#define UART_CR_RSTTX_Msk (_U_(0x1) << UART_CR_RSTTX_Pos) /**< (UART_CR) Reset Transmitter Mask */ +#define UART_CR_RSTTX UART_CR_RSTTX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTTX_Msk instead */ +#define UART_CR_RXEN_Pos 4 /**< (UART_CR) Receiver Enable Position */ +#define UART_CR_RXEN_Msk (_U_(0x1) << UART_CR_RXEN_Pos) /**< (UART_CR) Receiver Enable Mask */ +#define UART_CR_RXEN UART_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXEN_Msk instead */ +#define UART_CR_RXDIS_Pos 5 /**< (UART_CR) Receiver Disable Position */ +#define UART_CR_RXDIS_Msk (_U_(0x1) << UART_CR_RXDIS_Pos) /**< (UART_CR) Receiver Disable Mask */ +#define UART_CR_RXDIS UART_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXDIS_Msk instead */ +#define UART_CR_TXEN_Pos 6 /**< (UART_CR) Transmitter Enable Position */ +#define UART_CR_TXEN_Msk (_U_(0x1) << UART_CR_TXEN_Pos) /**< (UART_CR) Transmitter Enable Mask */ +#define UART_CR_TXEN UART_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXEN_Msk instead */ +#define UART_CR_TXDIS_Pos 7 /**< (UART_CR) Transmitter Disable Position */ +#define UART_CR_TXDIS_Msk (_U_(0x1) << UART_CR_TXDIS_Pos) /**< (UART_CR) Transmitter Disable Mask */ +#define UART_CR_TXDIS UART_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXDIS_Msk instead */ +#define UART_CR_RSTSTA_Pos 8 /**< (UART_CR) Reset Status Position */ +#define UART_CR_RSTSTA_Msk (_U_(0x1) << UART_CR_RSTSTA_Pos) /**< (UART_CR) Reset Status Mask */ +#define UART_CR_RSTSTA UART_CR_RSTSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTSTA_Msk instead */ +#define UART_CR_REQCLR_Pos 12 /**< (UART_CR) Request Clear Position */ +#define UART_CR_REQCLR_Msk (_U_(0x1) << UART_CR_REQCLR_Pos) /**< (UART_CR) Request Clear Mask */ +#define UART_CR_REQCLR UART_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_REQCLR_Msk instead */ +#define UART_CR_MASK _U_(0x11FC) /**< \deprecated (UART_CR) Register MASK (Use UART_CR_Msk instead) */ +#define UART_CR_Msk _U_(0x11FC) /**< (UART_CR) Register Mask */ + + +/* -------- UART_MR : (UART Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t FILTER:1; /**< bit: 4 Receiver Digital Filter */ + uint32_t :4; /**< bit: 5..8 Reserved */ + uint32_t PAR:3; /**< bit: 9..11 Parity Type */ + uint32_t BRSRCCK:1; /**< bit: 12 Baud Rate Source Clock */ + uint32_t :1; /**< bit: 13 Reserved */ + uint32_t CHMODE:2; /**< bit: 14..15 Channel Mode */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_MR_OFFSET (0x04) /**< (UART_MR) Mode Register Offset */ + +#define UART_MR_FILTER_Pos 4 /**< (UART_MR) Receiver Digital Filter Position */ +#define UART_MR_FILTER_Msk (_U_(0x1) << UART_MR_FILTER_Pos) /**< (UART_MR) Receiver Digital Filter Mask */ +#define UART_MR_FILTER UART_MR_FILTER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_FILTER_Msk instead */ +#define UART_MR_FILTER_DISABLED_Val _U_(0x0) /**< (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED_Val _U_(0x1) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_FILTER_DISABLED (UART_MR_FILTER_DISABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART does not filter the receive line. Position */ +#define UART_MR_FILTER_ENABLED (UART_MR_FILTER_ENABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). Position */ +#define UART_MR_PAR_Pos 9 /**< (UART_MR) Parity Type Position */ +#define UART_MR_PAR_Msk (_U_(0x7) << UART_MR_PAR_Pos) /**< (UART_MR) Parity Type Mask */ +#define UART_MR_PAR(value) (UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)) +#define UART_MR_PAR_EVEN_Val _U_(0x0) /**< (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD_Val _U_(0x1) /**< (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE_Val _U_(0x2) /**< (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK_Val _U_(0x3) /**< (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO_Val _U_(0x4) /**< (UART_MR) No parity */ +#define UART_MR_PAR_EVEN (UART_MR_PAR_EVEN_Val << UART_MR_PAR_Pos) /**< (UART_MR) Even Parity Position */ +#define UART_MR_PAR_ODD (UART_MR_PAR_ODD_Val << UART_MR_PAR_Pos) /**< (UART_MR) Odd Parity Position */ +#define UART_MR_PAR_SPACE (UART_MR_PAR_SPACE_Val << UART_MR_PAR_Pos) /**< (UART_MR) Space: parity forced to 0 Position */ +#define UART_MR_PAR_MARK (UART_MR_PAR_MARK_Val << UART_MR_PAR_Pos) /**< (UART_MR) Mark: parity forced to 1 Position */ +#define UART_MR_PAR_NO (UART_MR_PAR_NO_Val << UART_MR_PAR_Pos) /**< (UART_MR) No parity Position */ +#define UART_MR_BRSRCCK_Pos 12 /**< (UART_MR) Baud Rate Source Clock Position */ +#define UART_MR_BRSRCCK_Msk (_U_(0x1) << UART_MR_BRSRCCK_Pos) /**< (UART_MR) Baud Rate Source Clock Mask */ +#define UART_MR_BRSRCCK UART_MR_BRSRCCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_BRSRCCK_Msk instead */ +#define UART_MR_BRSRCCK_PERIPH_CLK_Val _U_(0x0) /**< (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK_Val _U_(0x1) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_BRSRCCK_PERIPH_CLK (UART_MR_BRSRCCK_PERIPH_CLK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by the peripheral clock Position */ +#define UART_MR_BRSRCCK_PMC_PCK (UART_MR_BRSRCCK_PMC_PCK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). Position */ +#define UART_MR_CHMODE_Pos 14 /**< (UART_MR) Channel Mode Position */ +#define UART_MR_CHMODE_Msk (_U_(0x3) << UART_MR_CHMODE_Pos) /**< (UART_MR) Channel Mode Mask */ +#define UART_MR_CHMODE(value) (UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)) +#define UART_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (UART_MR) Remote loopback */ +#define UART_MR_CHMODE_NORMAL (UART_MR_CHMODE_NORMAL_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Normal mode Position */ +#define UART_MR_CHMODE_AUTOMATIC (UART_MR_CHMODE_AUTOMATIC_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Automatic echo Position */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (UART_MR_CHMODE_LOCAL_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Local loopback Position */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (UART_MR_CHMODE_REMOTE_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Remote loopback Position */ +#define UART_MR_MASK _U_(0xDE10) /**< \deprecated (UART_MR) Register MASK (Use UART_MR_Msk instead) */ +#define UART_MR_Msk _U_(0xDE10) /**< (UART_MR) Register Mask */ + + +/* -------- UART_IER : (UART Offset: 0x08) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 Enable RXRDY Interrupt */ + uint32_t TXRDY:1; /**< bit: 1 Enable TXRDY Interrupt */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Enable Overrun Error Interrupt */ + uint32_t FRAME:1; /**< bit: 6 Enable Framing Error Interrupt */ + uint32_t PARE:1; /**< bit: 7 Enable Parity Error Interrupt */ + uint32_t :1; /**< bit: 8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 Enable TXEMPTY Interrupt */ + uint32_t :5; /**< bit: 10..14 Reserved */ + uint32_t CMP:1; /**< bit: 15 Enable Comparison Interrupt */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_IER_OFFSET (0x08) /**< (UART_IER) Interrupt Enable Register Offset */ + +#define UART_IER_RXRDY_Pos 0 /**< (UART_IER) Enable RXRDY Interrupt Position */ +#define UART_IER_RXRDY_Msk (_U_(0x1) << UART_IER_RXRDY_Pos) /**< (UART_IER) Enable RXRDY Interrupt Mask */ +#define UART_IER_RXRDY UART_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_RXRDY_Msk instead */ +#define UART_IER_TXRDY_Pos 1 /**< (UART_IER) Enable TXRDY Interrupt Position */ +#define UART_IER_TXRDY_Msk (_U_(0x1) << UART_IER_TXRDY_Pos) /**< (UART_IER) Enable TXRDY Interrupt Mask */ +#define UART_IER_TXRDY UART_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXRDY_Msk instead */ +#define UART_IER_OVRE_Pos 5 /**< (UART_IER) Enable Overrun Error Interrupt Position */ +#define UART_IER_OVRE_Msk (_U_(0x1) << UART_IER_OVRE_Pos) /**< (UART_IER) Enable Overrun Error Interrupt Mask */ +#define UART_IER_OVRE UART_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_OVRE_Msk instead */ +#define UART_IER_FRAME_Pos 6 /**< (UART_IER) Enable Framing Error Interrupt Position */ +#define UART_IER_FRAME_Msk (_U_(0x1) << UART_IER_FRAME_Pos) /**< (UART_IER) Enable Framing Error Interrupt Mask */ +#define UART_IER_FRAME UART_IER_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_FRAME_Msk instead */ +#define UART_IER_PARE_Pos 7 /**< (UART_IER) Enable Parity Error Interrupt Position */ +#define UART_IER_PARE_Msk (_U_(0x1) << UART_IER_PARE_Pos) /**< (UART_IER) Enable Parity Error Interrupt Mask */ +#define UART_IER_PARE UART_IER_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_PARE_Msk instead */ +#define UART_IER_TXEMPTY_Pos 9 /**< (UART_IER) Enable TXEMPTY Interrupt Position */ +#define UART_IER_TXEMPTY_Msk (_U_(0x1) << UART_IER_TXEMPTY_Pos) /**< (UART_IER) Enable TXEMPTY Interrupt Mask */ +#define UART_IER_TXEMPTY UART_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXEMPTY_Msk instead */ +#define UART_IER_CMP_Pos 15 /**< (UART_IER) Enable Comparison Interrupt Position */ +#define UART_IER_CMP_Msk (_U_(0x1) << UART_IER_CMP_Pos) /**< (UART_IER) Enable Comparison Interrupt Mask */ +#define UART_IER_CMP UART_IER_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_CMP_Msk instead */ +#define UART_IER_MASK _U_(0x82E3) /**< \deprecated (UART_IER) Register MASK (Use UART_IER_Msk instead) */ +#define UART_IER_Msk _U_(0x82E3) /**< (UART_IER) Register Mask */ + + +/* -------- UART_IDR : (UART Offset: 0x0c) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 Disable RXRDY Interrupt */ + uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Disable Overrun Error Interrupt */ + uint32_t FRAME:1; /**< bit: 6 Disable Framing Error Interrupt */ + uint32_t PARE:1; /**< bit: 7 Disable Parity Error Interrupt */ + uint32_t :1; /**< bit: 8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 Disable TXEMPTY Interrupt */ + uint32_t :5; /**< bit: 10..14 Reserved */ + uint32_t CMP:1; /**< bit: 15 Disable Comparison Interrupt */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_IDR_OFFSET (0x0C) /**< (UART_IDR) Interrupt Disable Register Offset */ + +#define UART_IDR_RXRDY_Pos 0 /**< (UART_IDR) Disable RXRDY Interrupt Position */ +#define UART_IDR_RXRDY_Msk (_U_(0x1) << UART_IDR_RXRDY_Pos) /**< (UART_IDR) Disable RXRDY Interrupt Mask */ +#define UART_IDR_RXRDY UART_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_RXRDY_Msk instead */ +#define UART_IDR_TXRDY_Pos 1 /**< (UART_IDR) Disable TXRDY Interrupt Position */ +#define UART_IDR_TXRDY_Msk (_U_(0x1) << UART_IDR_TXRDY_Pos) /**< (UART_IDR) Disable TXRDY Interrupt Mask */ +#define UART_IDR_TXRDY UART_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXRDY_Msk instead */ +#define UART_IDR_OVRE_Pos 5 /**< (UART_IDR) Disable Overrun Error Interrupt Position */ +#define UART_IDR_OVRE_Msk (_U_(0x1) << UART_IDR_OVRE_Pos) /**< (UART_IDR) Disable Overrun Error Interrupt Mask */ +#define UART_IDR_OVRE UART_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_OVRE_Msk instead */ +#define UART_IDR_FRAME_Pos 6 /**< (UART_IDR) Disable Framing Error Interrupt Position */ +#define UART_IDR_FRAME_Msk (_U_(0x1) << UART_IDR_FRAME_Pos) /**< (UART_IDR) Disable Framing Error Interrupt Mask */ +#define UART_IDR_FRAME UART_IDR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_FRAME_Msk instead */ +#define UART_IDR_PARE_Pos 7 /**< (UART_IDR) Disable Parity Error Interrupt Position */ +#define UART_IDR_PARE_Msk (_U_(0x1) << UART_IDR_PARE_Pos) /**< (UART_IDR) Disable Parity Error Interrupt Mask */ +#define UART_IDR_PARE UART_IDR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_PARE_Msk instead */ +#define UART_IDR_TXEMPTY_Pos 9 /**< (UART_IDR) Disable TXEMPTY Interrupt Position */ +#define UART_IDR_TXEMPTY_Msk (_U_(0x1) << UART_IDR_TXEMPTY_Pos) /**< (UART_IDR) Disable TXEMPTY Interrupt Mask */ +#define UART_IDR_TXEMPTY UART_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXEMPTY_Msk instead */ +#define UART_IDR_CMP_Pos 15 /**< (UART_IDR) Disable Comparison Interrupt Position */ +#define UART_IDR_CMP_Msk (_U_(0x1) << UART_IDR_CMP_Pos) /**< (UART_IDR) Disable Comparison Interrupt Mask */ +#define UART_IDR_CMP UART_IDR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_CMP_Msk instead */ +#define UART_IDR_MASK _U_(0x82E3) /**< \deprecated (UART_IDR) Register MASK (Use UART_IDR_Msk instead) */ +#define UART_IDR_Msk _U_(0x82E3) /**< (UART_IDR) Register Mask */ + + +/* -------- UART_IMR : (UART Offset: 0x10) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 Mask RXRDY Interrupt */ + uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Mask Overrun Error Interrupt */ + uint32_t FRAME:1; /**< bit: 6 Mask Framing Error Interrupt */ + uint32_t PARE:1; /**< bit: 7 Mask Parity Error Interrupt */ + uint32_t :1; /**< bit: 8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 Mask TXEMPTY Interrupt */ + uint32_t :5; /**< bit: 10..14 Reserved */ + uint32_t CMP:1; /**< bit: 15 Mask Comparison Interrupt */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_IMR_OFFSET (0x10) /**< (UART_IMR) Interrupt Mask Register Offset */ + +#define UART_IMR_RXRDY_Pos 0 /**< (UART_IMR) Mask RXRDY Interrupt Position */ +#define UART_IMR_RXRDY_Msk (_U_(0x1) << UART_IMR_RXRDY_Pos) /**< (UART_IMR) Mask RXRDY Interrupt Mask */ +#define UART_IMR_RXRDY UART_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_RXRDY_Msk instead */ +#define UART_IMR_TXRDY_Pos 1 /**< (UART_IMR) Disable TXRDY Interrupt Position */ +#define UART_IMR_TXRDY_Msk (_U_(0x1) << UART_IMR_TXRDY_Pos) /**< (UART_IMR) Disable TXRDY Interrupt Mask */ +#define UART_IMR_TXRDY UART_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXRDY_Msk instead */ +#define UART_IMR_OVRE_Pos 5 /**< (UART_IMR) Mask Overrun Error Interrupt Position */ +#define UART_IMR_OVRE_Msk (_U_(0x1) << UART_IMR_OVRE_Pos) /**< (UART_IMR) Mask Overrun Error Interrupt Mask */ +#define UART_IMR_OVRE UART_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_OVRE_Msk instead */ +#define UART_IMR_FRAME_Pos 6 /**< (UART_IMR) Mask Framing Error Interrupt Position */ +#define UART_IMR_FRAME_Msk (_U_(0x1) << UART_IMR_FRAME_Pos) /**< (UART_IMR) Mask Framing Error Interrupt Mask */ +#define UART_IMR_FRAME UART_IMR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_FRAME_Msk instead */ +#define UART_IMR_PARE_Pos 7 /**< (UART_IMR) Mask Parity Error Interrupt Position */ +#define UART_IMR_PARE_Msk (_U_(0x1) << UART_IMR_PARE_Pos) /**< (UART_IMR) Mask Parity Error Interrupt Mask */ +#define UART_IMR_PARE UART_IMR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_PARE_Msk instead */ +#define UART_IMR_TXEMPTY_Pos 9 /**< (UART_IMR) Mask TXEMPTY Interrupt Position */ +#define UART_IMR_TXEMPTY_Msk (_U_(0x1) << UART_IMR_TXEMPTY_Pos) /**< (UART_IMR) Mask TXEMPTY Interrupt Mask */ +#define UART_IMR_TXEMPTY UART_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXEMPTY_Msk instead */ +#define UART_IMR_CMP_Pos 15 /**< (UART_IMR) Mask Comparison Interrupt Position */ +#define UART_IMR_CMP_Msk (_U_(0x1) << UART_IMR_CMP_Pos) /**< (UART_IMR) Mask Comparison Interrupt Mask */ +#define UART_IMR_CMP UART_IMR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_CMP_Msk instead */ +#define UART_IMR_MASK _U_(0x82E3) /**< \deprecated (UART_IMR) Register MASK (Use UART_IMR_Msk instead) */ +#define UART_IMR_Msk _U_(0x82E3) /**< (UART_IMR) Register Mask */ + + +/* -------- UART_SR : (UART Offset: 0x14) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 Receiver Ready */ + uint32_t TXRDY:1; /**< bit: 1 Transmitter Ready */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Overrun Error */ + uint32_t FRAME:1; /**< bit: 6 Framing Error */ + uint32_t PARE:1; /**< bit: 7 Parity Error */ + uint32_t :1; /**< bit: 8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmitter Empty */ + uint32_t :5; /**< bit: 10..14 Reserved */ + uint32_t CMP:1; /**< bit: 15 Comparison Match */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_SR_OFFSET (0x14) /**< (UART_SR) Status Register Offset */ + +#define UART_SR_RXRDY_Pos 0 /**< (UART_SR) Receiver Ready Position */ +#define UART_SR_RXRDY_Msk (_U_(0x1) << UART_SR_RXRDY_Pos) /**< (UART_SR) Receiver Ready Mask */ +#define UART_SR_RXRDY UART_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_RXRDY_Msk instead */ +#define UART_SR_TXRDY_Pos 1 /**< (UART_SR) Transmitter Ready Position */ +#define UART_SR_TXRDY_Msk (_U_(0x1) << UART_SR_TXRDY_Pos) /**< (UART_SR) Transmitter Ready Mask */ +#define UART_SR_TXRDY UART_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXRDY_Msk instead */ +#define UART_SR_OVRE_Pos 5 /**< (UART_SR) Overrun Error Position */ +#define UART_SR_OVRE_Msk (_U_(0x1) << UART_SR_OVRE_Pos) /**< (UART_SR) Overrun Error Mask */ +#define UART_SR_OVRE UART_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_OVRE_Msk instead */ +#define UART_SR_FRAME_Pos 6 /**< (UART_SR) Framing Error Position */ +#define UART_SR_FRAME_Msk (_U_(0x1) << UART_SR_FRAME_Pos) /**< (UART_SR) Framing Error Mask */ +#define UART_SR_FRAME UART_SR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_FRAME_Msk instead */ +#define UART_SR_PARE_Pos 7 /**< (UART_SR) Parity Error Position */ +#define UART_SR_PARE_Msk (_U_(0x1) << UART_SR_PARE_Pos) /**< (UART_SR) Parity Error Mask */ +#define UART_SR_PARE UART_SR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_PARE_Msk instead */ +#define UART_SR_TXEMPTY_Pos 9 /**< (UART_SR) Transmitter Empty Position */ +#define UART_SR_TXEMPTY_Msk (_U_(0x1) << UART_SR_TXEMPTY_Pos) /**< (UART_SR) Transmitter Empty Mask */ +#define UART_SR_TXEMPTY UART_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXEMPTY_Msk instead */ +#define UART_SR_CMP_Pos 15 /**< (UART_SR) Comparison Match Position */ +#define UART_SR_CMP_Msk (_U_(0x1) << UART_SR_CMP_Pos) /**< (UART_SR) Comparison Match Mask */ +#define UART_SR_CMP UART_SR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_CMP_Msk instead */ +#define UART_SR_MASK _U_(0x82E3) /**< \deprecated (UART_SR) Register MASK (Use UART_SR_Msk instead) */ +#define UART_SR_Msk _U_(0x82E3) /**< (UART_SR) Register Mask */ + + +/* -------- UART_RHR : (UART Offset: 0x18) (R/ 32) Receive Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXCHR:8; /**< bit: 0..7 Received Character */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_RHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_RHR_OFFSET (0x18) /**< (UART_RHR) Receive Holding Register Offset */ + +#define UART_RHR_RXCHR_Pos 0 /**< (UART_RHR) Received Character Position */ +#define UART_RHR_RXCHR_Msk (_U_(0xFF) << UART_RHR_RXCHR_Pos) /**< (UART_RHR) Received Character Mask */ +#define UART_RHR_RXCHR(value) (UART_RHR_RXCHR_Msk & ((value) << UART_RHR_RXCHR_Pos)) +#define UART_RHR_MASK _U_(0xFF) /**< \deprecated (UART_RHR) Register MASK (Use UART_RHR_Msk instead) */ +#define UART_RHR_Msk _U_(0xFF) /**< (UART_RHR) Register Mask */ + + +/* -------- UART_THR : (UART Offset: 0x1c) (/W 32) Transmit Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCHR:8; /**< bit: 0..7 Character to be Transmitted */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_THR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_THR_OFFSET (0x1C) /**< (UART_THR) Transmit Holding Register Offset */ + +#define UART_THR_TXCHR_Pos 0 /**< (UART_THR) Character to be Transmitted Position */ +#define UART_THR_TXCHR_Msk (_U_(0xFF) << UART_THR_TXCHR_Pos) /**< (UART_THR) Character to be Transmitted Mask */ +#define UART_THR_TXCHR(value) (UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)) +#define UART_THR_MASK _U_(0xFF) /**< \deprecated (UART_THR) Register MASK (Use UART_THR_Msk instead) */ +#define UART_THR_Msk _U_(0xFF) /**< (UART_THR) Register Mask */ + + +/* -------- UART_BRGR : (UART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CD:16; /**< bit: 0..15 Clock Divisor */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_BRGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_BRGR_OFFSET (0x20) /**< (UART_BRGR) Baud Rate Generator Register Offset */ + +#define UART_BRGR_CD_Pos 0 /**< (UART_BRGR) Clock Divisor Position */ +#define UART_BRGR_CD_Msk (_U_(0xFFFF) << UART_BRGR_CD_Pos) /**< (UART_BRGR) Clock Divisor Mask */ +#define UART_BRGR_CD(value) (UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)) +#define UART_BRGR_MASK _U_(0xFFFF) /**< \deprecated (UART_BRGR) Register MASK (Use UART_BRGR_Msk instead) */ +#define UART_BRGR_Msk _U_(0xFFFF) /**< (UART_BRGR) Register Mask */ + + +/* -------- UART_CMPR : (UART Offset: 0x24) (R/W 32) Comparison Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t VAL1:8; /**< bit: 0..7 First Comparison Value for Received Character */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t CMPMODE:1; /**< bit: 12 Comparison Mode */ + uint32_t :1; /**< bit: 13 Reserved */ + uint32_t CMPPAR:1; /**< bit: 14 Compare Parity */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t VAL2:8; /**< bit: 16..23 Second Comparison Value for Received Character */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_CMPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_CMPR_OFFSET (0x24) /**< (UART_CMPR) Comparison Register Offset */ + +#define UART_CMPR_VAL1_Pos 0 /**< (UART_CMPR) First Comparison Value for Received Character Position */ +#define UART_CMPR_VAL1_Msk (_U_(0xFF) << UART_CMPR_VAL1_Pos) /**< (UART_CMPR) First Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL1(value) (UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)) +#define UART_CMPR_CMPMODE_Pos 12 /**< (UART_CMPR) Comparison Mode Position */ +#define UART_CMPR_CMPMODE_Msk (_U_(0x1) << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison Mode Mask */ +#define UART_CMPR_CMPMODE UART_CMPR_CMPMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPMODE_Msk instead */ +#define UART_CMPR_CMPMODE_FLAG_ONLY_Val _U_(0x0) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION_Val _U_(0x1) /**< (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (UART_CMPR_CMPMODE_FLAG_ONLY_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. Position */ +#define UART_CMPR_CMPMODE_START_CONDITION (UART_CMPR_CMPMODE_START_CONDITION_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison condition must be met to start reception. Position */ +#define UART_CMPR_CMPPAR_Pos 14 /**< (UART_CMPR) Compare Parity Position */ +#define UART_CMPR_CMPPAR_Msk (_U_(0x1) << UART_CMPR_CMPPAR_Pos) /**< (UART_CMPR) Compare Parity Mask */ +#define UART_CMPR_CMPPAR UART_CMPR_CMPPAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPPAR_Msk instead */ +#define UART_CMPR_VAL2_Pos 16 /**< (UART_CMPR) Second Comparison Value for Received Character Position */ +#define UART_CMPR_VAL2_Msk (_U_(0xFF) << UART_CMPR_VAL2_Pos) /**< (UART_CMPR) Second Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL2(value) (UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)) +#define UART_CMPR_MASK _U_(0xFF50FF) /**< \deprecated (UART_CMPR) Register MASK (Use UART_CMPR_Msk instead) */ +#define UART_CMPR_Msk _U_(0xFF50FF) /**< (UART_CMPR) Register Mask */ + + +/* -------- UART_WPMR : (UART Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UART_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UART_WPMR_OFFSET (0xE4) /**< (UART_WPMR) Write Protection Mode Register Offset */ + +#define UART_WPMR_WPEN_Pos 0 /**< (UART_WPMR) Write Protection Enable Position */ +#define UART_WPMR_WPEN_Msk (_U_(0x1) << UART_WPMR_WPEN_Pos) /**< (UART_WPMR) Write Protection Enable Mask */ +#define UART_WPMR_WPEN UART_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_WPMR_WPEN_Msk instead */ +#define UART_WPMR_WPKEY_Pos 8 /**< (UART_WPMR) Write Protection Key Position */ +#define UART_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Write Protection Key Mask */ +#define UART_WPMR_WPKEY(value) (UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)) +#define UART_WPMR_WPKEY_PASSWD_Val _U_(0x554152) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define UART_WPMR_WPKEY_PASSWD (UART_WPMR_WPKEY_PASSWD_Val << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define UART_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (UART_WPMR) Register MASK (Use UART_WPMR_Msk instead) */ +#define UART_WPMR_Msk _U_(0xFFFFFF01) /**< (UART_WPMR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief UART hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< (UART Offset: 0x00) Control Register */ + __IO uint32_t UART_MR; /**< (UART Offset: 0x04) Mode Register */ + __O uint32_t UART_IER; /**< (UART Offset: 0x08) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< (UART Offset: 0x0C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< (UART Offset: 0x10) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< (UART Offset: 0x14) Status Register */ + __I uint32_t UART_RHR; /**< (UART Offset: 0x18) Receive Holding Register */ + __O uint32_t UART_THR; /**< (UART Offset: 0x1C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< (UART Offset: 0x20) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< (UART Offset: 0x24) Comparison Register */ + __I uint8_t Reserved1[188]; + __IO uint32_t UART_WPMR; /**< (UART Offset: 0xE4) Write Protection Mode Register */ +} Uart; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief UART hardware registers */ +typedef struct { + __O UART_CR_Type UART_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO UART_MR_Type UART_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O UART_IER_Type UART_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O UART_IDR_Type UART_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I UART_IMR_Type UART_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I UART_SR_Type UART_SR; /**< Offset: 0x14 (R/ 32) Status Register */ + __I UART_RHR_Type UART_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O UART_THR_Type UART_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO UART_BRGR_Type UART_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO UART_CMPR_Type UART_CMPR; /**< Offset: 0x24 (R/W 32) Comparison Register */ + __I uint8_t Reserved1[188]; + __IO UART_WPMR_Type UART_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} Uart; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Universal Asynchronous Receiver Transmitter */ + +#endif /* _SAME70_UART_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/usart.h b/bsp/microchip/same70/bsp/same70b/include/component/usart.h new file mode 100644 index 0000000000..aa6062af67 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/usart.h @@ -0,0 +1,2069 @@ +/** + * \file + * + * \brief Component description for USART + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USART_COMPONENT_H_ +#define _SAME70_USART_COMPONENT_H_ +#define _SAME70_USART_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Universal Synchronous Asynchronous Receiver Transmitter + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR USART */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define USART_6089 /**< (USART) Module ID */ +#define REV_USART ZW /**< (USART) Module revision */ + +/* -------- US_CR : (USART Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RSTRX:1; /**< bit: 2 Reset Receiver */ + uint32_t RSTTX:1; /**< bit: 3 Reset Transmitter */ + uint32_t RXEN:1; /**< bit: 4 Receiver Enable */ + uint32_t RXDIS:1; /**< bit: 5 Receiver Disable */ + uint32_t TXEN:1; /**< bit: 6 Transmitter Enable */ + uint32_t TXDIS:1; /**< bit: 7 Transmitter Disable */ + uint32_t RSTSTA:1; /**< bit: 8 Reset Status Bits */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :9; /**< bit: 0..8 Reserved */ + uint32_t STTBRK:1; /**< bit: 9 Start Break */ + uint32_t STPBRK:1; /**< bit: 10 Stop Break */ + uint32_t STTTO:1; /**< bit: 11 Clear TIMEOUT Flag and Start Timeout After Next Character Received */ + uint32_t SENDA:1; /**< bit: 12 Send Address */ + uint32_t RSTIT:1; /**< bit: 13 Reset Iterations */ + uint32_t RSTNACK:1; /**< bit: 14 Reset Non Acknowledge */ + uint32_t RETTO:1; /**< bit: 15 Start Timeout Immediately */ + uint32_t DTREN:1; /**< bit: 16 Data Terminal Ready Enable */ + uint32_t DTRDIS:1; /**< bit: 17 Data Terminal Ready Disable */ + uint32_t RTSEN:1; /**< bit: 18 Request to Send Enable */ + uint32_t RTSDIS:1; /**< bit: 19 Request to Send Disable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // SPI mode + uint32_t :18; /**< bit: 0..17 Reserved */ + uint32_t FCS:1; /**< bit: 18 Force SPI Chip Select */ + uint32_t RCS:1; /**< bit: 19 Release SPI Chip Select */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + struct { // LIN mode + uint32_t :20; /**< bit: 0..19 Reserved */ + uint32_t LINABT:1; /**< bit: 20 Abort LIN Transmission */ + uint32_t LINWKUP:1; /**< bit: 21 Send LIN Wakeup Signal */ + uint32_t :10; /**< bit: 22..31 Reserved */ + } LIN; /**< Structure used for LIN mode access */ + uint32_t reg; /**< Type used for register access */ +} US_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_CR_OFFSET (0x00) /**< (US_CR) Control Register Offset */ + +#define US_CR_RSTRX_Pos 2 /**< (US_CR) Reset Receiver Position */ +#define US_CR_RSTRX_Msk (_U_(0x1) << US_CR_RSTRX_Pos) /**< (US_CR) Reset Receiver Mask */ +#define US_CR_RSTRX US_CR_RSTRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RSTRX_Msk instead */ +#define US_CR_RSTTX_Pos 3 /**< (US_CR) Reset Transmitter Position */ +#define US_CR_RSTTX_Msk (_U_(0x1) << US_CR_RSTTX_Pos) /**< (US_CR) Reset Transmitter Mask */ +#define US_CR_RSTTX US_CR_RSTTX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RSTTX_Msk instead */ +#define US_CR_RXEN_Pos 4 /**< (US_CR) Receiver Enable Position */ +#define US_CR_RXEN_Msk (_U_(0x1) << US_CR_RXEN_Pos) /**< (US_CR) Receiver Enable Mask */ +#define US_CR_RXEN US_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RXEN_Msk instead */ +#define US_CR_RXDIS_Pos 5 /**< (US_CR) Receiver Disable Position */ +#define US_CR_RXDIS_Msk (_U_(0x1) << US_CR_RXDIS_Pos) /**< (US_CR) Receiver Disable Mask */ +#define US_CR_RXDIS US_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RXDIS_Msk instead */ +#define US_CR_TXEN_Pos 6 /**< (US_CR) Transmitter Enable Position */ +#define US_CR_TXEN_Msk (_U_(0x1) << US_CR_TXEN_Pos) /**< (US_CR) Transmitter Enable Mask */ +#define US_CR_TXEN US_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_TXEN_Msk instead */ +#define US_CR_TXDIS_Pos 7 /**< (US_CR) Transmitter Disable Position */ +#define US_CR_TXDIS_Msk (_U_(0x1) << US_CR_TXDIS_Pos) /**< (US_CR) Transmitter Disable Mask */ +#define US_CR_TXDIS US_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_TXDIS_Msk instead */ +#define US_CR_RSTSTA_Pos 8 /**< (US_CR) Reset Status Bits Position */ +#define US_CR_RSTSTA_Msk (_U_(0x1) << US_CR_RSTSTA_Pos) /**< (US_CR) Reset Status Bits Mask */ +#define US_CR_RSTSTA US_CR_RSTSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_RSTSTA_Msk instead */ +#define US_CR_MASK _U_(0x1FC) /**< \deprecated (US_CR) Register MASK (Use US_CR_Msk instead) */ +#define US_CR_Msk _U_(0x1FC) /**< (US_CR) Register Mask */ + +/* USART mode */ +#define US_CR_USART_STTBRK_Pos 9 /**< (US_CR) Start Break Position */ +#define US_CR_USART_STTBRK_Msk (_U_(0x1) << US_CR_USART_STTBRK_Pos) /**< (US_CR) Start Break Mask */ +#define US_CR_USART_STTBRK US_CR_USART_STTBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_STTBRK_Msk instead */ +#define US_CR_USART_STPBRK_Pos 10 /**< (US_CR) Stop Break Position */ +#define US_CR_USART_STPBRK_Msk (_U_(0x1) << US_CR_USART_STPBRK_Pos) /**< (US_CR) Stop Break Mask */ +#define US_CR_USART_STPBRK US_CR_USART_STPBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_STPBRK_Msk instead */ +#define US_CR_USART_STTTO_Pos 11 /**< (US_CR) Clear TIMEOUT Flag and Start Timeout After Next Character Received Position */ +#define US_CR_USART_STTTO_Msk (_U_(0x1) << US_CR_USART_STTTO_Pos) /**< (US_CR) Clear TIMEOUT Flag and Start Timeout After Next Character Received Mask */ +#define US_CR_USART_STTTO US_CR_USART_STTTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_STTTO_Msk instead */ +#define US_CR_USART_SENDA_Pos 12 /**< (US_CR) Send Address Position */ +#define US_CR_USART_SENDA_Msk (_U_(0x1) << US_CR_USART_SENDA_Pos) /**< (US_CR) Send Address Mask */ +#define US_CR_USART_SENDA US_CR_USART_SENDA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_SENDA_Msk instead */ +#define US_CR_USART_RSTIT_Pos 13 /**< (US_CR) Reset Iterations Position */ +#define US_CR_USART_RSTIT_Msk (_U_(0x1) << US_CR_USART_RSTIT_Pos) /**< (US_CR) Reset Iterations Mask */ +#define US_CR_USART_RSTIT US_CR_USART_RSTIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_RSTIT_Msk instead */ +#define US_CR_USART_RSTNACK_Pos 14 /**< (US_CR) Reset Non Acknowledge Position */ +#define US_CR_USART_RSTNACK_Msk (_U_(0x1) << US_CR_USART_RSTNACK_Pos) /**< (US_CR) Reset Non Acknowledge Mask */ +#define US_CR_USART_RSTNACK US_CR_USART_RSTNACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_RSTNACK_Msk instead */ +#define US_CR_USART_RETTO_Pos 15 /**< (US_CR) Start Timeout Immediately Position */ +#define US_CR_USART_RETTO_Msk (_U_(0x1) << US_CR_USART_RETTO_Pos) /**< (US_CR) Start Timeout Immediately Mask */ +#define US_CR_USART_RETTO US_CR_USART_RETTO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_RETTO_Msk instead */ +#define US_CR_USART_DTREN_Pos 16 /**< (US_CR) Data Terminal Ready Enable Position */ +#define US_CR_USART_DTREN_Msk (_U_(0x1) << US_CR_USART_DTREN_Pos) /**< (US_CR) Data Terminal Ready Enable Mask */ +#define US_CR_USART_DTREN US_CR_USART_DTREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_DTREN_Msk instead */ +#define US_CR_USART_DTRDIS_Pos 17 /**< (US_CR) Data Terminal Ready Disable Position */ +#define US_CR_USART_DTRDIS_Msk (_U_(0x1) << US_CR_USART_DTRDIS_Pos) /**< (US_CR) Data Terminal Ready Disable Mask */ +#define US_CR_USART_DTRDIS US_CR_USART_DTRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_DTRDIS_Msk instead */ +#define US_CR_USART_RTSEN_Pos 18 /**< (US_CR) Request to Send Enable Position */ +#define US_CR_USART_RTSEN_Msk (_U_(0x1) << US_CR_USART_RTSEN_Pos) /**< (US_CR) Request to Send Enable Mask */ +#define US_CR_USART_RTSEN US_CR_USART_RTSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_RTSEN_Msk instead */ +#define US_CR_USART_RTSDIS_Pos 19 /**< (US_CR) Request to Send Disable Position */ +#define US_CR_USART_RTSDIS_Msk (_U_(0x1) << US_CR_USART_RTSDIS_Pos) /**< (US_CR) Request to Send Disable Mask */ +#define US_CR_USART_RTSDIS US_CR_USART_RTSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_USART_RTSDIS_Msk instead */ +#define US_CR_USART_MASK _U_(0xFFE00) /**< \deprecated (US_CR_USART) Register MASK (Use US_CR_USART_Msk instead) */ +#define US_CR_USART_Msk _U_(0xFFE00) /**< (US_CR_USART) Register Mask */ + +/* SPI mode */ +#define US_CR_SPI_FCS_Pos 18 /**< (US_CR) Force SPI Chip Select Position */ +#define US_CR_SPI_FCS_Msk (_U_(0x1) << US_CR_SPI_FCS_Pos) /**< (US_CR) Force SPI Chip Select Mask */ +#define US_CR_SPI_FCS US_CR_SPI_FCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_SPI_FCS_Msk instead */ +#define US_CR_SPI_RCS_Pos 19 /**< (US_CR) Release SPI Chip Select Position */ +#define US_CR_SPI_RCS_Msk (_U_(0x1) << US_CR_SPI_RCS_Pos) /**< (US_CR) Release SPI Chip Select Mask */ +#define US_CR_SPI_RCS US_CR_SPI_RCS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_SPI_RCS_Msk instead */ +#define US_CR_SPI_MASK _U_(0xC0000) /**< \deprecated (US_CR_SPI) Register MASK (Use US_CR_SPI_Msk instead) */ +#define US_CR_SPI_Msk _U_(0xC0000) /**< (US_CR_SPI) Register Mask */ + +/* LIN mode */ +#define US_CR_LIN_LINABT_Pos 20 /**< (US_CR) Abort LIN Transmission Position */ +#define US_CR_LIN_LINABT_Msk (_U_(0x1) << US_CR_LIN_LINABT_Pos) /**< (US_CR) Abort LIN Transmission Mask */ +#define US_CR_LIN_LINABT US_CR_LIN_LINABT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_LIN_LINABT_Msk instead */ +#define US_CR_LIN_LINWKUP_Pos 21 /**< (US_CR) Send LIN Wakeup Signal Position */ +#define US_CR_LIN_LINWKUP_Msk (_U_(0x1) << US_CR_LIN_LINWKUP_Pos) /**< (US_CR) Send LIN Wakeup Signal Mask */ +#define US_CR_LIN_LINWKUP US_CR_LIN_LINWKUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CR_LIN_LINWKUP_Msk instead */ +#define US_CR_LIN_MASK _U_(0x300000) /**< \deprecated (US_CR_LIN) Register MASK (Use US_CR_LIN_Msk instead) */ +#define US_CR_LIN_Msk _U_(0x300000) /**< (US_CR_LIN) Register Mask */ + + +/* -------- US_MR : (USART Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t USART_MODE:4; /**< bit: 0..3 USART Mode of Operation */ + uint32_t USCLKS:2; /**< bit: 4..5 Clock Selection */ + uint32_t CHRL:2; /**< bit: 6..7 Character Length */ + uint32_t :10; /**< bit: 8..17 Reserved */ + uint32_t CLKO:1; /**< bit: 18 Clock Output Select */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t SYNC:1; /**< bit: 8 Synchronous Mode Select */ + uint32_t PAR:3; /**< bit: 9..11 Parity Type */ + uint32_t NBSTOP:2; /**< bit: 12..13 Number of Stop Bits */ + uint32_t CHMODE:2; /**< bit: 14..15 Channel Mode */ + uint32_t MSBF:1; /**< bit: 16 Bit Order */ + uint32_t MODE9:1; /**< bit: 17 9-bit Character Length */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t OVER:1; /**< bit: 19 Oversampling Mode */ + uint32_t INACK:1; /**< bit: 20 Inhibit Non Acknowledge */ + uint32_t DSNACK:1; /**< bit: 21 Disable Successive NACK */ + uint32_t VAR_SYNC:1; /**< bit: 22 Variable Synchronization of Command/Data Sync Start Frame Delimiter */ + uint32_t INVDATA:1; /**< bit: 23 Inverted Data */ + uint32_t MAX_ITERATION:3; /**< bit: 24..26 Maximum Number of Automatic Iteration */ + uint32_t :1; /**< bit: 27 Reserved */ + uint32_t FILTER:1; /**< bit: 28 Receive Line Filter */ + uint32_t MAN:1; /**< bit: 29 Manchester Encoder/Decoder Enable */ + uint32_t MODSYNC:1; /**< bit: 30 Manchester Synchronization Mode */ + uint32_t ONEBIT:1; /**< bit: 31 Start Frame Delimiter Selector */ + } USART; /**< Structure used for USART mode access */ + struct { // SPI mode + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t CPHA:1; /**< bit: 8 SPI Clock Phase */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t CPOL:1; /**< bit: 16 SPI Clock Polarity */ + uint32_t :3; /**< bit: 17..19 Reserved */ + uint32_t WRDBT:1; /**< bit: 20 Wait Read Data Before Transfer */ + uint32_t :11; /**< bit: 21..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + uint32_t reg; /**< Type used for register access */ +} US_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_MR_OFFSET (0x04) /**< (US_MR) Mode Register Offset */ + +#define US_MR_USART_MODE_Pos 0 /**< (US_MR) USART Mode of Operation Position */ +#define US_MR_USART_MODE_Msk (_U_(0xF) << US_MR_USART_MODE_Pos) /**< (US_MR) USART Mode of Operation Mask */ +#define US_MR_USART_MODE(value) (US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)) +#define US_MR_USART_MODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485_Val _U_(0x1) /**< (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING_Val _U_(0x2) /**< (US_MR) Hardware handshaking */ +#define US_MR_USART_MODE_MODEM_Val _U_(0x3) /**< (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0_Val _U_(0x4) /**< (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1_Val _U_(0x6) /**< (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA_Val _U_(0x8) /**< (US_MR) IrDA */ +#define US_MR_USART_MODE_LON_Val _U_(0x9) /**< (US_MR) LON */ +#define US_MR_USART_MODE_LIN_MASTER_Val _U_(0xA) /**< (US_MR) LIN Master mode */ +#define US_MR_USART_MODE_LIN_SLAVE_Val _U_(0xB) /**< (US_MR) LIN Slave mode */ +#define US_MR_USART_MODE_SPI_MASTER_Val _U_(0xE) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) */ +#define US_MR_USART_MODE_SPI_SLAVE_Val _U_(0xF) /**< (US_MR) SPI Slave mode */ +#define US_MR_USART_MODE_NORMAL (US_MR_USART_MODE_NORMAL_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_USART_MODE_RS485 (US_MR_USART_MODE_RS485_Val << US_MR_USART_MODE_Pos) /**< (US_MR) RS485 Position */ +#define US_MR_USART_MODE_HW_HANDSHAKING (US_MR_USART_MODE_HW_HANDSHAKING_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Hardware handshaking Position */ +#define US_MR_USART_MODE_MODEM (US_MR_USART_MODE_MODEM_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Modem Position */ +#define US_MR_USART_MODE_IS07816_T_0 (US_MR_USART_MODE_IS07816_T_0_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 0 Position */ +#define US_MR_USART_MODE_IS07816_T_1 (US_MR_USART_MODE_IS07816_T_1_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 1 Position */ +#define US_MR_USART_MODE_IRDA (US_MR_USART_MODE_IRDA_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IrDA Position */ +#define US_MR_USART_MODE_LON (US_MR_USART_MODE_LON_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LON Position */ +#define US_MR_USART_MODE_LIN_MASTER (US_MR_USART_MODE_LIN_MASTER_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LIN Master mode Position */ +#define US_MR_USART_MODE_LIN_SLAVE (US_MR_USART_MODE_LIN_SLAVE_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LIN Slave mode Position */ +#define US_MR_USART_MODE_SPI_MASTER (US_MR_USART_MODE_SPI_MASTER_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) Position */ +#define US_MR_USART_MODE_SPI_SLAVE (US_MR_USART_MODE_SPI_SLAVE_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI Slave mode Position */ +#define US_MR_USCLKS_Pos 4 /**< (US_MR) Clock Selection Position */ +#define US_MR_USCLKS_Msk (_U_(0x3) << US_MR_USCLKS_Pos) /**< (US_MR) Clock Selection Mask */ +#define US_MR_USCLKS(value) (US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)) +#define US_MR_USCLKS_MCK_Val _U_(0x0) /**< (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV_Val _U_(0x1) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected */ +#define US_MR_USCLKS_PCK_Val _U_(0x2) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK_Val _U_(0x3) /**< (US_MR) Serial clock (SCK) is selected */ +#define US_MR_USCLKS_MCK (US_MR_USCLKS_MCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) Peripheral clock is selected Position */ +#define US_MR_USCLKS_DIV (US_MR_USCLKS_DIV_Val << US_MR_USCLKS_Pos) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected Position */ +#define US_MR_USCLKS_PCK (US_MR_USCLKS_PCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. Position */ +#define US_MR_USCLKS_SCK (US_MR_USCLKS_SCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) Serial clock (SCK) is selected Position */ +#define US_MR_CHRL_Pos 6 /**< (US_MR) Character Length Position */ +#define US_MR_CHRL_Msk (_U_(0x3) << US_MR_CHRL_Pos) /**< (US_MR) Character Length Mask */ +#define US_MR_CHRL(value) (US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)) +#define US_MR_CHRL_5_BIT_Val _U_(0x0) /**< (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT_Val _U_(0x1) /**< (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT_Val _U_(0x2) /**< (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT_Val _U_(0x3) /**< (US_MR) Character length is 8 bits */ +#define US_MR_CHRL_5_BIT (US_MR_CHRL_5_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 5 bits Position */ +#define US_MR_CHRL_6_BIT (US_MR_CHRL_6_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 6 bits Position */ +#define US_MR_CHRL_7_BIT (US_MR_CHRL_7_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 7 bits Position */ +#define US_MR_CHRL_8_BIT (US_MR_CHRL_8_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 8 bits Position */ +#define US_MR_CLKO_Pos 18 /**< (US_MR) Clock Output Select Position */ +#define US_MR_CLKO_Msk (_U_(0x1) << US_MR_CLKO_Pos) /**< (US_MR) Clock Output Select Mask */ +#define US_MR_CLKO US_MR_CLKO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_CLKO_Msk instead */ +#define US_MR_MASK _U_(0x400FF) /**< \deprecated (US_MR) Register MASK (Use US_MR_Msk instead) */ +#define US_MR_Msk _U_(0x400FF) /**< (US_MR) Register Mask */ + +/* USART mode */ +#define US_MR_USART_SYNC_Pos 8 /**< (US_MR) Synchronous Mode Select Position */ +#define US_MR_USART_SYNC_Msk (_U_(0x1) << US_MR_USART_SYNC_Pos) /**< (US_MR) Synchronous Mode Select Mask */ +#define US_MR_USART_SYNC US_MR_USART_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_SYNC_Msk instead */ +#define US_MR_USART_PAR_Pos 9 /**< (US_MR) Parity Type Position */ +#define US_MR_USART_PAR_Msk (_U_(0x7) << US_MR_USART_PAR_Pos) /**< (US_MR) Parity Type Mask */ +#define US_MR_USART_PAR(value) (US_MR_USART_PAR_Msk & ((value) << US_MR_USART_PAR_Pos)) +#define US_MR_USART_PAR_EVEN_Val _U_(0x0) /**< (US_MR) USART Even parity */ +#define US_MR_USART_PAR_ODD_Val _U_(0x1) /**< (US_MR) USART Odd parity */ +#define US_MR_USART_PAR_SPACE_Val _U_(0x2) /**< (US_MR) USART Parity forced to 0 (Space) */ +#define US_MR_USART_PAR_MARK_Val _U_(0x3) /**< (US_MR) USART Parity forced to 1 (Mark) */ +#define US_MR_USART_PAR_NO_Val _U_(0x4) /**< (US_MR) USART No parity */ +#define US_MR_USART_PAR_MULTIDROP_Val _U_(0x6) /**< (US_MR) USART Multidrop mode */ +#define US_MR_USART_PAR_EVEN (US_MR_USART_PAR_EVEN_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Even parity Position */ +#define US_MR_USART_PAR_ODD (US_MR_USART_PAR_ODD_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Odd parity Position */ +#define US_MR_USART_PAR_SPACE (US_MR_USART_PAR_SPACE_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Parity forced to 0 (Space) Position */ +#define US_MR_USART_PAR_MARK (US_MR_USART_PAR_MARK_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Parity forced to 1 (Mark) Position */ +#define US_MR_USART_PAR_NO (US_MR_USART_PAR_NO_Val << US_MR_USART_PAR_Pos) /**< (US_MR) No parity Position */ +#define US_MR_USART_PAR_MULTIDROP (US_MR_USART_PAR_MULTIDROP_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Multidrop mode Position */ +#define US_MR_USART_NBSTOP_Pos 12 /**< (US_MR) Number of Stop Bits Position */ +#define US_MR_USART_NBSTOP_Msk (_U_(0x3) << US_MR_USART_NBSTOP_Pos) /**< (US_MR) Number of Stop Bits Mask */ +#define US_MR_USART_NBSTOP(value) (US_MR_USART_NBSTOP_Msk & ((value) << US_MR_USART_NBSTOP_Pos)) +#define US_MR_USART_NBSTOP_1_BIT_Val _U_(0x0) /**< (US_MR) USART 1 stop bit */ +#define US_MR_USART_NBSTOP_1_5_BIT_Val _U_(0x1) /**< (US_MR) USART 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_USART_NBSTOP_2_BIT_Val _U_(0x2) /**< (US_MR) USART 2 stop bits */ +#define US_MR_USART_NBSTOP_1_BIT (US_MR_USART_NBSTOP_1_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 1 stop bit Position */ +#define US_MR_USART_NBSTOP_1_5_BIT (US_MR_USART_NBSTOP_1_5_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) Position */ +#define US_MR_USART_NBSTOP_2_BIT (US_MR_USART_NBSTOP_2_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 2 stop bits Position */ +#define US_MR_USART_CHMODE_Pos 14 /**< (US_MR) Channel Mode Position */ +#define US_MR_USART_CHMODE_Msk (_U_(0x3) << US_MR_USART_CHMODE_Pos) /**< (US_MR) Channel Mode Mask */ +#define US_MR_USART_CHMODE(value) (US_MR_USART_CHMODE_Msk & ((value) << US_MR_USART_CHMODE_Pos)) +#define US_MR_USART_CHMODE_NORMAL_Val _U_(0x0) /**< (US_MR) USART Normal mode */ +#define US_MR_USART_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (US_MR) USART Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_USART_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (US_MR) USART Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_USART_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (US_MR) USART Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_USART_CHMODE_NORMAL (US_MR_USART_CHMODE_NORMAL_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_USART_CHMODE_AUTOMATIC (US_MR_USART_CHMODE_AUTOMATIC_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. Position */ +#define US_MR_USART_CHMODE_LOCAL_LOOPBACK (US_MR_USART_CHMODE_LOCAL_LOOPBACK_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. Position */ +#define US_MR_USART_CHMODE_REMOTE_LOOPBACK (US_MR_USART_CHMODE_REMOTE_LOOPBACK_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. Position */ +#define US_MR_USART_MSBF_Pos 16 /**< (US_MR) Bit Order Position */ +#define US_MR_USART_MSBF_Msk (_U_(0x1) << US_MR_USART_MSBF_Pos) /**< (US_MR) Bit Order Mask */ +#define US_MR_USART_MSBF US_MR_USART_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_MSBF_Msk instead */ +#define US_MR_USART_MODE9_Pos 17 /**< (US_MR) 9-bit Character Length Position */ +#define US_MR_USART_MODE9_Msk (_U_(0x1) << US_MR_USART_MODE9_Pos) /**< (US_MR) 9-bit Character Length Mask */ +#define US_MR_USART_MODE9 US_MR_USART_MODE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_MODE9_Msk instead */ +#define US_MR_USART_OVER_Pos 19 /**< (US_MR) Oversampling Mode Position */ +#define US_MR_USART_OVER_Msk (_U_(0x1) << US_MR_USART_OVER_Pos) /**< (US_MR) Oversampling Mode Mask */ +#define US_MR_USART_OVER US_MR_USART_OVER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_OVER_Msk instead */ +#define US_MR_USART_INACK_Pos 20 /**< (US_MR) Inhibit Non Acknowledge Position */ +#define US_MR_USART_INACK_Msk (_U_(0x1) << US_MR_USART_INACK_Pos) /**< (US_MR) Inhibit Non Acknowledge Mask */ +#define US_MR_USART_INACK US_MR_USART_INACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_INACK_Msk instead */ +#define US_MR_USART_DSNACK_Pos 21 /**< (US_MR) Disable Successive NACK Position */ +#define US_MR_USART_DSNACK_Msk (_U_(0x1) << US_MR_USART_DSNACK_Pos) /**< (US_MR) Disable Successive NACK Mask */ +#define US_MR_USART_DSNACK US_MR_USART_DSNACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_DSNACK_Msk instead */ +#define US_MR_USART_VAR_SYNC_Pos 22 /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Position */ +#define US_MR_USART_VAR_SYNC_Msk (_U_(0x1) << US_MR_USART_VAR_SYNC_Pos) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Mask */ +#define US_MR_USART_VAR_SYNC US_MR_USART_VAR_SYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_VAR_SYNC_Msk instead */ +#define US_MR_USART_INVDATA_Pos 23 /**< (US_MR) Inverted Data Position */ +#define US_MR_USART_INVDATA_Msk (_U_(0x1) << US_MR_USART_INVDATA_Pos) /**< (US_MR) Inverted Data Mask */ +#define US_MR_USART_INVDATA US_MR_USART_INVDATA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_INVDATA_Msk instead */ +#define US_MR_USART_MAX_ITERATION_Pos 24 /**< (US_MR) Maximum Number of Automatic Iteration Position */ +#define US_MR_USART_MAX_ITERATION_Msk (_U_(0x7) << US_MR_USART_MAX_ITERATION_Pos) /**< (US_MR) Maximum Number of Automatic Iteration Mask */ +#define US_MR_USART_MAX_ITERATION(value) (US_MR_USART_MAX_ITERATION_Msk & ((value) << US_MR_USART_MAX_ITERATION_Pos)) +#define US_MR_USART_FILTER_Pos 28 /**< (US_MR) Receive Line Filter Position */ +#define US_MR_USART_FILTER_Msk (_U_(0x1) << US_MR_USART_FILTER_Pos) /**< (US_MR) Receive Line Filter Mask */ +#define US_MR_USART_FILTER US_MR_USART_FILTER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_FILTER_Msk instead */ +#define US_MR_USART_MAN_Pos 29 /**< (US_MR) Manchester Encoder/Decoder Enable Position */ +#define US_MR_USART_MAN_Msk (_U_(0x1) << US_MR_USART_MAN_Pos) /**< (US_MR) Manchester Encoder/Decoder Enable Mask */ +#define US_MR_USART_MAN US_MR_USART_MAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_MAN_Msk instead */ +#define US_MR_USART_MODSYNC_Pos 30 /**< (US_MR) Manchester Synchronization Mode Position */ +#define US_MR_USART_MODSYNC_Msk (_U_(0x1) << US_MR_USART_MODSYNC_Pos) /**< (US_MR) Manchester Synchronization Mode Mask */ +#define US_MR_USART_MODSYNC US_MR_USART_MODSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_MODSYNC_Msk instead */ +#define US_MR_USART_ONEBIT_Pos 31 /**< (US_MR) Start Frame Delimiter Selector Position */ +#define US_MR_USART_ONEBIT_Msk (_U_(0x1) << US_MR_USART_ONEBIT_Pos) /**< (US_MR) Start Frame Delimiter Selector Mask */ +#define US_MR_USART_ONEBIT US_MR_USART_ONEBIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_USART_ONEBIT_Msk instead */ +#define US_MR_USART_MASK _U_(0xF7FBFF00) /**< \deprecated (US_MR_USART) Register MASK (Use US_MR_USART_Msk instead) */ +#define US_MR_USART_Msk _U_(0xF7FBFF00) /**< (US_MR_USART) Register Mask */ + +/* SPI mode */ +#define US_MR_SPI_CPHA_Pos 8 /**< (US_MR) SPI Clock Phase Position */ +#define US_MR_SPI_CPHA_Msk (_U_(0x1) << US_MR_SPI_CPHA_Pos) /**< (US_MR) SPI Clock Phase Mask */ +#define US_MR_SPI_CPHA US_MR_SPI_CPHA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_SPI_CPHA_Msk instead */ +#define US_MR_SPI_CPOL_Pos 16 /**< (US_MR) SPI Clock Polarity Position */ +#define US_MR_SPI_CPOL_Msk (_U_(0x1) << US_MR_SPI_CPOL_Pos) /**< (US_MR) SPI Clock Polarity Mask */ +#define US_MR_SPI_CPOL US_MR_SPI_CPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_SPI_CPOL_Msk instead */ +#define US_MR_SPI_WRDBT_Pos 20 /**< (US_MR) Wait Read Data Before Transfer Position */ +#define US_MR_SPI_WRDBT_Msk (_U_(0x1) << US_MR_SPI_WRDBT_Pos) /**< (US_MR) Wait Read Data Before Transfer Mask */ +#define US_MR_SPI_WRDBT US_MR_SPI_WRDBT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MR_SPI_WRDBT_Msk instead */ +#define US_MR_SPI_MASK _U_(0x110100) /**< \deprecated (US_MR_SPI) Register MASK (Use US_MR_SPI_Msk instead) */ +#define US_MR_SPI_Msk _U_(0x110100) /**< (US_MR_SPI) Register Mask */ + + +/* -------- US_IER : (USART Offset: 0x08) (/W 32) Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 RXRDY Interrupt Enable */ + uint32_t TXRDY:1; /**< bit: 1 TXRDY Interrupt Enable */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Overrun Error Interrupt Enable */ + uint32_t :3; /**< bit: 6..8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 TXEMPTY Interrupt Enable */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXBRK:1; /**< bit: 2 Receiver Break Interrupt Enable */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t ITER:1; /**< bit: 10 Max number of Repetitions Reached Interrupt Enable */ + uint32_t :2; /**< bit: 11..12 Reserved */ + uint32_t NACK:1; /**< bit: 13 Non Acknowledge Interrupt Enable */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t RIIC:1; /**< bit: 16 Ring Indicator Input Change Enable */ + uint32_t DSRIC:1; /**< bit: 17 Data Set Ready Input Change Enable */ + uint32_t DCDIC:1; /**< bit: 18 Data Carrier Detect Input Change Interrupt Enable */ + uint32_t CTSIC:1; /**< bit: 19 Clear to Send Input Change Interrupt Enable */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t MANE:1; /**< bit: 24 Manchester Error Interrupt Enable */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // USART_LIN mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t FRAME:1; /**< bit: 6 Framing Error Interrupt Enable */ + uint32_t PARE:1; /**< bit: 7 Parity Error Interrupt Enable */ + uint32_t TIMEOUT:1; /**< bit: 8 Timeout Interrupt Enable */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } USART_LIN; /**< Structure used for USART_LIN mode access */ + struct { // SPI mode + uint32_t :19; /**< bit: 0..18 Reserved */ + uint32_t NSSE:1; /**< bit: 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + struct { // LIN mode + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t LINBK:1; /**< bit: 13 LIN Break Sent or LIN Break Received Interrupt Enable */ + uint32_t LINID:1; /**< bit: 14 LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ + uint32_t LINTC:1; /**< bit: 15 LIN Transfer Completed Interrupt Enable */ + uint32_t :9; /**< bit: 16..24 Reserved */ + uint32_t LINBE:1; /**< bit: 25 LIN Bus Error Interrupt Enable */ + uint32_t LINISFE:1; /**< bit: 26 LIN Inconsistent Synch Field Error Interrupt Enable */ + uint32_t LINIPE:1; /**< bit: 27 LIN Identifier Parity Interrupt Enable */ + uint32_t LINCE:1; /**< bit: 28 LIN Checksum Error Interrupt Enable */ + uint32_t LINSNRE:1; /**< bit: 29 LIN Slave Not Responding Error Interrupt Enable */ + uint32_t LINSTE:1; /**< bit: 30 LIN Synch Tolerance Error Interrupt Enable */ + uint32_t LINHTE:1; /**< bit: 31 LIN Header Timeout Error Interrupt Enable */ + } LIN; /**< Structure used for LIN mode access */ + struct { // LON mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t LSFE:1; /**< bit: 6 LON Short Frame Error Interrupt Enable */ + uint32_t LCRCE:1; /**< bit: 7 LON CRC Error Interrupt Enable */ + uint32_t :16; /**< bit: 8..23 Reserved */ + uint32_t LTXD:1; /**< bit: 24 LON Transmission Done Interrupt Enable */ + uint32_t LCOL:1; /**< bit: 25 LON Collision Interrupt Enable */ + uint32_t LFET:1; /**< bit: 26 LON Frame Early Termination Interrupt Enable */ + uint32_t LRXD:1; /**< bit: 27 LON Reception Done Interrupt Enable */ + uint32_t LBLOVFE:1; /**< bit: 28 LON Backlog Overflow Error Interrupt Enable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + struct { // LON_SPI mode + uint32_t :10; /**< bit: 0..9 Reserved */ + uint32_t UNRE:1; /**< bit: 10 Underrun Error Interrupt Enable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } LON_SPI; /**< Structure used for LON_SPI mode access */ + uint32_t reg; /**< Type used for register access */ +} US_IER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IER_OFFSET (0x08) /**< (US_IER) Interrupt Enable Register Offset */ + +#define US_IER_RXRDY_Pos 0 /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_RXRDY_Msk (_U_(0x1) << US_IER_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_RXRDY US_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_RXRDY_Msk instead */ +#define US_IER_TXRDY_Pos 1 /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_TXRDY_Msk (_U_(0x1) << US_IER_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_TXRDY US_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_TXRDY_Msk instead */ +#define US_IER_OVRE_Pos 5 /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_OVRE_Msk (_U_(0x1) << US_IER_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_OVRE US_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_OVRE_Msk instead */ +#define US_IER_TXEMPTY_Pos 9 /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_TXEMPTY_Msk (_U_(0x1) << US_IER_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_TXEMPTY US_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_TXEMPTY_Msk instead */ +#define US_IER_MASK _U_(0x223) /**< \deprecated (US_IER) Register MASK (Use US_IER_Msk instead) */ +#define US_IER_Msk _U_(0x223) /**< (US_IER) Register Mask */ + +/* USART mode */ +#define US_IER_USART_RXBRK_Pos 2 /**< (US_IER) Receiver Break Interrupt Enable Position */ +#define US_IER_USART_RXBRK_Msk (_U_(0x1) << US_IER_USART_RXBRK_Pos) /**< (US_IER) Receiver Break Interrupt Enable Mask */ +#define US_IER_USART_RXBRK US_IER_USART_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_RXBRK_Msk instead */ +#define US_IER_USART_ITER_Pos 10 /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Position */ +#define US_IER_USART_ITER_Msk (_U_(0x1) << US_IER_USART_ITER_Pos) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Mask */ +#define US_IER_USART_ITER US_IER_USART_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_ITER_Msk instead */ +#define US_IER_USART_NACK_Pos 13 /**< (US_IER) Non Acknowledge Interrupt Enable Position */ +#define US_IER_USART_NACK_Msk (_U_(0x1) << US_IER_USART_NACK_Pos) /**< (US_IER) Non Acknowledge Interrupt Enable Mask */ +#define US_IER_USART_NACK US_IER_USART_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_NACK_Msk instead */ +#define US_IER_USART_RIIC_Pos 16 /**< (US_IER) Ring Indicator Input Change Enable Position */ +#define US_IER_USART_RIIC_Msk (_U_(0x1) << US_IER_USART_RIIC_Pos) /**< (US_IER) Ring Indicator Input Change Enable Mask */ +#define US_IER_USART_RIIC US_IER_USART_RIIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_RIIC_Msk instead */ +#define US_IER_USART_DSRIC_Pos 17 /**< (US_IER) Data Set Ready Input Change Enable Position */ +#define US_IER_USART_DSRIC_Msk (_U_(0x1) << US_IER_USART_DSRIC_Pos) /**< (US_IER) Data Set Ready Input Change Enable Mask */ +#define US_IER_USART_DSRIC US_IER_USART_DSRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_DSRIC_Msk instead */ +#define US_IER_USART_DCDIC_Pos 18 /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Position */ +#define US_IER_USART_DCDIC_Msk (_U_(0x1) << US_IER_USART_DCDIC_Pos) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Mask */ +#define US_IER_USART_DCDIC US_IER_USART_DCDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_DCDIC_Msk instead */ +#define US_IER_USART_CTSIC_Pos 19 /**< (US_IER) Clear to Send Input Change Interrupt Enable Position */ +#define US_IER_USART_CTSIC_Msk (_U_(0x1) << US_IER_USART_CTSIC_Pos) /**< (US_IER) Clear to Send Input Change Interrupt Enable Mask */ +#define US_IER_USART_CTSIC US_IER_USART_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_CTSIC_Msk instead */ +#define US_IER_USART_MANE_Pos 24 /**< (US_IER) Manchester Error Interrupt Enable Position */ +#define US_IER_USART_MANE_Msk (_U_(0x1) << US_IER_USART_MANE_Pos) /**< (US_IER) Manchester Error Interrupt Enable Mask */ +#define US_IER_USART_MANE US_IER_USART_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_MANE_Msk instead */ +#define US_IER_USART_MASK _U_(0x10F2404) /**< \deprecated (US_IER_USART) Register MASK (Use US_IER_USART_Msk instead) */ +#define US_IER_USART_Msk _U_(0x10F2404) /**< (US_IER_USART) Register Mask */ + +/* USART_LIN mode */ +#define US_IER_USART_LIN_FRAME_Pos 6 /**< (US_IER) Framing Error Interrupt Enable Position */ +#define US_IER_USART_LIN_FRAME_Msk (_U_(0x1) << US_IER_USART_LIN_FRAME_Pos) /**< (US_IER) Framing Error Interrupt Enable Mask */ +#define US_IER_USART_LIN_FRAME US_IER_USART_LIN_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_LIN_FRAME_Msk instead */ +#define US_IER_USART_LIN_PARE_Pos 7 /**< (US_IER) Parity Error Interrupt Enable Position */ +#define US_IER_USART_LIN_PARE_Msk (_U_(0x1) << US_IER_USART_LIN_PARE_Pos) /**< (US_IER) Parity Error Interrupt Enable Mask */ +#define US_IER_USART_LIN_PARE US_IER_USART_LIN_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_LIN_PARE_Msk instead */ +#define US_IER_USART_LIN_TIMEOUT_Pos 8 /**< (US_IER) Timeout Interrupt Enable Position */ +#define US_IER_USART_LIN_TIMEOUT_Msk (_U_(0x1) << US_IER_USART_LIN_TIMEOUT_Pos) /**< (US_IER) Timeout Interrupt Enable Mask */ +#define US_IER_USART_LIN_TIMEOUT US_IER_USART_LIN_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_USART_LIN_TIMEOUT_Msk instead */ +#define US_IER_USART_LIN_MASK _U_(0x1C0) /**< \deprecated (US_IER_USART_LIN) Register MASK (Use US_IER_USART_LIN_Msk instead) */ +#define US_IER_USART_LIN_Msk _U_(0x1C0) /**< (US_IER_USART_LIN) Register Mask */ + +/* SPI mode */ +#define US_IER_SPI_NSSE_Pos 19 /**< (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IER_SPI_NSSE_Msk (_U_(0x1) << US_IER_SPI_NSSE_Pos) /**< (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IER_SPI_NSSE US_IER_SPI_NSSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_SPI_NSSE_Msk instead */ +#define US_IER_SPI_MASK _U_(0x80000) /**< \deprecated (US_IER_SPI) Register MASK (Use US_IER_SPI_Msk instead) */ +#define US_IER_SPI_Msk _U_(0x80000) /**< (US_IER_SPI) Register Mask */ + +/* LIN mode */ +#define US_IER_LIN_LINBK_Pos 13 /**< (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable Position */ +#define US_IER_LIN_LINBK_Msk (_U_(0x1) << US_IER_LIN_LINBK_Pos) /**< (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable Mask */ +#define US_IER_LIN_LINBK US_IER_LIN_LINBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINBK_Msk instead */ +#define US_IER_LIN_LINID_Pos 14 /**< (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable Position */ +#define US_IER_LIN_LINID_Msk (_U_(0x1) << US_IER_LIN_LINID_Pos) /**< (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable Mask */ +#define US_IER_LIN_LINID US_IER_LIN_LINID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINID_Msk instead */ +#define US_IER_LIN_LINTC_Pos 15 /**< (US_IER) LIN Transfer Completed Interrupt Enable Position */ +#define US_IER_LIN_LINTC_Msk (_U_(0x1) << US_IER_LIN_LINTC_Pos) /**< (US_IER) LIN Transfer Completed Interrupt Enable Mask */ +#define US_IER_LIN_LINTC US_IER_LIN_LINTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINTC_Msk instead */ +#define US_IER_LIN_LINBE_Pos 25 /**< (US_IER) LIN Bus Error Interrupt Enable Position */ +#define US_IER_LIN_LINBE_Msk (_U_(0x1) << US_IER_LIN_LINBE_Pos) /**< (US_IER) LIN Bus Error Interrupt Enable Mask */ +#define US_IER_LIN_LINBE US_IER_LIN_LINBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINBE_Msk instead */ +#define US_IER_LIN_LINISFE_Pos 26 /**< (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable Position */ +#define US_IER_LIN_LINISFE_Msk (_U_(0x1) << US_IER_LIN_LINISFE_Pos) /**< (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable Mask */ +#define US_IER_LIN_LINISFE US_IER_LIN_LINISFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINISFE_Msk instead */ +#define US_IER_LIN_LINIPE_Pos 27 /**< (US_IER) LIN Identifier Parity Interrupt Enable Position */ +#define US_IER_LIN_LINIPE_Msk (_U_(0x1) << US_IER_LIN_LINIPE_Pos) /**< (US_IER) LIN Identifier Parity Interrupt Enable Mask */ +#define US_IER_LIN_LINIPE US_IER_LIN_LINIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINIPE_Msk instead */ +#define US_IER_LIN_LINCE_Pos 28 /**< (US_IER) LIN Checksum Error Interrupt Enable Position */ +#define US_IER_LIN_LINCE_Msk (_U_(0x1) << US_IER_LIN_LINCE_Pos) /**< (US_IER) LIN Checksum Error Interrupt Enable Mask */ +#define US_IER_LIN_LINCE US_IER_LIN_LINCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINCE_Msk instead */ +#define US_IER_LIN_LINSNRE_Pos 29 /**< (US_IER) LIN Slave Not Responding Error Interrupt Enable Position */ +#define US_IER_LIN_LINSNRE_Msk (_U_(0x1) << US_IER_LIN_LINSNRE_Pos) /**< (US_IER) LIN Slave Not Responding Error Interrupt Enable Mask */ +#define US_IER_LIN_LINSNRE US_IER_LIN_LINSNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINSNRE_Msk instead */ +#define US_IER_LIN_LINSTE_Pos 30 /**< (US_IER) LIN Synch Tolerance Error Interrupt Enable Position */ +#define US_IER_LIN_LINSTE_Msk (_U_(0x1) << US_IER_LIN_LINSTE_Pos) /**< (US_IER) LIN Synch Tolerance Error Interrupt Enable Mask */ +#define US_IER_LIN_LINSTE US_IER_LIN_LINSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINSTE_Msk instead */ +#define US_IER_LIN_LINHTE_Pos 31 /**< (US_IER) LIN Header Timeout Error Interrupt Enable Position */ +#define US_IER_LIN_LINHTE_Msk (_U_(0x1) << US_IER_LIN_LINHTE_Pos) /**< (US_IER) LIN Header Timeout Error Interrupt Enable Mask */ +#define US_IER_LIN_LINHTE US_IER_LIN_LINHTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LIN_LINHTE_Msk instead */ +#define US_IER_LIN_MASK _U_(0xFE00E000) /**< \deprecated (US_IER_LIN) Register MASK (Use US_IER_LIN_Msk instead) */ +#define US_IER_LIN_Msk _U_(0xFE00E000) /**< (US_IER_LIN) Register Mask */ + +/* LON mode */ +#define US_IER_LON_LSFE_Pos 6 /**< (US_IER) LON Short Frame Error Interrupt Enable Position */ +#define US_IER_LON_LSFE_Msk (_U_(0x1) << US_IER_LON_LSFE_Pos) /**< (US_IER) LON Short Frame Error Interrupt Enable Mask */ +#define US_IER_LON_LSFE US_IER_LON_LSFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LSFE_Msk instead */ +#define US_IER_LON_LCRCE_Pos 7 /**< (US_IER) LON CRC Error Interrupt Enable Position */ +#define US_IER_LON_LCRCE_Msk (_U_(0x1) << US_IER_LON_LCRCE_Pos) /**< (US_IER) LON CRC Error Interrupt Enable Mask */ +#define US_IER_LON_LCRCE US_IER_LON_LCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LCRCE_Msk instead */ +#define US_IER_LON_LTXD_Pos 24 /**< (US_IER) LON Transmission Done Interrupt Enable Position */ +#define US_IER_LON_LTXD_Msk (_U_(0x1) << US_IER_LON_LTXD_Pos) /**< (US_IER) LON Transmission Done Interrupt Enable Mask */ +#define US_IER_LON_LTXD US_IER_LON_LTXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LTXD_Msk instead */ +#define US_IER_LON_LCOL_Pos 25 /**< (US_IER) LON Collision Interrupt Enable Position */ +#define US_IER_LON_LCOL_Msk (_U_(0x1) << US_IER_LON_LCOL_Pos) /**< (US_IER) LON Collision Interrupt Enable Mask */ +#define US_IER_LON_LCOL US_IER_LON_LCOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LCOL_Msk instead */ +#define US_IER_LON_LFET_Pos 26 /**< (US_IER) LON Frame Early Termination Interrupt Enable Position */ +#define US_IER_LON_LFET_Msk (_U_(0x1) << US_IER_LON_LFET_Pos) /**< (US_IER) LON Frame Early Termination Interrupt Enable Mask */ +#define US_IER_LON_LFET US_IER_LON_LFET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LFET_Msk instead */ +#define US_IER_LON_LRXD_Pos 27 /**< (US_IER) LON Reception Done Interrupt Enable Position */ +#define US_IER_LON_LRXD_Msk (_U_(0x1) << US_IER_LON_LRXD_Pos) /**< (US_IER) LON Reception Done Interrupt Enable Mask */ +#define US_IER_LON_LRXD US_IER_LON_LRXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LRXD_Msk instead */ +#define US_IER_LON_LBLOVFE_Pos 28 /**< (US_IER) LON Backlog Overflow Error Interrupt Enable Position */ +#define US_IER_LON_LBLOVFE_Msk (_U_(0x1) << US_IER_LON_LBLOVFE_Pos) /**< (US_IER) LON Backlog Overflow Error Interrupt Enable Mask */ +#define US_IER_LON_LBLOVFE US_IER_LON_LBLOVFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_LBLOVFE_Msk instead */ +#define US_IER_LON_MASK _U_(0x1F0000C0) /**< \deprecated (US_IER_LON) Register MASK (Use US_IER_LON_Msk instead) */ +#define US_IER_LON_Msk _U_(0x1F0000C0) /**< (US_IER_LON) Register Mask */ + +/* LON_SPI mode */ +#define US_IER_LON_SPI_UNRE_Pos 10 /**< (US_IER) Underrun Error Interrupt Enable Position */ +#define US_IER_LON_SPI_UNRE_Msk (_U_(0x1) << US_IER_LON_SPI_UNRE_Pos) /**< (US_IER) Underrun Error Interrupt Enable Mask */ +#define US_IER_LON_SPI_UNRE US_IER_LON_SPI_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IER_LON_SPI_UNRE_Msk instead */ +#define US_IER_LON_SPI_MASK _U_(0x400) /**< \deprecated (US_IER_LON_SPI) Register MASK (Use US_IER_LON_SPI_Msk instead) */ +#define US_IER_LON_SPI_Msk _U_(0x400) /**< (US_IER_LON_SPI) Register Mask */ + + +/* -------- US_IDR : (USART Offset: 0x0c) (/W 32) Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 RXRDY Interrupt Disable */ + uint32_t TXRDY:1; /**< bit: 1 TXRDY Interrupt Disable */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Overrun Error Interrupt Enable */ + uint32_t :3; /**< bit: 6..8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 TXEMPTY Interrupt Disable */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t RIIC:1; /**< bit: 16 Ring Indicator Input Change Disable */ + uint32_t DSRIC:1; /**< bit: 17 Data Set Ready Input Change Disable */ + uint32_t DCDIC:1; /**< bit: 18 Data Carrier Detect Input Change Interrupt Disable */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXBRK:1; /**< bit: 2 Receiver Break Interrupt Disable */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t ITER:1; /**< bit: 10 Max Number of Repetitions Reached Interrupt Disable */ + uint32_t :2; /**< bit: 11..12 Reserved */ + uint32_t NACK:1; /**< bit: 13 Non Acknowledge Interrupt Disable */ + uint32_t :5; /**< bit: 14..18 Reserved */ + uint32_t CTSIC:1; /**< bit: 19 Clear to Send Input Change Interrupt Disable */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t MANE:1; /**< bit: 24 Manchester Error Interrupt Disable */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // USART_LIN mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t FRAME:1; /**< bit: 6 Framing Error Interrupt Disable */ + uint32_t PARE:1; /**< bit: 7 Parity Error Interrupt Disable */ + uint32_t TIMEOUT:1; /**< bit: 8 Timeout Interrupt Disable */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } USART_LIN; /**< Structure used for USART_LIN mode access */ + struct { // SPI mode + uint32_t :19; /**< bit: 0..18 Reserved */ + uint32_t NSSE:1; /**< bit: 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + struct { // LIN mode + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t LINBK:1; /**< bit: 13 LIN Break Sent or LIN Break Received Interrupt Disable */ + uint32_t LINID:1; /**< bit: 14 LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ + uint32_t LINTC:1; /**< bit: 15 LIN Transfer Completed Interrupt Disable */ + uint32_t :9; /**< bit: 16..24 Reserved */ + uint32_t LINBE:1; /**< bit: 25 LIN Bus Error Interrupt Disable */ + uint32_t LINISFE:1; /**< bit: 26 LIN Inconsistent Synch Field Error Interrupt Disable */ + uint32_t LINIPE:1; /**< bit: 27 LIN Identifier Parity Interrupt Disable */ + uint32_t LINCE:1; /**< bit: 28 LIN Checksum Error Interrupt Disable */ + uint32_t LINSNRE:1; /**< bit: 29 LIN Slave Not Responding Error Interrupt Disable */ + uint32_t LINSTE:1; /**< bit: 30 LIN Synch Tolerance Error Interrupt Disable */ + uint32_t LINHTE:1; /**< bit: 31 LIN Header Timeout Error Interrupt Disable */ + } LIN; /**< Structure used for LIN mode access */ + struct { // LON mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t LSFE:1; /**< bit: 6 LON Short Frame Error Interrupt Disable */ + uint32_t LCRCE:1; /**< bit: 7 LON CRC Error Interrupt Disable */ + uint32_t :16; /**< bit: 8..23 Reserved */ + uint32_t LTXD:1; /**< bit: 24 LON Transmission Done Interrupt Disable */ + uint32_t LCOL:1; /**< bit: 25 LON Collision Interrupt Disable */ + uint32_t LFET:1; /**< bit: 26 LON Frame Early Termination Interrupt Disable */ + uint32_t LRXD:1; /**< bit: 27 LON Reception Done Interrupt Disable */ + uint32_t LBLOVFE:1; /**< bit: 28 LON Backlog Overflow Error Interrupt Disable */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + struct { // LON_SPI mode + uint32_t :10; /**< bit: 0..9 Reserved */ + uint32_t UNRE:1; /**< bit: 10 SPI Underrun Error Interrupt Disable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } LON_SPI; /**< Structure used for LON_SPI mode access */ + uint32_t reg; /**< Type used for register access */ +} US_IDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IDR_OFFSET (0x0C) /**< (US_IDR) Interrupt Disable Register Offset */ + +#define US_IDR_RXRDY_Pos 0 /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_RXRDY_Msk (_U_(0x1) << US_IDR_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_RXRDY US_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_RXRDY_Msk instead */ +#define US_IDR_TXRDY_Pos 1 /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_TXRDY_Msk (_U_(0x1) << US_IDR_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_TXRDY US_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_TXRDY_Msk instead */ +#define US_IDR_OVRE_Pos 5 /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_OVRE_Msk (_U_(0x1) << US_IDR_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_OVRE US_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_OVRE_Msk instead */ +#define US_IDR_TXEMPTY_Pos 9 /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_TXEMPTY_Msk (_U_(0x1) << US_IDR_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_TXEMPTY US_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_TXEMPTY_Msk instead */ +#define US_IDR_RIIC_Pos 16 /**< (US_IDR) Ring Indicator Input Change Disable Position */ +#define US_IDR_RIIC_Msk (_U_(0x1) << US_IDR_RIIC_Pos) /**< (US_IDR) Ring Indicator Input Change Disable Mask */ +#define US_IDR_RIIC US_IDR_RIIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_RIIC_Msk instead */ +#define US_IDR_DSRIC_Pos 17 /**< (US_IDR) Data Set Ready Input Change Disable Position */ +#define US_IDR_DSRIC_Msk (_U_(0x1) << US_IDR_DSRIC_Pos) /**< (US_IDR) Data Set Ready Input Change Disable Mask */ +#define US_IDR_DSRIC US_IDR_DSRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_DSRIC_Msk instead */ +#define US_IDR_DCDIC_Pos 18 /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Position */ +#define US_IDR_DCDIC_Msk (_U_(0x1) << US_IDR_DCDIC_Pos) /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Mask */ +#define US_IDR_DCDIC US_IDR_DCDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_DCDIC_Msk instead */ +#define US_IDR_MASK _U_(0x70223) /**< \deprecated (US_IDR) Register MASK (Use US_IDR_Msk instead) */ +#define US_IDR_Msk _U_(0x70223) /**< (US_IDR) Register Mask */ + +/* USART mode */ +#define US_IDR_USART_RXBRK_Pos 2 /**< (US_IDR) Receiver Break Interrupt Disable Position */ +#define US_IDR_USART_RXBRK_Msk (_U_(0x1) << US_IDR_USART_RXBRK_Pos) /**< (US_IDR) Receiver Break Interrupt Disable Mask */ +#define US_IDR_USART_RXBRK US_IDR_USART_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_RXBRK_Msk instead */ +#define US_IDR_USART_ITER_Pos 10 /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Position */ +#define US_IDR_USART_ITER_Msk (_U_(0x1) << US_IDR_USART_ITER_Pos) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Mask */ +#define US_IDR_USART_ITER US_IDR_USART_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_ITER_Msk instead */ +#define US_IDR_USART_NACK_Pos 13 /**< (US_IDR) Non Acknowledge Interrupt Disable Position */ +#define US_IDR_USART_NACK_Msk (_U_(0x1) << US_IDR_USART_NACK_Pos) /**< (US_IDR) Non Acknowledge Interrupt Disable Mask */ +#define US_IDR_USART_NACK US_IDR_USART_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_NACK_Msk instead */ +#define US_IDR_USART_CTSIC_Pos 19 /**< (US_IDR) Clear to Send Input Change Interrupt Disable Position */ +#define US_IDR_USART_CTSIC_Msk (_U_(0x1) << US_IDR_USART_CTSIC_Pos) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Mask */ +#define US_IDR_USART_CTSIC US_IDR_USART_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_CTSIC_Msk instead */ +#define US_IDR_USART_MANE_Pos 24 /**< (US_IDR) Manchester Error Interrupt Disable Position */ +#define US_IDR_USART_MANE_Msk (_U_(0x1) << US_IDR_USART_MANE_Pos) /**< (US_IDR) Manchester Error Interrupt Disable Mask */ +#define US_IDR_USART_MANE US_IDR_USART_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_MANE_Msk instead */ +#define US_IDR_USART_MASK _U_(0x1082404) /**< \deprecated (US_IDR_USART) Register MASK (Use US_IDR_USART_Msk instead) */ +#define US_IDR_USART_Msk _U_(0x1082404) /**< (US_IDR_USART) Register Mask */ + +/* USART_LIN mode */ +#define US_IDR_USART_LIN_FRAME_Pos 6 /**< (US_IDR) Framing Error Interrupt Disable Position */ +#define US_IDR_USART_LIN_FRAME_Msk (_U_(0x1) << US_IDR_USART_LIN_FRAME_Pos) /**< (US_IDR) Framing Error Interrupt Disable Mask */ +#define US_IDR_USART_LIN_FRAME US_IDR_USART_LIN_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_LIN_FRAME_Msk instead */ +#define US_IDR_USART_LIN_PARE_Pos 7 /**< (US_IDR) Parity Error Interrupt Disable Position */ +#define US_IDR_USART_LIN_PARE_Msk (_U_(0x1) << US_IDR_USART_LIN_PARE_Pos) /**< (US_IDR) Parity Error Interrupt Disable Mask */ +#define US_IDR_USART_LIN_PARE US_IDR_USART_LIN_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_LIN_PARE_Msk instead */ +#define US_IDR_USART_LIN_TIMEOUT_Pos 8 /**< (US_IDR) Timeout Interrupt Disable Position */ +#define US_IDR_USART_LIN_TIMEOUT_Msk (_U_(0x1) << US_IDR_USART_LIN_TIMEOUT_Pos) /**< (US_IDR) Timeout Interrupt Disable Mask */ +#define US_IDR_USART_LIN_TIMEOUT US_IDR_USART_LIN_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_USART_LIN_TIMEOUT_Msk instead */ +#define US_IDR_USART_LIN_MASK _U_(0x1C0) /**< \deprecated (US_IDR_USART_LIN) Register MASK (Use US_IDR_USART_LIN_Msk instead) */ +#define US_IDR_USART_LIN_Msk _U_(0x1C0) /**< (US_IDR_USART_LIN) Register Mask */ + +/* SPI mode */ +#define US_IDR_SPI_NSSE_Pos 19 /**< (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IDR_SPI_NSSE_Msk (_U_(0x1) << US_IDR_SPI_NSSE_Pos) /**< (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IDR_SPI_NSSE US_IDR_SPI_NSSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_SPI_NSSE_Msk instead */ +#define US_IDR_SPI_MASK _U_(0x80000) /**< \deprecated (US_IDR_SPI) Register MASK (Use US_IDR_SPI_Msk instead) */ +#define US_IDR_SPI_Msk _U_(0x80000) /**< (US_IDR_SPI) Register Mask */ + +/* LIN mode */ +#define US_IDR_LIN_LINBK_Pos 13 /**< (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable Position */ +#define US_IDR_LIN_LINBK_Msk (_U_(0x1) << US_IDR_LIN_LINBK_Pos) /**< (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable Mask */ +#define US_IDR_LIN_LINBK US_IDR_LIN_LINBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINBK_Msk instead */ +#define US_IDR_LIN_LINID_Pos 14 /**< (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable Position */ +#define US_IDR_LIN_LINID_Msk (_U_(0x1) << US_IDR_LIN_LINID_Pos) /**< (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable Mask */ +#define US_IDR_LIN_LINID US_IDR_LIN_LINID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINID_Msk instead */ +#define US_IDR_LIN_LINTC_Pos 15 /**< (US_IDR) LIN Transfer Completed Interrupt Disable Position */ +#define US_IDR_LIN_LINTC_Msk (_U_(0x1) << US_IDR_LIN_LINTC_Pos) /**< (US_IDR) LIN Transfer Completed Interrupt Disable Mask */ +#define US_IDR_LIN_LINTC US_IDR_LIN_LINTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINTC_Msk instead */ +#define US_IDR_LIN_LINBE_Pos 25 /**< (US_IDR) LIN Bus Error Interrupt Disable Position */ +#define US_IDR_LIN_LINBE_Msk (_U_(0x1) << US_IDR_LIN_LINBE_Pos) /**< (US_IDR) LIN Bus Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINBE US_IDR_LIN_LINBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINBE_Msk instead */ +#define US_IDR_LIN_LINISFE_Pos 26 /**< (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable Position */ +#define US_IDR_LIN_LINISFE_Msk (_U_(0x1) << US_IDR_LIN_LINISFE_Pos) /**< (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINISFE US_IDR_LIN_LINISFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINISFE_Msk instead */ +#define US_IDR_LIN_LINIPE_Pos 27 /**< (US_IDR) LIN Identifier Parity Interrupt Disable Position */ +#define US_IDR_LIN_LINIPE_Msk (_U_(0x1) << US_IDR_LIN_LINIPE_Pos) /**< (US_IDR) LIN Identifier Parity Interrupt Disable Mask */ +#define US_IDR_LIN_LINIPE US_IDR_LIN_LINIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINIPE_Msk instead */ +#define US_IDR_LIN_LINCE_Pos 28 /**< (US_IDR) LIN Checksum Error Interrupt Disable Position */ +#define US_IDR_LIN_LINCE_Msk (_U_(0x1) << US_IDR_LIN_LINCE_Pos) /**< (US_IDR) LIN Checksum Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINCE US_IDR_LIN_LINCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINCE_Msk instead */ +#define US_IDR_LIN_LINSNRE_Pos 29 /**< (US_IDR) LIN Slave Not Responding Error Interrupt Disable Position */ +#define US_IDR_LIN_LINSNRE_Msk (_U_(0x1) << US_IDR_LIN_LINSNRE_Pos) /**< (US_IDR) LIN Slave Not Responding Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINSNRE US_IDR_LIN_LINSNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINSNRE_Msk instead */ +#define US_IDR_LIN_LINSTE_Pos 30 /**< (US_IDR) LIN Synch Tolerance Error Interrupt Disable Position */ +#define US_IDR_LIN_LINSTE_Msk (_U_(0x1) << US_IDR_LIN_LINSTE_Pos) /**< (US_IDR) LIN Synch Tolerance Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINSTE US_IDR_LIN_LINSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINSTE_Msk instead */ +#define US_IDR_LIN_LINHTE_Pos 31 /**< (US_IDR) LIN Header Timeout Error Interrupt Disable Position */ +#define US_IDR_LIN_LINHTE_Msk (_U_(0x1) << US_IDR_LIN_LINHTE_Pos) /**< (US_IDR) LIN Header Timeout Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINHTE US_IDR_LIN_LINHTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LIN_LINHTE_Msk instead */ +#define US_IDR_LIN_MASK _U_(0xFE00E000) /**< \deprecated (US_IDR_LIN) Register MASK (Use US_IDR_LIN_Msk instead) */ +#define US_IDR_LIN_Msk _U_(0xFE00E000) /**< (US_IDR_LIN) Register Mask */ + +/* LON mode */ +#define US_IDR_LON_LSFE_Pos 6 /**< (US_IDR) LON Short Frame Error Interrupt Disable Position */ +#define US_IDR_LON_LSFE_Msk (_U_(0x1) << US_IDR_LON_LSFE_Pos) /**< (US_IDR) LON Short Frame Error Interrupt Disable Mask */ +#define US_IDR_LON_LSFE US_IDR_LON_LSFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LSFE_Msk instead */ +#define US_IDR_LON_LCRCE_Pos 7 /**< (US_IDR) LON CRC Error Interrupt Disable Position */ +#define US_IDR_LON_LCRCE_Msk (_U_(0x1) << US_IDR_LON_LCRCE_Pos) /**< (US_IDR) LON CRC Error Interrupt Disable Mask */ +#define US_IDR_LON_LCRCE US_IDR_LON_LCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LCRCE_Msk instead */ +#define US_IDR_LON_LTXD_Pos 24 /**< (US_IDR) LON Transmission Done Interrupt Disable Position */ +#define US_IDR_LON_LTXD_Msk (_U_(0x1) << US_IDR_LON_LTXD_Pos) /**< (US_IDR) LON Transmission Done Interrupt Disable Mask */ +#define US_IDR_LON_LTXD US_IDR_LON_LTXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LTXD_Msk instead */ +#define US_IDR_LON_LCOL_Pos 25 /**< (US_IDR) LON Collision Interrupt Disable Position */ +#define US_IDR_LON_LCOL_Msk (_U_(0x1) << US_IDR_LON_LCOL_Pos) /**< (US_IDR) LON Collision Interrupt Disable Mask */ +#define US_IDR_LON_LCOL US_IDR_LON_LCOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LCOL_Msk instead */ +#define US_IDR_LON_LFET_Pos 26 /**< (US_IDR) LON Frame Early Termination Interrupt Disable Position */ +#define US_IDR_LON_LFET_Msk (_U_(0x1) << US_IDR_LON_LFET_Pos) /**< (US_IDR) LON Frame Early Termination Interrupt Disable Mask */ +#define US_IDR_LON_LFET US_IDR_LON_LFET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LFET_Msk instead */ +#define US_IDR_LON_LRXD_Pos 27 /**< (US_IDR) LON Reception Done Interrupt Disable Position */ +#define US_IDR_LON_LRXD_Msk (_U_(0x1) << US_IDR_LON_LRXD_Pos) /**< (US_IDR) LON Reception Done Interrupt Disable Mask */ +#define US_IDR_LON_LRXD US_IDR_LON_LRXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LRXD_Msk instead */ +#define US_IDR_LON_LBLOVFE_Pos 28 /**< (US_IDR) LON Backlog Overflow Error Interrupt Disable Position */ +#define US_IDR_LON_LBLOVFE_Msk (_U_(0x1) << US_IDR_LON_LBLOVFE_Pos) /**< (US_IDR) LON Backlog Overflow Error Interrupt Disable Mask */ +#define US_IDR_LON_LBLOVFE US_IDR_LON_LBLOVFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_LBLOVFE_Msk instead */ +#define US_IDR_LON_MASK _U_(0x1F0000C0) /**< \deprecated (US_IDR_LON) Register MASK (Use US_IDR_LON_Msk instead) */ +#define US_IDR_LON_Msk _U_(0x1F0000C0) /**< (US_IDR_LON) Register Mask */ + +/* LON_SPI mode */ +#define US_IDR_LON_SPI_UNRE_Pos 10 /**< (US_IDR) SPI Underrun Error Interrupt Disable Position */ +#define US_IDR_LON_SPI_UNRE_Msk (_U_(0x1) << US_IDR_LON_SPI_UNRE_Pos) /**< (US_IDR) SPI Underrun Error Interrupt Disable Mask */ +#define US_IDR_LON_SPI_UNRE US_IDR_LON_SPI_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IDR_LON_SPI_UNRE_Msk instead */ +#define US_IDR_LON_SPI_MASK _U_(0x400) /**< \deprecated (US_IDR_LON_SPI) Register MASK (Use US_IDR_LON_SPI_Msk instead) */ +#define US_IDR_LON_SPI_Msk _U_(0x400) /**< (US_IDR_LON_SPI) Register Mask */ + + +/* -------- US_IMR : (USART Offset: 0x10) (R/ 32) Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 RXRDY Interrupt Mask */ + uint32_t TXRDY:1; /**< bit: 1 TXRDY Interrupt Mask */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Overrun Error Interrupt Mask */ + uint32_t :3; /**< bit: 6..8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 TXEMPTY Interrupt Mask */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t RIIC:1; /**< bit: 16 Ring Indicator Input Change Mask */ + uint32_t DSRIC:1; /**< bit: 17 Data Set Ready Input Change Mask */ + uint32_t DCDIC:1; /**< bit: 18 Data Carrier Detect Input Change Interrupt Mask */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXBRK:1; /**< bit: 2 Receiver Break Interrupt Mask */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t ITER:1; /**< bit: 10 Max Number of Repetitions Reached Interrupt Mask */ + uint32_t :2; /**< bit: 11..12 Reserved */ + uint32_t NACK:1; /**< bit: 13 Non Acknowledge Interrupt Mask */ + uint32_t :5; /**< bit: 14..18 Reserved */ + uint32_t CTSIC:1; /**< bit: 19 Clear to Send Input Change Interrupt Mask */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t MANE:1; /**< bit: 24 Manchester Error Interrupt Mask */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // USART_LIN mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t FRAME:1; /**< bit: 6 Framing Error Interrupt Mask */ + uint32_t PARE:1; /**< bit: 7 Parity Error Interrupt Mask */ + uint32_t TIMEOUT:1; /**< bit: 8 Timeout Interrupt Mask */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } USART_LIN; /**< Structure used for USART_LIN mode access */ + struct { // SPI mode + uint32_t :19; /**< bit: 0..18 Reserved */ + uint32_t NSSE:1; /**< bit: 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + struct { // LIN mode + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t LINBK:1; /**< bit: 13 LIN Break Sent or LIN Break Received Interrupt Mask */ + uint32_t LINID:1; /**< bit: 14 LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ + uint32_t LINTC:1; /**< bit: 15 LIN Transfer Completed Interrupt Mask */ + uint32_t :9; /**< bit: 16..24 Reserved */ + uint32_t LINBE:1; /**< bit: 25 LIN Bus Error Interrupt Mask */ + uint32_t LINISFE:1; /**< bit: 26 LIN Inconsistent Synch Field Error Interrupt Mask */ + uint32_t LINIPE:1; /**< bit: 27 LIN Identifier Parity Interrupt Mask */ + uint32_t LINCE:1; /**< bit: 28 LIN Checksum Error Interrupt Mask */ + uint32_t LINSNRE:1; /**< bit: 29 LIN Slave Not Responding Error Interrupt Mask */ + uint32_t LINSTE:1; /**< bit: 30 LIN Synch Tolerance Error Interrupt Mask */ + uint32_t LINHTE:1; /**< bit: 31 LIN Header Timeout Error Interrupt Mask */ + } LIN; /**< Structure used for LIN mode access */ + struct { // LON mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t LSFE:1; /**< bit: 6 LON Short Frame Error Interrupt Mask */ + uint32_t LCRCE:1; /**< bit: 7 LON CRC Error Interrupt Mask */ + uint32_t :16; /**< bit: 8..23 Reserved */ + uint32_t LTXD:1; /**< bit: 24 LON Transmission Done Interrupt Mask */ + uint32_t LCOL:1; /**< bit: 25 LON Collision Interrupt Mask */ + uint32_t LFET:1; /**< bit: 26 LON Frame Early Termination Interrupt Mask */ + uint32_t LRXD:1; /**< bit: 27 LON Reception Done Interrupt Mask */ + uint32_t LBLOVFE:1; /**< bit: 28 LON Backlog Overflow Error Interrupt Mask */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + struct { // LON_SPI mode + uint32_t :10; /**< bit: 0..9 Reserved */ + uint32_t UNRE:1; /**< bit: 10 SPI Underrun Error Interrupt Mask */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } LON_SPI; /**< Structure used for LON_SPI mode access */ + uint32_t reg; /**< Type used for register access */ +} US_IMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IMR_OFFSET (0x10) /**< (US_IMR) Interrupt Mask Register Offset */ + +#define US_IMR_RXRDY_Pos 0 /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_RXRDY_Msk (_U_(0x1) << US_IMR_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_RXRDY US_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_RXRDY_Msk instead */ +#define US_IMR_TXRDY_Pos 1 /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_TXRDY_Msk (_U_(0x1) << US_IMR_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_TXRDY US_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_TXRDY_Msk instead */ +#define US_IMR_OVRE_Pos 5 /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_OVRE_Msk (_U_(0x1) << US_IMR_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_OVRE US_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_OVRE_Msk instead */ +#define US_IMR_TXEMPTY_Pos 9 /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_TXEMPTY_Msk (_U_(0x1) << US_IMR_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_TXEMPTY US_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_TXEMPTY_Msk instead */ +#define US_IMR_RIIC_Pos 16 /**< (US_IMR) Ring Indicator Input Change Mask Position */ +#define US_IMR_RIIC_Msk (_U_(0x1) << US_IMR_RIIC_Pos) /**< (US_IMR) Ring Indicator Input Change Mask Mask */ +#define US_IMR_RIIC US_IMR_RIIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_RIIC_Msk instead */ +#define US_IMR_DSRIC_Pos 17 /**< (US_IMR) Data Set Ready Input Change Mask Position */ +#define US_IMR_DSRIC_Msk (_U_(0x1) << US_IMR_DSRIC_Pos) /**< (US_IMR) Data Set Ready Input Change Mask Mask */ +#define US_IMR_DSRIC US_IMR_DSRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_DSRIC_Msk instead */ +#define US_IMR_DCDIC_Pos 18 /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Position */ +#define US_IMR_DCDIC_Msk (_U_(0x1) << US_IMR_DCDIC_Pos) /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Mask */ +#define US_IMR_DCDIC US_IMR_DCDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_DCDIC_Msk instead */ +#define US_IMR_MASK _U_(0x70223) /**< \deprecated (US_IMR) Register MASK (Use US_IMR_Msk instead) */ +#define US_IMR_Msk _U_(0x70223) /**< (US_IMR) Register Mask */ + +/* USART mode */ +#define US_IMR_USART_RXBRK_Pos 2 /**< (US_IMR) Receiver Break Interrupt Mask Position */ +#define US_IMR_USART_RXBRK_Msk (_U_(0x1) << US_IMR_USART_RXBRK_Pos) /**< (US_IMR) Receiver Break Interrupt Mask Mask */ +#define US_IMR_USART_RXBRK US_IMR_USART_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_RXBRK_Msk instead */ +#define US_IMR_USART_ITER_Pos 10 /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Position */ +#define US_IMR_USART_ITER_Msk (_U_(0x1) << US_IMR_USART_ITER_Pos) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Mask */ +#define US_IMR_USART_ITER US_IMR_USART_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_ITER_Msk instead */ +#define US_IMR_USART_NACK_Pos 13 /**< (US_IMR) Non Acknowledge Interrupt Mask Position */ +#define US_IMR_USART_NACK_Msk (_U_(0x1) << US_IMR_USART_NACK_Pos) /**< (US_IMR) Non Acknowledge Interrupt Mask Mask */ +#define US_IMR_USART_NACK US_IMR_USART_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_NACK_Msk instead */ +#define US_IMR_USART_CTSIC_Pos 19 /**< (US_IMR) Clear to Send Input Change Interrupt Mask Position */ +#define US_IMR_USART_CTSIC_Msk (_U_(0x1) << US_IMR_USART_CTSIC_Pos) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Mask */ +#define US_IMR_USART_CTSIC US_IMR_USART_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_CTSIC_Msk instead */ +#define US_IMR_USART_MANE_Pos 24 /**< (US_IMR) Manchester Error Interrupt Mask Position */ +#define US_IMR_USART_MANE_Msk (_U_(0x1) << US_IMR_USART_MANE_Pos) /**< (US_IMR) Manchester Error Interrupt Mask Mask */ +#define US_IMR_USART_MANE US_IMR_USART_MANE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_MANE_Msk instead */ +#define US_IMR_USART_MASK _U_(0x1082404) /**< \deprecated (US_IMR_USART) Register MASK (Use US_IMR_USART_Msk instead) */ +#define US_IMR_USART_Msk _U_(0x1082404) /**< (US_IMR_USART) Register Mask */ + +/* USART_LIN mode */ +#define US_IMR_USART_LIN_FRAME_Pos 6 /**< (US_IMR) Framing Error Interrupt Mask Position */ +#define US_IMR_USART_LIN_FRAME_Msk (_U_(0x1) << US_IMR_USART_LIN_FRAME_Pos) /**< (US_IMR) Framing Error Interrupt Mask Mask */ +#define US_IMR_USART_LIN_FRAME US_IMR_USART_LIN_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_LIN_FRAME_Msk instead */ +#define US_IMR_USART_LIN_PARE_Pos 7 /**< (US_IMR) Parity Error Interrupt Mask Position */ +#define US_IMR_USART_LIN_PARE_Msk (_U_(0x1) << US_IMR_USART_LIN_PARE_Pos) /**< (US_IMR) Parity Error Interrupt Mask Mask */ +#define US_IMR_USART_LIN_PARE US_IMR_USART_LIN_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_LIN_PARE_Msk instead */ +#define US_IMR_USART_LIN_TIMEOUT_Pos 8 /**< (US_IMR) Timeout Interrupt Mask Position */ +#define US_IMR_USART_LIN_TIMEOUT_Msk (_U_(0x1) << US_IMR_USART_LIN_TIMEOUT_Pos) /**< (US_IMR) Timeout Interrupt Mask Mask */ +#define US_IMR_USART_LIN_TIMEOUT US_IMR_USART_LIN_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_USART_LIN_TIMEOUT_Msk instead */ +#define US_IMR_USART_LIN_MASK _U_(0x1C0) /**< \deprecated (US_IMR_USART_LIN) Register MASK (Use US_IMR_USART_LIN_Msk instead) */ +#define US_IMR_USART_LIN_Msk _U_(0x1C0) /**< (US_IMR_USART_LIN) Register Mask */ + +/* SPI mode */ +#define US_IMR_SPI_NSSE_Pos 19 /**< (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IMR_SPI_NSSE_Msk (_U_(0x1) << US_IMR_SPI_NSSE_Pos) /**< (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IMR_SPI_NSSE US_IMR_SPI_NSSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_SPI_NSSE_Msk instead */ +#define US_IMR_SPI_MASK _U_(0x80000) /**< \deprecated (US_IMR_SPI) Register MASK (Use US_IMR_SPI_Msk instead) */ +#define US_IMR_SPI_Msk _U_(0x80000) /**< (US_IMR_SPI) Register Mask */ + +/* LIN mode */ +#define US_IMR_LIN_LINBK_Pos 13 /**< (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask Position */ +#define US_IMR_LIN_LINBK_Msk (_U_(0x1) << US_IMR_LIN_LINBK_Pos) /**< (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask Mask */ +#define US_IMR_LIN_LINBK US_IMR_LIN_LINBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINBK_Msk instead */ +#define US_IMR_LIN_LINID_Pos 14 /**< (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask Position */ +#define US_IMR_LIN_LINID_Msk (_U_(0x1) << US_IMR_LIN_LINID_Pos) /**< (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask Mask */ +#define US_IMR_LIN_LINID US_IMR_LIN_LINID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINID_Msk instead */ +#define US_IMR_LIN_LINTC_Pos 15 /**< (US_IMR) LIN Transfer Completed Interrupt Mask Position */ +#define US_IMR_LIN_LINTC_Msk (_U_(0x1) << US_IMR_LIN_LINTC_Pos) /**< (US_IMR) LIN Transfer Completed Interrupt Mask Mask */ +#define US_IMR_LIN_LINTC US_IMR_LIN_LINTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINTC_Msk instead */ +#define US_IMR_LIN_LINBE_Pos 25 /**< (US_IMR) LIN Bus Error Interrupt Mask Position */ +#define US_IMR_LIN_LINBE_Msk (_U_(0x1) << US_IMR_LIN_LINBE_Pos) /**< (US_IMR) LIN Bus Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINBE US_IMR_LIN_LINBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINBE_Msk instead */ +#define US_IMR_LIN_LINISFE_Pos 26 /**< (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask Position */ +#define US_IMR_LIN_LINISFE_Msk (_U_(0x1) << US_IMR_LIN_LINISFE_Pos) /**< (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINISFE US_IMR_LIN_LINISFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINISFE_Msk instead */ +#define US_IMR_LIN_LINIPE_Pos 27 /**< (US_IMR) LIN Identifier Parity Interrupt Mask Position */ +#define US_IMR_LIN_LINIPE_Msk (_U_(0x1) << US_IMR_LIN_LINIPE_Pos) /**< (US_IMR) LIN Identifier Parity Interrupt Mask Mask */ +#define US_IMR_LIN_LINIPE US_IMR_LIN_LINIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINIPE_Msk instead */ +#define US_IMR_LIN_LINCE_Pos 28 /**< (US_IMR) LIN Checksum Error Interrupt Mask Position */ +#define US_IMR_LIN_LINCE_Msk (_U_(0x1) << US_IMR_LIN_LINCE_Pos) /**< (US_IMR) LIN Checksum Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINCE US_IMR_LIN_LINCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINCE_Msk instead */ +#define US_IMR_LIN_LINSNRE_Pos 29 /**< (US_IMR) LIN Slave Not Responding Error Interrupt Mask Position */ +#define US_IMR_LIN_LINSNRE_Msk (_U_(0x1) << US_IMR_LIN_LINSNRE_Pos) /**< (US_IMR) LIN Slave Not Responding Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINSNRE US_IMR_LIN_LINSNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINSNRE_Msk instead */ +#define US_IMR_LIN_LINSTE_Pos 30 /**< (US_IMR) LIN Synch Tolerance Error Interrupt Mask Position */ +#define US_IMR_LIN_LINSTE_Msk (_U_(0x1) << US_IMR_LIN_LINSTE_Pos) /**< (US_IMR) LIN Synch Tolerance Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINSTE US_IMR_LIN_LINSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINSTE_Msk instead */ +#define US_IMR_LIN_LINHTE_Pos 31 /**< (US_IMR) LIN Header Timeout Error Interrupt Mask Position */ +#define US_IMR_LIN_LINHTE_Msk (_U_(0x1) << US_IMR_LIN_LINHTE_Pos) /**< (US_IMR) LIN Header Timeout Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINHTE US_IMR_LIN_LINHTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LIN_LINHTE_Msk instead */ +#define US_IMR_LIN_MASK _U_(0xFE00E000) /**< \deprecated (US_IMR_LIN) Register MASK (Use US_IMR_LIN_Msk instead) */ +#define US_IMR_LIN_Msk _U_(0xFE00E000) /**< (US_IMR_LIN) Register Mask */ + +/* LON mode */ +#define US_IMR_LON_LSFE_Pos 6 /**< (US_IMR) LON Short Frame Error Interrupt Mask Position */ +#define US_IMR_LON_LSFE_Msk (_U_(0x1) << US_IMR_LON_LSFE_Pos) /**< (US_IMR) LON Short Frame Error Interrupt Mask Mask */ +#define US_IMR_LON_LSFE US_IMR_LON_LSFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LSFE_Msk instead */ +#define US_IMR_LON_LCRCE_Pos 7 /**< (US_IMR) LON CRC Error Interrupt Mask Position */ +#define US_IMR_LON_LCRCE_Msk (_U_(0x1) << US_IMR_LON_LCRCE_Pos) /**< (US_IMR) LON CRC Error Interrupt Mask Mask */ +#define US_IMR_LON_LCRCE US_IMR_LON_LCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LCRCE_Msk instead */ +#define US_IMR_LON_LTXD_Pos 24 /**< (US_IMR) LON Transmission Done Interrupt Mask Position */ +#define US_IMR_LON_LTXD_Msk (_U_(0x1) << US_IMR_LON_LTXD_Pos) /**< (US_IMR) LON Transmission Done Interrupt Mask Mask */ +#define US_IMR_LON_LTXD US_IMR_LON_LTXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LTXD_Msk instead */ +#define US_IMR_LON_LCOL_Pos 25 /**< (US_IMR) LON Collision Interrupt Mask Position */ +#define US_IMR_LON_LCOL_Msk (_U_(0x1) << US_IMR_LON_LCOL_Pos) /**< (US_IMR) LON Collision Interrupt Mask Mask */ +#define US_IMR_LON_LCOL US_IMR_LON_LCOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LCOL_Msk instead */ +#define US_IMR_LON_LFET_Pos 26 /**< (US_IMR) LON Frame Early Termination Interrupt Mask Position */ +#define US_IMR_LON_LFET_Msk (_U_(0x1) << US_IMR_LON_LFET_Pos) /**< (US_IMR) LON Frame Early Termination Interrupt Mask Mask */ +#define US_IMR_LON_LFET US_IMR_LON_LFET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LFET_Msk instead */ +#define US_IMR_LON_LRXD_Pos 27 /**< (US_IMR) LON Reception Done Interrupt Mask Position */ +#define US_IMR_LON_LRXD_Msk (_U_(0x1) << US_IMR_LON_LRXD_Pos) /**< (US_IMR) LON Reception Done Interrupt Mask Mask */ +#define US_IMR_LON_LRXD US_IMR_LON_LRXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LRXD_Msk instead */ +#define US_IMR_LON_LBLOVFE_Pos 28 /**< (US_IMR) LON Backlog Overflow Error Interrupt Mask Position */ +#define US_IMR_LON_LBLOVFE_Msk (_U_(0x1) << US_IMR_LON_LBLOVFE_Pos) /**< (US_IMR) LON Backlog Overflow Error Interrupt Mask Mask */ +#define US_IMR_LON_LBLOVFE US_IMR_LON_LBLOVFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_LBLOVFE_Msk instead */ +#define US_IMR_LON_MASK _U_(0x1F0000C0) /**< \deprecated (US_IMR_LON) Register MASK (Use US_IMR_LON_Msk instead) */ +#define US_IMR_LON_Msk _U_(0x1F0000C0) /**< (US_IMR_LON) Register Mask */ + +/* LON_SPI mode */ +#define US_IMR_LON_SPI_UNRE_Pos 10 /**< (US_IMR) SPI Underrun Error Interrupt Mask Position */ +#define US_IMR_LON_SPI_UNRE_Msk (_U_(0x1) << US_IMR_LON_SPI_UNRE_Pos) /**< (US_IMR) SPI Underrun Error Interrupt Mask Mask */ +#define US_IMR_LON_SPI_UNRE US_IMR_LON_SPI_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_IMR_LON_SPI_UNRE_Msk instead */ +#define US_IMR_LON_SPI_MASK _U_(0x400) /**< \deprecated (US_IMR_LON_SPI) Register MASK (Use US_IMR_LON_SPI_Msk instead) */ +#define US_IMR_LON_SPI_Msk _U_(0x400) /**< (US_IMR_LON_SPI) Register Mask */ + + +/* -------- US_CSR : (USART Offset: 0x14) (R/ 32) Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXRDY:1; /**< bit: 0 Receiver Ready (cleared by reading US_RHR) */ + uint32_t TXRDY:1; /**< bit: 1 Transmitter Ready (cleared by writing US_THR) */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVRE:1; /**< bit: 5 Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ + uint32_t :3; /**< bit: 6..8 Reserved */ + uint32_t TXEMPTY:1; /**< bit: 9 Transmitter Empty (cleared by writing US_THR) */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t RIIC:1; /**< bit: 16 Ring Indicator Input Change Flag (cleared on read) */ + uint32_t DSRIC:1; /**< bit: 17 Data Set Ready Input Change Flag (cleared on read) */ + uint32_t DCDIC:1; /**< bit: 18 Data Carrier Detect Input Change Flag (cleared on read) */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // USART mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXBRK:1; /**< bit: 2 Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ + uint32_t :7; /**< bit: 3..9 Reserved */ + uint32_t ITER:1; /**< bit: 10 Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) */ + uint32_t :2; /**< bit: 11..12 Reserved */ + uint32_t NACK:1; /**< bit: 13 Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) */ + uint32_t :5; /**< bit: 14..18 Reserved */ + uint32_t CTSIC:1; /**< bit: 19 Clear to Send Input Change Flag (cleared on read) */ + uint32_t RI:1; /**< bit: 20 Image of RI Input */ + uint32_t DSR:1; /**< bit: 21 Image of DSR Input */ + uint32_t DCD:1; /**< bit: 22 Image of DCD Input */ + uint32_t CTS:1; /**< bit: 23 Image of CTS Input */ + uint32_t MANERR:1; /**< bit: 24 Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // USART_LIN mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t FRAME:1; /**< bit: 6 Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ + uint32_t PARE:1; /**< bit: 7 Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ + uint32_t TIMEOUT:1; /**< bit: 8 Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } USART_LIN; /**< Structure used for USART_LIN mode access */ + struct { // SPI mode + uint32_t :19; /**< bit: 0..18 Reserved */ + uint32_t NSSE:1; /**< bit: 19 NSS Line (Driving CTS Pin) Rising or Falling Edge Event */ + uint32_t :3; /**< bit: 20..22 Reserved */ + uint32_t NSS:1; /**< bit: 23 Image of NSS Line */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } SPI; /**< Structure used for SPI mode access */ + struct { // LIN mode + uint32_t :13; /**< bit: 0..12 Reserved */ + uint32_t LINBK:1; /**< bit: 13 LIN Break Sent or LIN Break Received */ + uint32_t LINID:1; /**< bit: 14 LIN Identifier Sent or LIN Identifier Received */ + uint32_t LINTC:1; /**< bit: 15 LIN Transfer Completed */ + uint32_t :7; /**< bit: 16..22 Reserved */ + uint32_t LINBLS:1; /**< bit: 23 LIN Bus Line Status */ + uint32_t :1; /**< bit: 24 Reserved */ + uint32_t LINBE:1; /**< bit: 25 LIN Bus Error */ + uint32_t LINISFE:1; /**< bit: 26 LIN Inconsistent Synch Field Error */ + uint32_t LINIPE:1; /**< bit: 27 LIN Identifier Parity Error */ + uint32_t LINCE:1; /**< bit: 28 LIN Checksum Error */ + uint32_t LINSNRE:1; /**< bit: 29 LIN Slave Not Responding Error Interrupt Mask */ + uint32_t LINSTE:1; /**< bit: 30 LIN Synch Tolerance Error */ + uint32_t LINHTE:1; /**< bit: 31 LIN Header Timeout Error */ + } LIN; /**< Structure used for LIN mode access */ + struct { // LON mode + uint32_t :6; /**< bit: 0..5 Reserved */ + uint32_t LSFE:1; /**< bit: 6 LON Short Frame Error */ + uint32_t LCRCE:1; /**< bit: 7 LON CRC Error */ + uint32_t :16; /**< bit: 8..23 Reserved */ + uint32_t LTXD:1; /**< bit: 24 LON Transmission End Flag */ + uint32_t LCOL:1; /**< bit: 25 LON Collision Detected Flag */ + uint32_t LFET:1; /**< bit: 26 LON Frame Early Termination */ + uint32_t LRXD:1; /**< bit: 27 LON Reception End Flag */ + uint32_t LBLOVFE:1; /**< bit: 28 LON Backlog Overflow Error */ + uint32_t :3; /**< bit: 29..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + struct { // LON_SPI mode + uint32_t :10; /**< bit: 0..9 Reserved */ + uint32_t UNRE:1; /**< bit: 10 SPI Underrun Error */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } LON_SPI; /**< Structure used for LON_SPI mode access */ + uint32_t reg; /**< Type used for register access */ +} US_CSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_CSR_OFFSET (0x14) /**< (US_CSR) Channel Status Register Offset */ + +#define US_CSR_RXRDY_Pos 0 /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_RXRDY_Msk (_U_(0x1) << US_CSR_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_RXRDY US_CSR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_RXRDY_Msk instead */ +#define US_CSR_TXRDY_Pos 1 /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_TXRDY_Msk (_U_(0x1) << US_CSR_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_TXRDY US_CSR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_TXRDY_Msk instead */ +#define US_CSR_OVRE_Pos 5 /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_OVRE_Msk (_U_(0x1) << US_CSR_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_OVRE US_CSR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_OVRE_Msk instead */ +#define US_CSR_TXEMPTY_Pos 9 /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_TXEMPTY_Msk (_U_(0x1) << US_CSR_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_TXEMPTY US_CSR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_TXEMPTY_Msk instead */ +#define US_CSR_RIIC_Pos 16 /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Position */ +#define US_CSR_RIIC_Msk (_U_(0x1) << US_CSR_RIIC_Pos) /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Mask */ +#define US_CSR_RIIC US_CSR_RIIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_RIIC_Msk instead */ +#define US_CSR_DSRIC_Pos 17 /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Position */ +#define US_CSR_DSRIC_Msk (_U_(0x1) << US_CSR_DSRIC_Pos) /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Mask */ +#define US_CSR_DSRIC US_CSR_DSRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_DSRIC_Msk instead */ +#define US_CSR_DCDIC_Pos 18 /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Position */ +#define US_CSR_DCDIC_Msk (_U_(0x1) << US_CSR_DCDIC_Pos) /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Mask */ +#define US_CSR_DCDIC US_CSR_DCDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_DCDIC_Msk instead */ +#define US_CSR_MASK _U_(0x70223) /**< \deprecated (US_CSR) Register MASK (Use US_CSR_Msk instead) */ +#define US_CSR_Msk _U_(0x70223) /**< (US_CSR) Register Mask */ + +/* USART mode */ +#define US_CSR_USART_RXBRK_Pos 2 /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_RXBRK_Msk (_U_(0x1) << US_CSR_USART_RXBRK_Pos) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_RXBRK US_CSR_USART_RXBRK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_RXBRK_Msk instead */ +#define US_CSR_USART_ITER_Pos 10 /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Position */ +#define US_CSR_USART_ITER_Msk (_U_(0x1) << US_CSR_USART_ITER_Pos) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Mask */ +#define US_CSR_USART_ITER US_CSR_USART_ITER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_ITER_Msk instead */ +#define US_CSR_USART_NACK_Pos 13 /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Position */ +#define US_CSR_USART_NACK_Msk (_U_(0x1) << US_CSR_USART_NACK_Pos) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Mask */ +#define US_CSR_USART_NACK US_CSR_USART_NACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_NACK_Msk instead */ +#define US_CSR_USART_CTSIC_Pos 19 /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Position */ +#define US_CSR_USART_CTSIC_Msk (_U_(0x1) << US_CSR_USART_CTSIC_Pos) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Mask */ +#define US_CSR_USART_CTSIC US_CSR_USART_CTSIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_CTSIC_Msk instead */ +#define US_CSR_USART_RI_Pos 20 /**< (US_CSR) Image of RI Input Position */ +#define US_CSR_USART_RI_Msk (_U_(0x1) << US_CSR_USART_RI_Pos) /**< (US_CSR) Image of RI Input Mask */ +#define US_CSR_USART_RI US_CSR_USART_RI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_RI_Msk instead */ +#define US_CSR_USART_DSR_Pos 21 /**< (US_CSR) Image of DSR Input Position */ +#define US_CSR_USART_DSR_Msk (_U_(0x1) << US_CSR_USART_DSR_Pos) /**< (US_CSR) Image of DSR Input Mask */ +#define US_CSR_USART_DSR US_CSR_USART_DSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_DSR_Msk instead */ +#define US_CSR_USART_DCD_Pos 22 /**< (US_CSR) Image of DCD Input Position */ +#define US_CSR_USART_DCD_Msk (_U_(0x1) << US_CSR_USART_DCD_Pos) /**< (US_CSR) Image of DCD Input Mask */ +#define US_CSR_USART_DCD US_CSR_USART_DCD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_DCD_Msk instead */ +#define US_CSR_USART_CTS_Pos 23 /**< (US_CSR) Image of CTS Input Position */ +#define US_CSR_USART_CTS_Msk (_U_(0x1) << US_CSR_USART_CTS_Pos) /**< (US_CSR) Image of CTS Input Mask */ +#define US_CSR_USART_CTS US_CSR_USART_CTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_CTS_Msk instead */ +#define US_CSR_USART_MANERR_Pos 24 /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_MANERR_Msk (_U_(0x1) << US_CSR_USART_MANERR_Pos) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_MANERR US_CSR_USART_MANERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_MANERR_Msk instead */ +#define US_CSR_USART_MASK _U_(0x1F82404) /**< \deprecated (US_CSR_USART) Register MASK (Use US_CSR_USART_Msk instead) */ +#define US_CSR_USART_Msk _U_(0x1F82404) /**< (US_CSR_USART) Register Mask */ + +/* USART_LIN mode */ +#define US_CSR_USART_LIN_FRAME_Pos 6 /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_LIN_FRAME_Msk (_U_(0x1) << US_CSR_USART_LIN_FRAME_Pos) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_LIN_FRAME US_CSR_USART_LIN_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_LIN_FRAME_Msk instead */ +#define US_CSR_USART_LIN_PARE_Pos 7 /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_LIN_PARE_Msk (_U_(0x1) << US_CSR_USART_LIN_PARE_Pos) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_LIN_PARE US_CSR_USART_LIN_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_LIN_PARE_Msk instead */ +#define US_CSR_USART_LIN_TIMEOUT_Pos 8 /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Position */ +#define US_CSR_USART_LIN_TIMEOUT_Msk (_U_(0x1) << US_CSR_USART_LIN_TIMEOUT_Pos) /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Mask */ +#define US_CSR_USART_LIN_TIMEOUT US_CSR_USART_LIN_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_USART_LIN_TIMEOUT_Msk instead */ +#define US_CSR_USART_LIN_MASK _U_(0x1C0) /**< \deprecated (US_CSR_USART_LIN) Register MASK (Use US_CSR_USART_LIN_Msk instead) */ +#define US_CSR_USART_LIN_Msk _U_(0x1C0) /**< (US_CSR_USART_LIN) Register Mask */ + +/* SPI mode */ +#define US_CSR_SPI_NSSE_Pos 19 /**< (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_CSR_SPI_NSSE_Msk (_U_(0x1) << US_CSR_SPI_NSSE_Pos) /**< (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_CSR_SPI_NSSE US_CSR_SPI_NSSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_SPI_NSSE_Msk instead */ +#define US_CSR_SPI_NSS_Pos 23 /**< (US_CSR) Image of NSS Line Position */ +#define US_CSR_SPI_NSS_Msk (_U_(0x1) << US_CSR_SPI_NSS_Pos) /**< (US_CSR) Image of NSS Line Mask */ +#define US_CSR_SPI_NSS US_CSR_SPI_NSS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_SPI_NSS_Msk instead */ +#define US_CSR_SPI_MASK _U_(0x880000) /**< \deprecated (US_CSR_SPI) Register MASK (Use US_CSR_SPI_Msk instead) */ +#define US_CSR_SPI_Msk _U_(0x880000) /**< (US_CSR_SPI) Register Mask */ + +/* LIN mode */ +#define US_CSR_LIN_LINBK_Pos 13 /**< (US_CSR) LIN Break Sent or LIN Break Received Position */ +#define US_CSR_LIN_LINBK_Msk (_U_(0x1) << US_CSR_LIN_LINBK_Pos) /**< (US_CSR) LIN Break Sent or LIN Break Received Mask */ +#define US_CSR_LIN_LINBK US_CSR_LIN_LINBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINBK_Msk instead */ +#define US_CSR_LIN_LINID_Pos 14 /**< (US_CSR) LIN Identifier Sent or LIN Identifier Received Position */ +#define US_CSR_LIN_LINID_Msk (_U_(0x1) << US_CSR_LIN_LINID_Pos) /**< (US_CSR) LIN Identifier Sent or LIN Identifier Received Mask */ +#define US_CSR_LIN_LINID US_CSR_LIN_LINID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINID_Msk instead */ +#define US_CSR_LIN_LINTC_Pos 15 /**< (US_CSR) LIN Transfer Completed Position */ +#define US_CSR_LIN_LINTC_Msk (_U_(0x1) << US_CSR_LIN_LINTC_Pos) /**< (US_CSR) LIN Transfer Completed Mask */ +#define US_CSR_LIN_LINTC US_CSR_LIN_LINTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINTC_Msk instead */ +#define US_CSR_LIN_LINBLS_Pos 23 /**< (US_CSR) LIN Bus Line Status Position */ +#define US_CSR_LIN_LINBLS_Msk (_U_(0x1) << US_CSR_LIN_LINBLS_Pos) /**< (US_CSR) LIN Bus Line Status Mask */ +#define US_CSR_LIN_LINBLS US_CSR_LIN_LINBLS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINBLS_Msk instead */ +#define US_CSR_LIN_LINBE_Pos 25 /**< (US_CSR) LIN Bus Error Position */ +#define US_CSR_LIN_LINBE_Msk (_U_(0x1) << US_CSR_LIN_LINBE_Pos) /**< (US_CSR) LIN Bus Error Mask */ +#define US_CSR_LIN_LINBE US_CSR_LIN_LINBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINBE_Msk instead */ +#define US_CSR_LIN_LINISFE_Pos 26 /**< (US_CSR) LIN Inconsistent Synch Field Error Position */ +#define US_CSR_LIN_LINISFE_Msk (_U_(0x1) << US_CSR_LIN_LINISFE_Pos) /**< (US_CSR) LIN Inconsistent Synch Field Error Mask */ +#define US_CSR_LIN_LINISFE US_CSR_LIN_LINISFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINISFE_Msk instead */ +#define US_CSR_LIN_LINIPE_Pos 27 /**< (US_CSR) LIN Identifier Parity Error Position */ +#define US_CSR_LIN_LINIPE_Msk (_U_(0x1) << US_CSR_LIN_LINIPE_Pos) /**< (US_CSR) LIN Identifier Parity Error Mask */ +#define US_CSR_LIN_LINIPE US_CSR_LIN_LINIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINIPE_Msk instead */ +#define US_CSR_LIN_LINCE_Pos 28 /**< (US_CSR) LIN Checksum Error Position */ +#define US_CSR_LIN_LINCE_Msk (_U_(0x1) << US_CSR_LIN_LINCE_Pos) /**< (US_CSR) LIN Checksum Error Mask */ +#define US_CSR_LIN_LINCE US_CSR_LIN_LINCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINCE_Msk instead */ +#define US_CSR_LIN_LINSNRE_Pos 29 /**< (US_CSR) LIN Slave Not Responding Error Interrupt Mask Position */ +#define US_CSR_LIN_LINSNRE_Msk (_U_(0x1) << US_CSR_LIN_LINSNRE_Pos) /**< (US_CSR) LIN Slave Not Responding Error Interrupt Mask Mask */ +#define US_CSR_LIN_LINSNRE US_CSR_LIN_LINSNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINSNRE_Msk instead */ +#define US_CSR_LIN_LINSTE_Pos 30 /**< (US_CSR) LIN Synch Tolerance Error Position */ +#define US_CSR_LIN_LINSTE_Msk (_U_(0x1) << US_CSR_LIN_LINSTE_Pos) /**< (US_CSR) LIN Synch Tolerance Error Mask */ +#define US_CSR_LIN_LINSTE US_CSR_LIN_LINSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINSTE_Msk instead */ +#define US_CSR_LIN_LINHTE_Pos 31 /**< (US_CSR) LIN Header Timeout Error Position */ +#define US_CSR_LIN_LINHTE_Msk (_U_(0x1) << US_CSR_LIN_LINHTE_Pos) /**< (US_CSR) LIN Header Timeout Error Mask */ +#define US_CSR_LIN_LINHTE US_CSR_LIN_LINHTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LIN_LINHTE_Msk instead */ +#define US_CSR_LIN_MASK _U_(0xFE80E000) /**< \deprecated (US_CSR_LIN) Register MASK (Use US_CSR_LIN_Msk instead) */ +#define US_CSR_LIN_Msk _U_(0xFE80E000) /**< (US_CSR_LIN) Register Mask */ + +/* LON mode */ +#define US_CSR_LON_LSFE_Pos 6 /**< (US_CSR) LON Short Frame Error Position */ +#define US_CSR_LON_LSFE_Msk (_U_(0x1) << US_CSR_LON_LSFE_Pos) /**< (US_CSR) LON Short Frame Error Mask */ +#define US_CSR_LON_LSFE US_CSR_LON_LSFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LSFE_Msk instead */ +#define US_CSR_LON_LCRCE_Pos 7 /**< (US_CSR) LON CRC Error Position */ +#define US_CSR_LON_LCRCE_Msk (_U_(0x1) << US_CSR_LON_LCRCE_Pos) /**< (US_CSR) LON CRC Error Mask */ +#define US_CSR_LON_LCRCE US_CSR_LON_LCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LCRCE_Msk instead */ +#define US_CSR_LON_LTXD_Pos 24 /**< (US_CSR) LON Transmission End Flag Position */ +#define US_CSR_LON_LTXD_Msk (_U_(0x1) << US_CSR_LON_LTXD_Pos) /**< (US_CSR) LON Transmission End Flag Mask */ +#define US_CSR_LON_LTXD US_CSR_LON_LTXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LTXD_Msk instead */ +#define US_CSR_LON_LCOL_Pos 25 /**< (US_CSR) LON Collision Detected Flag Position */ +#define US_CSR_LON_LCOL_Msk (_U_(0x1) << US_CSR_LON_LCOL_Pos) /**< (US_CSR) LON Collision Detected Flag Mask */ +#define US_CSR_LON_LCOL US_CSR_LON_LCOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LCOL_Msk instead */ +#define US_CSR_LON_LFET_Pos 26 /**< (US_CSR) LON Frame Early Termination Position */ +#define US_CSR_LON_LFET_Msk (_U_(0x1) << US_CSR_LON_LFET_Pos) /**< (US_CSR) LON Frame Early Termination Mask */ +#define US_CSR_LON_LFET US_CSR_LON_LFET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LFET_Msk instead */ +#define US_CSR_LON_LRXD_Pos 27 /**< (US_CSR) LON Reception End Flag Position */ +#define US_CSR_LON_LRXD_Msk (_U_(0x1) << US_CSR_LON_LRXD_Pos) /**< (US_CSR) LON Reception End Flag Mask */ +#define US_CSR_LON_LRXD US_CSR_LON_LRXD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LRXD_Msk instead */ +#define US_CSR_LON_LBLOVFE_Pos 28 /**< (US_CSR) LON Backlog Overflow Error Position */ +#define US_CSR_LON_LBLOVFE_Msk (_U_(0x1) << US_CSR_LON_LBLOVFE_Pos) /**< (US_CSR) LON Backlog Overflow Error Mask */ +#define US_CSR_LON_LBLOVFE US_CSR_LON_LBLOVFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_LBLOVFE_Msk instead */ +#define US_CSR_LON_MASK _U_(0x1F0000C0) /**< \deprecated (US_CSR_LON) Register MASK (Use US_CSR_LON_Msk instead) */ +#define US_CSR_LON_Msk _U_(0x1F0000C0) /**< (US_CSR_LON) Register Mask */ + +/* LON_SPI mode */ +#define US_CSR_LON_SPI_UNRE_Pos 10 /**< (US_CSR) SPI Underrun Error Position */ +#define US_CSR_LON_SPI_UNRE_Msk (_U_(0x1) << US_CSR_LON_SPI_UNRE_Pos) /**< (US_CSR) SPI Underrun Error Mask */ +#define US_CSR_LON_SPI_UNRE US_CSR_LON_SPI_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_CSR_LON_SPI_UNRE_Msk instead */ +#define US_CSR_LON_SPI_MASK _U_(0x400) /**< \deprecated (US_CSR_LON_SPI) Register MASK (Use US_CSR_LON_SPI_Msk instead) */ +#define US_CSR_LON_SPI_Msk _U_(0x400) /**< (US_CSR_LON_SPI) Register Mask */ + + +/* -------- US_RHR : (USART Offset: 0x18) (R/ 32) Receive Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXCHR:9; /**< bit: 0..8 Received Character */ + uint32_t :6; /**< bit: 9..14 Reserved */ + uint32_t RXSYNH:1; /**< bit: 15 Received Sync */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_RHR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_RHR_OFFSET (0x18) /**< (US_RHR) Receive Holding Register Offset */ + +#define US_RHR_RXCHR_Pos 0 /**< (US_RHR) Received Character Position */ +#define US_RHR_RXCHR_Msk (_U_(0x1FF) << US_RHR_RXCHR_Pos) /**< (US_RHR) Received Character Mask */ +#define US_RHR_RXCHR(value) (US_RHR_RXCHR_Msk & ((value) << US_RHR_RXCHR_Pos)) +#define US_RHR_RXSYNH_Pos 15 /**< (US_RHR) Received Sync Position */ +#define US_RHR_RXSYNH_Msk (_U_(0x1) << US_RHR_RXSYNH_Pos) /**< (US_RHR) Received Sync Mask */ +#define US_RHR_RXSYNH US_RHR_RXSYNH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_RHR_RXSYNH_Msk instead */ +#define US_RHR_MASK _U_(0x81FF) /**< \deprecated (US_RHR) Register MASK (Use US_RHR_Msk instead) */ +#define US_RHR_Msk _U_(0x81FF) /**< (US_RHR) Register Mask */ + + +/* -------- US_THR : (USART Offset: 0x1c) (/W 32) Transmit Holding Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXCHR:9; /**< bit: 0..8 Character to be Transmitted */ + uint32_t :6; /**< bit: 9..14 Reserved */ + uint32_t TXSYNH:1; /**< bit: 15 Sync Field to be Transmitted */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_THR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_THR_OFFSET (0x1C) /**< (US_THR) Transmit Holding Register Offset */ + +#define US_THR_TXCHR_Pos 0 /**< (US_THR) Character to be Transmitted Position */ +#define US_THR_TXCHR_Msk (_U_(0x1FF) << US_THR_TXCHR_Pos) /**< (US_THR) Character to be Transmitted Mask */ +#define US_THR_TXCHR(value) (US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)) +#define US_THR_TXSYNH_Pos 15 /**< (US_THR) Sync Field to be Transmitted Position */ +#define US_THR_TXSYNH_Msk (_U_(0x1) << US_THR_TXSYNH_Pos) /**< (US_THR) Sync Field to be Transmitted Mask */ +#define US_THR_TXSYNH US_THR_TXSYNH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_THR_TXSYNH_Msk instead */ +#define US_THR_MASK _U_(0x81FF) /**< \deprecated (US_THR) Register MASK (Use US_THR_Msk instead) */ +#define US_THR_Msk _U_(0x81FF) /**< (US_THR) Register Mask */ + + +/* -------- US_BRGR : (USART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CD:16; /**< bit: 0..15 Clock Divider */ + uint32_t FP:3; /**< bit: 16..18 Fractional Part */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_BRGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_BRGR_OFFSET (0x20) /**< (US_BRGR) Baud Rate Generator Register Offset */ + +#define US_BRGR_CD_Pos 0 /**< (US_BRGR) Clock Divider Position */ +#define US_BRGR_CD_Msk (_U_(0xFFFF) << US_BRGR_CD_Pos) /**< (US_BRGR) Clock Divider Mask */ +#define US_BRGR_CD(value) (US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)) +#define US_BRGR_FP_Pos 16 /**< (US_BRGR) Fractional Part Position */ +#define US_BRGR_FP_Msk (_U_(0x7) << US_BRGR_FP_Pos) /**< (US_BRGR) Fractional Part Mask */ +#define US_BRGR_FP(value) (US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)) +#define US_BRGR_MASK _U_(0x7FFFF) /**< \deprecated (US_BRGR) Register MASK (Use US_BRGR_Msk instead) */ +#define US_BRGR_Msk _U_(0x7FFFF) /**< (US_BRGR) Register Mask */ + + +/* -------- US_RTOR : (USART Offset: 0x24) (R/W 32) Receiver Timeout Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TO:17; /**< bit: 0..16 Timeout Value */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_RTOR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_RTOR_OFFSET (0x24) /**< (US_RTOR) Receiver Timeout Register Offset */ + +#define US_RTOR_TO_Pos 0 /**< (US_RTOR) Timeout Value Position */ +#define US_RTOR_TO_Msk (_U_(0x1FFFF) << US_RTOR_TO_Pos) /**< (US_RTOR) Timeout Value Mask */ +#define US_RTOR_TO(value) (US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)) +#define US_RTOR_MASK _U_(0x1FFFF) /**< \deprecated (US_RTOR) Register MASK (Use US_RTOR_Msk instead) */ +#define US_RTOR_Msk _U_(0x1FFFF) /**< (US_RTOR) Register Mask */ + + +/* -------- US_TTGR : (USART Offset: 0x28) (R/W 32) Transmitter Timeguard Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { // USART mode + uint32_t TG:8; /**< bit: 0..7 Timeguard Value */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // LON mode + uint32_t PCYCLE:24; /**< bit: 0..23 LON PCYCLE Length */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + uint32_t reg; /**< Type used for register access */ +} US_TTGR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_TTGR_OFFSET (0x28) /**< (US_TTGR) Transmitter Timeguard Register Offset */ + +#define US_TTGR_MASK _U_(0x00) /**< \deprecated (US_TTGR) Register MASK (Use US_TTGR_Msk instead) */ +#define US_TTGR_Msk _U_(0x00) /**< (US_TTGR) Register Mask */ + +/* USART mode */ +#define US_TTGR_USART_TG_Pos 0 /**< (US_TTGR) Timeguard Value Position */ +#define US_TTGR_USART_TG_Msk (_U_(0xFF) << US_TTGR_USART_TG_Pos) /**< (US_TTGR) Timeguard Value Mask */ +#define US_TTGR_USART_TG(value) (US_TTGR_USART_TG_Msk & ((value) << US_TTGR_USART_TG_Pos)) +#define US_TTGR_USART_MASK _U_(0xFF) /**< \deprecated (US_TTGR_USART) Register MASK (Use US_TTGR_USART_Msk instead) */ +#define US_TTGR_USART_Msk _U_(0xFF) /**< (US_TTGR_USART) Register Mask */ + +/* LON mode */ +#define US_TTGR_LON_PCYCLE_Pos 0 /**< (US_TTGR) LON PCYCLE Length Position */ +#define US_TTGR_LON_PCYCLE_Msk (_U_(0xFFFFFF) << US_TTGR_LON_PCYCLE_Pos) /**< (US_TTGR) LON PCYCLE Length Mask */ +#define US_TTGR_LON_PCYCLE(value) (US_TTGR_LON_PCYCLE_Msk & ((value) << US_TTGR_LON_PCYCLE_Pos)) +#define US_TTGR_LON_MASK _U_(0xFFFFFF) /**< \deprecated (US_TTGR_LON) Register MASK (Use US_TTGR_LON_Msk instead) */ +#define US_TTGR_LON_Msk _U_(0xFFFFFF) /**< (US_TTGR_LON) Register Mask */ + + +/* -------- US_FIDI : (USART Offset: 0x40) (R/W 32) FI DI Ratio Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { // USART mode + uint32_t FI_DI_RATIO:16; /**< bit: 0..15 FI Over DI Ratio Value */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } USART; /**< Structure used for USART mode access */ + struct { // LON mode + uint32_t BETA2:24; /**< bit: 0..23 LON BETA2 Length */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } LON; /**< Structure used for LON mode access */ + uint32_t reg; /**< Type used for register access */ +} US_FIDI_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_FIDI_OFFSET (0x40) /**< (US_FIDI) FI DI Ratio Register Offset */ + +#define US_FIDI_MASK _U_(0x00) /**< \deprecated (US_FIDI) Register MASK (Use US_FIDI_Msk instead) */ +#define US_FIDI_Msk _U_(0x00) /**< (US_FIDI) Register Mask */ + +/* USART mode */ +#define US_FIDI_USART_FI_DI_RATIO_Pos 0 /**< (US_FIDI) FI Over DI Ratio Value Position */ +#define US_FIDI_USART_FI_DI_RATIO_Msk (_U_(0xFFFF) << US_FIDI_USART_FI_DI_RATIO_Pos) /**< (US_FIDI) FI Over DI Ratio Value Mask */ +#define US_FIDI_USART_FI_DI_RATIO(value) (US_FIDI_USART_FI_DI_RATIO_Msk & ((value) << US_FIDI_USART_FI_DI_RATIO_Pos)) +#define US_FIDI_USART_MASK _U_(0xFFFF) /**< \deprecated (US_FIDI_USART) Register MASK (Use US_FIDI_USART_Msk instead) */ +#define US_FIDI_USART_Msk _U_(0xFFFF) /**< (US_FIDI_USART) Register Mask */ + +/* LON mode */ +#define US_FIDI_LON_BETA2_Pos 0 /**< (US_FIDI) LON BETA2 Length Position */ +#define US_FIDI_LON_BETA2_Msk (_U_(0xFFFFFF) << US_FIDI_LON_BETA2_Pos) /**< (US_FIDI) LON BETA2 Length Mask */ +#define US_FIDI_LON_BETA2(value) (US_FIDI_LON_BETA2_Msk & ((value) << US_FIDI_LON_BETA2_Pos)) +#define US_FIDI_LON_MASK _U_(0xFFFFFF) /**< \deprecated (US_FIDI_LON) Register MASK (Use US_FIDI_LON_Msk instead) */ +#define US_FIDI_LON_Msk _U_(0xFFFFFF) /**< (US_FIDI_LON) Register Mask */ + + +/* -------- US_NER : (USART Offset: 0x44) (R/ 32) Number of Errors Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NB_ERRORS:8; /**< bit: 0..7 Number of Errors */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_NER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_NER_OFFSET (0x44) /**< (US_NER) Number of Errors Register Offset */ + +#define US_NER_NB_ERRORS_Pos 0 /**< (US_NER) Number of Errors Position */ +#define US_NER_NB_ERRORS_Msk (_U_(0xFF) << US_NER_NB_ERRORS_Pos) /**< (US_NER) Number of Errors Mask */ +#define US_NER_NB_ERRORS(value) (US_NER_NB_ERRORS_Msk & ((value) << US_NER_NB_ERRORS_Pos)) +#define US_NER_MASK _U_(0xFF) /**< \deprecated (US_NER) Register MASK (Use US_NER_Msk instead) */ +#define US_NER_Msk _U_(0xFF) /**< (US_NER) Register Mask */ + + +/* -------- US_IF : (USART Offset: 0x4c) (R/W 32) IrDA Filter Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IRDA_FILTER:8; /**< bit: 0..7 IrDA Filter */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_IF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IF_OFFSET (0x4C) /**< (US_IF) IrDA Filter Register Offset */ + +#define US_IF_IRDA_FILTER_Pos 0 /**< (US_IF) IrDA Filter Position */ +#define US_IF_IRDA_FILTER_Msk (_U_(0xFF) << US_IF_IRDA_FILTER_Pos) /**< (US_IF) IrDA Filter Mask */ +#define US_IF_IRDA_FILTER(value) (US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)) +#define US_IF_MASK _U_(0xFF) /**< \deprecated (US_IF) Register MASK (Use US_IF_Msk instead) */ +#define US_IF_Msk _U_(0xFF) /**< (US_IF) Register Mask */ + + +/* -------- US_MAN : (USART Offset: 0x50) (R/W 32) Manchester Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TX_PL:4; /**< bit: 0..3 Transmitter Preamble Length */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t TX_PP:2; /**< bit: 8..9 Transmitter Preamble Pattern */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t TX_MPOL:1; /**< bit: 12 Transmitter Manchester Polarity */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t RX_PL:4; /**< bit: 16..19 Receiver Preamble Length */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t RX_PP:2; /**< bit: 24..25 Receiver Preamble Pattern detected */ + uint32_t :2; /**< bit: 26..27 Reserved */ + uint32_t RX_MPOL:1; /**< bit: 28 Receiver Manchester Polarity */ + uint32_t ONE:1; /**< bit: 29 Must Be Set to 1 */ + uint32_t DRIFT:1; /**< bit: 30 Drift Compensation */ + uint32_t RXIDLEV:1; /**< bit: 31 Receiver Idle Value */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_MAN_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_MAN_OFFSET (0x50) /**< (US_MAN) Manchester Configuration Register Offset */ + +#define US_MAN_TX_PL_Pos 0 /**< (US_MAN) Transmitter Preamble Length Position */ +#define US_MAN_TX_PL_Msk (_U_(0xF) << US_MAN_TX_PL_Pos) /**< (US_MAN) Transmitter Preamble Length Mask */ +#define US_MAN_TX_PL(value) (US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)) +#define US_MAN_TX_PP_Pos 8 /**< (US_MAN) Transmitter Preamble Pattern Position */ +#define US_MAN_TX_PP_Msk (_U_(0x3) << US_MAN_TX_PP_Pos) /**< (US_MAN) Transmitter Preamble Pattern Mask */ +#define US_MAN_TX_PP(value) (US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)) +#define US_MAN_TX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_PP_ALL_ONE (US_MAN_TX_PP_ALL_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_TX_PP_ALL_ZERO (US_MAN_TX_PP_ALL_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_TX_PP_ZERO_ONE (US_MAN_TX_PP_ZERO_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_TX_PP_ONE_ZERO (US_MAN_TX_PP_ONE_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_TX_MPOL_Pos 12 /**< (US_MAN) Transmitter Manchester Polarity Position */ +#define US_MAN_TX_MPOL_Msk (_U_(0x1) << US_MAN_TX_MPOL_Pos) /**< (US_MAN) Transmitter Manchester Polarity Mask */ +#define US_MAN_TX_MPOL US_MAN_TX_MPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MAN_TX_MPOL_Msk instead */ +#define US_MAN_RX_PL_Pos 16 /**< (US_MAN) Receiver Preamble Length Position */ +#define US_MAN_RX_PL_Msk (_U_(0xF) << US_MAN_RX_PL_Pos) /**< (US_MAN) Receiver Preamble Length Mask */ +#define US_MAN_RX_PL(value) (US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)) +#define US_MAN_RX_PP_Pos 24 /**< (US_MAN) Receiver Preamble Pattern detected Position */ +#define US_MAN_RX_PP_Msk (_U_(0x3) << US_MAN_RX_PP_Pos) /**< (US_MAN) Receiver Preamble Pattern detected Mask */ +#define US_MAN_RX_PP(value) (US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)) +#define US_MAN_RX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_PP_ALL_ONE (US_MAN_RX_PP_ALL_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_RX_PP_ALL_ZERO (US_MAN_RX_PP_ALL_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_RX_PP_ZERO_ONE (US_MAN_RX_PP_ZERO_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_RX_PP_ONE_ZERO (US_MAN_RX_PP_ONE_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_RX_MPOL_Pos 28 /**< (US_MAN) Receiver Manchester Polarity Position */ +#define US_MAN_RX_MPOL_Msk (_U_(0x1) << US_MAN_RX_MPOL_Pos) /**< (US_MAN) Receiver Manchester Polarity Mask */ +#define US_MAN_RX_MPOL US_MAN_RX_MPOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MAN_RX_MPOL_Msk instead */ +#define US_MAN_ONE_Pos 29 /**< (US_MAN) Must Be Set to 1 Position */ +#define US_MAN_ONE_Msk (_U_(0x1) << US_MAN_ONE_Pos) /**< (US_MAN) Must Be Set to 1 Mask */ +#define US_MAN_ONE US_MAN_ONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MAN_ONE_Msk instead */ +#define US_MAN_DRIFT_Pos 30 /**< (US_MAN) Drift Compensation Position */ +#define US_MAN_DRIFT_Msk (_U_(0x1) << US_MAN_DRIFT_Pos) /**< (US_MAN) Drift Compensation Mask */ +#define US_MAN_DRIFT US_MAN_DRIFT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MAN_DRIFT_Msk instead */ +#define US_MAN_RXIDLEV_Pos 31 /**< (US_MAN) Receiver Idle Value Position */ +#define US_MAN_RXIDLEV_Msk (_U_(0x1) << US_MAN_RXIDLEV_Pos) /**< (US_MAN) Receiver Idle Value Mask */ +#define US_MAN_RXIDLEV US_MAN_RXIDLEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_MAN_RXIDLEV_Msk instead */ +#define US_MAN_MASK _U_(0xF30F130F) /**< \deprecated (US_MAN) Register MASK (Use US_MAN_Msk instead) */ +#define US_MAN_Msk _U_(0xF30F130F) /**< (US_MAN) Register Mask */ + + +/* -------- US_LINMR : (USART Offset: 0x54) (R/W 32) LIN Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NACT:2; /**< bit: 0..1 LIN Node Action */ + uint32_t PARDIS:1; /**< bit: 2 Parity Disable */ + uint32_t CHKDIS:1; /**< bit: 3 Checksum Disable */ + uint32_t CHKTYP:1; /**< bit: 4 Checksum Type */ + uint32_t DLM:1; /**< bit: 5 Data Length Mode */ + uint32_t FSDIS:1; /**< bit: 6 Frame Slot Mode Disable */ + uint32_t WKUPTYP:1; /**< bit: 7 Wakeup Signal Type */ + uint32_t DLC:8; /**< bit: 8..15 Data Length Control */ + uint32_t PDCM:1; /**< bit: 16 DMAC Mode */ + uint32_t SYNCDIS:1; /**< bit: 17 Synchronization Disable */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LINMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LINMR_OFFSET (0x54) /**< (US_LINMR) LIN Mode Register Offset */ + +#define US_LINMR_NACT_Pos 0 /**< (US_LINMR) LIN Node Action Position */ +#define US_LINMR_NACT_Msk (_U_(0x3) << US_LINMR_NACT_Pos) /**< (US_LINMR) LIN Node Action Mask */ +#define US_LINMR_NACT(value) (US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)) +#define US_LINMR_NACT_PUBLISH_Val _U_(0x0) /**< (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE_Val _U_(0x1) /**< (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE_Val _U_(0x2) /**< (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_NACT_PUBLISH (US_LINMR_NACT_PUBLISH_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART transmits the response. Position */ +#define US_LINMR_NACT_SUBSCRIBE (US_LINMR_NACT_SUBSCRIBE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART receives the response. Position */ +#define US_LINMR_NACT_IGNORE (US_LINMR_NACT_IGNORE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART does not transmit and does not receive the response. Position */ +#define US_LINMR_PARDIS_Pos 2 /**< (US_LINMR) Parity Disable Position */ +#define US_LINMR_PARDIS_Msk (_U_(0x1) << US_LINMR_PARDIS_Pos) /**< (US_LINMR) Parity Disable Mask */ +#define US_LINMR_PARDIS US_LINMR_PARDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_PARDIS_Msk instead */ +#define US_LINMR_CHKDIS_Pos 3 /**< (US_LINMR) Checksum Disable Position */ +#define US_LINMR_CHKDIS_Msk (_U_(0x1) << US_LINMR_CHKDIS_Pos) /**< (US_LINMR) Checksum Disable Mask */ +#define US_LINMR_CHKDIS US_LINMR_CHKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_CHKDIS_Msk instead */ +#define US_LINMR_CHKTYP_Pos 4 /**< (US_LINMR) Checksum Type Position */ +#define US_LINMR_CHKTYP_Msk (_U_(0x1) << US_LINMR_CHKTYP_Pos) /**< (US_LINMR) Checksum Type Mask */ +#define US_LINMR_CHKTYP US_LINMR_CHKTYP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_CHKTYP_Msk instead */ +#define US_LINMR_DLM_Pos 5 /**< (US_LINMR) Data Length Mode Position */ +#define US_LINMR_DLM_Msk (_U_(0x1) << US_LINMR_DLM_Pos) /**< (US_LINMR) Data Length Mode Mask */ +#define US_LINMR_DLM US_LINMR_DLM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_DLM_Msk instead */ +#define US_LINMR_FSDIS_Pos 6 /**< (US_LINMR) Frame Slot Mode Disable Position */ +#define US_LINMR_FSDIS_Msk (_U_(0x1) << US_LINMR_FSDIS_Pos) /**< (US_LINMR) Frame Slot Mode Disable Mask */ +#define US_LINMR_FSDIS US_LINMR_FSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_FSDIS_Msk instead */ +#define US_LINMR_WKUPTYP_Pos 7 /**< (US_LINMR) Wakeup Signal Type Position */ +#define US_LINMR_WKUPTYP_Msk (_U_(0x1) << US_LINMR_WKUPTYP_Pos) /**< (US_LINMR) Wakeup Signal Type Mask */ +#define US_LINMR_WKUPTYP US_LINMR_WKUPTYP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_WKUPTYP_Msk instead */ +#define US_LINMR_DLC_Pos 8 /**< (US_LINMR) Data Length Control Position */ +#define US_LINMR_DLC_Msk (_U_(0xFF) << US_LINMR_DLC_Pos) /**< (US_LINMR) Data Length Control Mask */ +#define US_LINMR_DLC(value) (US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)) +#define US_LINMR_PDCM_Pos 16 /**< (US_LINMR) DMAC Mode Position */ +#define US_LINMR_PDCM_Msk (_U_(0x1) << US_LINMR_PDCM_Pos) /**< (US_LINMR) DMAC Mode Mask */ +#define US_LINMR_PDCM US_LINMR_PDCM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_PDCM_Msk instead */ +#define US_LINMR_SYNCDIS_Pos 17 /**< (US_LINMR) Synchronization Disable Position */ +#define US_LINMR_SYNCDIS_Msk (_U_(0x1) << US_LINMR_SYNCDIS_Pos) /**< (US_LINMR) Synchronization Disable Mask */ +#define US_LINMR_SYNCDIS US_LINMR_SYNCDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LINMR_SYNCDIS_Msk instead */ +#define US_LINMR_MASK _U_(0x3FFFF) /**< \deprecated (US_LINMR) Register MASK (Use US_LINMR_Msk instead) */ +#define US_LINMR_Msk _U_(0x3FFFF) /**< (US_LINMR) Register Mask */ + + +/* -------- US_LINIR : (USART Offset: 0x58) (R/W 32) LIN Identifier Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDCHR:8; /**< bit: 0..7 Identifier Character */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LINIR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LINIR_OFFSET (0x58) /**< (US_LINIR) LIN Identifier Register Offset */ + +#define US_LINIR_IDCHR_Pos 0 /**< (US_LINIR) Identifier Character Position */ +#define US_LINIR_IDCHR_Msk (_U_(0xFF) << US_LINIR_IDCHR_Pos) /**< (US_LINIR) Identifier Character Mask */ +#define US_LINIR_IDCHR(value) (US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)) +#define US_LINIR_MASK _U_(0xFF) /**< \deprecated (US_LINIR) Register MASK (Use US_LINIR_Msk instead) */ +#define US_LINIR_Msk _U_(0xFF) /**< (US_LINIR) Register Mask */ + + +/* -------- US_LINBRR : (USART Offset: 0x5c) (R/ 32) LIN Baud Rate Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LINCD:16; /**< bit: 0..15 Clock Divider after Synchronization */ + uint32_t LINFP:3; /**< bit: 16..18 Fractional Part after Synchronization */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LINBRR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LINBRR_OFFSET (0x5C) /**< (US_LINBRR) LIN Baud Rate Register Offset */ + +#define US_LINBRR_LINCD_Pos 0 /**< (US_LINBRR) Clock Divider after Synchronization Position */ +#define US_LINBRR_LINCD_Msk (_U_(0xFFFF) << US_LINBRR_LINCD_Pos) /**< (US_LINBRR) Clock Divider after Synchronization Mask */ +#define US_LINBRR_LINCD(value) (US_LINBRR_LINCD_Msk & ((value) << US_LINBRR_LINCD_Pos)) +#define US_LINBRR_LINFP_Pos 16 /**< (US_LINBRR) Fractional Part after Synchronization Position */ +#define US_LINBRR_LINFP_Msk (_U_(0x7) << US_LINBRR_LINFP_Pos) /**< (US_LINBRR) Fractional Part after Synchronization Mask */ +#define US_LINBRR_LINFP(value) (US_LINBRR_LINFP_Msk & ((value) << US_LINBRR_LINFP_Pos)) +#define US_LINBRR_MASK _U_(0x7FFFF) /**< \deprecated (US_LINBRR) Register MASK (Use US_LINBRR_Msk instead) */ +#define US_LINBRR_Msk _U_(0x7FFFF) /**< (US_LINBRR) Register Mask */ + + +/* -------- US_LONMR : (USART Offset: 0x60) (R/W 32) LON Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t COMMT:1; /**< bit: 0 LON comm_type Parameter Value */ + uint32_t COLDET:1; /**< bit: 1 LON Collision Detection Feature */ + uint32_t TCOL:1; /**< bit: 2 Terminate Frame upon Collision Notification */ + uint32_t CDTAIL:1; /**< bit: 3 LON Collision Detection on Frame Tail */ + uint32_t DMAM:1; /**< bit: 4 LON DMA Mode */ + uint32_t LCDS:1; /**< bit: 5 LON Collision Detection Source */ + uint32_t :10; /**< bit: 6..15 Reserved */ + uint32_t EOFS:8; /**< bit: 16..23 End of Frame Condition Size */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONMR_OFFSET (0x60) /**< (US_LONMR) LON Mode Register Offset */ + +#define US_LONMR_COMMT_Pos 0 /**< (US_LONMR) LON comm_type Parameter Value Position */ +#define US_LONMR_COMMT_Msk (_U_(0x1) << US_LONMR_COMMT_Pos) /**< (US_LONMR) LON comm_type Parameter Value Mask */ +#define US_LONMR_COMMT US_LONMR_COMMT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_COMMT_Msk instead */ +#define US_LONMR_COLDET_Pos 1 /**< (US_LONMR) LON Collision Detection Feature Position */ +#define US_LONMR_COLDET_Msk (_U_(0x1) << US_LONMR_COLDET_Pos) /**< (US_LONMR) LON Collision Detection Feature Mask */ +#define US_LONMR_COLDET US_LONMR_COLDET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_COLDET_Msk instead */ +#define US_LONMR_TCOL_Pos 2 /**< (US_LONMR) Terminate Frame upon Collision Notification Position */ +#define US_LONMR_TCOL_Msk (_U_(0x1) << US_LONMR_TCOL_Pos) /**< (US_LONMR) Terminate Frame upon Collision Notification Mask */ +#define US_LONMR_TCOL US_LONMR_TCOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_TCOL_Msk instead */ +#define US_LONMR_CDTAIL_Pos 3 /**< (US_LONMR) LON Collision Detection on Frame Tail Position */ +#define US_LONMR_CDTAIL_Msk (_U_(0x1) << US_LONMR_CDTAIL_Pos) /**< (US_LONMR) LON Collision Detection on Frame Tail Mask */ +#define US_LONMR_CDTAIL US_LONMR_CDTAIL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_CDTAIL_Msk instead */ +#define US_LONMR_DMAM_Pos 4 /**< (US_LONMR) LON DMA Mode Position */ +#define US_LONMR_DMAM_Msk (_U_(0x1) << US_LONMR_DMAM_Pos) /**< (US_LONMR) LON DMA Mode Mask */ +#define US_LONMR_DMAM US_LONMR_DMAM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_DMAM_Msk instead */ +#define US_LONMR_LCDS_Pos 5 /**< (US_LONMR) LON Collision Detection Source Position */ +#define US_LONMR_LCDS_Msk (_U_(0x1) << US_LONMR_LCDS_Pos) /**< (US_LONMR) LON Collision Detection Source Mask */ +#define US_LONMR_LCDS US_LONMR_LCDS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONMR_LCDS_Msk instead */ +#define US_LONMR_EOFS_Pos 16 /**< (US_LONMR) End of Frame Condition Size Position */ +#define US_LONMR_EOFS_Msk (_U_(0xFF) << US_LONMR_EOFS_Pos) /**< (US_LONMR) End of Frame Condition Size Mask */ +#define US_LONMR_EOFS(value) (US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)) +#define US_LONMR_MASK _U_(0xFF003F) /**< \deprecated (US_LONMR) Register MASK (Use US_LONMR_Msk instead) */ +#define US_LONMR_Msk _U_(0xFF003F) /**< (US_LONMR) Register Mask */ + + +/* -------- US_LONPR : (USART Offset: 0x64) (R/W 32) LON Preamble Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LONPL:14; /**< bit: 0..13 LON Preamble Length */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONPR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONPR_OFFSET (0x64) /**< (US_LONPR) LON Preamble Register Offset */ + +#define US_LONPR_LONPL_Pos 0 /**< (US_LONPR) LON Preamble Length Position */ +#define US_LONPR_LONPL_Msk (_U_(0x3FFF) << US_LONPR_LONPL_Pos) /**< (US_LONPR) LON Preamble Length Mask */ +#define US_LONPR_LONPL(value) (US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)) +#define US_LONPR_MASK _U_(0x3FFF) /**< \deprecated (US_LONPR) Register MASK (Use US_LONPR_Msk instead) */ +#define US_LONPR_Msk _U_(0x3FFF) /**< (US_LONPR) Register Mask */ + + +/* -------- US_LONDL : (USART Offset: 0x68) (R/W 32) LON Data Length Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LONDL:8; /**< bit: 0..7 LON Data Length */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONDL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONDL_OFFSET (0x68) /**< (US_LONDL) LON Data Length Register Offset */ + +#define US_LONDL_LONDL_Pos 0 /**< (US_LONDL) LON Data Length Position */ +#define US_LONDL_LONDL_Msk (_U_(0xFF) << US_LONDL_LONDL_Pos) /**< (US_LONDL) LON Data Length Mask */ +#define US_LONDL_LONDL(value) (US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)) +#define US_LONDL_MASK _U_(0xFF) /**< \deprecated (US_LONDL) Register MASK (Use US_LONDL_Msk instead) */ +#define US_LONDL_Msk _U_(0xFF) /**< (US_LONDL) Register Mask */ + + +/* -------- US_LONL2HDR : (USART Offset: 0x6c) (R/W 32) LON L2HDR Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BLI:6; /**< bit: 0..5 LON Backlog Increment */ + uint32_t ALTP:1; /**< bit: 6 LON Alternate Path Bit */ + uint32_t PB:1; /**< bit: 7 LON Priority Bit */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONL2HDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONL2HDR_OFFSET (0x6C) /**< (US_LONL2HDR) LON L2HDR Register Offset */ + +#define US_LONL2HDR_BLI_Pos 0 /**< (US_LONL2HDR) LON Backlog Increment Position */ +#define US_LONL2HDR_BLI_Msk (_U_(0x3F) << US_LONL2HDR_BLI_Pos) /**< (US_LONL2HDR) LON Backlog Increment Mask */ +#define US_LONL2HDR_BLI(value) (US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)) +#define US_LONL2HDR_ALTP_Pos 6 /**< (US_LONL2HDR) LON Alternate Path Bit Position */ +#define US_LONL2HDR_ALTP_Msk (_U_(0x1) << US_LONL2HDR_ALTP_Pos) /**< (US_LONL2HDR) LON Alternate Path Bit Mask */ +#define US_LONL2HDR_ALTP US_LONL2HDR_ALTP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONL2HDR_ALTP_Msk instead */ +#define US_LONL2HDR_PB_Pos 7 /**< (US_LONL2HDR) LON Priority Bit Position */ +#define US_LONL2HDR_PB_Msk (_U_(0x1) << US_LONL2HDR_PB_Pos) /**< (US_LONL2HDR) LON Priority Bit Mask */ +#define US_LONL2HDR_PB US_LONL2HDR_PB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_LONL2HDR_PB_Msk instead */ +#define US_LONL2HDR_MASK _U_(0xFF) /**< \deprecated (US_LONL2HDR) Register MASK (Use US_LONL2HDR_Msk instead) */ +#define US_LONL2HDR_Msk _U_(0xFF) /**< (US_LONL2HDR) Register Mask */ + + +/* -------- US_LONBL : (USART Offset: 0x70) (R/ 32) LON Backlog Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t LONBL:6; /**< bit: 0..5 LON Node Backlog Value */ + uint32_t :26; /**< bit: 6..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONBL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONBL_OFFSET (0x70) /**< (US_LONBL) LON Backlog Register Offset */ + +#define US_LONBL_LONBL_Pos 0 /**< (US_LONBL) LON Node Backlog Value Position */ +#define US_LONBL_LONBL_Msk (_U_(0x3F) << US_LONBL_LONBL_Pos) /**< (US_LONBL) LON Node Backlog Value Mask */ +#define US_LONBL_LONBL(value) (US_LONBL_LONBL_Msk & ((value) << US_LONBL_LONBL_Pos)) +#define US_LONBL_MASK _U_(0x3F) /**< \deprecated (US_LONBL) Register MASK (Use US_LONBL_Msk instead) */ +#define US_LONBL_Msk _U_(0x3F) /**< (US_LONBL) Register Mask */ + + +/* -------- US_LONB1TX : (USART Offset: 0x74) (R/W 32) LON Beta1 Tx Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BETA1TX:24; /**< bit: 0..23 LON Beta1 Length after Transmission */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONB1TX_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONB1TX_OFFSET (0x74) /**< (US_LONB1TX) LON Beta1 Tx Register Offset */ + +#define US_LONB1TX_BETA1TX_Pos 0 /**< (US_LONB1TX) LON Beta1 Length after Transmission Position */ +#define US_LONB1TX_BETA1TX_Msk (_U_(0xFFFFFF) << US_LONB1TX_BETA1TX_Pos) /**< (US_LONB1TX) LON Beta1 Length after Transmission Mask */ +#define US_LONB1TX_BETA1TX(value) (US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)) +#define US_LONB1TX_MASK _U_(0xFFFFFF) /**< \deprecated (US_LONB1TX) Register MASK (Use US_LONB1TX_Msk instead) */ +#define US_LONB1TX_Msk _U_(0xFFFFFF) /**< (US_LONB1TX) Register Mask */ + + +/* -------- US_LONB1RX : (USART Offset: 0x78) (R/W 32) LON Beta1 Rx Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BETA1RX:24; /**< bit: 0..23 LON Beta1 Length after Reception */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONB1RX_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONB1RX_OFFSET (0x78) /**< (US_LONB1RX) LON Beta1 Rx Register Offset */ + +#define US_LONB1RX_BETA1RX_Pos 0 /**< (US_LONB1RX) LON Beta1 Length after Reception Position */ +#define US_LONB1RX_BETA1RX_Msk (_U_(0xFFFFFF) << US_LONB1RX_BETA1RX_Pos) /**< (US_LONB1RX) LON Beta1 Length after Reception Mask */ +#define US_LONB1RX_BETA1RX(value) (US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)) +#define US_LONB1RX_MASK _U_(0xFFFFFF) /**< \deprecated (US_LONB1RX) Register MASK (Use US_LONB1RX_Msk instead) */ +#define US_LONB1RX_Msk _U_(0xFFFFFF) /**< (US_LONB1RX) Register Mask */ + + +/* -------- US_LONPRIO : (USART Offset: 0x7c) (R/W 32) LON Priority Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PSNB:7; /**< bit: 0..6 LON Priority Slot Number */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t NPS:7; /**< bit: 8..14 LON Node Priority Slot */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_LONPRIO_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_LONPRIO_OFFSET (0x7C) /**< (US_LONPRIO) LON Priority Register Offset */ + +#define US_LONPRIO_PSNB_Pos 0 /**< (US_LONPRIO) LON Priority Slot Number Position */ +#define US_LONPRIO_PSNB_Msk (_U_(0x7F) << US_LONPRIO_PSNB_Pos) /**< (US_LONPRIO) LON Priority Slot Number Mask */ +#define US_LONPRIO_PSNB(value) (US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)) +#define US_LONPRIO_NPS_Pos 8 /**< (US_LONPRIO) LON Node Priority Slot Position */ +#define US_LONPRIO_NPS_Msk (_U_(0x7F) << US_LONPRIO_NPS_Pos) /**< (US_LONPRIO) LON Node Priority Slot Mask */ +#define US_LONPRIO_NPS(value) (US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)) +#define US_LONPRIO_MASK _U_(0x7F7F) /**< \deprecated (US_LONPRIO) Register MASK (Use US_LONPRIO_Msk instead) */ +#define US_LONPRIO_Msk _U_(0x7F7F) /**< (US_LONPRIO) Register Mask */ + + +/* -------- US_IDTTX : (USART Offset: 0x80) (R/W 32) LON IDT Tx Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDTTX:24; /**< bit: 0..23 LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_IDTTX_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IDTTX_OFFSET (0x80) /**< (US_IDTTX) LON IDT Tx Register Offset */ + +#define US_IDTTX_IDTTX_Pos 0 /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Position */ +#define US_IDTTX_IDTTX_Msk (_U_(0xFFFFFF) << US_IDTTX_IDTTX_Pos) /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Mask */ +#define US_IDTTX_IDTTX(value) (US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)) +#define US_IDTTX_MASK _U_(0xFFFFFF) /**< \deprecated (US_IDTTX) Register MASK (Use US_IDTTX_Msk instead) */ +#define US_IDTTX_Msk _U_(0xFFFFFF) /**< (US_IDTTX) Register Mask */ + + +/* -------- US_IDTRX : (USART Offset: 0x84) (R/W 32) LON IDT Rx Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IDTRX:24; /**< bit: 0..23 LON Indeterminate Time after Reception (comm_type = 1 mode only) */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_IDTRX_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_IDTRX_OFFSET (0x84) /**< (US_IDTRX) LON IDT Rx Register Offset */ + +#define US_IDTRX_IDTRX_Pos 0 /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Position */ +#define US_IDTRX_IDTRX_Msk (_U_(0xFFFFFF) << US_IDTRX_IDTRX_Pos) /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Mask */ +#define US_IDTRX_IDTRX(value) (US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)) +#define US_IDTRX_MASK _U_(0xFFFFFF) /**< \deprecated (US_IDTRX) Register MASK (Use US_IDTRX_Msk instead) */ +#define US_IDTRX_Msk _U_(0xFFFFFF) /**< (US_IDTRX) Register Mask */ + + +/* -------- US_ICDIFF : (USART Offset: 0x88) (R/W 32) IC DIFF Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ICDIFF:4; /**< bit: 0..3 IC Differentiator Number */ + uint32_t :28; /**< bit: 4..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_ICDIFF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_ICDIFF_OFFSET (0x88) /**< (US_ICDIFF) IC DIFF Register Offset */ + +#define US_ICDIFF_ICDIFF_Pos 0 /**< (US_ICDIFF) IC Differentiator Number Position */ +#define US_ICDIFF_ICDIFF_Msk (_U_(0xF) << US_ICDIFF_ICDIFF_Pos) /**< (US_ICDIFF) IC Differentiator Number Mask */ +#define US_ICDIFF_ICDIFF(value) (US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)) +#define US_ICDIFF_MASK _U_(0x0F) /**< \deprecated (US_ICDIFF) Register MASK (Use US_ICDIFF_Msk instead) */ +#define US_ICDIFF_Msk _U_(0x0F) /**< (US_ICDIFF) Register Mask */ + + +/* -------- US_WPMR : (USART Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_WPMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_WPMR_OFFSET (0xE4) /**< (US_WPMR) Write Protection Mode Register Offset */ + +#define US_WPMR_WPEN_Pos 0 /**< (US_WPMR) Write Protection Enable Position */ +#define US_WPMR_WPEN_Msk (_U_(0x1) << US_WPMR_WPEN_Pos) /**< (US_WPMR) Write Protection Enable Mask */ +#define US_WPMR_WPEN US_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_WPMR_WPEN_Msk instead */ +#define US_WPMR_WPKEY_Pos 8 /**< (US_WPMR) Write Protection Key Position */ +#define US_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Write Protection Key Mask */ +#define US_WPMR_WPKEY(value) (US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)) +#define US_WPMR_WPKEY_PASSWD_Val _U_(0x555341) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define US_WPMR_WPKEY_PASSWD (US_WPMR_WPKEY_PASSWD_Val << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define US_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (US_WPMR) Register MASK (Use US_WPMR_Msk instead) */ +#define US_WPMR_Msk _U_(0xFFFFFF01) /**< (US_WPMR) Register Mask */ + + +/* -------- US_WPSR : (USART Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ + uint32_t :7; /**< bit: 1..7 Reserved */ + uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} US_WPSR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define US_WPSR_OFFSET (0xE8) /**< (US_WPSR) Write Protection Status Register Offset */ + +#define US_WPSR_WPVS_Pos 0 /**< (US_WPSR) Write Protection Violation Status Position */ +#define US_WPSR_WPVS_Msk (_U_(0x1) << US_WPSR_WPVS_Pos) /**< (US_WPSR) Write Protection Violation Status Mask */ +#define US_WPSR_WPVS US_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use US_WPSR_WPVS_Msk instead */ +#define US_WPSR_WPVSRC_Pos 8 /**< (US_WPSR) Write Protection Violation Source Position */ +#define US_WPSR_WPVSRC_Msk (_U_(0xFFFF) << US_WPSR_WPVSRC_Pos) /**< (US_WPSR) Write Protection Violation Source Mask */ +#define US_WPSR_WPVSRC(value) (US_WPSR_WPVSRC_Msk & ((value) << US_WPSR_WPVSRC_Pos)) +#define US_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (US_WPSR) Register MASK (Use US_WPSR_Msk instead) */ +#define US_WPSR_Msk _U_(0xFFFF01) /**< (US_WPSR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief USART hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< (USART Offset: 0x00) Control Register */ + __IO uint32_t US_MR; /**< (USART Offset: 0x04) Mode Register */ + __O uint32_t US_IER; /**< (USART Offset: 0x08) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< (USART Offset: 0x0C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< (USART Offset: 0x10) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< (USART Offset: 0x14) Channel Status Register */ + __I uint32_t US_RHR; /**< (USART Offset: 0x18) Receive Holding Register */ + __O uint32_t US_THR; /**< (USART Offset: 0x1C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< (USART Offset: 0x20) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< (USART Offset: 0x24) Receiver Timeout Register */ + __IO uint32_t US_TTGR; /**< (USART Offset: 0x28) Transmitter Timeguard Register */ + __I uint8_t Reserved1[20]; + __IO uint32_t US_FIDI; /**< (USART Offset: 0x40) FI DI Ratio Register */ + __I uint32_t US_NER; /**< (USART Offset: 0x44) Number of Errors Register */ + __I uint8_t Reserved2[4]; + __IO uint32_t US_IF; /**< (USART Offset: 0x4C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< (USART Offset: 0x50) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< (USART Offset: 0x54) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< (USART Offset: 0x58) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< (USART Offset: 0x5C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< (USART Offset: 0x60) LON Mode Register */ + __IO uint32_t US_LONPR; /**< (USART Offset: 0x64) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< (USART Offset: 0x68) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< (USART Offset: 0x6C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< (USART Offset: 0x70) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< (USART Offset: 0x74) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< (USART Offset: 0x78) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< (USART Offset: 0x7C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< (USART Offset: 0x80) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< (USART Offset: 0x84) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< (USART Offset: 0x88) IC DIFF Register */ + __I uint8_t Reserved3[88]; + __IO uint32_t US_WPMR; /**< (USART Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< (USART Offset: 0xE8) Write Protection Status Register */ +} Usart; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief USART hardware registers */ +typedef struct { + __O US_CR_Type US_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO US_MR_Type US_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O US_IER_Type US_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O US_IDR_Type US_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I US_IMR_Type US_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I US_CSR_Type US_CSR; /**< Offset: 0x14 (R/ 32) Channel Status Register */ + __I US_RHR_Type US_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O US_THR_Type US_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO US_BRGR_Type US_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO US_RTOR_Type US_RTOR; /**< Offset: 0x24 (R/W 32) Receiver Timeout Register */ + __IO US_TTGR_Type US_TTGR; /**< Offset: 0x28 (R/W 32) Transmitter Timeguard Register */ + __I uint8_t Reserved1[20]; + __IO US_FIDI_Type US_FIDI; /**< Offset: 0x40 (R/W 32) FI DI Ratio Register */ + __I US_NER_Type US_NER; /**< Offset: 0x44 (R/ 32) Number of Errors Register */ + __I uint8_t Reserved2[4]; + __IO US_IF_Type US_IF; /**< Offset: 0x4C (R/W 32) IrDA Filter Register */ + __IO US_MAN_Type US_MAN; /**< Offset: 0x50 (R/W 32) Manchester Configuration Register */ + __IO US_LINMR_Type US_LINMR; /**< Offset: 0x54 (R/W 32) LIN Mode Register */ + __IO US_LINIR_Type US_LINIR; /**< Offset: 0x58 (R/W 32) LIN Identifier Register */ + __I US_LINBRR_Type US_LINBRR; /**< Offset: 0x5C (R/ 32) LIN Baud Rate Register */ + __IO US_LONMR_Type US_LONMR; /**< Offset: 0x60 (R/W 32) LON Mode Register */ + __IO US_LONPR_Type US_LONPR; /**< Offset: 0x64 (R/W 32) LON Preamble Register */ + __IO US_LONDL_Type US_LONDL; /**< Offset: 0x68 (R/W 32) LON Data Length Register */ + __IO US_LONL2HDR_Type US_LONL2HDR; /**< Offset: 0x6C (R/W 32) LON L2HDR Register */ + __I US_LONBL_Type US_LONBL; /**< Offset: 0x70 (R/ 32) LON Backlog Register */ + __IO US_LONB1TX_Type US_LONB1TX; /**< Offset: 0x74 (R/W 32) LON Beta1 Tx Register */ + __IO US_LONB1RX_Type US_LONB1RX; /**< Offset: 0x78 (R/W 32) LON Beta1 Rx Register */ + __IO US_LONPRIO_Type US_LONPRIO; /**< Offset: 0x7C (R/W 32) LON Priority Register */ + __IO US_IDTTX_Type US_IDTTX; /**< Offset: 0x80 (R/W 32) LON IDT Tx Register */ + __IO US_IDTRX_Type US_IDTRX; /**< Offset: 0x84 (R/W 32) LON IDT Rx Register */ + __IO US_ICDIFF_Type US_ICDIFF; /**< Offset: 0x88 (R/W 32) IC DIFF Register */ + __I uint8_t Reserved3[88]; + __IO US_WPMR_Type US_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I US_WPSR_Type US_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} Usart; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Universal Synchronous Asynchronous Receiver Transmitter */ + +#if !(defined(DO_NOT_USE_DEPRECATED_MACROS)) +#include "deprecated/usart.h" +#endif /* DO_NOT_USE_DEPRECATED_MACROS */ +#endif /* _SAME70_USART_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/usbhs.h b/bsp/microchip/same70/bsp/same70b/include/component/usbhs.h new file mode 100644 index 0000000000..561c015989 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/usbhs.h @@ -0,0 +1,4537 @@ +/** + * \file + * + * \brief Component description for USBHS + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USBHS_COMPONENT_H_ +#define _SAME70_USBHS_COMPONENT_H_ +#define _SAME70_USBHS_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 USB High-Speed Interface + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR USBHS */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define USBHS_11292 /**< (USBHS) Module ID */ +#define REV_USBHS G /**< (USBHS) Module revision */ + +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NXT_DSC_ADD:32; /**< bit: 0..31 Next Descriptor Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVDMANXTDSC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVDMANXTDSC_OFFSET (0x00) /**< (USBHS_DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ + +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) (USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_DEVDMANXTDSC_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_DEVDMANXTDSC) Register MASK (Use USBHS_DEVDMANXTDSC_Msk instead) */ +#define USBHS_DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMANXTDSC) Register Mask */ + + +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BUFF_ADD:32; /**< bit: 0..31 Buffer Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVDMAADDRESS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVDMAADDRESS_OFFSET (0x04) /**< (USBHS_DEVDMAADDRESS) Device DMA Channel Address Register Offset */ + +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 /**< (USBHS_DEVDMAADDRESS) Buffer Address Position */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_DEVDMAADDRESS) Buffer Address Mask */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) (USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_DEVDMAADDRESS_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_DEVDMAADDRESS) Register MASK (Use USBHS_DEVDMAADDRESS_Msk instead) */ +#define USBHS_DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMAADDRESS) Register Mask */ + + +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Command */ + uint32_t LDNXT_DSC:1; /**< bit: 1 Load Next Channel Transfer Descriptor Enable Command */ + uint32_t END_TR_EN:1; /**< bit: 2 End of Transfer Enable Control (OUT transfers only) */ + uint32_t END_B_EN:1; /**< bit: 3 End of Buffer Enable Control */ + uint32_t END_TR_IT:1; /**< bit: 4 End of Transfer Interrupt Enable */ + uint32_t END_BUFFIT:1; /**< bit: 5 End of Buffer Interrupt Enable */ + uint32_t DESC_LD_IT:1; /**< bit: 6 Descriptor Loaded Interrupt Enable */ + uint32_t BURST_LCK:1; /**< bit: 7 Burst Lock Enable */ + uint32_t :8; /**< bit: 8..15 Reserved */ + uint32_t BUFF_LENGTH:16; /**< bit: 16..31 Buffer Byte Length (Write-only) */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVDMACONTROL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVDMACONTROL_OFFSET (0x08) /**< (USBHS_DEVDMACONTROL) Device DMA Channel Control Register Offset */ + +#define USBHS_DEVDMACONTROL_CHANN_ENB_Pos 0 /**< (USBHS_DEVDMACONTROL) Channel Enable Command Position */ +#define USBHS_DEVDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Mask */ +#define USBHS_DEVDMACONTROL_CHANN_ENB USBHS_DEVDMACONTROL_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_CHANN_ENB_Msk instead */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Pos 1 /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC USBHS_DEVDMACONTROL_LDNXT_DSC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_LDNXT_DSC_Msk instead */ +#define USBHS_DEVDMACONTROL_END_TR_EN_Pos 2 /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_DEVDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_DEVDMACONTROL_END_TR_EN USBHS_DEVDMACONTROL_END_TR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_TR_EN_Msk instead */ +#define USBHS_DEVDMACONTROL_END_B_EN_Pos 3 /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_DEVDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_B_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_DEVDMACONTROL_END_B_EN USBHS_DEVDMACONTROL_END_B_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_B_EN_Msk instead */ +#define USBHS_DEVDMACONTROL_END_TR_IT_Pos 4 /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_IT_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_TR_IT USBHS_DEVDMACONTROL_END_TR_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_TR_IT_Msk instead */ +#define USBHS_DEVDMACONTROL_END_BUFFIT_Pos 5 /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_BUFFIT USBHS_DEVDMACONTROL_END_BUFFIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_BUFFIT_Msk instead */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Pos 6 /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT USBHS_DEVDMACONTROL_DESC_LD_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_DESC_LD_IT_Msk instead */ +#define USBHS_DEVDMACONTROL_BURST_LCK_Pos 7 /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Position */ +#define USBHS_DEVDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_BURST_LCK_Pos) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_DEVDMACONTROL_BURST_LCK USBHS_DEVDMACONTROL_BURST_LCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_BURST_LCK_Msk instead */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) (USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_DEVDMACONTROL_MASK _U_(0xFFFF00FF) /**< \deprecated (USBHS_DEVDMACONTROL) Register MASK (Use USBHS_DEVDMACONTROL_Msk instead) */ +#define USBHS_DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_DEVDMACONTROL) Register Mask */ + + +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Status */ + uint32_t CHANN_ACT:1; /**< bit: 1 Channel Active Status */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t END_TR_ST:1; /**< bit: 4 End of Channel Transfer Status */ + uint32_t END_BF_ST:1; /**< bit: 5 End of Channel Buffer Status */ + uint32_t DESC_LDST:1; /**< bit: 6 Descriptor Loaded Status */ + uint32_t :9; /**< bit: 7..15 Reserved */ + uint32_t BUFF_COUNT:16; /**< bit: 16..31 Buffer Byte Count */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVDMASTATUS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVDMASTATUS_OFFSET (0x0C) /**< (USBHS_DEVDMASTATUS) Device DMA Channel Status Register Offset */ + +#define USBHS_DEVDMASTATUS_CHANN_ENB_Pos 0 /**< (USBHS_DEVDMASTATUS) Channel Enable Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ENB USBHS_DEVDMASTATUS_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_CHANN_ENB_Msk instead */ +#define USBHS_DEVDMASTATUS_CHANN_ACT_Pos 1 /**< (USBHS_DEVDMASTATUS) Channel Active Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_DEVDMASTATUS) Channel Active Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ACT USBHS_DEVDMASTATUS_CHANN_ACT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_CHANN_ACT_Msk instead */ +#define USBHS_DEVDMASTATUS_END_TR_ST_Pos 4 /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_DEVDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_TR_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_DEVDMASTATUS_END_TR_ST USBHS_DEVDMASTATUS_END_TR_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_END_TR_ST_Msk instead */ +#define USBHS_DEVDMASTATUS_END_BF_ST_Pos 5 /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_DEVDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_BF_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_DEVDMASTATUS_END_BF_ST USBHS_DEVDMASTATUS_END_BF_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_END_BF_ST_Msk instead */ +#define USBHS_DEVDMASTATUS_DESC_LDST_Pos 6 /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_DEVDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_DESC_LDST_Pos) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_DEVDMASTATUS_DESC_LDST USBHS_DEVDMASTATUS_DESC_LDST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_DESC_LDST_Msk instead */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Position */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) (USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_DEVDMASTATUS_MASK _U_(0xFFFF0073) /**< \deprecated (USBHS_DEVDMASTATUS) Register MASK (Use USBHS_DEVDMASTATUS_Msk instead) */ +#define USBHS_DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_DEVDMASTATUS) Register Mask */ + + +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NXT_DSC_ADD:32; /**< bit: 0..31 Next Descriptor Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTDMANXTDSC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTDMANXTDSC_OFFSET (0x00) /**< (USBHS_HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ + +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) (USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_HSTDMANXTDSC_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_HSTDMANXTDSC) Register MASK (Use USBHS_HSTDMANXTDSC_Msk instead) */ +#define USBHS_HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMANXTDSC) Register Mask */ + + +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BUFF_ADD:32; /**< bit: 0..31 Buffer Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTDMAADDRESS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTDMAADDRESS_OFFSET (0x04) /**< (USBHS_HSTDMAADDRESS) Host DMA Channel Address Register Offset */ + +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 /**< (USBHS_HSTDMAADDRESS) Buffer Address Position */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_HSTDMAADDRESS) Buffer Address Mask */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) (USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_HSTDMAADDRESS_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_HSTDMAADDRESS) Register MASK (Use USBHS_HSTDMAADDRESS_Msk instead) */ +#define USBHS_HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMAADDRESS) Register Mask */ + + +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Command */ + uint32_t LDNXT_DSC:1; /**< bit: 1 Load Next Channel Transfer Descriptor Enable Command */ + uint32_t END_TR_EN:1; /**< bit: 2 End of Transfer Enable Control (OUT transfers only) */ + uint32_t END_B_EN:1; /**< bit: 3 End of Buffer Enable Control */ + uint32_t END_TR_IT:1; /**< bit: 4 End of Transfer Interrupt Enable */ + uint32_t END_BUFFIT:1; /**< bit: 5 End of Buffer Interrupt Enable */ + uint32_t DESC_LD_IT:1; /**< bit: 6 Descriptor Loaded Interrupt Enable */ + uint32_t BURST_LCK:1; /**< bit: 7 Burst Lock Enable */ + uint32_t :8; /**< bit: 8..15 Reserved */ + uint32_t BUFF_LENGTH:16; /**< bit: 16..31 Buffer Byte Length (Write-only) */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTDMACONTROL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTDMACONTROL_OFFSET (0x08) /**< (USBHS_HSTDMACONTROL) Host DMA Channel Control Register Offset */ + +#define USBHS_HSTDMACONTROL_CHANN_ENB_Pos 0 /**< (USBHS_HSTDMACONTROL) Channel Enable Command Position */ +#define USBHS_HSTDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Mask */ +#define USBHS_HSTDMACONTROL_CHANN_ENB USBHS_HSTDMACONTROL_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_CHANN_ENB_Msk instead */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Pos 1 /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC USBHS_HSTDMACONTROL_LDNXT_DSC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_LDNXT_DSC_Msk instead */ +#define USBHS_HSTDMACONTROL_END_TR_EN_Pos 2 /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_HSTDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_HSTDMACONTROL_END_TR_EN USBHS_HSTDMACONTROL_END_TR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_TR_EN_Msk instead */ +#define USBHS_HSTDMACONTROL_END_B_EN_Pos 3 /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_HSTDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_B_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_HSTDMACONTROL_END_B_EN USBHS_HSTDMACONTROL_END_B_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_B_EN_Msk instead */ +#define USBHS_HSTDMACONTROL_END_TR_IT_Pos 4 /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_IT_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_TR_IT USBHS_HSTDMACONTROL_END_TR_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_TR_IT_Msk instead */ +#define USBHS_HSTDMACONTROL_END_BUFFIT_Pos 5 /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_BUFFIT USBHS_HSTDMACONTROL_END_BUFFIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_BUFFIT_Msk instead */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Pos 6 /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT USBHS_HSTDMACONTROL_DESC_LD_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_DESC_LD_IT_Msk instead */ +#define USBHS_HSTDMACONTROL_BURST_LCK_Pos 7 /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Position */ +#define USBHS_HSTDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_BURST_LCK_Pos) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_HSTDMACONTROL_BURST_LCK USBHS_HSTDMACONTROL_BURST_LCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_BURST_LCK_Msk instead */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) (USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_HSTDMACONTROL_MASK _U_(0xFFFF00FF) /**< \deprecated (USBHS_HSTDMACONTROL) Register MASK (Use USBHS_HSTDMACONTROL_Msk instead) */ +#define USBHS_HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_HSTDMACONTROL) Register Mask */ + + +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Status */ + uint32_t CHANN_ACT:1; /**< bit: 1 Channel Active Status */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t END_TR_ST:1; /**< bit: 4 End of Channel Transfer Status */ + uint32_t END_BF_ST:1; /**< bit: 5 End of Channel Buffer Status */ + uint32_t DESC_LDST:1; /**< bit: 6 Descriptor Loaded Status */ + uint32_t :9; /**< bit: 7..15 Reserved */ + uint32_t BUFF_COUNT:16; /**< bit: 16..31 Buffer Byte Count */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTDMASTATUS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTDMASTATUS_OFFSET (0x0C) /**< (USBHS_HSTDMASTATUS) Host DMA Channel Status Register Offset */ + +#define USBHS_HSTDMASTATUS_CHANN_ENB_Pos 0 /**< (USBHS_HSTDMASTATUS) Channel Enable Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ENB USBHS_HSTDMASTATUS_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_CHANN_ENB_Msk instead */ +#define USBHS_HSTDMASTATUS_CHANN_ACT_Pos 1 /**< (USBHS_HSTDMASTATUS) Channel Active Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_HSTDMASTATUS) Channel Active Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ACT USBHS_HSTDMASTATUS_CHANN_ACT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_CHANN_ACT_Msk instead */ +#define USBHS_HSTDMASTATUS_END_TR_ST_Pos 4 /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_HSTDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_TR_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_HSTDMASTATUS_END_TR_ST USBHS_HSTDMASTATUS_END_TR_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_END_TR_ST_Msk instead */ +#define USBHS_HSTDMASTATUS_END_BF_ST_Pos 5 /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_HSTDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_BF_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_HSTDMASTATUS_END_BF_ST USBHS_HSTDMASTATUS_END_BF_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_END_BF_ST_Msk instead */ +#define USBHS_HSTDMASTATUS_DESC_LDST_Pos 6 /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_HSTDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_DESC_LDST_Pos) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_HSTDMASTATUS_DESC_LDST USBHS_HSTDMASTATUS_DESC_LDST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_DESC_LDST_Msk instead */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Position */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) (USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_HSTDMASTATUS_MASK _U_(0xFFFF0073) /**< \deprecated (USBHS_HSTDMASTATUS) Register MASK (Use USBHS_HSTDMASTATUS_Msk instead) */ +#define USBHS_HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_HSTDMASTATUS) Register Mask */ + + +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UADD:7; /**< bit: 0..6 USB Address */ + uint32_t ADDEN:1; /**< bit: 7 Address Enable */ + uint32_t DETACH:1; /**< bit: 8 Detach */ + uint32_t RMWKUP:1; /**< bit: 9 Remote Wake-Up */ + uint32_t SPDCONF:2; /**< bit: 10..11 Mode Configuration */ + uint32_t LS:1; /**< bit: 12 Low-Speed Mode Force */ + uint32_t TSTJ:1; /**< bit: 13 Test mode J */ + uint32_t TSTK:1; /**< bit: 14 Test mode K */ + uint32_t TSTPCKT:1; /**< bit: 15 Test packet mode */ + uint32_t OPMODE2:1; /**< bit: 16 Specific Operational mode */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :16; /**< bit: 0..15 Reserved */ + uint32_t OPMODE:1; /**< bit: 16 Specific Operational mode */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVCTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVCTRL_OFFSET (0x00) /**< (USBHS_DEVCTRL) Device General Control Register Offset */ + +#define USBHS_DEVCTRL_UADD_Pos 0 /**< (USBHS_DEVCTRL) USB Address Position */ +#define USBHS_DEVCTRL_UADD_Msk (_U_(0x7F) << USBHS_DEVCTRL_UADD_Pos) /**< (USBHS_DEVCTRL) USB Address Mask */ +#define USBHS_DEVCTRL_UADD(value) (USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)) +#define USBHS_DEVCTRL_ADDEN_Pos 7 /**< (USBHS_DEVCTRL) Address Enable Position */ +#define USBHS_DEVCTRL_ADDEN_Msk (_U_(0x1) << USBHS_DEVCTRL_ADDEN_Pos) /**< (USBHS_DEVCTRL) Address Enable Mask */ +#define USBHS_DEVCTRL_ADDEN USBHS_DEVCTRL_ADDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_ADDEN_Msk instead */ +#define USBHS_DEVCTRL_DETACH_Pos 8 /**< (USBHS_DEVCTRL) Detach Position */ +#define USBHS_DEVCTRL_DETACH_Msk (_U_(0x1) << USBHS_DEVCTRL_DETACH_Pos) /**< (USBHS_DEVCTRL) Detach Mask */ +#define USBHS_DEVCTRL_DETACH USBHS_DEVCTRL_DETACH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_DETACH_Msk instead */ +#define USBHS_DEVCTRL_RMWKUP_Pos 9 /**< (USBHS_DEVCTRL) Remote Wake-Up Position */ +#define USBHS_DEVCTRL_RMWKUP_Msk (_U_(0x1) << USBHS_DEVCTRL_RMWKUP_Pos) /**< (USBHS_DEVCTRL) Remote Wake-Up Mask */ +#define USBHS_DEVCTRL_RMWKUP USBHS_DEVCTRL_RMWKUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_RMWKUP_Msk instead */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 /**< (USBHS_DEVCTRL) Mode Configuration Position */ +#define USBHS_DEVCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Mode Configuration Mask */ +#define USBHS_DEVCTRL_SPDCONF(value) (USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)) +#define USBHS_DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_SPDCONF_NORMAL (USBHS_DEVCTRL_SPDCONF_NORMAL_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Forced high speed. Position */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ +#define USBHS_DEVCTRL_LS_Pos 12 /**< (USBHS_DEVCTRL) Low-Speed Mode Force Position */ +#define USBHS_DEVCTRL_LS_Msk (_U_(0x1) << USBHS_DEVCTRL_LS_Pos) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Mask */ +#define USBHS_DEVCTRL_LS USBHS_DEVCTRL_LS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_LS_Msk instead */ +#define USBHS_DEVCTRL_TSTJ_Pos 13 /**< (USBHS_DEVCTRL) Test mode J Position */ +#define USBHS_DEVCTRL_TSTJ_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTJ_Pos) /**< (USBHS_DEVCTRL) Test mode J Mask */ +#define USBHS_DEVCTRL_TSTJ USBHS_DEVCTRL_TSTJ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTJ_Msk instead */ +#define USBHS_DEVCTRL_TSTK_Pos 14 /**< (USBHS_DEVCTRL) Test mode K Position */ +#define USBHS_DEVCTRL_TSTK_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTK_Pos) /**< (USBHS_DEVCTRL) Test mode K Mask */ +#define USBHS_DEVCTRL_TSTK USBHS_DEVCTRL_TSTK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTK_Msk instead */ +#define USBHS_DEVCTRL_TSTPCKT_Pos 15 /**< (USBHS_DEVCTRL) Test packet mode Position */ +#define USBHS_DEVCTRL_TSTPCKT_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTPCKT_Pos) /**< (USBHS_DEVCTRL) Test packet mode Mask */ +#define USBHS_DEVCTRL_TSTPCKT USBHS_DEVCTRL_TSTPCKT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTPCKT_Msk instead */ +#define USBHS_DEVCTRL_OPMODE2_Pos 16 /**< (USBHS_DEVCTRL) Specific Operational mode Position */ +#define USBHS_DEVCTRL_OPMODE2_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE2_Pos) /**< (USBHS_DEVCTRL) Specific Operational mode Mask */ +#define USBHS_DEVCTRL_OPMODE2 USBHS_DEVCTRL_OPMODE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_OPMODE2_Msk instead */ +#define USBHS_DEVCTRL_MASK _U_(0x1FFFF) /**< \deprecated (USBHS_DEVCTRL) Register MASK (Use USBHS_DEVCTRL_Msk instead) */ +#define USBHS_DEVCTRL_Msk _U_(0x1FFFF) /**< (USBHS_DEVCTRL) Register Mask */ + +#define USBHS_DEVCTRL_OPMODE_Pos 16 /**< (USBHS_DEVCTRL Position) Specific Operational mode */ +#define USBHS_DEVCTRL_OPMODE_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE_Pos) /**< (USBHS_DEVCTRL Mask) OPMODE */ +#define USBHS_DEVCTRL_OPMODE(value) (USBHS_DEVCTRL_OPMODE_Msk & ((value) << USBHS_DEVCTRL_OPMODE_Pos)) + +/* -------- USBHS_DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSP:1; /**< bit: 0 Suspend Interrupt */ + uint32_t MSOF:1; /**< bit: 1 Micro Start of Frame Interrupt */ + uint32_t SOF:1; /**< bit: 2 Start of Frame Interrupt */ + uint32_t EORST:1; /**< bit: 3 End of Reset Interrupt */ + uint32_t WAKEUP:1; /**< bit: 4 Wake-Up Interrupt */ + uint32_t EORSM:1; /**< bit: 5 End of Resume Interrupt */ + uint32_t UPRSM:1; /**< bit: 6 Upstream Resume Interrupt */ + uint32_t :5; /**< bit: 7..11 Reserved */ + uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt */ + uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt */ + uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt */ + uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt */ + uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt */ + uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt */ + uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt */ + uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt */ + uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt */ + uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt */ + uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt */ + uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt */ + uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt */ + uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt */ + uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt */ + uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :12; /**< bit: 0..11 Reserved */ + uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVISR_OFFSET (0x04) /**< (USBHS_DEVISR) Device Global Interrupt Status Register Offset */ + +#define USBHS_DEVISR_SUSP_Pos 0 /**< (USBHS_DEVISR) Suspend Interrupt Position */ +#define USBHS_DEVISR_SUSP_Msk (_U_(0x1) << USBHS_DEVISR_SUSP_Pos) /**< (USBHS_DEVISR) Suspend Interrupt Mask */ +#define USBHS_DEVISR_SUSP USBHS_DEVISR_SUSP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_SUSP_Msk instead */ +#define USBHS_DEVISR_MSOF_Pos 1 /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Position */ +#define USBHS_DEVISR_MSOF_Msk (_U_(0x1) << USBHS_DEVISR_MSOF_Pos) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_MSOF USBHS_DEVISR_MSOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_MSOF_Msk instead */ +#define USBHS_DEVISR_SOF_Pos 2 /**< (USBHS_DEVISR) Start of Frame Interrupt Position */ +#define USBHS_DEVISR_SOF_Msk (_U_(0x1) << USBHS_DEVISR_SOF_Pos) /**< (USBHS_DEVISR) Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_SOF USBHS_DEVISR_SOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_SOF_Msk instead */ +#define USBHS_DEVISR_EORST_Pos 3 /**< (USBHS_DEVISR) End of Reset Interrupt Position */ +#define USBHS_DEVISR_EORST_Msk (_U_(0x1) << USBHS_DEVISR_EORST_Pos) /**< (USBHS_DEVISR) End of Reset Interrupt Mask */ +#define USBHS_DEVISR_EORST USBHS_DEVISR_EORST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_EORST_Msk instead */ +#define USBHS_DEVISR_WAKEUP_Pos 4 /**< (USBHS_DEVISR) Wake-Up Interrupt Position */ +#define USBHS_DEVISR_WAKEUP_Msk (_U_(0x1) << USBHS_DEVISR_WAKEUP_Pos) /**< (USBHS_DEVISR) Wake-Up Interrupt Mask */ +#define USBHS_DEVISR_WAKEUP USBHS_DEVISR_WAKEUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_WAKEUP_Msk instead */ +#define USBHS_DEVISR_EORSM_Pos 5 /**< (USBHS_DEVISR) End of Resume Interrupt Position */ +#define USBHS_DEVISR_EORSM_Msk (_U_(0x1) << USBHS_DEVISR_EORSM_Pos) /**< (USBHS_DEVISR) End of Resume Interrupt Mask */ +#define USBHS_DEVISR_EORSM USBHS_DEVISR_EORSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_EORSM_Msk instead */ +#define USBHS_DEVISR_UPRSM_Pos 6 /**< (USBHS_DEVISR) Upstream Resume Interrupt Position */ +#define USBHS_DEVISR_UPRSM_Msk (_U_(0x1) << USBHS_DEVISR_UPRSM_Pos) /**< (USBHS_DEVISR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVISR_UPRSM USBHS_DEVISR_UPRSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_UPRSM_Msk instead */ +#define USBHS_DEVISR_PEP_0_Pos 12 /**< (USBHS_DEVISR) Endpoint 0 Interrupt Position */ +#define USBHS_DEVISR_PEP_0_Msk (_U_(0x1) << USBHS_DEVISR_PEP_0_Pos) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVISR_PEP_0 USBHS_DEVISR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_0_Msk instead */ +#define USBHS_DEVISR_PEP_1_Pos 13 /**< (USBHS_DEVISR) Endpoint 1 Interrupt Position */ +#define USBHS_DEVISR_PEP_1_Msk (_U_(0x1) << USBHS_DEVISR_PEP_1_Pos) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVISR_PEP_1 USBHS_DEVISR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_1_Msk instead */ +#define USBHS_DEVISR_PEP_2_Pos 14 /**< (USBHS_DEVISR) Endpoint 2 Interrupt Position */ +#define USBHS_DEVISR_PEP_2_Msk (_U_(0x1) << USBHS_DEVISR_PEP_2_Pos) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVISR_PEP_2 USBHS_DEVISR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_2_Msk instead */ +#define USBHS_DEVISR_PEP_3_Pos 15 /**< (USBHS_DEVISR) Endpoint 3 Interrupt Position */ +#define USBHS_DEVISR_PEP_3_Msk (_U_(0x1) << USBHS_DEVISR_PEP_3_Pos) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVISR_PEP_3 USBHS_DEVISR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_3_Msk instead */ +#define USBHS_DEVISR_PEP_4_Pos 16 /**< (USBHS_DEVISR) Endpoint 4 Interrupt Position */ +#define USBHS_DEVISR_PEP_4_Msk (_U_(0x1) << USBHS_DEVISR_PEP_4_Pos) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVISR_PEP_4 USBHS_DEVISR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_4_Msk instead */ +#define USBHS_DEVISR_PEP_5_Pos 17 /**< (USBHS_DEVISR) Endpoint 5 Interrupt Position */ +#define USBHS_DEVISR_PEP_5_Msk (_U_(0x1) << USBHS_DEVISR_PEP_5_Pos) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVISR_PEP_5 USBHS_DEVISR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_5_Msk instead */ +#define USBHS_DEVISR_PEP_6_Pos 18 /**< (USBHS_DEVISR) Endpoint 6 Interrupt Position */ +#define USBHS_DEVISR_PEP_6_Msk (_U_(0x1) << USBHS_DEVISR_PEP_6_Pos) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVISR_PEP_6 USBHS_DEVISR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_6_Msk instead */ +#define USBHS_DEVISR_PEP_7_Pos 19 /**< (USBHS_DEVISR) Endpoint 7 Interrupt Position */ +#define USBHS_DEVISR_PEP_7_Msk (_U_(0x1) << USBHS_DEVISR_PEP_7_Pos) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVISR_PEP_7 USBHS_DEVISR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_7_Msk instead */ +#define USBHS_DEVISR_PEP_8_Pos 20 /**< (USBHS_DEVISR) Endpoint 8 Interrupt Position */ +#define USBHS_DEVISR_PEP_8_Msk (_U_(0x1) << USBHS_DEVISR_PEP_8_Pos) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVISR_PEP_8 USBHS_DEVISR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_8_Msk instead */ +#define USBHS_DEVISR_PEP_9_Pos 21 /**< (USBHS_DEVISR) Endpoint 9 Interrupt Position */ +#define USBHS_DEVISR_PEP_9_Msk (_U_(0x1) << USBHS_DEVISR_PEP_9_Pos) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVISR_PEP_9 USBHS_DEVISR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_9_Msk instead */ +#define USBHS_DEVISR_DMA_1_Pos 25 /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Position */ +#define USBHS_DEVISR_DMA_1_Msk (_U_(0x1) << USBHS_DEVISR_DMA_1_Pos) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVISR_DMA_1 USBHS_DEVISR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_1_Msk instead */ +#define USBHS_DEVISR_DMA_2_Pos 26 /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Position */ +#define USBHS_DEVISR_DMA_2_Msk (_U_(0x1) << USBHS_DEVISR_DMA_2_Pos) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVISR_DMA_2 USBHS_DEVISR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_2_Msk instead */ +#define USBHS_DEVISR_DMA_3_Pos 27 /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Position */ +#define USBHS_DEVISR_DMA_3_Msk (_U_(0x1) << USBHS_DEVISR_DMA_3_Pos) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVISR_DMA_3 USBHS_DEVISR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_3_Msk instead */ +#define USBHS_DEVISR_DMA_4_Pos 28 /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Position */ +#define USBHS_DEVISR_DMA_4_Msk (_U_(0x1) << USBHS_DEVISR_DMA_4_Pos) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVISR_DMA_4 USBHS_DEVISR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_4_Msk instead */ +#define USBHS_DEVISR_DMA_5_Pos 29 /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Position */ +#define USBHS_DEVISR_DMA_5_Msk (_U_(0x1) << USBHS_DEVISR_DMA_5_Pos) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVISR_DMA_5 USBHS_DEVISR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_5_Msk instead */ +#define USBHS_DEVISR_DMA_6_Pos 30 /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Position */ +#define USBHS_DEVISR_DMA_6_Msk (_U_(0x1) << USBHS_DEVISR_DMA_6_Pos) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVISR_DMA_6 USBHS_DEVISR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_6_Msk instead */ +#define USBHS_DEVISR_DMA_7_Pos 31 /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Position */ +#define USBHS_DEVISR_DMA_7_Msk (_U_(0x1) << USBHS_DEVISR_DMA_7_Pos) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVISR_DMA_7 USBHS_DEVISR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_7_Msk instead */ +#define USBHS_DEVISR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVISR) Register MASK (Use USBHS_DEVISR_Msk instead) */ +#define USBHS_DEVISR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVISR) Register Mask */ + +#define USBHS_DEVISR_PEP__Pos 12 /**< (USBHS_DEVISR Position) Endpoint x Interrupt */ +#define USBHS_DEVISR_PEP__Msk (_U_(0x3FF) << USBHS_DEVISR_PEP__Pos) /**< (USBHS_DEVISR Mask) PEP_ */ +#define USBHS_DEVISR_PEP_(value) (USBHS_DEVISR_PEP__Msk & ((value) << USBHS_DEVISR_PEP__Pos)) +#define USBHS_DEVISR_DMA__Pos 25 /**< (USBHS_DEVISR Position) DMA Channel 7 Interrupt */ +#define USBHS_DEVISR_DMA__Msk (_U_(0x7F) << USBHS_DEVISR_DMA__Pos) /**< (USBHS_DEVISR Mask) DMA_ */ +#define USBHS_DEVISR_DMA_(value) (USBHS_DEVISR_DMA__Msk & ((value) << USBHS_DEVISR_DMA__Pos)) + +/* -------- USBHS_DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSPC:1; /**< bit: 0 Suspend Interrupt Clear */ + uint32_t MSOFC:1; /**< bit: 1 Micro Start of Frame Interrupt Clear */ + uint32_t SOFC:1; /**< bit: 2 Start of Frame Interrupt Clear */ + uint32_t EORSTC:1; /**< bit: 3 End of Reset Interrupt Clear */ + uint32_t WAKEUPC:1; /**< bit: 4 Wake-Up Interrupt Clear */ + uint32_t EORSMC:1; /**< bit: 5 End of Resume Interrupt Clear */ + uint32_t UPRSMC:1; /**< bit: 6 Upstream Resume Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVICR_OFFSET (0x08) /**< (USBHS_DEVICR) Device Global Interrupt Clear Register Offset */ + +#define USBHS_DEVICR_SUSPC_Pos 0 /**< (USBHS_DEVICR) Suspend Interrupt Clear Position */ +#define USBHS_DEVICR_SUSPC_Msk (_U_(0x1) << USBHS_DEVICR_SUSPC_Pos) /**< (USBHS_DEVICR) Suspend Interrupt Clear Mask */ +#define USBHS_DEVICR_SUSPC USBHS_DEVICR_SUSPC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_SUSPC_Msk instead */ +#define USBHS_DEVICR_MSOFC_Pos 1 /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_MSOFC_Msk (_U_(0x1) << USBHS_DEVICR_MSOFC_Pos) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_MSOFC USBHS_DEVICR_MSOFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_MSOFC_Msk instead */ +#define USBHS_DEVICR_SOFC_Pos 2 /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_SOFC_Msk (_U_(0x1) << USBHS_DEVICR_SOFC_Pos) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_SOFC USBHS_DEVICR_SOFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_SOFC_Msk instead */ +#define USBHS_DEVICR_EORSTC_Pos 3 /**< (USBHS_DEVICR) End of Reset Interrupt Clear Position */ +#define USBHS_DEVICR_EORSTC_Msk (_U_(0x1) << USBHS_DEVICR_EORSTC_Pos) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSTC USBHS_DEVICR_EORSTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_EORSTC_Msk instead */ +#define USBHS_DEVICR_WAKEUPC_Pos 4 /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Position */ +#define USBHS_DEVICR_WAKEUPC_Msk (_U_(0x1) << USBHS_DEVICR_WAKEUPC_Pos) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Mask */ +#define USBHS_DEVICR_WAKEUPC USBHS_DEVICR_WAKEUPC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_WAKEUPC_Msk instead */ +#define USBHS_DEVICR_EORSMC_Pos 5 /**< (USBHS_DEVICR) End of Resume Interrupt Clear Position */ +#define USBHS_DEVICR_EORSMC_Msk (_U_(0x1) << USBHS_DEVICR_EORSMC_Pos) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSMC USBHS_DEVICR_EORSMC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_EORSMC_Msk instead */ +#define USBHS_DEVICR_UPRSMC_Pos 6 /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Position */ +#define USBHS_DEVICR_UPRSMC_Msk (_U_(0x1) << USBHS_DEVICR_UPRSMC_Pos) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_UPRSMC USBHS_DEVICR_UPRSMC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_UPRSMC_Msk instead */ +#define USBHS_DEVICR_MASK _U_(0x7F) /**< \deprecated (USBHS_DEVICR) Register MASK (Use USBHS_DEVICR_Msk instead) */ +#define USBHS_DEVICR_Msk _U_(0x7F) /**< (USBHS_DEVICR) Register Mask */ + + +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSPS:1; /**< bit: 0 Suspend Interrupt Set */ + uint32_t MSOFS:1; /**< bit: 1 Micro Start of Frame Interrupt Set */ + uint32_t SOFS:1; /**< bit: 2 Start of Frame Interrupt Set */ + uint32_t EORSTS:1; /**< bit: 3 End of Reset Interrupt Set */ + uint32_t WAKEUPS:1; /**< bit: 4 Wake-Up Interrupt Set */ + uint32_t EORSMS:1; /**< bit: 5 End of Resume Interrupt Set */ + uint32_t UPRSMS:1; /**< bit: 6 Upstream Resume Interrupt Set */ + uint32_t :18; /**< bit: 7..24 Reserved */ + uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Set */ + uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Set */ + uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Set */ + uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Set */ + uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Set */ + uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Set */ + uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Set */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :25; /**< bit: 0..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Set */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVIFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVIFR_OFFSET (0x0C) /**< (USBHS_DEVIFR) Device Global Interrupt Set Register Offset */ + +#define USBHS_DEVIFR_SUSPS_Pos 0 /**< (USBHS_DEVIFR) Suspend Interrupt Set Position */ +#define USBHS_DEVIFR_SUSPS_Msk (_U_(0x1) << USBHS_DEVIFR_SUSPS_Pos) /**< (USBHS_DEVIFR) Suspend Interrupt Set Mask */ +#define USBHS_DEVIFR_SUSPS USBHS_DEVIFR_SUSPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_SUSPS_Msk instead */ +#define USBHS_DEVIFR_MSOFS_Pos 1 /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_MSOFS_Msk (_U_(0x1) << USBHS_DEVIFR_MSOFS_Pos) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_MSOFS USBHS_DEVIFR_MSOFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_MSOFS_Msk instead */ +#define USBHS_DEVIFR_SOFS_Pos 2 /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_SOFS_Msk (_U_(0x1) << USBHS_DEVIFR_SOFS_Pos) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_SOFS USBHS_DEVIFR_SOFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_SOFS_Msk instead */ +#define USBHS_DEVIFR_EORSTS_Pos 3 /**< (USBHS_DEVIFR) End of Reset Interrupt Set Position */ +#define USBHS_DEVIFR_EORSTS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSTS_Pos) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSTS USBHS_DEVIFR_EORSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_EORSTS_Msk instead */ +#define USBHS_DEVIFR_WAKEUPS_Pos 4 /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Position */ +#define USBHS_DEVIFR_WAKEUPS_Msk (_U_(0x1) << USBHS_DEVIFR_WAKEUPS_Pos) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Mask */ +#define USBHS_DEVIFR_WAKEUPS USBHS_DEVIFR_WAKEUPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_WAKEUPS_Msk instead */ +#define USBHS_DEVIFR_EORSMS_Pos 5 /**< (USBHS_DEVIFR) End of Resume Interrupt Set Position */ +#define USBHS_DEVIFR_EORSMS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSMS_Pos) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSMS USBHS_DEVIFR_EORSMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_EORSMS_Msk instead */ +#define USBHS_DEVIFR_UPRSMS_Pos 6 /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Position */ +#define USBHS_DEVIFR_UPRSMS_Msk (_U_(0x1) << USBHS_DEVIFR_UPRSMS_Pos) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_UPRSMS USBHS_DEVIFR_UPRSMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_UPRSMS_Msk instead */ +#define USBHS_DEVIFR_DMA_1_Pos 25 /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_1_Pos) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_1 USBHS_DEVIFR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_1_Msk instead */ +#define USBHS_DEVIFR_DMA_2_Pos 26 /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_2_Pos) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_2 USBHS_DEVIFR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_2_Msk instead */ +#define USBHS_DEVIFR_DMA_3_Pos 27 /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_3_Pos) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_3 USBHS_DEVIFR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_3_Msk instead */ +#define USBHS_DEVIFR_DMA_4_Pos 28 /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_4_Pos) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_4 USBHS_DEVIFR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_4_Msk instead */ +#define USBHS_DEVIFR_DMA_5_Pos 29 /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_5_Pos) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_5 USBHS_DEVIFR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_5_Msk instead */ +#define USBHS_DEVIFR_DMA_6_Pos 30 /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_6_Pos) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_6 USBHS_DEVIFR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_6_Msk instead */ +#define USBHS_DEVIFR_DMA_7_Pos 31 /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_7_Pos) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_7 USBHS_DEVIFR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_7_Msk instead */ +#define USBHS_DEVIFR_MASK _U_(0xFE00007F) /**< \deprecated (USBHS_DEVIFR) Register MASK (Use USBHS_DEVIFR_Msk instead) */ +#define USBHS_DEVIFR_Msk _U_(0xFE00007F) /**< (USBHS_DEVIFR) Register Mask */ + +#define USBHS_DEVIFR_DMA__Pos 25 /**< (USBHS_DEVIFR Position) DMA Channel 7 Interrupt Set */ +#define USBHS_DEVIFR_DMA__Msk (_U_(0x7F) << USBHS_DEVIFR_DMA__Pos) /**< (USBHS_DEVIFR Mask) DMA_ */ +#define USBHS_DEVIFR_DMA_(value) (USBHS_DEVIFR_DMA__Msk & ((value) << USBHS_DEVIFR_DMA__Pos)) + +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSPE:1; /**< bit: 0 Suspend Interrupt Mask */ + uint32_t MSOFE:1; /**< bit: 1 Micro Start of Frame Interrupt Mask */ + uint32_t SOFE:1; /**< bit: 2 Start of Frame Interrupt Mask */ + uint32_t EORSTE:1; /**< bit: 3 End of Reset Interrupt Mask */ + uint32_t WAKEUPE:1; /**< bit: 4 Wake-Up Interrupt Mask */ + uint32_t EORSME:1; /**< bit: 5 End of Resume Interrupt Mask */ + uint32_t UPRSME:1; /**< bit: 6 Upstream Resume Interrupt Mask */ + uint32_t :5; /**< bit: 7..11 Reserved */ + uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Mask */ + uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Mask */ + uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Mask */ + uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Mask */ + uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Mask */ + uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Mask */ + uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Mask */ + uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Mask */ + uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Mask */ + uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Mask */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Mask */ + uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Mask */ + uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Mask */ + uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Mask */ + uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Mask */ + uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Mask */ + uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Mask */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :12; /**< bit: 0..11 Reserved */ + uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Mask */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Mask */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVIMR_OFFSET (0x10) /**< (USBHS_DEVIMR) Device Global Interrupt Mask Register Offset */ + +#define USBHS_DEVIMR_SUSPE_Pos 0 /**< (USBHS_DEVIMR) Suspend Interrupt Mask Position */ +#define USBHS_DEVIMR_SUSPE_Msk (_U_(0x1) << USBHS_DEVIMR_SUSPE_Pos) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Mask */ +#define USBHS_DEVIMR_SUSPE USBHS_DEVIMR_SUSPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_SUSPE_Msk instead */ +#define USBHS_DEVIMR_MSOFE_Pos 1 /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_MSOFE_Msk (_U_(0x1) << USBHS_DEVIMR_MSOFE_Pos) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_MSOFE USBHS_DEVIMR_MSOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_MSOFE_Msk instead */ +#define USBHS_DEVIMR_SOFE_Pos 2 /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_SOFE_Msk (_U_(0x1) << USBHS_DEVIMR_SOFE_Pos) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_SOFE USBHS_DEVIMR_SOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_SOFE_Msk instead */ +#define USBHS_DEVIMR_EORSTE_Pos 3 /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSTE_Msk (_U_(0x1) << USBHS_DEVIMR_EORSTE_Pos) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSTE USBHS_DEVIMR_EORSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_EORSTE_Msk instead */ +#define USBHS_DEVIMR_WAKEUPE_Pos 4 /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Position */ +#define USBHS_DEVIMR_WAKEUPE_Msk (_U_(0x1) << USBHS_DEVIMR_WAKEUPE_Pos) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Mask */ +#define USBHS_DEVIMR_WAKEUPE USBHS_DEVIMR_WAKEUPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_WAKEUPE_Msk instead */ +#define USBHS_DEVIMR_EORSME_Pos 5 /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSME_Msk (_U_(0x1) << USBHS_DEVIMR_EORSME_Pos) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSME USBHS_DEVIMR_EORSME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_EORSME_Msk instead */ +#define USBHS_DEVIMR_UPRSME_Pos 6 /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_UPRSME_Msk (_U_(0x1) << USBHS_DEVIMR_UPRSME_Pos) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_UPRSME USBHS_DEVIMR_UPRSME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_UPRSME_Msk instead */ +#define USBHS_DEVIMR_PEP_0_Pos 12 /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_0_Pos) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_0 USBHS_DEVIMR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_0_Msk instead */ +#define USBHS_DEVIMR_PEP_1_Pos 13 /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_1_Pos) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_1 USBHS_DEVIMR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_1_Msk instead */ +#define USBHS_DEVIMR_PEP_2_Pos 14 /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_2_Pos) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_2 USBHS_DEVIMR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_2_Msk instead */ +#define USBHS_DEVIMR_PEP_3_Pos 15 /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_3_Pos) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_3 USBHS_DEVIMR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_3_Msk instead */ +#define USBHS_DEVIMR_PEP_4_Pos 16 /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_4_Pos) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_4 USBHS_DEVIMR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_4_Msk instead */ +#define USBHS_DEVIMR_PEP_5_Pos 17 /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_5_Pos) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_5 USBHS_DEVIMR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_5_Msk instead */ +#define USBHS_DEVIMR_PEP_6_Pos 18 /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_6_Pos) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_6 USBHS_DEVIMR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_6_Msk instead */ +#define USBHS_DEVIMR_PEP_7_Pos 19 /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_7_Pos) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_7 USBHS_DEVIMR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_7_Msk instead */ +#define USBHS_DEVIMR_PEP_8_Pos 20 /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_8_Pos) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_8 USBHS_DEVIMR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_8_Msk instead */ +#define USBHS_DEVIMR_PEP_9_Pos 21 /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_9_Pos) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_9 USBHS_DEVIMR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_9_Msk instead */ +#define USBHS_DEVIMR_DMA_1_Pos 25 /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_1_Pos) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_1 USBHS_DEVIMR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_1_Msk instead */ +#define USBHS_DEVIMR_DMA_2_Pos 26 /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_2_Pos) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_2 USBHS_DEVIMR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_2_Msk instead */ +#define USBHS_DEVIMR_DMA_3_Pos 27 /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_3_Pos) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_3 USBHS_DEVIMR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_3_Msk instead */ +#define USBHS_DEVIMR_DMA_4_Pos 28 /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_4_Pos) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_4 USBHS_DEVIMR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_4_Msk instead */ +#define USBHS_DEVIMR_DMA_5_Pos 29 /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_5_Pos) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_5 USBHS_DEVIMR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_5_Msk instead */ +#define USBHS_DEVIMR_DMA_6_Pos 30 /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_6_Pos) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_6 USBHS_DEVIMR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_6_Msk instead */ +#define USBHS_DEVIMR_DMA_7_Pos 31 /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_7_Pos) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_7 USBHS_DEVIMR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_7_Msk instead */ +#define USBHS_DEVIMR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIMR) Register MASK (Use USBHS_DEVIMR_Msk instead) */ +#define USBHS_DEVIMR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIMR) Register Mask */ + +#define USBHS_DEVIMR_PEP__Pos 12 /**< (USBHS_DEVIMR Position) Endpoint x Interrupt Mask */ +#define USBHS_DEVIMR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIMR_PEP__Pos) /**< (USBHS_DEVIMR Mask) PEP_ */ +#define USBHS_DEVIMR_PEP_(value) (USBHS_DEVIMR_PEP__Msk & ((value) << USBHS_DEVIMR_PEP__Pos)) +#define USBHS_DEVIMR_DMA__Pos 25 /**< (USBHS_DEVIMR Position) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVIMR_DMA__Msk (_U_(0x7F) << USBHS_DEVIMR_DMA__Pos) /**< (USBHS_DEVIMR Mask) DMA_ */ +#define USBHS_DEVIMR_DMA_(value) (USBHS_DEVIMR_DMA__Msk & ((value) << USBHS_DEVIMR_DMA__Pos)) + +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSPEC:1; /**< bit: 0 Suspend Interrupt Disable */ + uint32_t MSOFEC:1; /**< bit: 1 Micro Start of Frame Interrupt Disable */ + uint32_t SOFEC:1; /**< bit: 2 Start of Frame Interrupt Disable */ + uint32_t EORSTEC:1; /**< bit: 3 End of Reset Interrupt Disable */ + uint32_t WAKEUPEC:1; /**< bit: 4 Wake-Up Interrupt Disable */ + uint32_t EORSMEC:1; /**< bit: 5 End of Resume Interrupt Disable */ + uint32_t UPRSMEC:1; /**< bit: 6 Upstream Resume Interrupt Disable */ + uint32_t :5; /**< bit: 7..11 Reserved */ + uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Disable */ + uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Disable */ + uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Disable */ + uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Disable */ + uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Disable */ + uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Disable */ + uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Disable */ + uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Disable */ + uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Disable */ + uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Disable */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Disable */ + uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Disable */ + uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Disable */ + uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Disable */ + uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Disable */ + uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Disable */ + uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :12; /**< bit: 0..11 Reserved */ + uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Disable */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVIDR_OFFSET (0x14) /**< (USBHS_DEVIDR) Device Global Interrupt Disable Register Offset */ + +#define USBHS_DEVIDR_SUSPEC_Pos 0 /**< (USBHS_DEVIDR) Suspend Interrupt Disable Position */ +#define USBHS_DEVIDR_SUSPEC_Msk (_U_(0x1) << USBHS_DEVIDR_SUSPEC_Pos) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Mask */ +#define USBHS_DEVIDR_SUSPEC USBHS_DEVIDR_SUSPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_SUSPEC_Msk instead */ +#define USBHS_DEVIDR_MSOFEC_Pos 1 /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_MSOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_MSOFEC_Pos) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_MSOFEC USBHS_DEVIDR_MSOFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_MSOFEC_Msk instead */ +#define USBHS_DEVIDR_SOFEC_Pos 2 /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_SOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_SOFEC_Pos) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_SOFEC USBHS_DEVIDR_SOFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_SOFEC_Msk instead */ +#define USBHS_DEVIDR_EORSTEC_Pos 3 /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSTEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSTEC_Pos) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSTEC USBHS_DEVIDR_EORSTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_EORSTEC_Msk instead */ +#define USBHS_DEVIDR_WAKEUPEC_Pos 4 /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Position */ +#define USBHS_DEVIDR_WAKEUPEC_Msk (_U_(0x1) << USBHS_DEVIDR_WAKEUPEC_Pos) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Mask */ +#define USBHS_DEVIDR_WAKEUPEC USBHS_DEVIDR_WAKEUPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_WAKEUPEC_Msk instead */ +#define USBHS_DEVIDR_EORSMEC_Pos 5 /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSMEC_Pos) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSMEC USBHS_DEVIDR_EORSMEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_EORSMEC_Msk instead */ +#define USBHS_DEVIDR_UPRSMEC_Pos 6 /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_UPRSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_UPRSMEC_Pos) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_UPRSMEC USBHS_DEVIDR_UPRSMEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_UPRSMEC_Msk instead */ +#define USBHS_DEVIDR_PEP_0_Pos 12 /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_0_Pos) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_0 USBHS_DEVIDR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_0_Msk instead */ +#define USBHS_DEVIDR_PEP_1_Pos 13 /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_1_Pos) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_1 USBHS_DEVIDR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_1_Msk instead */ +#define USBHS_DEVIDR_PEP_2_Pos 14 /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_2_Pos) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_2 USBHS_DEVIDR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_2_Msk instead */ +#define USBHS_DEVIDR_PEP_3_Pos 15 /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_3_Pos) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_3 USBHS_DEVIDR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_3_Msk instead */ +#define USBHS_DEVIDR_PEP_4_Pos 16 /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_4_Pos) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_4 USBHS_DEVIDR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_4_Msk instead */ +#define USBHS_DEVIDR_PEP_5_Pos 17 /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_5_Pos) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_5 USBHS_DEVIDR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_5_Msk instead */ +#define USBHS_DEVIDR_PEP_6_Pos 18 /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_6_Pos) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_6 USBHS_DEVIDR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_6_Msk instead */ +#define USBHS_DEVIDR_PEP_7_Pos 19 /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_7_Pos) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_7 USBHS_DEVIDR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_7_Msk instead */ +#define USBHS_DEVIDR_PEP_8_Pos 20 /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_8_Pos) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_8 USBHS_DEVIDR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_8_Msk instead */ +#define USBHS_DEVIDR_PEP_9_Pos 21 /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_9_Pos) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_9 USBHS_DEVIDR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_9_Msk instead */ +#define USBHS_DEVIDR_DMA_1_Pos 25 /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_1_Pos) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_1 USBHS_DEVIDR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_1_Msk instead */ +#define USBHS_DEVIDR_DMA_2_Pos 26 /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_2_Pos) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_2 USBHS_DEVIDR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_2_Msk instead */ +#define USBHS_DEVIDR_DMA_3_Pos 27 /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_3_Pos) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_3 USBHS_DEVIDR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_3_Msk instead */ +#define USBHS_DEVIDR_DMA_4_Pos 28 /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_4_Pos) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_4 USBHS_DEVIDR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_4_Msk instead */ +#define USBHS_DEVIDR_DMA_5_Pos 29 /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_5_Pos) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_5 USBHS_DEVIDR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_5_Msk instead */ +#define USBHS_DEVIDR_DMA_6_Pos 30 /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_6_Pos) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_6 USBHS_DEVIDR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_6_Msk instead */ +#define USBHS_DEVIDR_DMA_7_Pos 31 /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_7_Pos) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_7 USBHS_DEVIDR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_7_Msk instead */ +#define USBHS_DEVIDR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIDR) Register MASK (Use USBHS_DEVIDR_Msk instead) */ +#define USBHS_DEVIDR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIDR) Register Mask */ + +#define USBHS_DEVIDR_PEP__Pos 12 /**< (USBHS_DEVIDR Position) Endpoint x Interrupt Disable */ +#define USBHS_DEVIDR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIDR_PEP__Pos) /**< (USBHS_DEVIDR Mask) PEP_ */ +#define USBHS_DEVIDR_PEP_(value) (USBHS_DEVIDR_PEP__Msk & ((value) << USBHS_DEVIDR_PEP__Pos)) +#define USBHS_DEVIDR_DMA__Pos 25 /**< (USBHS_DEVIDR Position) DMA Channel 7 Interrupt Disable */ +#define USBHS_DEVIDR_DMA__Msk (_U_(0x7F) << USBHS_DEVIDR_DMA__Pos) /**< (USBHS_DEVIDR Mask) DMA_ */ +#define USBHS_DEVIDR_DMA_(value) (USBHS_DEVIDR_DMA__Msk & ((value) << USBHS_DEVIDR_DMA__Pos)) + +/* -------- USBHS_DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUSPES:1; /**< bit: 0 Suspend Interrupt Enable */ + uint32_t MSOFES:1; /**< bit: 1 Micro Start of Frame Interrupt Enable */ + uint32_t SOFES:1; /**< bit: 2 Start of Frame Interrupt Enable */ + uint32_t EORSTES:1; /**< bit: 3 End of Reset Interrupt Enable */ + uint32_t WAKEUPES:1; /**< bit: 4 Wake-Up Interrupt Enable */ + uint32_t EORSMES:1; /**< bit: 5 End of Resume Interrupt Enable */ + uint32_t UPRSMES:1; /**< bit: 6 Upstream Resume Interrupt Enable */ + uint32_t :5; /**< bit: 7..11 Reserved */ + uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Enable */ + uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Enable */ + uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Enable */ + uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Enable */ + uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Enable */ + uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Enable */ + uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Enable */ + uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Enable */ + uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Enable */ + uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Enable */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Enable */ + uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Enable */ + uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Enable */ + uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Enable */ + uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Enable */ + uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Enable */ + uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :12; /**< bit: 0..11 Reserved */ + uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Enable */ + uint32_t :3; /**< bit: 22..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVIER_OFFSET (0x18) /**< (USBHS_DEVIER) Device Global Interrupt Enable Register Offset */ + +#define USBHS_DEVIER_SUSPES_Pos 0 /**< (USBHS_DEVIER) Suspend Interrupt Enable Position */ +#define USBHS_DEVIER_SUSPES_Msk (_U_(0x1) << USBHS_DEVIER_SUSPES_Pos) /**< (USBHS_DEVIER) Suspend Interrupt Enable Mask */ +#define USBHS_DEVIER_SUSPES USBHS_DEVIER_SUSPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_SUSPES_Msk instead */ +#define USBHS_DEVIER_MSOFES_Pos 1 /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_MSOFES_Msk (_U_(0x1) << USBHS_DEVIER_MSOFES_Pos) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_MSOFES USBHS_DEVIER_MSOFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_MSOFES_Msk instead */ +#define USBHS_DEVIER_SOFES_Pos 2 /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_SOFES_Msk (_U_(0x1) << USBHS_DEVIER_SOFES_Pos) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_SOFES USBHS_DEVIER_SOFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_SOFES_Msk instead */ +#define USBHS_DEVIER_EORSTES_Pos 3 /**< (USBHS_DEVIER) End of Reset Interrupt Enable Position */ +#define USBHS_DEVIER_EORSTES_Msk (_U_(0x1) << USBHS_DEVIER_EORSTES_Pos) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSTES USBHS_DEVIER_EORSTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_EORSTES_Msk instead */ +#define USBHS_DEVIER_WAKEUPES_Pos 4 /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Position */ +#define USBHS_DEVIER_WAKEUPES_Msk (_U_(0x1) << USBHS_DEVIER_WAKEUPES_Pos) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Mask */ +#define USBHS_DEVIER_WAKEUPES USBHS_DEVIER_WAKEUPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_WAKEUPES_Msk instead */ +#define USBHS_DEVIER_EORSMES_Pos 5 /**< (USBHS_DEVIER) End of Resume Interrupt Enable Position */ +#define USBHS_DEVIER_EORSMES_Msk (_U_(0x1) << USBHS_DEVIER_EORSMES_Pos) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSMES USBHS_DEVIER_EORSMES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_EORSMES_Msk instead */ +#define USBHS_DEVIER_UPRSMES_Pos 6 /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Position */ +#define USBHS_DEVIER_UPRSMES_Msk (_U_(0x1) << USBHS_DEVIER_UPRSMES_Pos) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_UPRSMES USBHS_DEVIER_UPRSMES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_UPRSMES_Msk instead */ +#define USBHS_DEVIER_PEP_0_Pos 12 /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_0_Msk (_U_(0x1) << USBHS_DEVIER_PEP_0_Pos) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_0 USBHS_DEVIER_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_0_Msk instead */ +#define USBHS_DEVIER_PEP_1_Pos 13 /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_1_Msk (_U_(0x1) << USBHS_DEVIER_PEP_1_Pos) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_1 USBHS_DEVIER_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_1_Msk instead */ +#define USBHS_DEVIER_PEP_2_Pos 14 /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_2_Msk (_U_(0x1) << USBHS_DEVIER_PEP_2_Pos) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_2 USBHS_DEVIER_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_2_Msk instead */ +#define USBHS_DEVIER_PEP_3_Pos 15 /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_3_Msk (_U_(0x1) << USBHS_DEVIER_PEP_3_Pos) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_3 USBHS_DEVIER_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_3_Msk instead */ +#define USBHS_DEVIER_PEP_4_Pos 16 /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_4_Msk (_U_(0x1) << USBHS_DEVIER_PEP_4_Pos) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_4 USBHS_DEVIER_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_4_Msk instead */ +#define USBHS_DEVIER_PEP_5_Pos 17 /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_5_Msk (_U_(0x1) << USBHS_DEVIER_PEP_5_Pos) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_5 USBHS_DEVIER_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_5_Msk instead */ +#define USBHS_DEVIER_PEP_6_Pos 18 /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_6_Msk (_U_(0x1) << USBHS_DEVIER_PEP_6_Pos) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_6 USBHS_DEVIER_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_6_Msk instead */ +#define USBHS_DEVIER_PEP_7_Pos 19 /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_7_Msk (_U_(0x1) << USBHS_DEVIER_PEP_7_Pos) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_7 USBHS_DEVIER_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_7_Msk instead */ +#define USBHS_DEVIER_PEP_8_Pos 20 /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_8_Msk (_U_(0x1) << USBHS_DEVIER_PEP_8_Pos) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_8 USBHS_DEVIER_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_8_Msk instead */ +#define USBHS_DEVIER_PEP_9_Pos 21 /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_9_Msk (_U_(0x1) << USBHS_DEVIER_PEP_9_Pos) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_9 USBHS_DEVIER_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_9_Msk instead */ +#define USBHS_DEVIER_DMA_1_Pos 25 /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_1_Msk (_U_(0x1) << USBHS_DEVIER_DMA_1_Pos) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_1 USBHS_DEVIER_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_1_Msk instead */ +#define USBHS_DEVIER_DMA_2_Pos 26 /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_2_Msk (_U_(0x1) << USBHS_DEVIER_DMA_2_Pos) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_2 USBHS_DEVIER_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_2_Msk instead */ +#define USBHS_DEVIER_DMA_3_Pos 27 /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_3_Msk (_U_(0x1) << USBHS_DEVIER_DMA_3_Pos) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_3 USBHS_DEVIER_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_3_Msk instead */ +#define USBHS_DEVIER_DMA_4_Pos 28 /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_4_Msk (_U_(0x1) << USBHS_DEVIER_DMA_4_Pos) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_4 USBHS_DEVIER_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_4_Msk instead */ +#define USBHS_DEVIER_DMA_5_Pos 29 /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_5_Msk (_U_(0x1) << USBHS_DEVIER_DMA_5_Pos) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_5 USBHS_DEVIER_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_5_Msk instead */ +#define USBHS_DEVIER_DMA_6_Pos 30 /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_6_Msk (_U_(0x1) << USBHS_DEVIER_DMA_6_Pos) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_6 USBHS_DEVIER_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_6_Msk instead */ +#define USBHS_DEVIER_DMA_7_Pos 31 /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_7_Msk (_U_(0x1) << USBHS_DEVIER_DMA_7_Pos) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_7 USBHS_DEVIER_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_7_Msk instead */ +#define USBHS_DEVIER_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIER) Register MASK (Use USBHS_DEVIER_Msk instead) */ +#define USBHS_DEVIER_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIER) Register Mask */ + +#define USBHS_DEVIER_PEP__Pos 12 /**< (USBHS_DEVIER Position) Endpoint x Interrupt Enable */ +#define USBHS_DEVIER_PEP__Msk (_U_(0x3FF) << USBHS_DEVIER_PEP__Pos) /**< (USBHS_DEVIER Mask) PEP_ */ +#define USBHS_DEVIER_PEP_(value) (USBHS_DEVIER_PEP__Msk & ((value) << USBHS_DEVIER_PEP__Pos)) +#define USBHS_DEVIER_DMA__Pos 25 /**< (USBHS_DEVIER Position) DMA Channel 7 Interrupt Enable */ +#define USBHS_DEVIER_DMA__Msk (_U_(0x7F) << USBHS_DEVIER_DMA__Pos) /**< (USBHS_DEVIER Mask) DMA_ */ +#define USBHS_DEVIER_DMA_(value) (USBHS_DEVIER_DMA__Msk & ((value) << USBHS_DEVIER_DMA__Pos)) + +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EPEN0:1; /**< bit: 0 Endpoint 0 Enable */ + uint32_t EPEN1:1; /**< bit: 1 Endpoint 1 Enable */ + uint32_t EPEN2:1; /**< bit: 2 Endpoint 2 Enable */ + uint32_t EPEN3:1; /**< bit: 3 Endpoint 3 Enable */ + uint32_t EPEN4:1; /**< bit: 4 Endpoint 4 Enable */ + uint32_t EPEN5:1; /**< bit: 5 Endpoint 5 Enable */ + uint32_t EPEN6:1; /**< bit: 6 Endpoint 6 Enable */ + uint32_t EPEN7:1; /**< bit: 7 Endpoint 7 Enable */ + uint32_t EPEN8:1; /**< bit: 8 Endpoint 8 Enable */ + uint32_t EPEN9:1; /**< bit: 9 Endpoint 9 Enable */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t EPRST0:1; /**< bit: 16 Endpoint 0 Reset */ + uint32_t EPRST1:1; /**< bit: 17 Endpoint 1 Reset */ + uint32_t EPRST2:1; /**< bit: 18 Endpoint 2 Reset */ + uint32_t EPRST3:1; /**< bit: 19 Endpoint 3 Reset */ + uint32_t EPRST4:1; /**< bit: 20 Endpoint 4 Reset */ + uint32_t EPRST5:1; /**< bit: 21 Endpoint 5 Reset */ + uint32_t EPRST6:1; /**< bit: 22 Endpoint 6 Reset */ + uint32_t EPRST7:1; /**< bit: 23 Endpoint 7 Reset */ + uint32_t EPRST8:1; /**< bit: 24 Endpoint 8 Reset */ + uint32_t EPRST9:1; /**< bit: 25 Endpoint 9 Reset */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EPEN:10; /**< bit: 0..9 Endpoint x Enable */ + uint32_t :6; /**< bit: 10..15 Reserved */ + uint32_t EPRST:10; /**< bit: 16..25 Endpoint 9 Reset */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPT_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPT_OFFSET (0x1C) /**< (USBHS_DEVEPT) Device Endpoint Register Offset */ + +#define USBHS_DEVEPT_EPEN0_Pos 0 /**< (USBHS_DEVEPT) Endpoint 0 Enable Position */ +#define USBHS_DEVEPT_EPEN0_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Enable Mask */ +#define USBHS_DEVEPT_EPEN0 USBHS_DEVEPT_EPEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN0_Msk instead */ +#define USBHS_DEVEPT_EPEN1_Pos 1 /**< (USBHS_DEVEPT) Endpoint 1 Enable Position */ +#define USBHS_DEVEPT_EPEN1_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Enable Mask */ +#define USBHS_DEVEPT_EPEN1 USBHS_DEVEPT_EPEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN1_Msk instead */ +#define USBHS_DEVEPT_EPEN2_Pos 2 /**< (USBHS_DEVEPT) Endpoint 2 Enable Position */ +#define USBHS_DEVEPT_EPEN2_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Enable Mask */ +#define USBHS_DEVEPT_EPEN2 USBHS_DEVEPT_EPEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN2_Msk instead */ +#define USBHS_DEVEPT_EPEN3_Pos 3 /**< (USBHS_DEVEPT) Endpoint 3 Enable Position */ +#define USBHS_DEVEPT_EPEN3_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Enable Mask */ +#define USBHS_DEVEPT_EPEN3 USBHS_DEVEPT_EPEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN3_Msk instead */ +#define USBHS_DEVEPT_EPEN4_Pos 4 /**< (USBHS_DEVEPT) Endpoint 4 Enable Position */ +#define USBHS_DEVEPT_EPEN4_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Enable Mask */ +#define USBHS_DEVEPT_EPEN4 USBHS_DEVEPT_EPEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN4_Msk instead */ +#define USBHS_DEVEPT_EPEN5_Pos 5 /**< (USBHS_DEVEPT) Endpoint 5 Enable Position */ +#define USBHS_DEVEPT_EPEN5_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Enable Mask */ +#define USBHS_DEVEPT_EPEN5 USBHS_DEVEPT_EPEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN5_Msk instead */ +#define USBHS_DEVEPT_EPEN6_Pos 6 /**< (USBHS_DEVEPT) Endpoint 6 Enable Position */ +#define USBHS_DEVEPT_EPEN6_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Enable Mask */ +#define USBHS_DEVEPT_EPEN6 USBHS_DEVEPT_EPEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN6_Msk instead */ +#define USBHS_DEVEPT_EPEN7_Pos 7 /**< (USBHS_DEVEPT) Endpoint 7 Enable Position */ +#define USBHS_DEVEPT_EPEN7_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Enable Mask */ +#define USBHS_DEVEPT_EPEN7 USBHS_DEVEPT_EPEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN7_Msk instead */ +#define USBHS_DEVEPT_EPEN8_Pos 8 /**< (USBHS_DEVEPT) Endpoint 8 Enable Position */ +#define USBHS_DEVEPT_EPEN8_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Enable Mask */ +#define USBHS_DEVEPT_EPEN8 USBHS_DEVEPT_EPEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN8_Msk instead */ +#define USBHS_DEVEPT_EPEN9_Pos 9 /**< (USBHS_DEVEPT) Endpoint 9 Enable Position */ +#define USBHS_DEVEPT_EPEN9_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Enable Mask */ +#define USBHS_DEVEPT_EPEN9 USBHS_DEVEPT_EPEN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN9_Msk instead */ +#define USBHS_DEVEPT_EPRST0_Pos 16 /**< (USBHS_DEVEPT) Endpoint 0 Reset Position */ +#define USBHS_DEVEPT_EPRST0_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Reset Mask */ +#define USBHS_DEVEPT_EPRST0 USBHS_DEVEPT_EPRST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST0_Msk instead */ +#define USBHS_DEVEPT_EPRST1_Pos 17 /**< (USBHS_DEVEPT) Endpoint 1 Reset Position */ +#define USBHS_DEVEPT_EPRST1_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Reset Mask */ +#define USBHS_DEVEPT_EPRST1 USBHS_DEVEPT_EPRST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST1_Msk instead */ +#define USBHS_DEVEPT_EPRST2_Pos 18 /**< (USBHS_DEVEPT) Endpoint 2 Reset Position */ +#define USBHS_DEVEPT_EPRST2_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Reset Mask */ +#define USBHS_DEVEPT_EPRST2 USBHS_DEVEPT_EPRST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST2_Msk instead */ +#define USBHS_DEVEPT_EPRST3_Pos 19 /**< (USBHS_DEVEPT) Endpoint 3 Reset Position */ +#define USBHS_DEVEPT_EPRST3_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Reset Mask */ +#define USBHS_DEVEPT_EPRST3 USBHS_DEVEPT_EPRST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST3_Msk instead */ +#define USBHS_DEVEPT_EPRST4_Pos 20 /**< (USBHS_DEVEPT) Endpoint 4 Reset Position */ +#define USBHS_DEVEPT_EPRST4_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Reset Mask */ +#define USBHS_DEVEPT_EPRST4 USBHS_DEVEPT_EPRST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST4_Msk instead */ +#define USBHS_DEVEPT_EPRST5_Pos 21 /**< (USBHS_DEVEPT) Endpoint 5 Reset Position */ +#define USBHS_DEVEPT_EPRST5_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Reset Mask */ +#define USBHS_DEVEPT_EPRST5 USBHS_DEVEPT_EPRST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST5_Msk instead */ +#define USBHS_DEVEPT_EPRST6_Pos 22 /**< (USBHS_DEVEPT) Endpoint 6 Reset Position */ +#define USBHS_DEVEPT_EPRST6_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Reset Mask */ +#define USBHS_DEVEPT_EPRST6 USBHS_DEVEPT_EPRST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST6_Msk instead */ +#define USBHS_DEVEPT_EPRST7_Pos 23 /**< (USBHS_DEVEPT) Endpoint 7 Reset Position */ +#define USBHS_DEVEPT_EPRST7_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Reset Mask */ +#define USBHS_DEVEPT_EPRST7 USBHS_DEVEPT_EPRST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST7_Msk instead */ +#define USBHS_DEVEPT_EPRST8_Pos 24 /**< (USBHS_DEVEPT) Endpoint 8 Reset Position */ +#define USBHS_DEVEPT_EPRST8_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Reset Mask */ +#define USBHS_DEVEPT_EPRST8 USBHS_DEVEPT_EPRST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST8_Msk instead */ +#define USBHS_DEVEPT_EPRST9_Pos 25 /**< (USBHS_DEVEPT) Endpoint 9 Reset Position */ +#define USBHS_DEVEPT_EPRST9_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Reset Mask */ +#define USBHS_DEVEPT_EPRST9 USBHS_DEVEPT_EPRST9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST9_Msk instead */ +#define USBHS_DEVEPT_MASK _U_(0x3FF03FF) /**< \deprecated (USBHS_DEVEPT) Register MASK (Use USBHS_DEVEPT_Msk instead) */ +#define USBHS_DEVEPT_Msk _U_(0x3FF03FF) /**< (USBHS_DEVEPT) Register Mask */ + +#define USBHS_DEVEPT_EPEN_Pos 0 /**< (USBHS_DEVEPT Position) Endpoint x Enable */ +#define USBHS_DEVEPT_EPEN_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPEN_Pos) /**< (USBHS_DEVEPT Mask) EPEN */ +#define USBHS_DEVEPT_EPEN(value) (USBHS_DEVEPT_EPEN_Msk & ((value) << USBHS_DEVEPT_EPEN_Pos)) +#define USBHS_DEVEPT_EPRST_Pos 16 /**< (USBHS_DEVEPT Position) Endpoint 9 Reset */ +#define USBHS_DEVEPT_EPRST_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPRST_Pos) /**< (USBHS_DEVEPT Mask) EPRST */ +#define USBHS_DEVEPT_EPRST(value) (USBHS_DEVEPT_EPRST_Msk & ((value) << USBHS_DEVEPT_EPRST_Pos)) + +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFNUM:3; /**< bit: 0..2 Micro Frame Number */ + uint32_t FNUM:11; /**< bit: 3..13 Frame Number */ + uint32_t :1; /**< bit: 14 Reserved */ + uint32_t FNCERR:1; /**< bit: 15 Frame Number CRC Error */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVFNUM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVFNUM_OFFSET (0x20) /**< (USBHS_DEVFNUM) Device Frame Number Register Offset */ + +#define USBHS_DEVFNUM_MFNUM_Pos 0 /**< (USBHS_DEVFNUM) Micro Frame Number Position */ +#define USBHS_DEVFNUM_MFNUM_Msk (_U_(0x7) << USBHS_DEVFNUM_MFNUM_Pos) /**< (USBHS_DEVFNUM) Micro Frame Number Mask */ +#define USBHS_DEVFNUM_MFNUM(value) (USBHS_DEVFNUM_MFNUM_Msk & ((value) << USBHS_DEVFNUM_MFNUM_Pos)) +#define USBHS_DEVFNUM_FNUM_Pos 3 /**< (USBHS_DEVFNUM) Frame Number Position */ +#define USBHS_DEVFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_DEVFNUM_FNUM_Pos) /**< (USBHS_DEVFNUM) Frame Number Mask */ +#define USBHS_DEVFNUM_FNUM(value) (USBHS_DEVFNUM_FNUM_Msk & ((value) << USBHS_DEVFNUM_FNUM_Pos)) +#define USBHS_DEVFNUM_FNCERR_Pos 15 /**< (USBHS_DEVFNUM) Frame Number CRC Error Position */ +#define USBHS_DEVFNUM_FNCERR_Msk (_U_(0x1) << USBHS_DEVFNUM_FNCERR_Pos) /**< (USBHS_DEVFNUM) Frame Number CRC Error Mask */ +#define USBHS_DEVFNUM_FNCERR USBHS_DEVFNUM_FNCERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVFNUM_FNCERR_Msk instead */ +#define USBHS_DEVFNUM_MASK _U_(0xBFFF) /**< \deprecated (USBHS_DEVFNUM) Register MASK (Use USBHS_DEVFNUM_Msk instead) */ +#define USBHS_DEVFNUM_Msk _U_(0xBFFF) /**< (USBHS_DEVFNUM) Register Mask */ + + +/* -------- USBHS_DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t ALLOC:1; /**< bit: 1 Endpoint Memory Allocate */ + uint32_t EPBK:2; /**< bit: 2..3 Endpoint Banks */ + uint32_t EPSIZE:3; /**< bit: 4..6 Endpoint Size */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t EPDIR:1; /**< bit: 8 Endpoint Direction */ + uint32_t AUTOSW:1; /**< bit: 9 Automatic Switch */ + uint32_t :1; /**< bit: 10 Reserved */ + uint32_t EPTYPE:2; /**< bit: 11..12 Endpoint Type */ + uint32_t NBTRANS:2; /**< bit: 13..14 Number of transactions per microframe for isochronous endpoint */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTCFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTCFG_OFFSET (0x100) /**< (USBHS_DEVEPTCFG) Device Endpoint Configuration Register Offset */ + +#define USBHS_DEVEPTCFG_ALLOC_Pos 1 /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Position */ +#define USBHS_DEVEPTCFG_ALLOC_Msk (_U_(0x1) << USBHS_DEVEPTCFG_ALLOC_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Mask */ +#define USBHS_DEVEPTCFG_ALLOC USBHS_DEVEPTCFG_ALLOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_ALLOC_Msk instead */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 /**< (USBHS_DEVEPTCFG) Endpoint Banks Position */ +#define USBHS_DEVEPTCFG_EPBK_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Banks Mask */ +#define USBHS_DEVEPTCFG_EPBK(value) (USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)) +#define USBHS_DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_1_BANK (USBHS_DEVEPTCFG_EPBK_1_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Single-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (USBHS_DEVEPTCFG_EPBK_2_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Double-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (USBHS_DEVEPTCFG_EPBK_3_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 /**< (USBHS_DEVEPTCFG) Endpoint Size Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Msk (_U_(0x7) << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Size Mask */ +#define USBHS_DEVEPTCFG_EPSIZE(value) (USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_DEVEPTCFG) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_DEVEPTCFG) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_DEVEPTCFG) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_DEVEPTCFG) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 8 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 16 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 32 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 64 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 128 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 256 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 512 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 1024 bytes Position */ +#define USBHS_DEVEPTCFG_EPDIR_Pos 8 /**< (USBHS_DEVEPTCFG) Endpoint Direction Position */ +#define USBHS_DEVEPTCFG_EPDIR_Msk (_U_(0x1) << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Direction Mask */ +#define USBHS_DEVEPTCFG_EPDIR USBHS_DEVEPTCFG_EPDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_EPDIR_Msk instead */ +#define USBHS_DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (USBHS_DEVEPTCFG_EPDIR_OUT_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. Position */ +#define USBHS_DEVEPTCFG_EPDIR_IN (USBHS_DEVEPTCFG_EPDIR_IN_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Pos 9 /**< (USBHS_DEVEPTCFG) Automatic Switch Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Msk (_U_(0x1) << USBHS_DEVEPTCFG_AUTOSW_Pos) /**< (USBHS_DEVEPTCFG) Automatic Switch Mask */ +#define USBHS_DEVEPTCFG_AUTOSW USBHS_DEVEPTCFG_AUTOSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_AUTOSW_Msk instead */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 /**< (USBHS_DEVEPTCFG) Endpoint Type Position */ +#define USBHS_DEVEPTCFG_EPTYPE_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Type Mask */ +#define USBHS_DEVEPTCFG_EPTYPE(value) (USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Interrupt */ +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (USBHS_DEVEPTCFG_EPTYPE_CTRL_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Control Position */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (USBHS_DEVEPTCFG_EPTYPE_ISO_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Isochronous Position */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (USBHS_DEVEPTCFG_EPTYPE_BLK_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Bulk Position */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Interrupt Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Msk (_U_(0x3) << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ +#define USBHS_DEVEPTCFG_NBTRANS(value) (USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ +#define USBHS_DEVEPTCFG_MASK _U_(0x7B7E) /**< \deprecated (USBHS_DEVEPTCFG) Register MASK (Use USBHS_DEVEPTCFG_Msk instead) */ +#define USBHS_DEVEPTCFG_Msk _U_(0x7B7E) /**< (USBHS_DEVEPTCFG) Register Mask */ + + +/* -------- USBHS_DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINI:1; /**< bit: 0 Transmitted IN Data Interrupt */ + uint32_t RXOUTI:1; /**< bit: 1 Received OUT Data Interrupt */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFI:1; /**< bit: 5 Overflow Interrupt */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKET:1; /**< bit: 7 Short Packet Interrupt */ + uint32_t DTSEQ:2; /**< bit: 8..9 Data Toggle Sequence */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t NBUSYBK:2; /**< bit: 12..13 Number of Busy Banks */ + uint32_t CURRBK:2; /**< bit: 14..15 Current Bank */ + uint32_t RWALL:1; /**< bit: 16 Read/Write Allowed */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t CFGOK:1; /**< bit: 18 Configuration OK Status */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t BYCT:11; /**< bit: 20..30 Byte Count */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ + uint32_t HBISOINERRI:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt */ + uint32_t HBISOFLUSHI:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t CRCERRI:1; /**< bit: 6 CRC Error Interrupt */ + uint32_t :3; /**< bit: 7..9 Reserved */ + uint32_t ERRORTRANS:1; /**< bit: 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTISR_OFFSET (0x130) /**< (USBHS_DEVEPTISR) Device Endpoint Interrupt Status Register Offset */ + +#define USBHS_DEVEPTISR_TXINI_Pos 0 /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTISR_TXINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_TXINI_Pos) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTISR_TXINI USBHS_DEVEPTISR_TXINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_TXINI_Msk instead */ +#define USBHS_DEVEPTISR_RXOUTI_Pos 1 /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTISR_RXOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_RXOUTI_Pos) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTISR_RXOUTI USBHS_DEVEPTISR_RXOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_RXOUTI_Msk instead */ +#define USBHS_DEVEPTISR_OVERFI_Pos 5 /**< (USBHS_DEVEPTISR) Overflow Interrupt Position */ +#define USBHS_DEVEPTISR_OVERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_OVERFI_Pos) /**< (USBHS_DEVEPTISR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTISR_OVERFI USBHS_DEVEPTISR_OVERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_OVERFI_Msk instead */ +#define USBHS_DEVEPTISR_SHORTPACKET_Pos 7 /**< (USBHS_DEVEPTISR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTISR_SHORTPACKET_Msk (_U_(0x1) << USBHS_DEVEPTISR_SHORTPACKET_Pos) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTISR_SHORTPACKET USBHS_DEVEPTISR_SHORTPACKET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_SHORTPACKET_Msk instead */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 /**< (USBHS_DEVEPTISR) Data Toggle Sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_Msk (_U_(0x3) << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Mask */ +#define USBHS_DEVEPTISR_DTSEQ(value) (USBHS_DEVEPTISR_DTSEQ_Msk & ((value) << USBHS_DEVEPTISR_DTSEQ_Pos)) +#define USBHS_DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (USBHS_DEVEPTISR_DTSEQ_DATA0_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data0 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (USBHS_DEVEPTISR_DTSEQ_DATA1_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data1 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (USBHS_DEVEPTISR_DTSEQ_DATA2_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (USBHS_DEVEPTISR_DTSEQ_MDATA_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 /**< (USBHS_DEVEPTISR) Number of Busy Banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) Number of Busy Banks Mask */ +#define USBHS_DEVEPTISR_NBUSYBK(value) (USBHS_DEVEPTISR_NBUSYBK_Msk & ((value) << USBHS_DEVEPTISR_NBUSYBK_Pos)) +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_DEVEPTISR) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_DEVEPTISR) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_DEVEPTISR) 3 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) Position */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 1 busy bank Position */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 2 busy banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 3 busy banks Position */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 /**< (USBHS_DEVEPTISR) Current Bank Position */ +#define USBHS_DEVEPTISR_CURRBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current Bank Mask */ +#define USBHS_DEVEPTISR_CURRBK(value) (USBHS_DEVEPTISR_CURRBK_Msk & ((value) << USBHS_DEVEPTISR_CURRBK_Pos)) +#define USBHS_DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Current bank is bank2 */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (USBHS_DEVEPTISR_CURRBK_BANK0_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank0 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (USBHS_DEVEPTISR_CURRBK_BANK1_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank1 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (USBHS_DEVEPTISR_CURRBK_BANK2_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank2 Position */ +#define USBHS_DEVEPTISR_RWALL_Pos 16 /**< (USBHS_DEVEPTISR) Read/Write Allowed Position */ +#define USBHS_DEVEPTISR_RWALL_Msk (_U_(0x1) << USBHS_DEVEPTISR_RWALL_Pos) /**< (USBHS_DEVEPTISR) Read/Write Allowed Mask */ +#define USBHS_DEVEPTISR_RWALL USBHS_DEVEPTISR_RWALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_RWALL_Msk instead */ +#define USBHS_DEVEPTISR_CFGOK_Pos 18 /**< (USBHS_DEVEPTISR) Configuration OK Status Position */ +#define USBHS_DEVEPTISR_CFGOK_Msk (_U_(0x1) << USBHS_DEVEPTISR_CFGOK_Pos) /**< (USBHS_DEVEPTISR) Configuration OK Status Mask */ +#define USBHS_DEVEPTISR_CFGOK USBHS_DEVEPTISR_CFGOK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CFGOK_Msk instead */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 /**< (USBHS_DEVEPTISR) Byte Count Position */ +#define USBHS_DEVEPTISR_BYCT_Msk (_U_(0x7FF) << USBHS_DEVEPTISR_BYCT_Pos) /**< (USBHS_DEVEPTISR) Byte Count Mask */ +#define USBHS_DEVEPTISR_BYCT(value) (USBHS_DEVEPTISR_BYCT_Msk & ((value) << USBHS_DEVEPTISR_BYCT_Pos)) +#define USBHS_DEVEPTISR_MASK _U_(0x7FF5F3A3) /**< \deprecated (USBHS_DEVEPTISR) Register MASK (Use USBHS_DEVEPTISR_Msk instead) */ +#define USBHS_DEVEPTISR_Msk _U_(0x7FF5F3A3) /**< (USBHS_DEVEPTISR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI USBHS_DEVEPTISR_CTRL_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_RXSTPI_Msk instead */ +#define USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_NAKOUTI USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk instead */ +#define USBHS_DEVEPTISR_CTRL_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_NAKINI USBHS_DEVEPTISR_CTRL_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_NAKINI_Msk instead */ +#define USBHS_DEVEPTISR_CTRL_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_STALLEDI USBHS_DEVEPTISR_CTRL_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_STALLEDI_Msk instead */ +#define USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_CTRL_CTRLDIR USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk instead */ +#define USBHS_DEVEPTISR_CTRL_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_CTRL) Register MASK (Use USBHS_DEVEPTISR_CTRL_Msk instead) */ +#define USBHS_DEVEPTISR_CTRL_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTISR_ISO_UNDERFI_Pos 2 /**< (USBHS_DEVEPTISR) Underflow Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_UNDERFI_Pos) /**< (USBHS_DEVEPTISR) Underflow Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_UNDERFI USBHS_DEVEPTISR_ISO_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_UNDERFI_Msk instead */ +#define USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos 3 /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_HBISOINERRI USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk instead */ +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos 4 /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk instead */ +#define USBHS_DEVEPTISR_ISO_CRCERRI_Pos 6 /**< (USBHS_DEVEPTISR) CRC Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_CRCERRI_Pos) /**< (USBHS_DEVEPTISR) CRC Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_CRCERRI USBHS_DEVEPTISR_ISO_CRCERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_CRCERRI_Msk instead */ +#define USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos 10 /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos) /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_ERRORTRANS USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk instead */ +#define USBHS_DEVEPTISR_ISO_MASK _U_(0x45C) /**< \deprecated (USBHS_DEVEPTISR_ISO) Register MASK (Use USBHS_DEVEPTISR_ISO_Msk instead) */ +#define USBHS_DEVEPTISR_ISO_Msk _U_(0x45C) /**< (USBHS_DEVEPTISR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTISR_BLK_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_RXSTPI USBHS_DEVEPTISR_BLK_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_RXSTPI_Msk instead */ +#define USBHS_DEVEPTISR_BLK_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_NAKOUTI USBHS_DEVEPTISR_BLK_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_NAKOUTI_Msk instead */ +#define USBHS_DEVEPTISR_BLK_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_NAKINI USBHS_DEVEPTISR_BLK_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_NAKINI_Msk instead */ +#define USBHS_DEVEPTISR_BLK_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_STALLEDI USBHS_DEVEPTISR_BLK_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_STALLEDI_Msk instead */ +#define USBHS_DEVEPTISR_BLK_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_BLK_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_BLK_CTRLDIR USBHS_DEVEPTISR_BLK_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_CTRLDIR_Msk instead */ +#define USBHS_DEVEPTISR_BLK_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_BLK) Register MASK (Use USBHS_DEVEPTISR_BLK_Msk instead) */ +#define USBHS_DEVEPTISR_BLK_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk instead */ +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk instead */ +#define USBHS_DEVEPTISR_INTRPT_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_NAKINI USBHS_DEVEPTISR_INTRPT_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_NAKINI_Msk instead */ +#define USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_STALLEDI USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk instead */ +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk instead */ +#define USBHS_DEVEPTISR_INTRPT_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_INTRPT) Register MASK (Use USBHS_DEVEPTISR_INTRPT_Msk instead) */ +#define USBHS_DEVEPTISR_INTRPT_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINIC:1; /**< bit: 0 Transmitted IN Data Interrupt Clear */ + uint32_t RXOUTIC:1; /**< bit: 1 Received OUT Data Interrupt Clear */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFIC:1; /**< bit: 5 Overflow Interrupt Clear */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETC:1; /**< bit: 7 Short Packet Interrupt Clear */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ + uint32_t HBISOINERRIC:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ + uint32_t HBISOFLUSHIC:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t CRCERRIC:1; /**< bit: 6 CRC Error Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTICR_OFFSET (0x160) /**< (USBHS_DEVEPTICR) Device Endpoint Interrupt Clear Register Offset */ + +#define USBHS_DEVEPTICR_TXINIC_Pos 0 /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_TXINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_TXINIC_Pos) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_TXINIC USBHS_DEVEPTICR_TXINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_TXINIC_Msk instead */ +#define USBHS_DEVEPTICR_RXOUTIC_Pos 1 /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_RXOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_RXOUTIC_Pos) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_RXOUTIC USBHS_DEVEPTICR_RXOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_RXOUTIC_Msk instead */ +#define USBHS_DEVEPTICR_OVERFIC_Pos 5 /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTICR_OVERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_OVERFIC_Pos) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_OVERFIC USBHS_DEVEPTICR_OVERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_OVERFIC_Msk instead */ +#define USBHS_DEVEPTICR_SHORTPACKETC_Pos 7 /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Position */ +#define USBHS_DEVEPTICR_SHORTPACKETC_Msk (_U_(0x1) << USBHS_DEVEPTICR_SHORTPACKETC_Pos) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_SHORTPACKETC USBHS_DEVEPTICR_SHORTPACKETC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_SHORTPACKETC_Msk instead */ +#define USBHS_DEVEPTICR_MASK _U_(0xA3) /**< \deprecated (USBHS_DEVEPTICR) Register MASK (Use USBHS_DEVEPTICR_Msk instead) */ +#define USBHS_DEVEPTICR_Msk _U_(0xA3) /**< (USBHS_DEVEPTICR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk instead */ +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk instead */ +#define USBHS_DEVEPTICR_CTRL_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_NAKINIC USBHS_DEVEPTICR_CTRL_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_NAKINIC_Msk instead */ +#define USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_STALLEDIC USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk instead */ +#define USBHS_DEVEPTICR_CTRL_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_CTRL) Register MASK (Use USBHS_DEVEPTICR_CTRL_Msk instead) */ +#define USBHS_DEVEPTICR_CTRL_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC_Pos 2 /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_UNDERFIC_Pos) /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC USBHS_DEVEPTICR_ISO_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_UNDERFIC_Msk instead */ +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos 3 /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk instead */ +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4 /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk instead */ +#define USBHS_DEVEPTICR_ISO_CRCERRIC_Pos 6 /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_CRCERRIC_Pos) /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_CRCERRIC USBHS_DEVEPTICR_ISO_CRCERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_CRCERRIC_Msk instead */ +#define USBHS_DEVEPTICR_ISO_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_ISO) Register MASK (Use USBHS_DEVEPTICR_ISO_Msk instead) */ +#define USBHS_DEVEPTICR_ISO_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC USBHS_DEVEPTICR_BLK_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_RXSTPIC_Msk instead */ +#define USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_NAKOUTIC USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk instead */ +#define USBHS_DEVEPTICR_BLK_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_NAKINIC USBHS_DEVEPTICR_BLK_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_NAKINIC_Msk instead */ +#define USBHS_DEVEPTICR_BLK_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_STALLEDIC USBHS_DEVEPTICR_BLK_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_STALLEDIC_Msk instead */ +#define USBHS_DEVEPTICR_BLK_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_BLK) Register MASK (Use USBHS_DEVEPTICR_BLK_Msk instead) */ +#define USBHS_DEVEPTICR_BLK_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk instead */ +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk instead */ +#define USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_NAKINIC USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk instead */ +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk instead */ +#define USBHS_DEVEPTICR_INTRPT_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_INTRPT) Register MASK (Use USBHS_DEVEPTICR_INTRPT_Msk instead) */ +#define USBHS_DEVEPTICR_INTRPT_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINIS:1; /**< bit: 0 Transmitted IN Data Interrupt Set */ + uint32_t RXOUTIS:1; /**< bit: 1 Received OUT Data Interrupt Set */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFIS:1; /**< bit: 5 Overflow Interrupt Set */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETS:1; /**< bit: 7 Short Packet Interrupt Set */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKS:1; /**< bit: 12 Number of Busy Banks Interrupt Set */ + uint32_t :19; /**< bit: 13..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ + uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ + uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ + uint32_t HBISOINERRIS:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set */ + uint32_t HBISOFLUSHIS:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Set */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t CRCERRIS:1; /**< bit: 6 CRC Error Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ + uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ + uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ + uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ + uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTIFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTIFR_OFFSET (0x190) /**< (USBHS_DEVEPTIFR) Device Endpoint Interrupt Set Register Offset */ + +#define USBHS_DEVEPTIFR_TXINIS_Pos 0 /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_TXINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_TXINIS_Pos) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_TXINIS USBHS_DEVEPTIFR_TXINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_TXINIS_Msk instead */ +#define USBHS_DEVEPTIFR_RXOUTIS_Pos 1 /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_RXOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_RXOUTIS_Pos) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_RXOUTIS USBHS_DEVEPTIFR_RXOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_RXOUTIS_Msk instead */ +#define USBHS_DEVEPTIFR_OVERFIS_Pos 5 /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Position */ +#define USBHS_DEVEPTIFR_OVERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_OVERFIS_Pos) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_OVERFIS USBHS_DEVEPTIFR_OVERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_OVERFIS_Msk instead */ +#define USBHS_DEVEPTIFR_SHORTPACKETS_Pos 7 /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Position */ +#define USBHS_DEVEPTIFR_SHORTPACKETS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_SHORTPACKETS USBHS_DEVEPTIFR_SHORTPACKETS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_SHORTPACKETS_Msk instead */ +#define USBHS_DEVEPTIFR_NBUSYBKS_Pos 12 /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NBUSYBKS_Pos) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NBUSYBKS USBHS_DEVEPTIFR_NBUSYBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_NBUSYBKS_Msk instead */ +#define USBHS_DEVEPTIFR_MASK _U_(0x10A3) /**< \deprecated (USBHS_DEVEPTIFR) Register MASK (Use USBHS_DEVEPTIFR_Msk instead) */ +#define USBHS_DEVEPTIFR_Msk _U_(0x10A3) /**< (USBHS_DEVEPTIFR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk instead */ +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk instead */ +#define USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_NAKINIS USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk instead */ +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk instead */ +#define USBHS_DEVEPTIFR_CTRL_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_CTRL) Register MASK (Use USBHS_DEVEPTIFR_CTRL_Msk instead) */ +#define USBHS_DEVEPTIFR_CTRL_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos 2 /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos) /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk instead */ +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos 3 /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk instead */ +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4 /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk instead */ +#define USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos 6 /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos) /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_CRCERRIS USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk instead */ +#define USBHS_DEVEPTIFR_ISO_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_ISO) Register MASK (Use USBHS_DEVEPTIFR_ISO_Msk instead) */ +#define USBHS_DEVEPTIFR_ISO_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk instead */ +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk instead */ +#define USBHS_DEVEPTIFR_BLK_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_NAKINIS USBHS_DEVEPTIFR_BLK_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_NAKINIS_Msk instead */ +#define USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_STALLEDIS USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk instead */ +#define USBHS_DEVEPTIFR_BLK_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_BLK) Register MASK (Use USBHS_DEVEPTIFR_BLK_Msk instead) */ +#define USBHS_DEVEPTIFR_BLK_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk instead */ +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk instead */ +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk instead */ +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk instead */ +#define USBHS_DEVEPTIFR_INTRPT_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_INTRPT) Register MASK (Use USBHS_DEVEPTIFR_INTRPT_Msk instead) */ +#define USBHS_DEVEPTIFR_INTRPT_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINE:1; /**< bit: 0 Transmitted IN Data Interrupt */ + uint32_t RXOUTE:1; /**< bit: 1 Received OUT Data Interrupt */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFE:1; /**< bit: 5 Overflow Interrupt */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETE:1; /**< bit: 7 Short Packet Interrupt */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKE:1; /**< bit: 12 Number of Busy Banks Interrupt */ + uint32_t KILLBK:1; /**< bit: 13 Kill IN Bank */ + uint32_t FIFOCON:1; /**< bit: 14 FIFO Control */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t EPDISHDMA:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t RSTDT:1; /**< bit: 18 Reset Data Toggle */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFE:1; /**< bit: 2 Underflow Interrupt */ + uint32_t HBISOINERRE:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt */ + uint32_t HBISOFLUSHE:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t CRCERRE:1; /**< bit: 6 CRC Error Interrupt */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MDATAE:1; /**< bit: 8 MData Interrupt */ + uint32_t DATAXE:1; /**< bit: 9 DataX Interrupt */ + uint32_t ERRORTRANSE:1; /**< bit: 10 Transaction Error Interrupt */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ + uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ + uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTIMR_OFFSET (0x1C0) /**< (USBHS_DEVEPTIMR) Device Endpoint Interrupt Mask Register Offset */ + +#define USBHS_DEVEPTIMR_TXINE_Pos 0 /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTIMR_TXINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_TXINE_Pos) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_TXINE USBHS_DEVEPTIMR_TXINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_TXINE_Msk instead */ +#define USBHS_DEVEPTIMR_RXOUTE_Pos 1 /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTIMR_RXOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RXOUTE_Pos) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_RXOUTE USBHS_DEVEPTIMR_RXOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_RXOUTE_Msk instead */ +#define USBHS_DEVEPTIMR_OVERFE_Pos 5 /**< (USBHS_DEVEPTIMR) Overflow Interrupt Position */ +#define USBHS_DEVEPTIMR_OVERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_OVERFE_Pos) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTIMR_OVERFE USBHS_DEVEPTIMR_OVERFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_OVERFE_Msk instead */ +#define USBHS_DEVEPTIMR_SHORTPACKETE_Pos 7 /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTIMR_SHORTPACKETE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTIMR_SHORTPACKETE USBHS_DEVEPTIMR_SHORTPACKETE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_SHORTPACKETE_Msk instead */ +#define USBHS_DEVEPTIMR_NBUSYBKE_Pos 12 /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Position */ +#define USBHS_DEVEPTIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NBUSYBKE_Pos) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Mask */ +#define USBHS_DEVEPTIMR_NBUSYBKE USBHS_DEVEPTIMR_NBUSYBKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_NBUSYBKE_Msk instead */ +#define USBHS_DEVEPTIMR_KILLBK_Pos 13 /**< (USBHS_DEVEPTIMR) Kill IN Bank Position */ +#define USBHS_DEVEPTIMR_KILLBK_Msk (_U_(0x1) << USBHS_DEVEPTIMR_KILLBK_Pos) /**< (USBHS_DEVEPTIMR) Kill IN Bank Mask */ +#define USBHS_DEVEPTIMR_KILLBK USBHS_DEVEPTIMR_KILLBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_KILLBK_Msk instead */ +#define USBHS_DEVEPTIMR_FIFOCON_Pos 14 /**< (USBHS_DEVEPTIMR) FIFO Control Position */ +#define USBHS_DEVEPTIMR_FIFOCON_Msk (_U_(0x1) << USBHS_DEVEPTIMR_FIFOCON_Pos) /**< (USBHS_DEVEPTIMR) FIFO Control Mask */ +#define USBHS_DEVEPTIMR_FIFOCON USBHS_DEVEPTIMR_FIFOCON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_FIFOCON_Msk instead */ +#define USBHS_DEVEPTIMR_EPDISHDMA_Pos 16 /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ +#define USBHS_DEVEPTIMR_EPDISHDMA_Msk (_U_(0x1) << USBHS_DEVEPTIMR_EPDISHDMA_Pos) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ +#define USBHS_DEVEPTIMR_EPDISHDMA USBHS_DEVEPTIMR_EPDISHDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_EPDISHDMA_Msk instead */ +#define USBHS_DEVEPTIMR_RSTDT_Pos 18 /**< (USBHS_DEVEPTIMR) Reset Data Toggle Position */ +#define USBHS_DEVEPTIMR_RSTDT_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RSTDT_Pos) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Mask */ +#define USBHS_DEVEPTIMR_RSTDT USBHS_DEVEPTIMR_RSTDT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_RSTDT_Msk instead */ +#define USBHS_DEVEPTIMR_MASK _U_(0x570A3) /**< \deprecated (USBHS_DEVEPTIMR) Register MASK (Use USBHS_DEVEPTIMR_Msk instead) */ +#define USBHS_DEVEPTIMR_Msk _U_(0x570A3) /**< (USBHS_DEVEPTIMR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_NAKINE USBHS_DEVEPTIMR_CTRL_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NAKINE_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_STALLEDE USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_CTRL_NYETDIS USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_CTRL_STALLRQ USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk instead */ +#define USBHS_DEVEPTIMR_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_CTRL) Register MASK (Use USBHS_DEVEPTIMR_CTRL_Msk instead) */ +#define USBHS_DEVEPTIMR_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE_Pos 2 /**< (USBHS_DEVEPTIMR) Underflow Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_UNDERFE_Pos) /**< (USBHS_DEVEPTIMR) Underflow Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE USBHS_DEVEPTIMR_ISO_UNDERFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_UNDERFE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos 3 /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4 /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_CRCERRE_Pos 6 /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_CRCERRE_Pos) /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_CRCERRE USBHS_DEVEPTIMR_ISO_CRCERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_CRCERRE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_MDATAE_Pos 8 /**< (USBHS_DEVEPTIMR) MData Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_MDATAE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_MDATAE_Pos) /**< (USBHS_DEVEPTIMR) MData Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_MDATAE USBHS_DEVEPTIMR_ISO_MDATAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_MDATAE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_DATAXE_Pos 9 /**< (USBHS_DEVEPTIMR) DataX Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_DATAXE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_DATAXE_Pos) /**< (USBHS_DEVEPTIMR) DataX Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_DATAXE USBHS_DEVEPTIMR_ISO_DATAXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_DATAXE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos 10 /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos) /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk instead */ +#define USBHS_DEVEPTIMR_ISO_MASK _U_(0x75C) /**< \deprecated (USBHS_DEVEPTIMR_ISO) Register MASK (Use USBHS_DEVEPTIMR_ISO_Msk instead) */ +#define USBHS_DEVEPTIMR_ISO_Msk _U_(0x75C) /**< (USBHS_DEVEPTIMR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE USBHS_DEVEPTIMR_BLK_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_RXSTPE_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_NAKOUTE USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_NAKINE USBHS_DEVEPTIMR_BLK_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NAKINE_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_STALLEDE USBHS_DEVEPTIMR_BLK_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_STALLEDE_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_BLK_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_BLK_NYETDIS USBHS_DEVEPTIMR_BLK_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NYETDIS_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_BLK_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_BLK_STALLRQ USBHS_DEVEPTIMR_BLK_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_STALLRQ_Msk instead */ +#define USBHS_DEVEPTIMR_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_BLK) Register MASK (Use USBHS_DEVEPTIMR_BLK_Msk instead) */ +#define USBHS_DEVEPTIMR_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NAKINE USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk instead */ +#define USBHS_DEVEPTIMR_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_INTRPT) Register MASK (Use USBHS_DEVEPTIMR_INTRPT_Msk instead) */ +#define USBHS_DEVEPTIMR_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINES:1; /**< bit: 0 Transmitted IN Data Interrupt Enable */ + uint32_t RXOUTES:1; /**< bit: 1 Received OUT Data Interrupt Enable */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFES:1; /**< bit: 5 Overflow Interrupt Enable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETES:1; /**< bit: 7 Short Packet Interrupt Enable */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKES:1; /**< bit: 12 Number of Busy Banks Interrupt Enable */ + uint32_t KILLBKS:1; /**< bit: 13 Kill IN Bank */ + uint32_t FIFOCONS:1; /**< bit: 14 FIFO Control */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t EPDISHDMAS:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request Enable */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t RSTDTS:1; /**< bit: 18 Reset Data Toggle Enable */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ + uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ + uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFES:1; /**< bit: 2 Underflow Interrupt Enable */ + uint32_t HBISOINERRES:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable */ + uint32_t HBISOFLUSHES:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Enable */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t CRCERRES:1; /**< bit: 6 CRC Error Interrupt Enable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t MDATAES:1; /**< bit: 8 MData Interrupt Enable */ + uint32_t DATAXES:1; /**< bit: 9 DataX Interrupt Enable */ + uint32_t ERRORTRANSES:1; /**< bit: 10 Transaction Error Interrupt Enable */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ + uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ + uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ + uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ + uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTIER_OFFSET (0x1F0) /**< (USBHS_DEVEPTIER) Device Endpoint Interrupt Enable Register Offset */ + +#define USBHS_DEVEPTIER_TXINES_Pos 0 /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_TXINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_TXINES_Pos) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_TXINES USBHS_DEVEPTIER_TXINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_TXINES_Msk instead */ +#define USBHS_DEVEPTIER_RXOUTES_Pos 1 /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_RXOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_RXOUTES_Pos) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_RXOUTES USBHS_DEVEPTIER_RXOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_RXOUTES_Msk instead */ +#define USBHS_DEVEPTIER_OVERFES_Pos 5 /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Position */ +#define USBHS_DEVEPTIER_OVERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_OVERFES_Pos) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_OVERFES USBHS_DEVEPTIER_OVERFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_OVERFES_Msk instead */ +#define USBHS_DEVEPTIER_SHORTPACKETES_Pos 7 /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Position */ +#define USBHS_DEVEPTIER_SHORTPACKETES_Msk (_U_(0x1) << USBHS_DEVEPTIER_SHORTPACKETES_Pos) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_SHORTPACKETES USBHS_DEVEPTIER_SHORTPACKETES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_SHORTPACKETES_Msk instead */ +#define USBHS_DEVEPTIER_NBUSYBKES_Pos 12 /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NBUSYBKES_Pos) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NBUSYBKES USBHS_DEVEPTIER_NBUSYBKES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_NBUSYBKES_Msk instead */ +#define USBHS_DEVEPTIER_KILLBKS_Pos 13 /**< (USBHS_DEVEPTIER) Kill IN Bank Position */ +#define USBHS_DEVEPTIER_KILLBKS_Msk (_U_(0x1) << USBHS_DEVEPTIER_KILLBKS_Pos) /**< (USBHS_DEVEPTIER) Kill IN Bank Mask */ +#define USBHS_DEVEPTIER_KILLBKS USBHS_DEVEPTIER_KILLBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_KILLBKS_Msk instead */ +#define USBHS_DEVEPTIER_FIFOCONS_Pos 14 /**< (USBHS_DEVEPTIER) FIFO Control Position */ +#define USBHS_DEVEPTIER_FIFOCONS_Msk (_U_(0x1) << USBHS_DEVEPTIER_FIFOCONS_Pos) /**< (USBHS_DEVEPTIER) FIFO Control Mask */ +#define USBHS_DEVEPTIER_FIFOCONS USBHS_DEVEPTIER_FIFOCONS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_FIFOCONS_Msk instead */ +#define USBHS_DEVEPTIER_EPDISHDMAS_Pos 16 /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ +#define USBHS_DEVEPTIER_EPDISHDMAS_Msk (_U_(0x1) << USBHS_DEVEPTIER_EPDISHDMAS_Pos) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_DEVEPTIER_EPDISHDMAS USBHS_DEVEPTIER_EPDISHDMAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_EPDISHDMAS_Msk instead */ +#define USBHS_DEVEPTIER_RSTDTS_Pos 18 /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Position */ +#define USBHS_DEVEPTIER_RSTDTS_Msk (_U_(0x1) << USBHS_DEVEPTIER_RSTDTS_Pos) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Mask */ +#define USBHS_DEVEPTIER_RSTDTS USBHS_DEVEPTIER_RSTDTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_RSTDTS_Msk instead */ +#define USBHS_DEVEPTIER_MASK _U_(0x570A3) /**< \deprecated (USBHS_DEVEPTIER) Register MASK (Use USBHS_DEVEPTIER_Msk instead) */ +#define USBHS_DEVEPTIER_Msk _U_(0x570A3) /**< (USBHS_DEVEPTIER) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES USBHS_DEVEPTIER_CTRL_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_RXSTPES_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NAKOUTES USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NAKINES USBHS_DEVEPTIER_CTRL_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NAKINES_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_STALLEDES USBHS_DEVEPTIER_CTRL_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_STALLEDES_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NYETDISS USBHS_DEVEPTIER_CTRL_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NYETDISS_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_CTRL_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_STALLRQS USBHS_DEVEPTIER_CTRL_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_STALLRQS_Msk instead */ +#define USBHS_DEVEPTIER_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_CTRL) Register MASK (Use USBHS_DEVEPTIER_CTRL_Msk instead) */ +#define USBHS_DEVEPTIER_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIER_ISO_UNDERFES_Pos 2 /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_UNDERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_UNDERFES_Pos) /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_UNDERFES USBHS_DEVEPTIER_ISO_UNDERFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_UNDERFES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos 3 /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_HBISOINERRES USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos 4 /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_CRCERRES_Pos 6 /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_CRCERRES_Pos) /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_CRCERRES USBHS_DEVEPTIER_ISO_CRCERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_CRCERRES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_MDATAES_Pos 8 /**< (USBHS_DEVEPTIER) MData Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_MDATAES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_MDATAES_Pos) /**< (USBHS_DEVEPTIER) MData Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_MDATAES USBHS_DEVEPTIER_ISO_MDATAES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_MDATAES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_DATAXES_Pos 9 /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_DATAXES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_DATAXES_Pos) /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_DATAXES USBHS_DEVEPTIER_ISO_DATAXES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_DATAXES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos 10 /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos) /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk instead */ +#define USBHS_DEVEPTIER_ISO_MASK _U_(0x75C) /**< \deprecated (USBHS_DEVEPTIER_ISO) Register MASK (Use USBHS_DEVEPTIER_ISO_Msk instead) */ +#define USBHS_DEVEPTIER_ISO_Msk _U_(0x75C) /**< (USBHS_DEVEPTIER_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIER_BLK_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_RXSTPES USBHS_DEVEPTIER_BLK_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_RXSTPES_Msk instead */ +#define USBHS_DEVEPTIER_BLK_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NAKOUTES USBHS_DEVEPTIER_BLK_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NAKOUTES_Msk instead */ +#define USBHS_DEVEPTIER_BLK_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NAKINES USBHS_DEVEPTIER_BLK_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NAKINES_Msk instead */ +#define USBHS_DEVEPTIER_BLK_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_STALLEDES USBHS_DEVEPTIER_BLK_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_STALLEDES_Msk instead */ +#define USBHS_DEVEPTIER_BLK_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_BLK_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NYETDISS USBHS_DEVEPTIER_BLK_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NYETDISS_Msk instead */ +#define USBHS_DEVEPTIER_BLK_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_BLK_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_BLK_STALLRQS USBHS_DEVEPTIER_BLK_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_STALLRQS_Msk instead */ +#define USBHS_DEVEPTIER_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_BLK) Register MASK (Use USBHS_DEVEPTIER_BLK_Msk instead) */ +#define USBHS_DEVEPTIER_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NAKINES USBHS_DEVEPTIER_INTRPT_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NAKINES_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_STALLEDES USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NYETDISS USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_STALLRQS USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk instead */ +#define USBHS_DEVEPTIER_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_INTRPT) Register MASK (Use USBHS_DEVEPTIER_INTRPT_Msk instead) */ +#define USBHS_DEVEPTIER_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TXINEC:1; /**< bit: 0 Transmitted IN Interrupt Clear */ + uint32_t RXOUTEC:1; /**< bit: 1 Received OUT Data Interrupt Clear */ + uint32_t :3; /**< bit: 2..4 Reserved */ + uint32_t OVERFEC:1; /**< bit: 5 Overflow Interrupt Clear */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETEC:1; /**< bit: 7 Shortpacket Interrupt Clear */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKEC:1; /**< bit: 12 Number of Busy Banks Interrupt Clear */ + uint32_t :1; /**< bit: 13 Reserved */ + uint32_t FIFOCONC:1; /**< bit: 14 FIFO Control Clear */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t EPDISHDMAC:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request Clear */ + uint32_t :15; /**< bit: 17..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFEC:1; /**< bit: 2 Underflow Interrupt Clear */ + uint32_t HBISOINERREC:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ + uint32_t HBISOFLUSHEC:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Clear */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t MDATAEC:1; /**< bit: 8 MData Interrupt Clear */ + uint32_t DATAXEC:1; /**< bit: 9 DataX Interrupt Clear */ + uint32_t ERRORTRANSEC:1; /**< bit: 10 Transaction Error Interrupt Clear */ + uint32_t :21; /**< bit: 11..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ + uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ + uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ + uint32_t :10; /**< bit: 7..16 Reserved */ + uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ + uint32_t :1; /**< bit: 18 Reserved */ + uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ + uint32_t :12; /**< bit: 20..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_DEVEPTIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_DEVEPTIDR_OFFSET (0x220) /**< (USBHS_DEVEPTIDR) Device Endpoint Interrupt Disable Register Offset */ + +#define USBHS_DEVEPTIDR_TXINEC_Pos 0 /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_TXINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_TXINEC_Pos) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_TXINEC USBHS_DEVEPTIDR_TXINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_TXINEC_Msk instead */ +#define USBHS_DEVEPTIDR_RXOUTEC_Pos 1 /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_RXOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_RXOUTEC_Pos) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_RXOUTEC USBHS_DEVEPTIDR_RXOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_RXOUTEC_Msk instead */ +#define USBHS_DEVEPTIDR_OVERFEC_Pos 5 /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_OVERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_OVERFEC_Pos) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_OVERFEC USBHS_DEVEPTIDR_OVERFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_OVERFEC_Msk instead */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Pos 7 /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC USBHS_DEVEPTIDR_SHORTPACKETEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_SHORTPACKETEC_Msk instead */ +#define USBHS_DEVEPTIDR_NBUSYBKEC_Pos 12 /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NBUSYBKEC USBHS_DEVEPTIDR_NBUSYBKEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_NBUSYBKEC_Msk instead */ +#define USBHS_DEVEPTIDR_FIFOCONC_Pos 14 /**< (USBHS_DEVEPTIDR) FIFO Control Clear Position */ +#define USBHS_DEVEPTIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_FIFOCONC_Pos) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Mask */ +#define USBHS_DEVEPTIDR_FIFOCONC USBHS_DEVEPTIDR_FIFOCONC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_FIFOCONC_Msk instead */ +#define USBHS_DEVEPTIDR_EPDISHDMAC_Pos 16 /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ +#define USBHS_DEVEPTIDR_EPDISHDMAC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ +#define USBHS_DEVEPTIDR_EPDISHDMAC USBHS_DEVEPTIDR_EPDISHDMAC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_EPDISHDMAC_Msk instead */ +#define USBHS_DEVEPTIDR_MASK _U_(0x150A3) /**< \deprecated (USBHS_DEVEPTIDR) Register MASK (Use USBHS_DEVEPTIDR_Msk instead) */ +#define USBHS_DEVEPTIDR_Msk _U_(0x150A3) /**< (USBHS_DEVEPTIDR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NAKINEC USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NYETDISC USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_STALLRQC USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk instead */ +#define USBHS_DEVEPTIDR_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_CTRL) Register MASK (Use USBHS_DEVEPTIDR_CTRL_Msk instead) */ +#define USBHS_DEVEPTIDR_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos 2 /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos) /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos 3 /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4 /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_MDATAEC_Pos 8 /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_MDATAEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_MDATAEC_Pos) /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_MDATAEC USBHS_DEVEPTIDR_ISO_MDATAEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_MDATAEC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_DATAXEC_Pos 9 /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_DATAXEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_DATAXEC_Pos) /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_DATAXEC USBHS_DEVEPTIDR_ISO_DATAXEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_DATAXEC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10 /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos) /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk instead */ +#define USBHS_DEVEPTIDR_ISO_MASK _U_(0x71C) /**< \deprecated (USBHS_DEVEPTIDR_ISO) Register MASK (Use USBHS_DEVEPTIDR_ISO_Msk instead) */ +#define USBHS_DEVEPTIDR_ISO_Msk _U_(0x71C) /**< (USBHS_DEVEPTIDR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NAKINEC USBHS_DEVEPTIDR_BLK_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NAKINEC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_STALLEDEC USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NYETDISC USBHS_DEVEPTIDR_BLK_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NYETDISC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_BLK_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_STALLRQC USBHS_DEVEPTIDR_BLK_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_STALLRQC_Msk instead */ +#define USBHS_DEVEPTIDR_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_BLK) Register MASK (Use USBHS_DEVEPTIDR_BLK_Msk instead) */ +#define USBHS_DEVEPTIDR_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk instead */ +#define USBHS_DEVEPTIDR_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_INTRPT) Register MASK (Use USBHS_DEVEPTIDR_INTRPT_Msk instead) */ +#define USBHS_DEVEPTIDR_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t SOFE:1; /**< bit: 8 Start of Frame Generation Enable */ + uint32_t RESET:1; /**< bit: 9 Send USB Reset */ + uint32_t RESUME:1; /**< bit: 10 Send USB Resume */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t SPDCONF:2; /**< bit: 12..13 Mode Configuration */ + uint32_t :18; /**< bit: 14..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTCTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTCTRL_OFFSET (0x400) /**< (USBHS_HSTCTRL) Host General Control Register Offset */ + +#define USBHS_HSTCTRL_SOFE_Pos 8 /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Position */ +#define USBHS_HSTCTRL_SOFE_Msk (_U_(0x1) << USBHS_HSTCTRL_SOFE_Pos) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Mask */ +#define USBHS_HSTCTRL_SOFE USBHS_HSTCTRL_SOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_SOFE_Msk instead */ +#define USBHS_HSTCTRL_RESET_Pos 9 /**< (USBHS_HSTCTRL) Send USB Reset Position */ +#define USBHS_HSTCTRL_RESET_Msk (_U_(0x1) << USBHS_HSTCTRL_RESET_Pos) /**< (USBHS_HSTCTRL) Send USB Reset Mask */ +#define USBHS_HSTCTRL_RESET USBHS_HSTCTRL_RESET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_RESET_Msk instead */ +#define USBHS_HSTCTRL_RESUME_Pos 10 /**< (USBHS_HSTCTRL) Send USB Resume Position */ +#define USBHS_HSTCTRL_RESUME_Msk (_U_(0x1) << USBHS_HSTCTRL_RESUME_Pos) /**< (USBHS_HSTCTRL) Send USB Resume Mask */ +#define USBHS_HSTCTRL_RESUME USBHS_HSTCTRL_RESUME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_RESUME_Msk instead */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 /**< (USBHS_HSTCTRL) Mode Configuration Position */ +#define USBHS_HSTCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Mode Configuration Mask */ +#define USBHS_HSTCTRL_SPDCONF(value) (USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)) +#define USBHS_HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +#define USBHS_HSTCTRL_SPDCONF_NORMAL (USBHS_HSTCTRL_SPDCONF_NORMAL_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Forced high speed. Position */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ +#define USBHS_HSTCTRL_MASK _U_(0x3700) /**< \deprecated (USBHS_HSTCTRL) Register MASK (Use USBHS_HSTCTRL_Msk instead) */ +#define USBHS_HSTCTRL_Msk _U_(0x3700) /**< (USBHS_HSTCTRL) Register Mask */ + + +/* -------- USBHS_HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNI:1; /**< bit: 0 Device Connection Interrupt */ + uint32_t DDISCI:1; /**< bit: 1 Device Disconnection Interrupt */ + uint32_t RSTI:1; /**< bit: 2 USB Reset Sent Interrupt */ + uint32_t RSMEDI:1; /**< bit: 3 Downstream Resume Sent Interrupt */ + uint32_t RXRSMI:1; /**< bit: 4 Upstream Resume Received Interrupt */ + uint32_t HSOFI:1; /**< bit: 5 Host Start of Frame Interrupt */ + uint32_t HWUPI:1; /**< bit: 6 Host Wake-Up Interrupt */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt */ + uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt */ + uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt */ + uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt */ + uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt */ + uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt */ + uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt */ + uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt */ + uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt */ + uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt */ + uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt */ + uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt */ + uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt */ + uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt */ + uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt */ + uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTISR_OFFSET (0x404) /**< (USBHS_HSTISR) Host Global Interrupt Status Register Offset */ + +#define USBHS_HSTISR_DCONNI_Pos 0 /**< (USBHS_HSTISR) Device Connection Interrupt Position */ +#define USBHS_HSTISR_DCONNI_Msk (_U_(0x1) << USBHS_HSTISR_DCONNI_Pos) /**< (USBHS_HSTISR) Device Connection Interrupt Mask */ +#define USBHS_HSTISR_DCONNI USBHS_HSTISR_DCONNI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DCONNI_Msk instead */ +#define USBHS_HSTISR_DDISCI_Pos 1 /**< (USBHS_HSTISR) Device Disconnection Interrupt Position */ +#define USBHS_HSTISR_DDISCI_Msk (_U_(0x1) << USBHS_HSTISR_DDISCI_Pos) /**< (USBHS_HSTISR) Device Disconnection Interrupt Mask */ +#define USBHS_HSTISR_DDISCI USBHS_HSTISR_DDISCI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DDISCI_Msk instead */ +#define USBHS_HSTISR_RSTI_Pos 2 /**< (USBHS_HSTISR) USB Reset Sent Interrupt Position */ +#define USBHS_HSTISR_RSTI_Msk (_U_(0x1) << USBHS_HSTISR_RSTI_Pos) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Mask */ +#define USBHS_HSTISR_RSTI USBHS_HSTISR_RSTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RSTI_Msk instead */ +#define USBHS_HSTISR_RSMEDI_Pos 3 /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Position */ +#define USBHS_HSTISR_RSMEDI_Msk (_U_(0x1) << USBHS_HSTISR_RSMEDI_Pos) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Mask */ +#define USBHS_HSTISR_RSMEDI USBHS_HSTISR_RSMEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RSMEDI_Msk instead */ +#define USBHS_HSTISR_RXRSMI_Pos 4 /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Position */ +#define USBHS_HSTISR_RXRSMI_Msk (_U_(0x1) << USBHS_HSTISR_RXRSMI_Pos) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Mask */ +#define USBHS_HSTISR_RXRSMI USBHS_HSTISR_RXRSMI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RXRSMI_Msk instead */ +#define USBHS_HSTISR_HSOFI_Pos 5 /**< (USBHS_HSTISR) Host Start of Frame Interrupt Position */ +#define USBHS_HSTISR_HSOFI_Msk (_U_(0x1) << USBHS_HSTISR_HSOFI_Pos) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Mask */ +#define USBHS_HSTISR_HSOFI USBHS_HSTISR_HSOFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_HSOFI_Msk instead */ +#define USBHS_HSTISR_HWUPI_Pos 6 /**< (USBHS_HSTISR) Host Wake-Up Interrupt Position */ +#define USBHS_HSTISR_HWUPI_Msk (_U_(0x1) << USBHS_HSTISR_HWUPI_Pos) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Mask */ +#define USBHS_HSTISR_HWUPI USBHS_HSTISR_HWUPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_HWUPI_Msk instead */ +#define USBHS_HSTISR_PEP_0_Pos 8 /**< (USBHS_HSTISR) Pipe 0 Interrupt Position */ +#define USBHS_HSTISR_PEP_0_Msk (_U_(0x1) << USBHS_HSTISR_PEP_0_Pos) /**< (USBHS_HSTISR) Pipe 0 Interrupt Mask */ +#define USBHS_HSTISR_PEP_0 USBHS_HSTISR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_0_Msk instead */ +#define USBHS_HSTISR_PEP_1_Pos 9 /**< (USBHS_HSTISR) Pipe 1 Interrupt Position */ +#define USBHS_HSTISR_PEP_1_Msk (_U_(0x1) << USBHS_HSTISR_PEP_1_Pos) /**< (USBHS_HSTISR) Pipe 1 Interrupt Mask */ +#define USBHS_HSTISR_PEP_1 USBHS_HSTISR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_1_Msk instead */ +#define USBHS_HSTISR_PEP_2_Pos 10 /**< (USBHS_HSTISR) Pipe 2 Interrupt Position */ +#define USBHS_HSTISR_PEP_2_Msk (_U_(0x1) << USBHS_HSTISR_PEP_2_Pos) /**< (USBHS_HSTISR) Pipe 2 Interrupt Mask */ +#define USBHS_HSTISR_PEP_2 USBHS_HSTISR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_2_Msk instead */ +#define USBHS_HSTISR_PEP_3_Pos 11 /**< (USBHS_HSTISR) Pipe 3 Interrupt Position */ +#define USBHS_HSTISR_PEP_3_Msk (_U_(0x1) << USBHS_HSTISR_PEP_3_Pos) /**< (USBHS_HSTISR) Pipe 3 Interrupt Mask */ +#define USBHS_HSTISR_PEP_3 USBHS_HSTISR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_3_Msk instead */ +#define USBHS_HSTISR_PEP_4_Pos 12 /**< (USBHS_HSTISR) Pipe 4 Interrupt Position */ +#define USBHS_HSTISR_PEP_4_Msk (_U_(0x1) << USBHS_HSTISR_PEP_4_Pos) /**< (USBHS_HSTISR) Pipe 4 Interrupt Mask */ +#define USBHS_HSTISR_PEP_4 USBHS_HSTISR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_4_Msk instead */ +#define USBHS_HSTISR_PEP_5_Pos 13 /**< (USBHS_HSTISR) Pipe 5 Interrupt Position */ +#define USBHS_HSTISR_PEP_5_Msk (_U_(0x1) << USBHS_HSTISR_PEP_5_Pos) /**< (USBHS_HSTISR) Pipe 5 Interrupt Mask */ +#define USBHS_HSTISR_PEP_5 USBHS_HSTISR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_5_Msk instead */ +#define USBHS_HSTISR_PEP_6_Pos 14 /**< (USBHS_HSTISR) Pipe 6 Interrupt Position */ +#define USBHS_HSTISR_PEP_6_Msk (_U_(0x1) << USBHS_HSTISR_PEP_6_Pos) /**< (USBHS_HSTISR) Pipe 6 Interrupt Mask */ +#define USBHS_HSTISR_PEP_6 USBHS_HSTISR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_6_Msk instead */ +#define USBHS_HSTISR_PEP_7_Pos 15 /**< (USBHS_HSTISR) Pipe 7 Interrupt Position */ +#define USBHS_HSTISR_PEP_7_Msk (_U_(0x1) << USBHS_HSTISR_PEP_7_Pos) /**< (USBHS_HSTISR) Pipe 7 Interrupt Mask */ +#define USBHS_HSTISR_PEP_7 USBHS_HSTISR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_7_Msk instead */ +#define USBHS_HSTISR_PEP_8_Pos 16 /**< (USBHS_HSTISR) Pipe 8 Interrupt Position */ +#define USBHS_HSTISR_PEP_8_Msk (_U_(0x1) << USBHS_HSTISR_PEP_8_Pos) /**< (USBHS_HSTISR) Pipe 8 Interrupt Mask */ +#define USBHS_HSTISR_PEP_8 USBHS_HSTISR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_8_Msk instead */ +#define USBHS_HSTISR_PEP_9_Pos 17 /**< (USBHS_HSTISR) Pipe 9 Interrupt Position */ +#define USBHS_HSTISR_PEP_9_Msk (_U_(0x1) << USBHS_HSTISR_PEP_9_Pos) /**< (USBHS_HSTISR) Pipe 9 Interrupt Mask */ +#define USBHS_HSTISR_PEP_9 USBHS_HSTISR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_9_Msk instead */ +#define USBHS_HSTISR_DMA_0_Pos 25 /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Position */ +#define USBHS_HSTISR_DMA_0_Msk (_U_(0x1) << USBHS_HSTISR_DMA_0_Pos) /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Mask */ +#define USBHS_HSTISR_DMA_0 USBHS_HSTISR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_0_Msk instead */ +#define USBHS_HSTISR_DMA_1_Pos 26 /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Position */ +#define USBHS_HSTISR_DMA_1_Msk (_U_(0x1) << USBHS_HSTISR_DMA_1_Pos) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_HSTISR_DMA_1 USBHS_HSTISR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_1_Msk instead */ +#define USBHS_HSTISR_DMA_2_Pos 27 /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Position */ +#define USBHS_HSTISR_DMA_2_Msk (_U_(0x1) << USBHS_HSTISR_DMA_2_Pos) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_HSTISR_DMA_2 USBHS_HSTISR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_2_Msk instead */ +#define USBHS_HSTISR_DMA_3_Pos 28 /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Position */ +#define USBHS_HSTISR_DMA_3_Msk (_U_(0x1) << USBHS_HSTISR_DMA_3_Pos) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_HSTISR_DMA_3 USBHS_HSTISR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_3_Msk instead */ +#define USBHS_HSTISR_DMA_4_Pos 29 /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Position */ +#define USBHS_HSTISR_DMA_4_Msk (_U_(0x1) << USBHS_HSTISR_DMA_4_Pos) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_HSTISR_DMA_4 USBHS_HSTISR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_4_Msk instead */ +#define USBHS_HSTISR_DMA_5_Pos 30 /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Position */ +#define USBHS_HSTISR_DMA_5_Msk (_U_(0x1) << USBHS_HSTISR_DMA_5_Pos) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_HSTISR_DMA_5 USBHS_HSTISR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_5_Msk instead */ +#define USBHS_HSTISR_DMA_6_Pos 31 /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Position */ +#define USBHS_HSTISR_DMA_6_Msk (_U_(0x1) << USBHS_HSTISR_DMA_6_Pos) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_HSTISR_DMA_6 USBHS_HSTISR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_6_Msk instead */ +#define USBHS_HSTISR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTISR) Register MASK (Use USBHS_HSTISR_Msk instead) */ +#define USBHS_HSTISR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTISR) Register Mask */ + +#define USBHS_HSTISR_PEP__Pos 8 /**< (USBHS_HSTISR Position) Pipe x Interrupt */ +#define USBHS_HSTISR_PEP__Msk (_U_(0x3FF) << USBHS_HSTISR_PEP__Pos) /**< (USBHS_HSTISR Mask) PEP_ */ +#define USBHS_HSTISR_PEP_(value) (USBHS_HSTISR_PEP__Msk & ((value) << USBHS_HSTISR_PEP__Pos)) +#define USBHS_HSTISR_DMA__Pos 25 /**< (USBHS_HSTISR Position) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA__Msk (_U_(0x7F) << USBHS_HSTISR_DMA__Pos) /**< (USBHS_HSTISR Mask) DMA_ */ +#define USBHS_HSTISR_DMA_(value) (USBHS_HSTISR_DMA__Msk & ((value) << USBHS_HSTISR_DMA__Pos)) + +/* -------- USBHS_HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNIC:1; /**< bit: 0 Device Connection Interrupt Clear */ + uint32_t DDISCIC:1; /**< bit: 1 Device Disconnection Interrupt Clear */ + uint32_t RSTIC:1; /**< bit: 2 USB Reset Sent Interrupt Clear */ + uint32_t RSMEDIC:1; /**< bit: 3 Downstream Resume Sent Interrupt Clear */ + uint32_t RXRSMIC:1; /**< bit: 4 Upstream Resume Received Interrupt Clear */ + uint32_t HSOFIC:1; /**< bit: 5 Host Start of Frame Interrupt Clear */ + uint32_t HWUPIC:1; /**< bit: 6 Host Wake-Up Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTICR_OFFSET (0x408) /**< (USBHS_HSTICR) Host Global Interrupt Clear Register Offset */ + +#define USBHS_HSTICR_DCONNIC_Pos 0 /**< (USBHS_HSTICR) Device Connection Interrupt Clear Position */ +#define USBHS_HSTICR_DCONNIC_Msk (_U_(0x1) << USBHS_HSTICR_DCONNIC_Pos) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Mask */ +#define USBHS_HSTICR_DCONNIC USBHS_HSTICR_DCONNIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_DCONNIC_Msk instead */ +#define USBHS_HSTICR_DDISCIC_Pos 1 /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Position */ +#define USBHS_HSTICR_DDISCIC_Msk (_U_(0x1) << USBHS_HSTICR_DDISCIC_Pos) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Mask */ +#define USBHS_HSTICR_DDISCIC USBHS_HSTICR_DDISCIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_DDISCIC_Msk instead */ +#define USBHS_HSTICR_RSTIC_Pos 2 /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSTIC_Msk (_U_(0x1) << USBHS_HSTICR_RSTIC_Pos) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSTIC USBHS_HSTICR_RSTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RSTIC_Msk instead */ +#define USBHS_HSTICR_RSMEDIC_Pos 3 /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSMEDIC_Msk (_U_(0x1) << USBHS_HSTICR_RSMEDIC_Pos) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSMEDIC USBHS_HSTICR_RSMEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RSMEDIC_Msk instead */ +#define USBHS_HSTICR_RXRSMIC_Pos 4 /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Position */ +#define USBHS_HSTICR_RXRSMIC_Msk (_U_(0x1) << USBHS_HSTICR_RXRSMIC_Pos) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Mask */ +#define USBHS_HSTICR_RXRSMIC USBHS_HSTICR_RXRSMIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RXRSMIC_Msk instead */ +#define USBHS_HSTICR_HSOFIC_Pos 5 /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Position */ +#define USBHS_HSTICR_HSOFIC_Msk (_U_(0x1) << USBHS_HSTICR_HSOFIC_Pos) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Mask */ +#define USBHS_HSTICR_HSOFIC USBHS_HSTICR_HSOFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_HSOFIC_Msk instead */ +#define USBHS_HSTICR_HWUPIC_Pos 6 /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Position */ +#define USBHS_HSTICR_HWUPIC_Msk (_U_(0x1) << USBHS_HSTICR_HWUPIC_Pos) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Mask */ +#define USBHS_HSTICR_HWUPIC USBHS_HSTICR_HWUPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_HWUPIC_Msk instead */ +#define USBHS_HSTICR_MASK _U_(0x7F) /**< \deprecated (USBHS_HSTICR) Register MASK (Use USBHS_HSTICR_Msk instead) */ +#define USBHS_HSTICR_Msk _U_(0x7F) /**< (USBHS_HSTICR) Register Mask */ + + +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNIS:1; /**< bit: 0 Device Connection Interrupt Set */ + uint32_t DDISCIS:1; /**< bit: 1 Device Disconnection Interrupt Set */ + uint32_t RSTIS:1; /**< bit: 2 USB Reset Sent Interrupt Set */ + uint32_t RSMEDIS:1; /**< bit: 3 Downstream Resume Sent Interrupt Set */ + uint32_t RXRSMIS:1; /**< bit: 4 Upstream Resume Received Interrupt Set */ + uint32_t HSOFIS:1; /**< bit: 5 Host Start of Frame Interrupt Set */ + uint32_t HWUPIS:1; /**< bit: 6 Host Wake-Up Interrupt Set */ + uint32_t :18; /**< bit: 7..24 Reserved */ + uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Set */ + uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Set */ + uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Set */ + uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Set */ + uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Set */ + uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Set */ + uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Set */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :25; /**< bit: 0..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Set */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTIFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTIFR_OFFSET (0x40C) /**< (USBHS_HSTIFR) Host Global Interrupt Set Register Offset */ + +#define USBHS_HSTIFR_DCONNIS_Pos 0 /**< (USBHS_HSTIFR) Device Connection Interrupt Set Position */ +#define USBHS_HSTIFR_DCONNIS_Msk (_U_(0x1) << USBHS_HSTIFR_DCONNIS_Pos) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Mask */ +#define USBHS_HSTIFR_DCONNIS USBHS_HSTIFR_DCONNIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DCONNIS_Msk instead */ +#define USBHS_HSTIFR_DDISCIS_Pos 1 /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Position */ +#define USBHS_HSTIFR_DDISCIS_Msk (_U_(0x1) << USBHS_HSTIFR_DDISCIS_Pos) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Mask */ +#define USBHS_HSTIFR_DDISCIS USBHS_HSTIFR_DDISCIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DDISCIS_Msk instead */ +#define USBHS_HSTIFR_RSTIS_Pos 2 /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSTIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSTIS_Pos) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSTIS USBHS_HSTIFR_RSTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RSTIS_Msk instead */ +#define USBHS_HSTIFR_RSMEDIS_Pos 3 /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSMEDIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSMEDIS_Pos) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSMEDIS USBHS_HSTIFR_RSMEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RSMEDIS_Msk instead */ +#define USBHS_HSTIFR_RXRSMIS_Pos 4 /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Position */ +#define USBHS_HSTIFR_RXRSMIS_Msk (_U_(0x1) << USBHS_HSTIFR_RXRSMIS_Pos) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Mask */ +#define USBHS_HSTIFR_RXRSMIS USBHS_HSTIFR_RXRSMIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RXRSMIS_Msk instead */ +#define USBHS_HSTIFR_HSOFIS_Pos 5 /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Position */ +#define USBHS_HSTIFR_HSOFIS_Msk (_U_(0x1) << USBHS_HSTIFR_HSOFIS_Pos) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Mask */ +#define USBHS_HSTIFR_HSOFIS USBHS_HSTIFR_HSOFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_HSOFIS_Msk instead */ +#define USBHS_HSTIFR_HWUPIS_Pos 6 /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Position */ +#define USBHS_HSTIFR_HWUPIS_Msk (_U_(0x1) << USBHS_HSTIFR_HWUPIS_Pos) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Mask */ +#define USBHS_HSTIFR_HWUPIS USBHS_HSTIFR_HWUPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_HWUPIS_Msk instead */ +#define USBHS_HSTIFR_DMA_0_Pos 25 /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_0_Pos) /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_0 USBHS_HSTIFR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_0_Msk instead */ +#define USBHS_HSTIFR_DMA_1_Pos 26 /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_1_Pos) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_1 USBHS_HSTIFR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_1_Msk instead */ +#define USBHS_HSTIFR_DMA_2_Pos 27 /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_2_Pos) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_2 USBHS_HSTIFR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_2_Msk instead */ +#define USBHS_HSTIFR_DMA_3_Pos 28 /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_3_Pos) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_3 USBHS_HSTIFR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_3_Msk instead */ +#define USBHS_HSTIFR_DMA_4_Pos 29 /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_4_Pos) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_4 USBHS_HSTIFR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_4_Msk instead */ +#define USBHS_HSTIFR_DMA_5_Pos 30 /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_5_Pos) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_5 USBHS_HSTIFR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_5_Msk instead */ +#define USBHS_HSTIFR_DMA_6_Pos 31 /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_6_Pos) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_6 USBHS_HSTIFR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_6_Msk instead */ +#define USBHS_HSTIFR_MASK _U_(0xFE00007F) /**< \deprecated (USBHS_HSTIFR) Register MASK (Use USBHS_HSTIFR_Msk instead) */ +#define USBHS_HSTIFR_Msk _U_(0xFE00007F) /**< (USBHS_HSTIFR) Register Mask */ + +#define USBHS_HSTIFR_DMA__Pos 25 /**< (USBHS_HSTIFR Position) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA__Msk (_U_(0x7F) << USBHS_HSTIFR_DMA__Pos) /**< (USBHS_HSTIFR Mask) DMA_ */ +#define USBHS_HSTIFR_DMA_(value) (USBHS_HSTIFR_DMA__Msk & ((value) << USBHS_HSTIFR_DMA__Pos)) + +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNIE:1; /**< bit: 0 Device Connection Interrupt Enable */ + uint32_t DDISCIE:1; /**< bit: 1 Device Disconnection Interrupt Enable */ + uint32_t RSTIE:1; /**< bit: 2 USB Reset Sent Interrupt Enable */ + uint32_t RSMEDIE:1; /**< bit: 3 Downstream Resume Sent Interrupt Enable */ + uint32_t RXRSMIE:1; /**< bit: 4 Upstream Resume Received Interrupt Enable */ + uint32_t HSOFIE:1; /**< bit: 5 Host Start of Frame Interrupt Enable */ + uint32_t HWUPIE:1; /**< bit: 6 Host Wake-Up Interrupt Enable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Enable */ + uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Enable */ + uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Enable */ + uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Enable */ + uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Enable */ + uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Enable */ + uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Enable */ + uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Enable */ + uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Enable */ + uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Enable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Enable */ + uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Enable */ + uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Enable */ + uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Enable */ + uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Enable */ + uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Enable */ + uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Enable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTIMR_OFFSET (0x410) /**< (USBHS_HSTIMR) Host Global Interrupt Mask Register Offset */ + +#define USBHS_HSTIMR_DCONNIE_Pos 0 /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIMR_DCONNIE_Msk (_U_(0x1) << USBHS_HSTIMR_DCONNIE_Pos) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DCONNIE USBHS_HSTIMR_DCONNIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DCONNIE_Msk instead */ +#define USBHS_HSTIMR_DDISCIE_Pos 1 /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIMR_DDISCIE_Msk (_U_(0x1) << USBHS_HSTIMR_DDISCIE_Pos) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DDISCIE USBHS_HSTIMR_DDISCIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DDISCIE_Msk instead */ +#define USBHS_HSTIMR_RSTIE_Pos 2 /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSTIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSTIE_Pos) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSTIE USBHS_HSTIMR_RSTIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RSTIE_Msk instead */ +#define USBHS_HSTIMR_RSMEDIE_Pos 3 /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSMEDIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSMEDIE_Pos) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSMEDIE USBHS_HSTIMR_RSMEDIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RSMEDIE_Msk instead */ +#define USBHS_HSTIMR_RXRSMIE_Pos 4 /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIMR_RXRSMIE_Msk (_U_(0x1) << USBHS_HSTIMR_RXRSMIE_Pos) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIMR_RXRSMIE USBHS_HSTIMR_RXRSMIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RXRSMIE_Msk instead */ +#define USBHS_HSTIMR_HSOFIE_Pos 5 /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIMR_HSOFIE_Msk (_U_(0x1) << USBHS_HSTIMR_HSOFIE_Pos) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIMR_HSOFIE USBHS_HSTIMR_HSOFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_HSOFIE_Msk instead */ +#define USBHS_HSTIMR_HWUPIE_Pos 6 /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIMR_HWUPIE_Msk (_U_(0x1) << USBHS_HSTIMR_HWUPIE_Pos) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIMR_HWUPIE USBHS_HSTIMR_HWUPIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_HWUPIE_Msk instead */ +#define USBHS_HSTIMR_PEP_0_Pos 8 /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_0_Pos) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_0 USBHS_HSTIMR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_0_Msk instead */ +#define USBHS_HSTIMR_PEP_1_Pos 9 /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_1_Pos) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_1 USBHS_HSTIMR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_1_Msk instead */ +#define USBHS_HSTIMR_PEP_2_Pos 10 /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_2_Pos) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_2 USBHS_HSTIMR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_2_Msk instead */ +#define USBHS_HSTIMR_PEP_3_Pos 11 /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_3_Pos) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_3 USBHS_HSTIMR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_3_Msk instead */ +#define USBHS_HSTIMR_PEP_4_Pos 12 /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_4_Pos) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_4 USBHS_HSTIMR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_4_Msk instead */ +#define USBHS_HSTIMR_PEP_5_Pos 13 /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_5_Pos) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_5 USBHS_HSTIMR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_5_Msk instead */ +#define USBHS_HSTIMR_PEP_6_Pos 14 /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_6_Pos) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_6 USBHS_HSTIMR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_6_Msk instead */ +#define USBHS_HSTIMR_PEP_7_Pos 15 /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_7_Pos) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_7 USBHS_HSTIMR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_7_Msk instead */ +#define USBHS_HSTIMR_PEP_8_Pos 16 /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_8_Pos) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_8 USBHS_HSTIMR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_8_Msk instead */ +#define USBHS_HSTIMR_PEP_9_Pos 17 /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_9_Pos) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_9 USBHS_HSTIMR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_9_Msk instead */ +#define USBHS_HSTIMR_DMA_0_Pos 25 /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_0_Pos) /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_0 USBHS_HSTIMR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_0_Msk instead */ +#define USBHS_HSTIMR_DMA_1_Pos 26 /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_1_Pos) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_1 USBHS_HSTIMR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_1_Msk instead */ +#define USBHS_HSTIMR_DMA_2_Pos 27 /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_2_Pos) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_2 USBHS_HSTIMR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_2_Msk instead */ +#define USBHS_HSTIMR_DMA_3_Pos 28 /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_3_Pos) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_3 USBHS_HSTIMR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_3_Msk instead */ +#define USBHS_HSTIMR_DMA_4_Pos 29 /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_4_Pos) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_4 USBHS_HSTIMR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_4_Msk instead */ +#define USBHS_HSTIMR_DMA_5_Pos 30 /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_5_Pos) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_5 USBHS_HSTIMR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_5_Msk instead */ +#define USBHS_HSTIMR_DMA_6_Pos 31 /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_6_Pos) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_6 USBHS_HSTIMR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_6_Msk instead */ +#define USBHS_HSTIMR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIMR) Register MASK (Use USBHS_HSTIMR_Msk instead) */ +#define USBHS_HSTIMR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIMR) Register Mask */ + +#define USBHS_HSTIMR_PEP__Pos 8 /**< (USBHS_HSTIMR Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIMR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIMR_PEP__Pos) /**< (USBHS_HSTIMR Mask) PEP_ */ +#define USBHS_HSTIMR_PEP_(value) (USBHS_HSTIMR_PEP__Msk & ((value) << USBHS_HSTIMR_PEP__Pos)) +#define USBHS_HSTIMR_DMA__Pos 25 /**< (USBHS_HSTIMR Position) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA__Msk (_U_(0x7F) << USBHS_HSTIMR_DMA__Pos) /**< (USBHS_HSTIMR Mask) DMA_ */ +#define USBHS_HSTIMR_DMA_(value) (USBHS_HSTIMR_DMA__Msk & ((value) << USBHS_HSTIMR_DMA__Pos)) + +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNIEC:1; /**< bit: 0 Device Connection Interrupt Disable */ + uint32_t DDISCIEC:1; /**< bit: 1 Device Disconnection Interrupt Disable */ + uint32_t RSTIEC:1; /**< bit: 2 USB Reset Sent Interrupt Disable */ + uint32_t RSMEDIEC:1; /**< bit: 3 Downstream Resume Sent Interrupt Disable */ + uint32_t RXRSMIEC:1; /**< bit: 4 Upstream Resume Received Interrupt Disable */ + uint32_t HSOFIEC:1; /**< bit: 5 Host Start of Frame Interrupt Disable */ + uint32_t HWUPIEC:1; /**< bit: 6 Host Wake-Up Interrupt Disable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Disable */ + uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Disable */ + uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Disable */ + uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Disable */ + uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Disable */ + uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Disable */ + uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Disable */ + uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Disable */ + uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Disable */ + uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Disable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Disable */ + uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Disable */ + uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Disable */ + uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Disable */ + uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Disable */ + uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Disable */ + uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Disable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Disable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Disable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTIDR_OFFSET (0x414) /**< (USBHS_HSTIDR) Host Global Interrupt Disable Register Offset */ + +#define USBHS_HSTIDR_DCONNIEC_Pos 0 /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Position */ +#define USBHS_HSTIDR_DCONNIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DCONNIEC_Pos) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DCONNIEC USBHS_HSTIDR_DCONNIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DCONNIEC_Msk instead */ +#define USBHS_HSTIDR_DDISCIEC_Pos 1 /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Position */ +#define USBHS_HSTIDR_DDISCIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DDISCIEC_Pos) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DDISCIEC USBHS_HSTIDR_DDISCIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DDISCIEC_Msk instead */ +#define USBHS_HSTIDR_RSTIEC_Pos 2 /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSTIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSTIEC_Pos) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSTIEC USBHS_HSTIDR_RSTIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RSTIEC_Msk instead */ +#define USBHS_HSTIDR_RSMEDIEC_Pos 3 /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSMEDIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSMEDIEC_Pos) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSMEDIEC USBHS_HSTIDR_RSMEDIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RSMEDIEC_Msk instead */ +#define USBHS_HSTIDR_RXRSMIEC_Pos 4 /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Position */ +#define USBHS_HSTIDR_RXRSMIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RXRSMIEC_Pos) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Mask */ +#define USBHS_HSTIDR_RXRSMIEC USBHS_HSTIDR_RXRSMIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RXRSMIEC_Msk instead */ +#define USBHS_HSTIDR_HSOFIEC_Pos 5 /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Position */ +#define USBHS_HSTIDR_HSOFIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HSOFIEC_Pos) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Mask */ +#define USBHS_HSTIDR_HSOFIEC USBHS_HSTIDR_HSOFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_HSOFIEC_Msk instead */ +#define USBHS_HSTIDR_HWUPIEC_Pos 6 /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Position */ +#define USBHS_HSTIDR_HWUPIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HWUPIEC_Pos) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Mask */ +#define USBHS_HSTIDR_HWUPIEC USBHS_HSTIDR_HWUPIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_HWUPIEC_Msk instead */ +#define USBHS_HSTIDR_PEP_0_Pos 8 /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_0_Pos) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_0 USBHS_HSTIDR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_0_Msk instead */ +#define USBHS_HSTIDR_PEP_1_Pos 9 /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_1_Pos) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_1 USBHS_HSTIDR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_1_Msk instead */ +#define USBHS_HSTIDR_PEP_2_Pos 10 /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_2_Pos) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_2 USBHS_HSTIDR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_2_Msk instead */ +#define USBHS_HSTIDR_PEP_3_Pos 11 /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_3_Pos) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_3 USBHS_HSTIDR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_3_Msk instead */ +#define USBHS_HSTIDR_PEP_4_Pos 12 /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_4_Pos) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_4 USBHS_HSTIDR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_4_Msk instead */ +#define USBHS_HSTIDR_PEP_5_Pos 13 /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_5_Pos) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_5 USBHS_HSTIDR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_5_Msk instead */ +#define USBHS_HSTIDR_PEP_6_Pos 14 /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_6_Pos) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_6 USBHS_HSTIDR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_6_Msk instead */ +#define USBHS_HSTIDR_PEP_7_Pos 15 /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_7_Pos) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_7 USBHS_HSTIDR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_7_Msk instead */ +#define USBHS_HSTIDR_PEP_8_Pos 16 /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_8_Pos) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_8 USBHS_HSTIDR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_8_Msk instead */ +#define USBHS_HSTIDR_PEP_9_Pos 17 /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_9_Pos) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_9 USBHS_HSTIDR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_9_Msk instead */ +#define USBHS_HSTIDR_DMA_0_Pos 25 /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_0_Pos) /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_0 USBHS_HSTIDR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_0_Msk instead */ +#define USBHS_HSTIDR_DMA_1_Pos 26 /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_1_Pos) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_1 USBHS_HSTIDR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_1_Msk instead */ +#define USBHS_HSTIDR_DMA_2_Pos 27 /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_2_Pos) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_2 USBHS_HSTIDR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_2_Msk instead */ +#define USBHS_HSTIDR_DMA_3_Pos 28 /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_3_Pos) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_3 USBHS_HSTIDR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_3_Msk instead */ +#define USBHS_HSTIDR_DMA_4_Pos 29 /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_4_Pos) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_4 USBHS_HSTIDR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_4_Msk instead */ +#define USBHS_HSTIDR_DMA_5_Pos 30 /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_5_Pos) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_5 USBHS_HSTIDR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_5_Msk instead */ +#define USBHS_HSTIDR_DMA_6_Pos 31 /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_6_Pos) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_6 USBHS_HSTIDR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_6_Msk instead */ +#define USBHS_HSTIDR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIDR) Register MASK (Use USBHS_HSTIDR_Msk instead) */ +#define USBHS_HSTIDR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIDR) Register Mask */ + +#define USBHS_HSTIDR_PEP__Pos 8 /**< (USBHS_HSTIDR Position) Pipe x Interrupt Disable */ +#define USBHS_HSTIDR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIDR_PEP__Pos) /**< (USBHS_HSTIDR Mask) PEP_ */ +#define USBHS_HSTIDR_PEP_(value) (USBHS_HSTIDR_PEP__Msk & ((value) << USBHS_HSTIDR_PEP__Pos)) +#define USBHS_HSTIDR_DMA__Pos 25 /**< (USBHS_HSTIDR Position) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA__Msk (_U_(0x7F) << USBHS_HSTIDR_DMA__Pos) /**< (USBHS_HSTIDR Mask) DMA_ */ +#define USBHS_HSTIDR_DMA_(value) (USBHS_HSTIDR_DMA__Msk & ((value) << USBHS_HSTIDR_DMA__Pos)) + +/* -------- USBHS_HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DCONNIES:1; /**< bit: 0 Device Connection Interrupt Enable */ + uint32_t DDISCIES:1; /**< bit: 1 Device Disconnection Interrupt Enable */ + uint32_t RSTIES:1; /**< bit: 2 USB Reset Sent Interrupt Enable */ + uint32_t RSMEDIES:1; /**< bit: 3 Downstream Resume Sent Interrupt Enable */ + uint32_t RXRSMIES:1; /**< bit: 4 Upstream Resume Received Interrupt Enable */ + uint32_t HSOFIES:1; /**< bit: 5 Host Start of Frame Interrupt Enable */ + uint32_t HWUPIES:1; /**< bit: 6 Host Wake-Up Interrupt Enable */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Enable */ + uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Enable */ + uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Enable */ + uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Enable */ + uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Enable */ + uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Enable */ + uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Enable */ + uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Enable */ + uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Enable */ + uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Enable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Enable */ + uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Enable */ + uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Enable */ + uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Enable */ + uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Enable */ + uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Enable */ + uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Enable */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :8; /**< bit: 0..7 Reserved */ + uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Enable */ + uint32_t :7; /**< bit: 18..24 Reserved */ + uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Enable */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTIER_OFFSET (0x418) /**< (USBHS_HSTIER) Host Global Interrupt Enable Register Offset */ + +#define USBHS_HSTIER_DCONNIES_Pos 0 /**< (USBHS_HSTIER) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIER_DCONNIES_Msk (_U_(0x1) << USBHS_HSTIER_DCONNIES_Pos) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIER_DCONNIES USBHS_HSTIER_DCONNIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DCONNIES_Msk instead */ +#define USBHS_HSTIER_DDISCIES_Pos 1 /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIER_DDISCIES_Msk (_U_(0x1) << USBHS_HSTIER_DDISCIES_Pos) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIER_DDISCIES USBHS_HSTIER_DDISCIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DDISCIES_Msk instead */ +#define USBHS_HSTIER_RSTIES_Pos 2 /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSTIES_Msk (_U_(0x1) << USBHS_HSTIER_RSTIES_Pos) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSTIES USBHS_HSTIER_RSTIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RSTIES_Msk instead */ +#define USBHS_HSTIER_RSMEDIES_Pos 3 /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSMEDIES_Msk (_U_(0x1) << USBHS_HSTIER_RSMEDIES_Pos) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSMEDIES USBHS_HSTIER_RSMEDIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RSMEDIES_Msk instead */ +#define USBHS_HSTIER_RXRSMIES_Pos 4 /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIER_RXRSMIES_Msk (_U_(0x1) << USBHS_HSTIER_RXRSMIES_Pos) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIER_RXRSMIES USBHS_HSTIER_RXRSMIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RXRSMIES_Msk instead */ +#define USBHS_HSTIER_HSOFIES_Pos 5 /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIER_HSOFIES_Msk (_U_(0x1) << USBHS_HSTIER_HSOFIES_Pos) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIER_HSOFIES USBHS_HSTIER_HSOFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_HSOFIES_Msk instead */ +#define USBHS_HSTIER_HWUPIES_Pos 6 /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIER_HWUPIES_Msk (_U_(0x1) << USBHS_HSTIER_HWUPIES_Pos) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIER_HWUPIES USBHS_HSTIER_HWUPIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_HWUPIES_Msk instead */ +#define USBHS_HSTIER_PEP_0_Pos 8 /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_0_Msk (_U_(0x1) << USBHS_HSTIER_PEP_0_Pos) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_0 USBHS_HSTIER_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_0_Msk instead */ +#define USBHS_HSTIER_PEP_1_Pos 9 /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_1_Msk (_U_(0x1) << USBHS_HSTIER_PEP_1_Pos) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_1 USBHS_HSTIER_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_1_Msk instead */ +#define USBHS_HSTIER_PEP_2_Pos 10 /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_2_Msk (_U_(0x1) << USBHS_HSTIER_PEP_2_Pos) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_2 USBHS_HSTIER_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_2_Msk instead */ +#define USBHS_HSTIER_PEP_3_Pos 11 /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_3_Msk (_U_(0x1) << USBHS_HSTIER_PEP_3_Pos) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_3 USBHS_HSTIER_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_3_Msk instead */ +#define USBHS_HSTIER_PEP_4_Pos 12 /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_4_Msk (_U_(0x1) << USBHS_HSTIER_PEP_4_Pos) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_4 USBHS_HSTIER_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_4_Msk instead */ +#define USBHS_HSTIER_PEP_5_Pos 13 /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_5_Msk (_U_(0x1) << USBHS_HSTIER_PEP_5_Pos) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_5 USBHS_HSTIER_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_5_Msk instead */ +#define USBHS_HSTIER_PEP_6_Pos 14 /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_6_Msk (_U_(0x1) << USBHS_HSTIER_PEP_6_Pos) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_6 USBHS_HSTIER_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_6_Msk instead */ +#define USBHS_HSTIER_PEP_7_Pos 15 /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_7_Msk (_U_(0x1) << USBHS_HSTIER_PEP_7_Pos) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_7 USBHS_HSTIER_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_7_Msk instead */ +#define USBHS_HSTIER_PEP_8_Pos 16 /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_8_Msk (_U_(0x1) << USBHS_HSTIER_PEP_8_Pos) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_8 USBHS_HSTIER_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_8_Msk instead */ +#define USBHS_HSTIER_PEP_9_Pos 17 /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_9_Msk (_U_(0x1) << USBHS_HSTIER_PEP_9_Pos) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_9 USBHS_HSTIER_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_9_Msk instead */ +#define USBHS_HSTIER_DMA_0_Pos 25 /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_0_Msk (_U_(0x1) << USBHS_HSTIER_DMA_0_Pos) /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_0 USBHS_HSTIER_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_0_Msk instead */ +#define USBHS_HSTIER_DMA_1_Pos 26 /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_1_Msk (_U_(0x1) << USBHS_HSTIER_DMA_1_Pos) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_1 USBHS_HSTIER_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_1_Msk instead */ +#define USBHS_HSTIER_DMA_2_Pos 27 /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_2_Msk (_U_(0x1) << USBHS_HSTIER_DMA_2_Pos) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_2 USBHS_HSTIER_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_2_Msk instead */ +#define USBHS_HSTIER_DMA_3_Pos 28 /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_3_Msk (_U_(0x1) << USBHS_HSTIER_DMA_3_Pos) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_3 USBHS_HSTIER_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_3_Msk instead */ +#define USBHS_HSTIER_DMA_4_Pos 29 /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_4_Msk (_U_(0x1) << USBHS_HSTIER_DMA_4_Pos) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_4 USBHS_HSTIER_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_4_Msk instead */ +#define USBHS_HSTIER_DMA_5_Pos 30 /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_5_Msk (_U_(0x1) << USBHS_HSTIER_DMA_5_Pos) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_5 USBHS_HSTIER_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_5_Msk instead */ +#define USBHS_HSTIER_DMA_6_Pos 31 /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_6_Msk (_U_(0x1) << USBHS_HSTIER_DMA_6_Pos) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_6 USBHS_HSTIER_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_6_Msk instead */ +#define USBHS_HSTIER_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIER) Register MASK (Use USBHS_HSTIER_Msk instead) */ +#define USBHS_HSTIER_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIER) Register Mask */ + +#define USBHS_HSTIER_PEP__Pos 8 /**< (USBHS_HSTIER Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIER_PEP__Msk (_U_(0x3FF) << USBHS_HSTIER_PEP__Pos) /**< (USBHS_HSTIER Mask) PEP_ */ +#define USBHS_HSTIER_PEP_(value) (USBHS_HSTIER_PEP__Msk & ((value) << USBHS_HSTIER_PEP__Pos)) +#define USBHS_HSTIER_DMA__Pos 25 /**< (USBHS_HSTIER Position) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA__Msk (_U_(0x7F) << USBHS_HSTIER_DMA__Pos) /**< (USBHS_HSTIER Mask) DMA_ */ +#define USBHS_HSTIER_DMA_(value) (USBHS_HSTIER_DMA__Msk & ((value) << USBHS_HSTIER_DMA__Pos)) + +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PEN0:1; /**< bit: 0 Pipe 0 Enable */ + uint32_t PEN1:1; /**< bit: 1 Pipe 1 Enable */ + uint32_t PEN2:1; /**< bit: 2 Pipe 2 Enable */ + uint32_t PEN3:1; /**< bit: 3 Pipe 3 Enable */ + uint32_t PEN4:1; /**< bit: 4 Pipe 4 Enable */ + uint32_t PEN5:1; /**< bit: 5 Pipe 5 Enable */ + uint32_t PEN6:1; /**< bit: 6 Pipe 6 Enable */ + uint32_t PEN7:1; /**< bit: 7 Pipe 7 Enable */ + uint32_t PEN8:1; /**< bit: 8 Pipe 8 Enable */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t PRST0:1; /**< bit: 16 Pipe 0 Reset */ + uint32_t PRST1:1; /**< bit: 17 Pipe 1 Reset */ + uint32_t PRST2:1; /**< bit: 18 Pipe 2 Reset */ + uint32_t PRST3:1; /**< bit: 19 Pipe 3 Reset */ + uint32_t PRST4:1; /**< bit: 20 Pipe 4 Reset */ + uint32_t PRST5:1; /**< bit: 21 Pipe 5 Reset */ + uint32_t PRST6:1; /**< bit: 22 Pipe 6 Reset */ + uint32_t PRST7:1; /**< bit: 23 Pipe 7 Reset */ + uint32_t PRST8:1; /**< bit: 24 Pipe 8 Reset */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t PEN:9; /**< bit: 0..8 Pipe x Enable */ + uint32_t :7; /**< bit: 9..15 Reserved */ + uint32_t PRST:9; /**< bit: 16..24 Pipe 8 Reset */ + uint32_t :7; /**< bit: 25..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIP_OFFSET (0x41C) /**< (USBHS_HSTPIP) Host Pipe Register Offset */ + +#define USBHS_HSTPIP_PEN0_Pos 0 /**< (USBHS_HSTPIP) Pipe 0 Enable Position */ +#define USBHS_HSTPIP_PEN0_Msk (_U_(0x1) << USBHS_HSTPIP_PEN0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Enable Mask */ +#define USBHS_HSTPIP_PEN0 USBHS_HSTPIP_PEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN0_Msk instead */ +#define USBHS_HSTPIP_PEN1_Pos 1 /**< (USBHS_HSTPIP) Pipe 1 Enable Position */ +#define USBHS_HSTPIP_PEN1_Msk (_U_(0x1) << USBHS_HSTPIP_PEN1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Enable Mask */ +#define USBHS_HSTPIP_PEN1 USBHS_HSTPIP_PEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN1_Msk instead */ +#define USBHS_HSTPIP_PEN2_Pos 2 /**< (USBHS_HSTPIP) Pipe 2 Enable Position */ +#define USBHS_HSTPIP_PEN2_Msk (_U_(0x1) << USBHS_HSTPIP_PEN2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Enable Mask */ +#define USBHS_HSTPIP_PEN2 USBHS_HSTPIP_PEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN2_Msk instead */ +#define USBHS_HSTPIP_PEN3_Pos 3 /**< (USBHS_HSTPIP) Pipe 3 Enable Position */ +#define USBHS_HSTPIP_PEN3_Msk (_U_(0x1) << USBHS_HSTPIP_PEN3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Enable Mask */ +#define USBHS_HSTPIP_PEN3 USBHS_HSTPIP_PEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN3_Msk instead */ +#define USBHS_HSTPIP_PEN4_Pos 4 /**< (USBHS_HSTPIP) Pipe 4 Enable Position */ +#define USBHS_HSTPIP_PEN4_Msk (_U_(0x1) << USBHS_HSTPIP_PEN4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Enable Mask */ +#define USBHS_HSTPIP_PEN4 USBHS_HSTPIP_PEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN4_Msk instead */ +#define USBHS_HSTPIP_PEN5_Pos 5 /**< (USBHS_HSTPIP) Pipe 5 Enable Position */ +#define USBHS_HSTPIP_PEN5_Msk (_U_(0x1) << USBHS_HSTPIP_PEN5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Enable Mask */ +#define USBHS_HSTPIP_PEN5 USBHS_HSTPIP_PEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN5_Msk instead */ +#define USBHS_HSTPIP_PEN6_Pos 6 /**< (USBHS_HSTPIP) Pipe 6 Enable Position */ +#define USBHS_HSTPIP_PEN6_Msk (_U_(0x1) << USBHS_HSTPIP_PEN6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Enable Mask */ +#define USBHS_HSTPIP_PEN6 USBHS_HSTPIP_PEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN6_Msk instead */ +#define USBHS_HSTPIP_PEN7_Pos 7 /**< (USBHS_HSTPIP) Pipe 7 Enable Position */ +#define USBHS_HSTPIP_PEN7_Msk (_U_(0x1) << USBHS_HSTPIP_PEN7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Enable Mask */ +#define USBHS_HSTPIP_PEN7 USBHS_HSTPIP_PEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN7_Msk instead */ +#define USBHS_HSTPIP_PEN8_Pos 8 /**< (USBHS_HSTPIP) Pipe 8 Enable Position */ +#define USBHS_HSTPIP_PEN8_Msk (_U_(0x1) << USBHS_HSTPIP_PEN8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Enable Mask */ +#define USBHS_HSTPIP_PEN8 USBHS_HSTPIP_PEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN8_Msk instead */ +#define USBHS_HSTPIP_PRST0_Pos 16 /**< (USBHS_HSTPIP) Pipe 0 Reset Position */ +#define USBHS_HSTPIP_PRST0_Msk (_U_(0x1) << USBHS_HSTPIP_PRST0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Reset Mask */ +#define USBHS_HSTPIP_PRST0 USBHS_HSTPIP_PRST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST0_Msk instead */ +#define USBHS_HSTPIP_PRST1_Pos 17 /**< (USBHS_HSTPIP) Pipe 1 Reset Position */ +#define USBHS_HSTPIP_PRST1_Msk (_U_(0x1) << USBHS_HSTPIP_PRST1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Reset Mask */ +#define USBHS_HSTPIP_PRST1 USBHS_HSTPIP_PRST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST1_Msk instead */ +#define USBHS_HSTPIP_PRST2_Pos 18 /**< (USBHS_HSTPIP) Pipe 2 Reset Position */ +#define USBHS_HSTPIP_PRST2_Msk (_U_(0x1) << USBHS_HSTPIP_PRST2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Reset Mask */ +#define USBHS_HSTPIP_PRST2 USBHS_HSTPIP_PRST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST2_Msk instead */ +#define USBHS_HSTPIP_PRST3_Pos 19 /**< (USBHS_HSTPIP) Pipe 3 Reset Position */ +#define USBHS_HSTPIP_PRST3_Msk (_U_(0x1) << USBHS_HSTPIP_PRST3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Reset Mask */ +#define USBHS_HSTPIP_PRST3 USBHS_HSTPIP_PRST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST3_Msk instead */ +#define USBHS_HSTPIP_PRST4_Pos 20 /**< (USBHS_HSTPIP) Pipe 4 Reset Position */ +#define USBHS_HSTPIP_PRST4_Msk (_U_(0x1) << USBHS_HSTPIP_PRST4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Reset Mask */ +#define USBHS_HSTPIP_PRST4 USBHS_HSTPIP_PRST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST4_Msk instead */ +#define USBHS_HSTPIP_PRST5_Pos 21 /**< (USBHS_HSTPIP) Pipe 5 Reset Position */ +#define USBHS_HSTPIP_PRST5_Msk (_U_(0x1) << USBHS_HSTPIP_PRST5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Reset Mask */ +#define USBHS_HSTPIP_PRST5 USBHS_HSTPIP_PRST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST5_Msk instead */ +#define USBHS_HSTPIP_PRST6_Pos 22 /**< (USBHS_HSTPIP) Pipe 6 Reset Position */ +#define USBHS_HSTPIP_PRST6_Msk (_U_(0x1) << USBHS_HSTPIP_PRST6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Reset Mask */ +#define USBHS_HSTPIP_PRST6 USBHS_HSTPIP_PRST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST6_Msk instead */ +#define USBHS_HSTPIP_PRST7_Pos 23 /**< (USBHS_HSTPIP) Pipe 7 Reset Position */ +#define USBHS_HSTPIP_PRST7_Msk (_U_(0x1) << USBHS_HSTPIP_PRST7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Reset Mask */ +#define USBHS_HSTPIP_PRST7 USBHS_HSTPIP_PRST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST7_Msk instead */ +#define USBHS_HSTPIP_PRST8_Pos 24 /**< (USBHS_HSTPIP) Pipe 8 Reset Position */ +#define USBHS_HSTPIP_PRST8_Msk (_U_(0x1) << USBHS_HSTPIP_PRST8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Reset Mask */ +#define USBHS_HSTPIP_PRST8 USBHS_HSTPIP_PRST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST8_Msk instead */ +#define USBHS_HSTPIP_MASK _U_(0x1FF01FF) /**< \deprecated (USBHS_HSTPIP) Register MASK (Use USBHS_HSTPIP_Msk instead) */ +#define USBHS_HSTPIP_Msk _U_(0x1FF01FF) /**< (USBHS_HSTPIP) Register Mask */ + +#define USBHS_HSTPIP_PEN_Pos 0 /**< (USBHS_HSTPIP Position) Pipe x Enable */ +#define USBHS_HSTPIP_PEN_Msk (_U_(0x1FF) << USBHS_HSTPIP_PEN_Pos) /**< (USBHS_HSTPIP Mask) PEN */ +#define USBHS_HSTPIP_PEN(value) (USBHS_HSTPIP_PEN_Msk & ((value) << USBHS_HSTPIP_PEN_Pos)) +#define USBHS_HSTPIP_PRST_Pos 16 /**< (USBHS_HSTPIP Position) Pipe 8 Reset */ +#define USBHS_HSTPIP_PRST_Msk (_U_(0x1FF) << USBHS_HSTPIP_PRST_Pos) /**< (USBHS_HSTPIP Mask) PRST */ +#define USBHS_HSTPIP_PRST(value) (USBHS_HSTPIP_PRST_Msk & ((value) << USBHS_HSTPIP_PRST_Pos)) + +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t MFNUM:3; /**< bit: 0..2 Micro Frame Number */ + uint32_t FNUM:11; /**< bit: 3..13 Frame Number */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t FLENHIGH:8; /**< bit: 16..23 Frame Length */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTFNUM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTFNUM_OFFSET (0x420) /**< (USBHS_HSTFNUM) Host Frame Number Register Offset */ + +#define USBHS_HSTFNUM_MFNUM_Pos 0 /**< (USBHS_HSTFNUM) Micro Frame Number Position */ +#define USBHS_HSTFNUM_MFNUM_Msk (_U_(0x7) << USBHS_HSTFNUM_MFNUM_Pos) /**< (USBHS_HSTFNUM) Micro Frame Number Mask */ +#define USBHS_HSTFNUM_MFNUM(value) (USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)) +#define USBHS_HSTFNUM_FNUM_Pos 3 /**< (USBHS_HSTFNUM) Frame Number Position */ +#define USBHS_HSTFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_HSTFNUM_FNUM_Pos) /**< (USBHS_HSTFNUM) Frame Number Mask */ +#define USBHS_HSTFNUM_FNUM(value) (USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 /**< (USBHS_HSTFNUM) Frame Length Position */ +#define USBHS_HSTFNUM_FLENHIGH_Msk (_U_(0xFF) << USBHS_HSTFNUM_FLENHIGH_Pos) /**< (USBHS_HSTFNUM) Frame Length Mask */ +#define USBHS_HSTFNUM_FLENHIGH(value) (USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)) +#define USBHS_HSTFNUM_MASK _U_(0xFF3FFF) /**< \deprecated (USBHS_HSTFNUM) Register MASK (Use USBHS_HSTFNUM_Msk instead) */ +#define USBHS_HSTFNUM_Msk _U_(0xFF3FFF) /**< (USBHS_HSTFNUM) Register Mask */ + + +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HSTADDRP0:7; /**< bit: 0..6 USB Host Address */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t HSTADDRP1:7; /**< bit: 8..14 USB Host Address */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t HSTADDRP2:7; /**< bit: 16..22 USB Host Address */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t HSTADDRP3:7; /**< bit: 24..30 USB Host Address */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTADDR1_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTADDR1_OFFSET (0x424) /**< (USBHS_HSTADDR1) Host Address 1 Register Offset */ + +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP0_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP0(value) (USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP1_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP1(value) (USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP2_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP2(value) (USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP3_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP3(value) (USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)) +#define USBHS_HSTADDR1_MASK _U_(0x7F7F7F7F) /**< \deprecated (USBHS_HSTADDR1) Register MASK (Use USBHS_HSTADDR1_Msk instead) */ +#define USBHS_HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR1) Register Mask */ + + +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HSTADDRP4:7; /**< bit: 0..6 USB Host Address */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t HSTADDRP5:7; /**< bit: 8..14 USB Host Address */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t HSTADDRP6:7; /**< bit: 16..22 USB Host Address */ + uint32_t :1; /**< bit: 23 Reserved */ + uint32_t HSTADDRP7:7; /**< bit: 24..30 USB Host Address */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTADDR2_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTADDR2_OFFSET (0x428) /**< (USBHS_HSTADDR2) Host Address 2 Register Offset */ + +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP4_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP4(value) (USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP5_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP5(value) (USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP6_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP6(value) (USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP7_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP7(value) (USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)) +#define USBHS_HSTADDR2_MASK _U_(0x7F7F7F7F) /**< \deprecated (USBHS_HSTADDR2) Register MASK (Use USBHS_HSTADDR2_Msk instead) */ +#define USBHS_HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR2) Register Mask */ + + +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t HSTADDRP8:7; /**< bit: 0..6 USB Host Address */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t HSTADDRP9:7; /**< bit: 8..14 USB Host Address */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTADDR3_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTADDR3_OFFSET (0x42C) /**< (USBHS_HSTADDR3) Host Address 3 Register Offset */ + +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP8_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP8(value) (USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP9_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP9(value) (USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)) +#define USBHS_HSTADDR3_MASK _U_(0x7F7F) /**< \deprecated (USBHS_HSTADDR3) Register MASK (Use USBHS_HSTADDR3_Msk instead) */ +#define USBHS_HSTADDR3_Msk _U_(0x7F7F) /**< (USBHS_HSTADDR3) Register Mask */ + + +/* -------- USBHS_HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :1; /**< bit: 0 Reserved */ + uint32_t ALLOC:1; /**< bit: 1 Pipe Memory Allocate */ + uint32_t PBK:2; /**< bit: 2..3 Pipe Banks */ + uint32_t PSIZE:3; /**< bit: 4..6 Pipe Size */ + uint32_t :1; /**< bit: 7 Reserved */ + uint32_t PTOKEN:2; /**< bit: 8..9 Pipe Token */ + uint32_t AUTOSW:1; /**< bit: 10 Automatic Switch */ + uint32_t :1; /**< bit: 11 Reserved */ + uint32_t PTYPE:2; /**< bit: 12..13 Pipe Type */ + uint32_t :2; /**< bit: 14..15 Reserved */ + uint32_t PEPNUM:4; /**< bit: 16..19 Pipe Endpoint Number */ + uint32_t :4; /**< bit: 20..23 Reserved */ + uint32_t INTFRQ:8; /**< bit: 24..31 Pipe Interrupt Request Frequency */ + } bit; /**< Structure used for bit access */ + struct { // CTRL_BULK mode + uint32_t :20; /**< bit: 0..19 Reserved */ + uint32_t PINGEN:1; /**< bit: 20 Ping Enable */ + uint32_t :3; /**< bit: 21..23 Reserved */ + uint32_t BINTERVAL:8; /**< bit: 24..31 bInterval Parameter for the Bulk-Out/Ping Transaction */ + } CTRL_BULK; /**< Structure used for CTRL_BULK mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPCFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPCFG_OFFSET (0x500) /**< (USBHS_HSTPIPCFG) Host Pipe Configuration Register Offset */ + +#define USBHS_HSTPIPCFG_ALLOC_Pos 1 /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Position */ +#define USBHS_HSTPIPCFG_ALLOC_Msk (_U_(0x1) << USBHS_HSTPIPCFG_ALLOC_Pos) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Mask */ +#define USBHS_HSTPIPCFG_ALLOC USBHS_HSTPIPCFG_ALLOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_ALLOC_Msk instead */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 /**< (USBHS_HSTPIPCFG) Pipe Banks Position */ +#define USBHS_HSTPIPCFG_PBK_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Pipe Banks Mask */ +#define USBHS_HSTPIPCFG_PBK(value) (USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)) +#define USBHS_HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_1_BANK (USBHS_HSTPIPCFG_PBK_1_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Single-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (USBHS_HSTPIPCFG_PBK_2_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Double-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (USBHS_HSTPIPCFG_PBK_3_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Triple-bank pipe Position */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 /**< (USBHS_HSTPIPCFG) Pipe Size Position */ +#define USBHS_HSTPIPCFG_PSIZE_Msk (_U_(0x7) << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Size Mask */ +#define USBHS_HSTPIPCFG_PSIZE(value) (USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_HSTPIPCFG) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_HSTPIPCFG) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_HSTPIPCFG) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_HSTPIPCFG) 1024 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 8 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 16 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 32 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 64 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 128 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 256 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 512 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 1024 bytes Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 /**< (USBHS_HSTPIPCFG) Pipe Token Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) Pipe Token Mask */ +#define USBHS_HSTPIPCFG_PTOKEN(value) (USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) OUT */ +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (USBHS_HSTPIPCFG_PTOKEN_SETUP_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) SETUP Position */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (USBHS_HSTPIPCFG_PTOKEN_IN_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) IN Position */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (USBHS_HSTPIPCFG_PTOKEN_OUT_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) OUT Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Pos 10 /**< (USBHS_HSTPIPCFG) Automatic Switch Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Msk (_U_(0x1) << USBHS_HSTPIPCFG_AUTOSW_Pos) /**< (USBHS_HSTPIPCFG) Automatic Switch Mask */ +#define USBHS_HSTPIPCFG_AUTOSW USBHS_HSTPIPCFG_AUTOSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_AUTOSW_Msk instead */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 /**< (USBHS_HSTPIPCFG) Pipe Type Position */ +#define USBHS_HSTPIPCFG_PTYPE_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Type Mask */ +#define USBHS_HSTPIPCFG_PTYPE(value) (USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)) +#define USBHS_HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) Interrupt */ +#define USBHS_HSTPIPCFG_PTYPE_CTRL (USBHS_HSTPIPCFG_PTYPE_CTRL_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Control Position */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (USBHS_HSTPIPCFG_PTYPE_ISO_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Isochronous Position */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (USBHS_HSTPIPCFG_PTYPE_BLK_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Bulk Position */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (USBHS_HSTPIPCFG_PTYPE_INTRPT_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Interrupt Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Msk (_U_(0xF) << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Mask */ +#define USBHS_HSTPIPCFG_PEPNUM(value) (USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Position */ +#define USBHS_HSTPIPCFG_INTFRQ_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ +#define USBHS_HSTPIPCFG_INTFRQ(value) (USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)) +#define USBHS_HSTPIPCFG_MASK _U_(0xFF0F377E) /**< \deprecated (USBHS_HSTPIPCFG) Register MASK (Use USBHS_HSTPIPCFG_Msk instead) */ +#define USBHS_HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (USBHS_HSTPIPCFG) Register Mask */ + +/* CTRL_BULK mode */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20 /**< (USBHS_HSTPIPCFG) Ping Enable Position */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk (_U_(0x1) << USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos) /**< (USBHS_HSTPIPCFG) Ping Enable Mask */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk instead */ +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24 /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(value) (USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos)) +#define USBHS_HSTPIPCFG_CTRL_BULK_MASK _U_(0xFF100000) /**< \deprecated (USBHS_HSTPIPCFG_CTRL_BULK) Register MASK (Use USBHS_HSTPIPCFG_CTRL_BULK_Msk instead) */ +#define USBHS_HSTPIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (USBHS_HSTPIPCFG_CTRL_BULK) Register Mask */ + + +/* -------- USBHS_HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINI:1; /**< bit: 0 Received IN Data Interrupt */ + uint32_t TXOUTI:1; /**< bit: 1 Transmitted OUT Data Interrupt */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t PERRI:1; /**< bit: 3 Pipe Error Interrupt */ + uint32_t NAKEDI:1; /**< bit: 4 NAKed Interrupt */ + uint32_t OVERFI:1; /**< bit: 5 Overflow Interrupt */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETI:1; /**< bit: 7 Short Packet Interrupt */ + uint32_t DTSEQ:2; /**< bit: 8..9 Data Toggle Sequence */ + uint32_t :2; /**< bit: 10..11 Reserved */ + uint32_t NBUSYBK:2; /**< bit: 12..13 Number of Busy Banks */ + uint32_t CURRBK:2; /**< bit: 14..15 Current Bank */ + uint32_t RWALL:1; /**< bit: 16 Read/Write Allowed */ + uint32_t :1; /**< bit: 17 Reserved */ + uint32_t CFGOK:1; /**< bit: 18 Configuration OK Status */ + uint32_t :1; /**< bit: 19 Reserved */ + uint32_t PBYCT:11; /**< bit: 20..30 Pipe Byte Count */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPI:1; /**< bit: 2 Transmitted SETUP Interrupt */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERRI:1; /**< bit: 6 CRC Error Interrupt */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPI:1; /**< bit: 2 Transmitted SETUP Interrupt */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPISR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPISR_OFFSET (0x530) /**< (USBHS_HSTPIPISR) Host Pipe Status Register Offset */ + +#define USBHS_HSTPIPISR_RXINI_Pos 0 /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Position */ +#define USBHS_HSTPIPISR_RXINI_Msk (_U_(0x1) << USBHS_HSTPIPISR_RXINI_Pos) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Mask */ +#define USBHS_HSTPIPISR_RXINI USBHS_HSTPIPISR_RXINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_RXINI_Msk instead */ +#define USBHS_HSTPIPISR_TXOUTI_Pos 1 /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Position */ +#define USBHS_HSTPIPISR_TXOUTI_Msk (_U_(0x1) << USBHS_HSTPIPISR_TXOUTI_Pos) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Mask */ +#define USBHS_HSTPIPISR_TXOUTI USBHS_HSTPIPISR_TXOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_TXOUTI_Msk instead */ +#define USBHS_HSTPIPISR_PERRI_Pos 3 /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Position */ +#define USBHS_HSTPIPISR_PERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_PERRI_Pos) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Mask */ +#define USBHS_HSTPIPISR_PERRI USBHS_HSTPIPISR_PERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_PERRI_Msk instead */ +#define USBHS_HSTPIPISR_NAKEDI_Pos 4 /**< (USBHS_HSTPIPISR) NAKed Interrupt Position */ +#define USBHS_HSTPIPISR_NAKEDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_NAKEDI_Pos) /**< (USBHS_HSTPIPISR) NAKed Interrupt Mask */ +#define USBHS_HSTPIPISR_NAKEDI USBHS_HSTPIPISR_NAKEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_NAKEDI_Msk instead */ +#define USBHS_HSTPIPISR_OVERFI_Pos 5 /**< (USBHS_HSTPIPISR) Overflow Interrupt Position */ +#define USBHS_HSTPIPISR_OVERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_OVERFI_Pos) /**< (USBHS_HSTPIPISR) Overflow Interrupt Mask */ +#define USBHS_HSTPIPISR_OVERFI USBHS_HSTPIPISR_OVERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_OVERFI_Msk instead */ +#define USBHS_HSTPIPISR_SHORTPACKETI_Pos 7 /**< (USBHS_HSTPIPISR) Short Packet Interrupt Position */ +#define USBHS_HSTPIPISR_SHORTPACKETI_Msk (_U_(0x1) << USBHS_HSTPIPISR_SHORTPACKETI_Pos) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Mask */ +#define USBHS_HSTPIPISR_SHORTPACKETI USBHS_HSTPIPISR_SHORTPACKETI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_SHORTPACKETI_Msk instead */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 /**< (USBHS_HSTPIPISR) Data Toggle Sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_Msk (_U_(0x3) << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Mask */ +#define USBHS_HSTPIPISR_DTSEQ(value) (USBHS_HSTPIPISR_DTSEQ_Msk & ((value) << USBHS_HSTPIPISR_DTSEQ_Pos)) +#define USBHS_HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (USBHS_HSTPIPISR_DTSEQ_DATA0_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data0 toggle sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (USBHS_HSTPIPISR_DTSEQ_DATA1_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data1 toggle sequence Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 /**< (USBHS_HSTPIPISR) Number of Busy Banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) Number of Busy Banks Mask */ +#define USBHS_HSTPIPISR_NBUSYBK(value) (USBHS_HSTPIPISR_NBUSYBK_Msk & ((value) << USBHS_HSTPIPISR_NBUSYBK_Pos)) +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_HSTPIPISR) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_HSTPIPISR) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_HSTPIPISR) 3 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) Position */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 1 busy bank Position */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 2 busy banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 3 busy banks Position */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 /**< (USBHS_HSTPIPISR) Current Bank Position */ +#define USBHS_HSTPIPISR_CURRBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current Bank Mask */ +#define USBHS_HSTPIPISR_CURRBK(value) (USBHS_HSTPIPISR_CURRBK_Msk & ((value) << USBHS_HSTPIPISR_CURRBK_Pos)) +#define USBHS_HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_HSTPIPISR) Current bank is bank2 */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (USBHS_HSTPIPISR_CURRBK_BANK0_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank0 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (USBHS_HSTPIPISR_CURRBK_BANK1_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank1 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (USBHS_HSTPIPISR_CURRBK_BANK2_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank2 Position */ +#define USBHS_HSTPIPISR_RWALL_Pos 16 /**< (USBHS_HSTPIPISR) Read/Write Allowed Position */ +#define USBHS_HSTPIPISR_RWALL_Msk (_U_(0x1) << USBHS_HSTPIPISR_RWALL_Pos) /**< (USBHS_HSTPIPISR) Read/Write Allowed Mask */ +#define USBHS_HSTPIPISR_RWALL USBHS_HSTPIPISR_RWALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_RWALL_Msk instead */ +#define USBHS_HSTPIPISR_CFGOK_Pos 18 /**< (USBHS_HSTPIPISR) Configuration OK Status Position */ +#define USBHS_HSTPIPISR_CFGOK_Msk (_U_(0x1) << USBHS_HSTPIPISR_CFGOK_Pos) /**< (USBHS_HSTPIPISR) Configuration OK Status Mask */ +#define USBHS_HSTPIPISR_CFGOK USBHS_HSTPIPISR_CFGOK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CFGOK_Msk instead */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 /**< (USBHS_HSTPIPISR) Pipe Byte Count Position */ +#define USBHS_HSTPIPISR_PBYCT_Msk (_U_(0x7FF) << USBHS_HSTPIPISR_PBYCT_Pos) /**< (USBHS_HSTPIPISR) Pipe Byte Count Mask */ +#define USBHS_HSTPIPISR_PBYCT(value) (USBHS_HSTPIPISR_PBYCT_Msk & ((value) << USBHS_HSTPIPISR_PBYCT_Pos)) +#define USBHS_HSTPIPISR_MASK _U_(0x7FF5F3BB) /**< \deprecated (USBHS_HSTPIPISR) Register MASK (Use USBHS_HSTPIPISR_Msk instead) */ +#define USBHS_HSTPIPISR_Msk _U_(0x7FF5F3BB) /**< (USBHS_HSTPIPISR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI_Pos 2 /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI USBHS_HSTPIPISR_CTRL_TXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CTRL_TXSTPI_Msk instead */ +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk instead */ +#define USBHS_HSTPIPISR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_CTRL) Register MASK (Use USBHS_HSTPIPISR_CTRL_Msk instead) */ +#define USBHS_HSTPIPISR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPISR_ISO_UNDERFI_Pos 2 /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ +#define USBHS_HSTPIPISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ +#define USBHS_HSTPIPISR_ISO_UNDERFI USBHS_HSTPIPISR_ISO_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_ISO_UNDERFI_Msk instead */ +#define USBHS_HSTPIPISR_ISO_CRCERRI_Pos 6 /**< (USBHS_HSTPIPISR) CRC Error Interrupt Position */ +#define USBHS_HSTPIPISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_CRCERRI_Pos) /**< (USBHS_HSTPIPISR) CRC Error Interrupt Mask */ +#define USBHS_HSTPIPISR_ISO_CRCERRI USBHS_HSTPIPISR_ISO_CRCERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_ISO_CRCERRI_Msk instead */ +#define USBHS_HSTPIPISR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_ISO) Register MASK (Use USBHS_HSTPIPISR_ISO_Msk instead) */ +#define USBHS_HSTPIPISR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPISR_BLK_TXSTPI_Pos 2 /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_BLK_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_BLK_TXSTPI USBHS_HSTPIPISR_BLK_TXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_BLK_TXSTPI_Msk instead */ +#define USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_BLK_RXSTALLDI USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk instead */ +#define USBHS_HSTPIPISR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_BLK) Register MASK (Use USBHS_HSTPIPISR_BLK_Msk instead) */ +#define USBHS_HSTPIPISR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos 2 /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk instead */ +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk instead */ +#define USBHS_HSTPIPISR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_INTRPT) Register MASK (Use USBHS_HSTPIPISR_INTRPT_Msk instead) */ +#define USBHS_HSTPIPISR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINIC:1; /**< bit: 0 Received IN Data Interrupt Clear */ + uint32_t TXOUTIC:1; /**< bit: 1 Transmitted OUT Data Interrupt Clear */ + uint32_t :2; /**< bit: 2..3 Reserved */ + uint32_t NAKEDIC:1; /**< bit: 4 NAKed Interrupt Clear */ + uint32_t OVERFIC:1; /**< bit: 5 Overflow Interrupt Clear */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETIC:1; /**< bit: 7 Short Packet Interrupt Clear */ + uint32_t :24; /**< bit: 8..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPIC:1; /**< bit: 2 Transmitted SETUP Interrupt Clear */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERRIC:1; /**< bit: 6 CRC Error Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPIC:1; /**< bit: 2 Transmitted SETUP Interrupt Clear */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPICR_OFFSET (0x560) /**< (USBHS_HSTPIPICR) Host Pipe Clear Register Offset */ + +#define USBHS_HSTPIPICR_RXINIC_Pos 0 /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_RXINIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_RXINIC_Pos) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_RXINIC USBHS_HSTPIPICR_RXINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_RXINIC_Msk instead */ +#define USBHS_HSTPIPICR_TXOUTIC_Pos 1 /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_TXOUTIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_TXOUTIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_TXOUTIC USBHS_HSTPIPICR_TXOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_TXOUTIC_Msk instead */ +#define USBHS_HSTPIPICR_NAKEDIC_Pos 4 /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_NAKEDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_NAKEDIC_Pos) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_NAKEDIC USBHS_HSTPIPICR_NAKEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_NAKEDIC_Msk instead */ +#define USBHS_HSTPIPICR_OVERFIC_Pos 5 /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_OVERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_OVERFIC_Pos) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_OVERFIC USBHS_HSTPIPICR_OVERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_OVERFIC_Msk instead */ +#define USBHS_HSTPIPICR_SHORTPACKETIC_Pos 7 /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Position */ +#define USBHS_HSTPIPICR_SHORTPACKETIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_SHORTPACKETIC USBHS_HSTPIPICR_SHORTPACKETIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_SHORTPACKETIC_Msk instead */ +#define USBHS_HSTPIPICR_MASK _U_(0xB3) /**< \deprecated (USBHS_HSTPIPICR) Register MASK (Use USBHS_HSTPIPICR_Msk instead) */ +#define USBHS_HSTPIPICR_Msk _U_(0xB3) /**< (USBHS_HSTPIPICR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos 2 /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk instead */ +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk instead */ +#define USBHS_HSTPIPICR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_CTRL) Register MASK (Use USBHS_HSTPIPICR_CTRL_Msk instead) */ +#define USBHS_HSTPIPICR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC_Pos 2 /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC USBHS_HSTPIPICR_ISO_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_ISO_UNDERFIC_Msk instead */ +#define USBHS_HSTPIPICR_ISO_CRCERRIC_Pos 6 /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Position */ +#define USBHS_HSTPIPICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_CRCERRIC_Pos) /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_ISO_CRCERRIC USBHS_HSTPIPICR_ISO_CRCERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_ISO_CRCERRIC_Msk instead */ +#define USBHS_HSTPIPICR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_ISO) Register MASK (Use USBHS_HSTPIPICR_ISO_Msk instead) */ +#define USBHS_HSTPIPICR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC_Pos 2 /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC USBHS_HSTPIPICR_BLK_TXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_BLK_TXSTPIC_Msk instead */ +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk instead */ +#define USBHS_HSTPIPICR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_BLK) Register MASK (Use USBHS_HSTPIPICR_BLK_Msk instead) */ +#define USBHS_HSTPIPICR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos 2 /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk instead */ +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk instead */ +#define USBHS_HSTPIPICR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_INTRPT) Register MASK (Use USBHS_HSTPIPICR_INTRPT_Msk instead) */ +#define USBHS_HSTPIPICR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINIS:1; /**< bit: 0 Received IN Data Interrupt Set */ + uint32_t TXOUTIS:1; /**< bit: 1 Transmitted OUT Data Interrupt Set */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t PERRIS:1; /**< bit: 3 Pipe Error Interrupt Set */ + uint32_t NAKEDIS:1; /**< bit: 4 NAKed Interrupt Set */ + uint32_t OVERFIS:1; /**< bit: 5 Overflow Interrupt Set */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETIS:1; /**< bit: 7 Short Packet Interrupt Set */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKS:1; /**< bit: 12 Number of Busy Banks Set */ + uint32_t :19; /**< bit: 13..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPIS:1; /**< bit: 2 Transmitted SETUP Interrupt Set */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERRIS:1; /**< bit: 6 CRC Error Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPIS:1; /**< bit: 2 Transmitted SETUP Interrupt Set */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPIFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPIFR_OFFSET (0x590) /**< (USBHS_HSTPIPIFR) Host Pipe Set Register Offset */ + +#define USBHS_HSTPIPIFR_RXINIS_Pos 0 /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_RXINIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_RXINIS_Pos) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_RXINIS USBHS_HSTPIPIFR_RXINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_RXINIS_Msk instead */ +#define USBHS_HSTPIPIFR_TXOUTIS_Pos 1 /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_TXOUTIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_TXOUTIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_TXOUTIS USBHS_HSTPIPIFR_TXOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_TXOUTIS_Msk instead */ +#define USBHS_HSTPIPIFR_PERRIS_Pos 3 /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Position */ +#define USBHS_HSTPIPIFR_PERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_PERRIS_Pos) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_PERRIS USBHS_HSTPIPIFR_PERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_PERRIS_Msk instead */ +#define USBHS_HSTPIPIFR_NAKEDIS_Pos 4 /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_NAKEDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NAKEDIS_Pos) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_NAKEDIS USBHS_HSTPIPIFR_NAKEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_NAKEDIS_Msk instead */ +#define USBHS_HSTPIPIFR_OVERFIS_Pos 5 /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_OVERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_OVERFIS_Pos) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_OVERFIS USBHS_HSTPIPIFR_OVERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_OVERFIS_Msk instead */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Pos 7 /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Position */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS USBHS_HSTPIPIFR_SHORTPACKETIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_SHORTPACKETIS_Msk instead */ +#define USBHS_HSTPIPIFR_NBUSYBKS_Pos 12 /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Position */ +#define USBHS_HSTPIPIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NBUSYBKS_Pos) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Mask */ +#define USBHS_HSTPIPIFR_NBUSYBKS USBHS_HSTPIPIFR_NBUSYBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_NBUSYBKS_Msk instead */ +#define USBHS_HSTPIPIFR_MASK _U_(0x10BB) /**< \deprecated (USBHS_HSTPIPIFR) Register MASK (Use USBHS_HSTPIPIFR_Msk instead) */ +#define USBHS_HSTPIPIFR_Msk _U_(0x10BB) /**< (USBHS_HSTPIPIFR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos 2 /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk instead */ +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk instead */ +#define USBHS_HSTPIPIFR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_CTRL) Register MASK (Use USBHS_HSTPIPIFR_CTRL_Msk instead) */ +#define USBHS_HSTPIPIFR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos 2 /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk instead */ +#define USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos 6 /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Position */ +#define USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos) /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_ISO_CRCERRIS USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk instead */ +#define USBHS_HSTPIPIFR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_ISO) Register MASK (Use USBHS_HSTPIPIFR_ISO_Msk instead) */ +#define USBHS_HSTPIPIFR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos 2 /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk instead */ +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk instead */ +#define USBHS_HSTPIPIFR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_BLK) Register MASK (Use USBHS_HSTPIPIFR_BLK_Msk instead) */ +#define USBHS_HSTPIPIFR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos 2 /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk instead */ +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk instead */ +#define USBHS_HSTPIPIFR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_INTRPT) Register MASK (Use USBHS_HSTPIPIFR_INTRPT_Msk instead) */ +#define USBHS_HSTPIPIFR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINE:1; /**< bit: 0 Received IN Data Interrupt Enable */ + uint32_t TXOUTE:1; /**< bit: 1 Transmitted OUT Data Interrupt Enable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t PERRE:1; /**< bit: 3 Pipe Error Interrupt Enable */ + uint32_t NAKEDE:1; /**< bit: 4 NAKed Interrupt Enable */ + uint32_t OVERFIE:1; /**< bit: 5 Overflow Interrupt Enable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETIE:1; /**< bit: 7 Short Packet Interrupt Enable */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKE:1; /**< bit: 12 Number of Busy Banks Interrupt Enable */ + uint32_t :1; /**< bit: 13 Reserved */ + uint32_t FIFOCON:1; /**< bit: 14 FIFO Control */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t PDISHDMA:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Enable */ + uint32_t PFREEZE:1; /**< bit: 17 Pipe Freeze */ + uint32_t RSTDT:1; /**< bit: 18 Reset Data Toggle */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPE:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIE:1; /**< bit: 2 Underflow Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERRE:1; /**< bit: 6 CRC Error Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPE:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIE:1; /**< bit: 2 Underflow Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPIMR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPIMR_OFFSET (0x5C0) /**< (USBHS_HSTPIPIMR) Host Pipe Mask Register Offset */ + +#define USBHS_HSTPIPIMR_RXINE_Pos 0 /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_RXINE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RXINE_Pos) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_RXINE USBHS_HSTPIPIMR_RXINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_RXINE_Msk instead */ +#define USBHS_HSTPIPIMR_TXOUTE_Pos 1 /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_TXOUTE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_TXOUTE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_TXOUTE USBHS_HSTPIPIMR_TXOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_TXOUTE_Msk instead */ +#define USBHS_HSTPIPIMR_PERRE_Pos 3 /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_PERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PERRE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_PERRE USBHS_HSTPIPIMR_PERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PERRE_Msk instead */ +#define USBHS_HSTPIPIMR_NAKEDE_Pos 4 /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NAKEDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NAKEDE_Pos) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NAKEDE USBHS_HSTPIPIMR_NAKEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_NAKEDE_Msk instead */ +#define USBHS_HSTPIPIMR_OVERFIE_Pos 5 /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_OVERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_OVERFIE_Pos) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_OVERFIE USBHS_HSTPIPIMR_OVERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_OVERFIE_Msk instead */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Pos 7 /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE USBHS_HSTPIPIMR_SHORTPACKETIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_SHORTPACKETIE_Msk instead */ +#define USBHS_HSTPIPIMR_NBUSYBKE_Pos 12 /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NBUSYBKE_Pos) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NBUSYBKE USBHS_HSTPIPIMR_NBUSYBKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_NBUSYBKE_Msk instead */ +#define USBHS_HSTPIPIMR_FIFOCON_Pos 14 /**< (USBHS_HSTPIPIMR) FIFO Control Position */ +#define USBHS_HSTPIPIMR_FIFOCON_Msk (_U_(0x1) << USBHS_HSTPIPIMR_FIFOCON_Pos) /**< (USBHS_HSTPIPIMR) FIFO Control Mask */ +#define USBHS_HSTPIPIMR_FIFOCON USBHS_HSTPIPIMR_FIFOCON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_FIFOCON_Msk instead */ +#define USBHS_HSTPIPIMR_PDISHDMA_Pos 16 /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIMR_PDISHDMA_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PDISHDMA_Pos) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIMR_PDISHDMA USBHS_HSTPIPIMR_PDISHDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PDISHDMA_Msk instead */ +#define USBHS_HSTPIPIMR_PFREEZE_Pos 17 /**< (USBHS_HSTPIPIMR) Pipe Freeze Position */ +#define USBHS_HSTPIPIMR_PFREEZE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PFREEZE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Freeze Mask */ +#define USBHS_HSTPIPIMR_PFREEZE USBHS_HSTPIPIMR_PFREEZE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PFREEZE_Msk instead */ +#define USBHS_HSTPIPIMR_RSTDT_Pos 18 /**< (USBHS_HSTPIPIMR) Reset Data Toggle Position */ +#define USBHS_HSTPIPIMR_RSTDT_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RSTDT_Pos) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Mask */ +#define USBHS_HSTPIPIMR_RSTDT USBHS_HSTPIPIMR_RSTDT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_RSTDT_Msk instead */ +#define USBHS_HSTPIPIMR_MASK _U_(0x750BB) /**< \deprecated (USBHS_HSTPIPIMR) Register MASK (Use USBHS_HSTPIPIMR_Msk instead) */ +#define USBHS_HSTPIPIMR_Msk _U_(0x750BB) /**< (USBHS_HSTPIPIMR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos 2 /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk instead */ +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk instead */ +#define USBHS_HSTPIPIMR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_CTRL) Register MASK (Use USBHS_HSTPIPIMR_CTRL_Msk instead) */ +#define USBHS_HSTPIPIMR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos 2 /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk instead */ +#define USBHS_HSTPIPIMR_ISO_CRCERRE_Pos 6 /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_CRCERRE_Pos) /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_ISO_CRCERRE USBHS_HSTPIPIMR_ISO_CRCERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_ISO_CRCERRE_Msk instead */ +#define USBHS_HSTPIPIMR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_ISO) Register MASK (Use USBHS_HSTPIPIMR_ISO_Msk instead) */ +#define USBHS_HSTPIPIMR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE_Pos 2 /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE USBHS_HSTPIPIMR_BLK_TXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_BLK_TXSTPE_Msk instead */ +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk instead */ +#define USBHS_HSTPIPIMR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_BLK) Register MASK (Use USBHS_HSTPIPIMR_BLK_Msk instead) */ +#define USBHS_HSTPIPIMR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos 2 /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk instead */ +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk instead */ +#define USBHS_HSTPIPIMR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_INTRPT) Register MASK (Use USBHS_HSTPIPIMR_INTRPT_Msk instead) */ +#define USBHS_HSTPIPIMR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINES:1; /**< bit: 0 Received IN Data Interrupt Enable */ + uint32_t TXOUTES:1; /**< bit: 1 Transmitted OUT Data Interrupt Enable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t PERRES:1; /**< bit: 3 Pipe Error Interrupt Enable */ + uint32_t NAKEDES:1; /**< bit: 4 NAKed Interrupt Enable */ + uint32_t OVERFIES:1; /**< bit: 5 Overflow Interrupt Enable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETIES:1; /**< bit: 7 Short Packet Interrupt Enable */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKES:1; /**< bit: 12 Number of Busy Banks Enable */ + uint32_t :3; /**< bit: 13..15 Reserved */ + uint32_t PDISHDMAS:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Enable */ + uint32_t PFREEZES:1; /**< bit: 17 Pipe Freeze Enable */ + uint32_t RSTDTS:1; /**< bit: 18 Reset Data Toggle Enable */ + uint32_t :13; /**< bit: 19..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPES:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIES:1; /**< bit: 2 Underflow Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERRES:1; /**< bit: 6 CRC Error Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPES:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIES:1; /**< bit: 2 Underflow Interrupt Enable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPIER_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPIER_OFFSET (0x5F0) /**< (USBHS_HSTPIPIER) Host Pipe Enable Register Offset */ + +#define USBHS_HSTPIPIER_RXINES_Pos 0 /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_RXINES_Msk (_U_(0x1) << USBHS_HSTPIPIER_RXINES_Pos) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_RXINES USBHS_HSTPIPIER_RXINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_RXINES_Msk instead */ +#define USBHS_HSTPIPIER_TXOUTES_Pos 1 /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_TXOUTES_Msk (_U_(0x1) << USBHS_HSTPIPIER_TXOUTES_Pos) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_TXOUTES USBHS_HSTPIPIER_TXOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_TXOUTES_Msk instead */ +#define USBHS_HSTPIPIER_PERRES_Pos 3 /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIER_PERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PERRES_Pos) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_PERRES USBHS_HSTPIPIER_PERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PERRES_Msk instead */ +#define USBHS_HSTPIPIER_NAKEDES_Pos 4 /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_NAKEDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NAKEDES_Pos) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_NAKEDES USBHS_HSTPIPIER_NAKEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_NAKEDES_Msk instead */ +#define USBHS_HSTPIPIER_OVERFIES_Pos 5 /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_OVERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_OVERFIES_Pos) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_OVERFIES USBHS_HSTPIPIER_OVERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_OVERFIES_Msk instead */ +#define USBHS_HSTPIPIER_SHORTPACKETIES_Pos 7 /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIER_SHORTPACKETIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_SHORTPACKETIES USBHS_HSTPIPIER_SHORTPACKETIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_SHORTPACKETIES_Msk instead */ +#define USBHS_HSTPIPIER_NBUSYBKES_Pos 12 /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Position */ +#define USBHS_HSTPIPIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NBUSYBKES_Pos) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Mask */ +#define USBHS_HSTPIPIER_NBUSYBKES USBHS_HSTPIPIER_NBUSYBKES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_NBUSYBKES_Msk instead */ +#define USBHS_HSTPIPIER_PDISHDMAS_Pos 16 /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIER_PDISHDMAS_Msk (_U_(0x1) << USBHS_HSTPIPIER_PDISHDMAS_Pos) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIER_PDISHDMAS USBHS_HSTPIPIER_PDISHDMAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PDISHDMAS_Msk instead */ +#define USBHS_HSTPIPIER_PFREEZES_Pos 17 /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Position */ +#define USBHS_HSTPIPIER_PFREEZES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PFREEZES_Pos) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Mask */ +#define USBHS_HSTPIPIER_PFREEZES USBHS_HSTPIPIER_PFREEZES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PFREEZES_Msk instead */ +#define USBHS_HSTPIPIER_RSTDTS_Pos 18 /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Position */ +#define USBHS_HSTPIPIER_RSTDTS_Msk (_U_(0x1) << USBHS_HSTPIPIER_RSTDTS_Pos) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Mask */ +#define USBHS_HSTPIPIER_RSTDTS USBHS_HSTPIPIER_RSTDTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_RSTDTS_Msk instead */ +#define USBHS_HSTPIPIER_MASK _U_(0x710BB) /**< \deprecated (USBHS_HSTPIPIER) Register MASK (Use USBHS_HSTPIPIER_Msk instead) */ +#define USBHS_HSTPIPIER_Msk _U_(0x710BB) /**< (USBHS_HSTPIPIER) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES_Pos 2 /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES USBHS_HSTPIPIER_CTRL_TXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_CTRL_TXSTPES_Msk instead */ +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk instead */ +#define USBHS_HSTPIPIER_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_CTRL) Register MASK (Use USBHS_HSTPIPIER_CTRL_Msk instead) */ +#define USBHS_HSTPIPIER_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES_Pos 2 /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES USBHS_HSTPIPIER_ISO_UNDERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_ISO_UNDERFIES_Msk instead */ +#define USBHS_HSTPIPIER_ISO_CRCERRES_Pos 6 /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Position */ +#define USBHS_HSTPIPIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_CRCERRES_Pos) /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_ISO_CRCERRES USBHS_HSTPIPIER_ISO_CRCERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_ISO_CRCERRES_Msk instead */ +#define USBHS_HSTPIPIER_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_ISO) Register MASK (Use USBHS_HSTPIPIER_ISO_Msk instead) */ +#define USBHS_HSTPIPIER_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIER_BLK_TXSTPES_Pos 2 /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_BLK_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_BLK_TXSTPES USBHS_HSTPIPIER_BLK_TXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_BLK_TXSTPES_Msk instead */ +#define USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_BLK_RXSTALLDES USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk instead */ +#define USBHS_HSTPIPIER_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_BLK) Register MASK (Use USBHS_HSTPIPIER_BLK_Msk instead) */ +#define USBHS_HSTPIPIER_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos 2 /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk instead */ +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk instead */ +#define USBHS_HSTPIPIER_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_INTRPT) Register MASK (Use USBHS_HSTPIPIER_INTRPT_Msk instead) */ +#define USBHS_HSTPIPIER_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RXINEC:1; /**< bit: 0 Received IN Data Interrupt Disable */ + uint32_t TXOUTEC:1; /**< bit: 1 Transmitted OUT Data Interrupt Disable */ + uint32_t :1; /**< bit: 2 Reserved */ + uint32_t PERREC:1; /**< bit: 3 Pipe Error Interrupt Disable */ + uint32_t NAKEDEC:1; /**< bit: 4 NAKed Interrupt Disable */ + uint32_t OVERFIEC:1; /**< bit: 5 Overflow Interrupt Disable */ + uint32_t :1; /**< bit: 6 Reserved */ + uint32_t SHORTPACKETIEC:1; /**< bit: 7 Short Packet Interrupt Disable */ + uint32_t :4; /**< bit: 8..11 Reserved */ + uint32_t NBUSYBKEC:1; /**< bit: 12 Number of Busy Banks Disable */ + uint32_t :1; /**< bit: 13 Reserved */ + uint32_t FIFOCONC:1; /**< bit: 14 FIFO Control Disable */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t PDISHDMAC:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Disable */ + uint32_t PFREEZEC:1; /**< bit: 17 Pipe Freeze Disable */ + uint32_t :14; /**< bit: 18..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { // CTRL mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPEC:1; /**< bit: 2 Transmitted SETUP Interrupt Disable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } CTRL; /**< Structure used for CTRL mode access */ + struct { // ISO mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIEC:1; /**< bit: 2 Underflow Interrupt Disable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t CRCERREC:1; /**< bit: 6 CRC Error Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } ISO; /**< Structure used for ISO mode access */ + struct { // BLK mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t TXSTPEC:1; /**< bit: 2 Transmitted SETUP Interrupt Disable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } BLK; /**< Structure used for BLK mode access */ + struct { // INTRPT mode + uint32_t :2; /**< bit: 0..1 Reserved */ + uint32_t UNDERFIEC:1; /**< bit: 2 Underflow Interrupt Disable */ + uint32_t :3; /**< bit: 3..5 Reserved */ + uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } INTRPT; /**< Structure used for INTRPT mode access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPIDR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPIDR_OFFSET (0x620) /**< (USBHS_HSTPIPIDR) Host Pipe Disable Register Offset */ + +#define USBHS_HSTPIPIDR_RXINEC_Pos 0 /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_RXINEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_RXINEC_Pos) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_RXINEC USBHS_HSTPIPIDR_RXINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_RXINEC_Msk instead */ +#define USBHS_HSTPIPIDR_TXOUTEC_Pos 1 /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_TXOUTEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_TXOUTEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_TXOUTEC USBHS_HSTPIPIDR_TXOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_TXOUTEC_Msk instead */ +#define USBHS_HSTPIPIDR_PERREC_Pos 3 /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_PERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PERREC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_PERREC USBHS_HSTPIPIDR_PERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PERREC_Msk instead */ +#define USBHS_HSTPIPIDR_NAKEDEC_Pos 4 /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_NAKEDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NAKEDEC_Pos) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_NAKEDEC USBHS_HSTPIPIDR_NAKEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_NAKEDEC_Msk instead */ +#define USBHS_HSTPIPIDR_OVERFIEC_Pos 5 /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_OVERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_OVERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_OVERFIEC USBHS_HSTPIPIDR_OVERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_OVERFIEC_Msk instead */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos 7 /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk instead */ +#define USBHS_HSTPIPIDR_NBUSYBKEC_Pos 12 /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Position */ +#define USBHS_HSTPIPIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Mask */ +#define USBHS_HSTPIPIDR_NBUSYBKEC USBHS_HSTPIPIDR_NBUSYBKEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_NBUSYBKEC_Msk instead */ +#define USBHS_HSTPIPIDR_FIFOCONC_Pos 14 /**< (USBHS_HSTPIPIDR) FIFO Control Disable Position */ +#define USBHS_HSTPIPIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_FIFOCONC_Pos) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Mask */ +#define USBHS_HSTPIPIDR_FIFOCONC USBHS_HSTPIPIDR_FIFOCONC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_FIFOCONC_Msk instead */ +#define USBHS_HSTPIPIDR_PDISHDMAC_Pos 16 /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ +#define USBHS_HSTPIPIDR_PDISHDMAC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PDISHDMAC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ +#define USBHS_HSTPIPIDR_PDISHDMAC USBHS_HSTPIPIDR_PDISHDMAC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PDISHDMAC_Msk instead */ +#define USBHS_HSTPIPIDR_PFREEZEC_Pos 17 /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Position */ +#define USBHS_HSTPIPIDR_PFREEZEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PFREEZEC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Mask */ +#define USBHS_HSTPIPIDR_PFREEZEC USBHS_HSTPIPIDR_PFREEZEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PFREEZEC_Msk instead */ +#define USBHS_HSTPIPIDR_MASK _U_(0x350BB) /**< \deprecated (USBHS_HSTPIPIDR) Register MASK (Use USBHS_HSTPIPIDR_Msk instead) */ +#define USBHS_HSTPIPIDR_Msk _U_(0x350BB) /**< (USBHS_HSTPIPIDR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos 2 /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk instead */ +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk instead */ +#define USBHS_HSTPIPIDR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_CTRL) Register MASK (Use USBHS_HSTPIPIDR_CTRL_Msk instead) */ +#define USBHS_HSTPIPIDR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos 2 /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk instead */ +#define USBHS_HSTPIPIDR_ISO_CRCERREC_Pos 6 /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_ISO_CRCERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_CRCERREC_Pos) /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_ISO_CRCERREC USBHS_HSTPIPIDR_ISO_CRCERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_ISO_CRCERREC_Msk instead */ +#define USBHS_HSTPIPIDR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_ISO) Register MASK (Use USBHS_HSTPIPIDR_ISO_Msk instead) */ +#define USBHS_HSTPIPIDR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos 2 /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk instead */ +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk instead */ +#define USBHS_HSTPIPIDR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_BLK) Register MASK (Use USBHS_HSTPIPIDR_BLK_Msk instead) */ +#define USBHS_HSTPIPIDR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2 /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk instead */ +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk instead */ +#define USBHS_HSTPIPIDR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_INTRPT) Register MASK (Use USBHS_HSTPIPIDR_INTRPT_Msk instead) */ +#define USBHS_HSTPIPIDR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t INRQ:8; /**< bit: 0..7 IN Request Number before Freeze */ + uint32_t INMODE:1; /**< bit: 8 IN Request Mode */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPINRQ_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPINRQ_OFFSET (0x650) /**< (USBHS_HSTPIPINRQ) Host Pipe IN Request Register Offset */ + +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Position */ +#define USBHS_HSTPIPINRQ_INRQ_Msk (_U_(0xFF) << USBHS_HSTPIPINRQ_INRQ_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Mask */ +#define USBHS_HSTPIPINRQ_INRQ(value) (USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)) +#define USBHS_HSTPIPINRQ_INMODE_Pos 8 /**< (USBHS_HSTPIPINRQ) IN Request Mode Position */ +#define USBHS_HSTPIPINRQ_INMODE_Msk (_U_(0x1) << USBHS_HSTPIPINRQ_INMODE_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Mode Mask */ +#define USBHS_HSTPIPINRQ_INMODE USBHS_HSTPIPINRQ_INMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPINRQ_INMODE_Msk instead */ +#define USBHS_HSTPIPINRQ_MASK _U_(0x1FF) /**< \deprecated (USBHS_HSTPIPINRQ) Register MASK (Use USBHS_HSTPIPINRQ_Msk instead) */ +#define USBHS_HSTPIPINRQ_Msk _U_(0x1FF) /**< (USBHS_HSTPIPINRQ) Register Mask */ + + +/* -------- USBHS_HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DATATGL:1; /**< bit: 0 Data Toggle Error */ + uint32_t DATAPID:1; /**< bit: 1 Data PID Error */ + uint32_t PID:1; /**< bit: 2 Data PID Error */ + uint32_t TIMEOUT:1; /**< bit: 3 Time-Out Error */ + uint32_t CRC16:1; /**< bit: 4 CRC16 Error */ + uint32_t COUNTER:2; /**< bit: 5..6 Error Counter */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t CRC:1; /**< bit: 4 CRCx6 Error */ + uint32_t :27; /**< bit: 5..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_HSTPIPERR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_HSTPIPERR_OFFSET (0x680) /**< (USBHS_HSTPIPERR) Host Pipe Error Register Offset */ + +#define USBHS_HSTPIPERR_DATATGL_Pos 0 /**< (USBHS_HSTPIPERR) Data Toggle Error Position */ +#define USBHS_HSTPIPERR_DATATGL_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATATGL_Pos) /**< (USBHS_HSTPIPERR) Data Toggle Error Mask */ +#define USBHS_HSTPIPERR_DATATGL USBHS_HSTPIPERR_DATATGL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_DATATGL_Msk instead */ +#define USBHS_HSTPIPERR_DATAPID_Pos 1 /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_DATAPID_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATAPID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_DATAPID USBHS_HSTPIPERR_DATAPID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_DATAPID_Msk instead */ +#define USBHS_HSTPIPERR_PID_Pos 2 /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_PID_Msk (_U_(0x1) << USBHS_HSTPIPERR_PID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_PID USBHS_HSTPIPERR_PID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_PID_Msk instead */ +#define USBHS_HSTPIPERR_TIMEOUT_Pos 3 /**< (USBHS_HSTPIPERR) Time-Out Error Position */ +#define USBHS_HSTPIPERR_TIMEOUT_Msk (_U_(0x1) << USBHS_HSTPIPERR_TIMEOUT_Pos) /**< (USBHS_HSTPIPERR) Time-Out Error Mask */ +#define USBHS_HSTPIPERR_TIMEOUT USBHS_HSTPIPERR_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_TIMEOUT_Msk instead */ +#define USBHS_HSTPIPERR_CRC16_Pos 4 /**< (USBHS_HSTPIPERR) CRC16 Error Position */ +#define USBHS_HSTPIPERR_CRC16_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC16_Pos) /**< (USBHS_HSTPIPERR) CRC16 Error Mask */ +#define USBHS_HSTPIPERR_CRC16 USBHS_HSTPIPERR_CRC16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_CRC16_Msk instead */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 /**< (USBHS_HSTPIPERR) Error Counter Position */ +#define USBHS_HSTPIPERR_COUNTER_Msk (_U_(0x3) << USBHS_HSTPIPERR_COUNTER_Pos) /**< (USBHS_HSTPIPERR) Error Counter Mask */ +#define USBHS_HSTPIPERR_COUNTER(value) (USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)) +#define USBHS_HSTPIPERR_MASK _U_(0x7F) /**< \deprecated (USBHS_HSTPIPERR) Register MASK (Use USBHS_HSTPIPERR_Msk instead) */ +#define USBHS_HSTPIPERR_Msk _U_(0x7F) /**< (USBHS_HSTPIPERR) Register Mask */ + +#define USBHS_HSTPIPERR_CRC_Pos 4 /**< (USBHS_HSTPIPERR Position) CRCx6 Error */ +#define USBHS_HSTPIPERR_CRC_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC_Pos) /**< (USBHS_HSTPIPERR Mask) CRC */ +#define USBHS_HSTPIPERR_CRC(value) (USBHS_HSTPIPERR_CRC_Msk & ((value) << USBHS_HSTPIPERR_CRC_Pos)) + +/* -------- USBHS_CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t RDERRE:1; /**< bit: 4 Remote Device Connection Error Interrupt Enable */ + uint32_t :3; /**< bit: 5..7 Reserved */ + uint32_t VBUSHWC:1; /**< bit: 8 VBUS Hardware Control */ + uint32_t :5; /**< bit: 9..13 Reserved */ + uint32_t FRZCLK:1; /**< bit: 14 Freeze USB Clock */ + uint32_t USBE:1; /**< bit: 15 USBHS Enable */ + uint32_t :8; /**< bit: 16..23 Reserved */ + uint32_t UID:1; /**< bit: 24 UID Pin Enable */ + uint32_t UIMOD:1; /**< bit: 25 USBHS Mode */ + uint32_t :6; /**< bit: 26..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_CTRL_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_CTRL_OFFSET (0x800) /**< (USBHS_CTRL) General Control Register Offset */ + +#define USBHS_CTRL_RDERRE_Pos 4 /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Position */ +#define USBHS_CTRL_RDERRE_Msk (_U_(0x1) << USBHS_CTRL_RDERRE_Pos) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Mask */ +#define USBHS_CTRL_RDERRE USBHS_CTRL_RDERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_RDERRE_Msk instead */ +#define USBHS_CTRL_VBUSHWC_Pos 8 /**< (USBHS_CTRL) VBUS Hardware Control Position */ +#define USBHS_CTRL_VBUSHWC_Msk (_U_(0x1) << USBHS_CTRL_VBUSHWC_Pos) /**< (USBHS_CTRL) VBUS Hardware Control Mask */ +#define USBHS_CTRL_VBUSHWC USBHS_CTRL_VBUSHWC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_VBUSHWC_Msk instead */ +#define USBHS_CTRL_FRZCLK_Pos 14 /**< (USBHS_CTRL) Freeze USB Clock Position */ +#define USBHS_CTRL_FRZCLK_Msk (_U_(0x1) << USBHS_CTRL_FRZCLK_Pos) /**< (USBHS_CTRL) Freeze USB Clock Mask */ +#define USBHS_CTRL_FRZCLK USBHS_CTRL_FRZCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_FRZCLK_Msk instead */ +#define USBHS_CTRL_USBE_Pos 15 /**< (USBHS_CTRL) USBHS Enable Position */ +#define USBHS_CTRL_USBE_Msk (_U_(0x1) << USBHS_CTRL_USBE_Pos) /**< (USBHS_CTRL) USBHS Enable Mask */ +#define USBHS_CTRL_USBE USBHS_CTRL_USBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_USBE_Msk instead */ +#define USBHS_CTRL_UID_Pos 24 /**< (USBHS_CTRL) UID Pin Enable Position */ +#define USBHS_CTRL_UID_Msk (_U_(0x1) << USBHS_CTRL_UID_Pos) /**< (USBHS_CTRL) UID Pin Enable Mask */ +#define USBHS_CTRL_UID USBHS_CTRL_UID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_UID_Msk instead */ +#define USBHS_CTRL_UIMOD_Pos 25 /**< (USBHS_CTRL) USBHS Mode Position */ +#define USBHS_CTRL_UIMOD_Msk (_U_(0x1) << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) USBHS Mode Mask */ +#define USBHS_CTRL_UIMOD USBHS_CTRL_UIMOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_UIMOD_Msk instead */ +#define USBHS_CTRL_UIMOD_HOST_Val _U_(0x0) /**< (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (USBHS_CTRL) The module is in USB Device mode. */ +#define USBHS_CTRL_UIMOD_HOST (USBHS_CTRL_UIMOD_HOST_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Host mode. Position */ +#define USBHS_CTRL_UIMOD_DEVICE (USBHS_CTRL_UIMOD_DEVICE_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Device mode. Position */ +#define USBHS_CTRL_MASK _U_(0x300C110) /**< \deprecated (USBHS_CTRL) Register MASK (Use USBHS_CTRL_Msk instead) */ +#define USBHS_CTRL_Msk _U_(0x300C110) /**< (USBHS_CTRL) Register Mask */ + + +/* -------- USBHS_SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t RDERRI:1; /**< bit: 4 Remote Device Connection Error Interrupt (Host mode only) */ + uint32_t :7; /**< bit: 5..11 Reserved */ + uint32_t SPEED:2; /**< bit: 12..13 Speed Status (Device mode only) */ + uint32_t CLKUSABLE:1; /**< bit: 14 UTMI Clock Usable */ + uint32_t :17; /**< bit: 15..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_SR_OFFSET (0x804) /**< (USBHS_SR) General Status Register Offset */ + +#define USBHS_SR_RDERRI_Pos 4 /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Position */ +#define USBHS_SR_RDERRI_Msk (_U_(0x1) << USBHS_SR_RDERRI_Pos) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ +#define USBHS_SR_RDERRI USBHS_SR_RDERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SR_RDERRI_Msk instead */ +#define USBHS_SR_SPEED_Pos 12 /**< (USBHS_SR) Speed Status (Device mode only) Position */ +#define USBHS_SR_SPEED_Msk (_U_(0x3) << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Speed Status (Device mode only) Mask */ +#define USBHS_SR_SPEED(value) (USBHS_SR_SPEED_Msk & ((value) << USBHS_SR_SPEED_Pos)) +#define USBHS_SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_SPEED_FULL_SPEED (USBHS_SR_SPEED_FULL_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Full-Speed mode Position */ +#define USBHS_SR_SPEED_HIGH_SPEED (USBHS_SR_SPEED_HIGH_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) High-Speed mode Position */ +#define USBHS_SR_SPEED_LOW_SPEED (USBHS_SR_SPEED_LOW_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Low-Speed mode Position */ +#define USBHS_SR_CLKUSABLE_Pos 14 /**< (USBHS_SR) UTMI Clock Usable Position */ +#define USBHS_SR_CLKUSABLE_Msk (_U_(0x1) << USBHS_SR_CLKUSABLE_Pos) /**< (USBHS_SR) UTMI Clock Usable Mask */ +#define USBHS_SR_CLKUSABLE USBHS_SR_CLKUSABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SR_CLKUSABLE_Msk instead */ +#define USBHS_SR_MASK _U_(0x7010) /**< \deprecated (USBHS_SR) Register MASK (Use USBHS_SR_Msk instead) */ +#define USBHS_SR_Msk _U_(0x7010) /**< (USBHS_SR) Register Mask */ + + +/* -------- USBHS_SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t RDERRIC:1; /**< bit: 4 Remote Device Connection Error Interrupt Clear */ + uint32_t :27; /**< bit: 5..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_SCR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_SCR_OFFSET (0x808) /**< (USBHS_SCR) General Status Clear Register Offset */ + +#define USBHS_SCR_RDERRIC_Pos 4 /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Position */ +#define USBHS_SCR_RDERRIC_Msk (_U_(0x1) << USBHS_SCR_RDERRIC_Pos) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Mask */ +#define USBHS_SCR_RDERRIC USBHS_SCR_RDERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SCR_RDERRIC_Msk instead */ +#define USBHS_SCR_MASK _U_(0x10) /**< \deprecated (USBHS_SCR) Register MASK (Use USBHS_SCR_Msk instead) */ +#define USBHS_SCR_Msk _U_(0x10) /**< (USBHS_SCR) Register Mask */ + + +/* -------- USBHS_SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t :4; /**< bit: 0..3 Reserved */ + uint32_t RDERRIS:1; /**< bit: 4 Remote Device Connection Error Interrupt Set */ + uint32_t :4; /**< bit: 5..8 Reserved */ + uint32_t VBUSRQS:1; /**< bit: 9 VBUS Request Set */ + uint32_t :22; /**< bit: 10..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} USBHS_SFR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USBHS_SFR_OFFSET (0x80C) /**< (USBHS_SFR) General Status Set Register Offset */ + +#define USBHS_SFR_RDERRIS_Pos 4 /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Position */ +#define USBHS_SFR_RDERRIS_Msk (_U_(0x1) << USBHS_SFR_RDERRIS_Pos) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Mask */ +#define USBHS_SFR_RDERRIS USBHS_SFR_RDERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SFR_RDERRIS_Msk instead */ +#define USBHS_SFR_VBUSRQS_Pos 9 /**< (USBHS_SFR) VBUS Request Set Position */ +#define USBHS_SFR_VBUSRQS_Msk (_U_(0x1) << USBHS_SFR_VBUSRQS_Pos) /**< (USBHS_SFR) VBUS Request Set Mask */ +#define USBHS_SFR_VBUSRQS USBHS_SFR_VBUSRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SFR_VBUSRQS_Msk instead */ +#define USBHS_SFR_MASK _U_(0x210) /**< \deprecated (USBHS_SFR) Register MASK (Use USBHS_SFR_Msk instead) */ +#define USBHS_SFR_Msk _U_(0x210) /**< (USBHS_SFR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief USBHS_DEVDMA hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< (USBHS_DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< (USBHS_DEVDMA Offset: 0x04) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< (USBHS_DEVDMA Offset: 0x08) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< (USBHS_DEVDMA Offset: 0x0C) Device DMA Channel Status Register */ +} UsbhsDevdma; + +/** \brief USBHS_HSTDMA hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< (USBHS_HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< (USBHS_HSTDMA Offset: 0x04) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< (USBHS_HSTDMA Offset: 0x08) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< (USBHS_HSTDMA Offset: 0x0C) Host DMA Channel Status Register */ +} UsbhsHstdma; + +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +/** \brief USBHS hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< (USBHS Offset: 0x1C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< (USBHS Offset: 0x20) Device Frame Number Register */ + __I uint8_t Reserved1[220]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */ + __I uint8_t Reserved2[8]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */ + __I uint8_t Reserved3[8]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */ + __I uint8_t Reserved4[8]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */ + __I uint8_t Reserved5[8]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */ + __I uint8_t Reserved6[8]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */ + __I uint8_t Reserved7[8]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */ + __I uint8_t Reserved8[200]; + UsbhsDevdma UsbhsDevdma[USBHSDEVDMA_NUMBER]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved9[128]; + __IO uint32_t USBHS_HSTCTRL; /**< (USBHS Offset: 0x400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< (USBHS Offset: 0x41C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< (USBHS Offset: 0x420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */ + __I uint8_t Reserved10[208]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */ + __I uint8_t Reserved11[8]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */ + __I uint8_t Reserved12[8]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */ + __I uint8_t Reserved13[8]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */ + __I uint8_t Reserved14[8]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */ + __I uint8_t Reserved15[8]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */ + __I uint8_t Reserved16[8]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */ + __I uint8_t Reserved17[8]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */ + __I uint8_t Reserved18[8]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */ + __I uint8_t Reserved19[104]; + UsbhsHstdma UsbhsHstdma[USBHSHSTDMA_NUMBER]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved20[128]; + __IO uint32_t USBHS_CTRL; /**< (USBHS Offset: 0x800) General Control Register */ + __I uint32_t USBHS_SR; /**< (USBHS Offset: 0x804) General Status Register */ + __O uint32_t USBHS_SCR; /**< (USBHS Offset: 0x808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< (USBHS Offset: 0x80C) General Status Set Register */ +} Usbhs; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief USBHS_DEVDMA hardware registers */ +typedef struct { + __IO USBHS_DEVDMANXTDSC_Type USBHS_DEVDMANXTDSC; /**< Offset: 0x00 (R/W 32) Device DMA Channel Next Descriptor Address Register */ + __IO USBHS_DEVDMAADDRESS_Type USBHS_DEVDMAADDRESS; /**< Offset: 0x04 (R/W 32) Device DMA Channel Address Register */ + __IO USBHS_DEVDMACONTROL_Type USBHS_DEVDMACONTROL; /**< Offset: 0x08 (R/W 32) Device DMA Channel Control Register */ + __IO USBHS_DEVDMASTATUS_Type USBHS_DEVDMASTATUS; /**< Offset: 0x0C (R/W 32) Device DMA Channel Status Register */ +} UsbhsDevdma; + +/** \brief USBHS_HSTDMA hardware registers */ +typedef struct { + __IO USBHS_HSTDMANXTDSC_Type USBHS_HSTDMANXTDSC; /**< Offset: 0x00 (R/W 32) Host DMA Channel Next Descriptor Address Register */ + __IO USBHS_HSTDMAADDRESS_Type USBHS_HSTDMAADDRESS; /**< Offset: 0x04 (R/W 32) Host DMA Channel Address Register */ + __IO USBHS_HSTDMACONTROL_Type USBHS_HSTDMACONTROL; /**< Offset: 0x08 (R/W 32) Host DMA Channel Control Register */ + __IO USBHS_HSTDMASTATUS_Type USBHS_HSTDMASTATUS; /**< Offset: 0x0C (R/W 32) Host DMA Channel Status Register */ +} UsbhsHstdma; + +/** \brief USBHS hardware registers */ +typedef struct { + __IO USBHS_DEVCTRL_Type USBHS_DEVCTRL; /**< Offset: 0x00 (R/W 32) Device General Control Register */ + __I USBHS_DEVISR_Type USBHS_DEVISR; /**< Offset: 0x04 (R/ 32) Device Global Interrupt Status Register */ + __O USBHS_DEVICR_Type USBHS_DEVICR; /**< Offset: 0x08 ( /W 32) Device Global Interrupt Clear Register */ + __O USBHS_DEVIFR_Type USBHS_DEVIFR; /**< Offset: 0x0C ( /W 32) Device Global Interrupt Set Register */ + __I USBHS_DEVIMR_Type USBHS_DEVIMR; /**< Offset: 0x10 (R/ 32) Device Global Interrupt Mask Register */ + __O USBHS_DEVIDR_Type USBHS_DEVIDR; /**< Offset: 0x14 ( /W 32) Device Global Interrupt Disable Register */ + __O USBHS_DEVIER_Type USBHS_DEVIER; /**< Offset: 0x18 ( /W 32) Device Global Interrupt Enable Register */ + __IO USBHS_DEVEPT_Type USBHS_DEVEPT; /**< Offset: 0x1C (R/W 32) Device Endpoint Register */ + __I USBHS_DEVFNUM_Type USBHS_DEVFNUM; /**< Offset: 0x20 (R/ 32) Device Frame Number Register */ + __I uint8_t Reserved1[220]; + __IO USBHS_DEVEPTCFG_Type USBHS_DEVEPTCFG[10]; /**< Offset: 0x100 (R/W 32) Device Endpoint Configuration Register */ + __I uint8_t Reserved2[8]; + __I USBHS_DEVEPTISR_Type USBHS_DEVEPTISR[10]; /**< Offset: 0x130 (R/ 32) Device Endpoint Interrupt Status Register */ + __I uint8_t Reserved3[8]; + __O USBHS_DEVEPTICR_Type USBHS_DEVEPTICR[10]; /**< Offset: 0x160 ( /W 32) Device Endpoint Interrupt Clear Register */ + __I uint8_t Reserved4[8]; + __O USBHS_DEVEPTIFR_Type USBHS_DEVEPTIFR[10]; /**< Offset: 0x190 ( /W 32) Device Endpoint Interrupt Set Register */ + __I uint8_t Reserved5[8]; + __I USBHS_DEVEPTIMR_Type USBHS_DEVEPTIMR[10]; /**< Offset: 0x1C0 (R/ 32) Device Endpoint Interrupt Mask Register */ + __I uint8_t Reserved6[8]; + __O USBHS_DEVEPTIER_Type USBHS_DEVEPTIER[10]; /**< Offset: 0x1F0 ( /W 32) Device Endpoint Interrupt Enable Register */ + __I uint8_t Reserved7[8]; + __O USBHS_DEVEPTIDR_Type USBHS_DEVEPTIDR[10]; /**< Offset: 0x220 ( /W 32) Device Endpoint Interrupt Disable Register */ + __I uint8_t Reserved8[200]; + UsbhsDevdma UsbhsDevdma[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved9[128]; + __IO USBHS_HSTCTRL_Type USBHS_HSTCTRL; /**< Offset: 0x400 (R/W 32) Host General Control Register */ + __I USBHS_HSTISR_Type USBHS_HSTISR; /**< Offset: 0x404 (R/ 32) Host Global Interrupt Status Register */ + __O USBHS_HSTICR_Type USBHS_HSTICR; /**< Offset: 0x408 ( /W 32) Host Global Interrupt Clear Register */ + __O USBHS_HSTIFR_Type USBHS_HSTIFR; /**< Offset: 0x40C ( /W 32) Host Global Interrupt Set Register */ + __I USBHS_HSTIMR_Type USBHS_HSTIMR; /**< Offset: 0x410 (R/ 32) Host Global Interrupt Mask Register */ + __O USBHS_HSTIDR_Type USBHS_HSTIDR; /**< Offset: 0x414 ( /W 32) Host Global Interrupt Disable Register */ + __O USBHS_HSTIER_Type USBHS_HSTIER; /**< Offset: 0x418 ( /W 32) Host Global Interrupt Enable Register */ + __IO USBHS_HSTPIP_Type USBHS_HSTPIP; /**< Offset: 0x41C (R/W 32) Host Pipe Register */ + __IO USBHS_HSTFNUM_Type USBHS_HSTFNUM; /**< Offset: 0x420 (R/W 32) Host Frame Number Register */ + __IO USBHS_HSTADDR1_Type USBHS_HSTADDR1; /**< Offset: 0x424 (R/W 32) Host Address 1 Register */ + __IO USBHS_HSTADDR2_Type USBHS_HSTADDR2; /**< Offset: 0x428 (R/W 32) Host Address 2 Register */ + __IO USBHS_HSTADDR3_Type USBHS_HSTADDR3; /**< Offset: 0x42C (R/W 32) Host Address 3 Register */ + __I uint8_t Reserved10[208]; + __IO USBHS_HSTPIPCFG_Type USBHS_HSTPIPCFG[10]; /**< Offset: 0x500 (R/W 32) Host Pipe Configuration Register */ + __I uint8_t Reserved11[8]; + __I USBHS_HSTPIPISR_Type USBHS_HSTPIPISR[10]; /**< Offset: 0x530 (R/ 32) Host Pipe Status Register */ + __I uint8_t Reserved12[8]; + __O USBHS_HSTPIPICR_Type USBHS_HSTPIPICR[10]; /**< Offset: 0x560 ( /W 32) Host Pipe Clear Register */ + __I uint8_t Reserved13[8]; + __O USBHS_HSTPIPIFR_Type USBHS_HSTPIPIFR[10]; /**< Offset: 0x590 ( /W 32) Host Pipe Set Register */ + __I uint8_t Reserved14[8]; + __I USBHS_HSTPIPIMR_Type USBHS_HSTPIPIMR[10]; /**< Offset: 0x5C0 (R/ 32) Host Pipe Mask Register */ + __I uint8_t Reserved15[8]; + __O USBHS_HSTPIPIER_Type USBHS_HSTPIPIER[10]; /**< Offset: 0x5F0 ( /W 32) Host Pipe Enable Register */ + __I uint8_t Reserved16[8]; + __O USBHS_HSTPIPIDR_Type USBHS_HSTPIPIDR[10]; /**< Offset: 0x620 ( /W 32) Host Pipe Disable Register */ + __I uint8_t Reserved17[8]; + __IO USBHS_HSTPIPINRQ_Type USBHS_HSTPIPINRQ[10]; /**< Offset: 0x650 (R/W 32) Host Pipe IN Request Register */ + __I uint8_t Reserved18[8]; + __IO USBHS_HSTPIPERR_Type USBHS_HSTPIPERR[10]; /**< Offset: 0x680 (R/W 32) Host Pipe Error Register */ + __I uint8_t Reserved19[104]; + UsbhsHstdma UsbhsHstdma[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved20[128]; + __IO USBHS_CTRL_Type USBHS_CTRL; /**< Offset: 0x800 (R/W 32) General Control Register */ + __I USBHS_SR_Type USBHS_SR; /**< Offset: 0x804 (R/ 32) General Status Register */ + __O USBHS_SCR_Type USBHS_SCR; /**< Offset: 0x808 ( /W 32) General Status Clear Register */ + __O USBHS_SFR_Type USBHS_SFR; /**< Offset: 0x80C ( /W 32) General Status Set Register */ +} Usbhs; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of USB High-Speed Interface */ + +#if !(defined(DO_NOT_USE_DEPRECATED_MACROS)) +#include "deprecated/usbhs.h" +#endif /* DO_NOT_USE_DEPRECATED_MACROS */ +#endif /* _SAME70_USBHS_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/utmi.h b/bsp/microchip/same70/bsp/same70b/include/component/utmi.h new file mode 100644 index 0000000000..db36cc4ea0 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/utmi.h @@ -0,0 +1,143 @@ +/** + * \file + * + * \brief Component description for UTMI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UTMI_COMPONENT_H_ +#define _SAME70_UTMI_COMPONENT_H_ +#define _SAME70_UTMI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 USB Transmitter Interface Macrocell + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR UTMI */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define UTMI_11300 /**< (UTMI) Module ID */ +#define REV_UTMI A /**< (UTMI) Module revision */ + +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RES0:1; /**< bit: 0 USB PORTx Reset */ + uint32_t :3; /**< bit: 1..3 Reserved */ + uint32_t ARIE:1; /**< bit: 4 OHCI Asynchronous Resume Interrupt Enable */ + uint32_t APPSTART:1; /**< bit: 5 Reserved */ + uint32_t :17; /**< bit: 6..22 Reserved */ + uint32_t UDPPUDIS:1; /**< bit: 23 USB Device Pull-up Disable */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t RES:1; /**< bit: 0 USB PORTx Reset */ + uint32_t :31; /**< bit: 1..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} UTMI_OHCIICR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UTMI_OHCIICR_OFFSET (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */ + +#define UTMI_OHCIICR_RES0_Pos 0 /**< (UTMI_OHCIICR) USB PORTx Reset Position */ +#define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */ +#define UTMI_OHCIICR_RES0 UTMI_OHCIICR_RES0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_RES0_Msk instead */ +#define UTMI_OHCIICR_ARIE_Pos 4 /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */ +#define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */ +#define UTMI_OHCIICR_ARIE UTMI_OHCIICR_ARIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_ARIE_Msk instead */ +#define UTMI_OHCIICR_APPSTART_Pos 5 /**< (UTMI_OHCIICR) Reserved Position */ +#define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */ +#define UTMI_OHCIICR_APPSTART UTMI_OHCIICR_APPSTART_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_APPSTART_Msk instead */ +#define UTMI_OHCIICR_UDPPUDIS_Pos 23 /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */ +#define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */ +#define UTMI_OHCIICR_UDPPUDIS UTMI_OHCIICR_UDPPUDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UTMI_OHCIICR_UDPPUDIS_Msk instead */ +#define UTMI_OHCIICR_MASK _U_(0x800031) /**< \deprecated (UTMI_OHCIICR) Register MASK (Use UTMI_OHCIICR_Msk instead) */ +#define UTMI_OHCIICR_Msk _U_(0x800031) /**< (UTMI_OHCIICR) Register Mask */ + +#define UTMI_OHCIICR_RES_Pos 0 /**< (UTMI_OHCIICR Position) USB PORTx Reset */ +#define UTMI_OHCIICR_RES_Msk (_U_(0x1) << UTMI_OHCIICR_RES_Pos) /**< (UTMI_OHCIICR Mask) RES */ +#define UTMI_OHCIICR_RES(value) (UTMI_OHCIICR_RES_Msk & ((value) << UTMI_OHCIICR_RES_Pos)) + +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t FREQ:2; /**< bit: 0..1 UTMI Reference Clock Frequency */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} UTMI_CKTRIM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define UTMI_CKTRIM_OFFSET (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */ + +#define UTMI_CKTRIM_FREQ_Pos 0 /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */ +#define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */ +#define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)) +#define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */ +#define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */ +#define UTMI_CKTRIM_MASK _U_(0x03) /**< \deprecated (UTMI_CKTRIM) Register MASK (Use UTMI_CKTRIM_Msk instead) */ +#define UTMI_CKTRIM_Msk _U_(0x03) /**< (UTMI_CKTRIM) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief UTMI hardware registers */ +typedef struct { + __I uint8_t Reserved1[16]; + __IO uint32_t UTMI_OHCIICR; /**< (UTMI Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint8_t Reserved2[28]; + __IO uint32_t UTMI_CKTRIM; /**< (UTMI Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief UTMI hardware registers */ +typedef struct { + __I uint8_t Reserved1[16]; + __IO UTMI_OHCIICR_Type UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */ + __I uint8_t Reserved2[28]; + __IO UTMI_CKTRIM_Type UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */ +} Utmi; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of USB Transmitter Interface Macrocell */ + +#endif /* _SAME70_UTMI_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/wdt.h b/bsp/microchip/same70/bsp/same70b/include/component/wdt.h new file mode 100644 index 0000000000..c937592cc8 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/wdt.h @@ -0,0 +1,173 @@ +/** + * \file + * + * \brief Component description for WDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_WDT_COMPONENT_H_ +#define _SAME70_WDT_COMPONENT_H_ +#define _SAME70_WDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Watchdog Timer + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR WDT */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define WDT_6080 /**< (WDT) Module ID */ +#define REV_WDT N /**< (WDT) Module revision */ + +/* -------- WDT_CR : (WDT Offset: 0x00) (/W 32) Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */ + uint32_t :23; /**< bit: 1..23 Reserved */ + uint32_t KEY:8; /**< bit: 24..31 Password */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} WDT_CR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CR_OFFSET (0x00) /**< (WDT_CR) Control Register Offset */ + +#define WDT_CR_WDRSTT_Pos 0 /**< (WDT_CR) Watchdog Restart Position */ +#define WDT_CR_WDRSTT_Msk (_U_(0x1) << WDT_CR_WDRSTT_Pos) /**< (WDT_CR) Watchdog Restart Mask */ +#define WDT_CR_WDRSTT WDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_CR_WDRSTT_Msk instead */ +#define WDT_CR_KEY_Pos 24 /**< (WDT_CR) Password Position */ +#define WDT_CR_KEY_Msk (_U_(0xFF) << WDT_CR_KEY_Pos) /**< (WDT_CR) Password Mask */ +#define WDT_CR_KEY(value) (WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)) +#define WDT_CR_KEY_PASSWD_Val _U_(0xA5) /**< (WDT_CR) Writing any other value in this field aborts the write operation. */ +#define WDT_CR_KEY_PASSWD (WDT_CR_KEY_PASSWD_Val << WDT_CR_KEY_Pos) /**< (WDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define WDT_CR_MASK _U_(0xFF000001) /**< \deprecated (WDT_CR) Register MASK (Use WDT_CR_Msk instead) */ +#define WDT_CR_Msk _U_(0xFF000001) /**< (WDT_CR) Register Mask */ + + +/* -------- WDT_MR : (WDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */ + uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */ + uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */ + uint32_t :1; /**< bit: 14 Reserved */ + uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */ + uint32_t WDD:12; /**< bit: 16..27 Watchdog Delta Value */ + uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */ + uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */ + uint32_t :2; /**< bit: 30..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} WDT_MR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_MR_OFFSET (0x04) /**< (WDT_MR) Mode Register Offset */ + +#define WDT_MR_WDV_Pos 0 /**< (WDT_MR) Watchdog Counter Value Position */ +#define WDT_MR_WDV_Msk (_U_(0xFFF) << WDT_MR_WDV_Pos) /**< (WDT_MR) Watchdog Counter Value Mask */ +#define WDT_MR_WDV(value) (WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)) +#define WDT_MR_WDFIEN_Pos 12 /**< (WDT_MR) Watchdog Fault Interrupt Enable Position */ +#define WDT_MR_WDFIEN_Msk (_U_(0x1) << WDT_MR_WDFIEN_Pos) /**< (WDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define WDT_MR_WDFIEN WDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDFIEN_Msk instead */ +#define WDT_MR_WDRSTEN_Pos 13 /**< (WDT_MR) Watchdog Reset Enable Position */ +#define WDT_MR_WDRSTEN_Msk (_U_(0x1) << WDT_MR_WDRSTEN_Pos) /**< (WDT_MR) Watchdog Reset Enable Mask */ +#define WDT_MR_WDRSTEN WDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDRSTEN_Msk instead */ +#define WDT_MR_WDDIS_Pos 15 /**< (WDT_MR) Watchdog Disable Position */ +#define WDT_MR_WDDIS_Msk (_U_(0x1) << WDT_MR_WDDIS_Pos) /**< (WDT_MR) Watchdog Disable Mask */ +#define WDT_MR_WDDIS WDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDIS_Msk instead */ +#define WDT_MR_WDD_Pos 16 /**< (WDT_MR) Watchdog Delta Value Position */ +#define WDT_MR_WDD_Msk (_U_(0xFFF) << WDT_MR_WDD_Pos) /**< (WDT_MR) Watchdog Delta Value Mask */ +#define WDT_MR_WDD(value) (WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)) +#define WDT_MR_WDDBGHLT_Pos 28 /**< (WDT_MR) Watchdog Debug Halt Position */ +#define WDT_MR_WDDBGHLT_Msk (_U_(0x1) << WDT_MR_WDDBGHLT_Pos) /**< (WDT_MR) Watchdog Debug Halt Mask */ +#define WDT_MR_WDDBGHLT WDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDBGHLT_Msk instead */ +#define WDT_MR_WDIDLEHLT_Pos 29 /**< (WDT_MR) Watchdog Idle Halt Position */ +#define WDT_MR_WDIDLEHLT_Msk (_U_(0x1) << WDT_MR_WDIDLEHLT_Pos) /**< (WDT_MR) Watchdog Idle Halt Mask */ +#define WDT_MR_WDIDLEHLT WDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDIDLEHLT_Msk instead */ +#define WDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (WDT_MR) Register MASK (Use WDT_MR_Msk instead) */ +#define WDT_MR_Msk _U_(0x3FFFBFFF) /**< (WDT_MR) Register Mask */ + + +/* -------- WDT_SR : (WDT Offset: 0x08) (R/ 32) Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow (cleared on read) */ + uint32_t WDERR:1; /**< bit: 1 Watchdog Error (cleared on read) */ + uint32_t :30; /**< bit: 2..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} WDT_SR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_SR_OFFSET (0x08) /**< (WDT_SR) Status Register Offset */ + +#define WDT_SR_WDUNF_Pos 0 /**< (WDT_SR) Watchdog Underflow (cleared on read) Position */ +#define WDT_SR_WDUNF_Msk (_U_(0x1) << WDT_SR_WDUNF_Pos) /**< (WDT_SR) Watchdog Underflow (cleared on read) Mask */ +#define WDT_SR_WDUNF WDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDUNF_Msk instead */ +#define WDT_SR_WDERR_Pos 1 /**< (WDT_SR) Watchdog Error (cleared on read) Position */ +#define WDT_SR_WDERR_Msk (_U_(0x1) << WDT_SR_WDERR_Pos) /**< (WDT_SR) Watchdog Error (cleared on read) Mask */ +#define WDT_SR_WDERR WDT_SR_WDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDERR_Msk instead */ +#define WDT_SR_MASK _U_(0x03) /**< \deprecated (WDT_SR) Register MASK (Use WDT_SR_Msk instead) */ +#define WDT_SR_Msk _U_(0x03) /**< (WDT_SR) Register Mask */ + + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief WDT hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< (WDT Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< (WDT Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< (WDT Offset: 0x08) Status Register */ +} Wdt; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief WDT hardware registers */ +typedef struct { + __O WDT_CR_Type WDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO WDT_MR_Type WDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I WDT_SR_Type WDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} Wdt; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Watchdog Timer */ + +#endif /* _SAME70_WDT_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/component/xdmac.h b/bsp/microchip/same70/bsp/same70b/include/component/xdmac.h new file mode 100644 index 0000000000..b7f928acac --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/component/xdmac.h @@ -0,0 +1,2621 @@ +/** + * \file + * + * \brief Component description for XDMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_XDMAC_COMPONENT_H_ +#define _SAME70_XDMAC_COMPONENT_H_ +#define _SAME70_XDMAC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ + +/** \addtogroup SAME_SAME70 Extensible DMA Controller + * @{ + */ +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR XDMAC */ +/* ========================================================================== */ +#ifndef COMPONENT_TYPEDEF_STYLE + #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ +#endif + +#define XDMAC_11161 /**< (XDMAC) Module ID */ +#define REV_XDMAC K /**< (XDMAC) Module revision */ + +/* -------- XDMAC_CIE : (XDMAC Offset: 0x00) (/W 32) Channel Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BIE:1; /**< bit: 0 End of Block Interrupt Enable Bit */ + uint32_t LIE:1; /**< bit: 1 End of Linked List Interrupt Enable Bit */ + uint32_t DIE:1; /**< bit: 2 End of Disable Interrupt Enable Bit */ + uint32_t FIE:1; /**< bit: 3 End of Flush Interrupt Enable Bit */ + uint32_t RBIE:1; /**< bit: 4 Read Bus Error Interrupt Enable Bit */ + uint32_t WBIE:1; /**< bit: 5 Write Bus Error Interrupt Enable Bit */ + uint32_t ROIE:1; /**< bit: 6 Request Overflow Error Interrupt Enable Bit */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CIE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CIE_OFFSET (0x00) /**< (XDMAC_CIE) Channel Interrupt Enable Register Offset */ + +#define XDMAC_CIE_BIE_Pos 0 /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Position */ +#define XDMAC_CIE_BIE_Msk (_U_(0x1) << XDMAC_CIE_BIE_Pos) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Mask */ +#define XDMAC_CIE_BIE XDMAC_CIE_BIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_BIE_Msk instead */ +#define XDMAC_CIE_LIE_Pos 1 /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Position */ +#define XDMAC_CIE_LIE_Msk (_U_(0x1) << XDMAC_CIE_LIE_Pos) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Mask */ +#define XDMAC_CIE_LIE XDMAC_CIE_LIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_LIE_Msk instead */ +#define XDMAC_CIE_DIE_Pos 2 /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Position */ +#define XDMAC_CIE_DIE_Msk (_U_(0x1) << XDMAC_CIE_DIE_Pos) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Mask */ +#define XDMAC_CIE_DIE XDMAC_CIE_DIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_DIE_Msk instead */ +#define XDMAC_CIE_FIE_Pos 3 /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Position */ +#define XDMAC_CIE_FIE_Msk (_U_(0x1) << XDMAC_CIE_FIE_Pos) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Mask */ +#define XDMAC_CIE_FIE XDMAC_CIE_FIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_FIE_Msk instead */ +#define XDMAC_CIE_RBIE_Pos 4 /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_RBIE_Msk (_U_(0x1) << XDMAC_CIE_RBIE_Pos) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_RBIE XDMAC_CIE_RBIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_RBIE_Msk instead */ +#define XDMAC_CIE_WBIE_Pos 5 /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_WBIE_Msk (_U_(0x1) << XDMAC_CIE_WBIE_Pos) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_WBIE XDMAC_CIE_WBIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_WBIE_Msk instead */ +#define XDMAC_CIE_ROIE_Pos 6 /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_ROIE_Msk (_U_(0x1) << XDMAC_CIE_ROIE_Pos) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_ROIE XDMAC_CIE_ROIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIE_ROIE_Msk instead */ +#define XDMAC_CIE_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIE) Register MASK (Use XDMAC_CIE_Msk instead) */ +#define XDMAC_CIE_Msk _U_(0x7F) /**< (XDMAC_CIE) Register Mask */ + + +/* -------- XDMAC_CID : (XDMAC Offset: 0x04) (/W 32) Channel Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BID:1; /**< bit: 0 End of Block Interrupt Disable Bit */ + uint32_t LID:1; /**< bit: 1 End of Linked List Interrupt Disable Bit */ + uint32_t DID:1; /**< bit: 2 End of Disable Interrupt Disable Bit */ + uint32_t FID:1; /**< bit: 3 End of Flush Interrupt Disable Bit */ + uint32_t RBEID:1; /**< bit: 4 Read Bus Error Interrupt Disable Bit */ + uint32_t WBEID:1; /**< bit: 5 Write Bus Error Interrupt Disable Bit */ + uint32_t ROID:1; /**< bit: 6 Request Overflow Error Interrupt Disable Bit */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CID_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CID_OFFSET (0x04) /**< (XDMAC_CID) Channel Interrupt Disable Register Offset */ + +#define XDMAC_CID_BID_Pos 0 /**< (XDMAC_CID) End of Block Interrupt Disable Bit Position */ +#define XDMAC_CID_BID_Msk (_U_(0x1) << XDMAC_CID_BID_Pos) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Mask */ +#define XDMAC_CID_BID XDMAC_CID_BID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_BID_Msk instead */ +#define XDMAC_CID_LID_Pos 1 /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Position */ +#define XDMAC_CID_LID_Msk (_U_(0x1) << XDMAC_CID_LID_Pos) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Mask */ +#define XDMAC_CID_LID XDMAC_CID_LID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_LID_Msk instead */ +#define XDMAC_CID_DID_Pos 2 /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Position */ +#define XDMAC_CID_DID_Msk (_U_(0x1) << XDMAC_CID_DID_Pos) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Mask */ +#define XDMAC_CID_DID XDMAC_CID_DID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_DID_Msk instead */ +#define XDMAC_CID_FID_Pos 3 /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Position */ +#define XDMAC_CID_FID_Msk (_U_(0x1) << XDMAC_CID_FID_Pos) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Mask */ +#define XDMAC_CID_FID XDMAC_CID_FID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_FID_Msk instead */ +#define XDMAC_CID_RBEID_Pos 4 /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_RBEID_Msk (_U_(0x1) << XDMAC_CID_RBEID_Pos) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_RBEID XDMAC_CID_RBEID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_RBEID_Msk instead */ +#define XDMAC_CID_WBEID_Pos 5 /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_WBEID_Msk (_U_(0x1) << XDMAC_CID_WBEID_Pos) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_WBEID XDMAC_CID_WBEID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_WBEID_Msk instead */ +#define XDMAC_CID_ROID_Pos 6 /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Position */ +#define XDMAC_CID_ROID_Msk (_U_(0x1) << XDMAC_CID_ROID_Pos) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_ROID XDMAC_CID_ROID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CID_ROID_Msk instead */ +#define XDMAC_CID_MASK _U_(0x7F) /**< \deprecated (XDMAC_CID) Register MASK (Use XDMAC_CID_Msk instead) */ +#define XDMAC_CID_Msk _U_(0x7F) /**< (XDMAC_CID) Register Mask */ + + +/* -------- XDMAC_CIM : (XDMAC Offset: 0x08) (R/ 32) Channel Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BIM:1; /**< bit: 0 End of Block Interrupt Mask Bit */ + uint32_t LIM:1; /**< bit: 1 End of Linked List Interrupt Mask Bit */ + uint32_t DIM:1; /**< bit: 2 End of Disable Interrupt Mask Bit */ + uint32_t FIM:1; /**< bit: 3 End of Flush Interrupt Mask Bit */ + uint32_t RBEIM:1; /**< bit: 4 Read Bus Error Interrupt Mask Bit */ + uint32_t WBEIM:1; /**< bit: 5 Write Bus Error Interrupt Mask Bit */ + uint32_t ROIM:1; /**< bit: 6 Request Overflow Error Interrupt Mask Bit */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CIM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CIM_OFFSET (0x08) /**< (XDMAC_CIM) Channel Interrupt Mask Register Offset */ + +#define XDMAC_CIM_BIM_Pos 0 /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Position */ +#define XDMAC_CIM_BIM_Msk (_U_(0x1) << XDMAC_CIM_BIM_Pos) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Mask */ +#define XDMAC_CIM_BIM XDMAC_CIM_BIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_BIM_Msk instead */ +#define XDMAC_CIM_LIM_Pos 1 /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Position */ +#define XDMAC_CIM_LIM_Msk (_U_(0x1) << XDMAC_CIM_LIM_Pos) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Mask */ +#define XDMAC_CIM_LIM XDMAC_CIM_LIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_LIM_Msk instead */ +#define XDMAC_CIM_DIM_Pos 2 /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Position */ +#define XDMAC_CIM_DIM_Msk (_U_(0x1) << XDMAC_CIM_DIM_Pos) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Mask */ +#define XDMAC_CIM_DIM XDMAC_CIM_DIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_DIM_Msk instead */ +#define XDMAC_CIM_FIM_Pos 3 /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Position */ +#define XDMAC_CIM_FIM_Msk (_U_(0x1) << XDMAC_CIM_FIM_Pos) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Mask */ +#define XDMAC_CIM_FIM XDMAC_CIM_FIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_FIM_Msk instead */ +#define XDMAC_CIM_RBEIM_Pos 4 /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_RBEIM_Msk (_U_(0x1) << XDMAC_CIM_RBEIM_Pos) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_RBEIM XDMAC_CIM_RBEIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_RBEIM_Msk instead */ +#define XDMAC_CIM_WBEIM_Pos 5 /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_WBEIM_Msk (_U_(0x1) << XDMAC_CIM_WBEIM_Pos) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_WBEIM XDMAC_CIM_WBEIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_WBEIM_Msk instead */ +#define XDMAC_CIM_ROIM_Pos 6 /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_ROIM_Msk (_U_(0x1) << XDMAC_CIM_ROIM_Pos) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_ROIM XDMAC_CIM_ROIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIM_ROIM_Msk instead */ +#define XDMAC_CIM_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIM) Register MASK (Use XDMAC_CIM_Msk instead) */ +#define XDMAC_CIM_Msk _U_(0x7F) /**< (XDMAC_CIM) Register Mask */ + + +/* -------- XDMAC_CIS : (XDMAC Offset: 0x0c) (R/ 32) Channel Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BIS:1; /**< bit: 0 End of Block Interrupt Status Bit */ + uint32_t LIS:1; /**< bit: 1 End of Linked List Interrupt Status Bit */ + uint32_t DIS:1; /**< bit: 2 End of Disable Interrupt Status Bit */ + uint32_t FIS:1; /**< bit: 3 End of Flush Interrupt Status Bit */ + uint32_t RBEIS:1; /**< bit: 4 Read Bus Error Interrupt Status Bit */ + uint32_t WBEIS:1; /**< bit: 5 Write Bus Error Interrupt Status Bit */ + uint32_t ROIS:1; /**< bit: 6 Request Overflow Error Interrupt Status Bit */ + uint32_t :25; /**< bit: 7..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CIS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CIS_OFFSET (0x0C) /**< (XDMAC_CIS) Channel Interrupt Status Register Offset */ + +#define XDMAC_CIS_BIS_Pos 0 /**< (XDMAC_CIS) End of Block Interrupt Status Bit Position */ +#define XDMAC_CIS_BIS_Msk (_U_(0x1) << XDMAC_CIS_BIS_Pos) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Mask */ +#define XDMAC_CIS_BIS XDMAC_CIS_BIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_BIS_Msk instead */ +#define XDMAC_CIS_LIS_Pos 1 /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Position */ +#define XDMAC_CIS_LIS_Msk (_U_(0x1) << XDMAC_CIS_LIS_Pos) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Mask */ +#define XDMAC_CIS_LIS XDMAC_CIS_LIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_LIS_Msk instead */ +#define XDMAC_CIS_DIS_Pos 2 /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Position */ +#define XDMAC_CIS_DIS_Msk (_U_(0x1) << XDMAC_CIS_DIS_Pos) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Mask */ +#define XDMAC_CIS_DIS XDMAC_CIS_DIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_DIS_Msk instead */ +#define XDMAC_CIS_FIS_Pos 3 /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Position */ +#define XDMAC_CIS_FIS_Msk (_U_(0x1) << XDMAC_CIS_FIS_Pos) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Mask */ +#define XDMAC_CIS_FIS XDMAC_CIS_FIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_FIS_Msk instead */ +#define XDMAC_CIS_RBEIS_Pos 4 /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_RBEIS_Msk (_U_(0x1) << XDMAC_CIS_RBEIS_Pos) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_RBEIS XDMAC_CIS_RBEIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_RBEIS_Msk instead */ +#define XDMAC_CIS_WBEIS_Pos 5 /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_WBEIS_Msk (_U_(0x1) << XDMAC_CIS_WBEIS_Pos) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_WBEIS XDMAC_CIS_WBEIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_WBEIS_Msk instead */ +#define XDMAC_CIS_ROIS_Pos 6 /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Position */ +#define XDMAC_CIS_ROIS_Msk (_U_(0x1) << XDMAC_CIS_ROIS_Pos) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_ROIS XDMAC_CIS_ROIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CIS_ROIS_Msk instead */ +#define XDMAC_CIS_MASK _U_(0x7F) /**< \deprecated (XDMAC_CIS) Register MASK (Use XDMAC_CIS_Msk instead) */ +#define XDMAC_CIS_Msk _U_(0x7F) /**< (XDMAC_CIS) Register Mask */ + + +/* -------- XDMAC_CSA : (XDMAC Offset: 0x10) (R/W 32) Channel Source Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SA:32; /**< bit: 0..31 Channel x Source Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CSA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CSA_OFFSET (0x10) /**< (XDMAC_CSA) Channel Source Address Register Offset */ + +#define XDMAC_CSA_SA_Pos 0 /**< (XDMAC_CSA) Channel x Source Address Position */ +#define XDMAC_CSA_SA_Msk (_U_(0xFFFFFFFF) << XDMAC_CSA_SA_Pos) /**< (XDMAC_CSA) Channel x Source Address Mask */ +#define XDMAC_CSA_SA(value) (XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)) +#define XDMAC_CSA_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CSA) Register MASK (Use XDMAC_CSA_Msk instead) */ +#define XDMAC_CSA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CSA) Register Mask */ + + +/* -------- XDMAC_CDA : (XDMAC Offset: 0x14) (R/W 32) Channel Destination Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DA:32; /**< bit: 0..31 Channel x Destination Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CDA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CDA_OFFSET (0x14) /**< (XDMAC_CDA) Channel Destination Address Register Offset */ + +#define XDMAC_CDA_DA_Pos 0 /**< (XDMAC_CDA) Channel x Destination Address Position */ +#define XDMAC_CDA_DA_Msk (_U_(0xFFFFFFFF) << XDMAC_CDA_DA_Pos) /**< (XDMAC_CDA) Channel x Destination Address Mask */ +#define XDMAC_CDA_DA(value) (XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)) +#define XDMAC_CDA_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CDA) Register MASK (Use XDMAC_CDA_Msk instead) */ +#define XDMAC_CDA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDA) Register Mask */ + + +/* -------- XDMAC_CNDA : (XDMAC Offset: 0x18) (R/W 32) Channel Next Descriptor Address Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NDAIF:1; /**< bit: 0 Channel x Next Descriptor Interface */ + uint32_t :1; /**< bit: 1 Reserved */ + uint32_t NDA:30; /**< bit: 2..31 Channel x Next Descriptor Address */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CNDA_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CNDA_OFFSET (0x18) /**< (XDMAC_CNDA) Channel Next Descriptor Address Register Offset */ + +#define XDMAC_CNDA_NDAIF_Pos 0 /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Position */ +#define XDMAC_CNDA_NDAIF_Msk (_U_(0x1) << XDMAC_CNDA_NDAIF_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Mask */ +#define XDMAC_CNDA_NDAIF XDMAC_CNDA_NDAIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDA_NDAIF_Msk instead */ +#define XDMAC_CNDA_NDA_Pos 2 /**< (XDMAC_CNDA) Channel x Next Descriptor Address Position */ +#define XDMAC_CNDA_NDA_Msk (_U_(0x3FFFFFFF) << XDMAC_CNDA_NDA_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Mask */ +#define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)) +#define XDMAC_CNDA_MASK _U_(0xFFFFFFFD) /**< \deprecated (XDMAC_CNDA) Register MASK (Use XDMAC_CNDA_Msk instead) */ +#define XDMAC_CNDA_Msk _U_(0xFFFFFFFD) /**< (XDMAC_CNDA) Register Mask */ + + +/* -------- XDMAC_CNDC : (XDMAC Offset: 0x1c) (R/W 32) Channel Next Descriptor Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NDE:1; /**< bit: 0 Channel x Next Descriptor Enable */ + uint32_t NDSUP:1; /**< bit: 1 Channel x Next Descriptor Source Update */ + uint32_t NDDUP:1; /**< bit: 2 Channel x Next Descriptor Destination Update */ + uint32_t NDVIEW:2; /**< bit: 3..4 Channel x Next Descriptor View */ + uint32_t :27; /**< bit: 5..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CNDC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CNDC_OFFSET (0x1C) /**< (XDMAC_CNDC) Channel Next Descriptor Control Register Offset */ + +#define XDMAC_CNDC_NDE_Pos 0 /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Position */ +#define XDMAC_CNDC_NDE_Msk (_U_(0x1) << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Mask */ +#define XDMAC_CNDC_NDE XDMAC_CNDC_NDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDE_Msk instead */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val _U_(0x0) /**< (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val _U_(0x1) /**< (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is disabled. Position */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is enabled. Position */ +#define XDMAC_CNDC_NDSUP_Pos 1 /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Position */ +#define XDMAC_CNDC_NDSUP_Msk (_U_(0x1) << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Mask */ +#define XDMAC_CNDC_NDSUP XDMAC_CNDC_NDSUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDSUP_Msk instead */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDDUP_Pos 2 /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Position */ +#define XDMAC_CNDC_NDDUP_Msk (_U_(0x1) << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Mask */ +#define XDMAC_CNDC_NDDUP XDMAC_CNDC_NDDUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CNDC_NDDUP_Msk instead */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDVIEW_Pos 3 /**< (XDMAC_CNDC) Channel x Next Descriptor View Position */ +#define XDMAC_CNDC_NDVIEW_Msk (_U_(0x3) << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor View Mask */ +#define XDMAC_CNDC_NDVIEW(value) (XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)) +#define XDMAC_CNDC_NDVIEW_NDV0_Val _U_(0x0) /**< (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1_Val _U_(0x1) /**< (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2_Val _U_(0x2) /**< (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3_Val _U_(0x3) /**< (XDMAC_CNDC) Next Descriptor View 3 */ +#define XDMAC_CNDC_NDVIEW_NDV0 (XDMAC_CNDC_NDVIEW_NDV0_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 0 Position */ +#define XDMAC_CNDC_NDVIEW_NDV1 (XDMAC_CNDC_NDVIEW_NDV1_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 1 Position */ +#define XDMAC_CNDC_NDVIEW_NDV2 (XDMAC_CNDC_NDVIEW_NDV2_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 2 Position */ +#define XDMAC_CNDC_NDVIEW_NDV3 (XDMAC_CNDC_NDVIEW_NDV3_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 3 Position */ +#define XDMAC_CNDC_MASK _U_(0x1F) /**< \deprecated (XDMAC_CNDC) Register MASK (Use XDMAC_CNDC_Msk instead) */ +#define XDMAC_CNDC_Msk _U_(0x1F) /**< (XDMAC_CNDC) Register Mask */ + + +/* -------- XDMAC_CUBC : (XDMAC Offset: 0x20) (R/W 32) Channel Microblock Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t UBLEN:24; /**< bit: 0..23 Channel x Microblock Length */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CUBC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CUBC_OFFSET (0x20) /**< (XDMAC_CUBC) Channel Microblock Control Register Offset */ + +#define XDMAC_CUBC_UBLEN_Pos 0 /**< (XDMAC_CUBC) Channel x Microblock Length Position */ +#define XDMAC_CUBC_UBLEN_Msk (_U_(0xFFFFFF) << XDMAC_CUBC_UBLEN_Pos) /**< (XDMAC_CUBC) Channel x Microblock Length Mask */ +#define XDMAC_CUBC_UBLEN(value) (XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)) +#define XDMAC_CUBC_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CUBC) Register MASK (Use XDMAC_CUBC_Msk instead) */ +#define XDMAC_CUBC_Msk _U_(0xFFFFFF) /**< (XDMAC_CUBC) Register Mask */ + + +/* -------- XDMAC_CBC : (XDMAC Offset: 0x24) (R/W 32) Channel Block Control Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t BLEN:12; /**< bit: 0..11 Channel x Block Length */ + uint32_t :20; /**< bit: 12..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CBC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CBC_OFFSET (0x24) /**< (XDMAC_CBC) Channel Block Control Register Offset */ + +#define XDMAC_CBC_BLEN_Pos 0 /**< (XDMAC_CBC) Channel x Block Length Position */ +#define XDMAC_CBC_BLEN_Msk (_U_(0xFFF) << XDMAC_CBC_BLEN_Pos) /**< (XDMAC_CBC) Channel x Block Length Mask */ +#define XDMAC_CBC_BLEN(value) (XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)) +#define XDMAC_CBC_MASK _U_(0xFFF) /**< \deprecated (XDMAC_CBC) Register MASK (Use XDMAC_CBC_Msk instead) */ +#define XDMAC_CBC_Msk _U_(0xFFF) /**< (XDMAC_CBC) Register Mask */ + + +/* -------- XDMAC_CC : (XDMAC Offset: 0x28) (R/W 32) Channel Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t TYPE:1; /**< bit: 0 Channel x Transfer Type */ + uint32_t MBSIZE:2; /**< bit: 1..2 Channel x Memory Burst Size */ + uint32_t :1; /**< bit: 3 Reserved */ + uint32_t DSYNC:1; /**< bit: 4 Channel x Synchronization */ + uint32_t :1; /**< bit: 5 Reserved */ + uint32_t SWREQ:1; /**< bit: 6 Channel x Software Request Trigger */ + uint32_t MEMSET:1; /**< bit: 7 Channel x Fill Block of memory */ + uint32_t CSIZE:3; /**< bit: 8..10 Channel x Chunk Size */ + uint32_t DWIDTH:2; /**< bit: 11..12 Channel x Data Width */ + uint32_t SIF:1; /**< bit: 13 Channel x Source Interface Identifier */ + uint32_t DIF:1; /**< bit: 14 Channel x Destination Interface Identifier */ + uint32_t :1; /**< bit: 15 Reserved */ + uint32_t SAM:2; /**< bit: 16..17 Channel x Source Addressing Mode */ + uint32_t DAM:2; /**< bit: 18..19 Channel x Destination Addressing Mode */ + uint32_t :1; /**< bit: 20 Reserved */ + uint32_t INITD:1; /**< bit: 21 Channel Initialization Terminated (this bit is read-only) */ + uint32_t RDIP:1; /**< bit: 22 Read in Progress (this bit is read-only) */ + uint32_t WRIP:1; /**< bit: 23 Write in Progress (this bit is read-only) */ + uint32_t PERID:7; /**< bit: 24..30 Channel x Peripheral Hardware Request Line Identifier */ + uint32_t :1; /**< bit: 31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CC_OFFSET (0x28) /**< (XDMAC_CC) Channel Configuration Register Offset */ + +#define XDMAC_CC_TYPE_Pos 0 /**< (XDMAC_CC) Channel x Transfer Type Position */ +#define XDMAC_CC_TYPE_Msk (_U_(0x1) << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Channel x Transfer Type Mask */ +#define XDMAC_CC_TYPE XDMAC_CC_TYPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_TYPE_Msk instead */ +#define XDMAC_CC_TYPE_MEM_TRAN_Val _U_(0x0) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN_Val _U_(0x1) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). */ +#define XDMAC_CC_TYPE_MEM_TRAN (XDMAC_CC_TYPE_MEM_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). Position */ +#define XDMAC_CC_TYPE_PER_TRAN (XDMAC_CC_TYPE_PER_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). Position */ +#define XDMAC_CC_MBSIZE_Pos 1 /**< (XDMAC_CC) Channel x Memory Burst Size Position */ +#define XDMAC_CC_MBSIZE_Msk (_U_(0x3) << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) Channel x Memory Burst Size Mask */ +#define XDMAC_CC_MBSIZE(value) (XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)) +#define XDMAC_CC_MBSIZE_SINGLE_Val _U_(0x0) /**< (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR_Val _U_(0x1) /**< (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT_Val _U_(0x2) /**< (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN_Val _U_(0x3) /**< (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_MBSIZE_SINGLE (XDMAC_CC_MBSIZE_SINGLE_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to one. Position */ +#define XDMAC_CC_MBSIZE_FOUR (XDMAC_CC_MBSIZE_FOUR_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to four. Position */ +#define XDMAC_CC_MBSIZE_EIGHT (XDMAC_CC_MBSIZE_EIGHT_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to eight. Position */ +#define XDMAC_CC_MBSIZE_SIXTEEN (XDMAC_CC_MBSIZE_SIXTEEN_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to sixteen. Position */ +#define XDMAC_CC_DSYNC_Pos 4 /**< (XDMAC_CC) Channel x Synchronization Position */ +#define XDMAC_CC_DSYNC_Msk (_U_(0x1) << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Channel x Synchronization Mask */ +#define XDMAC_CC_DSYNC XDMAC_CC_DSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_DSYNC_Msk instead */ +#define XDMAC_CC_DSYNC_PER2MEM_Val _U_(0x0) /**< (XDMAC_CC) Peripheral-to-memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER_Val _U_(0x1) /**< (XDMAC_CC) Memory-to-peripheral transfer. */ +#define XDMAC_CC_DSYNC_PER2MEM (XDMAC_CC_DSYNC_PER2MEM_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Peripheral-to-memory transfer. Position */ +#define XDMAC_CC_DSYNC_MEM2PER (XDMAC_CC_DSYNC_MEM2PER_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Memory-to-peripheral transfer. Position */ +#define XDMAC_CC_SWREQ_Pos 6 /**< (XDMAC_CC) Channel x Software Request Trigger Position */ +#define XDMAC_CC_SWREQ_Msk (_U_(0x1) << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Channel x Software Request Trigger Mask */ +#define XDMAC_CC_SWREQ XDMAC_CC_SWREQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_SWREQ_Msk instead */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED_Val _U_(0x0) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED_Val _U_(0x1) /**< (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (XDMAC_CC_SWREQ_HWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. Position */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (XDMAC_CC_SWREQ_SWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Software request is connected to the peripheral request line. Position */ +#define XDMAC_CC_MEMSET_Pos 7 /**< (XDMAC_CC) Channel x Fill Block of memory Position */ +#define XDMAC_CC_MEMSET_Msk (_U_(0x1) << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Channel x Fill Block of memory Mask */ +#define XDMAC_CC_MEMSET XDMAC_CC_MEMSET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_MEMSET_Msk instead */ +#define XDMAC_CC_MEMSET_NORMAL_MODE_Val _U_(0x0) /**< (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE_Val _U_(0x1) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (XDMAC_CC_MEMSET_NORMAL_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Memset is not activated. Position */ +#define XDMAC_CC_MEMSET_HW_MODE (XDMAC_CC_MEMSET_HW_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. Position */ +#define XDMAC_CC_CSIZE_Pos 8 /**< (XDMAC_CC) Channel x Chunk Size Position */ +#define XDMAC_CC_CSIZE_Msk (_U_(0x7) << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) Channel x Chunk Size Mask */ +#define XDMAC_CC_CSIZE(value) (XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)) +#define XDMAC_CC_CSIZE_CHK_1_Val _U_(0x0) /**< (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2_Val _U_(0x1) /**< (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4_Val _U_(0x2) /**< (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8_Val _U_(0x3) /**< (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16_Val _U_(0x4) /**< (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_CSIZE_CHK_1 (XDMAC_CC_CSIZE_CHK_1_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 1 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_2 (XDMAC_CC_CSIZE_CHK_2_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 2 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_4 (XDMAC_CC_CSIZE_CHK_4_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 4 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_8 (XDMAC_CC_CSIZE_CHK_8_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 8 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_16 (XDMAC_CC_CSIZE_CHK_16_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 16 data transferred Position */ +#define XDMAC_CC_DWIDTH_Pos 11 /**< (XDMAC_CC) Channel x Data Width Position */ +#define XDMAC_CC_DWIDTH_Msk (_U_(0x3) << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) Channel x Data Width Mask */ +#define XDMAC_CC_DWIDTH(value) (XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)) +#define XDMAC_CC_DWIDTH_BYTE_Val _U_(0x0) /**< (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD_Val _U_(0x1) /**< (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD_Val _U_(0x2) /**< (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_DWIDTH_BYTE (XDMAC_CC_DWIDTH_BYTE_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 8 bits Position */ +#define XDMAC_CC_DWIDTH_HALFWORD (XDMAC_CC_DWIDTH_HALFWORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 16 bits Position */ +#define XDMAC_CC_DWIDTH_WORD (XDMAC_CC_DWIDTH_WORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 32 bits Position */ +#define XDMAC_CC_SIF_Pos 13 /**< (XDMAC_CC) Channel x Source Interface Identifier Position */ +#define XDMAC_CC_SIF_Msk (_U_(0x1) << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) Channel x Source Interface Identifier Mask */ +#define XDMAC_CC_SIF XDMAC_CC_SIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_SIF_Msk instead */ +#define XDMAC_CC_SIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_SIF_AHB_IF0 (XDMAC_CC_SIF_AHB_IF0_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 0. Position */ +#define XDMAC_CC_SIF_AHB_IF1 (XDMAC_CC_SIF_AHB_IF1_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 1. Position */ +#define XDMAC_CC_DIF_Pos 14 /**< (XDMAC_CC) Channel x Destination Interface Identifier Position */ +#define XDMAC_CC_DIF_Msk (_U_(0x1) << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) Channel x Destination Interface Identifier Mask */ +#define XDMAC_CC_DIF XDMAC_CC_DIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_DIF_Msk instead */ +#define XDMAC_CC_DIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_DIF_AHB_IF0 (XDMAC_CC_DIF_AHB_IF0_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written through the system bus interface 0. Position */ +#define XDMAC_CC_DIF_AHB_IF1 (XDMAC_CC_DIF_AHB_IF1_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written though the system bus interface 1. Position */ +#define XDMAC_CC_SAM_Pos 16 /**< (XDMAC_CC) Channel x Source Addressing Mode Position */ +#define XDMAC_CC_SAM_Msk (_U_(0x3) << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) Channel x Source Addressing Mode Mask */ +#define XDMAC_CC_SAM(value) (XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)) +#define XDMAC_CC_SAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_SAM_FIXED_AM (XDMAC_CC_SAM_FIXED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_SAM_INCREMENTED_AM (XDMAC_CC_SAM_INCREMENTED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_SAM_UBS_AM (XDMAC_CC_SAM_UBS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_SAM_UBS_DS_AM (XDMAC_CC_SAM_UBS_DS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Position */ +#define XDMAC_CC_DAM_Pos 18 /**< (XDMAC_CC) Channel x Destination Addressing Mode Position */ +#define XDMAC_CC_DAM_Msk (_U_(0x3) << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) Channel x Destination Addressing Mode Mask */ +#define XDMAC_CC_DAM(value) (XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)) +#define XDMAC_CC_DAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_FIXED_AM (XDMAC_CC_DAM_FIXED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_DAM_INCREMENTED_AM (XDMAC_CC_DAM_INCREMENTED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_DAM_UBS_AM (XDMAC_CC_DAM_UBS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_DAM_UBS_DS_AM (XDMAC_CC_DAM_UBS_DS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. Position */ +#define XDMAC_CC_INITD_Pos 21 /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Position */ +#define XDMAC_CC_INITD_Msk (_U_(0x1) << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Mask */ +#define XDMAC_CC_INITD XDMAC_CC_INITD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_INITD_Msk instead */ +#define XDMAC_CC_INITD_IN_PROGRESS_Val _U_(0x0) /**< (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_TERMINATED_Val _U_(0x1) /**< (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_INITD_IN_PROGRESS (XDMAC_CC_INITD_IN_PROGRESS_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is in progress. Position */ +#define XDMAC_CC_INITD_TERMINATED (XDMAC_CC_INITD_TERMINATED_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is completed. Position */ +#define XDMAC_CC_RDIP_Pos 22 /**< (XDMAC_CC) Read in Progress (this bit is read-only) Position */ +#define XDMAC_CC_RDIP_Msk (_U_(0x1) << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_RDIP XDMAC_CC_RDIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_RDIP_Msk instead */ +#define XDMAC_CC_RDIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_RDIP_DONE (XDMAC_CC_RDIP_DONE_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) No active read transaction on the bus. Position */ +#define XDMAC_CC_RDIP_IN_PROGRESS (XDMAC_CC_RDIP_IN_PROGRESS_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) A read transaction is in progress. Position */ +#define XDMAC_CC_WRIP_Pos 23 /**< (XDMAC_CC) Write in Progress (this bit is read-only) Position */ +#define XDMAC_CC_WRIP_Msk (_U_(0x1) << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_WRIP XDMAC_CC_WRIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_CC_WRIP_Msk instead */ +#define XDMAC_CC_WRIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A write transaction is in progress. */ +#define XDMAC_CC_WRIP_DONE (XDMAC_CC_WRIP_DONE_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) No active write transaction on the bus. Position */ +#define XDMAC_CC_WRIP_IN_PROGRESS (XDMAC_CC_WRIP_IN_PROGRESS_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) A write transaction is in progress. Position */ +#define XDMAC_CC_PERID_Pos 24 /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Position */ +#define XDMAC_CC_PERID_Msk (_U_(0x7F) << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Mask */ +#define XDMAC_CC_PERID(value) (XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)) +#define XDMAC_CC_PERID_HSMCI_Val _U_(0x0) /**< (XDMAC_CC) HSMCI */ +#define XDMAC_CC_PERID_SPI0_TX_Val _U_(0x1) /**< (XDMAC_CC) SPI0_TX */ +#define XDMAC_CC_PERID_SPI0_RX_Val _U_(0x2) /**< (XDMAC_CC) SPI0_RX */ +#define XDMAC_CC_PERID_SPI1_TX_Val _U_(0x3) /**< (XDMAC_CC) SPI1_TX */ +#define XDMAC_CC_PERID_SPI1_RX_Val _U_(0x4) /**< (XDMAC_CC) SPI1_RX */ +#define XDMAC_CC_PERID_QSPI_TX_Val _U_(0x5) /**< (XDMAC_CC) QSPI_TX */ +#define XDMAC_CC_PERID_QSPI_RX_Val _U_(0x6) /**< (XDMAC_CC) QSPI_RX */ +#define XDMAC_CC_PERID_USART0_TX_Val _U_(0x7) /**< (XDMAC_CC) USART0_TX */ +#define XDMAC_CC_PERID_USART0_RX_Val _U_(0x8) /**< (XDMAC_CC) USART0_RX */ +#define XDMAC_CC_PERID_USART1_TX_Val _U_(0x9) /**< (XDMAC_CC) USART1_TX */ +#define XDMAC_CC_PERID_USART1_RX_Val _U_(0xA) /**< (XDMAC_CC) USART1_RX */ +#define XDMAC_CC_PERID_USART2_TX_Val _U_(0xB) /**< (XDMAC_CC) USART2_TX */ +#define XDMAC_CC_PERID_USART2_RX_Val _U_(0xC) /**< (XDMAC_CC) USART2_RX */ +#define XDMAC_CC_PERID_PWM0_Val _U_(0xD) /**< (XDMAC_CC) PWM0 */ +#define XDMAC_CC_PERID_TWIHS0_TX_Val _U_(0xE) /**< (XDMAC_CC) TWIHS0_TX */ +#define XDMAC_CC_PERID_TWIHS0_RX_Val _U_(0xF) /**< (XDMAC_CC) TWIHS0_RX */ +#define XDMAC_CC_PERID_TWIHS1_TX_Val _U_(0x10) /**< (XDMAC_CC) TWIHS1_TX */ +#define XDMAC_CC_PERID_TWIHS1_RX_Val _U_(0x11) /**< (XDMAC_CC) TWIHS1_RX */ +#define XDMAC_CC_PERID_TWIHS2_TX_Val _U_(0x12) /**< (XDMAC_CC) TWIHS2_TX */ +#define XDMAC_CC_PERID_TWIHS2_RX_Val _U_(0x13) /**< (XDMAC_CC) TWIHS2_RX */ +#define XDMAC_CC_PERID_UART0_TX_Val _U_(0x14) /**< (XDMAC_CC) UART0_TX */ +#define XDMAC_CC_PERID_UART0_RX_Val _U_(0x15) /**< (XDMAC_CC) UART0_RX */ +#define XDMAC_CC_PERID_UART1_TX_Val _U_(0x16) /**< (XDMAC_CC) UART1_TX */ +#define XDMAC_CC_PERID_UART1_RX_Val _U_(0x17) /**< (XDMAC_CC) UART1_RX */ +#define XDMAC_CC_PERID_UART2_TX_Val _U_(0x18) /**< (XDMAC_CC) UART2_TX */ +#define XDMAC_CC_PERID_UART2_RX_Val _U_(0x19) /**< (XDMAC_CC) UART2_RX */ +#define XDMAC_CC_PERID_UART3_TX_Val _U_(0x1A) /**< (XDMAC_CC) UART3_TX */ +#define XDMAC_CC_PERID_UART3_RX_Val _U_(0x1B) /**< (XDMAC_CC) UART3_RX */ +#define XDMAC_CC_PERID_UART4_TX_Val _U_(0x1C) /**< (XDMAC_CC) UART4_TX */ +#define XDMAC_CC_PERID_UART4_RX_Val _U_(0x1D) /**< (XDMAC_CC) UART4_RX */ +#define XDMAC_CC_PERID_DACC0_Val _U_(0x1E) /**< (XDMAC_CC) DACC0 */ +#define XDMAC_CC_PERID_DACC1_Val _U_(0x1F) /**< (XDMAC_CC) DACC1 */ +#define XDMAC_CC_PERID_SSC_TX_Val _U_(0x20) /**< (XDMAC_CC) SSC_TX */ +#define XDMAC_CC_PERID_SSC_RX_Val _U_(0x21) /**< (XDMAC_CC) SSC_RX */ +#define XDMAC_CC_PERID_PIOA_Val _U_(0x22) /**< (XDMAC_CC) PIOA */ +#define XDMAC_CC_PERID_AFEC0_Val _U_(0x23) /**< (XDMAC_CC) AFEC0 */ +#define XDMAC_CC_PERID_AFEC1_Val _U_(0x24) /**< (XDMAC_CC) AFEC1 */ +#define XDMAC_CC_PERID_AES_TX_Val _U_(0x25) /**< (XDMAC_CC) AES_TX */ +#define XDMAC_CC_PERID_AES_RX_Val _U_(0x26) /**< (XDMAC_CC) AES_RX */ +#define XDMAC_CC_PERID_PWM1_Val _U_(0x27) /**< (XDMAC_CC) PWM1 */ +#define XDMAC_CC_PERID_TC0_Val _U_(0x28) /**< (XDMAC_CC) TC0 */ +#define XDMAC_CC_PERID_TC3_Val _U_(0x29) /**< (XDMAC_CC) TC3 */ +#define XDMAC_CC_PERID_TC6_Val _U_(0x2A) /**< (XDMAC_CC) TC6 */ +#define XDMAC_CC_PERID_TC9_Val _U_(0x2B) /**< (XDMAC_CC) TC9 */ +#define XDMAC_CC_PERID_I2SC0_TX_LEFT_Val _U_(0x2C) /**< (XDMAC_CC) I2SC0_TX_LEFT */ +#define XDMAC_CC_PERID_I2SC0_RX_LEFT_Val _U_(0x2D) /**< (XDMAC_CC) I2SC0_RX_LEFT */ +#define XDMAC_CC_PERID_I2SC1_TX_LEFT_Val _U_(0x2E) /**< (XDMAC_CC) I2SC1_TX_LEFT */ +#define XDMAC_CC_PERID_I2SC1_RX_LEFT_Val _U_(0x2F) /**< (XDMAC_CC) I2SC1_RX_LEFT */ +#define XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val _U_(0x30) /**< (XDMAC_CC) I2SC0_TX_RIGHT */ +#define XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val _U_(0x31) /**< (XDMAC_CC) I2SC0_RX_RIGHT */ +#define XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val _U_(0x32) /**< (XDMAC_CC) I2SC1_TX_RIGHT */ +#define XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val _U_(0x33) /**< (XDMAC_CC) I2SC1_RX_RIGHT */ +#define XDMAC_CC_PERID_HSMCI (XDMAC_CC_PERID_HSMCI_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) HSMCI Position */ +#define XDMAC_CC_PERID_SPI0_TX (XDMAC_CC_PERID_SPI0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_TX Position */ +#define XDMAC_CC_PERID_SPI0_RX (XDMAC_CC_PERID_SPI0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_RX Position */ +#define XDMAC_CC_PERID_SPI1_TX (XDMAC_CC_PERID_SPI1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_TX Position */ +#define XDMAC_CC_PERID_SPI1_RX (XDMAC_CC_PERID_SPI1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_RX Position */ +#define XDMAC_CC_PERID_QSPI_TX (XDMAC_CC_PERID_QSPI_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_TX Position */ +#define XDMAC_CC_PERID_QSPI_RX (XDMAC_CC_PERID_QSPI_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_RX Position */ +#define XDMAC_CC_PERID_USART0_TX (XDMAC_CC_PERID_USART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_TX Position */ +#define XDMAC_CC_PERID_USART0_RX (XDMAC_CC_PERID_USART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_RX Position */ +#define XDMAC_CC_PERID_USART1_TX (XDMAC_CC_PERID_USART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_TX Position */ +#define XDMAC_CC_PERID_USART1_RX (XDMAC_CC_PERID_USART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_RX Position */ +#define XDMAC_CC_PERID_USART2_TX (XDMAC_CC_PERID_USART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_TX Position */ +#define XDMAC_CC_PERID_USART2_RX (XDMAC_CC_PERID_USART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_RX Position */ +#define XDMAC_CC_PERID_PWM0 (XDMAC_CC_PERID_PWM0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM0 Position */ +#define XDMAC_CC_PERID_TWIHS0_TX (XDMAC_CC_PERID_TWIHS0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_TX Position */ +#define XDMAC_CC_PERID_TWIHS0_RX (XDMAC_CC_PERID_TWIHS0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_RX Position */ +#define XDMAC_CC_PERID_TWIHS1_TX (XDMAC_CC_PERID_TWIHS1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_TX Position */ +#define XDMAC_CC_PERID_TWIHS1_RX (XDMAC_CC_PERID_TWIHS1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_RX Position */ +#define XDMAC_CC_PERID_TWIHS2_TX (XDMAC_CC_PERID_TWIHS2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_TX Position */ +#define XDMAC_CC_PERID_TWIHS2_RX (XDMAC_CC_PERID_TWIHS2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_RX Position */ +#define XDMAC_CC_PERID_UART0_TX (XDMAC_CC_PERID_UART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_TX Position */ +#define XDMAC_CC_PERID_UART0_RX (XDMAC_CC_PERID_UART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_RX Position */ +#define XDMAC_CC_PERID_UART1_TX (XDMAC_CC_PERID_UART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_TX Position */ +#define XDMAC_CC_PERID_UART1_RX (XDMAC_CC_PERID_UART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_RX Position */ +#define XDMAC_CC_PERID_UART2_TX (XDMAC_CC_PERID_UART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_TX Position */ +#define XDMAC_CC_PERID_UART2_RX (XDMAC_CC_PERID_UART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_RX Position */ +#define XDMAC_CC_PERID_UART3_TX (XDMAC_CC_PERID_UART3_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_TX Position */ +#define XDMAC_CC_PERID_UART3_RX (XDMAC_CC_PERID_UART3_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_RX Position */ +#define XDMAC_CC_PERID_UART4_TX (XDMAC_CC_PERID_UART4_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_TX Position */ +#define XDMAC_CC_PERID_UART4_RX (XDMAC_CC_PERID_UART4_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_RX Position */ +#define XDMAC_CC_PERID_DACC0 (XDMAC_CC_PERID_DACC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC0 Position */ +#define XDMAC_CC_PERID_DACC1 (XDMAC_CC_PERID_DACC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC1 Position */ +#define XDMAC_CC_PERID_SSC_TX (XDMAC_CC_PERID_SSC_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_TX Position */ +#define XDMAC_CC_PERID_SSC_RX (XDMAC_CC_PERID_SSC_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_RX Position */ +#define XDMAC_CC_PERID_PIOA (XDMAC_CC_PERID_PIOA_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PIOA Position */ +#define XDMAC_CC_PERID_AFEC0 (XDMAC_CC_PERID_AFEC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC0 Position */ +#define XDMAC_CC_PERID_AFEC1 (XDMAC_CC_PERID_AFEC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC1 Position */ +#define XDMAC_CC_PERID_AES_TX (XDMAC_CC_PERID_AES_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_TX Position */ +#define XDMAC_CC_PERID_AES_RX (XDMAC_CC_PERID_AES_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_RX Position */ +#define XDMAC_CC_PERID_PWM1 (XDMAC_CC_PERID_PWM1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM1 Position */ +#define XDMAC_CC_PERID_TC0 (XDMAC_CC_PERID_TC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC0 Position */ +#define XDMAC_CC_PERID_TC3 (XDMAC_CC_PERID_TC3_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC3 Position */ +#define XDMAC_CC_PERID_TC6 (XDMAC_CC_PERID_TC6_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC6 Position */ +#define XDMAC_CC_PERID_TC9 (XDMAC_CC_PERID_TC9_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC9 Position */ +#define XDMAC_CC_PERID_I2SC0_TX_LEFT (XDMAC_CC_PERID_I2SC0_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC0_RX_LEFT (XDMAC_CC_PERID_I2SC0_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC1_TX_LEFT (XDMAC_CC_PERID_I2SC1_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC1_RX_LEFT (XDMAC_CC_PERID_I2SC1_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC0_TX_RIGHT (XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC0_RX_RIGHT (XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC1_TX_RIGHT (XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC1_RX_RIGHT (XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_RIGHT Position */ +#define XDMAC_CC_MASK _U_(0x7FEF7FD7) /**< \deprecated (XDMAC_CC) Register MASK (Use XDMAC_CC_Msk instead) */ +#define XDMAC_CC_Msk _U_(0x7FEF7FD7) /**< (XDMAC_CC) Register Mask */ + + +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: 0x2c) (R/W 32) Channel Data Stride Memory Set Pattern -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SDS_MSP:16; /**< bit: 0..15 Channel x Source Data stride or Memory Set Pattern */ + uint32_t DDS_MSP:16; /**< bit: 16..31 Channel x Destination Data Stride or Memory Set Pattern */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CDS_MSP_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CDS_MSP_OFFSET (0x2C) /**< (XDMAC_CDS_MSP) Channel Data Stride Memory Set Pattern Offset */ + +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_SDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_SDS_MSP(value) (XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_DDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_DDS_MSP(value) (XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)) +#define XDMAC_CDS_MSP_MASK _U_(0xFFFFFFFF) /**< \deprecated (XDMAC_CDS_MSP) Register MASK (Use XDMAC_CDS_MSP_Msk instead) */ +#define XDMAC_CDS_MSP_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDS_MSP) Register Mask */ + + +/* -------- XDMAC_CSUS : (XDMAC Offset: 0x30) (R/W 32) Channel Source Microblock Stride -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SUBS:24; /**< bit: 0..23 Channel x Source Microblock Stride */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CSUS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CSUS_OFFSET (0x30) /**< (XDMAC_CSUS) Channel Source Microblock Stride Offset */ + +#define XDMAC_CSUS_SUBS_Pos 0 /**< (XDMAC_CSUS) Channel x Source Microblock Stride Position */ +#define XDMAC_CSUS_SUBS_Msk (_U_(0xFFFFFF) << XDMAC_CSUS_SUBS_Pos) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Mask */ +#define XDMAC_CSUS_SUBS(value) (XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)) +#define XDMAC_CSUS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CSUS) Register MASK (Use XDMAC_CSUS_Msk instead) */ +#define XDMAC_CSUS_Msk _U_(0xFFFFFF) /**< (XDMAC_CSUS) Register Mask */ + + +/* -------- XDMAC_CDUS : (XDMAC Offset: 0x34) (R/W 32) Channel Destination Microblock Stride -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DUBS:24; /**< bit: 0..23 Channel x Destination Microblock Stride */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_CDUS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_CDUS_OFFSET (0x34) /**< (XDMAC_CDUS) Channel Destination Microblock Stride Offset */ + +#define XDMAC_CDUS_DUBS_Pos 0 /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Position */ +#define XDMAC_CDUS_DUBS_Msk (_U_(0xFFFFFF) << XDMAC_CDUS_DUBS_Pos) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Mask */ +#define XDMAC_CDUS_DUBS(value) (XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)) +#define XDMAC_CDUS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_CDUS) Register MASK (Use XDMAC_CDUS_Msk instead) */ +#define XDMAC_CDUS_Msk _U_(0xFFFFFF) /**< (XDMAC_CDUS) Register Mask */ + + +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) (R/ 32) Global Type Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t NB_CH:5; /**< bit: 0..4 Number of Channels Minus One */ + uint32_t FIFO_SZ:11; /**< bit: 5..15 Number of Bytes */ + uint32_t NB_REQ:7; /**< bit: 16..22 Number of Peripheral Requests Minus One */ + uint32_t :9; /**< bit: 23..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GTYPE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GTYPE_OFFSET (0x00) /**< (XDMAC_GTYPE) Global Type Register Offset */ + +#define XDMAC_GTYPE_NB_CH_Pos 0 /**< (XDMAC_GTYPE) Number of Channels Minus One Position */ +#define XDMAC_GTYPE_NB_CH_Msk (_U_(0x1F) << XDMAC_GTYPE_NB_CH_Pos) /**< (XDMAC_GTYPE) Number of Channels Minus One Mask */ +#define XDMAC_GTYPE_NB_CH(value) (XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 /**< (XDMAC_GTYPE) Number of Bytes Position */ +#define XDMAC_GTYPE_FIFO_SZ_Msk (_U_(0x7FF) << XDMAC_GTYPE_FIFO_SZ_Pos) /**< (XDMAC_GTYPE) Number of Bytes Mask */ +#define XDMAC_GTYPE_FIFO_SZ(value) (XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)) +#define XDMAC_GTYPE_NB_REQ_Pos 16 /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Position */ +#define XDMAC_GTYPE_NB_REQ_Msk (_U_(0x7F) << XDMAC_GTYPE_NB_REQ_Pos) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Mask */ +#define XDMAC_GTYPE_NB_REQ(value) (XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)) +#define XDMAC_GTYPE_MASK _U_(0x7FFFFF) /**< \deprecated (XDMAC_GTYPE) Register MASK (Use XDMAC_GTYPE_Msk instead) */ +#define XDMAC_GTYPE_Msk _U_(0x7FFFFF) /**< (XDMAC_GTYPE) Register Mask */ + + +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) (R/W 32) Global Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t CGDISREG:1; /**< bit: 0 Configuration Registers Clock Gating Disable */ + uint32_t CGDISPIPE:1; /**< bit: 1 Pipeline Clock Gating Disable */ + uint32_t CGDISFIFO:1; /**< bit: 2 FIFO Clock Gating Disable */ + uint32_t CGDISIF:1; /**< bit: 3 Bus Interface Clock Gating Disable */ + uint32_t :4; /**< bit: 4..7 Reserved */ + uint32_t BXKBEN:1; /**< bit: 8 Boundary X Kilobyte Enable */ + uint32_t :23; /**< bit: 9..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GCFG_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GCFG_OFFSET (0x04) /**< (XDMAC_GCFG) Global Configuration Register Offset */ + +#define XDMAC_GCFG_CGDISREG_Pos 0 /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISREG_Msk (_U_(0x1) << XDMAC_GCFG_CGDISREG_Pos) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISREG XDMAC_GCFG_CGDISREG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISREG_Msk instead */ +#define XDMAC_GCFG_CGDISPIPE_Pos 1 /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISPIPE_Msk (_U_(0x1) << XDMAC_GCFG_CGDISPIPE_Pos) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISPIPE XDMAC_GCFG_CGDISPIPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISPIPE_Msk instead */ +#define XDMAC_GCFG_CGDISFIFO_Pos 2 /**< (XDMAC_GCFG) FIFO Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISFIFO_Msk (_U_(0x1) << XDMAC_GCFG_CGDISFIFO_Pos) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISFIFO XDMAC_GCFG_CGDISFIFO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISFIFO_Msk instead */ +#define XDMAC_GCFG_CGDISIF_Pos 3 /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISIF_Msk (_U_(0x1) << XDMAC_GCFG_CGDISIF_Pos) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISIF XDMAC_GCFG_CGDISIF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_CGDISIF_Msk instead */ +#define XDMAC_GCFG_BXKBEN_Pos 8 /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Position */ +#define XDMAC_GCFG_BXKBEN_Msk (_U_(0x1) << XDMAC_GCFG_BXKBEN_Pos) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Mask */ +#define XDMAC_GCFG_BXKBEN XDMAC_GCFG_BXKBEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GCFG_BXKBEN_Msk instead */ +#define XDMAC_GCFG_MASK _U_(0x10F) /**< \deprecated (XDMAC_GCFG) Register MASK (Use XDMAC_GCFG_Msk instead) */ +#define XDMAC_GCFG_Msk _U_(0x10F) /**< (XDMAC_GCFG) Register Mask */ + + +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) (R/W 32) Global Weighted Arbiter Configuration Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t PW0:4; /**< bit: 0..3 Pool Weight 0 */ + uint32_t PW1:4; /**< bit: 4..7 Pool Weight 1 */ + uint32_t PW2:4; /**< bit: 8..11 Pool Weight 2 */ + uint32_t PW3:4; /**< bit: 12..15 Pool Weight 3 */ + uint32_t :16; /**< bit: 16..31 Reserved */ + } bit; /**< Structure used for bit access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GWAC_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GWAC_OFFSET (0x08) /**< (XDMAC_GWAC) Global Weighted Arbiter Configuration Register Offset */ + +#define XDMAC_GWAC_PW0_Pos 0 /**< (XDMAC_GWAC) Pool Weight 0 Position */ +#define XDMAC_GWAC_PW0_Msk (_U_(0xF) << XDMAC_GWAC_PW0_Pos) /**< (XDMAC_GWAC) Pool Weight 0 Mask */ +#define XDMAC_GWAC_PW0(value) (XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)) +#define XDMAC_GWAC_PW1_Pos 4 /**< (XDMAC_GWAC) Pool Weight 1 Position */ +#define XDMAC_GWAC_PW1_Msk (_U_(0xF) << XDMAC_GWAC_PW1_Pos) /**< (XDMAC_GWAC) Pool Weight 1 Mask */ +#define XDMAC_GWAC_PW1(value) (XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)) +#define XDMAC_GWAC_PW2_Pos 8 /**< (XDMAC_GWAC) Pool Weight 2 Position */ +#define XDMAC_GWAC_PW2_Msk (_U_(0xF) << XDMAC_GWAC_PW2_Pos) /**< (XDMAC_GWAC) Pool Weight 2 Mask */ +#define XDMAC_GWAC_PW2(value) (XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)) +#define XDMAC_GWAC_PW3_Pos 12 /**< (XDMAC_GWAC) Pool Weight 3 Position */ +#define XDMAC_GWAC_PW3_Msk (_U_(0xF) << XDMAC_GWAC_PW3_Pos) /**< (XDMAC_GWAC) Pool Weight 3 Mask */ +#define XDMAC_GWAC_PW3(value) (XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)) +#define XDMAC_GWAC_MASK _U_(0xFFFF) /**< \deprecated (XDMAC_GWAC) Register MASK (Use XDMAC_GWAC_Msk instead) */ +#define XDMAC_GWAC_Msk _U_(0xFFFF) /**< (XDMAC_GWAC) Register Mask */ + + +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0c) (/W 32) Global Interrupt Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IE0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Enable Bit */ + uint32_t IE1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Enable Bit */ + uint32_t IE2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Enable Bit */ + uint32_t IE3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Enable Bit */ + uint32_t IE4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Enable Bit */ + uint32_t IE5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Enable Bit */ + uint32_t IE6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Enable Bit */ + uint32_t IE7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Enable Bit */ + uint32_t IE8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Enable Bit */ + uint32_t IE9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Enable Bit */ + uint32_t IE10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Enable Bit */ + uint32_t IE11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Enable Bit */ + uint32_t IE12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Enable Bit */ + uint32_t IE13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Enable Bit */ + uint32_t IE14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Enable Bit */ + uint32_t IE15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Enable Bit */ + uint32_t IE16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Enable Bit */ + uint32_t IE17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Enable Bit */ + uint32_t IE18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Enable Bit */ + uint32_t IE19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Enable Bit */ + uint32_t IE20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Enable Bit */ + uint32_t IE21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Enable Bit */ + uint32_t IE22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Enable Bit */ + uint32_t IE23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Enable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t IE:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Enable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GIE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GIE_OFFSET (0x0C) /**< (XDMAC_GIE) Global Interrupt Enable Register Offset */ + +#define XDMAC_GIE_IE0_Pos 0 /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE0_Msk (_U_(0x1) << XDMAC_GIE_IE0_Pos) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE0 XDMAC_GIE_IE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE0_Msk instead */ +#define XDMAC_GIE_IE1_Pos 1 /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE1_Msk (_U_(0x1) << XDMAC_GIE_IE1_Pos) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE1 XDMAC_GIE_IE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE1_Msk instead */ +#define XDMAC_GIE_IE2_Pos 2 /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE2_Msk (_U_(0x1) << XDMAC_GIE_IE2_Pos) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE2 XDMAC_GIE_IE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE2_Msk instead */ +#define XDMAC_GIE_IE3_Pos 3 /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE3_Msk (_U_(0x1) << XDMAC_GIE_IE3_Pos) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE3 XDMAC_GIE_IE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE3_Msk instead */ +#define XDMAC_GIE_IE4_Pos 4 /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE4_Msk (_U_(0x1) << XDMAC_GIE_IE4_Pos) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE4 XDMAC_GIE_IE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE4_Msk instead */ +#define XDMAC_GIE_IE5_Pos 5 /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE5_Msk (_U_(0x1) << XDMAC_GIE_IE5_Pos) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE5 XDMAC_GIE_IE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE5_Msk instead */ +#define XDMAC_GIE_IE6_Pos 6 /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE6_Msk (_U_(0x1) << XDMAC_GIE_IE6_Pos) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE6 XDMAC_GIE_IE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE6_Msk instead */ +#define XDMAC_GIE_IE7_Pos 7 /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE7_Msk (_U_(0x1) << XDMAC_GIE_IE7_Pos) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE7 XDMAC_GIE_IE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE7_Msk instead */ +#define XDMAC_GIE_IE8_Pos 8 /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE8_Msk (_U_(0x1) << XDMAC_GIE_IE8_Pos) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE8 XDMAC_GIE_IE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE8_Msk instead */ +#define XDMAC_GIE_IE9_Pos 9 /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE9_Msk (_U_(0x1) << XDMAC_GIE_IE9_Pos) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE9 XDMAC_GIE_IE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE9_Msk instead */ +#define XDMAC_GIE_IE10_Pos 10 /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE10_Msk (_U_(0x1) << XDMAC_GIE_IE10_Pos) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE10 XDMAC_GIE_IE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE10_Msk instead */ +#define XDMAC_GIE_IE11_Pos 11 /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE11_Msk (_U_(0x1) << XDMAC_GIE_IE11_Pos) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE11 XDMAC_GIE_IE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE11_Msk instead */ +#define XDMAC_GIE_IE12_Pos 12 /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE12_Msk (_U_(0x1) << XDMAC_GIE_IE12_Pos) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE12 XDMAC_GIE_IE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE12_Msk instead */ +#define XDMAC_GIE_IE13_Pos 13 /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE13_Msk (_U_(0x1) << XDMAC_GIE_IE13_Pos) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE13 XDMAC_GIE_IE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE13_Msk instead */ +#define XDMAC_GIE_IE14_Pos 14 /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE14_Msk (_U_(0x1) << XDMAC_GIE_IE14_Pos) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE14 XDMAC_GIE_IE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE14_Msk instead */ +#define XDMAC_GIE_IE15_Pos 15 /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE15_Msk (_U_(0x1) << XDMAC_GIE_IE15_Pos) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE15 XDMAC_GIE_IE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE15_Msk instead */ +#define XDMAC_GIE_IE16_Pos 16 /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE16_Msk (_U_(0x1) << XDMAC_GIE_IE16_Pos) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE16 XDMAC_GIE_IE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE16_Msk instead */ +#define XDMAC_GIE_IE17_Pos 17 /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE17_Msk (_U_(0x1) << XDMAC_GIE_IE17_Pos) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE17 XDMAC_GIE_IE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE17_Msk instead */ +#define XDMAC_GIE_IE18_Pos 18 /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE18_Msk (_U_(0x1) << XDMAC_GIE_IE18_Pos) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE18 XDMAC_GIE_IE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE18_Msk instead */ +#define XDMAC_GIE_IE19_Pos 19 /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE19_Msk (_U_(0x1) << XDMAC_GIE_IE19_Pos) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE19 XDMAC_GIE_IE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE19_Msk instead */ +#define XDMAC_GIE_IE20_Pos 20 /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE20_Msk (_U_(0x1) << XDMAC_GIE_IE20_Pos) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE20 XDMAC_GIE_IE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE20_Msk instead */ +#define XDMAC_GIE_IE21_Pos 21 /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE21_Msk (_U_(0x1) << XDMAC_GIE_IE21_Pos) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE21 XDMAC_GIE_IE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE21_Msk instead */ +#define XDMAC_GIE_IE22_Pos 22 /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE22_Msk (_U_(0x1) << XDMAC_GIE_IE22_Pos) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE22 XDMAC_GIE_IE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE22_Msk instead */ +#define XDMAC_GIE_IE23_Pos 23 /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE23_Msk (_U_(0x1) << XDMAC_GIE_IE23_Pos) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE23 XDMAC_GIE_IE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIE_IE23_Msk instead */ +#define XDMAC_GIE_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIE) Register MASK (Use XDMAC_GIE_Msk instead) */ +#define XDMAC_GIE_Msk _U_(0xFFFFFF) /**< (XDMAC_GIE) Register Mask */ + +#define XDMAC_GIE_IE_Pos 0 /**< (XDMAC_GIE Position) XDMAC Channel 23 Interrupt Enable Bit */ +#define XDMAC_GIE_IE_Msk (_U_(0xFFFFFF) << XDMAC_GIE_IE_Pos) /**< (XDMAC_GIE Mask) IE */ +#define XDMAC_GIE_IE(value) (XDMAC_GIE_IE_Msk & ((value) << XDMAC_GIE_IE_Pos)) + +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) (/W 32) Global Interrupt Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ID0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Disable Bit */ + uint32_t ID1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Disable Bit */ + uint32_t ID2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Disable Bit */ + uint32_t ID3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Disable Bit */ + uint32_t ID4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Disable Bit */ + uint32_t ID5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Disable Bit */ + uint32_t ID6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Disable Bit */ + uint32_t ID7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Disable Bit */ + uint32_t ID8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Disable Bit */ + uint32_t ID9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Disable Bit */ + uint32_t ID10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Disable Bit */ + uint32_t ID11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Disable Bit */ + uint32_t ID12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Disable Bit */ + uint32_t ID13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Disable Bit */ + uint32_t ID14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Disable Bit */ + uint32_t ID15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Disable Bit */ + uint32_t ID16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Disable Bit */ + uint32_t ID17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Disable Bit */ + uint32_t ID18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Disable Bit */ + uint32_t ID19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Disable Bit */ + uint32_t ID20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Disable Bit */ + uint32_t ID21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Disable Bit */ + uint32_t ID22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Disable Bit */ + uint32_t ID23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Disable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ID:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Disable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GID_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GID_OFFSET (0x10) /**< (XDMAC_GID) Global Interrupt Disable Register Offset */ + +#define XDMAC_GID_ID0_Pos 0 /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID0_Msk (_U_(0x1) << XDMAC_GID_ID0_Pos) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID0 XDMAC_GID_ID0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID0_Msk instead */ +#define XDMAC_GID_ID1_Pos 1 /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID1_Msk (_U_(0x1) << XDMAC_GID_ID1_Pos) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID1 XDMAC_GID_ID1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID1_Msk instead */ +#define XDMAC_GID_ID2_Pos 2 /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID2_Msk (_U_(0x1) << XDMAC_GID_ID2_Pos) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID2 XDMAC_GID_ID2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID2_Msk instead */ +#define XDMAC_GID_ID3_Pos 3 /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID3_Msk (_U_(0x1) << XDMAC_GID_ID3_Pos) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID3 XDMAC_GID_ID3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID3_Msk instead */ +#define XDMAC_GID_ID4_Pos 4 /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID4_Msk (_U_(0x1) << XDMAC_GID_ID4_Pos) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID4 XDMAC_GID_ID4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID4_Msk instead */ +#define XDMAC_GID_ID5_Pos 5 /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID5_Msk (_U_(0x1) << XDMAC_GID_ID5_Pos) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID5 XDMAC_GID_ID5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID5_Msk instead */ +#define XDMAC_GID_ID6_Pos 6 /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID6_Msk (_U_(0x1) << XDMAC_GID_ID6_Pos) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID6 XDMAC_GID_ID6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID6_Msk instead */ +#define XDMAC_GID_ID7_Pos 7 /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID7_Msk (_U_(0x1) << XDMAC_GID_ID7_Pos) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID7 XDMAC_GID_ID7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID7_Msk instead */ +#define XDMAC_GID_ID8_Pos 8 /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID8_Msk (_U_(0x1) << XDMAC_GID_ID8_Pos) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID8 XDMAC_GID_ID8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID8_Msk instead */ +#define XDMAC_GID_ID9_Pos 9 /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID9_Msk (_U_(0x1) << XDMAC_GID_ID9_Pos) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID9 XDMAC_GID_ID9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID9_Msk instead */ +#define XDMAC_GID_ID10_Pos 10 /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID10_Msk (_U_(0x1) << XDMAC_GID_ID10_Pos) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID10 XDMAC_GID_ID10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID10_Msk instead */ +#define XDMAC_GID_ID11_Pos 11 /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID11_Msk (_U_(0x1) << XDMAC_GID_ID11_Pos) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID11 XDMAC_GID_ID11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID11_Msk instead */ +#define XDMAC_GID_ID12_Pos 12 /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID12_Msk (_U_(0x1) << XDMAC_GID_ID12_Pos) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID12 XDMAC_GID_ID12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID12_Msk instead */ +#define XDMAC_GID_ID13_Pos 13 /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID13_Msk (_U_(0x1) << XDMAC_GID_ID13_Pos) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID13 XDMAC_GID_ID13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID13_Msk instead */ +#define XDMAC_GID_ID14_Pos 14 /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID14_Msk (_U_(0x1) << XDMAC_GID_ID14_Pos) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID14 XDMAC_GID_ID14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID14_Msk instead */ +#define XDMAC_GID_ID15_Pos 15 /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID15_Msk (_U_(0x1) << XDMAC_GID_ID15_Pos) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID15 XDMAC_GID_ID15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID15_Msk instead */ +#define XDMAC_GID_ID16_Pos 16 /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID16_Msk (_U_(0x1) << XDMAC_GID_ID16_Pos) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID16 XDMAC_GID_ID16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID16_Msk instead */ +#define XDMAC_GID_ID17_Pos 17 /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID17_Msk (_U_(0x1) << XDMAC_GID_ID17_Pos) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID17 XDMAC_GID_ID17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID17_Msk instead */ +#define XDMAC_GID_ID18_Pos 18 /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID18_Msk (_U_(0x1) << XDMAC_GID_ID18_Pos) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID18 XDMAC_GID_ID18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID18_Msk instead */ +#define XDMAC_GID_ID19_Pos 19 /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID19_Msk (_U_(0x1) << XDMAC_GID_ID19_Pos) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID19 XDMAC_GID_ID19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID19_Msk instead */ +#define XDMAC_GID_ID20_Pos 20 /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID20_Msk (_U_(0x1) << XDMAC_GID_ID20_Pos) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID20 XDMAC_GID_ID20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID20_Msk instead */ +#define XDMAC_GID_ID21_Pos 21 /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID21_Msk (_U_(0x1) << XDMAC_GID_ID21_Pos) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID21 XDMAC_GID_ID21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID21_Msk instead */ +#define XDMAC_GID_ID22_Pos 22 /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID22_Msk (_U_(0x1) << XDMAC_GID_ID22_Pos) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID22 XDMAC_GID_ID22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID22_Msk instead */ +#define XDMAC_GID_ID23_Pos 23 /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID23_Msk (_U_(0x1) << XDMAC_GID_ID23_Pos) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID23 XDMAC_GID_ID23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GID_ID23_Msk instead */ +#define XDMAC_GID_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GID) Register MASK (Use XDMAC_GID_Msk instead) */ +#define XDMAC_GID_Msk _U_(0xFFFFFF) /**< (XDMAC_GID) Register Mask */ + +#define XDMAC_GID_ID_Pos 0 /**< (XDMAC_GID Position) XDMAC Channel 23 Interrupt Disable Bit */ +#define XDMAC_GID_ID_Msk (_U_(0xFFFFFF) << XDMAC_GID_ID_Pos) /**< (XDMAC_GID Mask) ID */ +#define XDMAC_GID_ID(value) (XDMAC_GID_ID_Msk & ((value) << XDMAC_GID_ID_Pos)) + +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) (R/ 32) Global Interrupt Mask Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IM0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Mask Bit */ + uint32_t IM1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Mask Bit */ + uint32_t IM2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Mask Bit */ + uint32_t IM3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Mask Bit */ + uint32_t IM4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Mask Bit */ + uint32_t IM5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Mask Bit */ + uint32_t IM6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Mask Bit */ + uint32_t IM7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Mask Bit */ + uint32_t IM8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Mask Bit */ + uint32_t IM9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Mask Bit */ + uint32_t IM10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Mask Bit */ + uint32_t IM11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Mask Bit */ + uint32_t IM12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Mask Bit */ + uint32_t IM13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Mask Bit */ + uint32_t IM14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Mask Bit */ + uint32_t IM15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Mask Bit */ + uint32_t IM16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Mask Bit */ + uint32_t IM17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Mask Bit */ + uint32_t IM18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Mask Bit */ + uint32_t IM19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Mask Bit */ + uint32_t IM20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Mask Bit */ + uint32_t IM21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Mask Bit */ + uint32_t IM22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Mask Bit */ + uint32_t IM23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Mask Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t IM:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Mask Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GIM_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GIM_OFFSET (0x14) /**< (XDMAC_GIM) Global Interrupt Mask Register Offset */ + +#define XDMAC_GIM_IM0_Pos 0 /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM0_Msk (_U_(0x1) << XDMAC_GIM_IM0_Pos) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM0 XDMAC_GIM_IM0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM0_Msk instead */ +#define XDMAC_GIM_IM1_Pos 1 /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM1_Msk (_U_(0x1) << XDMAC_GIM_IM1_Pos) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM1 XDMAC_GIM_IM1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM1_Msk instead */ +#define XDMAC_GIM_IM2_Pos 2 /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM2_Msk (_U_(0x1) << XDMAC_GIM_IM2_Pos) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM2 XDMAC_GIM_IM2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM2_Msk instead */ +#define XDMAC_GIM_IM3_Pos 3 /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM3_Msk (_U_(0x1) << XDMAC_GIM_IM3_Pos) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM3 XDMAC_GIM_IM3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM3_Msk instead */ +#define XDMAC_GIM_IM4_Pos 4 /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM4_Msk (_U_(0x1) << XDMAC_GIM_IM4_Pos) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM4 XDMAC_GIM_IM4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM4_Msk instead */ +#define XDMAC_GIM_IM5_Pos 5 /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM5_Msk (_U_(0x1) << XDMAC_GIM_IM5_Pos) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM5 XDMAC_GIM_IM5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM5_Msk instead */ +#define XDMAC_GIM_IM6_Pos 6 /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM6_Msk (_U_(0x1) << XDMAC_GIM_IM6_Pos) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM6 XDMAC_GIM_IM6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM6_Msk instead */ +#define XDMAC_GIM_IM7_Pos 7 /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM7_Msk (_U_(0x1) << XDMAC_GIM_IM7_Pos) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM7 XDMAC_GIM_IM7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM7_Msk instead */ +#define XDMAC_GIM_IM8_Pos 8 /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM8_Msk (_U_(0x1) << XDMAC_GIM_IM8_Pos) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM8 XDMAC_GIM_IM8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM8_Msk instead */ +#define XDMAC_GIM_IM9_Pos 9 /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM9_Msk (_U_(0x1) << XDMAC_GIM_IM9_Pos) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM9 XDMAC_GIM_IM9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM9_Msk instead */ +#define XDMAC_GIM_IM10_Pos 10 /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM10_Msk (_U_(0x1) << XDMAC_GIM_IM10_Pos) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM10 XDMAC_GIM_IM10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM10_Msk instead */ +#define XDMAC_GIM_IM11_Pos 11 /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM11_Msk (_U_(0x1) << XDMAC_GIM_IM11_Pos) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM11 XDMAC_GIM_IM11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM11_Msk instead */ +#define XDMAC_GIM_IM12_Pos 12 /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM12_Msk (_U_(0x1) << XDMAC_GIM_IM12_Pos) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM12 XDMAC_GIM_IM12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM12_Msk instead */ +#define XDMAC_GIM_IM13_Pos 13 /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM13_Msk (_U_(0x1) << XDMAC_GIM_IM13_Pos) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM13 XDMAC_GIM_IM13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM13_Msk instead */ +#define XDMAC_GIM_IM14_Pos 14 /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM14_Msk (_U_(0x1) << XDMAC_GIM_IM14_Pos) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM14 XDMAC_GIM_IM14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM14_Msk instead */ +#define XDMAC_GIM_IM15_Pos 15 /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM15_Msk (_U_(0x1) << XDMAC_GIM_IM15_Pos) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM15 XDMAC_GIM_IM15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM15_Msk instead */ +#define XDMAC_GIM_IM16_Pos 16 /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM16_Msk (_U_(0x1) << XDMAC_GIM_IM16_Pos) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM16 XDMAC_GIM_IM16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM16_Msk instead */ +#define XDMAC_GIM_IM17_Pos 17 /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM17_Msk (_U_(0x1) << XDMAC_GIM_IM17_Pos) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM17 XDMAC_GIM_IM17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM17_Msk instead */ +#define XDMAC_GIM_IM18_Pos 18 /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM18_Msk (_U_(0x1) << XDMAC_GIM_IM18_Pos) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM18 XDMAC_GIM_IM18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM18_Msk instead */ +#define XDMAC_GIM_IM19_Pos 19 /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM19_Msk (_U_(0x1) << XDMAC_GIM_IM19_Pos) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM19 XDMAC_GIM_IM19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM19_Msk instead */ +#define XDMAC_GIM_IM20_Pos 20 /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM20_Msk (_U_(0x1) << XDMAC_GIM_IM20_Pos) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM20 XDMAC_GIM_IM20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM20_Msk instead */ +#define XDMAC_GIM_IM21_Pos 21 /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM21_Msk (_U_(0x1) << XDMAC_GIM_IM21_Pos) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM21 XDMAC_GIM_IM21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM21_Msk instead */ +#define XDMAC_GIM_IM22_Pos 22 /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM22_Msk (_U_(0x1) << XDMAC_GIM_IM22_Pos) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM22 XDMAC_GIM_IM22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM22_Msk instead */ +#define XDMAC_GIM_IM23_Pos 23 /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM23_Msk (_U_(0x1) << XDMAC_GIM_IM23_Pos) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM23 XDMAC_GIM_IM23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIM_IM23_Msk instead */ +#define XDMAC_GIM_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIM) Register MASK (Use XDMAC_GIM_Msk instead) */ +#define XDMAC_GIM_Msk _U_(0xFFFFFF) /**< (XDMAC_GIM) Register Mask */ + +#define XDMAC_GIM_IM_Pos 0 /**< (XDMAC_GIM Position) XDMAC Channel 23 Interrupt Mask Bit */ +#define XDMAC_GIM_IM_Msk (_U_(0xFFFFFF) << XDMAC_GIM_IM_Pos) /**< (XDMAC_GIM Mask) IM */ +#define XDMAC_GIM_IM(value) (XDMAC_GIM_IM_Msk & ((value) << XDMAC_GIM_IM_Pos)) + +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) (R/ 32) Global Interrupt Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t IS0:1; /**< bit: 0 XDMAC Channel 0 Interrupt Status Bit */ + uint32_t IS1:1; /**< bit: 1 XDMAC Channel 1 Interrupt Status Bit */ + uint32_t IS2:1; /**< bit: 2 XDMAC Channel 2 Interrupt Status Bit */ + uint32_t IS3:1; /**< bit: 3 XDMAC Channel 3 Interrupt Status Bit */ + uint32_t IS4:1; /**< bit: 4 XDMAC Channel 4 Interrupt Status Bit */ + uint32_t IS5:1; /**< bit: 5 XDMAC Channel 5 Interrupt Status Bit */ + uint32_t IS6:1; /**< bit: 6 XDMAC Channel 6 Interrupt Status Bit */ + uint32_t IS7:1; /**< bit: 7 XDMAC Channel 7 Interrupt Status Bit */ + uint32_t IS8:1; /**< bit: 8 XDMAC Channel 8 Interrupt Status Bit */ + uint32_t IS9:1; /**< bit: 9 XDMAC Channel 9 Interrupt Status Bit */ + uint32_t IS10:1; /**< bit: 10 XDMAC Channel 10 Interrupt Status Bit */ + uint32_t IS11:1; /**< bit: 11 XDMAC Channel 11 Interrupt Status Bit */ + uint32_t IS12:1; /**< bit: 12 XDMAC Channel 12 Interrupt Status Bit */ + uint32_t IS13:1; /**< bit: 13 XDMAC Channel 13 Interrupt Status Bit */ + uint32_t IS14:1; /**< bit: 14 XDMAC Channel 14 Interrupt Status Bit */ + uint32_t IS15:1; /**< bit: 15 XDMAC Channel 15 Interrupt Status Bit */ + uint32_t IS16:1; /**< bit: 16 XDMAC Channel 16 Interrupt Status Bit */ + uint32_t IS17:1; /**< bit: 17 XDMAC Channel 17 Interrupt Status Bit */ + uint32_t IS18:1; /**< bit: 18 XDMAC Channel 18 Interrupt Status Bit */ + uint32_t IS19:1; /**< bit: 19 XDMAC Channel 19 Interrupt Status Bit */ + uint32_t IS20:1; /**< bit: 20 XDMAC Channel 20 Interrupt Status Bit */ + uint32_t IS21:1; /**< bit: 21 XDMAC Channel 21 Interrupt Status Bit */ + uint32_t IS22:1; /**< bit: 22 XDMAC Channel 22 Interrupt Status Bit */ + uint32_t IS23:1; /**< bit: 23 XDMAC Channel 23 Interrupt Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t IS:24; /**< bit: 0..23 XDMAC Channel 23 Interrupt Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GIS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GIS_OFFSET (0x18) /**< (XDMAC_GIS) Global Interrupt Status Register Offset */ + +#define XDMAC_GIS_IS0_Pos 0 /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS0_Msk (_U_(0x1) << XDMAC_GIS_IS0_Pos) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS0 XDMAC_GIS_IS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS0_Msk instead */ +#define XDMAC_GIS_IS1_Pos 1 /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS1_Msk (_U_(0x1) << XDMAC_GIS_IS1_Pos) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS1 XDMAC_GIS_IS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS1_Msk instead */ +#define XDMAC_GIS_IS2_Pos 2 /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS2_Msk (_U_(0x1) << XDMAC_GIS_IS2_Pos) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS2 XDMAC_GIS_IS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS2_Msk instead */ +#define XDMAC_GIS_IS3_Pos 3 /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS3_Msk (_U_(0x1) << XDMAC_GIS_IS3_Pos) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS3 XDMAC_GIS_IS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS3_Msk instead */ +#define XDMAC_GIS_IS4_Pos 4 /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS4_Msk (_U_(0x1) << XDMAC_GIS_IS4_Pos) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS4 XDMAC_GIS_IS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS4_Msk instead */ +#define XDMAC_GIS_IS5_Pos 5 /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS5_Msk (_U_(0x1) << XDMAC_GIS_IS5_Pos) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS5 XDMAC_GIS_IS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS5_Msk instead */ +#define XDMAC_GIS_IS6_Pos 6 /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS6_Msk (_U_(0x1) << XDMAC_GIS_IS6_Pos) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS6 XDMAC_GIS_IS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS6_Msk instead */ +#define XDMAC_GIS_IS7_Pos 7 /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS7_Msk (_U_(0x1) << XDMAC_GIS_IS7_Pos) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS7 XDMAC_GIS_IS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS7_Msk instead */ +#define XDMAC_GIS_IS8_Pos 8 /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS8_Msk (_U_(0x1) << XDMAC_GIS_IS8_Pos) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS8 XDMAC_GIS_IS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS8_Msk instead */ +#define XDMAC_GIS_IS9_Pos 9 /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS9_Msk (_U_(0x1) << XDMAC_GIS_IS9_Pos) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS9 XDMAC_GIS_IS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS9_Msk instead */ +#define XDMAC_GIS_IS10_Pos 10 /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS10_Msk (_U_(0x1) << XDMAC_GIS_IS10_Pos) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS10 XDMAC_GIS_IS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS10_Msk instead */ +#define XDMAC_GIS_IS11_Pos 11 /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS11_Msk (_U_(0x1) << XDMAC_GIS_IS11_Pos) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS11 XDMAC_GIS_IS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS11_Msk instead */ +#define XDMAC_GIS_IS12_Pos 12 /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS12_Msk (_U_(0x1) << XDMAC_GIS_IS12_Pos) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS12 XDMAC_GIS_IS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS12_Msk instead */ +#define XDMAC_GIS_IS13_Pos 13 /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS13_Msk (_U_(0x1) << XDMAC_GIS_IS13_Pos) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS13 XDMAC_GIS_IS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS13_Msk instead */ +#define XDMAC_GIS_IS14_Pos 14 /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS14_Msk (_U_(0x1) << XDMAC_GIS_IS14_Pos) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS14 XDMAC_GIS_IS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS14_Msk instead */ +#define XDMAC_GIS_IS15_Pos 15 /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS15_Msk (_U_(0x1) << XDMAC_GIS_IS15_Pos) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS15 XDMAC_GIS_IS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS15_Msk instead */ +#define XDMAC_GIS_IS16_Pos 16 /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS16_Msk (_U_(0x1) << XDMAC_GIS_IS16_Pos) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS16 XDMAC_GIS_IS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS16_Msk instead */ +#define XDMAC_GIS_IS17_Pos 17 /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS17_Msk (_U_(0x1) << XDMAC_GIS_IS17_Pos) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS17 XDMAC_GIS_IS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS17_Msk instead */ +#define XDMAC_GIS_IS18_Pos 18 /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS18_Msk (_U_(0x1) << XDMAC_GIS_IS18_Pos) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS18 XDMAC_GIS_IS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS18_Msk instead */ +#define XDMAC_GIS_IS19_Pos 19 /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS19_Msk (_U_(0x1) << XDMAC_GIS_IS19_Pos) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS19 XDMAC_GIS_IS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS19_Msk instead */ +#define XDMAC_GIS_IS20_Pos 20 /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS20_Msk (_U_(0x1) << XDMAC_GIS_IS20_Pos) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS20 XDMAC_GIS_IS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS20_Msk instead */ +#define XDMAC_GIS_IS21_Pos 21 /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS21_Msk (_U_(0x1) << XDMAC_GIS_IS21_Pos) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS21 XDMAC_GIS_IS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS21_Msk instead */ +#define XDMAC_GIS_IS22_Pos 22 /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS22_Msk (_U_(0x1) << XDMAC_GIS_IS22_Pos) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS22 XDMAC_GIS_IS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS22_Msk instead */ +#define XDMAC_GIS_IS23_Pos 23 /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS23_Msk (_U_(0x1) << XDMAC_GIS_IS23_Pos) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS23 XDMAC_GIS_IS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GIS_IS23_Msk instead */ +#define XDMAC_GIS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GIS) Register MASK (Use XDMAC_GIS_Msk instead) */ +#define XDMAC_GIS_Msk _U_(0xFFFFFF) /**< (XDMAC_GIS) Register Mask */ + +#define XDMAC_GIS_IS_Pos 0 /**< (XDMAC_GIS Position) XDMAC Channel 23 Interrupt Status Bit */ +#define XDMAC_GIS_IS_Msk (_U_(0xFFFFFF) << XDMAC_GIS_IS_Pos) /**< (XDMAC_GIS Mask) IS */ +#define XDMAC_GIS_IS(value) (XDMAC_GIS_IS_Msk & ((value) << XDMAC_GIS_IS_Pos)) + +/* -------- XDMAC_GE : (XDMAC Offset: 0x1c) (/W 32) Global Channel Enable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t EN0:1; /**< bit: 0 XDMAC Channel 0 Enable Bit */ + uint32_t EN1:1; /**< bit: 1 XDMAC Channel 1 Enable Bit */ + uint32_t EN2:1; /**< bit: 2 XDMAC Channel 2 Enable Bit */ + uint32_t EN3:1; /**< bit: 3 XDMAC Channel 3 Enable Bit */ + uint32_t EN4:1; /**< bit: 4 XDMAC Channel 4 Enable Bit */ + uint32_t EN5:1; /**< bit: 5 XDMAC Channel 5 Enable Bit */ + uint32_t EN6:1; /**< bit: 6 XDMAC Channel 6 Enable Bit */ + uint32_t EN7:1; /**< bit: 7 XDMAC Channel 7 Enable Bit */ + uint32_t EN8:1; /**< bit: 8 XDMAC Channel 8 Enable Bit */ + uint32_t EN9:1; /**< bit: 9 XDMAC Channel 9 Enable Bit */ + uint32_t EN10:1; /**< bit: 10 XDMAC Channel 10 Enable Bit */ + uint32_t EN11:1; /**< bit: 11 XDMAC Channel 11 Enable Bit */ + uint32_t EN12:1; /**< bit: 12 XDMAC Channel 12 Enable Bit */ + uint32_t EN13:1; /**< bit: 13 XDMAC Channel 13 Enable Bit */ + uint32_t EN14:1; /**< bit: 14 XDMAC Channel 14 Enable Bit */ + uint32_t EN15:1; /**< bit: 15 XDMAC Channel 15 Enable Bit */ + uint32_t EN16:1; /**< bit: 16 XDMAC Channel 16 Enable Bit */ + uint32_t EN17:1; /**< bit: 17 XDMAC Channel 17 Enable Bit */ + uint32_t EN18:1; /**< bit: 18 XDMAC Channel 18 Enable Bit */ + uint32_t EN19:1; /**< bit: 19 XDMAC Channel 19 Enable Bit */ + uint32_t EN20:1; /**< bit: 20 XDMAC Channel 20 Enable Bit */ + uint32_t EN21:1; /**< bit: 21 XDMAC Channel 21 Enable Bit */ + uint32_t EN22:1; /**< bit: 22 XDMAC Channel 22 Enable Bit */ + uint32_t EN23:1; /**< bit: 23 XDMAC Channel 23 Enable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t EN:24; /**< bit: 0..23 XDMAC Channel 23 Enable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GE_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GE_OFFSET (0x1C) /**< (XDMAC_GE) Global Channel Enable Register Offset */ + +#define XDMAC_GE_EN0_Pos 0 /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Position */ +#define XDMAC_GE_EN0_Msk (_U_(0x1) << XDMAC_GE_EN0_Pos) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Mask */ +#define XDMAC_GE_EN0 XDMAC_GE_EN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN0_Msk instead */ +#define XDMAC_GE_EN1_Pos 1 /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Position */ +#define XDMAC_GE_EN1_Msk (_U_(0x1) << XDMAC_GE_EN1_Pos) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Mask */ +#define XDMAC_GE_EN1 XDMAC_GE_EN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN1_Msk instead */ +#define XDMAC_GE_EN2_Pos 2 /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Position */ +#define XDMAC_GE_EN2_Msk (_U_(0x1) << XDMAC_GE_EN2_Pos) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Mask */ +#define XDMAC_GE_EN2 XDMAC_GE_EN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN2_Msk instead */ +#define XDMAC_GE_EN3_Pos 3 /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Position */ +#define XDMAC_GE_EN3_Msk (_U_(0x1) << XDMAC_GE_EN3_Pos) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Mask */ +#define XDMAC_GE_EN3 XDMAC_GE_EN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN3_Msk instead */ +#define XDMAC_GE_EN4_Pos 4 /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Position */ +#define XDMAC_GE_EN4_Msk (_U_(0x1) << XDMAC_GE_EN4_Pos) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Mask */ +#define XDMAC_GE_EN4 XDMAC_GE_EN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN4_Msk instead */ +#define XDMAC_GE_EN5_Pos 5 /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Position */ +#define XDMAC_GE_EN5_Msk (_U_(0x1) << XDMAC_GE_EN5_Pos) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Mask */ +#define XDMAC_GE_EN5 XDMAC_GE_EN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN5_Msk instead */ +#define XDMAC_GE_EN6_Pos 6 /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Position */ +#define XDMAC_GE_EN6_Msk (_U_(0x1) << XDMAC_GE_EN6_Pos) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Mask */ +#define XDMAC_GE_EN6 XDMAC_GE_EN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN6_Msk instead */ +#define XDMAC_GE_EN7_Pos 7 /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Position */ +#define XDMAC_GE_EN7_Msk (_U_(0x1) << XDMAC_GE_EN7_Pos) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Mask */ +#define XDMAC_GE_EN7 XDMAC_GE_EN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN7_Msk instead */ +#define XDMAC_GE_EN8_Pos 8 /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Position */ +#define XDMAC_GE_EN8_Msk (_U_(0x1) << XDMAC_GE_EN8_Pos) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Mask */ +#define XDMAC_GE_EN8 XDMAC_GE_EN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN8_Msk instead */ +#define XDMAC_GE_EN9_Pos 9 /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Position */ +#define XDMAC_GE_EN9_Msk (_U_(0x1) << XDMAC_GE_EN9_Pos) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Mask */ +#define XDMAC_GE_EN9 XDMAC_GE_EN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN9_Msk instead */ +#define XDMAC_GE_EN10_Pos 10 /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Position */ +#define XDMAC_GE_EN10_Msk (_U_(0x1) << XDMAC_GE_EN10_Pos) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Mask */ +#define XDMAC_GE_EN10 XDMAC_GE_EN10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN10_Msk instead */ +#define XDMAC_GE_EN11_Pos 11 /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Position */ +#define XDMAC_GE_EN11_Msk (_U_(0x1) << XDMAC_GE_EN11_Pos) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Mask */ +#define XDMAC_GE_EN11 XDMAC_GE_EN11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN11_Msk instead */ +#define XDMAC_GE_EN12_Pos 12 /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Position */ +#define XDMAC_GE_EN12_Msk (_U_(0x1) << XDMAC_GE_EN12_Pos) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Mask */ +#define XDMAC_GE_EN12 XDMAC_GE_EN12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN12_Msk instead */ +#define XDMAC_GE_EN13_Pos 13 /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Position */ +#define XDMAC_GE_EN13_Msk (_U_(0x1) << XDMAC_GE_EN13_Pos) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Mask */ +#define XDMAC_GE_EN13 XDMAC_GE_EN13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN13_Msk instead */ +#define XDMAC_GE_EN14_Pos 14 /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Position */ +#define XDMAC_GE_EN14_Msk (_U_(0x1) << XDMAC_GE_EN14_Pos) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Mask */ +#define XDMAC_GE_EN14 XDMAC_GE_EN14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN14_Msk instead */ +#define XDMAC_GE_EN15_Pos 15 /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Position */ +#define XDMAC_GE_EN15_Msk (_U_(0x1) << XDMAC_GE_EN15_Pos) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Mask */ +#define XDMAC_GE_EN15 XDMAC_GE_EN15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN15_Msk instead */ +#define XDMAC_GE_EN16_Pos 16 /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Position */ +#define XDMAC_GE_EN16_Msk (_U_(0x1) << XDMAC_GE_EN16_Pos) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Mask */ +#define XDMAC_GE_EN16 XDMAC_GE_EN16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN16_Msk instead */ +#define XDMAC_GE_EN17_Pos 17 /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Position */ +#define XDMAC_GE_EN17_Msk (_U_(0x1) << XDMAC_GE_EN17_Pos) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Mask */ +#define XDMAC_GE_EN17 XDMAC_GE_EN17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN17_Msk instead */ +#define XDMAC_GE_EN18_Pos 18 /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Position */ +#define XDMAC_GE_EN18_Msk (_U_(0x1) << XDMAC_GE_EN18_Pos) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Mask */ +#define XDMAC_GE_EN18 XDMAC_GE_EN18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN18_Msk instead */ +#define XDMAC_GE_EN19_Pos 19 /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Position */ +#define XDMAC_GE_EN19_Msk (_U_(0x1) << XDMAC_GE_EN19_Pos) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Mask */ +#define XDMAC_GE_EN19 XDMAC_GE_EN19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN19_Msk instead */ +#define XDMAC_GE_EN20_Pos 20 /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Position */ +#define XDMAC_GE_EN20_Msk (_U_(0x1) << XDMAC_GE_EN20_Pos) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Mask */ +#define XDMAC_GE_EN20 XDMAC_GE_EN20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN20_Msk instead */ +#define XDMAC_GE_EN21_Pos 21 /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Position */ +#define XDMAC_GE_EN21_Msk (_U_(0x1) << XDMAC_GE_EN21_Pos) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Mask */ +#define XDMAC_GE_EN21 XDMAC_GE_EN21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN21_Msk instead */ +#define XDMAC_GE_EN22_Pos 22 /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Position */ +#define XDMAC_GE_EN22_Msk (_U_(0x1) << XDMAC_GE_EN22_Pos) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Mask */ +#define XDMAC_GE_EN22 XDMAC_GE_EN22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN22_Msk instead */ +#define XDMAC_GE_EN23_Pos 23 /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Position */ +#define XDMAC_GE_EN23_Msk (_U_(0x1) << XDMAC_GE_EN23_Pos) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Mask */ +#define XDMAC_GE_EN23 XDMAC_GE_EN23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GE_EN23_Msk instead */ +#define XDMAC_GE_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GE) Register MASK (Use XDMAC_GE_Msk instead) */ +#define XDMAC_GE_Msk _U_(0xFFFFFF) /**< (XDMAC_GE) Register Mask */ + +#define XDMAC_GE_EN_Pos 0 /**< (XDMAC_GE Position) XDMAC Channel 23 Enable Bit */ +#define XDMAC_GE_EN_Msk (_U_(0xFFFFFF) << XDMAC_GE_EN_Pos) /**< (XDMAC_GE Mask) EN */ +#define XDMAC_GE_EN(value) (XDMAC_GE_EN_Msk & ((value) << XDMAC_GE_EN_Pos)) + +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) (/W 32) Global Channel Disable Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t DI0:1; /**< bit: 0 XDMAC Channel 0 Disable Bit */ + uint32_t DI1:1; /**< bit: 1 XDMAC Channel 1 Disable Bit */ + uint32_t DI2:1; /**< bit: 2 XDMAC Channel 2 Disable Bit */ + uint32_t DI3:1; /**< bit: 3 XDMAC Channel 3 Disable Bit */ + uint32_t DI4:1; /**< bit: 4 XDMAC Channel 4 Disable Bit */ + uint32_t DI5:1; /**< bit: 5 XDMAC Channel 5 Disable Bit */ + uint32_t DI6:1; /**< bit: 6 XDMAC Channel 6 Disable Bit */ + uint32_t DI7:1; /**< bit: 7 XDMAC Channel 7 Disable Bit */ + uint32_t DI8:1; /**< bit: 8 XDMAC Channel 8 Disable Bit */ + uint32_t DI9:1; /**< bit: 9 XDMAC Channel 9 Disable Bit */ + uint32_t DI10:1; /**< bit: 10 XDMAC Channel 10 Disable Bit */ + uint32_t DI11:1; /**< bit: 11 XDMAC Channel 11 Disable Bit */ + uint32_t DI12:1; /**< bit: 12 XDMAC Channel 12 Disable Bit */ + uint32_t DI13:1; /**< bit: 13 XDMAC Channel 13 Disable Bit */ + uint32_t DI14:1; /**< bit: 14 XDMAC Channel 14 Disable Bit */ + uint32_t DI15:1; /**< bit: 15 XDMAC Channel 15 Disable Bit */ + uint32_t DI16:1; /**< bit: 16 XDMAC Channel 16 Disable Bit */ + uint32_t DI17:1; /**< bit: 17 XDMAC Channel 17 Disable Bit */ + uint32_t DI18:1; /**< bit: 18 XDMAC Channel 18 Disable Bit */ + uint32_t DI19:1; /**< bit: 19 XDMAC Channel 19 Disable Bit */ + uint32_t DI20:1; /**< bit: 20 XDMAC Channel 20 Disable Bit */ + uint32_t DI21:1; /**< bit: 21 XDMAC Channel 21 Disable Bit */ + uint32_t DI22:1; /**< bit: 22 XDMAC Channel 22 Disable Bit */ + uint32_t DI23:1; /**< bit: 23 XDMAC Channel 23 Disable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t DI:24; /**< bit: 0..23 XDMAC Channel 23 Disable Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GD_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GD_OFFSET (0x20) /**< (XDMAC_GD) Global Channel Disable Register Offset */ + +#define XDMAC_GD_DI0_Pos 0 /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Position */ +#define XDMAC_GD_DI0_Msk (_U_(0x1) << XDMAC_GD_DI0_Pos) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Mask */ +#define XDMAC_GD_DI0 XDMAC_GD_DI0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI0_Msk instead */ +#define XDMAC_GD_DI1_Pos 1 /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Position */ +#define XDMAC_GD_DI1_Msk (_U_(0x1) << XDMAC_GD_DI1_Pos) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Mask */ +#define XDMAC_GD_DI1 XDMAC_GD_DI1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI1_Msk instead */ +#define XDMAC_GD_DI2_Pos 2 /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Position */ +#define XDMAC_GD_DI2_Msk (_U_(0x1) << XDMAC_GD_DI2_Pos) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Mask */ +#define XDMAC_GD_DI2 XDMAC_GD_DI2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI2_Msk instead */ +#define XDMAC_GD_DI3_Pos 3 /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Position */ +#define XDMAC_GD_DI3_Msk (_U_(0x1) << XDMAC_GD_DI3_Pos) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Mask */ +#define XDMAC_GD_DI3 XDMAC_GD_DI3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI3_Msk instead */ +#define XDMAC_GD_DI4_Pos 4 /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Position */ +#define XDMAC_GD_DI4_Msk (_U_(0x1) << XDMAC_GD_DI4_Pos) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Mask */ +#define XDMAC_GD_DI4 XDMAC_GD_DI4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI4_Msk instead */ +#define XDMAC_GD_DI5_Pos 5 /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Position */ +#define XDMAC_GD_DI5_Msk (_U_(0x1) << XDMAC_GD_DI5_Pos) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Mask */ +#define XDMAC_GD_DI5 XDMAC_GD_DI5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI5_Msk instead */ +#define XDMAC_GD_DI6_Pos 6 /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Position */ +#define XDMAC_GD_DI6_Msk (_U_(0x1) << XDMAC_GD_DI6_Pos) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Mask */ +#define XDMAC_GD_DI6 XDMAC_GD_DI6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI6_Msk instead */ +#define XDMAC_GD_DI7_Pos 7 /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Position */ +#define XDMAC_GD_DI7_Msk (_U_(0x1) << XDMAC_GD_DI7_Pos) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Mask */ +#define XDMAC_GD_DI7 XDMAC_GD_DI7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI7_Msk instead */ +#define XDMAC_GD_DI8_Pos 8 /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Position */ +#define XDMAC_GD_DI8_Msk (_U_(0x1) << XDMAC_GD_DI8_Pos) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Mask */ +#define XDMAC_GD_DI8 XDMAC_GD_DI8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI8_Msk instead */ +#define XDMAC_GD_DI9_Pos 9 /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Position */ +#define XDMAC_GD_DI9_Msk (_U_(0x1) << XDMAC_GD_DI9_Pos) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Mask */ +#define XDMAC_GD_DI9 XDMAC_GD_DI9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI9_Msk instead */ +#define XDMAC_GD_DI10_Pos 10 /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Position */ +#define XDMAC_GD_DI10_Msk (_U_(0x1) << XDMAC_GD_DI10_Pos) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Mask */ +#define XDMAC_GD_DI10 XDMAC_GD_DI10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI10_Msk instead */ +#define XDMAC_GD_DI11_Pos 11 /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Position */ +#define XDMAC_GD_DI11_Msk (_U_(0x1) << XDMAC_GD_DI11_Pos) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Mask */ +#define XDMAC_GD_DI11 XDMAC_GD_DI11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI11_Msk instead */ +#define XDMAC_GD_DI12_Pos 12 /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Position */ +#define XDMAC_GD_DI12_Msk (_U_(0x1) << XDMAC_GD_DI12_Pos) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Mask */ +#define XDMAC_GD_DI12 XDMAC_GD_DI12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI12_Msk instead */ +#define XDMAC_GD_DI13_Pos 13 /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Position */ +#define XDMAC_GD_DI13_Msk (_U_(0x1) << XDMAC_GD_DI13_Pos) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Mask */ +#define XDMAC_GD_DI13 XDMAC_GD_DI13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI13_Msk instead */ +#define XDMAC_GD_DI14_Pos 14 /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Position */ +#define XDMAC_GD_DI14_Msk (_U_(0x1) << XDMAC_GD_DI14_Pos) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Mask */ +#define XDMAC_GD_DI14 XDMAC_GD_DI14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI14_Msk instead */ +#define XDMAC_GD_DI15_Pos 15 /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Position */ +#define XDMAC_GD_DI15_Msk (_U_(0x1) << XDMAC_GD_DI15_Pos) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Mask */ +#define XDMAC_GD_DI15 XDMAC_GD_DI15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI15_Msk instead */ +#define XDMAC_GD_DI16_Pos 16 /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Position */ +#define XDMAC_GD_DI16_Msk (_U_(0x1) << XDMAC_GD_DI16_Pos) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Mask */ +#define XDMAC_GD_DI16 XDMAC_GD_DI16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI16_Msk instead */ +#define XDMAC_GD_DI17_Pos 17 /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Position */ +#define XDMAC_GD_DI17_Msk (_U_(0x1) << XDMAC_GD_DI17_Pos) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Mask */ +#define XDMAC_GD_DI17 XDMAC_GD_DI17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI17_Msk instead */ +#define XDMAC_GD_DI18_Pos 18 /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Position */ +#define XDMAC_GD_DI18_Msk (_U_(0x1) << XDMAC_GD_DI18_Pos) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Mask */ +#define XDMAC_GD_DI18 XDMAC_GD_DI18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI18_Msk instead */ +#define XDMAC_GD_DI19_Pos 19 /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Position */ +#define XDMAC_GD_DI19_Msk (_U_(0x1) << XDMAC_GD_DI19_Pos) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Mask */ +#define XDMAC_GD_DI19 XDMAC_GD_DI19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI19_Msk instead */ +#define XDMAC_GD_DI20_Pos 20 /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Position */ +#define XDMAC_GD_DI20_Msk (_U_(0x1) << XDMAC_GD_DI20_Pos) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Mask */ +#define XDMAC_GD_DI20 XDMAC_GD_DI20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI20_Msk instead */ +#define XDMAC_GD_DI21_Pos 21 /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Position */ +#define XDMAC_GD_DI21_Msk (_U_(0x1) << XDMAC_GD_DI21_Pos) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Mask */ +#define XDMAC_GD_DI21 XDMAC_GD_DI21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI21_Msk instead */ +#define XDMAC_GD_DI22_Pos 22 /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Position */ +#define XDMAC_GD_DI22_Msk (_U_(0x1) << XDMAC_GD_DI22_Pos) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Mask */ +#define XDMAC_GD_DI22 XDMAC_GD_DI22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI22_Msk instead */ +#define XDMAC_GD_DI23_Pos 23 /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Position */ +#define XDMAC_GD_DI23_Msk (_U_(0x1) << XDMAC_GD_DI23_Pos) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Mask */ +#define XDMAC_GD_DI23 XDMAC_GD_DI23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GD_DI23_Msk instead */ +#define XDMAC_GD_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GD) Register MASK (Use XDMAC_GD_Msk instead) */ +#define XDMAC_GD_Msk _U_(0xFFFFFF) /**< (XDMAC_GD) Register Mask */ + +#define XDMAC_GD_DI_Pos 0 /**< (XDMAC_GD Position) XDMAC Channel 23 Disable Bit */ +#define XDMAC_GD_DI_Msk (_U_(0xFFFFFF) << XDMAC_GD_DI_Pos) /**< (XDMAC_GD Mask) DI */ +#define XDMAC_GD_DI(value) (XDMAC_GD_DI_Msk & ((value) << XDMAC_GD_DI_Pos)) + +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) (R/ 32) Global Channel Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t ST0:1; /**< bit: 0 XDMAC Channel 0 Status Bit */ + uint32_t ST1:1; /**< bit: 1 XDMAC Channel 1 Status Bit */ + uint32_t ST2:1; /**< bit: 2 XDMAC Channel 2 Status Bit */ + uint32_t ST3:1; /**< bit: 3 XDMAC Channel 3 Status Bit */ + uint32_t ST4:1; /**< bit: 4 XDMAC Channel 4 Status Bit */ + uint32_t ST5:1; /**< bit: 5 XDMAC Channel 5 Status Bit */ + uint32_t ST6:1; /**< bit: 6 XDMAC Channel 6 Status Bit */ + uint32_t ST7:1; /**< bit: 7 XDMAC Channel 7 Status Bit */ + uint32_t ST8:1; /**< bit: 8 XDMAC Channel 8 Status Bit */ + uint32_t ST9:1; /**< bit: 9 XDMAC Channel 9 Status Bit */ + uint32_t ST10:1; /**< bit: 10 XDMAC Channel 10 Status Bit */ + uint32_t ST11:1; /**< bit: 11 XDMAC Channel 11 Status Bit */ + uint32_t ST12:1; /**< bit: 12 XDMAC Channel 12 Status Bit */ + uint32_t ST13:1; /**< bit: 13 XDMAC Channel 13 Status Bit */ + uint32_t ST14:1; /**< bit: 14 XDMAC Channel 14 Status Bit */ + uint32_t ST15:1; /**< bit: 15 XDMAC Channel 15 Status Bit */ + uint32_t ST16:1; /**< bit: 16 XDMAC Channel 16 Status Bit */ + uint32_t ST17:1; /**< bit: 17 XDMAC Channel 17 Status Bit */ + uint32_t ST18:1; /**< bit: 18 XDMAC Channel 18 Status Bit */ + uint32_t ST19:1; /**< bit: 19 XDMAC Channel 19 Status Bit */ + uint32_t ST20:1; /**< bit: 20 XDMAC Channel 20 Status Bit */ + uint32_t ST21:1; /**< bit: 21 XDMAC Channel 21 Status Bit */ + uint32_t ST22:1; /**< bit: 22 XDMAC Channel 22 Status Bit */ + uint32_t ST23:1; /**< bit: 23 XDMAC Channel 23 Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t ST:24; /**< bit: 0..23 XDMAC Channel 23 Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GS_OFFSET (0x24) /**< (XDMAC_GS) Global Channel Status Register Offset */ + +#define XDMAC_GS_ST0_Pos 0 /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Position */ +#define XDMAC_GS_ST0_Msk (_U_(0x1) << XDMAC_GS_ST0_Pos) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Mask */ +#define XDMAC_GS_ST0 XDMAC_GS_ST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST0_Msk instead */ +#define XDMAC_GS_ST1_Pos 1 /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Position */ +#define XDMAC_GS_ST1_Msk (_U_(0x1) << XDMAC_GS_ST1_Pos) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Mask */ +#define XDMAC_GS_ST1 XDMAC_GS_ST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST1_Msk instead */ +#define XDMAC_GS_ST2_Pos 2 /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Position */ +#define XDMAC_GS_ST2_Msk (_U_(0x1) << XDMAC_GS_ST2_Pos) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Mask */ +#define XDMAC_GS_ST2 XDMAC_GS_ST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST2_Msk instead */ +#define XDMAC_GS_ST3_Pos 3 /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Position */ +#define XDMAC_GS_ST3_Msk (_U_(0x1) << XDMAC_GS_ST3_Pos) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Mask */ +#define XDMAC_GS_ST3 XDMAC_GS_ST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST3_Msk instead */ +#define XDMAC_GS_ST4_Pos 4 /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Position */ +#define XDMAC_GS_ST4_Msk (_U_(0x1) << XDMAC_GS_ST4_Pos) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Mask */ +#define XDMAC_GS_ST4 XDMAC_GS_ST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST4_Msk instead */ +#define XDMAC_GS_ST5_Pos 5 /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Position */ +#define XDMAC_GS_ST5_Msk (_U_(0x1) << XDMAC_GS_ST5_Pos) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Mask */ +#define XDMAC_GS_ST5 XDMAC_GS_ST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST5_Msk instead */ +#define XDMAC_GS_ST6_Pos 6 /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Position */ +#define XDMAC_GS_ST6_Msk (_U_(0x1) << XDMAC_GS_ST6_Pos) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Mask */ +#define XDMAC_GS_ST6 XDMAC_GS_ST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST6_Msk instead */ +#define XDMAC_GS_ST7_Pos 7 /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Position */ +#define XDMAC_GS_ST7_Msk (_U_(0x1) << XDMAC_GS_ST7_Pos) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Mask */ +#define XDMAC_GS_ST7 XDMAC_GS_ST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST7_Msk instead */ +#define XDMAC_GS_ST8_Pos 8 /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Position */ +#define XDMAC_GS_ST8_Msk (_U_(0x1) << XDMAC_GS_ST8_Pos) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Mask */ +#define XDMAC_GS_ST8 XDMAC_GS_ST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST8_Msk instead */ +#define XDMAC_GS_ST9_Pos 9 /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Position */ +#define XDMAC_GS_ST9_Msk (_U_(0x1) << XDMAC_GS_ST9_Pos) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Mask */ +#define XDMAC_GS_ST9 XDMAC_GS_ST9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST9_Msk instead */ +#define XDMAC_GS_ST10_Pos 10 /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Position */ +#define XDMAC_GS_ST10_Msk (_U_(0x1) << XDMAC_GS_ST10_Pos) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Mask */ +#define XDMAC_GS_ST10 XDMAC_GS_ST10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST10_Msk instead */ +#define XDMAC_GS_ST11_Pos 11 /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Position */ +#define XDMAC_GS_ST11_Msk (_U_(0x1) << XDMAC_GS_ST11_Pos) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Mask */ +#define XDMAC_GS_ST11 XDMAC_GS_ST11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST11_Msk instead */ +#define XDMAC_GS_ST12_Pos 12 /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Position */ +#define XDMAC_GS_ST12_Msk (_U_(0x1) << XDMAC_GS_ST12_Pos) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Mask */ +#define XDMAC_GS_ST12 XDMAC_GS_ST12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST12_Msk instead */ +#define XDMAC_GS_ST13_Pos 13 /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Position */ +#define XDMAC_GS_ST13_Msk (_U_(0x1) << XDMAC_GS_ST13_Pos) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Mask */ +#define XDMAC_GS_ST13 XDMAC_GS_ST13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST13_Msk instead */ +#define XDMAC_GS_ST14_Pos 14 /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Position */ +#define XDMAC_GS_ST14_Msk (_U_(0x1) << XDMAC_GS_ST14_Pos) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Mask */ +#define XDMAC_GS_ST14 XDMAC_GS_ST14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST14_Msk instead */ +#define XDMAC_GS_ST15_Pos 15 /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Position */ +#define XDMAC_GS_ST15_Msk (_U_(0x1) << XDMAC_GS_ST15_Pos) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Mask */ +#define XDMAC_GS_ST15 XDMAC_GS_ST15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST15_Msk instead */ +#define XDMAC_GS_ST16_Pos 16 /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Position */ +#define XDMAC_GS_ST16_Msk (_U_(0x1) << XDMAC_GS_ST16_Pos) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Mask */ +#define XDMAC_GS_ST16 XDMAC_GS_ST16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST16_Msk instead */ +#define XDMAC_GS_ST17_Pos 17 /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Position */ +#define XDMAC_GS_ST17_Msk (_U_(0x1) << XDMAC_GS_ST17_Pos) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Mask */ +#define XDMAC_GS_ST17 XDMAC_GS_ST17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST17_Msk instead */ +#define XDMAC_GS_ST18_Pos 18 /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Position */ +#define XDMAC_GS_ST18_Msk (_U_(0x1) << XDMAC_GS_ST18_Pos) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Mask */ +#define XDMAC_GS_ST18 XDMAC_GS_ST18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST18_Msk instead */ +#define XDMAC_GS_ST19_Pos 19 /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Position */ +#define XDMAC_GS_ST19_Msk (_U_(0x1) << XDMAC_GS_ST19_Pos) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Mask */ +#define XDMAC_GS_ST19 XDMAC_GS_ST19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST19_Msk instead */ +#define XDMAC_GS_ST20_Pos 20 /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Position */ +#define XDMAC_GS_ST20_Msk (_U_(0x1) << XDMAC_GS_ST20_Pos) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Mask */ +#define XDMAC_GS_ST20 XDMAC_GS_ST20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST20_Msk instead */ +#define XDMAC_GS_ST21_Pos 21 /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Position */ +#define XDMAC_GS_ST21_Msk (_U_(0x1) << XDMAC_GS_ST21_Pos) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Mask */ +#define XDMAC_GS_ST21 XDMAC_GS_ST21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST21_Msk instead */ +#define XDMAC_GS_ST22_Pos 22 /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Position */ +#define XDMAC_GS_ST22_Msk (_U_(0x1) << XDMAC_GS_ST22_Pos) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Mask */ +#define XDMAC_GS_ST22 XDMAC_GS_ST22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST22_Msk instead */ +#define XDMAC_GS_ST23_Pos 23 /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Position */ +#define XDMAC_GS_ST23_Msk (_U_(0x1) << XDMAC_GS_ST23_Pos) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Mask */ +#define XDMAC_GS_ST23 XDMAC_GS_ST23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GS_ST23_Msk instead */ +#define XDMAC_GS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GS) Register MASK (Use XDMAC_GS_Msk instead) */ +#define XDMAC_GS_Msk _U_(0xFFFFFF) /**< (XDMAC_GS) Register Mask */ + +#define XDMAC_GS_ST_Pos 0 /**< (XDMAC_GS Position) XDMAC Channel 23 Status Bit */ +#define XDMAC_GS_ST_Msk (_U_(0xFFFFFF) << XDMAC_GS_ST_Pos) /**< (XDMAC_GS Mask) ST */ +#define XDMAC_GS_ST(value) (XDMAC_GS_ST_Msk & ((value) << XDMAC_GS_ST_Pos)) + +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) (R/W 32) Global Channel Read Suspend Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RS0:1; /**< bit: 0 XDMAC Channel 0 Read Suspend Bit */ + uint32_t RS1:1; /**< bit: 1 XDMAC Channel 1 Read Suspend Bit */ + uint32_t RS2:1; /**< bit: 2 XDMAC Channel 2 Read Suspend Bit */ + uint32_t RS3:1; /**< bit: 3 XDMAC Channel 3 Read Suspend Bit */ + uint32_t RS4:1; /**< bit: 4 XDMAC Channel 4 Read Suspend Bit */ + uint32_t RS5:1; /**< bit: 5 XDMAC Channel 5 Read Suspend Bit */ + uint32_t RS6:1; /**< bit: 6 XDMAC Channel 6 Read Suspend Bit */ + uint32_t RS7:1; /**< bit: 7 XDMAC Channel 7 Read Suspend Bit */ + uint32_t RS8:1; /**< bit: 8 XDMAC Channel 8 Read Suspend Bit */ + uint32_t RS9:1; /**< bit: 9 XDMAC Channel 9 Read Suspend Bit */ + uint32_t RS10:1; /**< bit: 10 XDMAC Channel 10 Read Suspend Bit */ + uint32_t RS11:1; /**< bit: 11 XDMAC Channel 11 Read Suspend Bit */ + uint32_t RS12:1; /**< bit: 12 XDMAC Channel 12 Read Suspend Bit */ + uint32_t RS13:1; /**< bit: 13 XDMAC Channel 13 Read Suspend Bit */ + uint32_t RS14:1; /**< bit: 14 XDMAC Channel 14 Read Suspend Bit */ + uint32_t RS15:1; /**< bit: 15 XDMAC Channel 15 Read Suspend Bit */ + uint32_t RS16:1; /**< bit: 16 XDMAC Channel 16 Read Suspend Bit */ + uint32_t RS17:1; /**< bit: 17 XDMAC Channel 17 Read Suspend Bit */ + uint32_t RS18:1; /**< bit: 18 XDMAC Channel 18 Read Suspend Bit */ + uint32_t RS19:1; /**< bit: 19 XDMAC Channel 19 Read Suspend Bit */ + uint32_t RS20:1; /**< bit: 20 XDMAC Channel 20 Read Suspend Bit */ + uint32_t RS21:1; /**< bit: 21 XDMAC Channel 21 Read Suspend Bit */ + uint32_t RS22:1; /**< bit: 22 XDMAC Channel 22 Read Suspend Bit */ + uint32_t RS23:1; /**< bit: 23 XDMAC Channel 23 Read Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t RS:24; /**< bit: 0..23 XDMAC Channel 23 Read Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GRS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GRS_OFFSET (0x28) /**< (XDMAC_GRS) Global Channel Read Suspend Register Offset */ + +#define XDMAC_GRS_RS0_Pos 0 /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Position */ +#define XDMAC_GRS_RS0_Msk (_U_(0x1) << XDMAC_GRS_RS0_Pos) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS0 XDMAC_GRS_RS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS0_Msk instead */ +#define XDMAC_GRS_RS1_Pos 1 /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Position */ +#define XDMAC_GRS_RS1_Msk (_U_(0x1) << XDMAC_GRS_RS1_Pos) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS1 XDMAC_GRS_RS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS1_Msk instead */ +#define XDMAC_GRS_RS2_Pos 2 /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Position */ +#define XDMAC_GRS_RS2_Msk (_U_(0x1) << XDMAC_GRS_RS2_Pos) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS2 XDMAC_GRS_RS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS2_Msk instead */ +#define XDMAC_GRS_RS3_Pos 3 /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Position */ +#define XDMAC_GRS_RS3_Msk (_U_(0x1) << XDMAC_GRS_RS3_Pos) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS3 XDMAC_GRS_RS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS3_Msk instead */ +#define XDMAC_GRS_RS4_Pos 4 /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Position */ +#define XDMAC_GRS_RS4_Msk (_U_(0x1) << XDMAC_GRS_RS4_Pos) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS4 XDMAC_GRS_RS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS4_Msk instead */ +#define XDMAC_GRS_RS5_Pos 5 /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Position */ +#define XDMAC_GRS_RS5_Msk (_U_(0x1) << XDMAC_GRS_RS5_Pos) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS5 XDMAC_GRS_RS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS5_Msk instead */ +#define XDMAC_GRS_RS6_Pos 6 /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Position */ +#define XDMAC_GRS_RS6_Msk (_U_(0x1) << XDMAC_GRS_RS6_Pos) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS6 XDMAC_GRS_RS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS6_Msk instead */ +#define XDMAC_GRS_RS7_Pos 7 /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Position */ +#define XDMAC_GRS_RS7_Msk (_U_(0x1) << XDMAC_GRS_RS7_Pos) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS7 XDMAC_GRS_RS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS7_Msk instead */ +#define XDMAC_GRS_RS8_Pos 8 /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Position */ +#define XDMAC_GRS_RS8_Msk (_U_(0x1) << XDMAC_GRS_RS8_Pos) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS8 XDMAC_GRS_RS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS8_Msk instead */ +#define XDMAC_GRS_RS9_Pos 9 /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Position */ +#define XDMAC_GRS_RS9_Msk (_U_(0x1) << XDMAC_GRS_RS9_Pos) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS9 XDMAC_GRS_RS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS9_Msk instead */ +#define XDMAC_GRS_RS10_Pos 10 /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Position */ +#define XDMAC_GRS_RS10_Msk (_U_(0x1) << XDMAC_GRS_RS10_Pos) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS10 XDMAC_GRS_RS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS10_Msk instead */ +#define XDMAC_GRS_RS11_Pos 11 /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Position */ +#define XDMAC_GRS_RS11_Msk (_U_(0x1) << XDMAC_GRS_RS11_Pos) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS11 XDMAC_GRS_RS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS11_Msk instead */ +#define XDMAC_GRS_RS12_Pos 12 /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Position */ +#define XDMAC_GRS_RS12_Msk (_U_(0x1) << XDMAC_GRS_RS12_Pos) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS12 XDMAC_GRS_RS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS12_Msk instead */ +#define XDMAC_GRS_RS13_Pos 13 /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Position */ +#define XDMAC_GRS_RS13_Msk (_U_(0x1) << XDMAC_GRS_RS13_Pos) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS13 XDMAC_GRS_RS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS13_Msk instead */ +#define XDMAC_GRS_RS14_Pos 14 /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Position */ +#define XDMAC_GRS_RS14_Msk (_U_(0x1) << XDMAC_GRS_RS14_Pos) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS14 XDMAC_GRS_RS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS14_Msk instead */ +#define XDMAC_GRS_RS15_Pos 15 /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Position */ +#define XDMAC_GRS_RS15_Msk (_U_(0x1) << XDMAC_GRS_RS15_Pos) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS15 XDMAC_GRS_RS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS15_Msk instead */ +#define XDMAC_GRS_RS16_Pos 16 /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Position */ +#define XDMAC_GRS_RS16_Msk (_U_(0x1) << XDMAC_GRS_RS16_Pos) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS16 XDMAC_GRS_RS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS16_Msk instead */ +#define XDMAC_GRS_RS17_Pos 17 /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Position */ +#define XDMAC_GRS_RS17_Msk (_U_(0x1) << XDMAC_GRS_RS17_Pos) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS17 XDMAC_GRS_RS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS17_Msk instead */ +#define XDMAC_GRS_RS18_Pos 18 /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Position */ +#define XDMAC_GRS_RS18_Msk (_U_(0x1) << XDMAC_GRS_RS18_Pos) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS18 XDMAC_GRS_RS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS18_Msk instead */ +#define XDMAC_GRS_RS19_Pos 19 /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Position */ +#define XDMAC_GRS_RS19_Msk (_U_(0x1) << XDMAC_GRS_RS19_Pos) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS19 XDMAC_GRS_RS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS19_Msk instead */ +#define XDMAC_GRS_RS20_Pos 20 /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Position */ +#define XDMAC_GRS_RS20_Msk (_U_(0x1) << XDMAC_GRS_RS20_Pos) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS20 XDMAC_GRS_RS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS20_Msk instead */ +#define XDMAC_GRS_RS21_Pos 21 /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Position */ +#define XDMAC_GRS_RS21_Msk (_U_(0x1) << XDMAC_GRS_RS21_Pos) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS21 XDMAC_GRS_RS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS21_Msk instead */ +#define XDMAC_GRS_RS22_Pos 22 /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Position */ +#define XDMAC_GRS_RS22_Msk (_U_(0x1) << XDMAC_GRS_RS22_Pos) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS22 XDMAC_GRS_RS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS22_Msk instead */ +#define XDMAC_GRS_RS23_Pos 23 /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Position */ +#define XDMAC_GRS_RS23_Msk (_U_(0x1) << XDMAC_GRS_RS23_Pos) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS23 XDMAC_GRS_RS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRS_RS23_Msk instead */ +#define XDMAC_GRS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRS) Register MASK (Use XDMAC_GRS_Msk instead) */ +#define XDMAC_GRS_Msk _U_(0xFFFFFF) /**< (XDMAC_GRS) Register Mask */ + +#define XDMAC_GRS_RS_Pos 0 /**< (XDMAC_GRS Position) XDMAC Channel 23 Read Suspend Bit */ +#define XDMAC_GRS_RS_Msk (_U_(0xFFFFFF) << XDMAC_GRS_RS_Pos) /**< (XDMAC_GRS Mask) RS */ +#define XDMAC_GRS_RS(value) (XDMAC_GRS_RS_Msk & ((value) << XDMAC_GRS_RS_Pos)) + +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2c) (R/W 32) Global Channel Write Suspend Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t WS0:1; /**< bit: 0 XDMAC Channel 0 Write Suspend Bit */ + uint32_t WS1:1; /**< bit: 1 XDMAC Channel 1 Write Suspend Bit */ + uint32_t WS2:1; /**< bit: 2 XDMAC Channel 2 Write Suspend Bit */ + uint32_t WS3:1; /**< bit: 3 XDMAC Channel 3 Write Suspend Bit */ + uint32_t WS4:1; /**< bit: 4 XDMAC Channel 4 Write Suspend Bit */ + uint32_t WS5:1; /**< bit: 5 XDMAC Channel 5 Write Suspend Bit */ + uint32_t WS6:1; /**< bit: 6 XDMAC Channel 6 Write Suspend Bit */ + uint32_t WS7:1; /**< bit: 7 XDMAC Channel 7 Write Suspend Bit */ + uint32_t WS8:1; /**< bit: 8 XDMAC Channel 8 Write Suspend Bit */ + uint32_t WS9:1; /**< bit: 9 XDMAC Channel 9 Write Suspend Bit */ + uint32_t WS10:1; /**< bit: 10 XDMAC Channel 10 Write Suspend Bit */ + uint32_t WS11:1; /**< bit: 11 XDMAC Channel 11 Write Suspend Bit */ + uint32_t WS12:1; /**< bit: 12 XDMAC Channel 12 Write Suspend Bit */ + uint32_t WS13:1; /**< bit: 13 XDMAC Channel 13 Write Suspend Bit */ + uint32_t WS14:1; /**< bit: 14 XDMAC Channel 14 Write Suspend Bit */ + uint32_t WS15:1; /**< bit: 15 XDMAC Channel 15 Write Suspend Bit */ + uint32_t WS16:1; /**< bit: 16 XDMAC Channel 16 Write Suspend Bit */ + uint32_t WS17:1; /**< bit: 17 XDMAC Channel 17 Write Suspend Bit */ + uint32_t WS18:1; /**< bit: 18 XDMAC Channel 18 Write Suspend Bit */ + uint32_t WS19:1; /**< bit: 19 XDMAC Channel 19 Write Suspend Bit */ + uint32_t WS20:1; /**< bit: 20 XDMAC Channel 20 Write Suspend Bit */ + uint32_t WS21:1; /**< bit: 21 XDMAC Channel 21 Write Suspend Bit */ + uint32_t WS22:1; /**< bit: 22 XDMAC Channel 22 Write Suspend Bit */ + uint32_t WS23:1; /**< bit: 23 XDMAC Channel 23 Write Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t WS:24; /**< bit: 0..23 XDMAC Channel 23 Write Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GWS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GWS_OFFSET (0x2C) /**< (XDMAC_GWS) Global Channel Write Suspend Register Offset */ + +#define XDMAC_GWS_WS0_Pos 0 /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Position */ +#define XDMAC_GWS_WS0_Msk (_U_(0x1) << XDMAC_GWS_WS0_Pos) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS0 XDMAC_GWS_WS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS0_Msk instead */ +#define XDMAC_GWS_WS1_Pos 1 /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Position */ +#define XDMAC_GWS_WS1_Msk (_U_(0x1) << XDMAC_GWS_WS1_Pos) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS1 XDMAC_GWS_WS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS1_Msk instead */ +#define XDMAC_GWS_WS2_Pos 2 /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Position */ +#define XDMAC_GWS_WS2_Msk (_U_(0x1) << XDMAC_GWS_WS2_Pos) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS2 XDMAC_GWS_WS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS2_Msk instead */ +#define XDMAC_GWS_WS3_Pos 3 /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Position */ +#define XDMAC_GWS_WS3_Msk (_U_(0x1) << XDMAC_GWS_WS3_Pos) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS3 XDMAC_GWS_WS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS3_Msk instead */ +#define XDMAC_GWS_WS4_Pos 4 /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Position */ +#define XDMAC_GWS_WS4_Msk (_U_(0x1) << XDMAC_GWS_WS4_Pos) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS4 XDMAC_GWS_WS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS4_Msk instead */ +#define XDMAC_GWS_WS5_Pos 5 /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Position */ +#define XDMAC_GWS_WS5_Msk (_U_(0x1) << XDMAC_GWS_WS5_Pos) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS5 XDMAC_GWS_WS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS5_Msk instead */ +#define XDMAC_GWS_WS6_Pos 6 /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Position */ +#define XDMAC_GWS_WS6_Msk (_U_(0x1) << XDMAC_GWS_WS6_Pos) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS6 XDMAC_GWS_WS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS6_Msk instead */ +#define XDMAC_GWS_WS7_Pos 7 /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Position */ +#define XDMAC_GWS_WS7_Msk (_U_(0x1) << XDMAC_GWS_WS7_Pos) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS7 XDMAC_GWS_WS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS7_Msk instead */ +#define XDMAC_GWS_WS8_Pos 8 /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Position */ +#define XDMAC_GWS_WS8_Msk (_U_(0x1) << XDMAC_GWS_WS8_Pos) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS8 XDMAC_GWS_WS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS8_Msk instead */ +#define XDMAC_GWS_WS9_Pos 9 /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Position */ +#define XDMAC_GWS_WS9_Msk (_U_(0x1) << XDMAC_GWS_WS9_Pos) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS9 XDMAC_GWS_WS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS9_Msk instead */ +#define XDMAC_GWS_WS10_Pos 10 /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Position */ +#define XDMAC_GWS_WS10_Msk (_U_(0x1) << XDMAC_GWS_WS10_Pos) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS10 XDMAC_GWS_WS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS10_Msk instead */ +#define XDMAC_GWS_WS11_Pos 11 /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Position */ +#define XDMAC_GWS_WS11_Msk (_U_(0x1) << XDMAC_GWS_WS11_Pos) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS11 XDMAC_GWS_WS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS11_Msk instead */ +#define XDMAC_GWS_WS12_Pos 12 /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Position */ +#define XDMAC_GWS_WS12_Msk (_U_(0x1) << XDMAC_GWS_WS12_Pos) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS12 XDMAC_GWS_WS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS12_Msk instead */ +#define XDMAC_GWS_WS13_Pos 13 /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Position */ +#define XDMAC_GWS_WS13_Msk (_U_(0x1) << XDMAC_GWS_WS13_Pos) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS13 XDMAC_GWS_WS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS13_Msk instead */ +#define XDMAC_GWS_WS14_Pos 14 /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Position */ +#define XDMAC_GWS_WS14_Msk (_U_(0x1) << XDMAC_GWS_WS14_Pos) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS14 XDMAC_GWS_WS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS14_Msk instead */ +#define XDMAC_GWS_WS15_Pos 15 /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Position */ +#define XDMAC_GWS_WS15_Msk (_U_(0x1) << XDMAC_GWS_WS15_Pos) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS15 XDMAC_GWS_WS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS15_Msk instead */ +#define XDMAC_GWS_WS16_Pos 16 /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Position */ +#define XDMAC_GWS_WS16_Msk (_U_(0x1) << XDMAC_GWS_WS16_Pos) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS16 XDMAC_GWS_WS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS16_Msk instead */ +#define XDMAC_GWS_WS17_Pos 17 /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Position */ +#define XDMAC_GWS_WS17_Msk (_U_(0x1) << XDMAC_GWS_WS17_Pos) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS17 XDMAC_GWS_WS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS17_Msk instead */ +#define XDMAC_GWS_WS18_Pos 18 /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Position */ +#define XDMAC_GWS_WS18_Msk (_U_(0x1) << XDMAC_GWS_WS18_Pos) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS18 XDMAC_GWS_WS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS18_Msk instead */ +#define XDMAC_GWS_WS19_Pos 19 /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Position */ +#define XDMAC_GWS_WS19_Msk (_U_(0x1) << XDMAC_GWS_WS19_Pos) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS19 XDMAC_GWS_WS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS19_Msk instead */ +#define XDMAC_GWS_WS20_Pos 20 /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Position */ +#define XDMAC_GWS_WS20_Msk (_U_(0x1) << XDMAC_GWS_WS20_Pos) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS20 XDMAC_GWS_WS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS20_Msk instead */ +#define XDMAC_GWS_WS21_Pos 21 /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Position */ +#define XDMAC_GWS_WS21_Msk (_U_(0x1) << XDMAC_GWS_WS21_Pos) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS21 XDMAC_GWS_WS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS21_Msk instead */ +#define XDMAC_GWS_WS22_Pos 22 /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Position */ +#define XDMAC_GWS_WS22_Msk (_U_(0x1) << XDMAC_GWS_WS22_Pos) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS22 XDMAC_GWS_WS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS22_Msk instead */ +#define XDMAC_GWS_WS23_Pos 23 /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Position */ +#define XDMAC_GWS_WS23_Msk (_U_(0x1) << XDMAC_GWS_WS23_Pos) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS23 XDMAC_GWS_WS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GWS_WS23_Msk instead */ +#define XDMAC_GWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GWS) Register MASK (Use XDMAC_GWS_Msk instead) */ +#define XDMAC_GWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GWS) Register Mask */ + +#define XDMAC_GWS_WS_Pos 0 /**< (XDMAC_GWS Position) XDMAC Channel 23 Write Suspend Bit */ +#define XDMAC_GWS_WS_Msk (_U_(0xFFFFFF) << XDMAC_GWS_WS_Pos) /**< (XDMAC_GWS Mask) WS */ +#define XDMAC_GWS_WS(value) (XDMAC_GWS_WS_Msk & ((value) << XDMAC_GWS_WS_Pos)) + +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) (/W 32) Global Channel Read Write Suspend Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RWS0:1; /**< bit: 0 XDMAC Channel 0 Read Write Suspend Bit */ + uint32_t RWS1:1; /**< bit: 1 XDMAC Channel 1 Read Write Suspend Bit */ + uint32_t RWS2:1; /**< bit: 2 XDMAC Channel 2 Read Write Suspend Bit */ + uint32_t RWS3:1; /**< bit: 3 XDMAC Channel 3 Read Write Suspend Bit */ + uint32_t RWS4:1; /**< bit: 4 XDMAC Channel 4 Read Write Suspend Bit */ + uint32_t RWS5:1; /**< bit: 5 XDMAC Channel 5 Read Write Suspend Bit */ + uint32_t RWS6:1; /**< bit: 6 XDMAC Channel 6 Read Write Suspend Bit */ + uint32_t RWS7:1; /**< bit: 7 XDMAC Channel 7 Read Write Suspend Bit */ + uint32_t RWS8:1; /**< bit: 8 XDMAC Channel 8 Read Write Suspend Bit */ + uint32_t RWS9:1; /**< bit: 9 XDMAC Channel 9 Read Write Suspend Bit */ + uint32_t RWS10:1; /**< bit: 10 XDMAC Channel 10 Read Write Suspend Bit */ + uint32_t RWS11:1; /**< bit: 11 XDMAC Channel 11 Read Write Suspend Bit */ + uint32_t RWS12:1; /**< bit: 12 XDMAC Channel 12 Read Write Suspend Bit */ + uint32_t RWS13:1; /**< bit: 13 XDMAC Channel 13 Read Write Suspend Bit */ + uint32_t RWS14:1; /**< bit: 14 XDMAC Channel 14 Read Write Suspend Bit */ + uint32_t RWS15:1; /**< bit: 15 XDMAC Channel 15 Read Write Suspend Bit */ + uint32_t RWS16:1; /**< bit: 16 XDMAC Channel 16 Read Write Suspend Bit */ + uint32_t RWS17:1; /**< bit: 17 XDMAC Channel 17 Read Write Suspend Bit */ + uint32_t RWS18:1; /**< bit: 18 XDMAC Channel 18 Read Write Suspend Bit */ + uint32_t RWS19:1; /**< bit: 19 XDMAC Channel 19 Read Write Suspend Bit */ + uint32_t RWS20:1; /**< bit: 20 XDMAC Channel 20 Read Write Suspend Bit */ + uint32_t RWS21:1; /**< bit: 21 XDMAC Channel 21 Read Write Suspend Bit */ + uint32_t RWS22:1; /**< bit: 22 XDMAC Channel 22 Read Write Suspend Bit */ + uint32_t RWS23:1; /**< bit: 23 XDMAC Channel 23 Read Write Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t RWS:24; /**< bit: 0..23 XDMAC Channel 23 Read Write Suspend Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GRWS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GRWS_OFFSET (0x30) /**< (XDMAC_GRWS) Global Channel Read Write Suspend Register Offset */ + +#define XDMAC_GRWS_RWS0_Pos 0 /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS0_Msk (_U_(0x1) << XDMAC_GRWS_RWS0_Pos) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS0 XDMAC_GRWS_RWS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS0_Msk instead */ +#define XDMAC_GRWS_RWS1_Pos 1 /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS1_Msk (_U_(0x1) << XDMAC_GRWS_RWS1_Pos) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS1 XDMAC_GRWS_RWS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS1_Msk instead */ +#define XDMAC_GRWS_RWS2_Pos 2 /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS2_Msk (_U_(0x1) << XDMAC_GRWS_RWS2_Pos) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS2 XDMAC_GRWS_RWS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS2_Msk instead */ +#define XDMAC_GRWS_RWS3_Pos 3 /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS3_Msk (_U_(0x1) << XDMAC_GRWS_RWS3_Pos) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS3 XDMAC_GRWS_RWS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS3_Msk instead */ +#define XDMAC_GRWS_RWS4_Pos 4 /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS4_Msk (_U_(0x1) << XDMAC_GRWS_RWS4_Pos) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS4 XDMAC_GRWS_RWS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS4_Msk instead */ +#define XDMAC_GRWS_RWS5_Pos 5 /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS5_Msk (_U_(0x1) << XDMAC_GRWS_RWS5_Pos) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS5 XDMAC_GRWS_RWS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS5_Msk instead */ +#define XDMAC_GRWS_RWS6_Pos 6 /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS6_Msk (_U_(0x1) << XDMAC_GRWS_RWS6_Pos) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS6 XDMAC_GRWS_RWS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS6_Msk instead */ +#define XDMAC_GRWS_RWS7_Pos 7 /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS7_Msk (_U_(0x1) << XDMAC_GRWS_RWS7_Pos) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS7 XDMAC_GRWS_RWS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS7_Msk instead */ +#define XDMAC_GRWS_RWS8_Pos 8 /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS8_Msk (_U_(0x1) << XDMAC_GRWS_RWS8_Pos) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS8 XDMAC_GRWS_RWS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS8_Msk instead */ +#define XDMAC_GRWS_RWS9_Pos 9 /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS9_Msk (_U_(0x1) << XDMAC_GRWS_RWS9_Pos) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS9 XDMAC_GRWS_RWS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS9_Msk instead */ +#define XDMAC_GRWS_RWS10_Pos 10 /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS10_Msk (_U_(0x1) << XDMAC_GRWS_RWS10_Pos) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS10 XDMAC_GRWS_RWS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS10_Msk instead */ +#define XDMAC_GRWS_RWS11_Pos 11 /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS11_Msk (_U_(0x1) << XDMAC_GRWS_RWS11_Pos) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS11 XDMAC_GRWS_RWS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS11_Msk instead */ +#define XDMAC_GRWS_RWS12_Pos 12 /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS12_Msk (_U_(0x1) << XDMAC_GRWS_RWS12_Pos) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS12 XDMAC_GRWS_RWS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS12_Msk instead */ +#define XDMAC_GRWS_RWS13_Pos 13 /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS13_Msk (_U_(0x1) << XDMAC_GRWS_RWS13_Pos) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS13 XDMAC_GRWS_RWS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS13_Msk instead */ +#define XDMAC_GRWS_RWS14_Pos 14 /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS14_Msk (_U_(0x1) << XDMAC_GRWS_RWS14_Pos) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS14 XDMAC_GRWS_RWS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS14_Msk instead */ +#define XDMAC_GRWS_RWS15_Pos 15 /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS15_Msk (_U_(0x1) << XDMAC_GRWS_RWS15_Pos) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS15 XDMAC_GRWS_RWS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS15_Msk instead */ +#define XDMAC_GRWS_RWS16_Pos 16 /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS16_Msk (_U_(0x1) << XDMAC_GRWS_RWS16_Pos) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS16 XDMAC_GRWS_RWS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS16_Msk instead */ +#define XDMAC_GRWS_RWS17_Pos 17 /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS17_Msk (_U_(0x1) << XDMAC_GRWS_RWS17_Pos) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS17 XDMAC_GRWS_RWS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS17_Msk instead */ +#define XDMAC_GRWS_RWS18_Pos 18 /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS18_Msk (_U_(0x1) << XDMAC_GRWS_RWS18_Pos) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS18 XDMAC_GRWS_RWS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS18_Msk instead */ +#define XDMAC_GRWS_RWS19_Pos 19 /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS19_Msk (_U_(0x1) << XDMAC_GRWS_RWS19_Pos) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS19 XDMAC_GRWS_RWS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS19_Msk instead */ +#define XDMAC_GRWS_RWS20_Pos 20 /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS20_Msk (_U_(0x1) << XDMAC_GRWS_RWS20_Pos) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS20 XDMAC_GRWS_RWS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS20_Msk instead */ +#define XDMAC_GRWS_RWS21_Pos 21 /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS21_Msk (_U_(0x1) << XDMAC_GRWS_RWS21_Pos) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS21 XDMAC_GRWS_RWS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS21_Msk instead */ +#define XDMAC_GRWS_RWS22_Pos 22 /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS22_Msk (_U_(0x1) << XDMAC_GRWS_RWS22_Pos) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS22 XDMAC_GRWS_RWS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS22_Msk instead */ +#define XDMAC_GRWS_RWS23_Pos 23 /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS23_Msk (_U_(0x1) << XDMAC_GRWS_RWS23_Pos) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS23 XDMAC_GRWS_RWS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWS_RWS23_Msk instead */ +#define XDMAC_GRWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRWS) Register MASK (Use XDMAC_GRWS_Msk instead) */ +#define XDMAC_GRWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GRWS) Register Mask */ + +#define XDMAC_GRWS_RWS_Pos 0 /**< (XDMAC_GRWS Position) XDMAC Channel 23 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS_Msk (_U_(0xFFFFFF) << XDMAC_GRWS_RWS_Pos) /**< (XDMAC_GRWS Mask) RWS */ +#define XDMAC_GRWS_RWS(value) (XDMAC_GRWS_RWS_Msk & ((value) << XDMAC_GRWS_RWS_Pos)) + +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) (/W 32) Global Channel Read Write Resume Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t RWR0:1; /**< bit: 0 XDMAC Channel 0 Read Write Resume Bit */ + uint32_t RWR1:1; /**< bit: 1 XDMAC Channel 1 Read Write Resume Bit */ + uint32_t RWR2:1; /**< bit: 2 XDMAC Channel 2 Read Write Resume Bit */ + uint32_t RWR3:1; /**< bit: 3 XDMAC Channel 3 Read Write Resume Bit */ + uint32_t RWR4:1; /**< bit: 4 XDMAC Channel 4 Read Write Resume Bit */ + uint32_t RWR5:1; /**< bit: 5 XDMAC Channel 5 Read Write Resume Bit */ + uint32_t RWR6:1; /**< bit: 6 XDMAC Channel 6 Read Write Resume Bit */ + uint32_t RWR7:1; /**< bit: 7 XDMAC Channel 7 Read Write Resume Bit */ + uint32_t RWR8:1; /**< bit: 8 XDMAC Channel 8 Read Write Resume Bit */ + uint32_t RWR9:1; /**< bit: 9 XDMAC Channel 9 Read Write Resume Bit */ + uint32_t RWR10:1; /**< bit: 10 XDMAC Channel 10 Read Write Resume Bit */ + uint32_t RWR11:1; /**< bit: 11 XDMAC Channel 11 Read Write Resume Bit */ + uint32_t RWR12:1; /**< bit: 12 XDMAC Channel 12 Read Write Resume Bit */ + uint32_t RWR13:1; /**< bit: 13 XDMAC Channel 13 Read Write Resume Bit */ + uint32_t RWR14:1; /**< bit: 14 XDMAC Channel 14 Read Write Resume Bit */ + uint32_t RWR15:1; /**< bit: 15 XDMAC Channel 15 Read Write Resume Bit */ + uint32_t RWR16:1; /**< bit: 16 XDMAC Channel 16 Read Write Resume Bit */ + uint32_t RWR17:1; /**< bit: 17 XDMAC Channel 17 Read Write Resume Bit */ + uint32_t RWR18:1; /**< bit: 18 XDMAC Channel 18 Read Write Resume Bit */ + uint32_t RWR19:1; /**< bit: 19 XDMAC Channel 19 Read Write Resume Bit */ + uint32_t RWR20:1; /**< bit: 20 XDMAC Channel 20 Read Write Resume Bit */ + uint32_t RWR21:1; /**< bit: 21 XDMAC Channel 21 Read Write Resume Bit */ + uint32_t RWR22:1; /**< bit: 22 XDMAC Channel 22 Read Write Resume Bit */ + uint32_t RWR23:1; /**< bit: 23 XDMAC Channel 23 Read Write Resume Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t RWR:24; /**< bit: 0..23 XDMAC Channel 23 Read Write Resume Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GRWR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GRWR_OFFSET (0x34) /**< (XDMAC_GRWR) Global Channel Read Write Resume Register Offset */ + +#define XDMAC_GRWR_RWR0_Pos 0 /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR0_Msk (_U_(0x1) << XDMAC_GRWR_RWR0_Pos) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR0 XDMAC_GRWR_RWR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR0_Msk instead */ +#define XDMAC_GRWR_RWR1_Pos 1 /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR1_Msk (_U_(0x1) << XDMAC_GRWR_RWR1_Pos) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR1 XDMAC_GRWR_RWR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR1_Msk instead */ +#define XDMAC_GRWR_RWR2_Pos 2 /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR2_Msk (_U_(0x1) << XDMAC_GRWR_RWR2_Pos) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR2 XDMAC_GRWR_RWR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR2_Msk instead */ +#define XDMAC_GRWR_RWR3_Pos 3 /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR3_Msk (_U_(0x1) << XDMAC_GRWR_RWR3_Pos) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR3 XDMAC_GRWR_RWR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR3_Msk instead */ +#define XDMAC_GRWR_RWR4_Pos 4 /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR4_Msk (_U_(0x1) << XDMAC_GRWR_RWR4_Pos) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR4 XDMAC_GRWR_RWR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR4_Msk instead */ +#define XDMAC_GRWR_RWR5_Pos 5 /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR5_Msk (_U_(0x1) << XDMAC_GRWR_RWR5_Pos) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR5 XDMAC_GRWR_RWR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR5_Msk instead */ +#define XDMAC_GRWR_RWR6_Pos 6 /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR6_Msk (_U_(0x1) << XDMAC_GRWR_RWR6_Pos) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR6 XDMAC_GRWR_RWR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR6_Msk instead */ +#define XDMAC_GRWR_RWR7_Pos 7 /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR7_Msk (_U_(0x1) << XDMAC_GRWR_RWR7_Pos) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR7 XDMAC_GRWR_RWR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR7_Msk instead */ +#define XDMAC_GRWR_RWR8_Pos 8 /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR8_Msk (_U_(0x1) << XDMAC_GRWR_RWR8_Pos) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR8 XDMAC_GRWR_RWR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR8_Msk instead */ +#define XDMAC_GRWR_RWR9_Pos 9 /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR9_Msk (_U_(0x1) << XDMAC_GRWR_RWR9_Pos) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR9 XDMAC_GRWR_RWR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR9_Msk instead */ +#define XDMAC_GRWR_RWR10_Pos 10 /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR10_Msk (_U_(0x1) << XDMAC_GRWR_RWR10_Pos) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR10 XDMAC_GRWR_RWR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR10_Msk instead */ +#define XDMAC_GRWR_RWR11_Pos 11 /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR11_Msk (_U_(0x1) << XDMAC_GRWR_RWR11_Pos) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR11 XDMAC_GRWR_RWR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR11_Msk instead */ +#define XDMAC_GRWR_RWR12_Pos 12 /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR12_Msk (_U_(0x1) << XDMAC_GRWR_RWR12_Pos) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR12 XDMAC_GRWR_RWR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR12_Msk instead */ +#define XDMAC_GRWR_RWR13_Pos 13 /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR13_Msk (_U_(0x1) << XDMAC_GRWR_RWR13_Pos) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR13 XDMAC_GRWR_RWR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR13_Msk instead */ +#define XDMAC_GRWR_RWR14_Pos 14 /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR14_Msk (_U_(0x1) << XDMAC_GRWR_RWR14_Pos) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR14 XDMAC_GRWR_RWR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR14_Msk instead */ +#define XDMAC_GRWR_RWR15_Pos 15 /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR15_Msk (_U_(0x1) << XDMAC_GRWR_RWR15_Pos) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR15 XDMAC_GRWR_RWR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR15_Msk instead */ +#define XDMAC_GRWR_RWR16_Pos 16 /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR16_Msk (_U_(0x1) << XDMAC_GRWR_RWR16_Pos) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR16 XDMAC_GRWR_RWR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR16_Msk instead */ +#define XDMAC_GRWR_RWR17_Pos 17 /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR17_Msk (_U_(0x1) << XDMAC_GRWR_RWR17_Pos) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR17 XDMAC_GRWR_RWR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR17_Msk instead */ +#define XDMAC_GRWR_RWR18_Pos 18 /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR18_Msk (_U_(0x1) << XDMAC_GRWR_RWR18_Pos) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR18 XDMAC_GRWR_RWR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR18_Msk instead */ +#define XDMAC_GRWR_RWR19_Pos 19 /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR19_Msk (_U_(0x1) << XDMAC_GRWR_RWR19_Pos) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR19 XDMAC_GRWR_RWR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR19_Msk instead */ +#define XDMAC_GRWR_RWR20_Pos 20 /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR20_Msk (_U_(0x1) << XDMAC_GRWR_RWR20_Pos) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR20 XDMAC_GRWR_RWR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR20_Msk instead */ +#define XDMAC_GRWR_RWR21_Pos 21 /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR21_Msk (_U_(0x1) << XDMAC_GRWR_RWR21_Pos) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR21 XDMAC_GRWR_RWR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR21_Msk instead */ +#define XDMAC_GRWR_RWR22_Pos 22 /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR22_Msk (_U_(0x1) << XDMAC_GRWR_RWR22_Pos) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR22 XDMAC_GRWR_RWR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR22_Msk instead */ +#define XDMAC_GRWR_RWR23_Pos 23 /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR23_Msk (_U_(0x1) << XDMAC_GRWR_RWR23_Pos) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR23 XDMAC_GRWR_RWR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GRWR_RWR23_Msk instead */ +#define XDMAC_GRWR_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GRWR) Register MASK (Use XDMAC_GRWR_Msk instead) */ +#define XDMAC_GRWR_Msk _U_(0xFFFFFF) /**< (XDMAC_GRWR) Register Mask */ + +#define XDMAC_GRWR_RWR_Pos 0 /**< (XDMAC_GRWR Position) XDMAC Channel 23 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR_Msk (_U_(0xFFFFFF) << XDMAC_GRWR_RWR_Pos) /**< (XDMAC_GRWR Mask) RWR */ +#define XDMAC_GRWR_RWR(value) (XDMAC_GRWR_RWR_Msk & ((value) << XDMAC_GRWR_RWR_Pos)) + +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) (/W 32) Global Channel Software Request Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWREQ0:1; /**< bit: 0 XDMAC Channel 0 Software Request Bit */ + uint32_t SWREQ1:1; /**< bit: 1 XDMAC Channel 1 Software Request Bit */ + uint32_t SWREQ2:1; /**< bit: 2 XDMAC Channel 2 Software Request Bit */ + uint32_t SWREQ3:1; /**< bit: 3 XDMAC Channel 3 Software Request Bit */ + uint32_t SWREQ4:1; /**< bit: 4 XDMAC Channel 4 Software Request Bit */ + uint32_t SWREQ5:1; /**< bit: 5 XDMAC Channel 5 Software Request Bit */ + uint32_t SWREQ6:1; /**< bit: 6 XDMAC Channel 6 Software Request Bit */ + uint32_t SWREQ7:1; /**< bit: 7 XDMAC Channel 7 Software Request Bit */ + uint32_t SWREQ8:1; /**< bit: 8 XDMAC Channel 8 Software Request Bit */ + uint32_t SWREQ9:1; /**< bit: 9 XDMAC Channel 9 Software Request Bit */ + uint32_t SWREQ10:1; /**< bit: 10 XDMAC Channel 10 Software Request Bit */ + uint32_t SWREQ11:1; /**< bit: 11 XDMAC Channel 11 Software Request Bit */ + uint32_t SWREQ12:1; /**< bit: 12 XDMAC Channel 12 Software Request Bit */ + uint32_t SWREQ13:1; /**< bit: 13 XDMAC Channel 13 Software Request Bit */ + uint32_t SWREQ14:1; /**< bit: 14 XDMAC Channel 14 Software Request Bit */ + uint32_t SWREQ15:1; /**< bit: 15 XDMAC Channel 15 Software Request Bit */ + uint32_t SWREQ16:1; /**< bit: 16 XDMAC Channel 16 Software Request Bit */ + uint32_t SWREQ17:1; /**< bit: 17 XDMAC Channel 17 Software Request Bit */ + uint32_t SWREQ18:1; /**< bit: 18 XDMAC Channel 18 Software Request Bit */ + uint32_t SWREQ19:1; /**< bit: 19 XDMAC Channel 19 Software Request Bit */ + uint32_t SWREQ20:1; /**< bit: 20 XDMAC Channel 20 Software Request Bit */ + uint32_t SWREQ21:1; /**< bit: 21 XDMAC Channel 21 Software Request Bit */ + uint32_t SWREQ22:1; /**< bit: 22 XDMAC Channel 22 Software Request Bit */ + uint32_t SWREQ23:1; /**< bit: 23 XDMAC Channel 23 Software Request Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SWREQ:24; /**< bit: 0..23 XDMAC Channel 23 Software Request Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GSWR_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GSWR_OFFSET (0x38) /**< (XDMAC_GSWR) Global Channel Software Request Register Offset */ + +#define XDMAC_GSWR_SWREQ0_Pos 0 /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ0_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ0_Pos) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ0 XDMAC_GSWR_SWREQ0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ0_Msk instead */ +#define XDMAC_GSWR_SWREQ1_Pos 1 /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ1_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ1_Pos) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ1 XDMAC_GSWR_SWREQ1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ1_Msk instead */ +#define XDMAC_GSWR_SWREQ2_Pos 2 /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ2_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ2_Pos) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ2 XDMAC_GSWR_SWREQ2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ2_Msk instead */ +#define XDMAC_GSWR_SWREQ3_Pos 3 /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ3_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ3_Pos) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ3 XDMAC_GSWR_SWREQ3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ3_Msk instead */ +#define XDMAC_GSWR_SWREQ4_Pos 4 /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ4_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ4_Pos) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ4 XDMAC_GSWR_SWREQ4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ4_Msk instead */ +#define XDMAC_GSWR_SWREQ5_Pos 5 /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ5_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ5_Pos) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ5 XDMAC_GSWR_SWREQ5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ5_Msk instead */ +#define XDMAC_GSWR_SWREQ6_Pos 6 /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ6_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ6_Pos) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ6 XDMAC_GSWR_SWREQ6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ6_Msk instead */ +#define XDMAC_GSWR_SWREQ7_Pos 7 /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ7_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ7_Pos) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ7 XDMAC_GSWR_SWREQ7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ7_Msk instead */ +#define XDMAC_GSWR_SWREQ8_Pos 8 /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ8_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ8_Pos) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ8 XDMAC_GSWR_SWREQ8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ8_Msk instead */ +#define XDMAC_GSWR_SWREQ9_Pos 9 /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ9_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ9_Pos) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ9 XDMAC_GSWR_SWREQ9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ9_Msk instead */ +#define XDMAC_GSWR_SWREQ10_Pos 10 /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ10_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ10_Pos) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ10 XDMAC_GSWR_SWREQ10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ10_Msk instead */ +#define XDMAC_GSWR_SWREQ11_Pos 11 /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ11_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ11_Pos) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ11 XDMAC_GSWR_SWREQ11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ11_Msk instead */ +#define XDMAC_GSWR_SWREQ12_Pos 12 /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ12_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ12_Pos) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ12 XDMAC_GSWR_SWREQ12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ12_Msk instead */ +#define XDMAC_GSWR_SWREQ13_Pos 13 /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ13_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ13_Pos) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ13 XDMAC_GSWR_SWREQ13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ13_Msk instead */ +#define XDMAC_GSWR_SWREQ14_Pos 14 /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ14_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ14_Pos) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ14 XDMAC_GSWR_SWREQ14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ14_Msk instead */ +#define XDMAC_GSWR_SWREQ15_Pos 15 /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ15_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ15_Pos) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ15 XDMAC_GSWR_SWREQ15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ15_Msk instead */ +#define XDMAC_GSWR_SWREQ16_Pos 16 /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ16_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ16_Pos) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ16 XDMAC_GSWR_SWREQ16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ16_Msk instead */ +#define XDMAC_GSWR_SWREQ17_Pos 17 /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ17_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ17_Pos) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ17 XDMAC_GSWR_SWREQ17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ17_Msk instead */ +#define XDMAC_GSWR_SWREQ18_Pos 18 /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ18_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ18_Pos) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ18 XDMAC_GSWR_SWREQ18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ18_Msk instead */ +#define XDMAC_GSWR_SWREQ19_Pos 19 /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ19_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ19_Pos) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ19 XDMAC_GSWR_SWREQ19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ19_Msk instead */ +#define XDMAC_GSWR_SWREQ20_Pos 20 /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ20_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ20_Pos) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ20 XDMAC_GSWR_SWREQ20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ20_Msk instead */ +#define XDMAC_GSWR_SWREQ21_Pos 21 /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ21_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ21_Pos) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ21 XDMAC_GSWR_SWREQ21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ21_Msk instead */ +#define XDMAC_GSWR_SWREQ22_Pos 22 /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ22_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ22_Pos) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ22 XDMAC_GSWR_SWREQ22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ22_Msk instead */ +#define XDMAC_GSWR_SWREQ23_Pos 23 /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ23_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ23_Pos) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ23 XDMAC_GSWR_SWREQ23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWR_SWREQ23_Msk instead */ +#define XDMAC_GSWR_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWR) Register MASK (Use XDMAC_GSWR_Msk instead) */ +#define XDMAC_GSWR_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWR) Register Mask */ + +#define XDMAC_GSWR_SWREQ_Pos 0 /**< (XDMAC_GSWR Position) XDMAC Channel 23 Software Request Bit */ +#define XDMAC_GSWR_SWREQ_Msk (_U_(0xFFFFFF) << XDMAC_GSWR_SWREQ_Pos) /**< (XDMAC_GSWR Mask) SWREQ */ +#define XDMAC_GSWR_SWREQ(value) (XDMAC_GSWR_SWREQ_Msk & ((value) << XDMAC_GSWR_SWREQ_Pos)) + +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3c) (R/ 32) Global Channel Software Request Status Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWRS0:1; /**< bit: 0 XDMAC Channel 0 Software Request Status Bit */ + uint32_t SWRS1:1; /**< bit: 1 XDMAC Channel 1 Software Request Status Bit */ + uint32_t SWRS2:1; /**< bit: 2 XDMAC Channel 2 Software Request Status Bit */ + uint32_t SWRS3:1; /**< bit: 3 XDMAC Channel 3 Software Request Status Bit */ + uint32_t SWRS4:1; /**< bit: 4 XDMAC Channel 4 Software Request Status Bit */ + uint32_t SWRS5:1; /**< bit: 5 XDMAC Channel 5 Software Request Status Bit */ + uint32_t SWRS6:1; /**< bit: 6 XDMAC Channel 6 Software Request Status Bit */ + uint32_t SWRS7:1; /**< bit: 7 XDMAC Channel 7 Software Request Status Bit */ + uint32_t SWRS8:1; /**< bit: 8 XDMAC Channel 8 Software Request Status Bit */ + uint32_t SWRS9:1; /**< bit: 9 XDMAC Channel 9 Software Request Status Bit */ + uint32_t SWRS10:1; /**< bit: 10 XDMAC Channel 10 Software Request Status Bit */ + uint32_t SWRS11:1; /**< bit: 11 XDMAC Channel 11 Software Request Status Bit */ + uint32_t SWRS12:1; /**< bit: 12 XDMAC Channel 12 Software Request Status Bit */ + uint32_t SWRS13:1; /**< bit: 13 XDMAC Channel 13 Software Request Status Bit */ + uint32_t SWRS14:1; /**< bit: 14 XDMAC Channel 14 Software Request Status Bit */ + uint32_t SWRS15:1; /**< bit: 15 XDMAC Channel 15 Software Request Status Bit */ + uint32_t SWRS16:1; /**< bit: 16 XDMAC Channel 16 Software Request Status Bit */ + uint32_t SWRS17:1; /**< bit: 17 XDMAC Channel 17 Software Request Status Bit */ + uint32_t SWRS18:1; /**< bit: 18 XDMAC Channel 18 Software Request Status Bit */ + uint32_t SWRS19:1; /**< bit: 19 XDMAC Channel 19 Software Request Status Bit */ + uint32_t SWRS20:1; /**< bit: 20 XDMAC Channel 20 Software Request Status Bit */ + uint32_t SWRS21:1; /**< bit: 21 XDMAC Channel 21 Software Request Status Bit */ + uint32_t SWRS22:1; /**< bit: 22 XDMAC Channel 22 Software Request Status Bit */ + uint32_t SWRS23:1; /**< bit: 23 XDMAC Channel 23 Software Request Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SWRS:24; /**< bit: 0..23 XDMAC Channel 23 Software Request Status Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GSWS_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GSWS_OFFSET (0x3C) /**< (XDMAC_GSWS) Global Channel Software Request Status Register Offset */ + +#define XDMAC_GSWS_SWRS0_Pos 0 /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS0_Msk (_U_(0x1) << XDMAC_GSWS_SWRS0_Pos) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS0 XDMAC_GSWS_SWRS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS0_Msk instead */ +#define XDMAC_GSWS_SWRS1_Pos 1 /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS1_Msk (_U_(0x1) << XDMAC_GSWS_SWRS1_Pos) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS1 XDMAC_GSWS_SWRS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS1_Msk instead */ +#define XDMAC_GSWS_SWRS2_Pos 2 /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS2_Msk (_U_(0x1) << XDMAC_GSWS_SWRS2_Pos) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS2 XDMAC_GSWS_SWRS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS2_Msk instead */ +#define XDMAC_GSWS_SWRS3_Pos 3 /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS3_Msk (_U_(0x1) << XDMAC_GSWS_SWRS3_Pos) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS3 XDMAC_GSWS_SWRS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS3_Msk instead */ +#define XDMAC_GSWS_SWRS4_Pos 4 /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS4_Msk (_U_(0x1) << XDMAC_GSWS_SWRS4_Pos) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS4 XDMAC_GSWS_SWRS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS4_Msk instead */ +#define XDMAC_GSWS_SWRS5_Pos 5 /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS5_Msk (_U_(0x1) << XDMAC_GSWS_SWRS5_Pos) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS5 XDMAC_GSWS_SWRS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS5_Msk instead */ +#define XDMAC_GSWS_SWRS6_Pos 6 /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS6_Msk (_U_(0x1) << XDMAC_GSWS_SWRS6_Pos) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS6 XDMAC_GSWS_SWRS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS6_Msk instead */ +#define XDMAC_GSWS_SWRS7_Pos 7 /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS7_Msk (_U_(0x1) << XDMAC_GSWS_SWRS7_Pos) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS7 XDMAC_GSWS_SWRS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS7_Msk instead */ +#define XDMAC_GSWS_SWRS8_Pos 8 /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS8_Msk (_U_(0x1) << XDMAC_GSWS_SWRS8_Pos) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS8 XDMAC_GSWS_SWRS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS8_Msk instead */ +#define XDMAC_GSWS_SWRS9_Pos 9 /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS9_Msk (_U_(0x1) << XDMAC_GSWS_SWRS9_Pos) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS9 XDMAC_GSWS_SWRS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS9_Msk instead */ +#define XDMAC_GSWS_SWRS10_Pos 10 /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS10_Msk (_U_(0x1) << XDMAC_GSWS_SWRS10_Pos) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS10 XDMAC_GSWS_SWRS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS10_Msk instead */ +#define XDMAC_GSWS_SWRS11_Pos 11 /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS11_Msk (_U_(0x1) << XDMAC_GSWS_SWRS11_Pos) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS11 XDMAC_GSWS_SWRS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS11_Msk instead */ +#define XDMAC_GSWS_SWRS12_Pos 12 /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS12_Msk (_U_(0x1) << XDMAC_GSWS_SWRS12_Pos) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS12 XDMAC_GSWS_SWRS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS12_Msk instead */ +#define XDMAC_GSWS_SWRS13_Pos 13 /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS13_Msk (_U_(0x1) << XDMAC_GSWS_SWRS13_Pos) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS13 XDMAC_GSWS_SWRS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS13_Msk instead */ +#define XDMAC_GSWS_SWRS14_Pos 14 /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS14_Msk (_U_(0x1) << XDMAC_GSWS_SWRS14_Pos) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS14 XDMAC_GSWS_SWRS14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS14_Msk instead */ +#define XDMAC_GSWS_SWRS15_Pos 15 /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS15_Msk (_U_(0x1) << XDMAC_GSWS_SWRS15_Pos) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS15 XDMAC_GSWS_SWRS15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS15_Msk instead */ +#define XDMAC_GSWS_SWRS16_Pos 16 /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS16_Msk (_U_(0x1) << XDMAC_GSWS_SWRS16_Pos) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS16 XDMAC_GSWS_SWRS16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS16_Msk instead */ +#define XDMAC_GSWS_SWRS17_Pos 17 /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS17_Msk (_U_(0x1) << XDMAC_GSWS_SWRS17_Pos) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS17 XDMAC_GSWS_SWRS17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS17_Msk instead */ +#define XDMAC_GSWS_SWRS18_Pos 18 /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS18_Msk (_U_(0x1) << XDMAC_GSWS_SWRS18_Pos) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS18 XDMAC_GSWS_SWRS18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS18_Msk instead */ +#define XDMAC_GSWS_SWRS19_Pos 19 /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS19_Msk (_U_(0x1) << XDMAC_GSWS_SWRS19_Pos) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS19 XDMAC_GSWS_SWRS19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS19_Msk instead */ +#define XDMAC_GSWS_SWRS20_Pos 20 /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS20_Msk (_U_(0x1) << XDMAC_GSWS_SWRS20_Pos) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS20 XDMAC_GSWS_SWRS20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS20_Msk instead */ +#define XDMAC_GSWS_SWRS21_Pos 21 /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS21_Msk (_U_(0x1) << XDMAC_GSWS_SWRS21_Pos) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS21 XDMAC_GSWS_SWRS21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS21_Msk instead */ +#define XDMAC_GSWS_SWRS22_Pos 22 /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS22_Msk (_U_(0x1) << XDMAC_GSWS_SWRS22_Pos) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS22 XDMAC_GSWS_SWRS22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS22_Msk instead */ +#define XDMAC_GSWS_SWRS23_Pos 23 /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS23_Msk (_U_(0x1) << XDMAC_GSWS_SWRS23_Pos) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS23 XDMAC_GSWS_SWRS23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWS_SWRS23_Msk instead */ +#define XDMAC_GSWS_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWS) Register MASK (Use XDMAC_GSWS_Msk instead) */ +#define XDMAC_GSWS_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWS) Register Mask */ + +#define XDMAC_GSWS_SWRS_Pos 0 /**< (XDMAC_GSWS Position) XDMAC Channel 23 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS_Msk (_U_(0xFFFFFF) << XDMAC_GSWS_SWRS_Pos) /**< (XDMAC_GSWS Mask) SWRS */ +#define XDMAC_GSWS_SWRS(value) (XDMAC_GSWS_SWRS_Msk & ((value) << XDMAC_GSWS_SWRS_Pos)) + +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) (/W 32) Global Channel Software Flush Request Register -------- */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'N' +typedef union { + struct { + uint32_t SWF0:1; /**< bit: 0 XDMAC Channel 0 Software Flush Request Bit */ + uint32_t SWF1:1; /**< bit: 1 XDMAC Channel 1 Software Flush Request Bit */ + uint32_t SWF2:1; /**< bit: 2 XDMAC Channel 2 Software Flush Request Bit */ + uint32_t SWF3:1; /**< bit: 3 XDMAC Channel 3 Software Flush Request Bit */ + uint32_t SWF4:1; /**< bit: 4 XDMAC Channel 4 Software Flush Request Bit */ + uint32_t SWF5:1; /**< bit: 5 XDMAC Channel 5 Software Flush Request Bit */ + uint32_t SWF6:1; /**< bit: 6 XDMAC Channel 6 Software Flush Request Bit */ + uint32_t SWF7:1; /**< bit: 7 XDMAC Channel 7 Software Flush Request Bit */ + uint32_t SWF8:1; /**< bit: 8 XDMAC Channel 8 Software Flush Request Bit */ + uint32_t SWF9:1; /**< bit: 9 XDMAC Channel 9 Software Flush Request Bit */ + uint32_t SWF10:1; /**< bit: 10 XDMAC Channel 10 Software Flush Request Bit */ + uint32_t SWF11:1; /**< bit: 11 XDMAC Channel 11 Software Flush Request Bit */ + uint32_t SWF12:1; /**< bit: 12 XDMAC Channel 12 Software Flush Request Bit */ + uint32_t SWF13:1; /**< bit: 13 XDMAC Channel 13 Software Flush Request Bit */ + uint32_t SWF14:1; /**< bit: 14 XDMAC Channel 14 Software Flush Request Bit */ + uint32_t SWF15:1; /**< bit: 15 XDMAC Channel 15 Software Flush Request Bit */ + uint32_t SWF16:1; /**< bit: 16 XDMAC Channel 16 Software Flush Request Bit */ + uint32_t SWF17:1; /**< bit: 17 XDMAC Channel 17 Software Flush Request Bit */ + uint32_t SWF18:1; /**< bit: 18 XDMAC Channel 18 Software Flush Request Bit */ + uint32_t SWF19:1; /**< bit: 19 XDMAC Channel 19 Software Flush Request Bit */ + uint32_t SWF20:1; /**< bit: 20 XDMAC Channel 20 Software Flush Request Bit */ + uint32_t SWF21:1; /**< bit: 21 XDMAC Channel 21 Software Flush Request Bit */ + uint32_t SWF22:1; /**< bit: 22 XDMAC Channel 22 Software Flush Request Bit */ + uint32_t SWF23:1; /**< bit: 23 XDMAC Channel 23 Software Flush Request Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } bit; /**< Structure used for bit access */ + struct { + uint32_t SWF:24; /**< bit: 0..23 XDMAC Channel 23 Software Flush Request Bit */ + uint32_t :8; /**< bit: 24..31 Reserved */ + } vec; /**< Structure used for vec access */ + uint32_t reg; /**< Type used for register access */ +} XDMAC_GSWF_Type; +#endif +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define XDMAC_GSWF_OFFSET (0x40) /**< (XDMAC_GSWF) Global Channel Software Flush Request Register Offset */ + +#define XDMAC_GSWF_SWF0_Pos 0 /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF0_Msk (_U_(0x1) << XDMAC_GSWF_SWF0_Pos) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF0 XDMAC_GSWF_SWF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF0_Msk instead */ +#define XDMAC_GSWF_SWF1_Pos 1 /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF1_Msk (_U_(0x1) << XDMAC_GSWF_SWF1_Pos) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF1 XDMAC_GSWF_SWF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF1_Msk instead */ +#define XDMAC_GSWF_SWF2_Pos 2 /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF2_Msk (_U_(0x1) << XDMAC_GSWF_SWF2_Pos) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF2 XDMAC_GSWF_SWF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF2_Msk instead */ +#define XDMAC_GSWF_SWF3_Pos 3 /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF3_Msk (_U_(0x1) << XDMAC_GSWF_SWF3_Pos) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF3 XDMAC_GSWF_SWF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF3_Msk instead */ +#define XDMAC_GSWF_SWF4_Pos 4 /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF4_Msk (_U_(0x1) << XDMAC_GSWF_SWF4_Pos) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF4 XDMAC_GSWF_SWF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF4_Msk instead */ +#define XDMAC_GSWF_SWF5_Pos 5 /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF5_Msk (_U_(0x1) << XDMAC_GSWF_SWF5_Pos) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF5 XDMAC_GSWF_SWF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF5_Msk instead */ +#define XDMAC_GSWF_SWF6_Pos 6 /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF6_Msk (_U_(0x1) << XDMAC_GSWF_SWF6_Pos) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF6 XDMAC_GSWF_SWF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF6_Msk instead */ +#define XDMAC_GSWF_SWF7_Pos 7 /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF7_Msk (_U_(0x1) << XDMAC_GSWF_SWF7_Pos) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF7 XDMAC_GSWF_SWF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF7_Msk instead */ +#define XDMAC_GSWF_SWF8_Pos 8 /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF8_Msk (_U_(0x1) << XDMAC_GSWF_SWF8_Pos) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF8 XDMAC_GSWF_SWF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF8_Msk instead */ +#define XDMAC_GSWF_SWF9_Pos 9 /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF9_Msk (_U_(0x1) << XDMAC_GSWF_SWF9_Pos) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF9 XDMAC_GSWF_SWF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF9_Msk instead */ +#define XDMAC_GSWF_SWF10_Pos 10 /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF10_Msk (_U_(0x1) << XDMAC_GSWF_SWF10_Pos) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF10 XDMAC_GSWF_SWF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF10_Msk instead */ +#define XDMAC_GSWF_SWF11_Pos 11 /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF11_Msk (_U_(0x1) << XDMAC_GSWF_SWF11_Pos) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF11 XDMAC_GSWF_SWF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF11_Msk instead */ +#define XDMAC_GSWF_SWF12_Pos 12 /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF12_Msk (_U_(0x1) << XDMAC_GSWF_SWF12_Pos) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF12 XDMAC_GSWF_SWF12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF12_Msk instead */ +#define XDMAC_GSWF_SWF13_Pos 13 /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF13_Msk (_U_(0x1) << XDMAC_GSWF_SWF13_Pos) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF13 XDMAC_GSWF_SWF13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF13_Msk instead */ +#define XDMAC_GSWF_SWF14_Pos 14 /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF14_Msk (_U_(0x1) << XDMAC_GSWF_SWF14_Pos) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF14 XDMAC_GSWF_SWF14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF14_Msk instead */ +#define XDMAC_GSWF_SWF15_Pos 15 /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF15_Msk (_U_(0x1) << XDMAC_GSWF_SWF15_Pos) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF15 XDMAC_GSWF_SWF15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF15_Msk instead */ +#define XDMAC_GSWF_SWF16_Pos 16 /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF16_Msk (_U_(0x1) << XDMAC_GSWF_SWF16_Pos) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF16 XDMAC_GSWF_SWF16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF16_Msk instead */ +#define XDMAC_GSWF_SWF17_Pos 17 /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF17_Msk (_U_(0x1) << XDMAC_GSWF_SWF17_Pos) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF17 XDMAC_GSWF_SWF17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF17_Msk instead */ +#define XDMAC_GSWF_SWF18_Pos 18 /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF18_Msk (_U_(0x1) << XDMAC_GSWF_SWF18_Pos) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF18 XDMAC_GSWF_SWF18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF18_Msk instead */ +#define XDMAC_GSWF_SWF19_Pos 19 /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF19_Msk (_U_(0x1) << XDMAC_GSWF_SWF19_Pos) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF19 XDMAC_GSWF_SWF19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF19_Msk instead */ +#define XDMAC_GSWF_SWF20_Pos 20 /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF20_Msk (_U_(0x1) << XDMAC_GSWF_SWF20_Pos) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF20 XDMAC_GSWF_SWF20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF20_Msk instead */ +#define XDMAC_GSWF_SWF21_Pos 21 /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF21_Msk (_U_(0x1) << XDMAC_GSWF_SWF21_Pos) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF21 XDMAC_GSWF_SWF21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF21_Msk instead */ +#define XDMAC_GSWF_SWF22_Pos 22 /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF22_Msk (_U_(0x1) << XDMAC_GSWF_SWF22_Pos) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF22 XDMAC_GSWF_SWF22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF22_Msk instead */ +#define XDMAC_GSWF_SWF23_Pos 23 /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF23_Msk (_U_(0x1) << XDMAC_GSWF_SWF23_Pos) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF23 XDMAC_GSWF_SWF23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use XDMAC_GSWF_SWF23_Msk instead */ +#define XDMAC_GSWF_MASK _U_(0xFFFFFF) /**< \deprecated (XDMAC_GSWF) Register MASK (Use XDMAC_GSWF_Msk instead) */ +#define XDMAC_GSWF_Msk _U_(0xFFFFFF) /**< (XDMAC_GSWF) Register Mask */ + +#define XDMAC_GSWF_SWF_Pos 0 /**< (XDMAC_GSWF Position) XDMAC Channel 23 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF_Msk (_U_(0xFFFFFF) << XDMAC_GSWF_SWF_Pos) /**< (XDMAC_GSWF Mask) SWF */ +#define XDMAC_GSWF_SWF(value) (XDMAC_GSWF_SWF_Msk & ((value) << XDMAC_GSWF_SWF_Pos)) + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if COMPONENT_TYPEDEF_STYLE == 'R' +/** \brief XDMAC_CHID hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< (XDMAC_CHID Offset: 0x00) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< (XDMAC_CHID Offset: 0x04) Channel Interrupt Disable Register */ + __I uint32_t XDMAC_CIM; /**< (XDMAC_CHID Offset: 0x08) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< (XDMAC_CHID Offset: 0x0C) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< (XDMAC_CHID Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< (XDMAC_CHID Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< (XDMAC_CHID Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< (XDMAC_CHID Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< (XDMAC_CHID Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< (XDMAC_CHID Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< (XDMAC_CHID Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< (XDMAC_CHID Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< (XDMAC_CHID Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< (XDMAC_CHID Offset: 0x34) Channel Destination Microblock Stride */ + __I uint8_t Reserved1[8]; +} XdmacChid; + +#define XDMACCHID_NUMBER 24 +/** \brief XDMAC hardware registers */ +typedef struct { + __I uint32_t XDMAC_GTYPE; /**< (XDMAC Offset: 0x00) Global Type Register */ + __IO uint32_t XDMAC_GCFG; /**< (XDMAC Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< (XDMAC Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< (XDMAC Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< (XDMAC Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< (XDMAC Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< (XDMAC Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< (XDMAC Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< (XDMAC Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< (XDMAC Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< (XDMAC Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< (XDMAC Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< (XDMAC Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< (XDMAC Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< (XDMAC Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint8_t Reserved1[12]; + XdmacChid XdmacChid[XDMACCHID_NUMBER]; /**< Offset: 0x50 Channel Interrupt Enable Register */ +} Xdmac; + +#elif COMPONENT_TYPEDEF_STYLE == 'N' +/** \brief XDMAC_CHID hardware registers */ +typedef struct { + __O XDMAC_CIE_Type XDMAC_CIE; /**< Offset: 0x00 ( /W 32) Channel Interrupt Enable Register */ + __O XDMAC_CID_Type XDMAC_CID; /**< Offset: 0x04 ( /W 32) Channel Interrupt Disable Register */ + __I XDMAC_CIM_Type XDMAC_CIM; /**< Offset: 0x08 (R/ 32) Channel Interrupt Mask Register */ + __I XDMAC_CIS_Type XDMAC_CIS; /**< Offset: 0x0C (R/ 32) Channel Interrupt Status Register */ + __IO XDMAC_CSA_Type XDMAC_CSA; /**< Offset: 0x10 (R/W 32) Channel Source Address Register */ + __IO XDMAC_CDA_Type XDMAC_CDA; /**< Offset: 0x14 (R/W 32) Channel Destination Address Register */ + __IO XDMAC_CNDA_Type XDMAC_CNDA; /**< Offset: 0x18 (R/W 32) Channel Next Descriptor Address Register */ + __IO XDMAC_CNDC_Type XDMAC_CNDC; /**< Offset: 0x1C (R/W 32) Channel Next Descriptor Control Register */ + __IO XDMAC_CUBC_Type XDMAC_CUBC; /**< Offset: 0x20 (R/W 32) Channel Microblock Control Register */ + __IO XDMAC_CBC_Type XDMAC_CBC; /**< Offset: 0x24 (R/W 32) Channel Block Control Register */ + __IO XDMAC_CC_Type XDMAC_CC; /**< Offset: 0x28 (R/W 32) Channel Configuration Register */ + __IO XDMAC_CDS_MSP_Type XDMAC_CDS_MSP; /**< Offset: 0x2C (R/W 32) Channel Data Stride Memory Set Pattern */ + __IO XDMAC_CSUS_Type XDMAC_CSUS; /**< Offset: 0x30 (R/W 32) Channel Source Microblock Stride */ + __IO XDMAC_CDUS_Type XDMAC_CDUS; /**< Offset: 0x34 (R/W 32) Channel Destination Microblock Stride */ + __I uint8_t Reserved1[8]; +} XdmacChid; + +/** \brief XDMAC hardware registers */ +typedef struct { + __I XDMAC_GTYPE_Type XDMAC_GTYPE; /**< Offset: 0x00 (R/ 32) Global Type Register */ + __IO XDMAC_GCFG_Type XDMAC_GCFG; /**< Offset: 0x04 (R/W 32) Global Configuration Register */ + __IO XDMAC_GWAC_Type XDMAC_GWAC; /**< Offset: 0x08 (R/W 32) Global Weighted Arbiter Configuration Register */ + __O XDMAC_GIE_Type XDMAC_GIE; /**< Offset: 0x0C ( /W 32) Global Interrupt Enable Register */ + __O XDMAC_GID_Type XDMAC_GID; /**< Offset: 0x10 ( /W 32) Global Interrupt Disable Register */ + __I XDMAC_GIM_Type XDMAC_GIM; /**< Offset: 0x14 (R/ 32) Global Interrupt Mask Register */ + __I XDMAC_GIS_Type XDMAC_GIS; /**< Offset: 0x18 (R/ 32) Global Interrupt Status Register */ + __O XDMAC_GE_Type XDMAC_GE; /**< Offset: 0x1C ( /W 32) Global Channel Enable Register */ + __O XDMAC_GD_Type XDMAC_GD; /**< Offset: 0x20 ( /W 32) Global Channel Disable Register */ + __I XDMAC_GS_Type XDMAC_GS; /**< Offset: 0x24 (R/ 32) Global Channel Status Register */ + __IO XDMAC_GRS_Type XDMAC_GRS; /**< Offset: 0x28 (R/W 32) Global Channel Read Suspend Register */ + __IO XDMAC_GWS_Type XDMAC_GWS; /**< Offset: 0x2C (R/W 32) Global Channel Write Suspend Register */ + __O XDMAC_GRWS_Type XDMAC_GRWS; /**< Offset: 0x30 ( /W 32) Global Channel Read Write Suspend Register */ + __O XDMAC_GRWR_Type XDMAC_GRWR; /**< Offset: 0x34 ( /W 32) Global Channel Read Write Resume Register */ + __O XDMAC_GSWR_Type XDMAC_GSWR; /**< Offset: 0x38 ( /W 32) Global Channel Software Request Register */ + __I XDMAC_GSWS_Type XDMAC_GSWS; /**< Offset: 0x3C (R/ 32) Global Channel Software Request Status Register */ + __O XDMAC_GSWF_Type XDMAC_GSWF; /**< Offset: 0x40 ( /W 32) Global Channel Software Flush Request Register */ + __I uint8_t Reserved1[12]; + XdmacChid XdmacChid[24]; /**< Offset: 0x50 Channel Interrupt Enable Register */ +} Xdmac; + +#else /* COMPONENT_TYPEDEF_STYLE */ +#error Unknown component typedef style +#endif /* COMPONENT_TYPEDEF_STYLE */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Extensible DMA Controller */ + +#endif /* _SAME70_XDMAC_COMPONENT_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/acc.h b/bsp/microchip/same70/bsp/same70b/include/instance/acc.h new file mode 100644 index 0000000000..c5689fb183 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/acc.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for ACC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ACC_INSTANCE_H_ +#define _SAME70_ACC_INSTANCE_H_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_ACC_CR (0x40044000) /**< (ACC) Control Register */ +#define REG_ACC_MR (0x40044004) /**< (ACC) Mode Register */ +#define REG_ACC_IER (0x40044024) /**< (ACC) Interrupt Enable Register */ +#define REG_ACC_IDR (0x40044028) /**< (ACC) Interrupt Disable Register */ +#define REG_ACC_IMR (0x4004402C) /**< (ACC) Interrupt Mask Register */ +#define REG_ACC_ISR (0x40044030) /**< (ACC) Interrupt Status Register */ +#define REG_ACC_ACR (0x40044094) /**< (ACC) Analog Control Register */ +#define REG_ACC_WPMR (0x400440E4) /**< (ACC) Write Protection Mode Register */ +#define REG_ACC_WPSR (0x400440E8) /**< (ACC) Write Protection Status Register */ + +#else + +#define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< (ACC) Control Register */ +#define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< (ACC) Mode Register */ +#define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< (ACC) Interrupt Enable Register */ +#define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< (ACC) Interrupt Disable Register */ +#define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< (ACC) Interrupt Mask Register */ +#define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< (ACC) Interrupt Status Register */ +#define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< (ACC) Analog Control Register */ +#define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< (ACC) Write Protection Mode Register */ +#define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< (ACC) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for ACC peripheral ========== */ +#define ACC_INSTANCE_ID 33 +#define ACC_CLOCK_ID 33 +#define ACC_HAS_PLUS_COMPARATOR_SELECTION 1 +#define ACC_HAS_MINUS_COMPARATOR_SELECTION 1 +#define ACC_HAS_INVERTED_COMPARATOR 1 +#define ACC_HAS_EDGETYPE_SELECTION 1 +#define ACC_HAS_INTERRUPTS 1 +#define ACC_HAS_CURRENT_SELECTION 1 +#define ACC_HAS_HYSTERESIS 1 +#define ACC_HAS_FAULT_ENABLE 1 + +#endif /* _SAME70_ACC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/aes.h b/bsp/microchip/same70/bsp/same70b/include/instance/aes.h new file mode 100644 index 0000000000..9ed7c636f3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/aes.h @@ -0,0 +1,145 @@ +/** + * \file + * + * \brief Instance description for AES + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_AES_INSTANCE_H_ +#define _SAME70_AES_INSTANCE_H_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_AES_CR (0x4006C000) /**< (AES) Control Register */ +#define REG_AES_MR (0x4006C004) /**< (AES) Mode Register */ +#define REG_AES_IER (0x4006C010) /**< (AES) Interrupt Enable Register */ +#define REG_AES_IDR (0x4006C014) /**< (AES) Interrupt Disable Register */ +#define REG_AES_IMR (0x4006C018) /**< (AES) Interrupt Mask Register */ +#define REG_AES_ISR (0x4006C01C) /**< (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (0x4006C020) /**< (AES) Key Word Register */ +#define REG_AES_KEYWR0 (0x4006C020) /**< (AES) Key Word Register 0 */ +#define REG_AES_KEYWR1 (0x4006C024) /**< (AES) Key Word Register 1 */ +#define REG_AES_KEYWR2 (0x4006C028) /**< (AES) Key Word Register 2 */ +#define REG_AES_KEYWR3 (0x4006C02C) /**< (AES) Key Word Register 3 */ +#define REG_AES_KEYWR4 (0x4006C030) /**< (AES) Key Word Register 4 */ +#define REG_AES_KEYWR5 (0x4006C034) /**< (AES) Key Word Register 5 */ +#define REG_AES_KEYWR6 (0x4006C038) /**< (AES) Key Word Register 6 */ +#define REG_AES_KEYWR7 (0x4006C03C) /**< (AES) Key Word Register 7 */ +#define REG_AES_IDATAR (0x4006C040) /**< (AES) Input Data Register */ +#define REG_AES_IDATAR0 (0x4006C040) /**< (AES) Input Data Register 0 */ +#define REG_AES_IDATAR1 (0x4006C044) /**< (AES) Input Data Register 1 */ +#define REG_AES_IDATAR2 (0x4006C048) /**< (AES) Input Data Register 2 */ +#define REG_AES_IDATAR3 (0x4006C04C) /**< (AES) Input Data Register 3 */ +#define REG_AES_ODATAR (0x4006C050) /**< (AES) Output Data Register */ +#define REG_AES_ODATAR0 (0x4006C050) /**< (AES) Output Data Register 0 */ +#define REG_AES_ODATAR1 (0x4006C054) /**< (AES) Output Data Register 1 */ +#define REG_AES_ODATAR2 (0x4006C058) /**< (AES) Output Data Register 2 */ +#define REG_AES_ODATAR3 (0x4006C05C) /**< (AES) Output Data Register 3 */ +#define REG_AES_IVR (0x4006C060) /**< (AES) Initialization Vector Register */ +#define REG_AES_IVR0 (0x4006C060) /**< (AES) Initialization Vector Register 0 */ +#define REG_AES_IVR1 (0x4006C064) /**< (AES) Initialization Vector Register 1 */ +#define REG_AES_IVR2 (0x4006C068) /**< (AES) Initialization Vector Register 2 */ +#define REG_AES_IVR3 (0x4006C06C) /**< (AES) Initialization Vector Register 3 */ +#define REG_AES_AADLENR (0x4006C070) /**< (AES) Additional Authenticated Data Length Register */ +#define REG_AES_CLENR (0x4006C074) /**< (AES) Plaintext/Ciphertext Length Register */ +#define REG_AES_GHASHR (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register */ +#define REG_AES_GHASHR0 (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */ +#define REG_AES_GHASHR1 (0x4006C07C) /**< (AES) GCM Intermediate Hash Word Register 1 */ +#define REG_AES_GHASHR2 (0x4006C080) /**< (AES) GCM Intermediate Hash Word Register 2 */ +#define REG_AES_GHASHR3 (0x4006C084) /**< (AES) GCM Intermediate Hash Word Register 3 */ +#define REG_AES_TAGR (0x4006C088) /**< (AES) GCM Authentication Tag Word Register */ +#define REG_AES_TAGR0 (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */ +#define REG_AES_TAGR1 (0x4006C08C) /**< (AES) GCM Authentication Tag Word Register 1 */ +#define REG_AES_TAGR2 (0x4006C090) /**< (AES) GCM Authentication Tag Word Register 2 */ +#define REG_AES_TAGR3 (0x4006C094) /**< (AES) GCM Authentication Tag Word Register 3 */ +#define REG_AES_CTRR (0x4006C098) /**< (AES) GCM Encryption Counter Value Register */ +#define REG_AES_GCMHR (0x4006C09C) /**< (AES) GCM H Word Register */ +#define REG_AES_GCMHR0 (0x4006C09C) /**< (AES) GCM H Word Register 0 */ +#define REG_AES_GCMHR1 (0x4006C0A0) /**< (AES) GCM H Word Register 1 */ +#define REG_AES_GCMHR2 (0x4006C0A4) /**< (AES) GCM H Word Register 2 */ +#define REG_AES_GCMHR3 (0x4006C0A8) /**< (AES) GCM H Word Register 3 */ + +#else + +#define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< (AES) Control Register */ +#define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< (AES) Mode Register */ +#define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< (AES) Interrupt Enable Register */ +#define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< (AES) Interrupt Disable Register */ +#define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< (AES) Interrupt Mask Register */ +#define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register */ +#define REG_AES_KEYWR0 (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */ +#define REG_AES_KEYWR1 (*(__O uint32_t*)0x4006C024U) /**< (AES) Key Word Register 1 */ +#define REG_AES_KEYWR2 (*(__O uint32_t*)0x4006C028U) /**< (AES) Key Word Register 2 */ +#define REG_AES_KEYWR3 (*(__O uint32_t*)0x4006C02CU) /**< (AES) Key Word Register 3 */ +#define REG_AES_KEYWR4 (*(__O uint32_t*)0x4006C030U) /**< (AES) Key Word Register 4 */ +#define REG_AES_KEYWR5 (*(__O uint32_t*)0x4006C034U) /**< (AES) Key Word Register 5 */ +#define REG_AES_KEYWR6 (*(__O uint32_t*)0x4006C038U) /**< (AES) Key Word Register 6 */ +#define REG_AES_KEYWR7 (*(__O uint32_t*)0x4006C03CU) /**< (AES) Key Word Register 7 */ +#define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register */ +#define REG_AES_IDATAR0 (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */ +#define REG_AES_IDATAR1 (*(__O uint32_t*)0x4006C044U) /**< (AES) Input Data Register 1 */ +#define REG_AES_IDATAR2 (*(__O uint32_t*)0x4006C048U) /**< (AES) Input Data Register 2 */ +#define REG_AES_IDATAR3 (*(__O uint32_t*)0x4006C04CU) /**< (AES) Input Data Register 3 */ +#define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register */ +#define REG_AES_ODATAR0 (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */ +#define REG_AES_ODATAR1 (*(__I uint32_t*)0x4006C054U) /**< (AES) Output Data Register 1 */ +#define REG_AES_ODATAR2 (*(__I uint32_t*)0x4006C058U) /**< (AES) Output Data Register 2 */ +#define REG_AES_ODATAR3 (*(__I uint32_t*)0x4006C05CU) /**< (AES) Output Data Register 3 */ +#define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register */ +#define REG_AES_IVR0 (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */ +#define REG_AES_IVR1 (*(__O uint32_t*)0x4006C064U) /**< (AES) Initialization Vector Register 1 */ +#define REG_AES_IVR2 (*(__O uint32_t*)0x4006C068U) /**< (AES) Initialization Vector Register 2 */ +#define REG_AES_IVR3 (*(__O uint32_t*)0x4006C06CU) /**< (AES) Initialization Vector Register 3 */ +#define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< (AES) Additional Authenticated Data Length Register */ +#define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< (AES) Plaintext/Ciphertext Length Register */ +#define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register */ +#define REG_AES_GHASHR0 (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */ +#define REG_AES_GHASHR1 (*(__IO uint32_t*)0x4006C07CU) /**< (AES) GCM Intermediate Hash Word Register 1 */ +#define REG_AES_GHASHR2 (*(__IO uint32_t*)0x4006C080U) /**< (AES) GCM Intermediate Hash Word Register 2 */ +#define REG_AES_GHASHR3 (*(__IO uint32_t*)0x4006C084U) /**< (AES) GCM Intermediate Hash Word Register 3 */ +#define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register */ +#define REG_AES_TAGR0 (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */ +#define REG_AES_TAGR1 (*(__I uint32_t*)0x4006C08CU) /**< (AES) GCM Authentication Tag Word Register 1 */ +#define REG_AES_TAGR2 (*(__I uint32_t*)0x4006C090U) /**< (AES) GCM Authentication Tag Word Register 2 */ +#define REG_AES_TAGR3 (*(__I uint32_t*)0x4006C094U) /**< (AES) GCM Authentication Tag Word Register 3 */ +#define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< (AES) GCM Encryption Counter Value Register */ +#define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register */ +#define REG_AES_GCMHR0 (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */ +#define REG_AES_GCMHR1 (*(__IO uint32_t*)0x4006C0A0U) /**< (AES) GCM H Word Register 1 */ +#define REG_AES_GCMHR2 (*(__IO uint32_t*)0x4006C0A4U) /**< (AES) GCM H Word Register 2 */ +#define REG_AES_GCMHR3 (*(__IO uint32_t*)0x4006C0A8U) /**< (AES) GCM H Word Register 3 */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for AES peripheral ========== */ +#define AES_DMAC_ID_TX 37 +#define AES_DMAC_ID_RX 38 +#define AES_INSTANCE_ID 56 +#define AES_CLOCK_ID 56 + +#endif /* _SAME70_AES_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/afec0.h b/bsp/microchip/same70/bsp/same70b/include/instance/afec0.h new file mode 100644 index 0000000000..71f18bdbc6 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/afec0.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief Instance description for AFEC0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_AFEC0_INSTANCE_H_ +#define _SAME70_AFEC0_INSTANCE_H_ + +/* ========== Register definition for AFEC0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_AFEC0_CR (0x4003C000) /**< (AFEC0) AFEC Control Register */ +#define REG_AFEC0_MR (0x4003C004) /**< (AFEC0) AFEC Mode Register */ +#define REG_AFEC0_EMR (0x4003C008) /**< (AFEC0) AFEC Extended Mode Register */ +#define REG_AFEC0_SEQ1R (0x4003C00C) /**< (AFEC0) AFEC Channel Sequence 1 Register */ +#define REG_AFEC0_SEQ2R (0x4003C010) /**< (AFEC0) AFEC Channel Sequence 2 Register */ +#define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */ +#define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */ +#define REG_AFEC0_CHSR (0x4003C01C) /**< (AFEC0) AFEC Channel Status Register */ +#define REG_AFEC0_LCDR (0x4003C020) /**< (AFEC0) AFEC Last Converted Data Register */ +#define REG_AFEC0_IER (0x4003C024) /**< (AFEC0) AFEC Interrupt Enable Register */ +#define REG_AFEC0_IDR (0x4003C028) /**< (AFEC0) AFEC Interrupt Disable Register */ +#define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */ +#define REG_AFEC0_ISR (0x4003C030) /**< (AFEC0) AFEC Interrupt Status Register */ +#define REG_AFEC0_OVER (0x4003C04C) /**< (AFEC0) AFEC Overrun Status Register */ +#define REG_AFEC0_CWR (0x4003C050) /**< (AFEC0) AFEC Compare Window Register */ +#define REG_AFEC0_CGR (0x4003C054) /**< (AFEC0) AFEC Channel Gain Register */ +#define REG_AFEC0_DIFFR (0x4003C060) /**< (AFEC0) AFEC Channel Differential Register */ +#define REG_AFEC0_CSELR (0x4003C064) /**< (AFEC0) AFEC Channel Selection Register */ +#define REG_AFEC0_CDR (0x4003C068) /**< (AFEC0) AFEC Channel Data Register */ +#define REG_AFEC0_COCR (0x4003C06C) /**< (AFEC0) AFEC Channel Offset Compensation Register */ +#define REG_AFEC0_TEMPMR (0x4003C070) /**< (AFEC0) AFEC Temperature Sensor Mode Register */ +#define REG_AFEC0_TEMPCWR (0x4003C074) /**< (AFEC0) AFEC Temperature Compare Window Register */ +#define REG_AFEC0_ACR (0x4003C094) /**< (AFEC0) AFEC Analog Control Register */ +#define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */ +#define REG_AFEC0_COSR (0x4003C0D0) /**< (AFEC0) AFEC Correction Select Register */ +#define REG_AFEC0_CVR (0x4003C0D4) /**< (AFEC0) AFEC Correction Values Register */ +#define REG_AFEC0_CECR (0x4003C0D8) /**< (AFEC0) AFEC Channel Error Correction Register */ +#define REG_AFEC0_WPMR (0x4003C0E4) /**< (AFEC0) AFEC Write Protection Mode Register */ +#define REG_AFEC0_WPSR (0x4003C0E8) /**< (AFEC0) AFEC Write Protection Status Register */ + +#else + +#define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< (AFEC0) AFEC Control Register */ +#define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< (AFEC0) AFEC Mode Register */ +#define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< (AFEC0) AFEC Extended Mode Register */ +#define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< (AFEC0) AFEC Channel Sequence 1 Register */ +#define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< (AFEC0) AFEC Channel Sequence 2 Register */ +#define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Register */ +#define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Register */ +#define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< (AFEC0) AFEC Channel Status Register */ +#define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< (AFEC0) AFEC Last Converted Data Register */ +#define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< (AFEC0) AFEC Interrupt Enable Register */ +#define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< (AFEC0) AFEC Interrupt Disable Register */ +#define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Register */ +#define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< (AFEC0) AFEC Interrupt Status Register */ +#define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< (AFEC0) AFEC Overrun Status Register */ +#define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< (AFEC0) AFEC Compare Window Register */ +#define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< (AFEC0) AFEC Channel Gain Register */ +#define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< (AFEC0) AFEC Channel Differential Register */ +#define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< (AFEC0) AFEC Channel Selection Register */ +#define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< (AFEC0) AFEC Channel Data Register */ +#define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< (AFEC0) AFEC Channel Offset Compensation Register */ +#define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< (AFEC0) AFEC Temperature Sensor Mode Register */ +#define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< (AFEC0) AFEC Temperature Compare Window Register */ +#define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< (AFEC0) AFEC Analog Control Register */ +#define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode Register */ +#define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< (AFEC0) AFEC Correction Select Register */ +#define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< (AFEC0) AFEC Correction Values Register */ +#define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< (AFEC0) AFEC Channel Error Correction Register */ +#define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< (AFEC0) AFEC Write Protection Mode Register */ +#define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< (AFEC0) AFEC Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for AFEC0 peripheral ========== */ +#define AFEC0_DMAC_ID_RX 35 +#define AFEC0_INSTANCE_ID 29 +#define AFEC0_CLOCK_ID 29 +#define AFEC0_TRGSEL_AFEC_TRIG0 0x0 /* External ADC Trigger Input (AFE0_ADTRG pin) */ +#define AFEC0_TRGSEL_AFEC_TRIG1 0x1 /* TC0 Channel 0 Output (TIOA0) */ +#define AFEC0_TRGSEL_AFEC_TRIG2 0x2 /* TC0 Channel 1 Output (TIOA1) */ +#define AFEC0_TRGSEL_AFEC_TRIG3 0x3 /* TC0 Channel 2 Output (TIOA2) */ +#define AFEC0_TRGSEL_AFEC_TRIG4 0x4 /* PWM0 event line 0 */ +#define AFEC0_TRGSEL_AFEC_TRIG5 0x5 /* PWM0 event line 1 */ +#define AFEC0_TRGSEL_AFEC_TRIG6 0x6 /* Analog Comparator Fault Output */ + +#endif /* _SAME70_AFEC0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/afec1.h b/bsp/microchip/same70/bsp/same70b/include/instance/afec1.h new file mode 100644 index 0000000000..950e661f06 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/afec1.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief Instance description for AFEC1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_AFEC1_INSTANCE_H_ +#define _SAME70_AFEC1_INSTANCE_H_ + +/* ========== Register definition for AFEC1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_AFEC1_CR (0x40064000) /**< (AFEC1) AFEC Control Register */ +#define REG_AFEC1_MR (0x40064004) /**< (AFEC1) AFEC Mode Register */ +#define REG_AFEC1_EMR (0x40064008) /**< (AFEC1) AFEC Extended Mode Register */ +#define REG_AFEC1_SEQ1R (0x4006400C) /**< (AFEC1) AFEC Channel Sequence 1 Register */ +#define REG_AFEC1_SEQ2R (0x40064010) /**< (AFEC1) AFEC Channel Sequence 2 Register */ +#define REG_AFEC1_CHER (0x40064014) /**< (AFEC1) AFEC Channel Enable Register */ +#define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */ +#define REG_AFEC1_CHSR (0x4006401C) /**< (AFEC1) AFEC Channel Status Register */ +#define REG_AFEC1_LCDR (0x40064020) /**< (AFEC1) AFEC Last Converted Data Register */ +#define REG_AFEC1_IER (0x40064024) /**< (AFEC1) AFEC Interrupt Enable Register */ +#define REG_AFEC1_IDR (0x40064028) /**< (AFEC1) AFEC Interrupt Disable Register */ +#define REG_AFEC1_IMR (0x4006402C) /**< (AFEC1) AFEC Interrupt Mask Register */ +#define REG_AFEC1_ISR (0x40064030) /**< (AFEC1) AFEC Interrupt Status Register */ +#define REG_AFEC1_OVER (0x4006404C) /**< (AFEC1) AFEC Overrun Status Register */ +#define REG_AFEC1_CWR (0x40064050) /**< (AFEC1) AFEC Compare Window Register */ +#define REG_AFEC1_CGR (0x40064054) /**< (AFEC1) AFEC Channel Gain Register */ +#define REG_AFEC1_DIFFR (0x40064060) /**< (AFEC1) AFEC Channel Differential Register */ +#define REG_AFEC1_CSELR (0x40064064) /**< (AFEC1) AFEC Channel Selection Register */ +#define REG_AFEC1_CDR (0x40064068) /**< (AFEC1) AFEC Channel Data Register */ +#define REG_AFEC1_COCR (0x4006406C) /**< (AFEC1) AFEC Channel Offset Compensation Register */ +#define REG_AFEC1_TEMPMR (0x40064070) /**< (AFEC1) AFEC Temperature Sensor Mode Register */ +#define REG_AFEC1_TEMPCWR (0x40064074) /**< (AFEC1) AFEC Temperature Compare Window Register */ +#define REG_AFEC1_ACR (0x40064094) /**< (AFEC1) AFEC Analog Control Register */ +#define REG_AFEC1_SHMR (0x400640A0) /**< (AFEC1) AFEC Sample & Hold Mode Register */ +#define REG_AFEC1_COSR (0x400640D0) /**< (AFEC1) AFEC Correction Select Register */ +#define REG_AFEC1_CVR (0x400640D4) /**< (AFEC1) AFEC Correction Values Register */ +#define REG_AFEC1_CECR (0x400640D8) /**< (AFEC1) AFEC Channel Error Correction Register */ +#define REG_AFEC1_WPMR (0x400640E4) /**< (AFEC1) AFEC Write Protection Mode Register */ +#define REG_AFEC1_WPSR (0x400640E8) /**< (AFEC1) AFEC Write Protection Status Register */ + +#else + +#define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< (AFEC1) AFEC Control Register */ +#define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< (AFEC1) AFEC Mode Register */ +#define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< (AFEC1) AFEC Extended Mode Register */ +#define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< (AFEC1) AFEC Channel Sequence 1 Register */ +#define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< (AFEC1) AFEC Channel Sequence 2 Register */ +#define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< (AFEC1) AFEC Channel Enable Register */ +#define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Register */ +#define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< (AFEC1) AFEC Channel Status Register */ +#define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< (AFEC1) AFEC Last Converted Data Register */ +#define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< (AFEC1) AFEC Interrupt Enable Register */ +#define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< (AFEC1) AFEC Interrupt Disable Register */ +#define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< (AFEC1) AFEC Interrupt Mask Register */ +#define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< (AFEC1) AFEC Interrupt Status Register */ +#define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< (AFEC1) AFEC Overrun Status Register */ +#define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< (AFEC1) AFEC Compare Window Register */ +#define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< (AFEC1) AFEC Channel Gain Register */ +#define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< (AFEC1) AFEC Channel Differential Register */ +#define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< (AFEC1) AFEC Channel Selection Register */ +#define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< (AFEC1) AFEC Channel Data Register */ +#define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< (AFEC1) AFEC Channel Offset Compensation Register */ +#define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< (AFEC1) AFEC Temperature Sensor Mode Register */ +#define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< (AFEC1) AFEC Temperature Compare Window Register */ +#define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< (AFEC1) AFEC Analog Control Register */ +#define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< (AFEC1) AFEC Sample & Hold Mode Register */ +#define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< (AFEC1) AFEC Correction Select Register */ +#define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< (AFEC1) AFEC Correction Values Register */ +#define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< (AFEC1) AFEC Channel Error Correction Register */ +#define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< (AFEC1) AFEC Write Protection Mode Register */ +#define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< (AFEC1) AFEC Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for AFEC1 peripheral ========== */ +#define AFEC1_DMAC_ID_RX 36 +#define AFEC1_INSTANCE_ID 40 +#define AFEC1_CLOCK_ID 40 +#define AFEC1_TRGSEL_AFEC_TRIG0 0x0 /* External ADC Trigger Input (AFE1_ADTRG Pin) */ +#define AFEC1_TRGSEL_AFEC_TRIG1 0x1 /* TC1 Channel 0 Output (TIOA3) */ +#define AFEC1_TRGSEL_AFEC_TRIG2 0x2 /* TC1 Channel 1 Output (TIOA4) */ +#define AFEC1_TRGSEL_AFEC_TRIG3 0x3 /* TC1 Channel 2 Output (TIOA5) */ +#define AFEC1_TRGSEL_AFEC_TRIG4 0x4 /* PWM1 event line 0 */ +#define AFEC1_TRGSEL_AFEC_TRIG5 0x5 /* PWM1 event line 1 */ +#define AFEC1_TRGSEL_AFEC_TRIG6 0x6 /* Analog Comparator Fault Output */ + +#endif /* _SAME70_AFEC1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/chipid.h b/bsp/microchip/same70/bsp/same70b/include/instance/chipid.h new file mode 100644 index 0000000000..43786187a6 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/chipid.h @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Instance description for CHIPID + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_CHIPID_INSTANCE_H_ +#define _SAME70_CHIPID_INSTANCE_H_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_CHIPID_CIDR (0x400E0940) /**< (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (0x400E0944) /**< (CHIPID) Chip ID Extension Register */ + +#else + +#define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< (CHIPID) Chip ID Extension Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_CHIPID_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/dacc.h b/bsp/microchip/same70/bsp/same70b/include/instance/dacc.h new file mode 100644 index 0000000000..6741fd6b87 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/dacc.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Instance description for DACC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_DACC_INSTANCE_H_ +#define _SAME70_DACC_INSTANCE_H_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_DACC_CR (0x40040000) /**< (DACC) Control Register */ +#define REG_DACC_MR (0x40040004) /**< (DACC) Mode Register */ +#define REG_DACC_TRIGR (0x40040008) /**< (DACC) Trigger Register */ +#define REG_DACC_CHER (0x40040010) /**< (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (0x40040014) /**< (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (0x40040018) /**< (DACC) Channel Status Register */ +#define REG_DACC_CDR (0x4004001C) /**< (DACC) Conversion Data Register 0 */ +#define REG_DACC_CDR0 (0x4004001C) /**< (DACC) Conversion Data Register 0 */ +#define REG_DACC_CDR1 (0x40040020) /**< (DACC) Conversion Data Register 1 */ +#define REG_DACC_IER (0x40040024) /**< (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (0x40040028) /**< (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (0x4004002C) /**< (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (0x40040030) /**< (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (0x40040094) /**< (DACC) Analog Current Register */ +#define REG_DACC_WPMR (0x400400E4) /**< (DACC) Write Protection Mode Register */ +#define REG_DACC_WPSR (0x400400E8) /**< (DACC) Write Protection Status Register */ + +#else + +#define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< (DACC) Control Register */ +#define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< (DACC) Mode Register */ +#define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< (DACC) Trigger Register */ +#define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< (DACC) Channel Status Register */ +#define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */ +#define REG_DACC_CDR0 (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */ +#define REG_DACC_CDR1 (*(__O uint32_t*)0x40040020U) /**< (DACC) Conversion Data Register 1 */ +#define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< (DACC) Analog Current Register */ +#define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< (DACC) Write Protection Mode Register */ +#define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< (DACC) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for DACC peripheral ========== */ +#define DACC_DMAC_ID_TX 30 +#define DACC_INSTANCE_ID 30 +#define DACC_CLOCK_ID 30 + +#endif /* _SAME70_DACC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/efc.h b/bsp/microchip/same70/bsp/same70b/include/instance/efc.h new file mode 100644 index 0000000000..475d470f8a --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/efc.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for EFC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_EFC_INSTANCE_H_ +#define _SAME70_EFC_INSTANCE_H_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_EEFC_FMR (0x400E0C00) /**< (EFC) EEFC Flash Mode Register */ +#define REG_EEFC_FCR (0x400E0C04) /**< (EFC) EEFC Flash Command Register */ +#define REG_EEFC_FSR (0x400E0C08) /**< (EFC) EEFC Flash Status Register */ +#define REG_EEFC_FRR (0x400E0C0C) /**< (EFC) EEFC Flash Result Register */ +#define REG_EEFC_WPMR (0x400E0CE4) /**< (EFC) Write Protection Mode Register */ + +#else + +#define REG_EEFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< (EFC) EEFC Flash Mode Register */ +#define REG_EEFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< (EFC) EEFC Flash Command Register */ +#define REG_EEFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< (EFC) EEFC Flash Status Register */ +#define REG_EEFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< (EFC) EEFC Flash Result Register */ +#define REG_EEFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< (EFC) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for EFC peripheral ========== */ +#define EFC_FLASH_SIZE 2097152 +#define EFC_PAGE_SIZE 512 +#define EFC_INSTANCE_ID 6 +#define EFC_PAGES_PR_REGION 32 + +#endif /* _SAME70_EFC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/gmac.h b/bsp/microchip/same70/bsp/same70b/include/instance/gmac.h new file mode 100644 index 0000000000..643839b882 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/gmac.h @@ -0,0 +1,489 @@ +/** + * \file + * + * \brief Instance description for GMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_GMAC_INSTANCE_H_ +#define _SAME70_GMAC_INSTANCE_H_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_GMAC_SAB1 (0x40050088) /**< (GMAC) Specific Address 1 Bottom Register 0 */ +#define REG_GMAC_SAT1 (0x4005008C) /**< (GMAC) Specific Address 1 Top Register 0 */ +#define REG_GMAC_SAB2 (0x40050090) /**< (GMAC) Specific Address 1 Bottom Register 1 */ +#define REG_GMAC_SAT2 (0x40050094) /**< (GMAC) Specific Address 1 Top Register 1 */ +#define REG_GMAC_SAB3 (0x40050098) /**< (GMAC) Specific Address 1 Bottom Register 2 */ +#define REG_GMAC_SAT3 (0x4005009C) /**< (GMAC) Specific Address 1 Top Register 2 */ +#define REG_GMAC_SAB4 (0x400500A0) /**< (GMAC) Specific Address 1 Bottom Register 3 */ +#define REG_GMAC_SAT4 (0x400500A4) /**< (GMAC) Specific Address 1 Top Register 3 */ +#define REG_GMAC_ST2CW00 (0x40050700) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */ +#define REG_GMAC_ST2CW10 (0x40050704) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */ +#define REG_GMAC_ST2CW01 (0x40050708) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */ +#define REG_GMAC_ST2CW11 (0x4005070C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */ +#define REG_GMAC_ST2CW02 (0x40050710) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */ +#define REG_GMAC_ST2CW12 (0x40050714) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */ +#define REG_GMAC_ST2CW03 (0x40050718) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */ +#define REG_GMAC_ST2CW13 (0x4005071C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */ +#define REG_GMAC_ST2CW04 (0x40050720) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */ +#define REG_GMAC_ST2CW14 (0x40050724) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */ +#define REG_GMAC_ST2CW05 (0x40050728) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */ +#define REG_GMAC_ST2CW15 (0x4005072C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */ +#define REG_GMAC_ST2CW06 (0x40050730) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */ +#define REG_GMAC_ST2CW16 (0x40050734) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */ +#define REG_GMAC_ST2CW07 (0x40050738) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */ +#define REG_GMAC_ST2CW17 (0x4005073C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */ +#define REG_GMAC_ST2CW08 (0x40050740) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */ +#define REG_GMAC_ST2CW18 (0x40050744) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */ +#define REG_GMAC_ST2CW09 (0x40050748) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */ +#define REG_GMAC_ST2CW19 (0x4005074C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */ +#define REG_GMAC_ST2CW010 (0x40050750) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */ +#define REG_GMAC_ST2CW110 (0x40050754) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */ +#define REG_GMAC_ST2CW011 (0x40050758) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */ +#define REG_GMAC_ST2CW111 (0x4005075C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */ +#define REG_GMAC_ST2CW012 (0x40050760) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */ +#define REG_GMAC_ST2CW112 (0x40050764) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */ +#define REG_GMAC_ST2CW013 (0x40050768) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */ +#define REG_GMAC_ST2CW113 (0x4005076C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */ +#define REG_GMAC_ST2CW014 (0x40050770) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */ +#define REG_GMAC_ST2CW114 (0x40050774) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */ +#define REG_GMAC_ST2CW015 (0x40050778) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */ +#define REG_GMAC_ST2CW115 (0x4005077C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */ +#define REG_GMAC_ST2CW016 (0x40050780) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */ +#define REG_GMAC_ST2CW116 (0x40050784) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */ +#define REG_GMAC_ST2CW017 (0x40050788) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */ +#define REG_GMAC_ST2CW117 (0x4005078C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */ +#define REG_GMAC_ST2CW018 (0x40050790) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */ +#define REG_GMAC_ST2CW118 (0x40050794) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */ +#define REG_GMAC_ST2CW019 (0x40050798) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */ +#define REG_GMAC_ST2CW119 (0x4005079C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */ +#define REG_GMAC_ST2CW020 (0x400507A0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */ +#define REG_GMAC_ST2CW120 (0x400507A4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */ +#define REG_GMAC_ST2CW021 (0x400507A8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */ +#define REG_GMAC_ST2CW121 (0x400507AC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */ +#define REG_GMAC_ST2CW022 (0x400507B0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */ +#define REG_GMAC_ST2CW122 (0x400507B4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */ +#define REG_GMAC_ST2CW023 (0x400507B8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */ +#define REG_GMAC_ST2CW123 (0x400507BC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */ +#define REG_GMAC_NCR (0x40050000) /**< (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (0x40050004) /**< (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (0x40050008) /**< (GMAC) Network Status Register */ +#define REG_GMAC_UR (0x4005000C) /**< (GMAC) User Register */ +#define REG_GMAC_DCFGR (0x40050010) /**< (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (0x40050014) /**< (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (0x40050018) /**< (GMAC) Receive Buffer Queue Base Address Register */ +#define REG_GMAC_TBQB (0x4005001C) /**< (GMAC) Transmit Buffer Queue Base Address Register */ +#define REG_GMAC_RSR (0x40050020) /**< (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (0x40050024) /**< (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (0x40050028) /**< (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (0x4005002C) /**< (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (0x40050030) /**< (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (0x40050034) /**< (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (0x40050038) /**< (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (0x4005003C) /**< (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (0x40050040) /**< (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (0x40050044) /**< (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_RJFML (0x40050048) /**< (GMAC) RX Jumbo Frame Max Length Register */ +#define REG_GMAC_HRB (0x40050080) /**< (GMAC) Hash Register Bottom */ +#define REG_GMAC_HRT (0x40050084) /**< (GMAC) Hash Register Top */ +#define REG_GMAC_TIDM1 (0x400500A8) /**< (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_TIDM2 (0x400500AC) /**< (GMAC) Type ID Match 2 Register */ +#define REG_GMAC_TIDM3 (0x400500B0) /**< (GMAC) Type ID Match 3 Register */ +#define REG_GMAC_TIDM4 (0x400500B4) /**< (GMAC) Type ID Match 4 Register */ +#define REG_GMAC_WOL (0x400500B8) /**< (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (0x400500BC) /**< (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (0x400500C0) /**< (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (0x400500C4) /**< (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (0x400500C8) /**< (GMAC) Specific Address 1 Mask Bottom Register */ +#define REG_GMAC_SAMT1 (0x400500CC) /**< (GMAC) Specific Address 1 Mask Top Register */ +#define REG_GMAC_NSC (0x400500DC) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */ +#define REG_GMAC_SCL (0x400500E0) /**< (GMAC) 1588 Timer Second Comparison Low Register */ +#define REG_GMAC_SCH (0x400500E4) /**< (GMAC) 1588 Timer Second Comparison High Register */ +#define REG_GMAC_EFTSH (0x400500E8) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */ +#define REG_GMAC_EFRSH (0x400500EC) /**< (GMAC) PTP Event Frame Received Seconds High Register */ +#define REG_GMAC_PEFTSH (0x400500F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ +#define REG_GMAC_PEFRSH (0x400500F4) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */ +#define REG_GMAC_OTLO (0x40050100) /**< (GMAC) Octets Transmitted Low Register */ +#define REG_GMAC_OTHI (0x40050104) /**< (GMAC) Octets Transmitted High Register */ +#define REG_GMAC_FT (0x40050108) /**< (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (0x4005010C) /**< (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (0x40050110) /**< (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (0x40050114) /**< (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (0x40050118) /**< (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (0x4005011C) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (0x40050120) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (0x40050124) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (0x40050128) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (0x4005012C) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (0x40050130) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (0x40050134) /**< (GMAC) Transmit Underruns Register */ +#define REG_GMAC_SCF (0x40050138) /**< (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (0x4005013C) /**< (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (0x40050140) /**< (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (0x40050144) /**< (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (0x40050148) /**< (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (0x4005014C) /**< (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (0x40050150) /**< (GMAC) Octets Received Low Received Register */ +#define REG_GMAC_ORHI (0x40050154) /**< (GMAC) Octets Received High Received Register */ +#define REG_GMAC_FR (0x40050158) /**< (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (0x4005015C) /**< (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (0x40050160) /**< (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (0x40050164) /**< (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (0x40050168) /**< (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (0x4005016C) /**< (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (0x40050170) /**< (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (0x40050174) /**< (GMAC) 256 to 511 Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (0x40050178) /**< (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (0x4005017C) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (0x40050180) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (0x40050184) /**< (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (0x40050188) /**< (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (0x4005018C) /**< (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (0x40050190) /**< (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (0x40050194) /**< (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (0x40050198) /**< (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (0x4005019C) /**< (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (0x400501A0) /**< (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (0x400501A4) /**< (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (0x400501A8) /**< (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (0x400501AC) /**< (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (0x400501B0) /**< (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TISUBN (0x400501BC) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ +#define REG_GMAC_TSH (0x400501C0) /**< (GMAC) 1588 Timer Seconds High Register */ +#define REG_GMAC_TSL (0x400501D0) /**< (GMAC) 1588 Timer Seconds Low Register */ +#define REG_GMAC_TN (0x400501D4) /**< (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (0x400501D8) /**< (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (0x400501DC) /**< (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTSL (0x400501E0) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */ +#define REG_GMAC_EFTN (0x400501E4) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ +#define REG_GMAC_EFRSL (0x400501E8) /**< (GMAC) PTP Event Frame Received Seconds Low Register */ +#define REG_GMAC_EFRN (0x400501EC) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */ +#define REG_GMAC_PEFTSL (0x400501F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ +#define REG_GMAC_PEFTN (0x400501F4) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ +#define REG_GMAC_PEFRSL (0x400501F8) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */ +#define REG_GMAC_PEFRN (0x400501FC) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ +#define REG_GMAC_RXLPI (0x40050270) /**< (GMAC) Received LPI Transitions */ +#define REG_GMAC_RXLPITIME (0x40050274) /**< (GMAC) Received LPI Time */ +#define REG_GMAC_TXLPI (0x40050278) /**< (GMAC) Transmit LPI Transitions */ +#define REG_GMAC_TXLPITIME (0x4005027C) /**< (GMAC) Transmit LPI Time */ +#define REG_GMAC_ISRPQ (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */ +#define REG_GMAC_ISRPQ0 (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */ +#define REG_GMAC_ISRPQ1 (0x40050404) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */ +#define REG_GMAC_ISRPQ2 (0x40050408) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */ +#define REG_GMAC_ISRPQ3 (0x4005040C) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */ +#define REG_GMAC_ISRPQ4 (0x40050410) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */ +#define REG_GMAC_TBQBAPQ (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ +#define REG_GMAC_TBQBAPQ0 (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */ +#define REG_GMAC_TBQBAPQ1 (0x40050444) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */ +#define REG_GMAC_TBQBAPQ2 (0x40050448) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */ +#define REG_GMAC_TBQBAPQ3 (0x4005044C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */ +#define REG_GMAC_TBQBAPQ4 (0x40050450) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */ +#define REG_GMAC_RBQBAPQ (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ +#define REG_GMAC_RBQBAPQ0 (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */ +#define REG_GMAC_RBQBAPQ1 (0x40050484) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */ +#define REG_GMAC_RBQBAPQ2 (0x40050488) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */ +#define REG_GMAC_RBQBAPQ3 (0x4005048C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */ +#define REG_GMAC_RBQBAPQ4 (0x40050490) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */ +#define REG_GMAC_RBSRPQ (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */ +#define REG_GMAC_RBSRPQ0 (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */ +#define REG_GMAC_RBSRPQ1 (0x400504A4) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */ +#define REG_GMAC_RBSRPQ2 (0x400504A8) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */ +#define REG_GMAC_RBSRPQ3 (0x400504AC) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */ +#define REG_GMAC_RBSRPQ4 (0x400504B0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */ +#define REG_GMAC_CBSCR (0x400504BC) /**< (GMAC) Credit-Based Shaping Control Register */ +#define REG_GMAC_CBSISQA (0x400504C0) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ +#define REG_GMAC_CBSISQB (0x400504C4) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ +#define REG_GMAC_ST1RPQ (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue */ +#define REG_GMAC_ST1RPQ0 (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */ +#define REG_GMAC_ST1RPQ1 (0x40050504) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */ +#define REG_GMAC_ST1RPQ2 (0x40050508) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */ +#define REG_GMAC_ST1RPQ3 (0x4005050C) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */ +#define REG_GMAC_ST2RPQ (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue */ +#define REG_GMAC_ST2RPQ0 (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */ +#define REG_GMAC_ST2RPQ1 (0x40050544) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */ +#define REG_GMAC_ST2RPQ2 (0x40050548) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */ +#define REG_GMAC_ST2RPQ3 (0x4005054C) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */ +#define REG_GMAC_ST2RPQ4 (0x40050550) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */ +#define REG_GMAC_ST2RPQ5 (0x40050554) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */ +#define REG_GMAC_ST2RPQ6 (0x40050558) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */ +#define REG_GMAC_ST2RPQ7 (0x4005055C) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */ +#define REG_GMAC_IERPQ (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */ +#define REG_GMAC_IERPQ0 (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IERPQ1 (0x40050604) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IERPQ2 (0x40050608) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IERPQ3 (0x4005060C) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IERPQ4 (0x40050610) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */ +#define REG_GMAC_IDRPQ (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */ +#define REG_GMAC_IDRPQ0 (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IDRPQ1 (0x40050624) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IDRPQ2 (0x40050628) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IDRPQ3 (0x4005062C) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IDRPQ4 (0x40050630) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */ +#define REG_GMAC_IMRPQ (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */ +#define REG_GMAC_IMRPQ0 (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IMRPQ1 (0x40050644) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IMRPQ2 (0x40050648) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IMRPQ3 (0x4005064C) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IMRPQ4 (0x40050650) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */ +#define REG_GMAC_ST2ER (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register */ +#define REG_GMAC_ST2ER0 (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register 0 */ +#define REG_GMAC_ST2ER1 (0x400506E4) /**< (GMAC) Screening Type 2 Ethertype Register 1 */ +#define REG_GMAC_ST2ER2 (0x400506E8) /**< (GMAC) Screening Type 2 Ethertype Register 2 */ +#define REG_GMAC_ST2ER3 (0x400506EC) /**< (GMAC) Screening Type 2 Ethertype Register 3 */ + +#else + +#define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< (GMAC) Specific Address 1 Bottom Register 0 */ +#define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< (GMAC) Specific Address 1 Top Register 0 */ +#define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< (GMAC) Specific Address 1 Bottom Register 1 */ +#define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< (GMAC) Specific Address 1 Top Register 1 */ +#define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< (GMAC) Specific Address 1 Bottom Register 2 */ +#define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< (GMAC) Specific Address 1 Top Register 2 */ +#define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< (GMAC) Specific Address 1 Bottom Register 3 */ +#define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< (GMAC) Specific Address 1 Top Register 3 */ +#define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */ +#define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */ +#define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */ +#define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */ +#define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */ +#define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */ +#define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */ +#define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */ +#define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */ +#define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */ +#define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */ +#define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */ +#define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */ +#define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */ +#define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */ +#define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */ +#define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */ +#define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */ +#define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */ +#define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */ +#define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */ +#define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */ +#define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */ +#define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */ +#define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */ +#define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */ +#define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */ +#define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */ +#define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */ +#define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */ +#define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */ +#define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */ +#define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */ +#define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */ +#define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */ +#define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */ +#define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */ +#define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */ +#define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */ +#define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */ +#define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */ +#define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */ +#define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */ +#define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */ +#define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */ +#define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */ +#define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */ +#define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */ +#define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< (GMAC) Network Status Register */ +#define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< (GMAC) User Register */ +#define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< (GMAC) Receive Buffer Queue Base Address Register */ +#define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< (GMAC) Transmit Buffer Queue Base Address Register */ +#define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< (GMAC) RX Jumbo Frame Max Length Register */ +#define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< (GMAC) Hash Register Bottom */ +#define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< (GMAC) Hash Register Top */ +#define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< (GMAC) Type ID Match 2 Register */ +#define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< (GMAC) Type ID Match 3 Register */ +#define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< (GMAC) Type ID Match 4 Register */ +#define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< (GMAC) Specific Address 1 Mask Bottom Register */ +#define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< (GMAC) Specific Address 1 Mask Top Register */ +#define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */ +#define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< (GMAC) 1588 Timer Second Comparison Low Register */ +#define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< (GMAC) 1588 Timer Second Comparison High Register */ +#define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */ +#define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< (GMAC) PTP Event Frame Received Seconds High Register */ +#define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ +#define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */ +#define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< (GMAC) Octets Transmitted Low Register */ +#define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< (GMAC) Octets Transmitted High Register */ +#define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< (GMAC) Transmit Underruns Register */ +#define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< (GMAC) Octets Received Low Received Register */ +#define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< (GMAC) Octets Received High Received Register */ +#define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< (GMAC) 256 to 511 Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ +#define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< (GMAC) 1588 Timer Seconds High Register */ +#define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< (GMAC) 1588 Timer Seconds Low Register */ +#define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */ +#define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ +#define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< (GMAC) PTP Event Frame Received Seconds Low Register */ +#define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */ +#define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ +#define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ +#define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */ +#define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ +#define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< (GMAC) Received LPI Transitions */ +#define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< (GMAC) Received LPI Time */ +#define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< (GMAC) Transmit LPI Transitions */ +#define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< (GMAC) Transmit LPI Time */ +#define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */ +#define REG_GMAC_ISRPQ0 (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */ +#define REG_GMAC_ISRPQ1 (*(__I uint32_t*)0x40050404U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */ +#define REG_GMAC_ISRPQ2 (*(__I uint32_t*)0x40050408U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */ +#define REG_GMAC_ISRPQ3 (*(__I uint32_t*)0x4005040CU) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */ +#define REG_GMAC_ISRPQ4 (*(__I uint32_t*)0x40050410U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */ +#define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ +#define REG_GMAC_TBQBAPQ0 (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */ +#define REG_GMAC_TBQBAPQ1 (*(__IO uint32_t*)0x40050444U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */ +#define REG_GMAC_TBQBAPQ2 (*(__IO uint32_t*)0x40050448U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */ +#define REG_GMAC_TBQBAPQ3 (*(__IO uint32_t*)0x4005044CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */ +#define REG_GMAC_TBQBAPQ4 (*(__IO uint32_t*)0x40050450U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */ +#define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ +#define REG_GMAC_RBQBAPQ0 (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */ +#define REG_GMAC_RBQBAPQ1 (*(__IO uint32_t*)0x40050484U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */ +#define REG_GMAC_RBQBAPQ2 (*(__IO uint32_t*)0x40050488U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */ +#define REG_GMAC_RBQBAPQ3 (*(__IO uint32_t*)0x4005048CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */ +#define REG_GMAC_RBQBAPQ4 (*(__IO uint32_t*)0x40050490U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */ +#define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */ +#define REG_GMAC_RBSRPQ0 (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */ +#define REG_GMAC_RBSRPQ1 (*(__IO uint32_t*)0x400504A4U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */ +#define REG_GMAC_RBSRPQ2 (*(__IO uint32_t*)0x400504A8U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */ +#define REG_GMAC_RBSRPQ3 (*(__IO uint32_t*)0x400504ACU) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */ +#define REG_GMAC_RBSRPQ4 (*(__IO uint32_t*)0x400504B0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */ +#define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< (GMAC) Credit-Based Shaping Control Register */ +#define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ +#define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ +#define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue */ +#define REG_GMAC_ST1RPQ0 (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */ +#define REG_GMAC_ST1RPQ1 (*(__IO uint32_t*)0x40050504U) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */ +#define REG_GMAC_ST1RPQ2 (*(__IO uint32_t*)0x40050508U) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */ +#define REG_GMAC_ST1RPQ3 (*(__IO uint32_t*)0x4005050CU) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */ +#define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue */ +#define REG_GMAC_ST2RPQ0 (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */ +#define REG_GMAC_ST2RPQ1 (*(__IO uint32_t*)0x40050544U) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */ +#define REG_GMAC_ST2RPQ2 (*(__IO uint32_t*)0x40050548U) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */ +#define REG_GMAC_ST2RPQ3 (*(__IO uint32_t*)0x4005054CU) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */ +#define REG_GMAC_ST2RPQ4 (*(__IO uint32_t*)0x40050550U) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */ +#define REG_GMAC_ST2RPQ5 (*(__IO uint32_t*)0x40050554U) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */ +#define REG_GMAC_ST2RPQ6 (*(__IO uint32_t*)0x40050558U) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */ +#define REG_GMAC_ST2RPQ7 (*(__IO uint32_t*)0x4005055CU) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */ +#define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */ +#define REG_GMAC_IERPQ0 (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IERPQ1 (*(__O uint32_t*)0x40050604U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IERPQ2 (*(__O uint32_t*)0x40050608U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IERPQ3 (*(__O uint32_t*)0x4005060CU) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IERPQ4 (*(__O uint32_t*)0x40050610U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */ +#define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */ +#define REG_GMAC_IDRPQ0 (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IDRPQ1 (*(__O uint32_t*)0x40050624U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IDRPQ2 (*(__O uint32_t*)0x40050628U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IDRPQ3 (*(__O uint32_t*)0x4005062CU) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IDRPQ4 (*(__O uint32_t*)0x40050630U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */ +#define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */ +#define REG_GMAC_IMRPQ0 (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */ +#define REG_GMAC_IMRPQ1 (*(__IO uint32_t*)0x40050644U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */ +#define REG_GMAC_IMRPQ2 (*(__IO uint32_t*)0x40050648U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */ +#define REG_GMAC_IMRPQ3 (*(__IO uint32_t*)0x4005064CU) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */ +#define REG_GMAC_IMRPQ4 (*(__IO uint32_t*)0x40050650U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */ +#define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register */ +#define REG_GMAC_ST2ER0 (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register 0 */ +#define REG_GMAC_ST2ER1 (*(__IO uint32_t*)0x400506E4U) /**< (GMAC) Screening Type 2 Ethertype Register 1 */ +#define REG_GMAC_ST2ER2 (*(__IO uint32_t*)0x400506E8U) /**< (GMAC) Screening Type 2 Ethertype Register 2 */ +#define REG_GMAC_ST2ER3 (*(__IO uint32_t*)0x400506ECU) /**< (GMAC) Screening Type 2 Ethertype Register 3 */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for GMAC peripheral ========== */ +#define GMAC_INSTANCE_ID 39 +#define GMAC_CLOCK_ID 39 + +#endif /* _SAME70_GMAC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/gpbr.h b/bsp/microchip/same70/bsp/same70b/include/instance/gpbr.h new file mode 100644 index 0000000000..01402ec9d4 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/gpbr.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Instance description for GPBR + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_GPBR_INSTANCE_H_ +#define _SAME70_GPBR_INSTANCE_H_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_GPBR_SYS_GPBR (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_SYS_GPBR0 (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_SYS_GPBR1 (0x400E1894) /**< (GPBR) General Purpose Backup Register 1 */ +#define REG_GPBR_SYS_GPBR2 (0x400E1898) /**< (GPBR) General Purpose Backup Register 2 */ +#define REG_GPBR_SYS_GPBR3 (0x400E189C) /**< (GPBR) General Purpose Backup Register 3 */ +#define REG_GPBR_SYS_GPBR4 (0x400E18A0) /**< (GPBR) General Purpose Backup Register 4 */ +#define REG_GPBR_SYS_GPBR5 (0x400E18A4) /**< (GPBR) General Purpose Backup Register 5 */ +#define REG_GPBR_SYS_GPBR6 (0x400E18A8) /**< (GPBR) General Purpose Backup Register 6 */ +#define REG_GPBR_SYS_GPBR7 (0x400E18AC) /**< (GPBR) General Purpose Backup Register 7 */ + +#else + +#define REG_GPBR_SYS_GPBR (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_SYS_GPBR0 (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */ +#define REG_GPBR_SYS_GPBR1 (*(__IO uint32_t*)0x400E1894U) /**< (GPBR) General Purpose Backup Register 1 */ +#define REG_GPBR_SYS_GPBR2 (*(__IO uint32_t*)0x400E1898U) /**< (GPBR) General Purpose Backup Register 2 */ +#define REG_GPBR_SYS_GPBR3 (*(__IO uint32_t*)0x400E189CU) /**< (GPBR) General Purpose Backup Register 3 */ +#define REG_GPBR_SYS_GPBR4 (*(__IO uint32_t*)0x400E18A0U) /**< (GPBR) General Purpose Backup Register 4 */ +#define REG_GPBR_SYS_GPBR5 (*(__IO uint32_t*)0x400E18A4U) /**< (GPBR) General Purpose Backup Register 5 */ +#define REG_GPBR_SYS_GPBR6 (*(__IO uint32_t*)0x400E18A8U) /**< (GPBR) General Purpose Backup Register 6 */ +#define REG_GPBR_SYS_GPBR7 (*(__IO uint32_t*)0x400E18ACU) /**< (GPBR) General Purpose Backup Register 7 */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_GPBR_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/hsmci.h b/bsp/microchip/same70/bsp/same70b/include/instance/hsmci.h new file mode 100644 index 0000000000..e245da6029 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/hsmci.h @@ -0,0 +1,609 @@ +/** + * \file + * + * \brief Instance description for HSMCI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_HSMCI_INSTANCE_H_ +#define _SAME70_HSMCI_INSTANCE_H_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_HSMCI_CR (0x40000000) /**< (HSMCI) Control Register */ +#define REG_HSMCI_MR (0x40000004) /**< (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (0x40000008) /**< (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (0x4000000C) /**< (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (0x40000010) /**< (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (0x40000014) /**< (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (0x40000018) /**< (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (0x4000001C) /**< (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (0x40000020) /**< (HSMCI) Response Register 0 */ +#define REG_HSMCI_RSPR0 (0x40000020) /**< (HSMCI) Response Register 0 */ +#define REG_HSMCI_RSPR1 (0x40000024) /**< (HSMCI) Response Register 1 */ +#define REG_HSMCI_RSPR2 (0x40000028) /**< (HSMCI) Response Register 2 */ +#define REG_HSMCI_RSPR3 (0x4000002C) /**< (HSMCI) Response Register 3 */ +#define REG_HSMCI_RDR (0x40000030) /**< (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (0x40000034) /**< (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (0x40000040) /**< (HSMCI) Status Register */ +#define REG_HSMCI_IER (0x40000044) /**< (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (0x40000048) /**< (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (0x4000004C) /**< (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (0x40000050) /**< (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (0x40000054) /**< (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (0x400000E4) /**< (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (0x400000E8) /**< (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */ +#define REG_HSMCI_FIFO0 (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */ +#define REG_HSMCI_FIFO1 (0x40000204) /**< (HSMCI) FIFO Memory Aperture0 1 */ +#define REG_HSMCI_FIFO2 (0x40000208) /**< (HSMCI) FIFO Memory Aperture0 2 */ +#define REG_HSMCI_FIFO3 (0x4000020C) /**< (HSMCI) FIFO Memory Aperture0 3 */ +#define REG_HSMCI_FIFO4 (0x40000210) /**< (HSMCI) FIFO Memory Aperture0 4 */ +#define REG_HSMCI_FIFO5 (0x40000214) /**< (HSMCI) FIFO Memory Aperture0 5 */ +#define REG_HSMCI_FIFO6 (0x40000218) /**< (HSMCI) FIFO Memory Aperture0 6 */ +#define REG_HSMCI_FIFO7 (0x4000021C) /**< (HSMCI) FIFO Memory Aperture0 7 */ +#define REG_HSMCI_FIFO8 (0x40000220) /**< (HSMCI) FIFO Memory Aperture0 8 */ +#define REG_HSMCI_FIFO9 (0x40000224) /**< (HSMCI) FIFO Memory Aperture0 9 */ +#define REG_HSMCI_FIFO10 (0x40000228) /**< (HSMCI) FIFO Memory Aperture0 10 */ +#define REG_HSMCI_FIFO11 (0x4000022C) /**< (HSMCI) FIFO Memory Aperture0 11 */ +#define REG_HSMCI_FIFO12 (0x40000230) /**< (HSMCI) FIFO Memory Aperture0 12 */ +#define REG_HSMCI_FIFO13 (0x40000234) /**< (HSMCI) FIFO Memory Aperture0 13 */ +#define REG_HSMCI_FIFO14 (0x40000238) /**< (HSMCI) FIFO Memory Aperture0 14 */ +#define REG_HSMCI_FIFO15 (0x4000023C) /**< (HSMCI) FIFO Memory Aperture0 15 */ +#define REG_HSMCI_FIFO16 (0x40000240) /**< (HSMCI) FIFO Memory Aperture0 16 */ +#define REG_HSMCI_FIFO17 (0x40000244) /**< (HSMCI) FIFO Memory Aperture0 17 */ +#define REG_HSMCI_FIFO18 (0x40000248) /**< (HSMCI) FIFO Memory Aperture0 18 */ +#define REG_HSMCI_FIFO19 (0x4000024C) /**< (HSMCI) FIFO Memory Aperture0 19 */ +#define REG_HSMCI_FIFO20 (0x40000250) /**< (HSMCI) FIFO Memory Aperture0 20 */ +#define REG_HSMCI_FIFO21 (0x40000254) /**< (HSMCI) FIFO Memory Aperture0 21 */ +#define REG_HSMCI_FIFO22 (0x40000258) /**< (HSMCI) FIFO Memory Aperture0 22 */ +#define REG_HSMCI_FIFO23 (0x4000025C) /**< (HSMCI) FIFO Memory Aperture0 23 */ +#define REG_HSMCI_FIFO24 (0x40000260) /**< (HSMCI) FIFO Memory Aperture0 24 */ +#define REG_HSMCI_FIFO25 (0x40000264) /**< (HSMCI) FIFO Memory Aperture0 25 */ +#define REG_HSMCI_FIFO26 (0x40000268) /**< (HSMCI) FIFO Memory Aperture0 26 */ +#define REG_HSMCI_FIFO27 (0x4000026C) /**< (HSMCI) FIFO Memory Aperture0 27 */ +#define REG_HSMCI_FIFO28 (0x40000270) /**< (HSMCI) FIFO Memory Aperture0 28 */ +#define REG_HSMCI_FIFO29 (0x40000274) /**< (HSMCI) FIFO Memory Aperture0 29 */ +#define REG_HSMCI_FIFO30 (0x40000278) /**< (HSMCI) FIFO Memory Aperture0 30 */ +#define REG_HSMCI_FIFO31 (0x4000027C) /**< (HSMCI) FIFO Memory Aperture0 31 */ +#define REG_HSMCI_FIFO32 (0x40000280) /**< (HSMCI) FIFO Memory Aperture0 32 */ +#define REG_HSMCI_FIFO33 (0x40000284) /**< (HSMCI) FIFO Memory Aperture0 33 */ +#define REG_HSMCI_FIFO34 (0x40000288) /**< (HSMCI) FIFO Memory Aperture0 34 */ +#define REG_HSMCI_FIFO35 (0x4000028C) /**< (HSMCI) FIFO Memory Aperture0 35 */ +#define REG_HSMCI_FIFO36 (0x40000290) /**< (HSMCI) FIFO Memory Aperture0 36 */ +#define REG_HSMCI_FIFO37 (0x40000294) /**< (HSMCI) FIFO Memory Aperture0 37 */ +#define REG_HSMCI_FIFO38 (0x40000298) /**< (HSMCI) FIFO Memory Aperture0 38 */ +#define REG_HSMCI_FIFO39 (0x4000029C) /**< (HSMCI) FIFO Memory Aperture0 39 */ +#define REG_HSMCI_FIFO40 (0x400002A0) /**< (HSMCI) FIFO Memory Aperture0 40 */ +#define REG_HSMCI_FIFO41 (0x400002A4) /**< (HSMCI) FIFO Memory Aperture0 41 */ +#define REG_HSMCI_FIFO42 (0x400002A8) /**< (HSMCI) FIFO Memory Aperture0 42 */ +#define REG_HSMCI_FIFO43 (0x400002AC) /**< (HSMCI) FIFO Memory Aperture0 43 */ +#define REG_HSMCI_FIFO44 (0x400002B0) /**< (HSMCI) FIFO Memory Aperture0 44 */ +#define REG_HSMCI_FIFO45 (0x400002B4) /**< (HSMCI) FIFO Memory Aperture0 45 */ +#define REG_HSMCI_FIFO46 (0x400002B8) /**< (HSMCI) FIFO Memory Aperture0 46 */ +#define REG_HSMCI_FIFO47 (0x400002BC) /**< (HSMCI) FIFO Memory Aperture0 47 */ +#define REG_HSMCI_FIFO48 (0x400002C0) /**< (HSMCI) FIFO Memory Aperture0 48 */ +#define REG_HSMCI_FIFO49 (0x400002C4) /**< (HSMCI) FIFO Memory Aperture0 49 */ +#define REG_HSMCI_FIFO50 (0x400002C8) /**< (HSMCI) FIFO Memory Aperture0 50 */ +#define REG_HSMCI_FIFO51 (0x400002CC) /**< (HSMCI) FIFO Memory Aperture0 51 */ +#define REG_HSMCI_FIFO52 (0x400002D0) /**< (HSMCI) FIFO Memory Aperture0 52 */ +#define REG_HSMCI_FIFO53 (0x400002D4) /**< (HSMCI) FIFO Memory Aperture0 53 */ +#define REG_HSMCI_FIFO54 (0x400002D8) /**< (HSMCI) FIFO Memory Aperture0 54 */ +#define REG_HSMCI_FIFO55 (0x400002DC) /**< (HSMCI) FIFO Memory Aperture0 55 */ +#define REG_HSMCI_FIFO56 (0x400002E0) /**< (HSMCI) FIFO Memory Aperture0 56 */ +#define REG_HSMCI_FIFO57 (0x400002E4) /**< (HSMCI) FIFO Memory Aperture0 57 */ +#define REG_HSMCI_FIFO58 (0x400002E8) /**< (HSMCI) FIFO Memory Aperture0 58 */ +#define REG_HSMCI_FIFO59 (0x400002EC) /**< (HSMCI) FIFO Memory Aperture0 59 */ +#define REG_HSMCI_FIFO60 (0x400002F0) /**< (HSMCI) FIFO Memory Aperture0 60 */ +#define REG_HSMCI_FIFO61 (0x400002F4) /**< (HSMCI) FIFO Memory Aperture0 61 */ +#define REG_HSMCI_FIFO62 (0x400002F8) /**< (HSMCI) FIFO Memory Aperture0 62 */ +#define REG_HSMCI_FIFO63 (0x400002FC) /**< (HSMCI) FIFO Memory Aperture0 63 */ +#define REG_HSMCI_FIFO64 (0x40000300) /**< (HSMCI) FIFO Memory Aperture0 64 */ +#define REG_HSMCI_FIFO65 (0x40000304) /**< (HSMCI) FIFO Memory Aperture0 65 */ +#define REG_HSMCI_FIFO66 (0x40000308) /**< (HSMCI) FIFO Memory Aperture0 66 */ +#define REG_HSMCI_FIFO67 (0x4000030C) /**< (HSMCI) FIFO Memory Aperture0 67 */ +#define REG_HSMCI_FIFO68 (0x40000310) /**< (HSMCI) FIFO Memory Aperture0 68 */ +#define REG_HSMCI_FIFO69 (0x40000314) /**< (HSMCI) FIFO Memory Aperture0 69 */ +#define REG_HSMCI_FIFO70 (0x40000318) /**< (HSMCI) FIFO Memory Aperture0 70 */ +#define REG_HSMCI_FIFO71 (0x4000031C) /**< (HSMCI) FIFO Memory Aperture0 71 */ +#define REG_HSMCI_FIFO72 (0x40000320) /**< (HSMCI) FIFO Memory Aperture0 72 */ +#define REG_HSMCI_FIFO73 (0x40000324) /**< (HSMCI) FIFO Memory Aperture0 73 */ +#define REG_HSMCI_FIFO74 (0x40000328) /**< (HSMCI) FIFO Memory Aperture0 74 */ +#define REG_HSMCI_FIFO75 (0x4000032C) /**< (HSMCI) FIFO Memory Aperture0 75 */ +#define REG_HSMCI_FIFO76 (0x40000330) /**< (HSMCI) FIFO Memory Aperture0 76 */ +#define REG_HSMCI_FIFO77 (0x40000334) /**< (HSMCI) FIFO Memory Aperture0 77 */ +#define REG_HSMCI_FIFO78 (0x40000338) /**< (HSMCI) FIFO Memory Aperture0 78 */ +#define REG_HSMCI_FIFO79 (0x4000033C) /**< (HSMCI) FIFO Memory Aperture0 79 */ +#define REG_HSMCI_FIFO80 (0x40000340) /**< (HSMCI) FIFO Memory Aperture0 80 */ +#define REG_HSMCI_FIFO81 (0x40000344) /**< (HSMCI) FIFO Memory Aperture0 81 */ +#define REG_HSMCI_FIFO82 (0x40000348) /**< (HSMCI) FIFO Memory Aperture0 82 */ +#define REG_HSMCI_FIFO83 (0x4000034C) /**< (HSMCI) FIFO Memory Aperture0 83 */ +#define REG_HSMCI_FIFO84 (0x40000350) /**< (HSMCI) FIFO Memory Aperture0 84 */ +#define REG_HSMCI_FIFO85 (0x40000354) /**< (HSMCI) FIFO Memory Aperture0 85 */ +#define REG_HSMCI_FIFO86 (0x40000358) /**< (HSMCI) FIFO Memory Aperture0 86 */ +#define REG_HSMCI_FIFO87 (0x4000035C) /**< (HSMCI) FIFO Memory Aperture0 87 */ +#define REG_HSMCI_FIFO88 (0x40000360) /**< (HSMCI) FIFO Memory Aperture0 88 */ +#define REG_HSMCI_FIFO89 (0x40000364) /**< (HSMCI) FIFO Memory Aperture0 89 */ +#define REG_HSMCI_FIFO90 (0x40000368) /**< (HSMCI) FIFO Memory Aperture0 90 */ +#define REG_HSMCI_FIFO91 (0x4000036C) /**< (HSMCI) FIFO Memory Aperture0 91 */ +#define REG_HSMCI_FIFO92 (0x40000370) /**< (HSMCI) FIFO Memory Aperture0 92 */ +#define REG_HSMCI_FIFO93 (0x40000374) /**< (HSMCI) FIFO Memory Aperture0 93 */ +#define REG_HSMCI_FIFO94 (0x40000378) /**< (HSMCI) FIFO Memory Aperture0 94 */ +#define REG_HSMCI_FIFO95 (0x4000037C) /**< (HSMCI) FIFO Memory Aperture0 95 */ +#define REG_HSMCI_FIFO96 (0x40000380) /**< (HSMCI) FIFO Memory Aperture0 96 */ +#define REG_HSMCI_FIFO97 (0x40000384) /**< (HSMCI) FIFO Memory Aperture0 97 */ +#define REG_HSMCI_FIFO98 (0x40000388) /**< (HSMCI) FIFO Memory Aperture0 98 */ +#define REG_HSMCI_FIFO99 (0x4000038C) /**< (HSMCI) FIFO Memory Aperture0 99 */ +#define REG_HSMCI_FIFO100 (0x40000390) /**< (HSMCI) FIFO Memory Aperture0 100 */ +#define REG_HSMCI_FIFO101 (0x40000394) /**< (HSMCI) FIFO Memory Aperture0 101 */ +#define REG_HSMCI_FIFO102 (0x40000398) /**< (HSMCI) FIFO Memory Aperture0 102 */ +#define REG_HSMCI_FIFO103 (0x4000039C) /**< (HSMCI) FIFO Memory Aperture0 103 */ +#define REG_HSMCI_FIFO104 (0x400003A0) /**< (HSMCI) FIFO Memory Aperture0 104 */ +#define REG_HSMCI_FIFO105 (0x400003A4) /**< (HSMCI) FIFO Memory Aperture0 105 */ +#define REG_HSMCI_FIFO106 (0x400003A8) /**< (HSMCI) FIFO Memory Aperture0 106 */ +#define REG_HSMCI_FIFO107 (0x400003AC) /**< (HSMCI) FIFO Memory Aperture0 107 */ +#define REG_HSMCI_FIFO108 (0x400003B0) /**< (HSMCI) FIFO Memory Aperture0 108 */ +#define REG_HSMCI_FIFO109 (0x400003B4) /**< (HSMCI) FIFO Memory Aperture0 109 */ +#define REG_HSMCI_FIFO110 (0x400003B8) /**< (HSMCI) FIFO Memory Aperture0 110 */ +#define REG_HSMCI_FIFO111 (0x400003BC) /**< (HSMCI) FIFO Memory Aperture0 111 */ +#define REG_HSMCI_FIFO112 (0x400003C0) /**< (HSMCI) FIFO Memory Aperture0 112 */ +#define REG_HSMCI_FIFO113 (0x400003C4) /**< (HSMCI) FIFO Memory Aperture0 113 */ +#define REG_HSMCI_FIFO114 (0x400003C8) /**< (HSMCI) FIFO Memory Aperture0 114 */ +#define REG_HSMCI_FIFO115 (0x400003CC) /**< (HSMCI) FIFO Memory Aperture0 115 */ +#define REG_HSMCI_FIFO116 (0x400003D0) /**< (HSMCI) FIFO Memory Aperture0 116 */ +#define REG_HSMCI_FIFO117 (0x400003D4) /**< (HSMCI) FIFO Memory Aperture0 117 */ +#define REG_HSMCI_FIFO118 (0x400003D8) /**< (HSMCI) FIFO Memory Aperture0 118 */ +#define REG_HSMCI_FIFO119 (0x400003DC) /**< (HSMCI) FIFO Memory Aperture0 119 */ +#define REG_HSMCI_FIFO120 (0x400003E0) /**< (HSMCI) FIFO Memory Aperture0 120 */ +#define REG_HSMCI_FIFO121 (0x400003E4) /**< (HSMCI) FIFO Memory Aperture0 121 */ +#define REG_HSMCI_FIFO122 (0x400003E8) /**< (HSMCI) FIFO Memory Aperture0 122 */ +#define REG_HSMCI_FIFO123 (0x400003EC) /**< (HSMCI) FIFO Memory Aperture0 123 */ +#define REG_HSMCI_FIFO124 (0x400003F0) /**< (HSMCI) FIFO Memory Aperture0 124 */ +#define REG_HSMCI_FIFO125 (0x400003F4) /**< (HSMCI) FIFO Memory Aperture0 125 */ +#define REG_HSMCI_FIFO126 (0x400003F8) /**< (HSMCI) FIFO Memory Aperture0 126 */ +#define REG_HSMCI_FIFO127 (0x400003FC) /**< (HSMCI) FIFO Memory Aperture0 127 */ +#define REG_HSMCI_FIFO128 (0x40000400) /**< (HSMCI) FIFO Memory Aperture0 128 */ +#define REG_HSMCI_FIFO129 (0x40000404) /**< (HSMCI) FIFO Memory Aperture0 129 */ +#define REG_HSMCI_FIFO130 (0x40000408) /**< (HSMCI) FIFO Memory Aperture0 130 */ +#define REG_HSMCI_FIFO131 (0x4000040C) /**< (HSMCI) FIFO Memory Aperture0 131 */ +#define REG_HSMCI_FIFO132 (0x40000410) /**< (HSMCI) FIFO Memory Aperture0 132 */ +#define REG_HSMCI_FIFO133 (0x40000414) /**< (HSMCI) FIFO Memory Aperture0 133 */ +#define REG_HSMCI_FIFO134 (0x40000418) /**< (HSMCI) FIFO Memory Aperture0 134 */ +#define REG_HSMCI_FIFO135 (0x4000041C) /**< (HSMCI) FIFO Memory Aperture0 135 */ +#define REG_HSMCI_FIFO136 (0x40000420) /**< (HSMCI) FIFO Memory Aperture0 136 */ +#define REG_HSMCI_FIFO137 (0x40000424) /**< (HSMCI) FIFO Memory Aperture0 137 */ +#define REG_HSMCI_FIFO138 (0x40000428) /**< (HSMCI) FIFO Memory Aperture0 138 */ +#define REG_HSMCI_FIFO139 (0x4000042C) /**< (HSMCI) FIFO Memory Aperture0 139 */ +#define REG_HSMCI_FIFO140 (0x40000430) /**< (HSMCI) FIFO Memory Aperture0 140 */ +#define REG_HSMCI_FIFO141 (0x40000434) /**< (HSMCI) FIFO Memory Aperture0 141 */ +#define REG_HSMCI_FIFO142 (0x40000438) /**< (HSMCI) FIFO Memory Aperture0 142 */ +#define REG_HSMCI_FIFO143 (0x4000043C) /**< (HSMCI) FIFO Memory Aperture0 143 */ +#define REG_HSMCI_FIFO144 (0x40000440) /**< (HSMCI) FIFO Memory Aperture0 144 */ +#define REG_HSMCI_FIFO145 (0x40000444) /**< (HSMCI) FIFO Memory Aperture0 145 */ +#define REG_HSMCI_FIFO146 (0x40000448) /**< (HSMCI) FIFO Memory Aperture0 146 */ +#define REG_HSMCI_FIFO147 (0x4000044C) /**< (HSMCI) FIFO Memory Aperture0 147 */ +#define REG_HSMCI_FIFO148 (0x40000450) /**< (HSMCI) FIFO Memory Aperture0 148 */ +#define REG_HSMCI_FIFO149 (0x40000454) /**< (HSMCI) FIFO Memory Aperture0 149 */ +#define REG_HSMCI_FIFO150 (0x40000458) /**< (HSMCI) FIFO Memory Aperture0 150 */ +#define REG_HSMCI_FIFO151 (0x4000045C) /**< (HSMCI) FIFO Memory Aperture0 151 */ +#define REG_HSMCI_FIFO152 (0x40000460) /**< (HSMCI) FIFO Memory Aperture0 152 */ +#define REG_HSMCI_FIFO153 (0x40000464) /**< (HSMCI) FIFO Memory Aperture0 153 */ +#define REG_HSMCI_FIFO154 (0x40000468) /**< (HSMCI) FIFO Memory Aperture0 154 */ +#define REG_HSMCI_FIFO155 (0x4000046C) /**< (HSMCI) FIFO Memory Aperture0 155 */ +#define REG_HSMCI_FIFO156 (0x40000470) /**< (HSMCI) FIFO Memory Aperture0 156 */ +#define REG_HSMCI_FIFO157 (0x40000474) /**< (HSMCI) FIFO Memory Aperture0 157 */ +#define REG_HSMCI_FIFO158 (0x40000478) /**< (HSMCI) FIFO Memory Aperture0 158 */ +#define REG_HSMCI_FIFO159 (0x4000047C) /**< (HSMCI) FIFO Memory Aperture0 159 */ +#define REG_HSMCI_FIFO160 (0x40000480) /**< (HSMCI) FIFO Memory Aperture0 160 */ +#define REG_HSMCI_FIFO161 (0x40000484) /**< (HSMCI) FIFO Memory Aperture0 161 */ +#define REG_HSMCI_FIFO162 (0x40000488) /**< (HSMCI) FIFO Memory Aperture0 162 */ +#define REG_HSMCI_FIFO163 (0x4000048C) /**< (HSMCI) FIFO Memory Aperture0 163 */ +#define REG_HSMCI_FIFO164 (0x40000490) /**< (HSMCI) FIFO Memory Aperture0 164 */ +#define REG_HSMCI_FIFO165 (0x40000494) /**< (HSMCI) FIFO Memory Aperture0 165 */ +#define REG_HSMCI_FIFO166 (0x40000498) /**< (HSMCI) FIFO Memory Aperture0 166 */ +#define REG_HSMCI_FIFO167 (0x4000049C) /**< (HSMCI) FIFO Memory Aperture0 167 */ +#define REG_HSMCI_FIFO168 (0x400004A0) /**< (HSMCI) FIFO Memory Aperture0 168 */ +#define REG_HSMCI_FIFO169 (0x400004A4) /**< (HSMCI) FIFO Memory Aperture0 169 */ +#define REG_HSMCI_FIFO170 (0x400004A8) /**< (HSMCI) FIFO Memory Aperture0 170 */ +#define REG_HSMCI_FIFO171 (0x400004AC) /**< (HSMCI) FIFO Memory Aperture0 171 */ +#define REG_HSMCI_FIFO172 (0x400004B0) /**< (HSMCI) FIFO Memory Aperture0 172 */ +#define REG_HSMCI_FIFO173 (0x400004B4) /**< (HSMCI) FIFO Memory Aperture0 173 */ +#define REG_HSMCI_FIFO174 (0x400004B8) /**< (HSMCI) FIFO Memory Aperture0 174 */ +#define REG_HSMCI_FIFO175 (0x400004BC) /**< (HSMCI) FIFO Memory Aperture0 175 */ +#define REG_HSMCI_FIFO176 (0x400004C0) /**< (HSMCI) FIFO Memory Aperture0 176 */ +#define REG_HSMCI_FIFO177 (0x400004C4) /**< (HSMCI) FIFO Memory Aperture0 177 */ +#define REG_HSMCI_FIFO178 (0x400004C8) /**< (HSMCI) FIFO Memory Aperture0 178 */ +#define REG_HSMCI_FIFO179 (0x400004CC) /**< (HSMCI) FIFO Memory Aperture0 179 */ +#define REG_HSMCI_FIFO180 (0x400004D0) /**< (HSMCI) FIFO Memory Aperture0 180 */ +#define REG_HSMCI_FIFO181 (0x400004D4) /**< (HSMCI) FIFO Memory Aperture0 181 */ +#define REG_HSMCI_FIFO182 (0x400004D8) /**< (HSMCI) FIFO Memory Aperture0 182 */ +#define REG_HSMCI_FIFO183 (0x400004DC) /**< (HSMCI) FIFO Memory Aperture0 183 */ +#define REG_HSMCI_FIFO184 (0x400004E0) /**< (HSMCI) FIFO Memory Aperture0 184 */ +#define REG_HSMCI_FIFO185 (0x400004E4) /**< (HSMCI) FIFO Memory Aperture0 185 */ +#define REG_HSMCI_FIFO186 (0x400004E8) /**< (HSMCI) FIFO Memory Aperture0 186 */ +#define REG_HSMCI_FIFO187 (0x400004EC) /**< (HSMCI) FIFO Memory Aperture0 187 */ +#define REG_HSMCI_FIFO188 (0x400004F0) /**< (HSMCI) FIFO Memory Aperture0 188 */ +#define REG_HSMCI_FIFO189 (0x400004F4) /**< (HSMCI) FIFO Memory Aperture0 189 */ +#define REG_HSMCI_FIFO190 (0x400004F8) /**< (HSMCI) FIFO Memory Aperture0 190 */ +#define REG_HSMCI_FIFO191 (0x400004FC) /**< (HSMCI) FIFO Memory Aperture0 191 */ +#define REG_HSMCI_FIFO192 (0x40000500) /**< (HSMCI) FIFO Memory Aperture0 192 */ +#define REG_HSMCI_FIFO193 (0x40000504) /**< (HSMCI) FIFO Memory Aperture0 193 */ +#define REG_HSMCI_FIFO194 (0x40000508) /**< (HSMCI) FIFO Memory Aperture0 194 */ +#define REG_HSMCI_FIFO195 (0x4000050C) /**< (HSMCI) FIFO Memory Aperture0 195 */ +#define REG_HSMCI_FIFO196 (0x40000510) /**< (HSMCI) FIFO Memory Aperture0 196 */ +#define REG_HSMCI_FIFO197 (0x40000514) /**< (HSMCI) FIFO Memory Aperture0 197 */ +#define REG_HSMCI_FIFO198 (0x40000518) /**< (HSMCI) FIFO Memory Aperture0 198 */ +#define REG_HSMCI_FIFO199 (0x4000051C) /**< (HSMCI) FIFO Memory Aperture0 199 */ +#define REG_HSMCI_FIFO200 (0x40000520) /**< (HSMCI) FIFO Memory Aperture0 200 */ +#define REG_HSMCI_FIFO201 (0x40000524) /**< (HSMCI) FIFO Memory Aperture0 201 */ +#define REG_HSMCI_FIFO202 (0x40000528) /**< (HSMCI) FIFO Memory Aperture0 202 */ +#define REG_HSMCI_FIFO203 (0x4000052C) /**< (HSMCI) FIFO Memory Aperture0 203 */ +#define REG_HSMCI_FIFO204 (0x40000530) /**< (HSMCI) FIFO Memory Aperture0 204 */ +#define REG_HSMCI_FIFO205 (0x40000534) /**< (HSMCI) FIFO Memory Aperture0 205 */ +#define REG_HSMCI_FIFO206 (0x40000538) /**< (HSMCI) FIFO Memory Aperture0 206 */ +#define REG_HSMCI_FIFO207 (0x4000053C) /**< (HSMCI) FIFO Memory Aperture0 207 */ +#define REG_HSMCI_FIFO208 (0x40000540) /**< (HSMCI) FIFO Memory Aperture0 208 */ +#define REG_HSMCI_FIFO209 (0x40000544) /**< (HSMCI) FIFO Memory Aperture0 209 */ +#define REG_HSMCI_FIFO210 (0x40000548) /**< (HSMCI) FIFO Memory Aperture0 210 */ +#define REG_HSMCI_FIFO211 (0x4000054C) /**< (HSMCI) FIFO Memory Aperture0 211 */ +#define REG_HSMCI_FIFO212 (0x40000550) /**< (HSMCI) FIFO Memory Aperture0 212 */ +#define REG_HSMCI_FIFO213 (0x40000554) /**< (HSMCI) FIFO Memory Aperture0 213 */ +#define REG_HSMCI_FIFO214 (0x40000558) /**< (HSMCI) FIFO Memory Aperture0 214 */ +#define REG_HSMCI_FIFO215 (0x4000055C) /**< (HSMCI) FIFO Memory Aperture0 215 */ +#define REG_HSMCI_FIFO216 (0x40000560) /**< (HSMCI) FIFO Memory Aperture0 216 */ +#define REG_HSMCI_FIFO217 (0x40000564) /**< (HSMCI) FIFO Memory Aperture0 217 */ +#define REG_HSMCI_FIFO218 (0x40000568) /**< (HSMCI) FIFO Memory Aperture0 218 */ +#define REG_HSMCI_FIFO219 (0x4000056C) /**< (HSMCI) FIFO Memory Aperture0 219 */ +#define REG_HSMCI_FIFO220 (0x40000570) /**< (HSMCI) FIFO Memory Aperture0 220 */ +#define REG_HSMCI_FIFO221 (0x40000574) /**< (HSMCI) FIFO Memory Aperture0 221 */ +#define REG_HSMCI_FIFO222 (0x40000578) /**< (HSMCI) FIFO Memory Aperture0 222 */ +#define REG_HSMCI_FIFO223 (0x4000057C) /**< (HSMCI) FIFO Memory Aperture0 223 */ +#define REG_HSMCI_FIFO224 (0x40000580) /**< (HSMCI) FIFO Memory Aperture0 224 */ +#define REG_HSMCI_FIFO225 (0x40000584) /**< (HSMCI) FIFO Memory Aperture0 225 */ +#define REG_HSMCI_FIFO226 (0x40000588) /**< (HSMCI) FIFO Memory Aperture0 226 */ +#define REG_HSMCI_FIFO227 (0x4000058C) /**< (HSMCI) FIFO Memory Aperture0 227 */ +#define REG_HSMCI_FIFO228 (0x40000590) /**< (HSMCI) FIFO Memory Aperture0 228 */ +#define REG_HSMCI_FIFO229 (0x40000594) /**< (HSMCI) FIFO Memory Aperture0 229 */ +#define REG_HSMCI_FIFO230 (0x40000598) /**< (HSMCI) FIFO Memory Aperture0 230 */ +#define REG_HSMCI_FIFO231 (0x4000059C) /**< (HSMCI) FIFO Memory Aperture0 231 */ +#define REG_HSMCI_FIFO232 (0x400005A0) /**< (HSMCI) FIFO Memory Aperture0 232 */ +#define REG_HSMCI_FIFO233 (0x400005A4) /**< (HSMCI) FIFO Memory Aperture0 233 */ +#define REG_HSMCI_FIFO234 (0x400005A8) /**< (HSMCI) FIFO Memory Aperture0 234 */ +#define REG_HSMCI_FIFO235 (0x400005AC) /**< (HSMCI) FIFO Memory Aperture0 235 */ +#define REG_HSMCI_FIFO236 (0x400005B0) /**< (HSMCI) FIFO Memory Aperture0 236 */ +#define REG_HSMCI_FIFO237 (0x400005B4) /**< (HSMCI) FIFO Memory Aperture0 237 */ +#define REG_HSMCI_FIFO238 (0x400005B8) /**< (HSMCI) FIFO Memory Aperture0 238 */ +#define REG_HSMCI_FIFO239 (0x400005BC) /**< (HSMCI) FIFO Memory Aperture0 239 */ +#define REG_HSMCI_FIFO240 (0x400005C0) /**< (HSMCI) FIFO Memory Aperture0 240 */ +#define REG_HSMCI_FIFO241 (0x400005C4) /**< (HSMCI) FIFO Memory Aperture0 241 */ +#define REG_HSMCI_FIFO242 (0x400005C8) /**< (HSMCI) FIFO Memory Aperture0 242 */ +#define REG_HSMCI_FIFO243 (0x400005CC) /**< (HSMCI) FIFO Memory Aperture0 243 */ +#define REG_HSMCI_FIFO244 (0x400005D0) /**< (HSMCI) FIFO Memory Aperture0 244 */ +#define REG_HSMCI_FIFO245 (0x400005D4) /**< (HSMCI) FIFO Memory Aperture0 245 */ +#define REG_HSMCI_FIFO246 (0x400005D8) /**< (HSMCI) FIFO Memory Aperture0 246 */ +#define REG_HSMCI_FIFO247 (0x400005DC) /**< (HSMCI) FIFO Memory Aperture0 247 */ +#define REG_HSMCI_FIFO248 (0x400005E0) /**< (HSMCI) FIFO Memory Aperture0 248 */ +#define REG_HSMCI_FIFO249 (0x400005E4) /**< (HSMCI) FIFO Memory Aperture0 249 */ +#define REG_HSMCI_FIFO250 (0x400005E8) /**< (HSMCI) FIFO Memory Aperture0 250 */ +#define REG_HSMCI_FIFO251 (0x400005EC) /**< (HSMCI) FIFO Memory Aperture0 251 */ +#define REG_HSMCI_FIFO252 (0x400005F0) /**< (HSMCI) FIFO Memory Aperture0 252 */ +#define REG_HSMCI_FIFO253 (0x400005F4) /**< (HSMCI) FIFO Memory Aperture0 253 */ +#define REG_HSMCI_FIFO254 (0x400005F8) /**< (HSMCI) FIFO Memory Aperture0 254 */ +#define REG_HSMCI_FIFO255 (0x400005FC) /**< (HSMCI) FIFO Memory Aperture0 255 */ + +#else + +#define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< (HSMCI) Control Register */ +#define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */ +#define REG_HSMCI_RSPR0 (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */ +#define REG_HSMCI_RSPR1 (*(__I uint32_t*)0x40000024U) /**< (HSMCI) Response Register 1 */ +#define REG_HSMCI_RSPR2 (*(__I uint32_t*)0x40000028U) /**< (HSMCI) Response Register 2 */ +#define REG_HSMCI_RSPR3 (*(__I uint32_t*)0x4000002CU) /**< (HSMCI) Response Register 3 */ +#define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< (HSMCI) Status Register */ +#define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */ +#define REG_HSMCI_FIFO0 (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */ +#define REG_HSMCI_FIFO1 (*(__IO uint32_t*)0x40000204U) /**< (HSMCI) FIFO Memory Aperture0 1 */ +#define REG_HSMCI_FIFO2 (*(__IO uint32_t*)0x40000208U) /**< (HSMCI) FIFO Memory Aperture0 2 */ +#define REG_HSMCI_FIFO3 (*(__IO uint32_t*)0x4000020CU) /**< (HSMCI) FIFO Memory Aperture0 3 */ +#define REG_HSMCI_FIFO4 (*(__IO uint32_t*)0x40000210U) /**< (HSMCI) FIFO Memory Aperture0 4 */ +#define REG_HSMCI_FIFO5 (*(__IO uint32_t*)0x40000214U) /**< (HSMCI) FIFO Memory Aperture0 5 */ +#define REG_HSMCI_FIFO6 (*(__IO uint32_t*)0x40000218U) /**< (HSMCI) FIFO Memory Aperture0 6 */ +#define REG_HSMCI_FIFO7 (*(__IO uint32_t*)0x4000021CU) /**< (HSMCI) FIFO Memory Aperture0 7 */ +#define REG_HSMCI_FIFO8 (*(__IO uint32_t*)0x40000220U) /**< (HSMCI) FIFO Memory Aperture0 8 */ +#define REG_HSMCI_FIFO9 (*(__IO uint32_t*)0x40000224U) /**< (HSMCI) FIFO Memory Aperture0 9 */ +#define REG_HSMCI_FIFO10 (*(__IO uint32_t*)0x40000228U) /**< (HSMCI) FIFO Memory Aperture0 10 */ +#define REG_HSMCI_FIFO11 (*(__IO uint32_t*)0x4000022CU) /**< (HSMCI) FIFO Memory Aperture0 11 */ +#define REG_HSMCI_FIFO12 (*(__IO uint32_t*)0x40000230U) /**< (HSMCI) FIFO Memory Aperture0 12 */ +#define REG_HSMCI_FIFO13 (*(__IO uint32_t*)0x40000234U) /**< (HSMCI) FIFO Memory Aperture0 13 */ +#define REG_HSMCI_FIFO14 (*(__IO uint32_t*)0x40000238U) /**< (HSMCI) FIFO Memory Aperture0 14 */ +#define REG_HSMCI_FIFO15 (*(__IO uint32_t*)0x4000023CU) /**< (HSMCI) FIFO Memory Aperture0 15 */ +#define REG_HSMCI_FIFO16 (*(__IO uint32_t*)0x40000240U) /**< (HSMCI) FIFO Memory Aperture0 16 */ +#define REG_HSMCI_FIFO17 (*(__IO uint32_t*)0x40000244U) /**< (HSMCI) FIFO Memory Aperture0 17 */ +#define REG_HSMCI_FIFO18 (*(__IO uint32_t*)0x40000248U) /**< (HSMCI) FIFO Memory Aperture0 18 */ +#define REG_HSMCI_FIFO19 (*(__IO uint32_t*)0x4000024CU) /**< (HSMCI) FIFO Memory Aperture0 19 */ +#define REG_HSMCI_FIFO20 (*(__IO uint32_t*)0x40000250U) /**< (HSMCI) FIFO Memory Aperture0 20 */ +#define REG_HSMCI_FIFO21 (*(__IO uint32_t*)0x40000254U) /**< (HSMCI) FIFO Memory Aperture0 21 */ +#define REG_HSMCI_FIFO22 (*(__IO uint32_t*)0x40000258U) /**< (HSMCI) FIFO Memory Aperture0 22 */ +#define REG_HSMCI_FIFO23 (*(__IO uint32_t*)0x4000025CU) /**< (HSMCI) FIFO Memory Aperture0 23 */ +#define REG_HSMCI_FIFO24 (*(__IO uint32_t*)0x40000260U) /**< (HSMCI) FIFO Memory Aperture0 24 */ +#define REG_HSMCI_FIFO25 (*(__IO uint32_t*)0x40000264U) /**< (HSMCI) FIFO Memory Aperture0 25 */ +#define REG_HSMCI_FIFO26 (*(__IO uint32_t*)0x40000268U) /**< (HSMCI) FIFO Memory Aperture0 26 */ +#define REG_HSMCI_FIFO27 (*(__IO uint32_t*)0x4000026CU) /**< (HSMCI) FIFO Memory Aperture0 27 */ +#define REG_HSMCI_FIFO28 (*(__IO uint32_t*)0x40000270U) /**< (HSMCI) FIFO Memory Aperture0 28 */ +#define REG_HSMCI_FIFO29 (*(__IO uint32_t*)0x40000274U) /**< (HSMCI) FIFO Memory Aperture0 29 */ +#define REG_HSMCI_FIFO30 (*(__IO uint32_t*)0x40000278U) /**< (HSMCI) FIFO Memory Aperture0 30 */ +#define REG_HSMCI_FIFO31 (*(__IO uint32_t*)0x4000027CU) /**< (HSMCI) FIFO Memory Aperture0 31 */ +#define REG_HSMCI_FIFO32 (*(__IO uint32_t*)0x40000280U) /**< (HSMCI) FIFO Memory Aperture0 32 */ +#define REG_HSMCI_FIFO33 (*(__IO uint32_t*)0x40000284U) /**< (HSMCI) FIFO Memory Aperture0 33 */ +#define REG_HSMCI_FIFO34 (*(__IO uint32_t*)0x40000288U) /**< (HSMCI) FIFO Memory Aperture0 34 */ +#define REG_HSMCI_FIFO35 (*(__IO uint32_t*)0x4000028CU) /**< (HSMCI) FIFO Memory Aperture0 35 */ +#define REG_HSMCI_FIFO36 (*(__IO uint32_t*)0x40000290U) /**< (HSMCI) FIFO Memory Aperture0 36 */ +#define REG_HSMCI_FIFO37 (*(__IO uint32_t*)0x40000294U) /**< (HSMCI) FIFO Memory Aperture0 37 */ +#define REG_HSMCI_FIFO38 (*(__IO uint32_t*)0x40000298U) /**< (HSMCI) FIFO Memory Aperture0 38 */ +#define REG_HSMCI_FIFO39 (*(__IO uint32_t*)0x4000029CU) /**< (HSMCI) FIFO Memory Aperture0 39 */ +#define REG_HSMCI_FIFO40 (*(__IO uint32_t*)0x400002A0U) /**< (HSMCI) FIFO Memory Aperture0 40 */ +#define REG_HSMCI_FIFO41 (*(__IO uint32_t*)0x400002A4U) /**< (HSMCI) FIFO Memory Aperture0 41 */ +#define REG_HSMCI_FIFO42 (*(__IO uint32_t*)0x400002A8U) /**< (HSMCI) FIFO Memory Aperture0 42 */ +#define REG_HSMCI_FIFO43 (*(__IO uint32_t*)0x400002ACU) /**< (HSMCI) FIFO Memory Aperture0 43 */ +#define REG_HSMCI_FIFO44 (*(__IO uint32_t*)0x400002B0U) /**< (HSMCI) FIFO Memory Aperture0 44 */ +#define REG_HSMCI_FIFO45 (*(__IO uint32_t*)0x400002B4U) /**< (HSMCI) FIFO Memory Aperture0 45 */ +#define REG_HSMCI_FIFO46 (*(__IO uint32_t*)0x400002B8U) /**< (HSMCI) FIFO Memory Aperture0 46 */ +#define REG_HSMCI_FIFO47 (*(__IO uint32_t*)0x400002BCU) /**< (HSMCI) FIFO Memory Aperture0 47 */ +#define REG_HSMCI_FIFO48 (*(__IO uint32_t*)0x400002C0U) /**< (HSMCI) FIFO Memory Aperture0 48 */ +#define REG_HSMCI_FIFO49 (*(__IO uint32_t*)0x400002C4U) /**< (HSMCI) FIFO Memory Aperture0 49 */ +#define REG_HSMCI_FIFO50 (*(__IO uint32_t*)0x400002C8U) /**< (HSMCI) FIFO Memory Aperture0 50 */ +#define REG_HSMCI_FIFO51 (*(__IO uint32_t*)0x400002CCU) /**< (HSMCI) FIFO Memory Aperture0 51 */ +#define REG_HSMCI_FIFO52 (*(__IO uint32_t*)0x400002D0U) /**< (HSMCI) FIFO Memory Aperture0 52 */ +#define REG_HSMCI_FIFO53 (*(__IO uint32_t*)0x400002D4U) /**< (HSMCI) FIFO Memory Aperture0 53 */ +#define REG_HSMCI_FIFO54 (*(__IO uint32_t*)0x400002D8U) /**< (HSMCI) FIFO Memory Aperture0 54 */ +#define REG_HSMCI_FIFO55 (*(__IO uint32_t*)0x400002DCU) /**< (HSMCI) FIFO Memory Aperture0 55 */ +#define REG_HSMCI_FIFO56 (*(__IO uint32_t*)0x400002E0U) /**< (HSMCI) FIFO Memory Aperture0 56 */ +#define REG_HSMCI_FIFO57 (*(__IO uint32_t*)0x400002E4U) /**< (HSMCI) FIFO Memory Aperture0 57 */ +#define REG_HSMCI_FIFO58 (*(__IO uint32_t*)0x400002E8U) /**< (HSMCI) FIFO Memory Aperture0 58 */ +#define REG_HSMCI_FIFO59 (*(__IO uint32_t*)0x400002ECU) /**< (HSMCI) FIFO Memory Aperture0 59 */ +#define REG_HSMCI_FIFO60 (*(__IO uint32_t*)0x400002F0U) /**< (HSMCI) FIFO Memory Aperture0 60 */ +#define REG_HSMCI_FIFO61 (*(__IO uint32_t*)0x400002F4U) /**< (HSMCI) FIFO Memory Aperture0 61 */ +#define REG_HSMCI_FIFO62 (*(__IO uint32_t*)0x400002F8U) /**< (HSMCI) FIFO Memory Aperture0 62 */ +#define REG_HSMCI_FIFO63 (*(__IO uint32_t*)0x400002FCU) /**< (HSMCI) FIFO Memory Aperture0 63 */ +#define REG_HSMCI_FIFO64 (*(__IO uint32_t*)0x40000300U) /**< (HSMCI) FIFO Memory Aperture0 64 */ +#define REG_HSMCI_FIFO65 (*(__IO uint32_t*)0x40000304U) /**< (HSMCI) FIFO Memory Aperture0 65 */ +#define REG_HSMCI_FIFO66 (*(__IO uint32_t*)0x40000308U) /**< (HSMCI) FIFO Memory Aperture0 66 */ +#define REG_HSMCI_FIFO67 (*(__IO uint32_t*)0x4000030CU) /**< (HSMCI) FIFO Memory Aperture0 67 */ +#define REG_HSMCI_FIFO68 (*(__IO uint32_t*)0x40000310U) /**< (HSMCI) FIFO Memory Aperture0 68 */ +#define REG_HSMCI_FIFO69 (*(__IO uint32_t*)0x40000314U) /**< (HSMCI) FIFO Memory Aperture0 69 */ +#define REG_HSMCI_FIFO70 (*(__IO uint32_t*)0x40000318U) /**< (HSMCI) FIFO Memory Aperture0 70 */ +#define REG_HSMCI_FIFO71 (*(__IO uint32_t*)0x4000031CU) /**< (HSMCI) FIFO Memory Aperture0 71 */ +#define REG_HSMCI_FIFO72 (*(__IO uint32_t*)0x40000320U) /**< (HSMCI) FIFO Memory Aperture0 72 */ +#define REG_HSMCI_FIFO73 (*(__IO uint32_t*)0x40000324U) /**< (HSMCI) FIFO Memory Aperture0 73 */ +#define REG_HSMCI_FIFO74 (*(__IO uint32_t*)0x40000328U) /**< (HSMCI) FIFO Memory Aperture0 74 */ +#define REG_HSMCI_FIFO75 (*(__IO uint32_t*)0x4000032CU) /**< (HSMCI) FIFO Memory Aperture0 75 */ +#define REG_HSMCI_FIFO76 (*(__IO uint32_t*)0x40000330U) /**< (HSMCI) FIFO Memory Aperture0 76 */ +#define REG_HSMCI_FIFO77 (*(__IO uint32_t*)0x40000334U) /**< (HSMCI) FIFO Memory Aperture0 77 */ +#define REG_HSMCI_FIFO78 (*(__IO uint32_t*)0x40000338U) /**< (HSMCI) FIFO Memory Aperture0 78 */ +#define REG_HSMCI_FIFO79 (*(__IO uint32_t*)0x4000033CU) /**< (HSMCI) FIFO Memory Aperture0 79 */ +#define REG_HSMCI_FIFO80 (*(__IO uint32_t*)0x40000340U) /**< (HSMCI) FIFO Memory Aperture0 80 */ +#define REG_HSMCI_FIFO81 (*(__IO uint32_t*)0x40000344U) /**< (HSMCI) FIFO Memory Aperture0 81 */ +#define REG_HSMCI_FIFO82 (*(__IO uint32_t*)0x40000348U) /**< (HSMCI) FIFO Memory Aperture0 82 */ +#define REG_HSMCI_FIFO83 (*(__IO uint32_t*)0x4000034CU) /**< (HSMCI) FIFO Memory Aperture0 83 */ +#define REG_HSMCI_FIFO84 (*(__IO uint32_t*)0x40000350U) /**< (HSMCI) FIFO Memory Aperture0 84 */ +#define REG_HSMCI_FIFO85 (*(__IO uint32_t*)0x40000354U) /**< (HSMCI) FIFO Memory Aperture0 85 */ +#define REG_HSMCI_FIFO86 (*(__IO uint32_t*)0x40000358U) /**< (HSMCI) FIFO Memory Aperture0 86 */ +#define REG_HSMCI_FIFO87 (*(__IO uint32_t*)0x4000035CU) /**< (HSMCI) FIFO Memory Aperture0 87 */ +#define REG_HSMCI_FIFO88 (*(__IO uint32_t*)0x40000360U) /**< (HSMCI) FIFO Memory Aperture0 88 */ +#define REG_HSMCI_FIFO89 (*(__IO uint32_t*)0x40000364U) /**< (HSMCI) FIFO Memory Aperture0 89 */ +#define REG_HSMCI_FIFO90 (*(__IO uint32_t*)0x40000368U) /**< (HSMCI) FIFO Memory Aperture0 90 */ +#define REG_HSMCI_FIFO91 (*(__IO uint32_t*)0x4000036CU) /**< (HSMCI) FIFO Memory Aperture0 91 */ +#define REG_HSMCI_FIFO92 (*(__IO uint32_t*)0x40000370U) /**< (HSMCI) FIFO Memory Aperture0 92 */ +#define REG_HSMCI_FIFO93 (*(__IO uint32_t*)0x40000374U) /**< (HSMCI) FIFO Memory Aperture0 93 */ +#define REG_HSMCI_FIFO94 (*(__IO uint32_t*)0x40000378U) /**< (HSMCI) FIFO Memory Aperture0 94 */ +#define REG_HSMCI_FIFO95 (*(__IO uint32_t*)0x4000037CU) /**< (HSMCI) FIFO Memory Aperture0 95 */ +#define REG_HSMCI_FIFO96 (*(__IO uint32_t*)0x40000380U) /**< (HSMCI) FIFO Memory Aperture0 96 */ +#define REG_HSMCI_FIFO97 (*(__IO uint32_t*)0x40000384U) /**< (HSMCI) FIFO Memory Aperture0 97 */ +#define REG_HSMCI_FIFO98 (*(__IO uint32_t*)0x40000388U) /**< (HSMCI) FIFO Memory Aperture0 98 */ +#define REG_HSMCI_FIFO99 (*(__IO uint32_t*)0x4000038CU) /**< (HSMCI) FIFO Memory Aperture0 99 */ +#define REG_HSMCI_FIFO100 (*(__IO uint32_t*)0x40000390U) /**< (HSMCI) FIFO Memory Aperture0 100 */ +#define REG_HSMCI_FIFO101 (*(__IO uint32_t*)0x40000394U) /**< (HSMCI) FIFO Memory Aperture0 101 */ +#define REG_HSMCI_FIFO102 (*(__IO uint32_t*)0x40000398U) /**< (HSMCI) FIFO Memory Aperture0 102 */ +#define REG_HSMCI_FIFO103 (*(__IO uint32_t*)0x4000039CU) /**< (HSMCI) FIFO Memory Aperture0 103 */ +#define REG_HSMCI_FIFO104 (*(__IO uint32_t*)0x400003A0U) /**< (HSMCI) FIFO Memory Aperture0 104 */ +#define REG_HSMCI_FIFO105 (*(__IO uint32_t*)0x400003A4U) /**< (HSMCI) FIFO Memory Aperture0 105 */ +#define REG_HSMCI_FIFO106 (*(__IO uint32_t*)0x400003A8U) /**< (HSMCI) FIFO Memory Aperture0 106 */ +#define REG_HSMCI_FIFO107 (*(__IO uint32_t*)0x400003ACU) /**< (HSMCI) FIFO Memory Aperture0 107 */ +#define REG_HSMCI_FIFO108 (*(__IO uint32_t*)0x400003B0U) /**< (HSMCI) FIFO Memory Aperture0 108 */ +#define REG_HSMCI_FIFO109 (*(__IO uint32_t*)0x400003B4U) /**< (HSMCI) FIFO Memory Aperture0 109 */ +#define REG_HSMCI_FIFO110 (*(__IO uint32_t*)0x400003B8U) /**< (HSMCI) FIFO Memory Aperture0 110 */ +#define REG_HSMCI_FIFO111 (*(__IO uint32_t*)0x400003BCU) /**< (HSMCI) FIFO Memory Aperture0 111 */ +#define REG_HSMCI_FIFO112 (*(__IO uint32_t*)0x400003C0U) /**< (HSMCI) FIFO Memory Aperture0 112 */ +#define REG_HSMCI_FIFO113 (*(__IO uint32_t*)0x400003C4U) /**< (HSMCI) FIFO Memory Aperture0 113 */ +#define REG_HSMCI_FIFO114 (*(__IO uint32_t*)0x400003C8U) /**< (HSMCI) FIFO Memory Aperture0 114 */ +#define REG_HSMCI_FIFO115 (*(__IO uint32_t*)0x400003CCU) /**< (HSMCI) FIFO Memory Aperture0 115 */ +#define REG_HSMCI_FIFO116 (*(__IO uint32_t*)0x400003D0U) /**< (HSMCI) FIFO Memory Aperture0 116 */ +#define REG_HSMCI_FIFO117 (*(__IO uint32_t*)0x400003D4U) /**< (HSMCI) FIFO Memory Aperture0 117 */ +#define REG_HSMCI_FIFO118 (*(__IO uint32_t*)0x400003D8U) /**< (HSMCI) FIFO Memory Aperture0 118 */ +#define REG_HSMCI_FIFO119 (*(__IO uint32_t*)0x400003DCU) /**< (HSMCI) FIFO Memory Aperture0 119 */ +#define REG_HSMCI_FIFO120 (*(__IO uint32_t*)0x400003E0U) /**< (HSMCI) FIFO Memory Aperture0 120 */ +#define REG_HSMCI_FIFO121 (*(__IO uint32_t*)0x400003E4U) /**< (HSMCI) FIFO Memory Aperture0 121 */ +#define REG_HSMCI_FIFO122 (*(__IO uint32_t*)0x400003E8U) /**< (HSMCI) FIFO Memory Aperture0 122 */ +#define REG_HSMCI_FIFO123 (*(__IO uint32_t*)0x400003ECU) /**< (HSMCI) FIFO Memory Aperture0 123 */ +#define REG_HSMCI_FIFO124 (*(__IO uint32_t*)0x400003F0U) /**< (HSMCI) FIFO Memory Aperture0 124 */ +#define REG_HSMCI_FIFO125 (*(__IO uint32_t*)0x400003F4U) /**< (HSMCI) FIFO Memory Aperture0 125 */ +#define REG_HSMCI_FIFO126 (*(__IO uint32_t*)0x400003F8U) /**< (HSMCI) FIFO Memory Aperture0 126 */ +#define REG_HSMCI_FIFO127 (*(__IO uint32_t*)0x400003FCU) /**< (HSMCI) FIFO Memory Aperture0 127 */ +#define REG_HSMCI_FIFO128 (*(__IO uint32_t*)0x40000400U) /**< (HSMCI) FIFO Memory Aperture0 128 */ +#define REG_HSMCI_FIFO129 (*(__IO uint32_t*)0x40000404U) /**< (HSMCI) FIFO Memory Aperture0 129 */ +#define REG_HSMCI_FIFO130 (*(__IO uint32_t*)0x40000408U) /**< (HSMCI) FIFO Memory Aperture0 130 */ +#define REG_HSMCI_FIFO131 (*(__IO uint32_t*)0x4000040CU) /**< (HSMCI) FIFO Memory Aperture0 131 */ +#define REG_HSMCI_FIFO132 (*(__IO uint32_t*)0x40000410U) /**< (HSMCI) FIFO Memory Aperture0 132 */ +#define REG_HSMCI_FIFO133 (*(__IO uint32_t*)0x40000414U) /**< (HSMCI) FIFO Memory Aperture0 133 */ +#define REG_HSMCI_FIFO134 (*(__IO uint32_t*)0x40000418U) /**< (HSMCI) FIFO Memory Aperture0 134 */ +#define REG_HSMCI_FIFO135 (*(__IO uint32_t*)0x4000041CU) /**< (HSMCI) FIFO Memory Aperture0 135 */ +#define REG_HSMCI_FIFO136 (*(__IO uint32_t*)0x40000420U) /**< (HSMCI) FIFO Memory Aperture0 136 */ +#define REG_HSMCI_FIFO137 (*(__IO uint32_t*)0x40000424U) /**< (HSMCI) FIFO Memory Aperture0 137 */ +#define REG_HSMCI_FIFO138 (*(__IO uint32_t*)0x40000428U) /**< (HSMCI) FIFO Memory Aperture0 138 */ +#define REG_HSMCI_FIFO139 (*(__IO uint32_t*)0x4000042CU) /**< (HSMCI) FIFO Memory Aperture0 139 */ +#define REG_HSMCI_FIFO140 (*(__IO uint32_t*)0x40000430U) /**< (HSMCI) FIFO Memory Aperture0 140 */ +#define REG_HSMCI_FIFO141 (*(__IO uint32_t*)0x40000434U) /**< (HSMCI) FIFO Memory Aperture0 141 */ +#define REG_HSMCI_FIFO142 (*(__IO uint32_t*)0x40000438U) /**< (HSMCI) FIFO Memory Aperture0 142 */ +#define REG_HSMCI_FIFO143 (*(__IO uint32_t*)0x4000043CU) /**< (HSMCI) FIFO Memory Aperture0 143 */ +#define REG_HSMCI_FIFO144 (*(__IO uint32_t*)0x40000440U) /**< (HSMCI) FIFO Memory Aperture0 144 */ +#define REG_HSMCI_FIFO145 (*(__IO uint32_t*)0x40000444U) /**< (HSMCI) FIFO Memory Aperture0 145 */ +#define REG_HSMCI_FIFO146 (*(__IO uint32_t*)0x40000448U) /**< (HSMCI) FIFO Memory Aperture0 146 */ +#define REG_HSMCI_FIFO147 (*(__IO uint32_t*)0x4000044CU) /**< (HSMCI) FIFO Memory Aperture0 147 */ +#define REG_HSMCI_FIFO148 (*(__IO uint32_t*)0x40000450U) /**< (HSMCI) FIFO Memory Aperture0 148 */ +#define REG_HSMCI_FIFO149 (*(__IO uint32_t*)0x40000454U) /**< (HSMCI) FIFO Memory Aperture0 149 */ +#define REG_HSMCI_FIFO150 (*(__IO uint32_t*)0x40000458U) /**< (HSMCI) FIFO Memory Aperture0 150 */ +#define REG_HSMCI_FIFO151 (*(__IO uint32_t*)0x4000045CU) /**< (HSMCI) FIFO Memory Aperture0 151 */ +#define REG_HSMCI_FIFO152 (*(__IO uint32_t*)0x40000460U) /**< (HSMCI) FIFO Memory Aperture0 152 */ +#define REG_HSMCI_FIFO153 (*(__IO uint32_t*)0x40000464U) /**< (HSMCI) FIFO Memory Aperture0 153 */ +#define REG_HSMCI_FIFO154 (*(__IO uint32_t*)0x40000468U) /**< (HSMCI) FIFO Memory Aperture0 154 */ +#define REG_HSMCI_FIFO155 (*(__IO uint32_t*)0x4000046CU) /**< (HSMCI) FIFO Memory Aperture0 155 */ +#define REG_HSMCI_FIFO156 (*(__IO uint32_t*)0x40000470U) /**< (HSMCI) FIFO Memory Aperture0 156 */ +#define REG_HSMCI_FIFO157 (*(__IO uint32_t*)0x40000474U) /**< (HSMCI) FIFO Memory Aperture0 157 */ +#define REG_HSMCI_FIFO158 (*(__IO uint32_t*)0x40000478U) /**< (HSMCI) FIFO Memory Aperture0 158 */ +#define REG_HSMCI_FIFO159 (*(__IO uint32_t*)0x4000047CU) /**< (HSMCI) FIFO Memory Aperture0 159 */ +#define REG_HSMCI_FIFO160 (*(__IO uint32_t*)0x40000480U) /**< (HSMCI) FIFO Memory Aperture0 160 */ +#define REG_HSMCI_FIFO161 (*(__IO uint32_t*)0x40000484U) /**< (HSMCI) FIFO Memory Aperture0 161 */ +#define REG_HSMCI_FIFO162 (*(__IO uint32_t*)0x40000488U) /**< (HSMCI) FIFO Memory Aperture0 162 */ +#define REG_HSMCI_FIFO163 (*(__IO uint32_t*)0x4000048CU) /**< (HSMCI) FIFO Memory Aperture0 163 */ +#define REG_HSMCI_FIFO164 (*(__IO uint32_t*)0x40000490U) /**< (HSMCI) FIFO Memory Aperture0 164 */ +#define REG_HSMCI_FIFO165 (*(__IO uint32_t*)0x40000494U) /**< (HSMCI) FIFO Memory Aperture0 165 */ +#define REG_HSMCI_FIFO166 (*(__IO uint32_t*)0x40000498U) /**< (HSMCI) FIFO Memory Aperture0 166 */ +#define REG_HSMCI_FIFO167 (*(__IO uint32_t*)0x4000049CU) /**< (HSMCI) FIFO Memory Aperture0 167 */ +#define REG_HSMCI_FIFO168 (*(__IO uint32_t*)0x400004A0U) /**< (HSMCI) FIFO Memory Aperture0 168 */ +#define REG_HSMCI_FIFO169 (*(__IO uint32_t*)0x400004A4U) /**< (HSMCI) FIFO Memory Aperture0 169 */ +#define REG_HSMCI_FIFO170 (*(__IO uint32_t*)0x400004A8U) /**< (HSMCI) FIFO Memory Aperture0 170 */ +#define REG_HSMCI_FIFO171 (*(__IO uint32_t*)0x400004ACU) /**< (HSMCI) FIFO Memory Aperture0 171 */ +#define REG_HSMCI_FIFO172 (*(__IO uint32_t*)0x400004B0U) /**< (HSMCI) FIFO Memory Aperture0 172 */ +#define REG_HSMCI_FIFO173 (*(__IO uint32_t*)0x400004B4U) /**< (HSMCI) FIFO Memory Aperture0 173 */ +#define REG_HSMCI_FIFO174 (*(__IO uint32_t*)0x400004B8U) /**< (HSMCI) FIFO Memory Aperture0 174 */ +#define REG_HSMCI_FIFO175 (*(__IO uint32_t*)0x400004BCU) /**< (HSMCI) FIFO Memory Aperture0 175 */ +#define REG_HSMCI_FIFO176 (*(__IO uint32_t*)0x400004C0U) /**< (HSMCI) FIFO Memory Aperture0 176 */ +#define REG_HSMCI_FIFO177 (*(__IO uint32_t*)0x400004C4U) /**< (HSMCI) FIFO Memory Aperture0 177 */ +#define REG_HSMCI_FIFO178 (*(__IO uint32_t*)0x400004C8U) /**< (HSMCI) FIFO Memory Aperture0 178 */ +#define REG_HSMCI_FIFO179 (*(__IO uint32_t*)0x400004CCU) /**< (HSMCI) FIFO Memory Aperture0 179 */ +#define REG_HSMCI_FIFO180 (*(__IO uint32_t*)0x400004D0U) /**< (HSMCI) FIFO Memory Aperture0 180 */ +#define REG_HSMCI_FIFO181 (*(__IO uint32_t*)0x400004D4U) /**< (HSMCI) FIFO Memory Aperture0 181 */ +#define REG_HSMCI_FIFO182 (*(__IO uint32_t*)0x400004D8U) /**< (HSMCI) FIFO Memory Aperture0 182 */ +#define REG_HSMCI_FIFO183 (*(__IO uint32_t*)0x400004DCU) /**< (HSMCI) FIFO Memory Aperture0 183 */ +#define REG_HSMCI_FIFO184 (*(__IO uint32_t*)0x400004E0U) /**< (HSMCI) FIFO Memory Aperture0 184 */ +#define REG_HSMCI_FIFO185 (*(__IO uint32_t*)0x400004E4U) /**< (HSMCI) FIFO Memory Aperture0 185 */ +#define REG_HSMCI_FIFO186 (*(__IO uint32_t*)0x400004E8U) /**< (HSMCI) FIFO Memory Aperture0 186 */ +#define REG_HSMCI_FIFO187 (*(__IO uint32_t*)0x400004ECU) /**< (HSMCI) FIFO Memory Aperture0 187 */ +#define REG_HSMCI_FIFO188 (*(__IO uint32_t*)0x400004F0U) /**< (HSMCI) FIFO Memory Aperture0 188 */ +#define REG_HSMCI_FIFO189 (*(__IO uint32_t*)0x400004F4U) /**< (HSMCI) FIFO Memory Aperture0 189 */ +#define REG_HSMCI_FIFO190 (*(__IO uint32_t*)0x400004F8U) /**< (HSMCI) FIFO Memory Aperture0 190 */ +#define REG_HSMCI_FIFO191 (*(__IO uint32_t*)0x400004FCU) /**< (HSMCI) FIFO Memory Aperture0 191 */ +#define REG_HSMCI_FIFO192 (*(__IO uint32_t*)0x40000500U) /**< (HSMCI) FIFO Memory Aperture0 192 */ +#define REG_HSMCI_FIFO193 (*(__IO uint32_t*)0x40000504U) /**< (HSMCI) FIFO Memory Aperture0 193 */ +#define REG_HSMCI_FIFO194 (*(__IO uint32_t*)0x40000508U) /**< (HSMCI) FIFO Memory Aperture0 194 */ +#define REG_HSMCI_FIFO195 (*(__IO uint32_t*)0x4000050CU) /**< (HSMCI) FIFO Memory Aperture0 195 */ +#define REG_HSMCI_FIFO196 (*(__IO uint32_t*)0x40000510U) /**< (HSMCI) FIFO Memory Aperture0 196 */ +#define REG_HSMCI_FIFO197 (*(__IO uint32_t*)0x40000514U) /**< (HSMCI) FIFO Memory Aperture0 197 */ +#define REG_HSMCI_FIFO198 (*(__IO uint32_t*)0x40000518U) /**< (HSMCI) FIFO Memory Aperture0 198 */ +#define REG_HSMCI_FIFO199 (*(__IO uint32_t*)0x4000051CU) /**< (HSMCI) FIFO Memory Aperture0 199 */ +#define REG_HSMCI_FIFO200 (*(__IO uint32_t*)0x40000520U) /**< (HSMCI) FIFO Memory Aperture0 200 */ +#define REG_HSMCI_FIFO201 (*(__IO uint32_t*)0x40000524U) /**< (HSMCI) FIFO Memory Aperture0 201 */ +#define REG_HSMCI_FIFO202 (*(__IO uint32_t*)0x40000528U) /**< (HSMCI) FIFO Memory Aperture0 202 */ +#define REG_HSMCI_FIFO203 (*(__IO uint32_t*)0x4000052CU) /**< (HSMCI) FIFO Memory Aperture0 203 */ +#define REG_HSMCI_FIFO204 (*(__IO uint32_t*)0x40000530U) /**< (HSMCI) FIFO Memory Aperture0 204 */ +#define REG_HSMCI_FIFO205 (*(__IO uint32_t*)0x40000534U) /**< (HSMCI) FIFO Memory Aperture0 205 */ +#define REG_HSMCI_FIFO206 (*(__IO uint32_t*)0x40000538U) /**< (HSMCI) FIFO Memory Aperture0 206 */ +#define REG_HSMCI_FIFO207 (*(__IO uint32_t*)0x4000053CU) /**< (HSMCI) FIFO Memory Aperture0 207 */ +#define REG_HSMCI_FIFO208 (*(__IO uint32_t*)0x40000540U) /**< (HSMCI) FIFO Memory Aperture0 208 */ +#define REG_HSMCI_FIFO209 (*(__IO uint32_t*)0x40000544U) /**< (HSMCI) FIFO Memory Aperture0 209 */ +#define REG_HSMCI_FIFO210 (*(__IO uint32_t*)0x40000548U) /**< (HSMCI) FIFO Memory Aperture0 210 */ +#define REG_HSMCI_FIFO211 (*(__IO uint32_t*)0x4000054CU) /**< (HSMCI) FIFO Memory Aperture0 211 */ +#define REG_HSMCI_FIFO212 (*(__IO uint32_t*)0x40000550U) /**< (HSMCI) FIFO Memory Aperture0 212 */ +#define REG_HSMCI_FIFO213 (*(__IO uint32_t*)0x40000554U) /**< (HSMCI) FIFO Memory Aperture0 213 */ +#define REG_HSMCI_FIFO214 (*(__IO uint32_t*)0x40000558U) /**< (HSMCI) FIFO Memory Aperture0 214 */ +#define REG_HSMCI_FIFO215 (*(__IO uint32_t*)0x4000055CU) /**< (HSMCI) FIFO Memory Aperture0 215 */ +#define REG_HSMCI_FIFO216 (*(__IO uint32_t*)0x40000560U) /**< (HSMCI) FIFO Memory Aperture0 216 */ +#define REG_HSMCI_FIFO217 (*(__IO uint32_t*)0x40000564U) /**< (HSMCI) FIFO Memory Aperture0 217 */ +#define REG_HSMCI_FIFO218 (*(__IO uint32_t*)0x40000568U) /**< (HSMCI) FIFO Memory Aperture0 218 */ +#define REG_HSMCI_FIFO219 (*(__IO uint32_t*)0x4000056CU) /**< (HSMCI) FIFO Memory Aperture0 219 */ +#define REG_HSMCI_FIFO220 (*(__IO uint32_t*)0x40000570U) /**< (HSMCI) FIFO Memory Aperture0 220 */ +#define REG_HSMCI_FIFO221 (*(__IO uint32_t*)0x40000574U) /**< (HSMCI) FIFO Memory Aperture0 221 */ +#define REG_HSMCI_FIFO222 (*(__IO uint32_t*)0x40000578U) /**< (HSMCI) FIFO Memory Aperture0 222 */ +#define REG_HSMCI_FIFO223 (*(__IO uint32_t*)0x4000057CU) /**< (HSMCI) FIFO Memory Aperture0 223 */ +#define REG_HSMCI_FIFO224 (*(__IO uint32_t*)0x40000580U) /**< (HSMCI) FIFO Memory Aperture0 224 */ +#define REG_HSMCI_FIFO225 (*(__IO uint32_t*)0x40000584U) /**< (HSMCI) FIFO Memory Aperture0 225 */ +#define REG_HSMCI_FIFO226 (*(__IO uint32_t*)0x40000588U) /**< (HSMCI) FIFO Memory Aperture0 226 */ +#define REG_HSMCI_FIFO227 (*(__IO uint32_t*)0x4000058CU) /**< (HSMCI) FIFO Memory Aperture0 227 */ +#define REG_HSMCI_FIFO228 (*(__IO uint32_t*)0x40000590U) /**< (HSMCI) FIFO Memory Aperture0 228 */ +#define REG_HSMCI_FIFO229 (*(__IO uint32_t*)0x40000594U) /**< (HSMCI) FIFO Memory Aperture0 229 */ +#define REG_HSMCI_FIFO230 (*(__IO uint32_t*)0x40000598U) /**< (HSMCI) FIFO Memory Aperture0 230 */ +#define REG_HSMCI_FIFO231 (*(__IO uint32_t*)0x4000059CU) /**< (HSMCI) FIFO Memory Aperture0 231 */ +#define REG_HSMCI_FIFO232 (*(__IO uint32_t*)0x400005A0U) /**< (HSMCI) FIFO Memory Aperture0 232 */ +#define REG_HSMCI_FIFO233 (*(__IO uint32_t*)0x400005A4U) /**< (HSMCI) FIFO Memory Aperture0 233 */ +#define REG_HSMCI_FIFO234 (*(__IO uint32_t*)0x400005A8U) /**< (HSMCI) FIFO Memory Aperture0 234 */ +#define REG_HSMCI_FIFO235 (*(__IO uint32_t*)0x400005ACU) /**< (HSMCI) FIFO Memory Aperture0 235 */ +#define REG_HSMCI_FIFO236 (*(__IO uint32_t*)0x400005B0U) /**< (HSMCI) FIFO Memory Aperture0 236 */ +#define REG_HSMCI_FIFO237 (*(__IO uint32_t*)0x400005B4U) /**< (HSMCI) FIFO Memory Aperture0 237 */ +#define REG_HSMCI_FIFO238 (*(__IO uint32_t*)0x400005B8U) /**< (HSMCI) FIFO Memory Aperture0 238 */ +#define REG_HSMCI_FIFO239 (*(__IO uint32_t*)0x400005BCU) /**< (HSMCI) FIFO Memory Aperture0 239 */ +#define REG_HSMCI_FIFO240 (*(__IO uint32_t*)0x400005C0U) /**< (HSMCI) FIFO Memory Aperture0 240 */ +#define REG_HSMCI_FIFO241 (*(__IO uint32_t*)0x400005C4U) /**< (HSMCI) FIFO Memory Aperture0 241 */ +#define REG_HSMCI_FIFO242 (*(__IO uint32_t*)0x400005C8U) /**< (HSMCI) FIFO Memory Aperture0 242 */ +#define REG_HSMCI_FIFO243 (*(__IO uint32_t*)0x400005CCU) /**< (HSMCI) FIFO Memory Aperture0 243 */ +#define REG_HSMCI_FIFO244 (*(__IO uint32_t*)0x400005D0U) /**< (HSMCI) FIFO Memory Aperture0 244 */ +#define REG_HSMCI_FIFO245 (*(__IO uint32_t*)0x400005D4U) /**< (HSMCI) FIFO Memory Aperture0 245 */ +#define REG_HSMCI_FIFO246 (*(__IO uint32_t*)0x400005D8U) /**< (HSMCI) FIFO Memory Aperture0 246 */ +#define REG_HSMCI_FIFO247 (*(__IO uint32_t*)0x400005DCU) /**< (HSMCI) FIFO Memory Aperture0 247 */ +#define REG_HSMCI_FIFO248 (*(__IO uint32_t*)0x400005E0U) /**< (HSMCI) FIFO Memory Aperture0 248 */ +#define REG_HSMCI_FIFO249 (*(__IO uint32_t*)0x400005E4U) /**< (HSMCI) FIFO Memory Aperture0 249 */ +#define REG_HSMCI_FIFO250 (*(__IO uint32_t*)0x400005E8U) /**< (HSMCI) FIFO Memory Aperture0 250 */ +#define REG_HSMCI_FIFO251 (*(__IO uint32_t*)0x400005ECU) /**< (HSMCI) FIFO Memory Aperture0 251 */ +#define REG_HSMCI_FIFO252 (*(__IO uint32_t*)0x400005F0U) /**< (HSMCI) FIFO Memory Aperture0 252 */ +#define REG_HSMCI_FIFO253 (*(__IO uint32_t*)0x400005F4U) /**< (HSMCI) FIFO Memory Aperture0 253 */ +#define REG_HSMCI_FIFO254 (*(__IO uint32_t*)0x400005F8U) /**< (HSMCI) FIFO Memory Aperture0 254 */ +#define REG_HSMCI_FIFO255 (*(__IO uint32_t*)0x400005FCU) /**< (HSMCI) FIFO Memory Aperture0 255 */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for HSMCI peripheral ========== */ +#define HSMCI_DMAC_ID_RX 0 +#define HSMCI_DMAC_ID_TX 0 +#define HSMCI_INSTANCE_ID 18 +#define HSMCI_CLOCK_ID 18 + +#endif /* _SAME70_HSMCI_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/i2sc0.h b/bsp/microchip/same70/bsp/same70b/include/instance/i2sc0.h new file mode 100644 index 0000000000..7d5b074fee --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/i2sc0.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Instance description for I2SC0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_I2SC0_INSTANCE_H_ +#define _SAME70_I2SC0_INSTANCE_H_ + +/* ========== Register definition for I2SC0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_I2SC0_CR (0x4008C000) /**< (I2SC0) Control Register */ +#define REG_I2SC0_MR (0x4008C004) /**< (I2SC0) Mode Register */ +#define REG_I2SC0_SR (0x4008C008) /**< (I2SC0) Status Register */ +#define REG_I2SC0_SCR (0x4008C00C) /**< (I2SC0) Status Clear Register */ +#define REG_I2SC0_SSR (0x4008C010) /**< (I2SC0) Status Set Register */ +#define REG_I2SC0_IER (0x4008C014) /**< (I2SC0) Interrupt Enable Register */ +#define REG_I2SC0_IDR (0x4008C018) /**< (I2SC0) Interrupt Disable Register */ +#define REG_I2SC0_IMR (0x4008C01C) /**< (I2SC0) Interrupt Mask Register */ +#define REG_I2SC0_RHR (0x4008C020) /**< (I2SC0) Receiver Holding Register */ +#define REG_I2SC0_THR (0x4008C024) /**< (I2SC0) Transmitter Holding Register */ + +#else + +#define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */ +#define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< (I2SC0) Mode Register */ +#define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< (I2SC0) Status Register */ +#define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */ +#define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */ +#define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Register */ +#define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Register */ +#define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< (I2SC0) Interrupt Mask Register */ +#define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< (I2SC0) Receiver Holding Register */ +#define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for I2SC0 peripheral ========== */ +#define I2SC0_INSTANCE_ID 69 +#define I2SC0_CLOCK_ID 69 +#define I2SC0_DMAC_ID_TX_LEFT 44 +#define I2SC0_DMAC_ID_RX_LEFT 45 +#define I2SC0_DMAC_ID_TX_RIGHT 48 +#define I2SC0_DMAC_ID_RX_RIGHT 49 + +#endif /* _SAME70_I2SC0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/i2sc1.h b/bsp/microchip/same70/bsp/same70b/include/instance/i2sc1.h new file mode 100644 index 0000000000..0b0ccc3de6 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/i2sc1.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Instance description for I2SC1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_I2SC1_INSTANCE_H_ +#define _SAME70_I2SC1_INSTANCE_H_ + +/* ========== Register definition for I2SC1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_I2SC1_CR (0x40090000) /**< (I2SC1) Control Register */ +#define REG_I2SC1_MR (0x40090004) /**< (I2SC1) Mode Register */ +#define REG_I2SC1_SR (0x40090008) /**< (I2SC1) Status Register */ +#define REG_I2SC1_SCR (0x4009000C) /**< (I2SC1) Status Clear Register */ +#define REG_I2SC1_SSR (0x40090010) /**< (I2SC1) Status Set Register */ +#define REG_I2SC1_IER (0x40090014) /**< (I2SC1) Interrupt Enable Register */ +#define REG_I2SC1_IDR (0x40090018) /**< (I2SC1) Interrupt Disable Register */ +#define REG_I2SC1_IMR (0x4009001C) /**< (I2SC1) Interrupt Mask Register */ +#define REG_I2SC1_RHR (0x40090020) /**< (I2SC1) Receiver Holding Register */ +#define REG_I2SC1_THR (0x40090024) /**< (I2SC1) Transmitter Holding Register */ + +#else + +#define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< (I2SC1) Control Register */ +#define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< (I2SC1) Mode Register */ +#define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< (I2SC1) Status Register */ +#define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< (I2SC1) Status Clear Register */ +#define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< (I2SC1) Status Set Register */ +#define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< (I2SC1) Interrupt Enable Register */ +#define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< (I2SC1) Interrupt Disable Register */ +#define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< (I2SC1) Interrupt Mask Register */ +#define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< (I2SC1) Receiver Holding Register */ +#define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< (I2SC1) Transmitter Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for I2SC1 peripheral ========== */ +#define I2SC1_INSTANCE_ID 70 +#define I2SC1_CLOCK_ID 70 +#define I2SC1_DMAC_ID_TX_LEFT 46 +#define I2SC1_DMAC_ID_RX_LEFT 47 +#define I2SC1_DMAC_ID_TX_RIGHT 50 +#define I2SC1_DMAC_ID_RX_RIGHT 51 + +#endif /* _SAME70_I2SC1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/icm.h b/bsp/microchip/same70/bsp/same70b/include/instance/icm.h new file mode 100644 index 0000000000..5aa354ad58 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/icm.h @@ -0,0 +1,85 @@ +/** + * \file + * + * \brief Instance description for ICM + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ICM_INSTANCE_H_ +#define _SAME70_ICM_INSTANCE_H_ + +/* ========== Register definition for ICM peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_ICM_CFG (0x40048000) /**< (ICM) Configuration Register */ +#define REG_ICM_CTRL (0x40048004) /**< (ICM) Control Register */ +#define REG_ICM_SR (0x40048008) /**< (ICM) Status Register */ +#define REG_ICM_IER (0x40048010) /**< (ICM) Interrupt Enable Register */ +#define REG_ICM_IDR (0x40048014) /**< (ICM) Interrupt Disable Register */ +#define REG_ICM_IMR (0x40048018) /**< (ICM) Interrupt Mask Register */ +#define REG_ICM_ISR (0x4004801C) /**< (ICM) Interrupt Status Register */ +#define REG_ICM_UASR (0x40048020) /**< (ICM) Undefined Access Status Register */ +#define REG_ICM_DSCR (0x40048030) /**< (ICM) Region Descriptor Area Start Address Register */ +#define REG_ICM_HASH (0x40048034) /**< (ICM) Region Hash Area Start Address Register */ +#define REG_ICM_UIHVAL (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */ +#define REG_ICM_UIHVAL0 (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */ +#define REG_ICM_UIHVAL1 (0x4004803C) /**< (ICM) User Initial Hash Value 0 Register 1 */ +#define REG_ICM_UIHVAL2 (0x40048040) /**< (ICM) User Initial Hash Value 0 Register 2 */ +#define REG_ICM_UIHVAL3 (0x40048044) /**< (ICM) User Initial Hash Value 0 Register 3 */ +#define REG_ICM_UIHVAL4 (0x40048048) /**< (ICM) User Initial Hash Value 0 Register 4 */ +#define REG_ICM_UIHVAL5 (0x4004804C) /**< (ICM) User Initial Hash Value 0 Register 5 */ +#define REG_ICM_UIHVAL6 (0x40048050) /**< (ICM) User Initial Hash Value 0 Register 6 */ +#define REG_ICM_UIHVAL7 (0x40048054) /**< (ICM) User Initial Hash Value 0 Register 7 */ + +#else + +#define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< (ICM) Configuration Register */ +#define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< (ICM) Control Register */ +#define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< (ICM) Status Register */ +#define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< (ICM) Interrupt Enable Register */ +#define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< (ICM) Interrupt Disable Register */ +#define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< (ICM) Interrupt Mask Register */ +#define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< (ICM) Interrupt Status Register */ +#define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< (ICM) Undefined Access Status Register */ +#define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< (ICM) Region Descriptor Area Start Address Register */ +#define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< (ICM) Region Hash Area Start Address Register */ +#define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */ +#define REG_ICM_UIHVAL0 (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */ +#define REG_ICM_UIHVAL1 (*(__O uint32_t*)0x4004803CU) /**< (ICM) User Initial Hash Value 0 Register 1 */ +#define REG_ICM_UIHVAL2 (*(__O uint32_t*)0x40048040U) /**< (ICM) User Initial Hash Value 0 Register 2 */ +#define REG_ICM_UIHVAL3 (*(__O uint32_t*)0x40048044U) /**< (ICM) User Initial Hash Value 0 Register 3 */ +#define REG_ICM_UIHVAL4 (*(__O uint32_t*)0x40048048U) /**< (ICM) User Initial Hash Value 0 Register 4 */ +#define REG_ICM_UIHVAL5 (*(__O uint32_t*)0x4004804CU) /**< (ICM) User Initial Hash Value 0 Register 5 */ +#define REG_ICM_UIHVAL6 (*(__O uint32_t*)0x40048050U) /**< (ICM) User Initial Hash Value 0 Register 6 */ +#define REG_ICM_UIHVAL7 (*(__O uint32_t*)0x40048054U) /**< (ICM) User Initial Hash Value 0 Register 7 */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for ICM peripheral ========== */ +#define ICM_INSTANCE_ID 32 +#define ICM_CLOCK_ID 32 + +#endif /* _SAME70_ICM_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/isi.h b/bsp/microchip/same70/bsp/same70b/include/instance/isi.h new file mode 100644 index 0000000000..08ec3b7650 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/isi.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Instance description for ISI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_ISI_INSTANCE_H_ +#define _SAME70_ISI_INSTANCE_H_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_ISI_CFG1 (0x4004C000) /**< (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (0x4004C004) /**< (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (0x4004C008) /**< (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (0x4004C00C) /**< (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (0x4004C010) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (0x4004C014) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (0x4004C018) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (0x4004C01C) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (0x4004C020) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (0x4004C024) /**< (ISI) ISI Control Register */ +#define REG_ISI_SR (0x4004C028) /**< (ISI) ISI Status Register */ +#define REG_ISI_IER (0x4004C02C) /**< (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (0x4004C030) /**< (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (0x4004C034) /**< (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (0x4004C038) /**< (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (0x4004C03C) /**< (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (0x4004C040) /**< (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (0x4004C044) /**< (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (0x4004C048) /**< (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (0x4004C04C) /**< (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (0x4004C050) /**< (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (0x4004C054) /**< (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (0x4004C058) /**< (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPMR (0x4004C0E4) /**< (ISI) Write Protection Mode Register */ +#define REG_ISI_WPSR (0x4004C0E8) /**< (ISI) Write Protection Status Register */ + +#else + +#define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< (ISI) ISI Control Register */ +#define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< (ISI) ISI Status Register */ +#define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< (ISI) Write Protection Mode Register */ +#define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< (ISI) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for ISI peripheral ========== */ +#define ISI_INSTANCE_ID 59 +#define ISI_CLOCK_ID 59 + +#endif /* _SAME70_ISI_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/matrix.h b/bsp/microchip/same70/bsp/same70b/include/instance/matrix.h new file mode 100644 index 0000000000..e0886a0cfe --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/matrix.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Instance description for MATRIX + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_MATRIX_INSTANCE_H_ +#define _SAME70_MATRIX_INSTANCE_H_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_MATRIX_PRAS0 (0x40088080) /**< (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (0x40088084) /**< (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (0x40088088) /**< (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (0x4008808C) /**< (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (0x40088090) /**< (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (0x40088094) /**< (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (0x40088098) /**< (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (0x4008809C) /**< (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (0x400880A0) /**< (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (0x400880A4) /**< (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (0x400880A8) /**< (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (0x400880AC) /**< (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (0x400880B0) /**< (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (0x400880B4) /**< (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (0x400880B8) /**< (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (0x400880BC) /**< (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (0x400880C0) /**< (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (0x400880C4) /**< (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_MCFG (0x40088000) /**< (MATRIX) Master Configuration Register 0 */ +#define REG_MATRIX_MCFG0 (0x40088000) /**< (MATRIX) Master Configuration Register 0 */ +#define REG_MATRIX_MCFG1 (0x40088004) /**< (MATRIX) Master Configuration Register 1 */ +#define REG_MATRIX_MCFG2 (0x40088008) /**< (MATRIX) Master Configuration Register 2 */ +#define REG_MATRIX_MCFG3 (0x4008800C) /**< (MATRIX) Master Configuration Register 3 */ +#define REG_MATRIX_MCFG4 (0x40088010) /**< (MATRIX) Master Configuration Register 4 */ +#define REG_MATRIX_MCFG5 (0x40088014) /**< (MATRIX) Master Configuration Register 5 */ +#define REG_MATRIX_MCFG6 (0x40088018) /**< (MATRIX) Master Configuration Register 6 */ +#define REG_MATRIX_MCFG7 (0x4008801C) /**< (MATRIX) Master Configuration Register 7 */ +#define REG_MATRIX_MCFG8 (0x40088020) /**< (MATRIX) Master Configuration Register 8 */ +#define REG_MATRIX_MCFG9 (0x40088024) /**< (MATRIX) Master Configuration Register 9 */ +#define REG_MATRIX_MCFG10 (0x40088028) /**< (MATRIX) Master Configuration Register 10 */ +#define REG_MATRIX_MCFG11 (0x4008802C) /**< (MATRIX) Master Configuration Register 11 */ +#define REG_MATRIX_MCFG12 (0x40088030) /**< (MATRIX) Master Configuration Register 12 */ +#define REG_MATRIX_SCFG (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */ +#define REG_MATRIX_SCFG0 (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */ +#define REG_MATRIX_SCFG1 (0x40088044) /**< (MATRIX) Slave Configuration Register 1 */ +#define REG_MATRIX_SCFG2 (0x40088048) /**< (MATRIX) Slave Configuration Register 2 */ +#define REG_MATRIX_SCFG3 (0x4008804C) /**< (MATRIX) Slave Configuration Register 3 */ +#define REG_MATRIX_SCFG4 (0x40088050) /**< (MATRIX) Slave Configuration Register 4 */ +#define REG_MATRIX_SCFG5 (0x40088054) /**< (MATRIX) Slave Configuration Register 5 */ +#define REG_MATRIX_SCFG6 (0x40088058) /**< (MATRIX) Slave Configuration Register 6 */ +#define REG_MATRIX_SCFG7 (0x4008805C) /**< (MATRIX) Slave Configuration Register 7 */ +#define REG_MATRIX_SCFG8 (0x40088060) /**< (MATRIX) Slave Configuration Register 8 */ +#define REG_MATRIX_MRCR (0x40088100) /**< (MATRIX) Master Remap Control Register */ +#define REG_CCFG_CAN0 (0x40088110) /**< (MATRIX) CAN0 Configuration Register */ +#define REG_CCFG_SYSIO (0x40088114) /**< (MATRIX) System I/O and CAN1 Configuration Register */ +#define REG_CCFG_PCCR (0x40088118) /**< (MATRIX) Peripheral Clock Configuration Register */ +#define REG_CCFG_DYNCKG (0x4008811C) /**< (MATRIX) Dynamic Clock Gating Register */ +#define REG_CCFG_SMCNFCS (0x40088124) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */ +#define REG_MATRIX_WPMR (0x400881E4) /**< (MATRIX) Write Protection Mode Register */ +#define REG_MATRIX_WPSR (0x400881E8) /**< (MATRIX) Write Protection Status Register */ + +#else + +#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */ +#define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */ +#define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< (MATRIX) Master Configuration Register 1 */ +#define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< (MATRIX) Master Configuration Register 2 */ +#define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< (MATRIX) Master Configuration Register 3 */ +#define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< (MATRIX) Master Configuration Register 4 */ +#define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< (MATRIX) Master Configuration Register 5 */ +#define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< (MATRIX) Master Configuration Register 6 */ +#define REG_MATRIX_MCFG7 (*(__IO uint32_t*)0x4008801CU) /**< (MATRIX) Master Configuration Register 7 */ +#define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< (MATRIX) Master Configuration Register 8 */ +#define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) /**< (MATRIX) Master Configuration Register 9 */ +#define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) /**< (MATRIX) Master Configuration Register 10 */ +#define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) /**< (MATRIX) Master Configuration Register 11 */ +#define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) /**< (MATRIX) Master Configuration Register 12 */ +#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */ +#define REG_MATRIX_SCFG0 (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */ +#define REG_MATRIX_SCFG1 (*(__IO uint32_t*)0x40088044U) /**< (MATRIX) Slave Configuration Register 1 */ +#define REG_MATRIX_SCFG2 (*(__IO uint32_t*)0x40088048U) /**< (MATRIX) Slave Configuration Register 2 */ +#define REG_MATRIX_SCFG3 (*(__IO uint32_t*)0x4008804CU) /**< (MATRIX) Slave Configuration Register 3 */ +#define REG_MATRIX_SCFG4 (*(__IO uint32_t*)0x40088050U) /**< (MATRIX) Slave Configuration Register 4 */ +#define REG_MATRIX_SCFG5 (*(__IO uint32_t*)0x40088054U) /**< (MATRIX) Slave Configuration Register 5 */ +#define REG_MATRIX_SCFG6 (*(__IO uint32_t*)0x40088058U) /**< (MATRIX) Slave Configuration Register 6 */ +#define REG_MATRIX_SCFG7 (*(__IO uint32_t*)0x4008805CU) /**< (MATRIX) Slave Configuration Register 7 */ +#define REG_MATRIX_SCFG8 (*(__IO uint32_t*)0x40088060U) /**< (MATRIX) Slave Configuration Register 8 */ +#define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< (MATRIX) Master Remap Control Register */ +#define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< (MATRIX) CAN0 Configuration Register */ +#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< (MATRIX) System I/O and CAN1 Configuration Register */ +#define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) /**< (MATRIX) Peripheral Clock Configuration Register */ +#define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) /**< (MATRIX) Dynamic Clock Gating Register */ +#define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */ +#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< (MATRIX) Write Protection Mode Register */ +#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< (MATRIX) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_MATRIX_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/mcan0.h b/bsp/microchip/same70/bsp/same70b/include/instance/mcan0.h new file mode 100644 index 0000000000..0f16b8997e --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/mcan0.h @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief Instance description for MCAN0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_MCAN0_INSTANCE_H_ +#define _SAME70_MCAN0_INSTANCE_H_ + +/* ========== Register definition for MCAN0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_MCAN0_CREL (0x40030000) /**< (MCAN0) Core Release Register */ +#define REG_MCAN0_ENDN (0x40030004) /**< (MCAN0) Endian Register */ +#define REG_MCAN0_CUST (0x40030008) /**< (MCAN0) Customer Register */ +#define REG_MCAN0_DBTP (0x4003000C) /**< (MCAN0) Data Bit Timing and Prescaler Register */ +#define REG_MCAN0_TEST (0x40030010) /**< (MCAN0) Test Register */ +#define REG_MCAN0_RWD (0x40030014) /**< (MCAN0) RAM Watchdog Register */ +#define REG_MCAN0_CCCR (0x40030018) /**< (MCAN0) CC Control Register */ +#define REG_MCAN0_NBTP (0x4003001C) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */ +#define REG_MCAN0_TSCC (0x40030020) /**< (MCAN0) Timestamp Counter Configuration Register */ +#define REG_MCAN0_TSCV (0x40030024) /**< (MCAN0) Timestamp Counter Value Register */ +#define REG_MCAN0_TOCC (0x40030028) /**< (MCAN0) Timeout Counter Configuration Register */ +#define REG_MCAN0_TOCV (0x4003002C) /**< (MCAN0) Timeout Counter Value Register */ +#define REG_MCAN0_ECR (0x40030040) /**< (MCAN0) Error Counter Register */ +#define REG_MCAN0_PSR (0x40030044) /**< (MCAN0) Protocol Status Register */ +#define REG_MCAN0_TDCR (0x40030048) /**< (MCAN0) Transmit Delay Compensation Register */ +#define REG_MCAN0_IR (0x40030050) /**< (MCAN0) Interrupt Register */ +#define REG_MCAN0_IE (0x40030054) /**< (MCAN0) Interrupt Enable Register */ +#define REG_MCAN0_ILS (0x40030058) /**< (MCAN0) Interrupt Line Select Register */ +#define REG_MCAN0_ILE (0x4003005C) /**< (MCAN0) Interrupt Line Enable Register */ +#define REG_MCAN0_GFC (0x40030080) /**< (MCAN0) Global Filter Configuration Register */ +#define REG_MCAN0_SIDFC (0x40030084) /**< (MCAN0) Standard ID Filter Configuration Register */ +#define REG_MCAN0_XIDFC (0x40030088) /**< (MCAN0) Extended ID Filter Configuration Register */ +#define REG_MCAN0_XIDAM (0x40030090) /**< (MCAN0) Extended ID AND Mask Register */ +#define REG_MCAN0_HPMS (0x40030094) /**< (MCAN0) High Priority Message Status Register */ +#define REG_MCAN0_NDAT1 (0x40030098) /**< (MCAN0) New Data 1 Register */ +#define REG_MCAN0_NDAT2 (0x4003009C) /**< (MCAN0) New Data 2 Register */ +#define REG_MCAN0_RXF0C (0x400300A0) /**< (MCAN0) Receive FIFO 0 Configuration Register */ +#define REG_MCAN0_RXF0S (0x400300A4) /**< (MCAN0) Receive FIFO 0 Status Register */ +#define REG_MCAN0_RXF0A (0x400300A8) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */ +#define REG_MCAN0_RXBC (0x400300AC) /**< (MCAN0) Receive Rx Buffer Configuration Register */ +#define REG_MCAN0_RXF1C (0x400300B0) /**< (MCAN0) Receive FIFO 1 Configuration Register */ +#define REG_MCAN0_RXF1S (0x400300B4) /**< (MCAN0) Receive FIFO 1 Status Register */ +#define REG_MCAN0_RXF1A (0x400300B8) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */ +#define REG_MCAN0_RXESC (0x400300BC) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ +#define REG_MCAN0_TXBC (0x400300C0) /**< (MCAN0) Transmit Buffer Configuration Register */ +#define REG_MCAN0_TXFQS (0x400300C4) /**< (MCAN0) Transmit FIFO/Queue Status Register */ +#define REG_MCAN0_TXESC (0x400300C8) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */ +#define REG_MCAN0_TXBRP (0x400300CC) /**< (MCAN0) Transmit Buffer Request Pending Register */ +#define REG_MCAN0_TXBAR (0x400300D0) /**< (MCAN0) Transmit Buffer Add Request Register */ +#define REG_MCAN0_TXBCR (0x400300D4) /**< (MCAN0) Transmit Buffer Cancellation Request Register */ +#define REG_MCAN0_TXBTO (0x400300D8) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */ +#define REG_MCAN0_TXBCF (0x400300DC) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */ +#define REG_MCAN0_TXBTIE (0x400300E0) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ +#define REG_MCAN0_TXBCIE (0x400300E4) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ +#define REG_MCAN0_TXEFC (0x400300F0) /**< (MCAN0) Transmit Event FIFO Configuration Register */ +#define REG_MCAN0_TXEFS (0x400300F4) /**< (MCAN0) Transmit Event FIFO Status Register */ +#define REG_MCAN0_TXEFA (0x400300F8) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */ + +#else + +#define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U) /**< (MCAN0) Core Release Register */ +#define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U) /**< (MCAN0) Endian Register */ +#define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< (MCAN0) Customer Register */ +#define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU) /**< (MCAN0) Data Bit Timing and Prescaler Register */ +#define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< (MCAN0) Test Register */ +#define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< (MCAN0) RAM Watchdog Register */ +#define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< (MCAN0) CC Control Register */ +#define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */ +#define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< (MCAN0) Timestamp Counter Configuration Register */ +#define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< (MCAN0) Timestamp Counter Value Register */ +#define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< (MCAN0) Timeout Counter Configuration Register */ +#define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< (MCAN0) Timeout Counter Value Register */ +#define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< (MCAN0) Error Counter Register */ +#define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< (MCAN0) Protocol Status Register */ +#define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U) /**< (MCAN0) Transmit Delay Compensation Register */ +#define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< (MCAN0) Interrupt Register */ +#define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< (MCAN0) Interrupt Enable Register */ +#define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< (MCAN0) Interrupt Line Select Register */ +#define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< (MCAN0) Interrupt Line Enable Register */ +#define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< (MCAN0) Global Filter Configuration Register */ +#define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< (MCAN0) Standard ID Filter Configuration Register */ +#define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< (MCAN0) Extended ID Filter Configuration Register */ +#define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< (MCAN0) Extended ID AND Mask Register */ +#define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< (MCAN0) High Priority Message Status Register */ +#define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< (MCAN0) New Data 1 Register */ +#define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< (MCAN0) New Data 2 Register */ +#define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< (MCAN0) Receive FIFO 0 Configuration Register */ +#define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< (MCAN0) Receive FIFO 0 Status Register */ +#define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */ +#define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< (MCAN0) Receive Rx Buffer Configuration Register */ +#define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< (MCAN0) Receive FIFO 1 Configuration Register */ +#define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< (MCAN0) Receive FIFO 1 Status Register */ +#define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */ +#define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ +#define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< (MCAN0) Transmit Buffer Configuration Register */ +#define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< (MCAN0) Transmit FIFO/Queue Status Register */ +#define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */ +#define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< (MCAN0) Transmit Buffer Request Pending Register */ +#define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< (MCAN0) Transmit Buffer Add Request Register */ +#define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< (MCAN0) Transmit Buffer Cancellation Request Register */ +#define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */ +#define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */ +#define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ +#define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ +#define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< (MCAN0) Transmit Event FIFO Configuration Register */ +#define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< (MCAN0) Transmit Event FIFO Status Register */ +#define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for MCAN0 peripheral ========== */ +#define MCAN0_INSTANCE_ID 35 +#define MCAN0_CLOCK_ID 35 + +#endif /* _SAME70_MCAN0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/mcan1.h b/bsp/microchip/same70/bsp/same70b/include/instance/mcan1.h new file mode 100644 index 0000000000..a3ac43b50a --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/mcan1.h @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief Instance description for MCAN1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_MCAN1_INSTANCE_H_ +#define _SAME70_MCAN1_INSTANCE_H_ + +/* ========== Register definition for MCAN1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_MCAN1_CREL (0x40034000) /**< (MCAN1) Core Release Register */ +#define REG_MCAN1_ENDN (0x40034004) /**< (MCAN1) Endian Register */ +#define REG_MCAN1_CUST (0x40034008) /**< (MCAN1) Customer Register */ +#define REG_MCAN1_DBTP (0x4003400C) /**< (MCAN1) Data Bit Timing and Prescaler Register */ +#define REG_MCAN1_TEST (0x40034010) /**< (MCAN1) Test Register */ +#define REG_MCAN1_RWD (0x40034014) /**< (MCAN1) RAM Watchdog Register */ +#define REG_MCAN1_CCCR (0x40034018) /**< (MCAN1) CC Control Register */ +#define REG_MCAN1_NBTP (0x4003401C) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */ +#define REG_MCAN1_TSCC (0x40034020) /**< (MCAN1) Timestamp Counter Configuration Register */ +#define REG_MCAN1_TSCV (0x40034024) /**< (MCAN1) Timestamp Counter Value Register */ +#define REG_MCAN1_TOCC (0x40034028) /**< (MCAN1) Timeout Counter Configuration Register */ +#define REG_MCAN1_TOCV (0x4003402C) /**< (MCAN1) Timeout Counter Value Register */ +#define REG_MCAN1_ECR (0x40034040) /**< (MCAN1) Error Counter Register */ +#define REG_MCAN1_PSR (0x40034044) /**< (MCAN1) Protocol Status Register */ +#define REG_MCAN1_TDCR (0x40034048) /**< (MCAN1) Transmit Delay Compensation Register */ +#define REG_MCAN1_IR (0x40034050) /**< (MCAN1) Interrupt Register */ +#define REG_MCAN1_IE (0x40034054) /**< (MCAN1) Interrupt Enable Register */ +#define REG_MCAN1_ILS (0x40034058) /**< (MCAN1) Interrupt Line Select Register */ +#define REG_MCAN1_ILE (0x4003405C) /**< (MCAN1) Interrupt Line Enable Register */ +#define REG_MCAN1_GFC (0x40034080) /**< (MCAN1) Global Filter Configuration Register */ +#define REG_MCAN1_SIDFC (0x40034084) /**< (MCAN1) Standard ID Filter Configuration Register */ +#define REG_MCAN1_XIDFC (0x40034088) /**< (MCAN1) Extended ID Filter Configuration Register */ +#define REG_MCAN1_XIDAM (0x40034090) /**< (MCAN1) Extended ID AND Mask Register */ +#define REG_MCAN1_HPMS (0x40034094) /**< (MCAN1) High Priority Message Status Register */ +#define REG_MCAN1_NDAT1 (0x40034098) /**< (MCAN1) New Data 1 Register */ +#define REG_MCAN1_NDAT2 (0x4003409C) /**< (MCAN1) New Data 2 Register */ +#define REG_MCAN1_RXF0C (0x400340A0) /**< (MCAN1) Receive FIFO 0 Configuration Register */ +#define REG_MCAN1_RXF0S (0x400340A4) /**< (MCAN1) Receive FIFO 0 Status Register */ +#define REG_MCAN1_RXF0A (0x400340A8) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */ +#define REG_MCAN1_RXBC (0x400340AC) /**< (MCAN1) Receive Rx Buffer Configuration Register */ +#define REG_MCAN1_RXF1C (0x400340B0) /**< (MCAN1) Receive FIFO 1 Configuration Register */ +#define REG_MCAN1_RXF1S (0x400340B4) /**< (MCAN1) Receive FIFO 1 Status Register */ +#define REG_MCAN1_RXF1A (0x400340B8) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */ +#define REG_MCAN1_RXESC (0x400340BC) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ +#define REG_MCAN1_TXBC (0x400340C0) /**< (MCAN1) Transmit Buffer Configuration Register */ +#define REG_MCAN1_TXFQS (0x400340C4) /**< (MCAN1) Transmit FIFO/Queue Status Register */ +#define REG_MCAN1_TXESC (0x400340C8) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */ +#define REG_MCAN1_TXBRP (0x400340CC) /**< (MCAN1) Transmit Buffer Request Pending Register */ +#define REG_MCAN1_TXBAR (0x400340D0) /**< (MCAN1) Transmit Buffer Add Request Register */ +#define REG_MCAN1_TXBCR (0x400340D4) /**< (MCAN1) Transmit Buffer Cancellation Request Register */ +#define REG_MCAN1_TXBTO (0x400340D8) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */ +#define REG_MCAN1_TXBCF (0x400340DC) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */ +#define REG_MCAN1_TXBTIE (0x400340E0) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ +#define REG_MCAN1_TXBCIE (0x400340E4) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ +#define REG_MCAN1_TXEFC (0x400340F0) /**< (MCAN1) Transmit Event FIFO Configuration Register */ +#define REG_MCAN1_TXEFS (0x400340F4) /**< (MCAN1) Transmit Event FIFO Status Register */ +#define REG_MCAN1_TXEFA (0x400340F8) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */ + +#else + +#define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< (MCAN1) Core Release Register */ +#define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< (MCAN1) Endian Register */ +#define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< (MCAN1) Customer Register */ +#define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< (MCAN1) Data Bit Timing and Prescaler Register */ +#define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< (MCAN1) Test Register */ +#define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< (MCAN1) RAM Watchdog Register */ +#define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< (MCAN1) CC Control Register */ +#define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */ +#define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< (MCAN1) Timestamp Counter Configuration Register */ +#define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< (MCAN1) Timestamp Counter Value Register */ +#define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< (MCAN1) Timeout Counter Configuration Register */ +#define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< (MCAN1) Timeout Counter Value Register */ +#define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< (MCAN1) Error Counter Register */ +#define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< (MCAN1) Protocol Status Register */ +#define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< (MCAN1) Transmit Delay Compensation Register */ +#define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< (MCAN1) Interrupt Register */ +#define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< (MCAN1) Interrupt Enable Register */ +#define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< (MCAN1) Interrupt Line Select Register */ +#define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< (MCAN1) Interrupt Line Enable Register */ +#define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< (MCAN1) Global Filter Configuration Register */ +#define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< (MCAN1) Standard ID Filter Configuration Register */ +#define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< (MCAN1) Extended ID Filter Configuration Register */ +#define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< (MCAN1) Extended ID AND Mask Register */ +#define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< (MCAN1) High Priority Message Status Register */ +#define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< (MCAN1) New Data 1 Register */ +#define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< (MCAN1) New Data 2 Register */ +#define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< (MCAN1) Receive FIFO 0 Configuration Register */ +#define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< (MCAN1) Receive FIFO 0 Status Register */ +#define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */ +#define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< (MCAN1) Receive Rx Buffer Configuration Register */ +#define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< (MCAN1) Receive FIFO 1 Configuration Register */ +#define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< (MCAN1) Receive FIFO 1 Status Register */ +#define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */ +#define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ +#define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< (MCAN1) Transmit Buffer Configuration Register */ +#define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< (MCAN1) Transmit FIFO/Queue Status Register */ +#define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */ +#define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< (MCAN1) Transmit Buffer Request Pending Register */ +#define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< (MCAN1) Transmit Buffer Add Request Register */ +#define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< (MCAN1) Transmit Buffer Cancellation Request Register */ +#define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */ +#define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */ +#define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ +#define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ +#define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< (MCAN1) Transmit Event FIFO Configuration Register */ +#define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< (MCAN1) Transmit Event FIFO Status Register */ +#define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for MCAN1 peripheral ========== */ +#define MCAN1_INSTANCE_ID 37 +#define MCAN1_CLOCK_ID 37 + +#endif /* _SAME70_MCAN1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pioa.h b/bsp/microchip/same70/bsp/same70b/include/instance/pioa.h new file mode 100644 index 0000000000..fba12f1222 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pioa.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Instance description for PIOA + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIOA_INSTANCE_H_ +#define _SAME70_PIOA_INSTANCE_H_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PIOA_PER (0x400E0E00) /**< (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0x400E0E04) /**< (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0x400E0E08) /**< (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0x400E0E10) /**< (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0x400E0E14) /**< (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0x400E0E18) /**< (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0x400E0E24) /**< (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0x400E0E28) /**< (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0x400E0E30) /**< (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0x400E0E34) /**< (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0x400E0E38) /**< (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0x400E0E3C) /**< (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0x400E0E40) /**< (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0x400E0E44) /**< (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0x400E0E48) /**< (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0x400E0E4C) /**< (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0x400E0E50) /**< (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0x400E0E54) /**< (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0x400E0E58) /**< (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0x400E0E60) /**< (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0x400E0E64) /**< (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0x400E0E68) /**< (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */ +#define REG_PIOA_ABCDSR0 (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */ +#define REG_PIOA_ABCDSR1 (0x400E0E74) /**< (PIOA) Peripheral ABCD Select Register 1 */ +#define REG_PIOA_IFSCDR (0x400E0E80) /**< (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (0x400E0E84) /**< (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (0x400E0E88) /**< (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (0x400E0E8C) /**< (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (0x400E0E90) /**< (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (0x400E0E94) /**< (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (0x400E0E98) /**< (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (0x400E0EA0) /**< (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0x400E0EA4) /**< (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0x400E0EA8) /**< (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0x400E0EB0) /**< (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0x400E0EB4) /**< (PIOA) Additional Interrupt Modes Disable Register */ +#define REG_PIOA_AIMMR (0x400E0EB8) /**< (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0x400E0EC0) /**< (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0x400E0EC4) /**< (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0x400E0EC8) /**< (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0x400E0ED0) /**< (PIOA) Falling Edge/Low-Level Select Register */ +#define REG_PIOA_REHLSR (0x400E0ED4) /**< (PIOA) Rising Edge/High-Level Select Register */ +#define REG_PIOA_FRLHSR (0x400E0ED8) /**< (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0x400E0EE0) /**< (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0x400E0EE4) /**< (PIOA) Write Protection Mode Register */ +#define REG_PIOA_WPSR (0x400E0EE8) /**< (PIOA) Write Protection Status Register */ +#define REG_PIOA_SCHMITT (0x400E0F00) /**< (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER (0x400E0F18) /**< (PIOA) I/O Drive Register */ +#define REG_PIOA_PCMR (0x400E0F50) /**< (PIOA) Parallel Capture Mode Register */ +#define REG_PIOA_PCIER (0x400E0F54) /**< (PIOA) Parallel Capture Interrupt Enable Register */ +#define REG_PIOA_PCIDR (0x400E0F58) /**< (PIOA) Parallel Capture Interrupt Disable Register */ +#define REG_PIOA_PCIMR (0x400E0F5C) /**< (PIOA) Parallel Capture Interrupt Mask Register */ +#define REG_PIOA_PCISR (0x400E0F60) /**< (PIOA) Parallel Capture Interrupt Status Register */ +#define REG_PIOA_PCRHR (0x400E0F64) /**< (PIOA) Parallel Capture Reception Holding Register */ + +#else + +#define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */ +#define REG_PIOA_ABCDSR0 (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */ +#define REG_PIOA_ABCDSR1 (*(__IO uint32_t*)0x400E0E74U) /**< (PIOA) Peripheral ABCD Select Register 1 */ +#define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< (PIOA) Additional Interrupt Modes Disable Register */ +#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< (PIOA) Falling Edge/Low-Level Select Register */ +#define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< (PIOA) Rising Edge/High-Level Select Register */ +#define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< (PIOA) Write Protection Mode Register */ +#define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< (PIOA) Write Protection Status Register */ +#define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< (PIOA) I/O Drive Register */ +#define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< (PIOA) Parallel Capture Mode Register */ +#define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< (PIOA) Parallel Capture Interrupt Enable Register */ +#define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< (PIOA) Parallel Capture Interrupt Disable Register */ +#define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< (PIOA) Parallel Capture Interrupt Mask Register */ +#define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< (PIOA) Parallel Capture Interrupt Status Register */ +#define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< (PIOA) Parallel Capture Reception Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PIOA peripheral ========== */ +#define PIOA_DMAC_ID_RX 34 +#define PIOA_INSTANCE_ID 10 +#define PIOA_CLOCK_ID 10 + +#endif /* _SAME70_PIOA_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/piob.h b/bsp/microchip/same70/bsp/same70b/include/instance/piob.h new file mode 100644 index 0000000000..975754f7d8 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/piob.h @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief Instance description for PIOB + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIOB_INSTANCE_H_ +#define _SAME70_PIOB_INSTANCE_H_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PIOB_PER (0x400E1000) /**< (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0x400E1004) /**< (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0x400E1008) /**< (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0x400E1010) /**< (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0x400E1014) /**< (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0x400E1018) /**< (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0x400E1020) /**< (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0x400E1024) /**< (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0x400E1028) /**< (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0x400E1030) /**< (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0x400E1034) /**< (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0x400E1038) /**< (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0x400E103C) /**< (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0x400E1040) /**< (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0x400E1044) /**< (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0x400E1048) /**< (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0x400E104C) /**< (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0x400E1050) /**< (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0x400E1054) /**< (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0x400E1058) /**< (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0x400E1060) /**< (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0x400E1064) /**< (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0x400E1068) /**< (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */ +#define REG_PIOB_ABCDSR0 (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */ +#define REG_PIOB_ABCDSR1 (0x400E1074) /**< (PIOB) Peripheral ABCD Select Register 1 */ +#define REG_PIOB_IFSCDR (0x400E1080) /**< (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (0x400E1084) /**< (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (0x400E1088) /**< (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (0x400E108C) /**< (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (0x400E1090) /**< (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (0x400E1094) /**< (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (0x400E1098) /**< (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (0x400E10A0) /**< (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0x400E10A4) /**< (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0x400E10A8) /**< (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0x400E10B0) /**< (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0x400E10B4) /**< (PIOB) Additional Interrupt Modes Disable Register */ +#define REG_PIOB_AIMMR (0x400E10B8) /**< (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0x400E10C0) /**< (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0x400E10C4) /**< (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0x400E10C8) /**< (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0x400E10D0) /**< (PIOB) Falling Edge/Low-Level Select Register */ +#define REG_PIOB_REHLSR (0x400E10D4) /**< (PIOB) Rising Edge/High-Level Select Register */ +#define REG_PIOB_FRLHSR (0x400E10D8) /**< (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0x400E10E0) /**< (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0x400E10E4) /**< (PIOB) Write Protection Mode Register */ +#define REG_PIOB_WPSR (0x400E10E8) /**< (PIOB) Write Protection Status Register */ +#define REG_PIOB_SCHMITT (0x400E1100) /**< (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER (0x400E1118) /**< (PIOB) I/O Drive Register */ +#define REG_PIOB_PCMR (0x400E1150) /**< (PIOB) Parallel Capture Mode Register */ +#define REG_PIOB_PCIER (0x400E1154) /**< (PIOB) Parallel Capture Interrupt Enable Register */ +#define REG_PIOB_PCIDR (0x400E1158) /**< (PIOB) Parallel Capture Interrupt Disable Register */ +#define REG_PIOB_PCIMR (0x400E115C) /**< (PIOB) Parallel Capture Interrupt Mask Register */ +#define REG_PIOB_PCISR (0x400E1160) /**< (PIOB) Parallel Capture Interrupt Status Register */ +#define REG_PIOB_PCRHR (0x400E1164) /**< (PIOB) Parallel Capture Reception Holding Register */ + +#else + +#define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */ +#define REG_PIOB_ABCDSR0 (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */ +#define REG_PIOB_ABCDSR1 (*(__IO uint32_t*)0x400E1074U) /**< (PIOB) Peripheral ABCD Select Register 1 */ +#define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< (PIOB) Additional Interrupt Modes Disable Register */ +#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< (PIOB) Falling Edge/Low-Level Select Register */ +#define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< (PIOB) Rising Edge/High-Level Select Register */ +#define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< (PIOB) Write Protection Mode Register */ +#define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< (PIOB) Write Protection Status Register */ +#define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< (PIOB) I/O Drive Register */ +#define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< (PIOB) Parallel Capture Mode Register */ +#define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< (PIOB) Parallel Capture Interrupt Enable Register */ +#define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< (PIOB) Parallel Capture Interrupt Disable Register */ +#define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< (PIOB) Parallel Capture Interrupt Mask Register */ +#define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< (PIOB) Parallel Capture Interrupt Status Register */ +#define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< (PIOB) Parallel Capture Reception Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PIOB peripheral ========== */ +#define PIOB_INSTANCE_ID 11 +#define PIOB_CLOCK_ID 11 + +#endif /* _SAME70_PIOB_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pioc.h b/bsp/microchip/same70/bsp/same70b/include/instance/pioc.h new file mode 100644 index 0000000000..8a3756b4ca --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pioc.h @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief Instance description for PIOC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIOC_INSTANCE_H_ +#define _SAME70_PIOC_INSTANCE_H_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PIOC_PER (0x400E1200) /**< (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0x400E1204) /**< (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0x400E1208) /**< (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0x400E1210) /**< (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0x400E1214) /**< (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0x400E1218) /**< (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0x400E1220) /**< (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0x400E1224) /**< (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0x400E1228) /**< (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0x400E1230) /**< (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0x400E1234) /**< (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0x400E1238) /**< (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0x400E123C) /**< (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0x400E1240) /**< (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0x400E1244) /**< (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0x400E1248) /**< (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0x400E124C) /**< (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0x400E1250) /**< (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0x400E1254) /**< (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0x400E1258) /**< (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0x400E1260) /**< (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0x400E1264) /**< (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0x400E1268) /**< (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */ +#define REG_PIOC_ABCDSR0 (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */ +#define REG_PIOC_ABCDSR1 (0x400E1274) /**< (PIOC) Peripheral ABCD Select Register 1 */ +#define REG_PIOC_IFSCDR (0x400E1280) /**< (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (0x400E1284) /**< (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (0x400E1288) /**< (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (0x400E128C) /**< (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (0x400E1290) /**< (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (0x400E1294) /**< (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (0x400E1298) /**< (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (0x400E12A0) /**< (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0x400E12A4) /**< (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0x400E12A8) /**< (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0x400E12B0) /**< (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0x400E12B4) /**< (PIOC) Additional Interrupt Modes Disable Register */ +#define REG_PIOC_AIMMR (0x400E12B8) /**< (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0x400E12C0) /**< (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0x400E12C4) /**< (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0x400E12C8) /**< (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0x400E12D0) /**< (PIOC) Falling Edge/Low-Level Select Register */ +#define REG_PIOC_REHLSR (0x400E12D4) /**< (PIOC) Rising Edge/High-Level Select Register */ +#define REG_PIOC_FRLHSR (0x400E12D8) /**< (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0x400E12E0) /**< (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0x400E12E4) /**< (PIOC) Write Protection Mode Register */ +#define REG_PIOC_WPSR (0x400E12E8) /**< (PIOC) Write Protection Status Register */ +#define REG_PIOC_SCHMITT (0x400E1300) /**< (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER (0x400E1318) /**< (PIOC) I/O Drive Register */ +#define REG_PIOC_PCMR (0x400E1350) /**< (PIOC) Parallel Capture Mode Register */ +#define REG_PIOC_PCIER (0x400E1354) /**< (PIOC) Parallel Capture Interrupt Enable Register */ +#define REG_PIOC_PCIDR (0x400E1358) /**< (PIOC) Parallel Capture Interrupt Disable Register */ +#define REG_PIOC_PCIMR (0x400E135C) /**< (PIOC) Parallel Capture Interrupt Mask Register */ +#define REG_PIOC_PCISR (0x400E1360) /**< (PIOC) Parallel Capture Interrupt Status Register */ +#define REG_PIOC_PCRHR (0x400E1364) /**< (PIOC) Parallel Capture Reception Holding Register */ + +#else + +#define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */ +#define REG_PIOC_ABCDSR0 (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */ +#define REG_PIOC_ABCDSR1 (*(__IO uint32_t*)0x400E1274U) /**< (PIOC) Peripheral ABCD Select Register 1 */ +#define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< (PIOC) Additional Interrupt Modes Disable Register */ +#define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< (PIOC) Falling Edge/Low-Level Select Register */ +#define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< (PIOC) Rising Edge/High-Level Select Register */ +#define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< (PIOC) Write Protection Mode Register */ +#define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< (PIOC) Write Protection Status Register */ +#define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< (PIOC) I/O Drive Register */ +#define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< (PIOC) Parallel Capture Mode Register */ +#define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< (PIOC) Parallel Capture Interrupt Enable Register */ +#define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< (PIOC) Parallel Capture Interrupt Disable Register */ +#define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< (PIOC) Parallel Capture Interrupt Mask Register */ +#define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< (PIOC) Parallel Capture Interrupt Status Register */ +#define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< (PIOC) Parallel Capture Reception Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PIOC peripheral ========== */ +#define PIOC_INSTANCE_ID 12 +#define PIOC_CLOCK_ID 12 + +#endif /* _SAME70_PIOC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/piod.h b/bsp/microchip/same70/bsp/same70b/include/instance/piod.h new file mode 100644 index 0000000000..e0add60474 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/piod.h @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief Instance description for PIOD + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIOD_INSTANCE_H_ +#define _SAME70_PIOD_INSTANCE_H_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PIOD_PER (0x400E1400) /**< (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (0x400E1404) /**< (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (0x400E1408) /**< (PIOD) PIO Status Register */ +#define REG_PIOD_OER (0x400E1410) /**< (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (0x400E1414) /**< (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (0x400E1418) /**< (PIOD) Output Status Register */ +#define REG_PIOD_IFER (0x400E1420) /**< (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (0x400E1424) /**< (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (0x400E1428) /**< (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (0x400E1430) /**< (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (0x400E1434) /**< (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (0x400E1438) /**< (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (0x400E143C) /**< (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (0x400E1440) /**< (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (0x400E1444) /**< (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (0x400E1448) /**< (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (0x400E144C) /**< (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (0x400E1450) /**< (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (0x400E1454) /**< (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (0x400E1458) /**< (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (0x400E1460) /**< (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (0x400E1464) /**< (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (0x400E1468) /**< (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */ +#define REG_PIOD_ABCDSR0 (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */ +#define REG_PIOD_ABCDSR1 (0x400E1474) /**< (PIOD) Peripheral ABCD Select Register 1 */ +#define REG_PIOD_IFSCDR (0x400E1480) /**< (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (0x400E1484) /**< (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (0x400E1488) /**< (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (0x400E148C) /**< (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (0x400E1490) /**< (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (0x400E1494) /**< (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (0x400E1498) /**< (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (0x400E14A0) /**< (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (0x400E14A4) /**< (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (0x400E14A8) /**< (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (0x400E14B0) /**< (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (0x400E14B4) /**< (PIOD) Additional Interrupt Modes Disable Register */ +#define REG_PIOD_AIMMR (0x400E14B8) /**< (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (0x400E14C0) /**< (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (0x400E14C4) /**< (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (0x400E14C8) /**< (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (0x400E14D0) /**< (PIOD) Falling Edge/Low-Level Select Register */ +#define REG_PIOD_REHLSR (0x400E14D4) /**< (PIOD) Rising Edge/High-Level Select Register */ +#define REG_PIOD_FRLHSR (0x400E14D8) /**< (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (0x400E14E0) /**< (PIOD) Lock Status */ +#define REG_PIOD_WPMR (0x400E14E4) /**< (PIOD) Write Protection Mode Register */ +#define REG_PIOD_WPSR (0x400E14E8) /**< (PIOD) Write Protection Status Register */ +#define REG_PIOD_SCHMITT (0x400E1500) /**< (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER (0x400E1518) /**< (PIOD) I/O Drive Register */ +#define REG_PIOD_PCMR (0x400E1550) /**< (PIOD) Parallel Capture Mode Register */ +#define REG_PIOD_PCIER (0x400E1554) /**< (PIOD) Parallel Capture Interrupt Enable Register */ +#define REG_PIOD_PCIDR (0x400E1558) /**< (PIOD) Parallel Capture Interrupt Disable Register */ +#define REG_PIOD_PCIMR (0x400E155C) /**< (PIOD) Parallel Capture Interrupt Mask Register */ +#define REG_PIOD_PCISR (0x400E1560) /**< (PIOD) Parallel Capture Interrupt Status Register */ +#define REG_PIOD_PCRHR (0x400E1564) /**< (PIOD) Parallel Capture Reception Holding Register */ + +#else + +#define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< (PIOD) PIO Status Register */ +#define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< (PIOD) Output Status Register */ +#define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */ +#define REG_PIOD_ABCDSR0 (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */ +#define REG_PIOD_ABCDSR1 (*(__IO uint32_t*)0x400E1474U) /**< (PIOD) Peripheral ABCD Select Register 1 */ +#define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< (PIOD) Additional Interrupt Modes Disable Register */ +#define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< (PIOD) Falling Edge/Low-Level Select Register */ +#define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< (PIOD) Rising Edge/High-Level Select Register */ +#define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< (PIOD) Lock Status */ +#define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< (PIOD) Write Protection Mode Register */ +#define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< (PIOD) Write Protection Status Register */ +#define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< (PIOD) I/O Drive Register */ +#define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< (PIOD) Parallel Capture Mode Register */ +#define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< (PIOD) Parallel Capture Interrupt Enable Register */ +#define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< (PIOD) Parallel Capture Interrupt Disable Register */ +#define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< (PIOD) Parallel Capture Interrupt Mask Register */ +#define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< (PIOD) Parallel Capture Interrupt Status Register */ +#define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< (PIOD) Parallel Capture Reception Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PIOD peripheral ========== */ +#define PIOD_INSTANCE_ID 16 +#define PIOD_CLOCK_ID 16 + +#endif /* _SAME70_PIOD_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pioe.h b/bsp/microchip/same70/bsp/same70b/include/instance/pioe.h new file mode 100644 index 0000000000..283a9a2e25 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pioe.h @@ -0,0 +1,159 @@ +/** + * \file + * + * \brief Instance description for PIOE + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PIOE_INSTANCE_H_ +#define _SAME70_PIOE_INSTANCE_H_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PIOE_PER (0x400E1600) /**< (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (0x400E1604) /**< (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (0x400E1608) /**< (PIOE) PIO Status Register */ +#define REG_PIOE_OER (0x400E1610) /**< (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (0x400E1614) /**< (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (0x400E1618) /**< (PIOE) Output Status Register */ +#define REG_PIOE_IFER (0x400E1620) /**< (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (0x400E1624) /**< (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (0x400E1628) /**< (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (0x400E1630) /**< (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (0x400E1634) /**< (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (0x400E1638) /**< (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (0x400E163C) /**< (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (0x400E1640) /**< (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (0x400E1644) /**< (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (0x400E1648) /**< (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (0x400E164C) /**< (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (0x400E1650) /**< (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (0x400E1654) /**< (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (0x400E1658) /**< (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (0x400E1660) /**< (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (0x400E1664) /**< (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (0x400E1668) /**< (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */ +#define REG_PIOE_ABCDSR0 (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */ +#define REG_PIOE_ABCDSR1 (0x400E1674) /**< (PIOE) Peripheral ABCD Select Register 1 */ +#define REG_PIOE_IFSCDR (0x400E1680) /**< (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (0x400E1684) /**< (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (0x400E1688) /**< (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (0x400E168C) /**< (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (0x400E1690) /**< (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (0x400E1694) /**< (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (0x400E1698) /**< (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (0x400E16A0) /**< (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (0x400E16A4) /**< (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (0x400E16A8) /**< (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Register */ +#define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (0x400E16C0) /**< (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (0x400E16C4) /**< (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (0x400E16C8) /**< (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (0x400E16D0) /**< (PIOE) Falling Edge/Low-Level Select Register */ +#define REG_PIOE_REHLSR (0x400E16D4) /**< (PIOE) Rising Edge/High-Level Select Register */ +#define REG_PIOE_FRLHSR (0x400E16D8) /**< (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (0x400E16E0) /**< (PIOE) Lock Status */ +#define REG_PIOE_WPMR (0x400E16E4) /**< (PIOE) Write Protection Mode Register */ +#define REG_PIOE_WPSR (0x400E16E8) /**< (PIOE) Write Protection Status Register */ +#define REG_PIOE_SCHMITT (0x400E1700) /**< (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER (0x400E1718) /**< (PIOE) I/O Drive Register */ +#define REG_PIOE_PCMR (0x400E1750) /**< (PIOE) Parallel Capture Mode Register */ +#define REG_PIOE_PCIER (0x400E1754) /**< (PIOE) Parallel Capture Interrupt Enable Register */ +#define REG_PIOE_PCIDR (0x400E1758) /**< (PIOE) Parallel Capture Interrupt Disable Register */ +#define REG_PIOE_PCIMR (0x400E175C) /**< (PIOE) Parallel Capture Interrupt Mask Register */ +#define REG_PIOE_PCISR (0x400E1760) /**< (PIOE) Parallel Capture Interrupt Status Register */ +#define REG_PIOE_PCRHR (0x400E1764) /**< (PIOE) Parallel Capture Reception Holding Register */ + +#else + +#define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< (PIOE) PIO Status Register */ +#define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< (PIOE) Output Status Register */ +#define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */ +#define REG_PIOE_ABCDSR0 (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */ +#define REG_PIOE_ABCDSR1 (*(__IO uint32_t*)0x400E1674U) /**< (PIOE) Peripheral ABCD Select Register 1 */ +#define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Modes Disable Register */ +#define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< (PIOE) Falling Edge/Low-Level Select Register */ +#define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< (PIOE) Rising Edge/High-Level Select Register */ +#define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< (PIOE) Lock Status */ +#define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< (PIOE) Write Protection Mode Register */ +#define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< (PIOE) Write Protection Status Register */ +#define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< (PIOE) I/O Drive Register */ +#define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< (PIOE) Parallel Capture Mode Register */ +#define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< (PIOE) Parallel Capture Interrupt Enable Register */ +#define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< (PIOE) Parallel Capture Interrupt Disable Register */ +#define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< (PIOE) Parallel Capture Interrupt Mask Register */ +#define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< (PIOE) Parallel Capture Interrupt Status Register */ +#define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< (PIOE) Parallel Capture Reception Holding Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PIOE peripheral ========== */ +#define PIOE_INSTANCE_ID 17 +#define PIOE_CLOCK_ID 17 + +#endif /* _SAME70_PIOE_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pmc.h b/bsp/microchip/same70/bsp/same70b/include/instance/pmc.h new file mode 100644 index 0000000000..f58b8f21fd --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pmc.h @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief Instance description for PMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PMC_INSTANCE_H_ +#define _SAME70_PMC_INSTANCE_H_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PMC_SCER (0x400E0600) /**< (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0x400E0604) /**< (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0x400E0608) /**< (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0x400E0610) /**< (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0x400E0614) /**< (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0x400E0618) /**< (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0x400E061C) /**< (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0x400E0620) /**< (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0x400E0624) /**< (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0x400E0628) /**< (PMC) PLLA Register */ +#define REG_PMC_MCKR (0x400E0630) /**< (PMC) Master Clock Register */ +#define REG_PMC_USB (0x400E0638) /**< (PMC) USB Clock Register */ +#define REG_PMC_PCK (0x400E0640) /**< (PMC) Programmable Clock Register */ +#define REG_PMC_PCK0 (0x400E0640) /**< (PMC) Programmable Clock Register 0 */ +#define REG_PMC_PCK1 (0x400E0644) /**< (PMC) Programmable Clock Register 1 */ +#define REG_PMC_PCK2 (0x400E0648) /**< (PMC) Programmable Clock Register 2 */ +#define REG_PMC_PCK3 (0x400E064C) /**< (PMC) Programmable Clock Register 3 */ +#define REG_PMC_PCK4 (0x400E0650) /**< (PMC) Programmable Clock Register 4 */ +#define REG_PMC_PCK5 (0x400E0654) /**< (PMC) Programmable Clock Register 5 */ +#define REG_PMC_PCK6 (0x400E0658) /**< (PMC) Programmable Clock Register 6 */ +#define REG_PMC_PCK7 (0x400E065C) /**< (PMC) Programmable Clock Register 7 */ +#define REG_PMC_IER (0x400E0660) /**< (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0x400E0664) /**< (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0x400E0668) /**< (PMC) Status Register */ +#define REG_PMC_IMR (0x400E066C) /**< (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (0x400E0670) /**< (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (0x400E0674) /**< (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (0x400E0678) /**< (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (0x400E06E4) /**< (PMC) Write Protection Mode Register */ +#define REG_PMC_WPSR (0x400E06E8) /**< (PMC) Write Protection Status Register */ +#define REG_PMC_PCER1 (0x400E0700) /**< (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (0x400E0704) /**< (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (0x400E0708) /**< (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (0x400E070C) /**< (PMC) Peripheral Control Register */ +#define REG_PMC_OCR (0x400E0710) /**< (PMC) Oscillator Calibration Register */ +#define REG_PMC_SLPWK_ER0 (0x400E0714) /**< (PMC) SleepWalking Enable Register 0 */ +#define REG_PMC_SLPWK_DR0 (0x400E0718) /**< (PMC) SleepWalking Disable Register 0 */ +#define REG_PMC_SLPWK_SR0 (0x400E071C) /**< (PMC) SleepWalking Status Register 0 */ +#define REG_PMC_SLPWK_ASR0 (0x400E0720) /**< (PMC) SleepWalking Activity Status Register 0 */ +#define REG_PMC_PMMR (0x400E0730) /**< (PMC) PLL Maximum Multiplier Value Register */ +#define REG_PMC_SLPWK_ER1 (0x400E0734) /**< (PMC) SleepWalking Enable Register 1 */ +#define REG_PMC_SLPWK_DR1 (0x400E0738) /**< (PMC) SleepWalking Disable Register 1 */ +#define REG_PMC_SLPWK_SR1 (0x400E073C) /**< (PMC) SleepWalking Status Register 1 */ +#define REG_PMC_SLPWK_ASR1 (0x400E0740) /**< (PMC) SleepWalking Activity Status Register 1 */ +#define REG_PMC_SLPWK_AIPR (0x400E0744) /**< (PMC) SleepWalking Activity In Progress Register */ + +#else + +#define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< (PMC) Master Clock Register */ +#define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< (PMC) USB Clock Register */ +#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register */ +#define REG_PMC_PCK0 (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register 0 */ +#define REG_PMC_PCK1 (*(__IO uint32_t*)0x400E0644U) /**< (PMC) Programmable Clock Register 1 */ +#define REG_PMC_PCK2 (*(__IO uint32_t*)0x400E0648U) /**< (PMC) Programmable Clock Register 2 */ +#define REG_PMC_PCK3 (*(__IO uint32_t*)0x400E064CU) /**< (PMC) Programmable Clock Register 3 */ +#define REG_PMC_PCK4 (*(__IO uint32_t*)0x400E0650U) /**< (PMC) Programmable Clock Register 4 */ +#define REG_PMC_PCK5 (*(__IO uint32_t*)0x400E0654U) /**< (PMC) Programmable Clock Register 5 */ +#define REG_PMC_PCK6 (*(__IO uint32_t*)0x400E0658U) /**< (PMC) Programmable Clock Register 6 */ +#define REG_PMC_PCK7 (*(__IO uint32_t*)0x400E065CU) /**< (PMC) Programmable Clock Register 7 */ +#define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< (PMC) Status Register */ +#define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< (PMC) Write Protection Mode Register */ +#define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< (PMC) Write Protection Status Register */ +#define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< (PMC) Peripheral Control Register */ +#define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< (PMC) Oscillator Calibration Register */ +#define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< (PMC) SleepWalking Enable Register 0 */ +#define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< (PMC) SleepWalking Disable Register 0 */ +#define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< (PMC) SleepWalking Status Register 0 */ +#define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< (PMC) SleepWalking Activity Status Register 0 */ +#define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< (PMC) PLL Maximum Multiplier Value Register */ +#define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< (PMC) SleepWalking Enable Register 1 */ +#define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< (PMC) SleepWalking Disable Register 1 */ +#define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< (PMC) SleepWalking Status Register 1 */ +#define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< (PMC) SleepWalking Activity Status Register 1 */ +#define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< (PMC) SleepWalking Activity In Progress Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PMC peripheral ========== */ +#define PMC_INSTANCE_ID 5 + +#endif /* _SAME70_PMC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pwm0.h b/bsp/microchip/same70/bsp/same70b/include/instance/pwm0.h new file mode 100644 index 0000000000..db2028c003 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pwm0.h @@ -0,0 +1,274 @@ +/** + * \file + * + * \brief Instance description for PWM0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PWM0_INSTANCE_H_ +#define _SAME70_PWM0_INSTANCE_H_ + +/* ========== Register definition for PWM0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PWM0_CMPV0 (0x40020130) /**< (PWM0) PWM Comparison 0 Value Register 0 */ +#define REG_PWM0_CMPVUPD0 (0x40020134) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */ +#define REG_PWM0_CMPM0 (0x40020138) /**< (PWM0) PWM Comparison 0 Mode Register 0 */ +#define REG_PWM0_CMPMUPD0 (0x4002013C) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */ +#define REG_PWM0_CMPV1 (0x40020140) /**< (PWM0) PWM Comparison 0 Value Register 1 */ +#define REG_PWM0_CMPVUPD1 (0x40020144) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */ +#define REG_PWM0_CMPM1 (0x40020148) /**< (PWM0) PWM Comparison 0 Mode Register 1 */ +#define REG_PWM0_CMPMUPD1 (0x4002014C) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */ +#define REG_PWM0_CMPV2 (0x40020150) /**< (PWM0) PWM Comparison 0 Value Register 2 */ +#define REG_PWM0_CMPVUPD2 (0x40020154) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */ +#define REG_PWM0_CMPM2 (0x40020158) /**< (PWM0) PWM Comparison 0 Mode Register 2 */ +#define REG_PWM0_CMPMUPD2 (0x4002015C) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */ +#define REG_PWM0_CMPV3 (0x40020160) /**< (PWM0) PWM Comparison 0 Value Register 3 */ +#define REG_PWM0_CMPVUPD3 (0x40020164) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */ +#define REG_PWM0_CMPM3 (0x40020168) /**< (PWM0) PWM Comparison 0 Mode Register 3 */ +#define REG_PWM0_CMPMUPD3 (0x4002016C) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */ +#define REG_PWM0_CMPV4 (0x40020170) /**< (PWM0) PWM Comparison 0 Value Register 4 */ +#define REG_PWM0_CMPVUPD4 (0x40020174) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */ +#define REG_PWM0_CMPM4 (0x40020178) /**< (PWM0) PWM Comparison 0 Mode Register 4 */ +#define REG_PWM0_CMPMUPD4 (0x4002017C) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */ +#define REG_PWM0_CMPV5 (0x40020180) /**< (PWM0) PWM Comparison 0 Value Register 5 */ +#define REG_PWM0_CMPVUPD5 (0x40020184) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */ +#define REG_PWM0_CMPM5 (0x40020188) /**< (PWM0) PWM Comparison 0 Mode Register 5 */ +#define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ +#define REG_PWM0_CMPV6 (0x40020190) /**< (PWM0) PWM Comparison 0 Value Register 6 */ +#define REG_PWM0_CMPVUPD6 (0x40020194) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */ +#define REG_PWM0_CMPM6 (0x40020198) /**< (PWM0) PWM Comparison 0 Mode Register 6 */ +#define REG_PWM0_CMPMUPD6 (0x4002019C) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */ +#define REG_PWM0_CMPV7 (0x400201A0) /**< (PWM0) PWM Comparison 0 Value Register 7 */ +#define REG_PWM0_CMPVUPD7 (0x400201A4) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */ +#define REG_PWM0_CMPM7 (0x400201A8) /**< (PWM0) PWM Comparison 0 Mode Register 7 */ +#define REG_PWM0_CMPMUPD7 (0x400201AC) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */ +#define REG_PWM0_CMR0 (0x40020200) /**< (PWM0) PWM Channel Mode Register 0 */ +#define REG_PWM0_CDTY0 (0x40020204) /**< (PWM0) PWM Channel Duty Cycle Register 0 */ +#define REG_PWM0_CDTYUPD0 (0x40020208) /**< (PWM0) PWM Channel Duty Cycle Update Register 0 */ +#define REG_PWM0_CPRD0 (0x4002020C) /**< (PWM0) PWM Channel Period Register 0 */ +#define REG_PWM0_CPRDUPD0 (0x40020210) /**< (PWM0) PWM Channel Period Update Register 0 */ +#define REG_PWM0_CCNT0 (0x40020214) /**< (PWM0) PWM Channel Counter Register 0 */ +#define REG_PWM0_DT0 (0x40020218) /**< (PWM0) PWM Channel Dead Time Register 0 */ +#define REG_PWM0_DTUPD0 (0x4002021C) /**< (PWM0) PWM Channel Dead Time Update Register 0 */ +#define REG_PWM0_CMR1 (0x40020220) /**< (PWM0) PWM Channel Mode Register 1 */ +#define REG_PWM0_CDTY1 (0x40020224) /**< (PWM0) PWM Channel Duty Cycle Register 1 */ +#define REG_PWM0_CDTYUPD1 (0x40020228) /**< (PWM0) PWM Channel Duty Cycle Update Register 1 */ +#define REG_PWM0_CPRD1 (0x4002022C) /**< (PWM0) PWM Channel Period Register 1 */ +#define REG_PWM0_CPRDUPD1 (0x40020230) /**< (PWM0) PWM Channel Period Update Register 1 */ +#define REG_PWM0_CCNT1 (0x40020234) /**< (PWM0) PWM Channel Counter Register 1 */ +#define REG_PWM0_DT1 (0x40020238) /**< (PWM0) PWM Channel Dead Time Register 1 */ +#define REG_PWM0_DTUPD1 (0x4002023C) /**< (PWM0) PWM Channel Dead Time Update Register 1 */ +#define REG_PWM0_CMR2 (0x40020240) /**< (PWM0) PWM Channel Mode Register 2 */ +#define REG_PWM0_CDTY2 (0x40020244) /**< (PWM0) PWM Channel Duty Cycle Register 2 */ +#define REG_PWM0_CDTYUPD2 (0x40020248) /**< (PWM0) PWM Channel Duty Cycle Update Register 2 */ +#define REG_PWM0_CPRD2 (0x4002024C) /**< (PWM0) PWM Channel Period Register 2 */ +#define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register 2 */ +#define REG_PWM0_CCNT2 (0x40020254) /**< (PWM0) PWM Channel Counter Register 2 */ +#define REG_PWM0_DT2 (0x40020258) /**< (PWM0) PWM Channel Dead Time Register 2 */ +#define REG_PWM0_DTUPD2 (0x4002025C) /**< (PWM0) PWM Channel Dead Time Update Register 2 */ +#define REG_PWM0_CMR3 (0x40020260) /**< (PWM0) PWM Channel Mode Register 3 */ +#define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register 3 */ +#define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */ +#define REG_PWM0_CPRD3 (0x4002026C) /**< (PWM0) PWM Channel Period Register 3 */ +#define REG_PWM0_CPRDUPD3 (0x40020270) /**< (PWM0) PWM Channel Period Update Register 3 */ +#define REG_PWM0_CCNT3 (0x40020274) /**< (PWM0) PWM Channel Counter Register 3 */ +#define REG_PWM0_DT3 (0x40020278) /**< (PWM0) PWM Channel Dead Time Register 3 */ +#define REG_PWM0_DTUPD3 (0x4002027C) /**< (PWM0) PWM Channel Dead Time Update Register 3 */ +#define REG_PWM0_CLK (0x40020000) /**< (PWM0) PWM Clock Register */ +#define REG_PWM0_ENA (0x40020004) /**< (PWM0) PWM Enable Register */ +#define REG_PWM0_DIS (0x40020008) /**< (PWM0) PWM Disable Register */ +#define REG_PWM0_SR (0x4002000C) /**< (PWM0) PWM Status Register */ +#define REG_PWM0_IER1 (0x40020010) /**< (PWM0) PWM Interrupt Enable Register 1 */ +#define REG_PWM0_IDR1 (0x40020014) /**< (PWM0) PWM Interrupt Disable Register 1 */ +#define REG_PWM0_IMR1 (0x40020018) /**< (PWM0) PWM Interrupt Mask Register 1 */ +#define REG_PWM0_ISR1 (0x4002001C) /**< (PWM0) PWM Interrupt Status Register 1 */ +#define REG_PWM0_SCM (0x40020020) /**< (PWM0) PWM Sync Channels Mode Register */ +#define REG_PWM0_DMAR (0x40020024) /**< (PWM0) PWM DMA Register */ +#define REG_PWM0_SCUC (0x40020028) /**< (PWM0) PWM Sync Channels Update Control Register */ +#define REG_PWM0_SCUP (0x4002002C) /**< (PWM0) PWM Sync Channels Update Period Register */ +#define REG_PWM0_SCUPUPD (0x40020030) /**< (PWM0) PWM Sync Channels Update Period Update Register */ +#define REG_PWM0_IER2 (0x40020034) /**< (PWM0) PWM Interrupt Enable Register 2 */ +#define REG_PWM0_IDR2 (0x40020038) /**< (PWM0) PWM Interrupt Disable Register 2 */ +#define REG_PWM0_IMR2 (0x4002003C) /**< (PWM0) PWM Interrupt Mask Register 2 */ +#define REG_PWM0_ISR2 (0x40020040) /**< (PWM0) PWM Interrupt Status Register 2 */ +#define REG_PWM0_OOV (0x40020044) /**< (PWM0) PWM Output Override Value Register */ +#define REG_PWM0_OS (0x40020048) /**< (PWM0) PWM Output Selection Register */ +#define REG_PWM0_OSS (0x4002004C) /**< (PWM0) PWM Output Selection Set Register */ +#define REG_PWM0_OSC (0x40020050) /**< (PWM0) PWM Output Selection Clear Register */ +#define REG_PWM0_OSSUPD (0x40020054) /**< (PWM0) PWM Output Selection Set Update Register */ +#define REG_PWM0_OSCUPD (0x40020058) /**< (PWM0) PWM Output Selection Clear Update Register */ +#define REG_PWM0_FMR (0x4002005C) /**< (PWM0) PWM Fault Mode Register */ +#define REG_PWM0_FSR (0x40020060) /**< (PWM0) PWM Fault Status Register */ +#define REG_PWM0_FCR (0x40020064) /**< (PWM0) PWM Fault Clear Register */ +#define REG_PWM0_FPV1 (0x40020068) /**< (PWM0) PWM Fault Protection Value Register 1 */ +#define REG_PWM0_FPE (0x4002006C) /**< (PWM0) PWM Fault Protection Enable Register */ +#define REG_PWM0_ELMR (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM0_ELMR0 (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM0_ELMR1 (0x40020080) /**< (PWM0) PWM Event Line 0 Mode Register 1 */ +#define REG_PWM0_SSPR (0x400200A0) /**< (PWM0) PWM Spread Spectrum Register */ +#define REG_PWM0_SSPUP (0x400200A4) /**< (PWM0) PWM Spread Spectrum Update Register */ +#define REG_PWM0_SMMR (0x400200B0) /**< (PWM0) PWM Stepper Motor Mode Register */ +#define REG_PWM0_FPV2 (0x400200C0) /**< (PWM0) PWM Fault Protection Value 2 Register */ +#define REG_PWM0_WPCR (0x400200E4) /**< (PWM0) PWM Write Protection Control Register */ +#define REG_PWM0_WPSR (0x400200E8) /**< (PWM0) PWM Write Protection Status Register */ +#define REG_PWM0_CMUPD0 (0x40020400) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM0_CMUPD1 (0x40020420) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM0_ETRG1 (0x4002042C) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */ +#define REG_PWM0_LEBR1 (0x40020430) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ +#define REG_PWM0_CMUPD2 (0x40020440) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM0_ETRG2 (0x4002044C) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */ +#define REG_PWM0_LEBR2 (0x40020450) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ +#define REG_PWM0_CMUPD3 (0x40020460) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + +#else + +#define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< (PWM0) PWM Comparison 0 Value Register 0 */ +#define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */ +#define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< (PWM0) PWM Comparison 0 Mode Register 0 */ +#define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */ +#define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< (PWM0) PWM Comparison 0 Value Register 1 */ +#define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */ +#define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< (PWM0) PWM Comparison 0 Mode Register 1 */ +#define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */ +#define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< (PWM0) PWM Comparison 0 Value Register 2 */ +#define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */ +#define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< (PWM0) PWM Comparison 0 Mode Register 2 */ +#define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */ +#define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< (PWM0) PWM Comparison 0 Value Register 3 */ +#define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */ +#define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< (PWM0) PWM Comparison 0 Mode Register 3 */ +#define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */ +#define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< (PWM0) PWM Comparison 0 Value Register 4 */ +#define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */ +#define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< (PWM0) PWM Comparison 0 Mode Register 4 */ +#define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */ +#define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< (PWM0) PWM Comparison 0 Value Register 5 */ +#define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */ +#define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< (PWM0) PWM Comparison 0 Mode Register 5 */ +#define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ +#define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< (PWM0) PWM Comparison 0 Value Register 6 */ +#define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */ +#define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< (PWM0) PWM Comparison 0 Mode Register 6 */ +#define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */ +#define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< (PWM0) PWM Comparison 0 Value Register 7 */ +#define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */ +#define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< (PWM0) PWM Comparison 0 Mode Register 7 */ +#define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */ +#define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< (PWM0) PWM Channel Mode Register 0 */ +#define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< (PWM0) PWM Channel Duty Cycle Register 0 */ +#define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< (PWM0) PWM Channel Duty Cycle Update Register 0 */ +#define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< (PWM0) PWM Channel Period Register 0 */ +#define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< (PWM0) PWM Channel Period Update Register 0 */ +#define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< (PWM0) PWM Channel Counter Register 0 */ +#define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< (PWM0) PWM Channel Dead Time Register 0 */ +#define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< (PWM0) PWM Channel Dead Time Update Register 0 */ +#define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< (PWM0) PWM Channel Mode Register 1 */ +#define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< (PWM0) PWM Channel Duty Cycle Register 1 */ +#define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< (PWM0) PWM Channel Duty Cycle Update Register 1 */ +#define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< (PWM0) PWM Channel Period Register 1 */ +#define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< (PWM0) PWM Channel Period Update Register 1 */ +#define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< (PWM0) PWM Channel Counter Register 1 */ +#define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< (PWM0) PWM Channel Dead Time Register 1 */ +#define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< (PWM0) PWM Channel Dead Time Update Register 1 */ +#define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< (PWM0) PWM Channel Mode Register 2 */ +#define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< (PWM0) PWM Channel Duty Cycle Register 2 */ +#define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< (PWM0) PWM Channel Duty Cycle Update Register 2 */ +#define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< (PWM0) PWM Channel Period Register 2 */ +#define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Update Register 2 */ +#define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< (PWM0) PWM Channel Counter Register 2 */ +#define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< (PWM0) PWM Channel Dead Time Register 2 */ +#define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< (PWM0) PWM Channel Dead Time Update Register 2 */ +#define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< (PWM0) PWM Channel Mode Register 3 */ +#define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle Register 3 */ +#define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */ +#define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< (PWM0) PWM Channel Period Register 3 */ +#define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< (PWM0) PWM Channel Period Update Register 3 */ +#define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< (PWM0) PWM Channel Counter Register 3 */ +#define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< (PWM0) PWM Channel Dead Time Register 3 */ +#define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< (PWM0) PWM Channel Dead Time Update Register 3 */ +#define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< (PWM0) PWM Clock Register */ +#define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< (PWM0) PWM Enable Register */ +#define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< (PWM0) PWM Disable Register */ +#define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< (PWM0) PWM Status Register */ +#define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< (PWM0) PWM Interrupt Enable Register 1 */ +#define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< (PWM0) PWM Interrupt Disable Register 1 */ +#define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< (PWM0) PWM Interrupt Mask Register 1 */ +#define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< (PWM0) PWM Interrupt Status Register 1 */ +#define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< (PWM0) PWM Sync Channels Mode Register */ +#define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< (PWM0) PWM DMA Register */ +#define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< (PWM0) PWM Sync Channels Update Control Register */ +#define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< (PWM0) PWM Sync Channels Update Period Register */ +#define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< (PWM0) PWM Sync Channels Update Period Update Register */ +#define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< (PWM0) PWM Interrupt Enable Register 2 */ +#define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< (PWM0) PWM Interrupt Disable Register 2 */ +#define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< (PWM0) PWM Interrupt Mask Register 2 */ +#define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< (PWM0) PWM Interrupt Status Register 2 */ +#define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< (PWM0) PWM Output Override Value Register */ +#define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< (PWM0) PWM Output Selection Register */ +#define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< (PWM0) PWM Output Selection Set Register */ +#define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< (PWM0) PWM Output Selection Clear Register */ +#define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< (PWM0) PWM Output Selection Set Update Register */ +#define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< (PWM0) PWM Output Selection Clear Update Register */ +#define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< (PWM0) PWM Fault Mode Register */ +#define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< (PWM0) PWM Fault Status Register */ +#define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< (PWM0) PWM Fault Clear Register */ +#define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< (PWM0) PWM Fault Protection Value Register 1 */ +#define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< (PWM0) PWM Fault Protection Enable Register */ +#define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM0_ELMR0 (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM0_ELMR1 (*(__IO uint32_t*)0x40020080U) /**< (PWM0) PWM Event Line 0 Mode Register 1 */ +#define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< (PWM0) PWM Spread Spectrum Register */ +#define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< (PWM0) PWM Spread Spectrum Update Register */ +#define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< (PWM0) PWM Stepper Motor Mode Register */ +#define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< (PWM0) PWM Fault Protection Value 2 Register */ +#define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< (PWM0) PWM Write Protection Control Register */ +#define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< (PWM0) PWM Write Protection Status Register */ +#define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */ +#define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ +#define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */ +#define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ +#define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PWM0 peripheral ========== */ +#define PWM0_DMAC_ID_TX 13 +#define PWM0_INSTANCE_ID 31 +#define PWM0_CLOCK_ID 31 +#define PWM0_FAULT_PWM_ID0 0x0 /* Fault 0 - PWM0_PWMFI0 Input pin */ +#define PWM0_FAULT_PWM_ID1 0x1 /* Fault 1 - PWM0_PWMFI1 Input pin */ +#define PWM0_FAULT_PWM_ID2 0x2 /* Fault 2 - PWM0_PWMFI2 Input pin */ +#define PWM0_FAULT_PWM_ID3 0x3 /* Fault 3 - MAIN_OSC_PMC */ +#define PWM0_FAULT_PWM_ID4 0x4 /* Fault 4 - AFEC0 */ +#define PWM0_FAULT_PWM_ID5 0x5 /* Fault 5 - AFEC1 */ +#define PWM0_FAULT_PWM_ID6 0x6 /* Fault 6 - ACC */ +#define PWM0_FAULT_PWM_ID7 0x7 /* Fault 7 - TC0 */ + +#endif /* _SAME70_PWM0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/pwm1.h b/bsp/microchip/same70/bsp/same70b/include/instance/pwm1.h new file mode 100644 index 0000000000..c302078fce --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/pwm1.h @@ -0,0 +1,274 @@ +/** + * \file + * + * \brief Instance description for PWM1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_PWM1_INSTANCE_H_ +#define _SAME70_PWM1_INSTANCE_H_ + +/* ========== Register definition for PWM1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_PWM1_CMPV0 (0x4005C130) /**< (PWM1) PWM Comparison 0 Value Register 0 */ +#define REG_PWM1_CMPVUPD0 (0x4005C134) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */ +#define REG_PWM1_CMPM0 (0x4005C138) /**< (PWM1) PWM Comparison 0 Mode Register 0 */ +#define REG_PWM1_CMPMUPD0 (0x4005C13C) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */ +#define REG_PWM1_CMPV1 (0x4005C140) /**< (PWM1) PWM Comparison 0 Value Register 1 */ +#define REG_PWM1_CMPVUPD1 (0x4005C144) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */ +#define REG_PWM1_CMPM1 (0x4005C148) /**< (PWM1) PWM Comparison 0 Mode Register 1 */ +#define REG_PWM1_CMPMUPD1 (0x4005C14C) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */ +#define REG_PWM1_CMPV2 (0x4005C150) /**< (PWM1) PWM Comparison 0 Value Register 2 */ +#define REG_PWM1_CMPVUPD2 (0x4005C154) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */ +#define REG_PWM1_CMPM2 (0x4005C158) /**< (PWM1) PWM Comparison 0 Mode Register 2 */ +#define REG_PWM1_CMPMUPD2 (0x4005C15C) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */ +#define REG_PWM1_CMPV3 (0x4005C160) /**< (PWM1) PWM Comparison 0 Value Register 3 */ +#define REG_PWM1_CMPVUPD3 (0x4005C164) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */ +#define REG_PWM1_CMPM3 (0x4005C168) /**< (PWM1) PWM Comparison 0 Mode Register 3 */ +#define REG_PWM1_CMPMUPD3 (0x4005C16C) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */ +#define REG_PWM1_CMPV4 (0x4005C170) /**< (PWM1) PWM Comparison 0 Value Register 4 */ +#define REG_PWM1_CMPVUPD4 (0x4005C174) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */ +#define REG_PWM1_CMPM4 (0x4005C178) /**< (PWM1) PWM Comparison 0 Mode Register 4 */ +#define REG_PWM1_CMPMUPD4 (0x4005C17C) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */ +#define REG_PWM1_CMPV5 (0x4005C180) /**< (PWM1) PWM Comparison 0 Value Register 5 */ +#define REG_PWM1_CMPVUPD5 (0x4005C184) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */ +#define REG_PWM1_CMPM5 (0x4005C188) /**< (PWM1) PWM Comparison 0 Mode Register 5 */ +#define REG_PWM1_CMPMUPD5 (0x4005C18C) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */ +#define REG_PWM1_CMPV6 (0x4005C190) /**< (PWM1) PWM Comparison 0 Value Register 6 */ +#define REG_PWM1_CMPVUPD6 (0x4005C194) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */ +#define REG_PWM1_CMPM6 (0x4005C198) /**< (PWM1) PWM Comparison 0 Mode Register 6 */ +#define REG_PWM1_CMPMUPD6 (0x4005C19C) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */ +#define REG_PWM1_CMPV7 (0x4005C1A0) /**< (PWM1) PWM Comparison 0 Value Register 7 */ +#define REG_PWM1_CMPVUPD7 (0x4005C1A4) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */ +#define REG_PWM1_CMPM7 (0x4005C1A8) /**< (PWM1) PWM Comparison 0 Mode Register 7 */ +#define REG_PWM1_CMPMUPD7 (0x4005C1AC) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */ +#define REG_PWM1_CMR0 (0x4005C200) /**< (PWM1) PWM Channel Mode Register 0 */ +#define REG_PWM1_CDTY0 (0x4005C204) /**< (PWM1) PWM Channel Duty Cycle Register 0 */ +#define REG_PWM1_CDTYUPD0 (0x4005C208) /**< (PWM1) PWM Channel Duty Cycle Update Register 0 */ +#define REG_PWM1_CPRD0 (0x4005C20C) /**< (PWM1) PWM Channel Period Register 0 */ +#define REG_PWM1_CPRDUPD0 (0x4005C210) /**< (PWM1) PWM Channel Period Update Register 0 */ +#define REG_PWM1_CCNT0 (0x4005C214) /**< (PWM1) PWM Channel Counter Register 0 */ +#define REG_PWM1_DT0 (0x4005C218) /**< (PWM1) PWM Channel Dead Time Register 0 */ +#define REG_PWM1_DTUPD0 (0x4005C21C) /**< (PWM1) PWM Channel Dead Time Update Register 0 */ +#define REG_PWM1_CMR1 (0x4005C220) /**< (PWM1) PWM Channel Mode Register 1 */ +#define REG_PWM1_CDTY1 (0x4005C224) /**< (PWM1) PWM Channel Duty Cycle Register 1 */ +#define REG_PWM1_CDTYUPD1 (0x4005C228) /**< (PWM1) PWM Channel Duty Cycle Update Register 1 */ +#define REG_PWM1_CPRD1 (0x4005C22C) /**< (PWM1) PWM Channel Period Register 1 */ +#define REG_PWM1_CPRDUPD1 (0x4005C230) /**< (PWM1) PWM Channel Period Update Register 1 */ +#define REG_PWM1_CCNT1 (0x4005C234) /**< (PWM1) PWM Channel Counter Register 1 */ +#define REG_PWM1_DT1 (0x4005C238) /**< (PWM1) PWM Channel Dead Time Register 1 */ +#define REG_PWM1_DTUPD1 (0x4005C23C) /**< (PWM1) PWM Channel Dead Time Update Register 1 */ +#define REG_PWM1_CMR2 (0x4005C240) /**< (PWM1) PWM Channel Mode Register 2 */ +#define REG_PWM1_CDTY2 (0x4005C244) /**< (PWM1) PWM Channel Duty Cycle Register 2 */ +#define REG_PWM1_CDTYUPD2 (0x4005C248) /**< (PWM1) PWM Channel Duty Cycle Update Register 2 */ +#define REG_PWM1_CPRD2 (0x4005C24C) /**< (PWM1) PWM Channel Period Register 2 */ +#define REG_PWM1_CPRDUPD2 (0x4005C250) /**< (PWM1) PWM Channel Period Update Register 2 */ +#define REG_PWM1_CCNT2 (0x4005C254) /**< (PWM1) PWM Channel Counter Register 2 */ +#define REG_PWM1_DT2 (0x4005C258) /**< (PWM1) PWM Channel Dead Time Register 2 */ +#define REG_PWM1_DTUPD2 (0x4005C25C) /**< (PWM1) PWM Channel Dead Time Update Register 2 */ +#define REG_PWM1_CMR3 (0x4005C260) /**< (PWM1) PWM Channel Mode Register 3 */ +#define REG_PWM1_CDTY3 (0x4005C264) /**< (PWM1) PWM Channel Duty Cycle Register 3 */ +#define REG_PWM1_CDTYUPD3 (0x4005C268) /**< (PWM1) PWM Channel Duty Cycle Update Register 3 */ +#define REG_PWM1_CPRD3 (0x4005C26C) /**< (PWM1) PWM Channel Period Register 3 */ +#define REG_PWM1_CPRDUPD3 (0x4005C270) /**< (PWM1) PWM Channel Period Update Register 3 */ +#define REG_PWM1_CCNT3 (0x4005C274) /**< (PWM1) PWM Channel Counter Register 3 */ +#define REG_PWM1_DT3 (0x4005C278) /**< (PWM1) PWM Channel Dead Time Register 3 */ +#define REG_PWM1_DTUPD3 (0x4005C27C) /**< (PWM1) PWM Channel Dead Time Update Register 3 */ +#define REG_PWM1_CLK (0x4005C000) /**< (PWM1) PWM Clock Register */ +#define REG_PWM1_ENA (0x4005C004) /**< (PWM1) PWM Enable Register */ +#define REG_PWM1_DIS (0x4005C008) /**< (PWM1) PWM Disable Register */ +#define REG_PWM1_SR (0x4005C00C) /**< (PWM1) PWM Status Register */ +#define REG_PWM1_IER1 (0x4005C010) /**< (PWM1) PWM Interrupt Enable Register 1 */ +#define REG_PWM1_IDR1 (0x4005C014) /**< (PWM1) PWM Interrupt Disable Register 1 */ +#define REG_PWM1_IMR1 (0x4005C018) /**< (PWM1) PWM Interrupt Mask Register 1 */ +#define REG_PWM1_ISR1 (0x4005C01C) /**< (PWM1) PWM Interrupt Status Register 1 */ +#define REG_PWM1_SCM (0x4005C020) /**< (PWM1) PWM Sync Channels Mode Register */ +#define REG_PWM1_DMAR (0x4005C024) /**< (PWM1) PWM DMA Register */ +#define REG_PWM1_SCUC (0x4005C028) /**< (PWM1) PWM Sync Channels Update Control Register */ +#define REG_PWM1_SCUP (0x4005C02C) /**< (PWM1) PWM Sync Channels Update Period Register */ +#define REG_PWM1_SCUPUPD (0x4005C030) /**< (PWM1) PWM Sync Channels Update Period Update Register */ +#define REG_PWM1_IER2 (0x4005C034) /**< (PWM1) PWM Interrupt Enable Register 2 */ +#define REG_PWM1_IDR2 (0x4005C038) /**< (PWM1) PWM Interrupt Disable Register 2 */ +#define REG_PWM1_IMR2 (0x4005C03C) /**< (PWM1) PWM Interrupt Mask Register 2 */ +#define REG_PWM1_ISR2 (0x4005C040) /**< (PWM1) PWM Interrupt Status Register 2 */ +#define REG_PWM1_OOV (0x4005C044) /**< (PWM1) PWM Output Override Value Register */ +#define REG_PWM1_OS (0x4005C048) /**< (PWM1) PWM Output Selection Register */ +#define REG_PWM1_OSS (0x4005C04C) /**< (PWM1) PWM Output Selection Set Register */ +#define REG_PWM1_OSC (0x4005C050) /**< (PWM1) PWM Output Selection Clear Register */ +#define REG_PWM1_OSSUPD (0x4005C054) /**< (PWM1) PWM Output Selection Set Update Register */ +#define REG_PWM1_OSCUPD (0x4005C058) /**< (PWM1) PWM Output Selection Clear Update Register */ +#define REG_PWM1_FMR (0x4005C05C) /**< (PWM1) PWM Fault Mode Register */ +#define REG_PWM1_FSR (0x4005C060) /**< (PWM1) PWM Fault Status Register */ +#define REG_PWM1_FCR (0x4005C064) /**< (PWM1) PWM Fault Clear Register */ +#define REG_PWM1_FPV1 (0x4005C068) /**< (PWM1) PWM Fault Protection Value Register 1 */ +#define REG_PWM1_FPE (0x4005C06C) /**< (PWM1) PWM Fault Protection Enable Register */ +#define REG_PWM1_ELMR (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM1_ELMR0 (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM1_ELMR1 (0x4005C080) /**< (PWM1) PWM Event Line 0 Mode Register 1 */ +#define REG_PWM1_SSPR (0x4005C0A0) /**< (PWM1) PWM Spread Spectrum Register */ +#define REG_PWM1_SSPUP (0x4005C0A4) /**< (PWM1) PWM Spread Spectrum Update Register */ +#define REG_PWM1_SMMR (0x4005C0B0) /**< (PWM1) PWM Stepper Motor Mode Register */ +#define REG_PWM1_FPV2 (0x4005C0C0) /**< (PWM1) PWM Fault Protection Value 2 Register */ +#define REG_PWM1_WPCR (0x4005C0E4) /**< (PWM1) PWM Write Protection Control Register */ +#define REG_PWM1_WPSR (0x4005C0E8) /**< (PWM1) PWM Write Protection Status Register */ +#define REG_PWM1_CMUPD0 (0x4005C400) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM1_CMUPD1 (0x4005C420) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM1_ETRG1 (0x4005C42C) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */ +#define REG_PWM1_LEBR1 (0x4005C430) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ +#define REG_PWM1_CMUPD2 (0x4005C440) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM1_ETRG2 (0x4005C44C) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */ +#define REG_PWM1_LEBR2 (0x4005C450) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ +#define REG_PWM1_CMUPD3 (0x4005C460) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + +#else + +#define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< (PWM1) PWM Comparison 0 Value Register 0 */ +#define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */ +#define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< (PWM1) PWM Comparison 0 Mode Register 0 */ +#define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */ +#define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< (PWM1) PWM Comparison 0 Value Register 1 */ +#define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */ +#define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< (PWM1) PWM Comparison 0 Mode Register 1 */ +#define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */ +#define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< (PWM1) PWM Comparison 0 Value Register 2 */ +#define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */ +#define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< (PWM1) PWM Comparison 0 Mode Register 2 */ +#define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */ +#define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< (PWM1) PWM Comparison 0 Value Register 3 */ +#define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */ +#define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< (PWM1) PWM Comparison 0 Mode Register 3 */ +#define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */ +#define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< (PWM1) PWM Comparison 0 Value Register 4 */ +#define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */ +#define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< (PWM1) PWM Comparison 0 Mode Register 4 */ +#define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */ +#define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< (PWM1) PWM Comparison 0 Value Register 5 */ +#define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */ +#define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< (PWM1) PWM Comparison 0 Mode Register 5 */ +#define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */ +#define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< (PWM1) PWM Comparison 0 Value Register 6 */ +#define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */ +#define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< (PWM1) PWM Comparison 0 Mode Register 6 */ +#define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */ +#define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< (PWM1) PWM Comparison 0 Value Register 7 */ +#define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */ +#define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< (PWM1) PWM Comparison 0 Mode Register 7 */ +#define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */ +#define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< (PWM1) PWM Channel Mode Register 0 */ +#define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< (PWM1) PWM Channel Duty Cycle Register 0 */ +#define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< (PWM1) PWM Channel Duty Cycle Update Register 0 */ +#define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< (PWM1) PWM Channel Period Register 0 */ +#define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< (PWM1) PWM Channel Period Update Register 0 */ +#define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< (PWM1) PWM Channel Counter Register 0 */ +#define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< (PWM1) PWM Channel Dead Time Register 0 */ +#define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< (PWM1) PWM Channel Dead Time Update Register 0 */ +#define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< (PWM1) PWM Channel Mode Register 1 */ +#define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< (PWM1) PWM Channel Duty Cycle Register 1 */ +#define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< (PWM1) PWM Channel Duty Cycle Update Register 1 */ +#define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< (PWM1) PWM Channel Period Register 1 */ +#define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< (PWM1) PWM Channel Period Update Register 1 */ +#define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< (PWM1) PWM Channel Counter Register 1 */ +#define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< (PWM1) PWM Channel Dead Time Register 1 */ +#define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< (PWM1) PWM Channel Dead Time Update Register 1 */ +#define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< (PWM1) PWM Channel Mode Register 2 */ +#define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< (PWM1) PWM Channel Duty Cycle Register 2 */ +#define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< (PWM1) PWM Channel Duty Cycle Update Register 2 */ +#define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< (PWM1) PWM Channel Period Register 2 */ +#define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< (PWM1) PWM Channel Period Update Register 2 */ +#define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< (PWM1) PWM Channel Counter Register 2 */ +#define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< (PWM1) PWM Channel Dead Time Register 2 */ +#define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< (PWM1) PWM Channel Dead Time Update Register 2 */ +#define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< (PWM1) PWM Channel Mode Register 3 */ +#define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< (PWM1) PWM Channel Duty Cycle Register 3 */ +#define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< (PWM1) PWM Channel Duty Cycle Update Register 3 */ +#define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< (PWM1) PWM Channel Period Register 3 */ +#define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< (PWM1) PWM Channel Period Update Register 3 */ +#define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< (PWM1) PWM Channel Counter Register 3 */ +#define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< (PWM1) PWM Channel Dead Time Register 3 */ +#define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< (PWM1) PWM Channel Dead Time Update Register 3 */ +#define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< (PWM1) PWM Clock Register */ +#define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< (PWM1) PWM Enable Register */ +#define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< (PWM1) PWM Disable Register */ +#define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< (PWM1) PWM Status Register */ +#define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< (PWM1) PWM Interrupt Enable Register 1 */ +#define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< (PWM1) PWM Interrupt Disable Register 1 */ +#define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< (PWM1) PWM Interrupt Mask Register 1 */ +#define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< (PWM1) PWM Interrupt Status Register 1 */ +#define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< (PWM1) PWM Sync Channels Mode Register */ +#define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< (PWM1) PWM DMA Register */ +#define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< (PWM1) PWM Sync Channels Update Control Register */ +#define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< (PWM1) PWM Sync Channels Update Period Register */ +#define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< (PWM1) PWM Sync Channels Update Period Update Register */ +#define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< (PWM1) PWM Interrupt Enable Register 2 */ +#define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< (PWM1) PWM Interrupt Disable Register 2 */ +#define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< (PWM1) PWM Interrupt Mask Register 2 */ +#define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< (PWM1) PWM Interrupt Status Register 2 */ +#define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< (PWM1) PWM Output Override Value Register */ +#define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< (PWM1) PWM Output Selection Register */ +#define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< (PWM1) PWM Output Selection Set Register */ +#define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< (PWM1) PWM Output Selection Clear Register */ +#define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< (PWM1) PWM Output Selection Set Update Register */ +#define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< (PWM1) PWM Output Selection Clear Update Register */ +#define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< (PWM1) PWM Fault Mode Register */ +#define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< (PWM1) PWM Fault Status Register */ +#define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< (PWM1) PWM Fault Clear Register */ +#define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< (PWM1) PWM Fault Protection Value Register 1 */ +#define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< (PWM1) PWM Fault Protection Enable Register */ +#define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM1_ELMR0 (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */ +#define REG_PWM1_ELMR1 (*(__IO uint32_t*)0x4005C080U) /**< (PWM1) PWM Event Line 0 Mode Register 1 */ +#define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< (PWM1) PWM Spread Spectrum Register */ +#define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< (PWM1) PWM Spread Spectrum Update Register */ +#define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< (PWM1) PWM Stepper Motor Mode Register */ +#define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< (PWM1) PWM Fault Protection Value 2 Register */ +#define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< (PWM1) PWM Write Protection Control Register */ +#define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< (PWM1) PWM Write Protection Status Register */ +#define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */ +#define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ +#define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */ +#define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ +#define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for PWM1 peripheral ========== */ +#define PWM1_DMAC_ID_TX 39 +#define PWM1_INSTANCE_ID 60 +#define PWM1_CLOCK_ID 60 +#define PWM1_FAULT_PWM_ID0 0x0 /* Fault 0 - PWM0_PWMFI0 Input pin */ +#define PWM1_FAULT_PWM_ID1 0x1 /* Fault 1 - PWM0_PWMFI1 Input pin */ +#define PWM1_FAULT_PWM_ID2 0x2 /* Fault 2 - PWM0_PWMFI2 Input pin */ +#define PWM1_FAULT_PWM_ID3 0x3 /* Fault 3 - MAIN_OSC_PMC */ +#define PWM1_FAULT_PWM_ID4 0x4 /* Fault 4 - AFEC0 */ +#define PWM1_FAULT_PWM_ID5 0x5 /* Fault 5 - AFEC1 */ +#define PWM1_FAULT_PWM_ID6 0x6 /* Fault 6 - ACC */ +#define PWM1_FAULT_PWM_ID7 0x7 /* Fault 7 - TC1 */ + +#endif /* _SAME70_PWM1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/qspi.h b/bsp/microchip/same70/bsp/same70b/include/instance/qspi.h new file mode 100644 index 0000000000..0c6fde21f3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/qspi.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Instance description for QSPI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_QSPI_INSTANCE_H_ +#define _SAME70_QSPI_INSTANCE_H_ + +/* ========== Register definition for QSPI peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_QSPI_CR (0x4007C000) /**< (QSPI) Control Register */ +#define REG_QSPI_MR (0x4007C004) /**< (QSPI) Mode Register */ +#define REG_QSPI_RDR (0x4007C008) /**< (QSPI) Receive Data Register */ +#define REG_QSPI_TDR (0x4007C00C) /**< (QSPI) Transmit Data Register */ +#define REG_QSPI_SR (0x4007C010) /**< (QSPI) Status Register */ +#define REG_QSPI_IER (0x4007C014) /**< (QSPI) Interrupt Enable Register */ +#define REG_QSPI_IDR (0x4007C018) /**< (QSPI) Interrupt Disable Register */ +#define REG_QSPI_IMR (0x4007C01C) /**< (QSPI) Interrupt Mask Register */ +#define REG_QSPI_SCR (0x4007C020) /**< (QSPI) Serial Clock Register */ +#define REG_QSPI_IAR (0x4007C030) /**< (QSPI) Instruction Address Register */ +#define REG_QSPI_ICR (0x4007C034) /**< (QSPI) Instruction Code Register */ +#define REG_QSPI_IFR (0x4007C038) /**< (QSPI) Instruction Frame Register */ +#define REG_QSPI_SMR (0x4007C040) /**< (QSPI) Scrambling Mode Register */ +#define REG_QSPI_SKR (0x4007C044) /**< (QSPI) Scrambling Key Register */ +#define REG_QSPI_WPMR (0x4007C0E4) /**< (QSPI) Write Protection Mode Register */ +#define REG_QSPI_WPSR (0x4007C0E8) /**< (QSPI) Write Protection Status Register */ + +#else + +#define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */ +#define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< (QSPI) Mode Register */ +#define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< (QSPI) Receive Data Register */ +#define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */ +#define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< (QSPI) Status Register */ +#define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Register */ +#define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Register */ +#define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< (QSPI) Interrupt Mask Register */ +#define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< (QSPI) Serial Clock Register */ +#define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< (QSPI) Instruction Address Register */ +#define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< (QSPI) Instruction Code Register */ +#define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< (QSPI) Instruction Frame Register */ +#define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< (QSPI) Scrambling Mode Register */ +#define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register */ +#define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< (QSPI) Write Protection Mode Register */ +#define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< (QSPI) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for QSPI peripheral ========== */ +#define QSPI_DMAC_ID_RX 6 +#define QSPI_DMAC_ID_TX 5 +#define QSPI_INSTANCE_ID 43 +#define QSPI_CLOCK_ID 43 + +#endif /* _SAME70_QSPI_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/rstc.h b/bsp/microchip/same70/bsp/same70b/include/instance/rstc.h new file mode 100644 index 0000000000..b653288cef --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/rstc.h @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief Instance description for RSTC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RSTC_INSTANCE_H_ +#define _SAME70_RSTC_INSTANCE_H_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_RSTC_CR (0x400E1800) /**< (RSTC) Control Register */ +#define REG_RSTC_SR (0x400E1804) /**< (RSTC) Status Register */ +#define REG_RSTC_MR (0x400E1808) /**< (RSTC) Mode Register */ + +#else + +#define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< (RSTC) Control Register */ +#define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< (RSTC) Status Register */ +#define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< (RSTC) Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for RSTC peripheral ========== */ +#define RSTC_INSTANCE_ID 1 + +#endif /* _SAME70_RSTC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/rswdt.h b/bsp/microchip/same70/bsp/same70b/include/instance/rswdt.h new file mode 100644 index 0000000000..d57fe7da74 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/rswdt.h @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief Instance description for RSWDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RSWDT_INSTANCE_H_ +#define _SAME70_RSWDT_INSTANCE_H_ + +/* ========== Register definition for RSWDT peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_RSWDT_CR (0x400E1900) /**< (RSWDT) Control Register */ +#define REG_RSWDT_MR (0x400E1904) /**< (RSWDT) Mode Register */ +#define REG_RSWDT_SR (0x400E1908) /**< (RSWDT) Status Register */ + +#else + +#define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< (RSWDT) Control Register */ +#define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< (RSWDT) Mode Register */ +#define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< (RSWDT) Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for RSWDT peripheral ========== */ +#define RSWDT_INSTANCE_ID 63 + +#endif /* _SAME70_RSWDT_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/rtc.h b/bsp/microchip/same70/bsp/same70b/include/instance/rtc.h new file mode 100644 index 0000000000..d71648b1aa --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/rtc.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RTC_INSTANCE_H_ +#define _SAME70_RTC_INSTANCE_H_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_RTC_CR (0x400E1860) /**< (RTC) Control Register */ +#define REG_RTC_MR (0x400E1864) /**< (RTC) Mode Register */ +#define REG_RTC_TIMR (0x400E1868) /**< (RTC) Time Register */ +#define REG_RTC_CALR (0x400E186C) /**< (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0x400E1870) /**< (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0x400E1874) /**< (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0x400E1878) /**< (RTC) Status Register */ +#define REG_RTC_SCCR (0x400E187C) /**< (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0x400E1880) /**< (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0x400E1884) /**< (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0x400E1888) /**< (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0x400E188C) /**< (RTC) Valid Entry Register */ + +#else + +#define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< (RTC) Control Register */ +#define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< (RTC) Mode Register */ +#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< (RTC) Time Register */ +#define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< (RTC) Status Register */ +#define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< (RTC) Valid Entry Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for RTC peripheral ========== */ +#define RTC_INSTANCE_ID 2 + +#endif /* _SAME70_RTC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/rtt.h b/bsp/microchip/same70/bsp/same70b/include/instance/rtt.h new file mode 100644 index 0000000000..3b699345c0 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/rtt.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Instance description for RTT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_RTT_INSTANCE_H_ +#define _SAME70_RTT_INSTANCE_H_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_RTT_MR (0x400E1830) /**< (RTT) Mode Register */ +#define REG_RTT_AR (0x400E1834) /**< (RTT) Alarm Register */ +#define REG_RTT_VR (0x400E1838) /**< (RTT) Value Register */ +#define REG_RTT_SR (0x400E183C) /**< (RTT) Status Register */ + +#else + +#define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< (RTT) Mode Register */ +#define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< (RTT) Alarm Register */ +#define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< (RTT) Value Register */ +#define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< (RTT) Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for RTT peripheral ========== */ +#define RTT_INSTANCE_ID 3 + +#endif /* _SAME70_RTT_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/sdramc.h b/bsp/microchip/same70/bsp/same70b/include/instance/sdramc.h new file mode 100644 index 0000000000..e94d1ba2ca --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/sdramc.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for SDRAMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SDRAMC_INSTANCE_H_ +#define _SAME70_SDRAMC_INSTANCE_H_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SDRAMC_MR (0x40084000) /**< (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (0x40084004) /**< (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (0x40084008) /**< (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (0x40084010) /**< (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (0x40084014) /**< (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (0x40084018) /**< (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (0x4008401C) /**< (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (0x40084020) /**< (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (0x40084024) /**< (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CFR1 (0x40084028) /**< (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (0x4008402C) /**< (SDRAMC) SDRAMC OCMS Register */ +#define REG_SDRAMC_OCMS_KEY1 (0x40084030) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */ +#define REG_SDRAMC_OCMS_KEY2 (0x40084034) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */ + +#else + +#define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< (SDRAMC) SDRAMC OCMS Register */ +#define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */ +#define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SDRAMC peripheral ========== */ +#define SDRAMC_INSTANCE_ID 62 +#define SDRAMC_CLOCK_ID 62 + +#endif /* _SAME70_SDRAMC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/smc.h b/bsp/microchip/same70/bsp/same70b/include/instance/smc.h new file mode 100644 index 0000000000..a67f5b7bd3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/smc.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief Instance description for SMC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SMC_INSTANCE_H_ +#define _SAME70_SMC_INSTANCE_H_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SMC_SETUP0 (0x40080000) /**< (SMC) SMC Setup Register 0 */ +#define REG_SMC_PULSE0 (0x40080004) /**< (SMC) SMC Pulse Register 0 */ +#define REG_SMC_CYCLE0 (0x40080008) /**< (SMC) SMC Cycle Register 0 */ +#define REG_SMC_MODE0 (0x4008000C) /**< (SMC) SMC Mode Register 0 */ +#define REG_SMC_SETUP1 (0x40080010) /**< (SMC) SMC Setup Register 1 */ +#define REG_SMC_PULSE1 (0x40080014) /**< (SMC) SMC Pulse Register 1 */ +#define REG_SMC_CYCLE1 (0x40080018) /**< (SMC) SMC Cycle Register 1 */ +#define REG_SMC_MODE1 (0x4008001C) /**< (SMC) SMC Mode Register 1 */ +#define REG_SMC_SETUP2 (0x40080020) /**< (SMC) SMC Setup Register 2 */ +#define REG_SMC_PULSE2 (0x40080024) /**< (SMC) SMC Pulse Register 2 */ +#define REG_SMC_CYCLE2 (0x40080028) /**< (SMC) SMC Cycle Register 2 */ +#define REG_SMC_MODE2 (0x4008002C) /**< (SMC) SMC Mode Register 2 */ +#define REG_SMC_SETUP3 (0x40080030) /**< (SMC) SMC Setup Register 3 */ +#define REG_SMC_PULSE3 (0x40080034) /**< (SMC) SMC Pulse Register 3 */ +#define REG_SMC_CYCLE3 (0x40080038) /**< (SMC) SMC Cycle Register 3 */ +#define REG_SMC_MODE3 (0x4008003C) /**< (SMC) SMC Mode Register 3 */ +#define REG_SMC_OCMS (0x40080080) /**< (SMC) SMC Off-Chip Memory Scrambling Register */ +#define REG_SMC_KEY1 (0x40080084) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ +#define REG_SMC_KEY2 (0x40080088) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ +#define REG_SMC_WPMR (0x400800E4) /**< (SMC) SMC Write Protection Mode Register */ +#define REG_SMC_WPSR (0x400800E8) /**< (SMC) SMC Write Protection Status Register */ + +#else + +#define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< (SMC) SMC Setup Register 0 */ +#define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< (SMC) SMC Pulse Register 0 */ +#define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< (SMC) SMC Cycle Register 0 */ +#define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< (SMC) SMC Mode Register 0 */ +#define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< (SMC) SMC Setup Register 1 */ +#define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< (SMC) SMC Pulse Register 1 */ +#define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< (SMC) SMC Cycle Register 1 */ +#define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< (SMC) SMC Mode Register 1 */ +#define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< (SMC) SMC Setup Register 2 */ +#define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< (SMC) SMC Pulse Register 2 */ +#define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< (SMC) SMC Cycle Register 2 */ +#define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< (SMC) SMC Mode Register 2 */ +#define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< (SMC) SMC Setup Register 3 */ +#define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< (SMC) SMC Pulse Register 3 */ +#define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< (SMC) SMC Cycle Register 3 */ +#define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< (SMC) SMC Mode Register 3 */ +#define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< (SMC) SMC Off-Chip Memory Scrambling Register */ +#define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */ +#define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */ +#define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< (SMC) SMC Write Protection Mode Register */ +#define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< (SMC) SMC Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SMC peripheral ========== */ +#define SMC_INSTANCE_ID 9 +#define SMC_CLOCK_ID 9 + +#endif /* _SAME70_SMC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/spi0.h b/bsp/microchip/same70/bsp/same70b/include/instance/spi0.h new file mode 100644 index 0000000000..59dd0ce223 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/spi0.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Instance description for SPI0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SPI0_INSTANCE_H_ +#define _SAME70_SPI0_INSTANCE_H_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SPI0_CR (0x40008000) /**< (SPI0) Control Register */ +#define REG_SPI0_MR (0x40008004) /**< (SPI0) Mode Register */ +#define REG_SPI0_RDR (0x40008008) /**< (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (0x4000800C) /**< (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (0x40008010) /**< (SPI0) Status Register */ +#define REG_SPI0_IER (0x40008014) /**< (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (0x40008018) /**< (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (0x40008030) /**< (SPI0) Chip Select Register */ +#define REG_SPI0_CSR0 (0x40008030) /**< (SPI0) Chip Select Register 0 */ +#define REG_SPI0_CSR1 (0x40008034) /**< (SPI0) Chip Select Register 1 */ +#define REG_SPI0_CSR2 (0x40008038) /**< (SPI0) Chip Select Register 2 */ +#define REG_SPI0_CSR3 (0x4000803C) /**< (SPI0) Chip Select Register 3 */ +#define REG_SPI0_WPMR (0x400080E4) /**< (SPI0) Write Protection Mode Register */ +#define REG_SPI0_WPSR (0x400080E8) /**< (SPI0) Write Protection Status Register */ + +#else + +#define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< (SPI0) Control Register */ +#define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< (SPI0) Mode Register */ +#define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< (SPI0) Status Register */ +#define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register */ +#define REG_SPI0_CSR0 (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register 0 */ +#define REG_SPI0_CSR1 (*(__IO uint32_t*)0x40008034U) /**< (SPI0) Chip Select Register 1 */ +#define REG_SPI0_CSR2 (*(__IO uint32_t*)0x40008038U) /**< (SPI0) Chip Select Register 2 */ +#define REG_SPI0_CSR3 (*(__IO uint32_t*)0x4000803CU) /**< (SPI0) Chip Select Register 3 */ +#define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< (SPI0) Write Protection Mode Register */ +#define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< (SPI0) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SPI0 peripheral ========== */ +#define SPI0_DMAC_ID_RX 2 +#define SPI0_DMAC_ID_TX 1 +#define SPI0_INSTANCE_ID 21 +#define SPI0_CLOCK_ID 21 + +#endif /* _SAME70_SPI0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/spi1.h b/bsp/microchip/same70/bsp/same70b/include/instance/spi1.h new file mode 100644 index 0000000000..72dcd7ea73 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/spi1.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Instance description for SPI1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SPI1_INSTANCE_H_ +#define _SAME70_SPI1_INSTANCE_H_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SPI1_CR (0x40058000) /**< (SPI1) Control Register */ +#define REG_SPI1_MR (0x40058004) /**< (SPI1) Mode Register */ +#define REG_SPI1_RDR (0x40058008) /**< (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (0x4005800C) /**< (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (0x40058010) /**< (SPI1) Status Register */ +#define REG_SPI1_IER (0x40058014) /**< (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (0x40058018) /**< (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (0x4005801C) /**< (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (0x40058030) /**< (SPI1) Chip Select Register */ +#define REG_SPI1_CSR0 (0x40058030) /**< (SPI1) Chip Select Register 0 */ +#define REG_SPI1_CSR1 (0x40058034) /**< (SPI1) Chip Select Register 1 */ +#define REG_SPI1_CSR2 (0x40058038) /**< (SPI1) Chip Select Register 2 */ +#define REG_SPI1_CSR3 (0x4005803C) /**< (SPI1) Chip Select Register 3 */ +#define REG_SPI1_WPMR (0x400580E4) /**< (SPI1) Write Protection Mode Register */ +#define REG_SPI1_WPSR (0x400580E8) /**< (SPI1) Write Protection Status Register */ + +#else + +#define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< (SPI1) Control Register */ +#define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< (SPI1) Mode Register */ +#define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< (SPI1) Status Register */ +#define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register */ +#define REG_SPI1_CSR0 (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */ +#define REG_SPI1_CSR1 (*(__IO uint32_t*)0x40058034U) /**< (SPI1) Chip Select Register 1 */ +#define REG_SPI1_CSR2 (*(__IO uint32_t*)0x40058038U) /**< (SPI1) Chip Select Register 2 */ +#define REG_SPI1_CSR3 (*(__IO uint32_t*)0x4005803CU) /**< (SPI1) Chip Select Register 3 */ +#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< (SPI1) Write Protection Mode Register */ +#define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< (SPI1) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SPI1 peripheral ========== */ +#define SPI1_DMAC_ID_RX 4 +#define SPI1_DMAC_ID_TX 3 +#define SPI1_INSTANCE_ID 42 +#define SPI1_CLOCK_ID 42 + +#endif /* _SAME70_SPI1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/ssc.h b/bsp/microchip/same70/bsp/same70b/include/instance/ssc.h new file mode 100644 index 0000000000..adcfe768d8 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/ssc.h @@ -0,0 +1,85 @@ +/** + * \file + * + * \brief Instance description for SSC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SSC_INSTANCE_H_ +#define _SAME70_SSC_INSTANCE_H_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SSC_CR (0x40004000) /**< (SSC) Control Register */ +#define REG_SSC_CMR (0x40004004) /**< (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (0x40004010) /**< (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (0x40004014) /**< (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (0x40004018) /**< (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (0x4000401C) /**< (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (0x40004020) /**< (SSC) Receive Holding Register */ +#define REG_SSC_THR (0x40004024) /**< (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (0x40004030) /**< (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (0x40004034) /**< (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (0x40004038) /**< (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (0x4000403C) /**< (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (0x40004040) /**< (SSC) Status Register */ +#define REG_SSC_IER (0x40004044) /**< (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (0x40004048) /**< (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (0x4000404C) /**< (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (0x400040E4) /**< (SSC) Write Protection Mode Register */ +#define REG_SSC_WPSR (0x400040E8) /**< (SSC) Write Protection Status Register */ + +#else + +#define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< (SSC) Control Register */ +#define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< (SSC) Receive Holding Register */ +#define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< (SSC) Status Register */ +#define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< (SSC) Write Protection Mode Register */ +#define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< (SSC) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SSC peripheral ========== */ +#define SSC_DMAC_ID_RX 33 +#define SSC_DMAC_ID_TX 32 +#define SSC_INSTANCE_ID 22 +#define SSC_CLOCK_ID 22 + +#endif /* _SAME70_SSC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/supc.h b/bsp/microchip/same70/bsp/same70b/include/instance/supc.h new file mode 100644 index 0000000000..845066b653 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/supc.h @@ -0,0 +1,58 @@ +/** + * \file + * + * \brief Instance description for SUPC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_SUPC_INSTANCE_H_ +#define _SAME70_SUPC_INSTANCE_H_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_SUPC_CR (0x400E1810) /**< (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (0x400E1814) /**< (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (0x400E1818) /**< (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (0x400E181C) /**< (SUPC) Supply Controller Wake-up Mode Register */ +#define REG_SUPC_WUIR (0x400E1820) /**< (SUPC) Supply Controller Wake-up Inputs Register */ +#define REG_SUPC_SR (0x400E1824) /**< (SUPC) Supply Controller Status Register */ + +#else + +#define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< (SUPC) Supply Controller Wake-up Mode Register */ +#define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< (SUPC) Supply Controller Wake-up Inputs Register */ +#define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< (SUPC) Supply Controller Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for SUPC peripheral ========== */ +#define SUPC_INSTANCE_ID 0 + +#endif /* _SAME70_SUPC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/tc0.h b/bsp/microchip/same70/bsp/same70b/include/instance/tc0.h new file mode 100644 index 0000000000..760577b25f --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/tc0.h @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TC0_INSTANCE_H_ +#define _SAME70_TC0_INSTANCE_H_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TC0_CCR0 (0x4000C000) /**< (TC0) Channel Control Register (channel = 0) 0 */ +#define REG_TC0_CMR0 (0x4000C004) /**< (TC0) Channel Mode Register (channel = 0) 0 */ +#define REG_TC0_SMMR0 (0x4000C008) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC0_RAB0 (0x4000C00C) /**< (TC0) Register AB (channel = 0) 0 */ +#define REG_TC0_CV0 (0x4000C010) /**< (TC0) Counter Value (channel = 0) 0 */ +#define REG_TC0_RA0 (0x4000C014) /**< (TC0) Register A (channel = 0) 0 */ +#define REG_TC0_RB0 (0x4000C018) /**< (TC0) Register B (channel = 0) 0 */ +#define REG_TC0_RC0 (0x4000C01C) /**< (TC0) Register C (channel = 0) 0 */ +#define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */ +#define REG_TC0_IER0 (0x4000C024) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC0_IDR0 (0x4000C028) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC0_IMR0 (0x4000C02C) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC0_EMR0 (0x4000C030) /**< (TC0) Extended Mode Register (channel = 0) 0 */ +#define REG_TC0_CCR1 (0x4000C040) /**< (TC0) Channel Control Register (channel = 0) 1 */ +#define REG_TC0_CMR1 (0x4000C044) /**< (TC0) Channel Mode Register (channel = 0) 1 */ +#define REG_TC0_SMMR1 (0x4000C048) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC0_RAB1 (0x4000C04C) /**< (TC0) Register AB (channel = 0) 1 */ +#define REG_TC0_CV1 (0x4000C050) /**< (TC0) Counter Value (channel = 0) 1 */ +#define REG_TC0_RA1 (0x4000C054) /**< (TC0) Register A (channel = 0) 1 */ +#define REG_TC0_RB1 (0x4000C058) /**< (TC0) Register B (channel = 0) 1 */ +#define REG_TC0_RC1 (0x4000C05C) /**< (TC0) Register C (channel = 0) 1 */ +#define REG_TC0_SR1 (0x4000C060) /**< (TC0) Status Register (channel = 0) 1 */ +#define REG_TC0_IER1 (0x4000C064) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC0_IDR1 (0x4000C068) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC0_EMR1 (0x4000C070) /**< (TC0) Extended Mode Register (channel = 0) 1 */ +#define REG_TC0_CCR2 (0x4000C080) /**< (TC0) Channel Control Register (channel = 0) 2 */ +#define REG_TC0_CMR2 (0x4000C084) /**< (TC0) Channel Mode Register (channel = 0) 2 */ +#define REG_TC0_SMMR2 (0x4000C088) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC0_RAB2 (0x4000C08C) /**< (TC0) Register AB (channel = 0) 2 */ +#define REG_TC0_CV2 (0x4000C090) /**< (TC0) Counter Value (channel = 0) 2 */ +#define REG_TC0_RA2 (0x4000C094) /**< (TC0) Register A (channel = 0) 2 */ +#define REG_TC0_RB2 (0x4000C098) /**< (TC0) Register B (channel = 0) 2 */ +#define REG_TC0_RC2 (0x4000C09C) /**< (TC0) Register C (channel = 0) 2 */ +#define REG_TC0_SR2 (0x4000C0A0) /**< (TC0) Status Register (channel = 0) 2 */ +#define REG_TC0_IER2 (0x4000C0A4) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC0_IDR2 (0x4000C0A8) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC0_IMR2 (0x4000C0AC) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC0_EMR2 (0x4000C0B0) /**< (TC0) Extended Mode Register (channel = 0) 2 */ +#define REG_TC0_BCR (0x4000C0C0) /**< (TC0) Block Control Register */ +#define REG_TC0_BMR (0x4000C0C4) /**< (TC0) Block Mode Register */ +#define REG_TC0_QIER (0x4000C0C8) /**< (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (0x4000C0CC) /**< (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (0x4000C0D0) /**< (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (0x4000C0D4) /**< (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (0x4000C0D8) /**< (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (0x4000C0E4) /**< (TC0) Write Protection Mode Register */ + +#else + +#define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< (TC0) Channel Control Register (channel = 0) 0 */ +#define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< (TC0) Channel Mode Register (channel = 0) 0 */ +#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< (TC0) Register AB (channel = 0) 0 */ +#define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< (TC0) Counter Value (channel = 0) 0 */ +#define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< (TC0) Register A (channel = 0) 0 */ +#define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< (TC0) Register B (channel = 0) 0 */ +#define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< (TC0) Register C (channel = 0) 0 */ +#define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel = 0) 0 */ +#define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< (TC0) Extended Mode Register (channel = 0) 0 */ +#define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< (TC0) Channel Control Register (channel = 0) 1 */ +#define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< (TC0) Channel Mode Register (channel = 0) 1 */ +#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< (TC0) Register AB (channel = 0) 1 */ +#define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< (TC0) Counter Value (channel = 0) 1 */ +#define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< (TC0) Register A (channel = 0) 1 */ +#define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< (TC0) Register B (channel = 0) 1 */ +#define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< (TC0) Register C (channel = 0) 1 */ +#define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< (TC0) Status Register (channel = 0) 1 */ +#define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< (TC0) Extended Mode Register (channel = 0) 1 */ +#define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< (TC0) Channel Control Register (channel = 0) 2 */ +#define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< (TC0) Channel Mode Register (channel = 0) 2 */ +#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< (TC0) Register AB (channel = 0) 2 */ +#define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< (TC0) Counter Value (channel = 0) 2 */ +#define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< (TC0) Register A (channel = 0) 2 */ +#define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< (TC0) Register B (channel = 0) 2 */ +#define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< (TC0) Register C (channel = 0) 2 */ +#define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< (TC0) Status Register (channel = 0) 2 */ +#define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< (TC0) Extended Mode Register (channel = 0) 2 */ +#define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< (TC0) Block Control Register */ +#define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< (TC0) Block Mode Register */ +#define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< (TC0) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TC0 peripheral ========== */ +#define TC0_DMAC_ID_RX 40 +#define TC0_INSTANCE_ID_CHANNEL0 23 +#define TC0_INSTANCE_ID_CHANNEL1 24 +#define TC0_INSTANCE_ID_CHANNEL2 25 +#define TC0_CLOCK_ID_CHANNEL0 23 +#define TC0_CLOCK_ID_CHANNEL1 24 +#define TC0_CLOCK_ID_CHANNEL2 25 +#define TC0_TCCLKS_ 0 /* MCK */ +#define TC0_TCCLKS_TIMER_CLOCK1 1 /* PCK */ +#define TC0_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ +#define TC0_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ +#define TC0_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ +#define TC0_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ +#define TC0_TCCLKS_XC0 6 /* XC0 */ +#define TC0_TCCLKS_XC1 7 /* XC1 */ +#define TC0_TCCLKS_XC2 8 /* XC2 */ +#define TC0_NUM_INTERRUPT_LINES 3 +#define TC0_TIMER_WIDTH 16 + +#endif /* _SAME70_TC0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/tc1.h b/bsp/microchip/same70/bsp/same70b/include/instance/tc1.h new file mode 100644 index 0000000000..f7aad2d06c --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/tc1.h @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Instance description for TC1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TC1_INSTANCE_H_ +#define _SAME70_TC1_INSTANCE_H_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TC1_CCR0 (0x40010000) /**< (TC1) Channel Control Register (channel = 0) 0 */ +#define REG_TC1_CMR0 (0x40010004) /**< (TC1) Channel Mode Register (channel = 0) 0 */ +#define REG_TC1_SMMR0 (0x40010008) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC1_RAB0 (0x4001000C) /**< (TC1) Register AB (channel = 0) 0 */ +#define REG_TC1_CV0 (0x40010010) /**< (TC1) Counter Value (channel = 0) 0 */ +#define REG_TC1_RA0 (0x40010014) /**< (TC1) Register A (channel = 0) 0 */ +#define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ +#define REG_TC1_RC0 (0x4001001C) /**< (TC1) Register C (channel = 0) 0 */ +#define REG_TC1_SR0 (0x40010020) /**< (TC1) Status Register (channel = 0) 0 */ +#define REG_TC1_IER0 (0x40010024) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC1_IDR0 (0x40010028) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC1_IMR0 (0x4001002C) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC1_EMR0 (0x40010030) /**< (TC1) Extended Mode Register (channel = 0) 0 */ +#define REG_TC1_CCR1 (0x40010040) /**< (TC1) Channel Control Register (channel = 0) 1 */ +#define REG_TC1_CMR1 (0x40010044) /**< (TC1) Channel Mode Register (channel = 0) 1 */ +#define REG_TC1_SMMR1 (0x40010048) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC1_RAB1 (0x4001004C) /**< (TC1) Register AB (channel = 0) 1 */ +#define REG_TC1_CV1 (0x40010050) /**< (TC1) Counter Value (channel = 0) 1 */ +#define REG_TC1_RA1 (0x40010054) /**< (TC1) Register A (channel = 0) 1 */ +#define REG_TC1_RB1 (0x40010058) /**< (TC1) Register B (channel = 0) 1 */ +#define REG_TC1_RC1 (0x4001005C) /**< (TC1) Register C (channel = 0) 1 */ +#define REG_TC1_SR1 (0x40010060) /**< (TC1) Status Register (channel = 0) 1 */ +#define REG_TC1_IER1 (0x40010064) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC1_IDR1 (0x40010068) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC1_IMR1 (0x4001006C) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC1_EMR1 (0x40010070) /**< (TC1) Extended Mode Register (channel = 0) 1 */ +#define REG_TC1_CCR2 (0x40010080) /**< (TC1) Channel Control Register (channel = 0) 2 */ +#define REG_TC1_CMR2 (0x40010084) /**< (TC1) Channel Mode Register (channel = 0) 2 */ +#define REG_TC1_SMMR2 (0x40010088) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC1_RAB2 (0x4001008C) /**< (TC1) Register AB (channel = 0) 2 */ +#define REG_TC1_CV2 (0x40010090) /**< (TC1) Counter Value (channel = 0) 2 */ +#define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ +#define REG_TC1_RB2 (0x40010098) /**< (TC1) Register B (channel = 0) 2 */ +#define REG_TC1_RC2 (0x4001009C) /**< (TC1) Register C (channel = 0) 2 */ +#define REG_TC1_SR2 (0x400100A0) /**< (TC1) Status Register (channel = 0) 2 */ +#define REG_TC1_IER2 (0x400100A4) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC1_IDR2 (0x400100A8) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC1_IMR2 (0x400100AC) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC1_EMR2 (0x400100B0) /**< (TC1) Extended Mode Register (channel = 0) 2 */ +#define REG_TC1_BCR (0x400100C0) /**< (TC1) Block Control Register */ +#define REG_TC1_BMR (0x400100C4) /**< (TC1) Block Mode Register */ +#define REG_TC1_QIER (0x400100C8) /**< (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (0x400100CC) /**< (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (0x400100D4) /**< (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (0x400100D8) /**< (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (0x400100E4) /**< (TC1) Write Protection Mode Register */ + +#else + +#define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< (TC1) Channel Control Register (channel = 0) 0 */ +#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< (TC1) Channel Mode Register (channel = 0) 0 */ +#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< (TC1) Register AB (channel = 0) 0 */ +#define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< (TC1) Counter Value (channel = 0) 0 */ +#define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< (TC1) Register A (channel = 0) 0 */ +#define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) 0 */ +#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< (TC1) Register C (channel = 0) 0 */ +#define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< (TC1) Status Register (channel = 0) 0 */ +#define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< (TC1) Extended Mode Register (channel = 0) 0 */ +#define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< (TC1) Channel Control Register (channel = 0) 1 */ +#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< (TC1) Channel Mode Register (channel = 0) 1 */ +#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< (TC1) Register AB (channel = 0) 1 */ +#define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< (TC1) Counter Value (channel = 0) 1 */ +#define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< (TC1) Register A (channel = 0) 1 */ +#define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< (TC1) Register B (channel = 0) 1 */ +#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< (TC1) Register C (channel = 0) 1 */ +#define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< (TC1) Status Register (channel = 0) 1 */ +#define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< (TC1) Extended Mode Register (channel = 0) 1 */ +#define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< (TC1) Channel Control Register (channel = 0) 2 */ +#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< (TC1) Channel Mode Register (channel = 0) 2 */ +#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< (TC1) Register AB (channel = 0) 2 */ +#define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< (TC1) Counter Value (channel = 0) 2 */ +#define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) 2 */ +#define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< (TC1) Register B (channel = 0) 2 */ +#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< (TC1) Register C (channel = 0) 2 */ +#define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< (TC1) Status Register (channel = 0) 2 */ +#define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< (TC1) Extended Mode Register (channel = 0) 2 */ +#define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< (TC1) Block Control Register */ +#define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< (TC1) Block Mode Register */ +#define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< (TC1) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TC1 peripheral ========== */ +#define TC1_DMAC_ID_RX 41 +#define TC1_INSTANCE_ID_CHANNEL0 26 +#define TC1_INSTANCE_ID_CHANNEL1 27 +#define TC1_INSTANCE_ID_CHANNEL2 28 +#define TC1_CLOCK_ID_CHANNEL0 26 +#define TC1_CLOCK_ID_CHANNEL1 27 +#define TC1_CLOCK_ID_CHANNEL2 28 +#define TC1_TCCLKS_ 0 /* MCK */ +#define TC1_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */ +#define TC1_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ +#define TC1_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ +#define TC1_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ +#define TC1_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ +#define TC1_TCCLKS_XC0 6 /* XC0 */ +#define TC1_TCCLKS_XC1 7 /* XC1 */ +#define TC1_TCCLKS_XC2 8 /* XC2 */ +#define TC1_NUM_INTERRUPT_LINES 3 +#define TC1_TIMER_WIDTH 16 + +#endif /* _SAME70_TC1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/tc2.h b/bsp/microchip/same70/bsp/same70b/include/instance/tc2.h new file mode 100644 index 0000000000..c7069930ef --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/tc2.h @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Instance description for TC2 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TC2_INSTANCE_H_ +#define _SAME70_TC2_INSTANCE_H_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TC2_CCR0 (0x40014000) /**< (TC2) Channel Control Register (channel = 0) 0 */ +#define REG_TC2_CMR0 (0x40014004) /**< (TC2) Channel Mode Register (channel = 0) 0 */ +#define REG_TC2_SMMR0 (0x40014008) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC2_RAB0 (0x4001400C) /**< (TC2) Register AB (channel = 0) 0 */ +#define REG_TC2_CV0 (0x40014010) /**< (TC2) Counter Value (channel = 0) 0 */ +#define REG_TC2_RA0 (0x40014014) /**< (TC2) Register A (channel = 0) 0 */ +#define REG_TC2_RB0 (0x40014018) /**< (TC2) Register B (channel = 0) 0 */ +#define REG_TC2_RC0 (0x4001401C) /**< (TC2) Register C (channel = 0) 0 */ +#define REG_TC2_SR0 (0x40014020) /**< (TC2) Status Register (channel = 0) 0 */ +#define REG_TC2_IER0 (0x40014024) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC2_IDR0 (0x40014028) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC2_IMR0 (0x4001402C) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC2_EMR0 (0x40014030) /**< (TC2) Extended Mode Register (channel = 0) 0 */ +#define REG_TC2_CCR1 (0x40014040) /**< (TC2) Channel Control Register (channel = 0) 1 */ +#define REG_TC2_CMR1 (0x40014044) /**< (TC2) Channel Mode Register (channel = 0) 1 */ +#define REG_TC2_SMMR1 (0x40014048) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC2_RAB1 (0x4001404C) /**< (TC2) Register AB (channel = 0) 1 */ +#define REG_TC2_CV1 (0x40014050) /**< (TC2) Counter Value (channel = 0) 1 */ +#define REG_TC2_RA1 (0x40014054) /**< (TC2) Register A (channel = 0) 1 */ +#define REG_TC2_RB1 (0x40014058) /**< (TC2) Register B (channel = 0) 1 */ +#define REG_TC2_RC1 (0x4001405C) /**< (TC2) Register C (channel = 0) 1 */ +#define REG_TC2_SR1 (0x40014060) /**< (TC2) Status Register (channel = 0) 1 */ +#define REG_TC2_IER1 (0x40014064) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC2_IDR1 (0x40014068) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC2_IMR1 (0x4001406C) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC2_EMR1 (0x40014070) /**< (TC2) Extended Mode Register (channel = 0) 1 */ +#define REG_TC2_CCR2 (0x40014080) /**< (TC2) Channel Control Register (channel = 0) 2 */ +#define REG_TC2_CMR2 (0x40014084) /**< (TC2) Channel Mode Register (channel = 0) 2 */ +#define REG_TC2_SMMR2 (0x40014088) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC2_RAB2 (0x4001408C) /**< (TC2) Register AB (channel = 0) 2 */ +#define REG_TC2_CV2 (0x40014090) /**< (TC2) Counter Value (channel = 0) 2 */ +#define REG_TC2_RA2 (0x40014094) /**< (TC2) Register A (channel = 0) 2 */ +#define REG_TC2_RB2 (0x40014098) /**< (TC2) Register B (channel = 0) 2 */ +#define REG_TC2_RC2 (0x4001409C) /**< (TC2) Register C (channel = 0) 2 */ +#define REG_TC2_SR2 (0x400140A0) /**< (TC2) Status Register (channel = 0) 2 */ +#define REG_TC2_IER2 (0x400140A4) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC2_IDR2 (0x400140A8) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC2_IMR2 (0x400140AC) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC2_EMR2 (0x400140B0) /**< (TC2) Extended Mode Register (channel = 0) 2 */ +#define REG_TC2_BCR (0x400140C0) /**< (TC2) Block Control Register */ +#define REG_TC2_BMR (0x400140C4) /**< (TC2) Block Mode Register */ +#define REG_TC2_QIER (0x400140C8) /**< (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (0x400140CC) /**< (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (0x400140D0) /**< (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (0x400140D4) /**< (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (0x400140D8) /**< (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (0x400140E4) /**< (TC2) Write Protection Mode Register */ + +#else + +#define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< (TC2) Channel Control Register (channel = 0) 0 */ +#define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< (TC2) Channel Mode Register (channel = 0) 0 */ +#define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< (TC2) Register AB (channel = 0) 0 */ +#define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< (TC2) Counter Value (channel = 0) 0 */ +#define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< (TC2) Register A (channel = 0) 0 */ +#define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< (TC2) Register B (channel = 0) 0 */ +#define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< (TC2) Register C (channel = 0) 0 */ +#define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< (TC2) Status Register (channel = 0) 0 */ +#define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< (TC2) Extended Mode Register (channel = 0) 0 */ +#define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< (TC2) Channel Control Register (channel = 0) 1 */ +#define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< (TC2) Channel Mode Register (channel = 0) 1 */ +#define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< (TC2) Register AB (channel = 0) 1 */ +#define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< (TC2) Counter Value (channel = 0) 1 */ +#define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< (TC2) Register A (channel = 0) 1 */ +#define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< (TC2) Register B (channel = 0) 1 */ +#define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< (TC2) Register C (channel = 0) 1 */ +#define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< (TC2) Status Register (channel = 0) 1 */ +#define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< (TC2) Extended Mode Register (channel = 0) 1 */ +#define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< (TC2) Channel Control Register (channel = 0) 2 */ +#define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< (TC2) Channel Mode Register (channel = 0) 2 */ +#define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< (TC2) Register AB (channel = 0) 2 */ +#define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< (TC2) Counter Value (channel = 0) 2 */ +#define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< (TC2) Register A (channel = 0) 2 */ +#define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< (TC2) Register B (channel = 0) 2 */ +#define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< (TC2) Register C (channel = 0) 2 */ +#define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< (TC2) Status Register (channel = 0) 2 */ +#define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< (TC2) Extended Mode Register (channel = 0) 2 */ +#define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< (TC2) Block Control Register */ +#define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< (TC2) Block Mode Register */ +#define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< (TC2) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TC2 peripheral ========== */ +#define TC2_DMAC_ID_RX 42 +#define TC2_INSTANCE_ID_CHANNEL0 47 +#define TC2_INSTANCE_ID_CHANNEL1 48 +#define TC2_INSTANCE_ID_CHANNEL2 49 +#define TC2_CLOCK_ID_CHANNEL0 47 +#define TC2_CLOCK_ID_CHANNEL1 48 +#define TC2_CLOCK_ID_CHANNEL2 49 +#define TC2_TCCLKS_ 0 /* MCK */ +#define TC2_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */ +#define TC2_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ +#define TC2_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ +#define TC2_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ +#define TC2_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ +#define TC2_TCCLKS_XC0 6 /* XC0 */ +#define TC2_TCCLKS_XC1 7 /* XC1 */ +#define TC2_TCCLKS_XC2 8 /* XC2 */ +#define TC2_NUM_INTERRUPT_LINES 3 +#define TC2_TIMER_WIDTH 16 + +#endif /* _SAME70_TC2_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/tc3.h b/bsp/microchip/same70/bsp/same70b/include/instance/tc3.h new file mode 100644 index 0000000000..16758251cd --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/tc3.h @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TC3_INSTANCE_H_ +#define _SAME70_TC3_INSTANCE_H_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TC3_CCR0 (0x40054000) /**< (TC3) Channel Control Register (channel = 0) 0 */ +#define REG_TC3_CMR0 (0x40054004) /**< (TC3) Channel Mode Register (channel = 0) 0 */ +#define REG_TC3_SMMR0 (0x40054008) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC3_RAB0 (0x4005400C) /**< (TC3) Register AB (channel = 0) 0 */ +#define REG_TC3_CV0 (0x40054010) /**< (TC3) Counter Value (channel = 0) 0 */ +#define REG_TC3_RA0 (0x40054014) /**< (TC3) Register A (channel = 0) 0 */ +#define REG_TC3_RB0 (0x40054018) /**< (TC3) Register B (channel = 0) 0 */ +#define REG_TC3_RC0 (0x4005401C) /**< (TC3) Register C (channel = 0) 0 */ +#define REG_TC3_SR0 (0x40054020) /**< (TC3) Status Register (channel = 0) 0 */ +#define REG_TC3_IER0 (0x40054024) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC3_IDR0 (0x40054028) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC3_IMR0 (0x4005402C) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC3_EMR0 (0x40054030) /**< (TC3) Extended Mode Register (channel = 0) 0 */ +#define REG_TC3_CCR1 (0x40054040) /**< (TC3) Channel Control Register (channel = 0) 1 */ +#define REG_TC3_CMR1 (0x40054044) /**< (TC3) Channel Mode Register (channel = 0) 1 */ +#define REG_TC3_SMMR1 (0x40054048) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC3_RAB1 (0x4005404C) /**< (TC3) Register AB (channel = 0) 1 */ +#define REG_TC3_CV1 (0x40054050) /**< (TC3) Counter Value (channel = 0) 1 */ +#define REG_TC3_RA1 (0x40054054) /**< (TC3) Register A (channel = 0) 1 */ +#define REG_TC3_RB1 (0x40054058) /**< (TC3) Register B (channel = 0) 1 */ +#define REG_TC3_RC1 (0x4005405C) /**< (TC3) Register C (channel = 0) 1 */ +#define REG_TC3_SR1 (0x40054060) /**< (TC3) Status Register (channel = 0) 1 */ +#define REG_TC3_IER1 (0x40054064) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC3_IDR1 (0x40054068) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC3_IMR1 (0x4005406C) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC3_EMR1 (0x40054070) /**< (TC3) Extended Mode Register (channel = 0) 1 */ +#define REG_TC3_CCR2 (0x40054080) /**< (TC3) Channel Control Register (channel = 0) 2 */ +#define REG_TC3_CMR2 (0x40054084) /**< (TC3) Channel Mode Register (channel = 0) 2 */ +#define REG_TC3_SMMR2 (0x40054088) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC3_RAB2 (0x4005408C) /**< (TC3) Register AB (channel = 0) 2 */ +#define REG_TC3_CV2 (0x40054090) /**< (TC3) Counter Value (channel = 0) 2 */ +#define REG_TC3_RA2 (0x40054094) /**< (TC3) Register A (channel = 0) 2 */ +#define REG_TC3_RB2 (0x40054098) /**< (TC3) Register B (channel = 0) 2 */ +#define REG_TC3_RC2 (0x4005409C) /**< (TC3) Register C (channel = 0) 2 */ +#define REG_TC3_SR2 (0x400540A0) /**< (TC3) Status Register (channel = 0) 2 */ +#define REG_TC3_IER2 (0x400540A4) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC3_IDR2 (0x400540A8) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC3_IMR2 (0x400540AC) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC3_EMR2 (0x400540B0) /**< (TC3) Extended Mode Register (channel = 0) 2 */ +#define REG_TC3_BCR (0x400540C0) /**< (TC3) Block Control Register */ +#define REG_TC3_BMR (0x400540C4) /**< (TC3) Block Mode Register */ +#define REG_TC3_QIER (0x400540C8) /**< (TC3) QDEC Interrupt Enable Register */ +#define REG_TC3_QIDR (0x400540CC) /**< (TC3) QDEC Interrupt Disable Register */ +#define REG_TC3_QIMR (0x400540D0) /**< (TC3) QDEC Interrupt Mask Register */ +#define REG_TC3_QISR (0x400540D4) /**< (TC3) QDEC Interrupt Status Register */ +#define REG_TC3_FMR (0x400540D8) /**< (TC3) Fault Mode Register */ +#define REG_TC3_WPMR (0x400540E4) /**< (TC3) Write Protection Mode Register */ + +#else + +#define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< (TC3) Channel Control Register (channel = 0) 0 */ +#define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< (TC3) Channel Mode Register (channel = 0) 0 */ +#define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */ +#define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< (TC3) Register AB (channel = 0) 0 */ +#define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< (TC3) Counter Value (channel = 0) 0 */ +#define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< (TC3) Register A (channel = 0) 0 */ +#define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< (TC3) Register B (channel = 0) 0 */ +#define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< (TC3) Register C (channel = 0) 0 */ +#define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< (TC3) Status Register (channel = 0) 0 */ +#define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */ +#define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */ +#define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */ +#define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< (TC3) Extended Mode Register (channel = 0) 0 */ +#define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< (TC3) Channel Control Register (channel = 0) 1 */ +#define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< (TC3) Channel Mode Register (channel = 0) 1 */ +#define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */ +#define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< (TC3) Register AB (channel = 0) 1 */ +#define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< (TC3) Counter Value (channel = 0) 1 */ +#define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< (TC3) Register A (channel = 0) 1 */ +#define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< (TC3) Register B (channel = 0) 1 */ +#define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< (TC3) Register C (channel = 0) 1 */ +#define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< (TC3) Status Register (channel = 0) 1 */ +#define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */ +#define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */ +#define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */ +#define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< (TC3) Extended Mode Register (channel = 0) 1 */ +#define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< (TC3) Channel Control Register (channel = 0) 2 */ +#define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< (TC3) Channel Mode Register (channel = 0) 2 */ +#define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */ +#define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< (TC3) Register AB (channel = 0) 2 */ +#define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< (TC3) Counter Value (channel = 0) 2 */ +#define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< (TC3) Register A (channel = 0) 2 */ +#define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< (TC3) Register B (channel = 0) 2 */ +#define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< (TC3) Register C (channel = 0) 2 */ +#define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< (TC3) Status Register (channel = 0) 2 */ +#define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */ +#define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */ +#define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */ +#define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< (TC3) Extended Mode Register (channel = 0) 2 */ +#define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< (TC3) Block Control Register */ +#define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< (TC3) Block Mode Register */ +#define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< (TC3) QDEC Interrupt Enable Register */ +#define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< (TC3) QDEC Interrupt Disable Register */ +#define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< (TC3) QDEC Interrupt Mask Register */ +#define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< (TC3) QDEC Interrupt Status Register */ +#define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< (TC3) Fault Mode Register */ +#define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< (TC3) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TC3 peripheral ========== */ +#define TC3_DMAC_ID_RX 43 +#define TC3_INSTANCE_ID_CHANNEL0 50 +#define TC3_INSTANCE_ID_CHANNEL1 51 +#define TC3_INSTANCE_ID_CHANNEL2 52 +#define TC3_CLOCK_ID_CHANNEL0 50 +#define TC3_CLOCK_ID_CHANNEL1 51 +#define TC3_CLOCK_ID_CHANNEL2 52 +#define TC3_TCCLKS_ 0 /* MCK */ +#define TC3_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */ +#define TC3_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ +#define TC3_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ +#define TC3_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ +#define TC3_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ +#define TC3_TCCLKS_XC0 6 /* XC0 */ +#define TC3_TCCLKS_XC1 7 /* XC1 */ +#define TC3_TCCLKS_XC2 8 /* XC2 */ +#define TC3_NUM_INTERRUPT_LINES 3 +#define TC3_TIMER_WIDTH 16 + +#endif /* _SAME70_TC3_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/trng.h b/bsp/microchip/same70/bsp/same70b/include/instance/trng.h new file mode 100644 index 0000000000..96485afb62 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/trng.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for TRNG + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TRNG_INSTANCE_H_ +#define _SAME70_TRNG_INSTANCE_H_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TRNG_CR (0x40070000) /**< (TRNG) Control Register */ +#define REG_TRNG_IER (0x40070010) /**< (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (0x40070014) /**< (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (0x40070018) /**< (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (0x4007001C) /**< (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (0x40070050) /**< (TRNG) Output Data Register */ + +#else + +#define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< (TRNG) Control Register */ +#define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< (TRNG) Output Data Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TRNG peripheral ========== */ +#define TRNG_INSTANCE_ID 57 +#define TRNG_CLOCK_ID 57 + +#endif /* _SAME70_TRNG_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/twihs0.h b/bsp/microchip/same70/bsp/same70b/include/instance/twihs0.h new file mode 100644 index 0000000000..5db2fb7105 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/twihs0.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Instance description for TWIHS0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TWIHS0_INSTANCE_H_ +#define _SAME70_TWIHS0_INSTANCE_H_ + +/* ========== Register definition for TWIHS0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TWIHS0_CR (0x40018000) /**< (TWIHS0) Control Register */ +#define REG_TWIHS0_MMR (0x40018004) /**< (TWIHS0) Master Mode Register */ +#define REG_TWIHS0_SMR (0x40018008) /**< (TWIHS0) Slave Mode Register */ +#define REG_TWIHS0_IADR (0x4001800C) /**< (TWIHS0) Internal Address Register */ +#define REG_TWIHS0_CWGR (0x40018010) /**< (TWIHS0) Clock Waveform Generator Register */ +#define REG_TWIHS0_SR (0x40018020) /**< (TWIHS0) Status Register */ +#define REG_TWIHS0_IER (0x40018024) /**< (TWIHS0) Interrupt Enable Register */ +#define REG_TWIHS0_IDR (0x40018028) /**< (TWIHS0) Interrupt Disable Register */ +#define REG_TWIHS0_IMR (0x4001802C) /**< (TWIHS0) Interrupt Mask Register */ +#define REG_TWIHS0_RHR (0x40018030) /**< (TWIHS0) Receive Holding Register */ +#define REG_TWIHS0_THR (0x40018034) /**< (TWIHS0) Transmit Holding Register */ +#define REG_TWIHS0_SMBTR (0x40018038) /**< (TWIHS0) SMBus Timing Register */ +#define REG_TWIHS0_FILTR (0x40018044) /**< (TWIHS0) Filter Register */ +#define REG_TWIHS0_SWMR (0x4001804C) /**< (TWIHS0) SleepWalking Matching Register */ +#define REG_TWIHS0_WPMR (0x400180E4) /**< (TWIHS0) Write Protection Mode Register */ +#define REG_TWIHS0_WPSR (0x400180E8) /**< (TWIHS0) Write Protection Status Register */ + +#else + +#define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< (TWIHS0) Control Register */ +#define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< (TWIHS0) Master Mode Register */ +#define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< (TWIHS0) Slave Mode Register */ +#define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< (TWIHS0) Internal Address Register */ +#define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< (TWIHS0) Clock Waveform Generator Register */ +#define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< (TWIHS0) Status Register */ +#define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< (TWIHS0) Interrupt Enable Register */ +#define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< (TWIHS0) Interrupt Disable Register */ +#define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< (TWIHS0) Interrupt Mask Register */ +#define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< (TWIHS0) Receive Holding Register */ +#define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< (TWIHS0) Transmit Holding Register */ +#define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< (TWIHS0) SMBus Timing Register */ +#define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< (TWIHS0) Filter Register */ +#define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< (TWIHS0) SleepWalking Matching Register */ +#define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< (TWIHS0) Write Protection Mode Register */ +#define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< (TWIHS0) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TWIHS0 peripheral ========== */ +#define TWIHS0_DMAC_ID_RX 15 +#define TWIHS0_DMAC_ID_TX 14 +#define TWIHS0_INSTANCE_ID 19 +#define TWIHS0_CLOCK_ID 19 + +#endif /* _SAME70_TWIHS0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/twihs1.h b/bsp/microchip/same70/bsp/same70b/include/instance/twihs1.h new file mode 100644 index 0000000000..7c0b88ccd8 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/twihs1.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Instance description for TWIHS1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TWIHS1_INSTANCE_H_ +#define _SAME70_TWIHS1_INSTANCE_H_ + +/* ========== Register definition for TWIHS1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TWIHS1_CR (0x4001C000) /**< (TWIHS1) Control Register */ +#define REG_TWIHS1_MMR (0x4001C004) /**< (TWIHS1) Master Mode Register */ +#define REG_TWIHS1_SMR (0x4001C008) /**< (TWIHS1) Slave Mode Register */ +#define REG_TWIHS1_IADR (0x4001C00C) /**< (TWIHS1) Internal Address Register */ +#define REG_TWIHS1_CWGR (0x4001C010) /**< (TWIHS1) Clock Waveform Generator Register */ +#define REG_TWIHS1_SR (0x4001C020) /**< (TWIHS1) Status Register */ +#define REG_TWIHS1_IER (0x4001C024) /**< (TWIHS1) Interrupt Enable Register */ +#define REG_TWIHS1_IDR (0x4001C028) /**< (TWIHS1) Interrupt Disable Register */ +#define REG_TWIHS1_IMR (0x4001C02C) /**< (TWIHS1) Interrupt Mask Register */ +#define REG_TWIHS1_RHR (0x4001C030) /**< (TWIHS1) Receive Holding Register */ +#define REG_TWIHS1_THR (0x4001C034) /**< (TWIHS1) Transmit Holding Register */ +#define REG_TWIHS1_SMBTR (0x4001C038) /**< (TWIHS1) SMBus Timing Register */ +#define REG_TWIHS1_FILTR (0x4001C044) /**< (TWIHS1) Filter Register */ +#define REG_TWIHS1_SWMR (0x4001C04C) /**< (TWIHS1) SleepWalking Matching Register */ +#define REG_TWIHS1_WPMR (0x4001C0E4) /**< (TWIHS1) Write Protection Mode Register */ +#define REG_TWIHS1_WPSR (0x4001C0E8) /**< (TWIHS1) Write Protection Status Register */ + +#else + +#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< (TWIHS1) Control Register */ +#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< (TWIHS1) Master Mode Register */ +#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< (TWIHS1) Slave Mode Register */ +#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< (TWIHS1) Internal Address Register */ +#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< (TWIHS1) Clock Waveform Generator Register */ +#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< (TWIHS1) Status Register */ +#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< (TWIHS1) Interrupt Enable Register */ +#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< (TWIHS1) Interrupt Disable Register */ +#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< (TWIHS1) Interrupt Mask Register */ +#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< (TWIHS1) Receive Holding Register */ +#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< (TWIHS1) Transmit Holding Register */ +#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< (TWIHS1) SMBus Timing Register */ +#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< (TWIHS1) Filter Register */ +#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< (TWIHS1) SleepWalking Matching Register */ +#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< (TWIHS1) Write Protection Mode Register */ +#define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< (TWIHS1) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TWIHS1 peripheral ========== */ +#define TWIHS1_DMAC_ID_RX 17 +#define TWIHS1_DMAC_ID_TX 16 +#define TWIHS1_INSTANCE_ID 20 +#define TWIHS1_CLOCK_ID 20 + +#endif /* _SAME70_TWIHS1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/twihs2.h b/bsp/microchip/same70/bsp/same70b/include/instance/twihs2.h new file mode 100644 index 0000000000..a72c860c97 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/twihs2.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief Instance description for TWIHS2 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_TWIHS2_INSTANCE_H_ +#define _SAME70_TWIHS2_INSTANCE_H_ + +/* ========== Register definition for TWIHS2 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_TWIHS2_CR (0x40060000) /**< (TWIHS2) Control Register */ +#define REG_TWIHS2_MMR (0x40060004) /**< (TWIHS2) Master Mode Register */ +#define REG_TWIHS2_SMR (0x40060008) /**< (TWIHS2) Slave Mode Register */ +#define REG_TWIHS2_IADR (0x4006000C) /**< (TWIHS2) Internal Address Register */ +#define REG_TWIHS2_CWGR (0x40060010) /**< (TWIHS2) Clock Waveform Generator Register */ +#define REG_TWIHS2_SR (0x40060020) /**< (TWIHS2) Status Register */ +#define REG_TWIHS2_IER (0x40060024) /**< (TWIHS2) Interrupt Enable Register */ +#define REG_TWIHS2_IDR (0x40060028) /**< (TWIHS2) Interrupt Disable Register */ +#define REG_TWIHS2_IMR (0x4006002C) /**< (TWIHS2) Interrupt Mask Register */ +#define REG_TWIHS2_RHR (0x40060030) /**< (TWIHS2) Receive Holding Register */ +#define REG_TWIHS2_THR (0x40060034) /**< (TWIHS2) Transmit Holding Register */ +#define REG_TWIHS2_SMBTR (0x40060038) /**< (TWIHS2) SMBus Timing Register */ +#define REG_TWIHS2_FILTR (0x40060044) /**< (TWIHS2) Filter Register */ +#define REG_TWIHS2_SWMR (0x4006004C) /**< (TWIHS2) SleepWalking Matching Register */ +#define REG_TWIHS2_WPMR (0x400600E4) /**< (TWIHS2) Write Protection Mode Register */ +#define REG_TWIHS2_WPSR (0x400600E8) /**< (TWIHS2) Write Protection Status Register */ + +#else + +#define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< (TWIHS2) Control Register */ +#define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< (TWIHS2) Master Mode Register */ +#define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< (TWIHS2) Slave Mode Register */ +#define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< (TWIHS2) Internal Address Register */ +#define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< (TWIHS2) Clock Waveform Generator Register */ +#define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< (TWIHS2) Status Register */ +#define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< (TWIHS2) Interrupt Enable Register */ +#define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< (TWIHS2) Interrupt Disable Register */ +#define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< (TWIHS2) Interrupt Mask Register */ +#define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< (TWIHS2) Receive Holding Register */ +#define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< (TWIHS2) Transmit Holding Register */ +#define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< (TWIHS2) SMBus Timing Register */ +#define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< (TWIHS2) Filter Register */ +#define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< (TWIHS2) SleepWalking Matching Register */ +#define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< (TWIHS2) Write Protection Mode Register */ +#define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< (TWIHS2) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for TWIHS2 peripheral ========== */ +#define TWIHS2_DMAC_ID_RX 19 +#define TWIHS2_DMAC_ID_TX 18 +#define TWIHS2_INSTANCE_ID 41 +#define TWIHS2_CLOCK_ID 41 + +#endif /* _SAME70_TWIHS2_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/uart0.h b/bsp/microchip/same70/bsp/same70b/include/instance/uart0.h new file mode 100644 index 0000000000..62ac12f6de --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/uart0.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for UART0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART0_INSTANCE_H_ +#define _SAME70_UART0_INSTANCE_H_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UART0_CR (0x400E0800) /**< (UART0) Control Register */ +#define REG_UART0_MR (0x400E0804) /**< (UART0) Mode Register */ +#define REG_UART0_IER (0x400E0808) /**< (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (0x400E080C) /**< (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (0x400E0810) /**< (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (0x400E0814) /**< (UART0) Status Register */ +#define REG_UART0_RHR (0x400E0818) /**< (UART0) Receive Holding Register */ +#define REG_UART0_THR (0x400E081C) /**< (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (0x400E0820) /**< (UART0) Baud Rate Generator Register */ +#define REG_UART0_CMPR (0x400E0824) /**< (UART0) Comparison Register */ +#define REG_UART0_WPMR (0x400E08E4) /**< (UART0) Write Protection Mode Register */ + +#else + +#define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */ +#define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< (UART0) Mode Register */ +#define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< (UART0) Status Register */ +#define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< (UART0) Receive Holding Register */ +#define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< (UART0) Baud Rate Generator Register */ +#define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< (UART0) Comparison Register */ +#define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< (UART0) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for UART0 peripheral ========== */ +#define UART0_DMAC_ID_RX 21 +#define UART0_DMAC_ID_TX 20 +#define UART0_INSTANCE_ID 7 +#define UART0_CLOCK_ID 7 +#define UART0_BRSRCCK_PERIPH_CLK 0 /* MCK */ +#define UART0_BRSRCCK_PMC_PCK 0 /* PCK4 */ + +#endif /* _SAME70_UART0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/uart1.h b/bsp/microchip/same70/bsp/same70b/include/instance/uart1.h new file mode 100644 index 0000000000..7e373dda51 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/uart1.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for UART1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART1_INSTANCE_H_ +#define _SAME70_UART1_INSTANCE_H_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UART1_CR (0x400E0A00) /**< (UART1) Control Register */ +#define REG_UART1_MR (0x400E0A04) /**< (UART1) Mode Register */ +#define REG_UART1_IER (0x400E0A08) /**< (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (0x400E0A0C) /**< (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (0x400E0A10) /**< (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (0x400E0A14) /**< (UART1) Status Register */ +#define REG_UART1_RHR (0x400E0A18) /**< (UART1) Receive Holding Register */ +#define REG_UART1_THR (0x400E0A1C) /**< (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (0x400E0A20) /**< (UART1) Baud Rate Generator Register */ +#define REG_UART1_CMPR (0x400E0A24) /**< (UART1) Comparison Register */ +#define REG_UART1_WPMR (0x400E0AE4) /**< (UART1) Write Protection Mode Register */ + +#else + +#define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */ +#define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< (UART1) Mode Register */ +#define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< (UART1) Status Register */ +#define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< (UART1) Receive Holding Register */ +#define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< (UART1) Baud Rate Generator Register */ +#define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< (UART1) Comparison Register */ +#define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< (UART1) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for UART1 peripheral ========== */ +#define UART1_DMAC_ID_RX 23 +#define UART1_DMAC_ID_TX 22 +#define UART1_INSTANCE_ID 8 +#define UART1_CLOCK_ID 8 +#define UART1_BRSRCCK_PERIPH_CLK 0 /* MCK */ +#define UART1_BRSRCCK_PMC_PCK 0 /* PCK4 */ + +#endif /* _SAME70_UART1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/uart2.h b/bsp/microchip/same70/bsp/same70b/include/instance/uart2.h new file mode 100644 index 0000000000..34f0a40be6 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/uart2.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for UART2 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART2_INSTANCE_H_ +#define _SAME70_UART2_INSTANCE_H_ + +/* ========== Register definition for UART2 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UART2_CR (0x400E1A00) /**< (UART2) Control Register */ +#define REG_UART2_MR (0x400E1A04) /**< (UART2) Mode Register */ +#define REG_UART2_IER (0x400E1A08) /**< (UART2) Interrupt Enable Register */ +#define REG_UART2_IDR (0x400E1A0C) /**< (UART2) Interrupt Disable Register */ +#define REG_UART2_IMR (0x400E1A10) /**< (UART2) Interrupt Mask Register */ +#define REG_UART2_SR (0x400E1A14) /**< (UART2) Status Register */ +#define REG_UART2_RHR (0x400E1A18) /**< (UART2) Receive Holding Register */ +#define REG_UART2_THR (0x400E1A1C) /**< (UART2) Transmit Holding Register */ +#define REG_UART2_BRGR (0x400E1A20) /**< (UART2) Baud Rate Generator Register */ +#define REG_UART2_CMPR (0x400E1A24) /**< (UART2) Comparison Register */ +#define REG_UART2_WPMR (0x400E1AE4) /**< (UART2) Write Protection Mode Register */ + +#else + +#define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< (UART2) Control Register */ +#define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< (UART2) Mode Register */ +#define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< (UART2) Interrupt Enable Register */ +#define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< (UART2) Interrupt Disable Register */ +#define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< (UART2) Interrupt Mask Register */ +#define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< (UART2) Status Register */ +#define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< (UART2) Receive Holding Register */ +#define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< (UART2) Transmit Holding Register */ +#define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< (UART2) Baud Rate Generator Register */ +#define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< (UART2) Comparison Register */ +#define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< (UART2) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for UART2 peripheral ========== */ +#define UART2_DMAC_ID_RX 25 +#define UART2_DMAC_ID_TX 24 +#define UART2_INSTANCE_ID 44 +#define UART2_CLOCK_ID 44 +#define UART2_BRSRCCK_PERIPH_CLK 0 /* MCK */ +#define UART2_BRSRCCK_PMC_PCK 0 /* PCK4 */ + +#endif /* _SAME70_UART2_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/uart3.h b/bsp/microchip/same70/bsp/same70b/include/instance/uart3.h new file mode 100644 index 0000000000..827c0f9b45 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/uart3.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for UART3 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART3_INSTANCE_H_ +#define _SAME70_UART3_INSTANCE_H_ + +/* ========== Register definition for UART3 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UART3_CR (0x400E1C00) /**< (UART3) Control Register */ +#define REG_UART3_MR (0x400E1C04) /**< (UART3) Mode Register */ +#define REG_UART3_IER (0x400E1C08) /**< (UART3) Interrupt Enable Register */ +#define REG_UART3_IDR (0x400E1C0C) /**< (UART3) Interrupt Disable Register */ +#define REG_UART3_IMR (0x400E1C10) /**< (UART3) Interrupt Mask Register */ +#define REG_UART3_SR (0x400E1C14) /**< (UART3) Status Register */ +#define REG_UART3_RHR (0x400E1C18) /**< (UART3) Receive Holding Register */ +#define REG_UART3_THR (0x400E1C1C) /**< (UART3) Transmit Holding Register */ +#define REG_UART3_BRGR (0x400E1C20) /**< (UART3) Baud Rate Generator Register */ +#define REG_UART3_CMPR (0x400E1C24) /**< (UART3) Comparison Register */ +#define REG_UART3_WPMR (0x400E1CE4) /**< (UART3) Write Protection Mode Register */ + +#else + +#define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< (UART3) Control Register */ +#define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< (UART3) Mode Register */ +#define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< (UART3) Interrupt Enable Register */ +#define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< (UART3) Interrupt Disable Register */ +#define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< (UART3) Interrupt Mask Register */ +#define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< (UART3) Status Register */ +#define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< (UART3) Receive Holding Register */ +#define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< (UART3) Transmit Holding Register */ +#define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< (UART3) Baud Rate Generator Register */ +#define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< (UART3) Comparison Register */ +#define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< (UART3) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for UART3 peripheral ========== */ +#define UART3_DMAC_ID_RX 27 +#define UART3_DMAC_ID_TX 26 +#define UART3_INSTANCE_ID 45 +#define UART3_CLOCK_ID 45 +#define UART3_BRSRCCK_PERIPH_CLK 0 /* MCK */ +#define UART3_BRSRCCK_PMC_PCK 0 /* PCK4 */ + +#endif /* _SAME70_UART3_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/uart4.h b/bsp/microchip/same70/bsp/same70b/include/instance/uart4.h new file mode 100644 index 0000000000..ad3e302970 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/uart4.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Instance description for UART4 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UART4_INSTANCE_H_ +#define _SAME70_UART4_INSTANCE_H_ + +/* ========== Register definition for UART4 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UART4_CR (0x400E1E00) /**< (UART4) Control Register */ +#define REG_UART4_MR (0x400E1E04) /**< (UART4) Mode Register */ +#define REG_UART4_IER (0x400E1E08) /**< (UART4) Interrupt Enable Register */ +#define REG_UART4_IDR (0x400E1E0C) /**< (UART4) Interrupt Disable Register */ +#define REG_UART4_IMR (0x400E1E10) /**< (UART4) Interrupt Mask Register */ +#define REG_UART4_SR (0x400E1E14) /**< (UART4) Status Register */ +#define REG_UART4_RHR (0x400E1E18) /**< (UART4) Receive Holding Register */ +#define REG_UART4_THR (0x400E1E1C) /**< (UART4) Transmit Holding Register */ +#define REG_UART4_BRGR (0x400E1E20) /**< (UART4) Baud Rate Generator Register */ +#define REG_UART4_CMPR (0x400E1E24) /**< (UART4) Comparison Register */ +#define REG_UART4_WPMR (0x400E1EE4) /**< (UART4) Write Protection Mode Register */ + +#else + +#define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< (UART4) Control Register */ +#define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< (UART4) Mode Register */ +#define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< (UART4) Interrupt Enable Register */ +#define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< (UART4) Interrupt Disable Register */ +#define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< (UART4) Interrupt Mask Register */ +#define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< (UART4) Status Register */ +#define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< (UART4) Receive Holding Register */ +#define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< (UART4) Transmit Holding Register */ +#define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< (UART4) Baud Rate Generator Register */ +#define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< (UART4) Comparison Register */ +#define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< (UART4) Write Protection Mode Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for UART4 peripheral ========== */ +#define UART4_DMAC_ID_RX 29 +#define UART4_DMAC_ID_TX 28 +#define UART4_INSTANCE_ID 46 +#define UART4_CLOCK_ID 46 +#define UART4_BRSRCCK_PERIPH_CLK 0 /* MCK */ +#define UART4_BRSRCCK_PMC_PCK 0 /* PCK4 */ + +#endif /* _SAME70_UART4_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/usart0.h b/bsp/microchip/same70/bsp/same70b/include/instance/usart0.h new file mode 100644 index 0000000000..348be0477f --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/usart0.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Instance description for USART0 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USART0_INSTANCE_H_ +#define _SAME70_USART0_INSTANCE_H_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_USART0_US_CR (0x40024000) /**< (USART0) Control Register */ +#define REG_USART0_US_MR (0x40024004) /**< (USART0) Mode Register */ +#define REG_USART0_US_IER (0x40024008) /**< (USART0) Interrupt Enable Register */ +#define REG_USART0_US_IDR (0x4002400C) /**< (USART0) Interrupt Disable Register */ +#define REG_USART0_US_IMR (0x40024010) /**< (USART0) Interrupt Mask Register */ +#define REG_USART0_US_CSR (0x40024014) /**< (USART0) Channel Status Register */ +#define REG_USART0_US_RHR (0x40024018) /**< (USART0) Receive Holding Register */ +#define REG_USART0_US_THR (0x4002401C) /**< (USART0) Transmit Holding Register */ +#define REG_USART0_US_BRGR (0x40024020) /**< (USART0) Baud Rate Generator Register */ +#define REG_USART0_US_RTOR (0x40024024) /**< (USART0) Receiver Timeout Register */ +#define REG_USART0_US_TTGR (0x40024028) /**< (USART0) Transmitter Timeguard Register */ +#define REG_USART0_US_FIDI (0x40024040) /**< (USART0) FI DI Ratio Register */ +#define REG_USART0_US_NER (0x40024044) /**< (USART0) Number of Errors Register */ +#define REG_USART0_US_IF (0x4002404C) /**< (USART0) IrDA Filter Register */ +#define REG_USART0_US_MAN (0x40024050) /**< (USART0) Manchester Configuration Register */ +#define REG_USART0_US_LINMR (0x40024054) /**< (USART0) LIN Mode Register */ +#define REG_USART0_US_LINIR (0x40024058) /**< (USART0) LIN Identifier Register */ +#define REG_USART0_US_LINBRR (0x4002405C) /**< (USART0) LIN Baud Rate Register */ +#define REG_USART0_US_LONMR (0x40024060) /**< (USART0) LON Mode Register */ +#define REG_USART0_US_LONPR (0x40024064) /**< (USART0) LON Preamble Register */ +#define REG_USART0_US_LONDL (0x40024068) /**< (USART0) LON Data Length Register */ +#define REG_USART0_US_LONL2HDR (0x4002406C) /**< (USART0) LON L2HDR Register */ +#define REG_USART0_US_LONBL (0x40024070) /**< (USART0) LON Backlog Register */ +#define REG_USART0_US_LONB1TX (0x40024074) /**< (USART0) LON Beta1 Tx Register */ +#define REG_USART0_US_LONB1RX (0x40024078) /**< (USART0) LON Beta1 Rx Register */ +#define REG_USART0_US_LONPRIO (0x4002407C) /**< (USART0) LON Priority Register */ +#define REG_USART0_US_IDTTX (0x40024080) /**< (USART0) LON IDT Tx Register */ +#define REG_USART0_US_IDTRX (0x40024084) /**< (USART0) LON IDT Rx Register */ +#define REG_USART0_US_ICDIFF (0x40024088) /**< (USART0) IC DIFF Register */ +#define REG_USART0_US_WPMR (0x400240E4) /**< (USART0) Write Protection Mode Register */ +#define REG_USART0_US_WPSR (0x400240E8) /**< (USART0) Write Protection Status Register */ + +#else + +#define REG_USART0_US_CR (*(__O uint32_t*)0x40024000U) /**< (USART0) Control Register */ +#define REG_USART0_US_MR (*(__IO uint32_t*)0x40024004U) /**< (USART0) Mode Register */ +#define REG_USART0_US_IER (*(__O uint32_t*)0x40024008U) /**< (USART0) Interrupt Enable Register */ +#define REG_USART0_US_IDR (*(__O uint32_t*)0x4002400CU) /**< (USART0) Interrupt Disable Register */ +#define REG_USART0_US_IMR (*(__I uint32_t*)0x40024010U) /**< (USART0) Interrupt Mask Register */ +#define REG_USART0_US_CSR (*(__I uint32_t*)0x40024014U) /**< (USART0) Channel Status Register */ +#define REG_USART0_US_RHR (*(__I uint32_t*)0x40024018U) /**< (USART0) Receive Holding Register */ +#define REG_USART0_US_THR (*(__O uint32_t*)0x4002401CU) /**< (USART0) Transmit Holding Register */ +#define REG_USART0_US_BRGR (*(__IO uint32_t*)0x40024020U) /**< (USART0) Baud Rate Generator Register */ +#define REG_USART0_US_RTOR (*(__IO uint32_t*)0x40024024U) /**< (USART0) Receiver Timeout Register */ +#define REG_USART0_US_TTGR (*(__IO uint32_t*)0x40024028U) /**< (USART0) Transmitter Timeguard Register */ +#define REG_USART0_US_FIDI (*(__IO uint32_t*)0x40024040U) /**< (USART0) FI DI Ratio Register */ +#define REG_USART0_US_NER (*(__I uint32_t*)0x40024044U) /**< (USART0) Number of Errors Register */ +#define REG_USART0_US_IF (*(__IO uint32_t*)0x4002404CU) /**< (USART0) IrDA Filter Register */ +#define REG_USART0_US_MAN (*(__IO uint32_t*)0x40024050U) /**< (USART0) Manchester Configuration Register */ +#define REG_USART0_US_LINMR (*(__IO uint32_t*)0x40024054U) /**< (USART0) LIN Mode Register */ +#define REG_USART0_US_LINIR (*(__IO uint32_t*)0x40024058U) /**< (USART0) LIN Identifier Register */ +#define REG_USART0_US_LINBRR (*(__I uint32_t*)0x4002405CU) /**< (USART0) LIN Baud Rate Register */ +#define REG_USART0_US_LONMR (*(__IO uint32_t*)0x40024060U) /**< (USART0) LON Mode Register */ +#define REG_USART0_US_LONPR (*(__IO uint32_t*)0x40024064U) /**< (USART0) LON Preamble Register */ +#define REG_USART0_US_LONDL (*(__IO uint32_t*)0x40024068U) /**< (USART0) LON Data Length Register */ +#define REG_USART0_US_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< (USART0) LON L2HDR Register */ +#define REG_USART0_US_LONBL (*(__I uint32_t*)0x40024070U) /**< (USART0) LON Backlog Register */ +#define REG_USART0_US_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< (USART0) LON Beta1 Tx Register */ +#define REG_USART0_US_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< (USART0) LON Beta1 Rx Register */ +#define REG_USART0_US_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< (USART0) LON Priority Register */ +#define REG_USART0_US_IDTTX (*(__IO uint32_t*)0x40024080U) /**< (USART0) LON IDT Tx Register */ +#define REG_USART0_US_IDTRX (*(__IO uint32_t*)0x40024084U) /**< (USART0) LON IDT Rx Register */ +#define REG_USART0_US_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< (USART0) IC DIFF Register */ +#define REG_USART0_US_WPMR (*(__IO uint32_t*)0x400240E4U) /**< (USART0) Write Protection Mode Register */ +#define REG_USART0_US_WPSR (*(__I uint32_t*)0x400240E8U) /**< (USART0) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for USART0 peripheral ========== */ +#define USART0_DMAC_ID_RX 8 +#define USART0_DMAC_ID_TX 7 +#define USART0_INSTANCE_ID 13 +#define USART0_CLOCK_ID 13 +#define USART0_USCLKS_MCK 0 /* MCK */ +#define USART0_USCLKS_DIV 1 /* MCK/8 */ +#define USART0_USCLKS_PCK 2 /* PCK4 */ +#define USART0_USCLKS_SCK 3 /* SCK */ + +#endif /* _SAME70_USART0_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/usart1.h b/bsp/microchip/same70/bsp/same70b/include/instance/usart1.h new file mode 100644 index 0000000000..9d3d49d360 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/usart1.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Instance description for USART1 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USART1_INSTANCE_H_ +#define _SAME70_USART1_INSTANCE_H_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_USART1_US_CR (0x40028000) /**< (USART1) Control Register */ +#define REG_USART1_US_MR (0x40028004) /**< (USART1) Mode Register */ +#define REG_USART1_US_IER (0x40028008) /**< (USART1) Interrupt Enable Register */ +#define REG_USART1_US_IDR (0x4002800C) /**< (USART1) Interrupt Disable Register */ +#define REG_USART1_US_IMR (0x40028010) /**< (USART1) Interrupt Mask Register */ +#define REG_USART1_US_CSR (0x40028014) /**< (USART1) Channel Status Register */ +#define REG_USART1_US_RHR (0x40028018) /**< (USART1) Receive Holding Register */ +#define REG_USART1_US_THR (0x4002801C) /**< (USART1) Transmit Holding Register */ +#define REG_USART1_US_BRGR (0x40028020) /**< (USART1) Baud Rate Generator Register */ +#define REG_USART1_US_RTOR (0x40028024) /**< (USART1) Receiver Timeout Register */ +#define REG_USART1_US_TTGR (0x40028028) /**< (USART1) Transmitter Timeguard Register */ +#define REG_USART1_US_FIDI (0x40028040) /**< (USART1) FI DI Ratio Register */ +#define REG_USART1_US_NER (0x40028044) /**< (USART1) Number of Errors Register */ +#define REG_USART1_US_IF (0x4002804C) /**< (USART1) IrDA Filter Register */ +#define REG_USART1_US_MAN (0x40028050) /**< (USART1) Manchester Configuration Register */ +#define REG_USART1_US_LINMR (0x40028054) /**< (USART1) LIN Mode Register */ +#define REG_USART1_US_LINIR (0x40028058) /**< (USART1) LIN Identifier Register */ +#define REG_USART1_US_LINBRR (0x4002805C) /**< (USART1) LIN Baud Rate Register */ +#define REG_USART1_US_LONMR (0x40028060) /**< (USART1) LON Mode Register */ +#define REG_USART1_US_LONPR (0x40028064) /**< (USART1) LON Preamble Register */ +#define REG_USART1_US_LONDL (0x40028068) /**< (USART1) LON Data Length Register */ +#define REG_USART1_US_LONL2HDR (0x4002806C) /**< (USART1) LON L2HDR Register */ +#define REG_USART1_US_LONBL (0x40028070) /**< (USART1) LON Backlog Register */ +#define REG_USART1_US_LONB1TX (0x40028074) /**< (USART1) LON Beta1 Tx Register */ +#define REG_USART1_US_LONB1RX (0x40028078) /**< (USART1) LON Beta1 Rx Register */ +#define REG_USART1_US_LONPRIO (0x4002807C) /**< (USART1) LON Priority Register */ +#define REG_USART1_US_IDTTX (0x40028080) /**< (USART1) LON IDT Tx Register */ +#define REG_USART1_US_IDTRX (0x40028084) /**< (USART1) LON IDT Rx Register */ +#define REG_USART1_US_ICDIFF (0x40028088) /**< (USART1) IC DIFF Register */ +#define REG_USART1_US_WPMR (0x400280E4) /**< (USART1) Write Protection Mode Register */ +#define REG_USART1_US_WPSR (0x400280E8) /**< (USART1) Write Protection Status Register */ + +#else + +#define REG_USART1_US_CR (*(__O uint32_t*)0x40028000U) /**< (USART1) Control Register */ +#define REG_USART1_US_MR (*(__IO uint32_t*)0x40028004U) /**< (USART1) Mode Register */ +#define REG_USART1_US_IER (*(__O uint32_t*)0x40028008U) /**< (USART1) Interrupt Enable Register */ +#define REG_USART1_US_IDR (*(__O uint32_t*)0x4002800CU) /**< (USART1) Interrupt Disable Register */ +#define REG_USART1_US_IMR (*(__I uint32_t*)0x40028010U) /**< (USART1) Interrupt Mask Register */ +#define REG_USART1_US_CSR (*(__I uint32_t*)0x40028014U) /**< (USART1) Channel Status Register */ +#define REG_USART1_US_RHR (*(__I uint32_t*)0x40028018U) /**< (USART1) Receive Holding Register */ +#define REG_USART1_US_THR (*(__O uint32_t*)0x4002801CU) /**< (USART1) Transmit Holding Register */ +#define REG_USART1_US_BRGR (*(__IO uint32_t*)0x40028020U) /**< (USART1) Baud Rate Generator Register */ +#define REG_USART1_US_RTOR (*(__IO uint32_t*)0x40028024U) /**< (USART1) Receiver Timeout Register */ +#define REG_USART1_US_TTGR (*(__IO uint32_t*)0x40028028U) /**< (USART1) Transmitter Timeguard Register */ +#define REG_USART1_US_FIDI (*(__IO uint32_t*)0x40028040U) /**< (USART1) FI DI Ratio Register */ +#define REG_USART1_US_NER (*(__I uint32_t*)0x40028044U) /**< (USART1) Number of Errors Register */ +#define REG_USART1_US_IF (*(__IO uint32_t*)0x4002804CU) /**< (USART1) IrDA Filter Register */ +#define REG_USART1_US_MAN (*(__IO uint32_t*)0x40028050U) /**< (USART1) Manchester Configuration Register */ +#define REG_USART1_US_LINMR (*(__IO uint32_t*)0x40028054U) /**< (USART1) LIN Mode Register */ +#define REG_USART1_US_LINIR (*(__IO uint32_t*)0x40028058U) /**< (USART1) LIN Identifier Register */ +#define REG_USART1_US_LINBRR (*(__I uint32_t*)0x4002805CU) /**< (USART1) LIN Baud Rate Register */ +#define REG_USART1_US_LONMR (*(__IO uint32_t*)0x40028060U) /**< (USART1) LON Mode Register */ +#define REG_USART1_US_LONPR (*(__IO uint32_t*)0x40028064U) /**< (USART1) LON Preamble Register */ +#define REG_USART1_US_LONDL (*(__IO uint32_t*)0x40028068U) /**< (USART1) LON Data Length Register */ +#define REG_USART1_US_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< (USART1) LON L2HDR Register */ +#define REG_USART1_US_LONBL (*(__I uint32_t*)0x40028070U) /**< (USART1) LON Backlog Register */ +#define REG_USART1_US_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< (USART1) LON Beta1 Tx Register */ +#define REG_USART1_US_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< (USART1) LON Beta1 Rx Register */ +#define REG_USART1_US_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< (USART1) LON Priority Register */ +#define REG_USART1_US_IDTTX (*(__IO uint32_t*)0x40028080U) /**< (USART1) LON IDT Tx Register */ +#define REG_USART1_US_IDTRX (*(__IO uint32_t*)0x40028084U) /**< (USART1) LON IDT Rx Register */ +#define REG_USART1_US_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< (USART1) IC DIFF Register */ +#define REG_USART1_US_WPMR (*(__IO uint32_t*)0x400280E4U) /**< (USART1) Write Protection Mode Register */ +#define REG_USART1_US_WPSR (*(__I uint32_t*)0x400280E8U) /**< (USART1) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for USART1 peripheral ========== */ +#define USART1_DMAC_ID_RX 10 +#define USART1_DMAC_ID_TX 9 +#define USART1_INSTANCE_ID 14 +#define USART1_CLOCK_ID 14 +#define USART1_USCLKS_MCK 0 /* MCK */ +#define USART1_USCLKS_DIV 1 /* MCK/8 */ +#define USART1_USCLKS_PCK 2 /* PCK4 */ +#define USART1_USCLKS_SCK 3 /* SCK */ + +#endif /* _SAME70_USART1_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/usart2.h b/bsp/microchip/same70/bsp/same70b/include/instance/usart2.h new file mode 100644 index 0000000000..d4ed9f453d --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/usart2.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Instance description for USART2 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USART2_INSTANCE_H_ +#define _SAME70_USART2_INSTANCE_H_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_USART2_US_CR (0x4002C000) /**< (USART2) Control Register */ +#define REG_USART2_US_MR (0x4002C004) /**< (USART2) Mode Register */ +#define REG_USART2_US_IER (0x4002C008) /**< (USART2) Interrupt Enable Register */ +#define REG_USART2_US_IDR (0x4002C00C) /**< (USART2) Interrupt Disable Register */ +#define REG_USART2_US_IMR (0x4002C010) /**< (USART2) Interrupt Mask Register */ +#define REG_USART2_US_CSR (0x4002C014) /**< (USART2) Channel Status Register */ +#define REG_USART2_US_RHR (0x4002C018) /**< (USART2) Receive Holding Register */ +#define REG_USART2_US_THR (0x4002C01C) /**< (USART2) Transmit Holding Register */ +#define REG_USART2_US_BRGR (0x4002C020) /**< (USART2) Baud Rate Generator Register */ +#define REG_USART2_US_RTOR (0x4002C024) /**< (USART2) Receiver Timeout Register */ +#define REG_USART2_US_TTGR (0x4002C028) /**< (USART2) Transmitter Timeguard Register */ +#define REG_USART2_US_FIDI (0x4002C040) /**< (USART2) FI DI Ratio Register */ +#define REG_USART2_US_NER (0x4002C044) /**< (USART2) Number of Errors Register */ +#define REG_USART2_US_IF (0x4002C04C) /**< (USART2) IrDA Filter Register */ +#define REG_USART2_US_MAN (0x4002C050) /**< (USART2) Manchester Configuration Register */ +#define REG_USART2_US_LINMR (0x4002C054) /**< (USART2) LIN Mode Register */ +#define REG_USART2_US_LINIR (0x4002C058) /**< (USART2) LIN Identifier Register */ +#define REG_USART2_US_LINBRR (0x4002C05C) /**< (USART2) LIN Baud Rate Register */ +#define REG_USART2_US_LONMR (0x4002C060) /**< (USART2) LON Mode Register */ +#define REG_USART2_US_LONPR (0x4002C064) /**< (USART2) LON Preamble Register */ +#define REG_USART2_US_LONDL (0x4002C068) /**< (USART2) LON Data Length Register */ +#define REG_USART2_US_LONL2HDR (0x4002C06C) /**< (USART2) LON L2HDR Register */ +#define REG_USART2_US_LONBL (0x4002C070) /**< (USART2) LON Backlog Register */ +#define REG_USART2_US_LONB1TX (0x4002C074) /**< (USART2) LON Beta1 Tx Register */ +#define REG_USART2_US_LONB1RX (0x4002C078) /**< (USART2) LON Beta1 Rx Register */ +#define REG_USART2_US_LONPRIO (0x4002C07C) /**< (USART2) LON Priority Register */ +#define REG_USART2_US_IDTTX (0x4002C080) /**< (USART2) LON IDT Tx Register */ +#define REG_USART2_US_IDTRX (0x4002C084) /**< (USART2) LON IDT Rx Register */ +#define REG_USART2_US_ICDIFF (0x4002C088) /**< (USART2) IC DIFF Register */ +#define REG_USART2_US_WPMR (0x4002C0E4) /**< (USART2) Write Protection Mode Register */ +#define REG_USART2_US_WPSR (0x4002C0E8) /**< (USART2) Write Protection Status Register */ + +#else + +#define REG_USART2_US_CR (*(__O uint32_t*)0x4002C000U) /**< (USART2) Control Register */ +#define REG_USART2_US_MR (*(__IO uint32_t*)0x4002C004U) /**< (USART2) Mode Register */ +#define REG_USART2_US_IER (*(__O uint32_t*)0x4002C008U) /**< (USART2) Interrupt Enable Register */ +#define REG_USART2_US_IDR (*(__O uint32_t*)0x4002C00CU) /**< (USART2) Interrupt Disable Register */ +#define REG_USART2_US_IMR (*(__I uint32_t*)0x4002C010U) /**< (USART2) Interrupt Mask Register */ +#define REG_USART2_US_CSR (*(__I uint32_t*)0x4002C014U) /**< (USART2) Channel Status Register */ +#define REG_USART2_US_RHR (*(__I uint32_t*)0x4002C018U) /**< (USART2) Receive Holding Register */ +#define REG_USART2_US_THR (*(__O uint32_t*)0x4002C01CU) /**< (USART2) Transmit Holding Register */ +#define REG_USART2_US_BRGR (*(__IO uint32_t*)0x4002C020U) /**< (USART2) Baud Rate Generator Register */ +#define REG_USART2_US_RTOR (*(__IO uint32_t*)0x4002C024U) /**< (USART2) Receiver Timeout Register */ +#define REG_USART2_US_TTGR (*(__IO uint32_t*)0x4002C028U) /**< (USART2) Transmitter Timeguard Register */ +#define REG_USART2_US_FIDI (*(__IO uint32_t*)0x4002C040U) /**< (USART2) FI DI Ratio Register */ +#define REG_USART2_US_NER (*(__I uint32_t*)0x4002C044U) /**< (USART2) Number of Errors Register */ +#define REG_USART2_US_IF (*(__IO uint32_t*)0x4002C04CU) /**< (USART2) IrDA Filter Register */ +#define REG_USART2_US_MAN (*(__IO uint32_t*)0x4002C050U) /**< (USART2) Manchester Configuration Register */ +#define REG_USART2_US_LINMR (*(__IO uint32_t*)0x4002C054U) /**< (USART2) LIN Mode Register */ +#define REG_USART2_US_LINIR (*(__IO uint32_t*)0x4002C058U) /**< (USART2) LIN Identifier Register */ +#define REG_USART2_US_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< (USART2) LIN Baud Rate Register */ +#define REG_USART2_US_LONMR (*(__IO uint32_t*)0x4002C060U) /**< (USART2) LON Mode Register */ +#define REG_USART2_US_LONPR (*(__IO uint32_t*)0x4002C064U) /**< (USART2) LON Preamble Register */ +#define REG_USART2_US_LONDL (*(__IO uint32_t*)0x4002C068U) /**< (USART2) LON Data Length Register */ +#define REG_USART2_US_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< (USART2) LON L2HDR Register */ +#define REG_USART2_US_LONBL (*(__I uint32_t*)0x4002C070U) /**< (USART2) LON Backlog Register */ +#define REG_USART2_US_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< (USART2) LON Beta1 Tx Register */ +#define REG_USART2_US_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< (USART2) LON Beta1 Rx Register */ +#define REG_USART2_US_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< (USART2) LON Priority Register */ +#define REG_USART2_US_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< (USART2) LON IDT Tx Register */ +#define REG_USART2_US_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< (USART2) LON IDT Rx Register */ +#define REG_USART2_US_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< (USART2) IC DIFF Register */ +#define REG_USART2_US_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< (USART2) Write Protection Mode Register */ +#define REG_USART2_US_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< (USART2) Write Protection Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for USART2 peripheral ========== */ +#define USART2_DMAC_ID_RX 12 +#define USART2_DMAC_ID_TX 11 +#define USART2_INSTANCE_ID 15 +#define USART2_CLOCK_ID 15 +#define USART2_USCLKS_MCK 0 /* MCK */ +#define USART2_USCLKS_DIV 1 /* MCK/8 */ +#define USART2_USCLKS_PCK 2 /* PCK4 */ +#define USART2_USCLKS_SCK 3 /* SCK */ + +#endif /* _SAME70_USART2_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/usbhs.h b/bsp/microchip/same70/bsp/same70b/include/instance/usbhs.h new file mode 100644 index 0000000000..ff8b60ce2c --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/usbhs.h @@ -0,0 +1,561 @@ +/** + * \file + * + * \brief Instance description for USBHS + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_USBHS_INSTANCE_H_ +#define _SAME70_USBHS_INSTANCE_H_ + +/* ========== Register definition for USBHS peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_USBHS_DEVDMANXTDSC0 (0x40038310) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 0 */ +#define REG_USBHS_DEVDMAADDRESS0 (0x40038314) /**< (USBHS) Device DMA Channel Address Register 0 */ +#define REG_USBHS_DEVDMACONTROL0 (0x40038318) /**< (USBHS) Device DMA Channel Control Register 0 */ +#define REG_USBHS_DEVDMASTATUS0 (0x4003831C) /**< (USBHS) Device DMA Channel Status Register 0 */ +#define REG_USBHS_DEVDMANXTDSC1 (0x40038320) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 1 */ +#define REG_USBHS_DEVDMAADDRESS1 (0x40038324) /**< (USBHS) Device DMA Channel Address Register 1 */ +#define REG_USBHS_DEVDMACONTROL1 (0x40038328) /**< (USBHS) Device DMA Channel Control Register 1 */ +#define REG_USBHS_DEVDMASTATUS1 (0x4003832C) /**< (USBHS) Device DMA Channel Status Register 1 */ +#define REG_USBHS_DEVDMANXTDSC2 (0x40038330) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 2 */ +#define REG_USBHS_DEVDMAADDRESS2 (0x40038334) /**< (USBHS) Device DMA Channel Address Register 2 */ +#define REG_USBHS_DEVDMACONTROL2 (0x40038338) /**< (USBHS) Device DMA Channel Control Register 2 */ +#define REG_USBHS_DEVDMASTATUS2 (0x4003833C) /**< (USBHS) Device DMA Channel Status Register 2 */ +#define REG_USBHS_DEVDMANXTDSC3 (0x40038340) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 3 */ +#define REG_USBHS_DEVDMAADDRESS3 (0x40038344) /**< (USBHS) Device DMA Channel Address Register 3 */ +#define REG_USBHS_DEVDMACONTROL3 (0x40038348) /**< (USBHS) Device DMA Channel Control Register 3 */ +#define REG_USBHS_DEVDMASTATUS3 (0x4003834C) /**< (USBHS) Device DMA Channel Status Register 3 */ +#define REG_USBHS_DEVDMANXTDSC4 (0x40038350) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 4 */ +#define REG_USBHS_DEVDMAADDRESS4 (0x40038354) /**< (USBHS) Device DMA Channel Address Register 4 */ +#define REG_USBHS_DEVDMACONTROL4 (0x40038358) /**< (USBHS) Device DMA Channel Control Register 4 */ +#define REG_USBHS_DEVDMASTATUS4 (0x4003835C) /**< (USBHS) Device DMA Channel Status Register 4 */ +#define REG_USBHS_DEVDMANXTDSC5 (0x40038360) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 5 */ +#define REG_USBHS_DEVDMAADDRESS5 (0x40038364) /**< (USBHS) Device DMA Channel Address Register 5 */ +#define REG_USBHS_DEVDMACONTROL5 (0x40038368) /**< (USBHS) Device DMA Channel Control Register 5 */ +#define REG_USBHS_DEVDMASTATUS5 (0x4003836C) /**< (USBHS) Device DMA Channel Status Register 5 */ +#define REG_USBHS_DEVDMANXTDSC6 (0x40038370) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 6 */ +#define REG_USBHS_DEVDMAADDRESS6 (0x40038374) /**< (USBHS) Device DMA Channel Address Register 6 */ +#define REG_USBHS_DEVDMACONTROL6 (0x40038378) /**< (USBHS) Device DMA Channel Control Register 6 */ +#define REG_USBHS_DEVDMASTATUS6 (0x4003837C) /**< (USBHS) Device DMA Channel Status Register 6 */ +#define REG_USBHS_HSTDMANXTDSC0 (0x40038710) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 0 */ +#define REG_USBHS_HSTDMAADDRESS0 (0x40038714) /**< (USBHS) Host DMA Channel Address Register 0 */ +#define REG_USBHS_HSTDMACONTROL0 (0x40038718) /**< (USBHS) Host DMA Channel Control Register 0 */ +#define REG_USBHS_HSTDMASTATUS0 (0x4003871C) /**< (USBHS) Host DMA Channel Status Register 0 */ +#define REG_USBHS_HSTDMANXTDSC1 (0x40038720) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 1 */ +#define REG_USBHS_HSTDMAADDRESS1 (0x40038724) /**< (USBHS) Host DMA Channel Address Register 1 */ +#define REG_USBHS_HSTDMACONTROL1 (0x40038728) /**< (USBHS) Host DMA Channel Control Register 1 */ +#define REG_USBHS_HSTDMASTATUS1 (0x4003872C) /**< (USBHS) Host DMA Channel Status Register 1 */ +#define REG_USBHS_HSTDMANXTDSC2 (0x40038730) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 2 */ +#define REG_USBHS_HSTDMAADDRESS2 (0x40038734) /**< (USBHS) Host DMA Channel Address Register 2 */ +#define REG_USBHS_HSTDMACONTROL2 (0x40038738) /**< (USBHS) Host DMA Channel Control Register 2 */ +#define REG_USBHS_HSTDMASTATUS2 (0x4003873C) /**< (USBHS) Host DMA Channel Status Register 2 */ +#define REG_USBHS_HSTDMANXTDSC3 (0x40038740) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 3 */ +#define REG_USBHS_HSTDMAADDRESS3 (0x40038744) /**< (USBHS) Host DMA Channel Address Register 3 */ +#define REG_USBHS_HSTDMACONTROL3 (0x40038748) /**< (USBHS) Host DMA Channel Control Register 3 */ +#define REG_USBHS_HSTDMASTATUS3 (0x4003874C) /**< (USBHS) Host DMA Channel Status Register 3 */ +#define REG_USBHS_HSTDMANXTDSC4 (0x40038750) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 4 */ +#define REG_USBHS_HSTDMAADDRESS4 (0x40038754) /**< (USBHS) Host DMA Channel Address Register 4 */ +#define REG_USBHS_HSTDMACONTROL4 (0x40038758) /**< (USBHS) Host DMA Channel Control Register 4 */ +#define REG_USBHS_HSTDMASTATUS4 (0x4003875C) /**< (USBHS) Host DMA Channel Status Register 4 */ +#define REG_USBHS_HSTDMANXTDSC5 (0x40038760) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 5 */ +#define REG_USBHS_HSTDMAADDRESS5 (0x40038764) /**< (USBHS) Host DMA Channel Address Register 5 */ +#define REG_USBHS_HSTDMACONTROL5 (0x40038768) /**< (USBHS) Host DMA Channel Control Register 5 */ +#define REG_USBHS_HSTDMASTATUS5 (0x4003876C) /**< (USBHS) Host DMA Channel Status Register 5 */ +#define REG_USBHS_HSTDMANXTDSC6 (0x40038770) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 6 */ +#define REG_USBHS_HSTDMAADDRESS6 (0x40038774) /**< (USBHS) Host DMA Channel Address Register 6 */ +#define REG_USBHS_HSTDMACONTROL6 (0x40038778) /**< (USBHS) Host DMA Channel Control Register 6 */ +#define REG_USBHS_HSTDMASTATUS6 (0x4003877C) /**< (USBHS) Host DMA Channel Status Register 6 */ +#define REG_USBHS_DEVCTRL (0x40038000) /**< (USBHS) Device General Control Register */ +#define REG_USBHS_DEVISR (0x40038004) /**< (USBHS) Device Global Interrupt Status Register */ +#define REG_USBHS_DEVICR (0x40038008) /**< (USBHS) Device Global Interrupt Clear Register */ +#define REG_USBHS_DEVIFR (0x4003800C) /**< (USBHS) Device Global Interrupt Set Register */ +#define REG_USBHS_DEVIMR (0x40038010) /**< (USBHS) Device Global Interrupt Mask Register */ +#define REG_USBHS_DEVIDR (0x40038014) /**< (USBHS) Device Global Interrupt Disable Register */ +#define REG_USBHS_DEVIER (0x40038018) /**< (USBHS) Device Global Interrupt Enable Register */ +#define REG_USBHS_DEVEPT (0x4003801C) /**< (USBHS) Device Endpoint Register */ +#define REG_USBHS_DEVFNUM (0x40038020) /**< (USBHS) Device Frame Number Register */ +#define REG_USBHS_DEVEPTCFG (0x40038100) /**< (USBHS) Device Endpoint Configuration Register */ +#define REG_USBHS_DEVEPTCFG0 (0x40038100) /**< (USBHS) Device Endpoint Configuration Register 0 */ +#define REG_USBHS_DEVEPTCFG1 (0x40038104) /**< (USBHS) Device Endpoint Configuration Register 1 */ +#define REG_USBHS_DEVEPTCFG2 (0x40038108) /**< (USBHS) Device Endpoint Configuration Register 2 */ +#define REG_USBHS_DEVEPTCFG3 (0x4003810C) /**< (USBHS) Device Endpoint Configuration Register 3 */ +#define REG_USBHS_DEVEPTCFG4 (0x40038110) /**< (USBHS) Device Endpoint Configuration Register 4 */ +#define REG_USBHS_DEVEPTCFG5 (0x40038114) /**< (USBHS) Device Endpoint Configuration Register 5 */ +#define REG_USBHS_DEVEPTCFG6 (0x40038118) /**< (USBHS) Device Endpoint Configuration Register 6 */ +#define REG_USBHS_DEVEPTCFG7 (0x4003811C) /**< (USBHS) Device Endpoint Configuration Register 7 */ +#define REG_USBHS_DEVEPTCFG8 (0x40038120) /**< (USBHS) Device Endpoint Configuration Register 8 */ +#define REG_USBHS_DEVEPTCFG9 (0x40038124) /**< (USBHS) Device Endpoint Configuration Register 9 */ +#define REG_USBHS_DEVEPTISR (0x40038130) /**< (USBHS) Device Endpoint Interrupt Status Register */ +#define REG_USBHS_DEVEPTISR0 (0x40038130) /**< (USBHS) Device Endpoint Interrupt Status Register 0 */ +#define REG_USBHS_DEVEPTISR1 (0x40038134) /**< (USBHS) Device Endpoint Interrupt Status Register 1 */ +#define REG_USBHS_DEVEPTISR2 (0x40038138) /**< (USBHS) Device Endpoint Interrupt Status Register 2 */ +#define REG_USBHS_DEVEPTISR3 (0x4003813C) /**< (USBHS) Device Endpoint Interrupt Status Register 3 */ +#define REG_USBHS_DEVEPTISR4 (0x40038140) /**< (USBHS) Device Endpoint Interrupt Status Register 4 */ +#define REG_USBHS_DEVEPTISR5 (0x40038144) /**< (USBHS) Device Endpoint Interrupt Status Register 5 */ +#define REG_USBHS_DEVEPTISR6 (0x40038148) /**< (USBHS) Device Endpoint Interrupt Status Register 6 */ +#define REG_USBHS_DEVEPTISR7 (0x4003814C) /**< (USBHS) Device Endpoint Interrupt Status Register 7 */ +#define REG_USBHS_DEVEPTISR8 (0x40038150) /**< (USBHS) Device Endpoint Interrupt Status Register 8 */ +#define REG_USBHS_DEVEPTISR9 (0x40038154) /**< (USBHS) Device Endpoint Interrupt Status Register 9 */ +#define REG_USBHS_DEVEPTICR (0x40038160) /**< (USBHS) Device Endpoint Interrupt Clear Register */ +#define REG_USBHS_DEVEPTICR0 (0x40038160) /**< (USBHS) Device Endpoint Interrupt Clear Register 0 */ +#define REG_USBHS_DEVEPTICR1 (0x40038164) /**< (USBHS) Device Endpoint Interrupt Clear Register 1 */ +#define REG_USBHS_DEVEPTICR2 (0x40038168) /**< (USBHS) Device Endpoint Interrupt Clear Register 2 */ +#define REG_USBHS_DEVEPTICR3 (0x4003816C) /**< (USBHS) Device Endpoint Interrupt Clear Register 3 */ +#define REG_USBHS_DEVEPTICR4 (0x40038170) /**< (USBHS) Device Endpoint Interrupt Clear Register 4 */ +#define REG_USBHS_DEVEPTICR5 (0x40038174) /**< (USBHS) Device Endpoint Interrupt Clear Register 5 */ +#define REG_USBHS_DEVEPTICR6 (0x40038178) /**< (USBHS) Device Endpoint Interrupt Clear Register 6 */ +#define REG_USBHS_DEVEPTICR7 (0x4003817C) /**< (USBHS) Device Endpoint Interrupt Clear Register 7 */ +#define REG_USBHS_DEVEPTICR8 (0x40038180) /**< (USBHS) Device Endpoint Interrupt Clear Register 8 */ +#define REG_USBHS_DEVEPTICR9 (0x40038184) /**< (USBHS) Device Endpoint Interrupt Clear Register 9 */ +#define REG_USBHS_DEVEPTIFR (0x40038190) /**< (USBHS) Device Endpoint Interrupt Set Register */ +#define REG_USBHS_DEVEPTIFR0 (0x40038190) /**< (USBHS) Device Endpoint Interrupt Set Register 0 */ +#define REG_USBHS_DEVEPTIFR1 (0x40038194) /**< (USBHS) Device Endpoint Interrupt Set Register 1 */ +#define REG_USBHS_DEVEPTIFR2 (0x40038198) /**< (USBHS) Device Endpoint Interrupt Set Register 2 */ +#define REG_USBHS_DEVEPTIFR3 (0x4003819C) /**< (USBHS) Device Endpoint Interrupt Set Register 3 */ +#define REG_USBHS_DEVEPTIFR4 (0x400381A0) /**< (USBHS) Device Endpoint Interrupt Set Register 4 */ +#define REG_USBHS_DEVEPTIFR5 (0x400381A4) /**< (USBHS) Device Endpoint Interrupt Set Register 5 */ +#define REG_USBHS_DEVEPTIFR6 (0x400381A8) /**< (USBHS) Device Endpoint Interrupt Set Register 6 */ +#define REG_USBHS_DEVEPTIFR7 (0x400381AC) /**< (USBHS) Device Endpoint Interrupt Set Register 7 */ +#define REG_USBHS_DEVEPTIFR8 (0x400381B0) /**< (USBHS) Device Endpoint Interrupt Set Register 8 */ +#define REG_USBHS_DEVEPTIFR9 (0x400381B4) /**< (USBHS) Device Endpoint Interrupt Set Register 9 */ +#define REG_USBHS_DEVEPTIMR (0x400381C0) /**< (USBHS) Device Endpoint Interrupt Mask Register */ +#define REG_USBHS_DEVEPTIMR0 (0x400381C0) /**< (USBHS) Device Endpoint Interrupt Mask Register 0 */ +#define REG_USBHS_DEVEPTIMR1 (0x400381C4) /**< (USBHS) Device Endpoint Interrupt Mask Register 1 */ +#define REG_USBHS_DEVEPTIMR2 (0x400381C8) /**< (USBHS) Device Endpoint Interrupt Mask Register 2 */ +#define REG_USBHS_DEVEPTIMR3 (0x400381CC) /**< (USBHS) Device Endpoint Interrupt Mask Register 3 */ +#define REG_USBHS_DEVEPTIMR4 (0x400381D0) /**< (USBHS) Device Endpoint Interrupt Mask Register 4 */ +#define REG_USBHS_DEVEPTIMR5 (0x400381D4) /**< (USBHS) Device Endpoint Interrupt Mask Register 5 */ +#define REG_USBHS_DEVEPTIMR6 (0x400381D8) /**< (USBHS) Device Endpoint Interrupt Mask Register 6 */ +#define REG_USBHS_DEVEPTIMR7 (0x400381DC) /**< (USBHS) Device Endpoint Interrupt Mask Register 7 */ +#define REG_USBHS_DEVEPTIMR8 (0x400381E0) /**< (USBHS) Device Endpoint Interrupt Mask Register 8 */ +#define REG_USBHS_DEVEPTIMR9 (0x400381E4) /**< (USBHS) Device Endpoint Interrupt Mask Register 9 */ +#define REG_USBHS_DEVEPTIER (0x400381F0) /**< (USBHS) Device Endpoint Interrupt Enable Register */ +#define REG_USBHS_DEVEPTIER0 (0x400381F0) /**< (USBHS) Device Endpoint Interrupt Enable Register 0 */ +#define REG_USBHS_DEVEPTIER1 (0x400381F4) /**< (USBHS) Device Endpoint Interrupt Enable Register 1 */ +#define REG_USBHS_DEVEPTIER2 (0x400381F8) /**< (USBHS) Device Endpoint Interrupt Enable Register 2 */ +#define REG_USBHS_DEVEPTIER3 (0x400381FC) /**< (USBHS) Device Endpoint Interrupt Enable Register 3 */ +#define REG_USBHS_DEVEPTIER4 (0x40038200) /**< (USBHS) Device Endpoint Interrupt Enable Register 4 */ +#define REG_USBHS_DEVEPTIER5 (0x40038204) /**< (USBHS) Device Endpoint Interrupt Enable Register 5 */ +#define REG_USBHS_DEVEPTIER6 (0x40038208) /**< (USBHS) Device Endpoint Interrupt Enable Register 6 */ +#define REG_USBHS_DEVEPTIER7 (0x4003820C) /**< (USBHS) Device Endpoint Interrupt Enable Register 7 */ +#define REG_USBHS_DEVEPTIER8 (0x40038210) /**< (USBHS) Device Endpoint Interrupt Enable Register 8 */ +#define REG_USBHS_DEVEPTIER9 (0x40038214) /**< (USBHS) Device Endpoint Interrupt Enable Register 9 */ +#define REG_USBHS_DEVEPTIDR (0x40038220) /**< (USBHS) Device Endpoint Interrupt Disable Register */ +#define REG_USBHS_DEVEPTIDR0 (0x40038220) /**< (USBHS) Device Endpoint Interrupt Disable Register 0 */ +#define REG_USBHS_DEVEPTIDR1 (0x40038224) /**< (USBHS) Device Endpoint Interrupt Disable Register 1 */ +#define REG_USBHS_DEVEPTIDR2 (0x40038228) /**< (USBHS) Device Endpoint Interrupt Disable Register 2 */ +#define REG_USBHS_DEVEPTIDR3 (0x4003822C) /**< (USBHS) Device Endpoint Interrupt Disable Register 3 */ +#define REG_USBHS_DEVEPTIDR4 (0x40038230) /**< (USBHS) Device Endpoint Interrupt Disable Register 4 */ +#define REG_USBHS_DEVEPTIDR5 (0x40038234) /**< (USBHS) Device Endpoint Interrupt Disable Register 5 */ +#define REG_USBHS_DEVEPTIDR6 (0x40038238) /**< (USBHS) Device Endpoint Interrupt Disable Register 6 */ +#define REG_USBHS_DEVEPTIDR7 (0x4003823C) /**< (USBHS) Device Endpoint Interrupt Disable Register 7 */ +#define REG_USBHS_DEVEPTIDR8 (0x40038240) /**< (USBHS) Device Endpoint Interrupt Disable Register 8 */ +#define REG_USBHS_DEVEPTIDR9 (0x40038244) /**< (USBHS) Device Endpoint Interrupt Disable Register 9 */ +#define REG_USBHS_HSTCTRL (0x40038400) /**< (USBHS) Host General Control Register */ +#define REG_USBHS_HSTISR (0x40038404) /**< (USBHS) Host Global Interrupt Status Register */ +#define REG_USBHS_HSTICR (0x40038408) /**< (USBHS) Host Global Interrupt Clear Register */ +#define REG_USBHS_HSTIFR (0x4003840C) /**< (USBHS) Host Global Interrupt Set Register */ +#define REG_USBHS_HSTIMR (0x40038410) /**< (USBHS) Host Global Interrupt Mask Register */ +#define REG_USBHS_HSTIDR (0x40038414) /**< (USBHS) Host Global Interrupt Disable Register */ +#define REG_USBHS_HSTIER (0x40038418) /**< (USBHS) Host Global Interrupt Enable Register */ +#define REG_USBHS_HSTPIP (0x4003841C) /**< (USBHS) Host Pipe Register */ +#define REG_USBHS_HSTFNUM (0x40038420) /**< (USBHS) Host Frame Number Register */ +#define REG_USBHS_HSTADDR1 (0x40038424) /**< (USBHS) Host Address 1 Register */ +#define REG_USBHS_HSTADDR2 (0x40038428) /**< (USBHS) Host Address 2 Register */ +#define REG_USBHS_HSTADDR3 (0x4003842C) /**< (USBHS) Host Address 3 Register */ +#define REG_USBHS_HSTPIPCFG (0x40038500) /**< (USBHS) Host Pipe Configuration Register */ +#define REG_USBHS_HSTPIPCFG0 (0x40038500) /**< (USBHS) Host Pipe Configuration Register 0 */ +#define REG_USBHS_HSTPIPCFG1 (0x40038504) /**< (USBHS) Host Pipe Configuration Register 1 */ +#define REG_USBHS_HSTPIPCFG2 (0x40038508) /**< (USBHS) Host Pipe Configuration Register 2 */ +#define REG_USBHS_HSTPIPCFG3 (0x4003850C) /**< (USBHS) Host Pipe Configuration Register 3 */ +#define REG_USBHS_HSTPIPCFG4 (0x40038510) /**< (USBHS) Host Pipe Configuration Register 4 */ +#define REG_USBHS_HSTPIPCFG5 (0x40038514) /**< (USBHS) Host Pipe Configuration Register 5 */ +#define REG_USBHS_HSTPIPCFG6 (0x40038518) /**< (USBHS) Host Pipe Configuration Register 6 */ +#define REG_USBHS_HSTPIPCFG7 (0x4003851C) /**< (USBHS) Host Pipe Configuration Register 7 */ +#define REG_USBHS_HSTPIPCFG8 (0x40038520) /**< (USBHS) Host Pipe Configuration Register 8 */ +#define REG_USBHS_HSTPIPCFG9 (0x40038524) /**< (USBHS) Host Pipe Configuration Register 9 */ +#define REG_USBHS_HSTPIPISR (0x40038530) /**< (USBHS) Host Pipe Status Register */ +#define REG_USBHS_HSTPIPISR0 (0x40038530) /**< (USBHS) Host Pipe Status Register 0 */ +#define REG_USBHS_HSTPIPISR1 (0x40038534) /**< (USBHS) Host Pipe Status Register 1 */ +#define REG_USBHS_HSTPIPISR2 (0x40038538) /**< (USBHS) Host Pipe Status Register 2 */ +#define REG_USBHS_HSTPIPISR3 (0x4003853C) /**< (USBHS) Host Pipe Status Register 3 */ +#define REG_USBHS_HSTPIPISR4 (0x40038540) /**< (USBHS) Host Pipe Status Register 4 */ +#define REG_USBHS_HSTPIPISR5 (0x40038544) /**< (USBHS) Host Pipe Status Register 5 */ +#define REG_USBHS_HSTPIPISR6 (0x40038548) /**< (USBHS) Host Pipe Status Register 6 */ +#define REG_USBHS_HSTPIPISR7 (0x4003854C) /**< (USBHS) Host Pipe Status Register 7 */ +#define REG_USBHS_HSTPIPISR8 (0x40038550) /**< (USBHS) Host Pipe Status Register 8 */ +#define REG_USBHS_HSTPIPISR9 (0x40038554) /**< (USBHS) Host Pipe Status Register 9 */ +#define REG_USBHS_HSTPIPICR (0x40038560) /**< (USBHS) Host Pipe Clear Register */ +#define REG_USBHS_HSTPIPICR0 (0x40038560) /**< (USBHS) Host Pipe Clear Register 0 */ +#define REG_USBHS_HSTPIPICR1 (0x40038564) /**< (USBHS) Host Pipe Clear Register 1 */ +#define REG_USBHS_HSTPIPICR2 (0x40038568) /**< (USBHS) Host Pipe Clear Register 2 */ +#define REG_USBHS_HSTPIPICR3 (0x4003856C) /**< (USBHS) Host Pipe Clear Register 3 */ +#define REG_USBHS_HSTPIPICR4 (0x40038570) /**< (USBHS) Host Pipe Clear Register 4 */ +#define REG_USBHS_HSTPIPICR5 (0x40038574) /**< (USBHS) Host Pipe Clear Register 5 */ +#define REG_USBHS_HSTPIPICR6 (0x40038578) /**< (USBHS) Host Pipe Clear Register 6 */ +#define REG_USBHS_HSTPIPICR7 (0x4003857C) /**< (USBHS) Host Pipe Clear Register 7 */ +#define REG_USBHS_HSTPIPICR8 (0x40038580) /**< (USBHS) Host Pipe Clear Register 8 */ +#define REG_USBHS_HSTPIPICR9 (0x40038584) /**< (USBHS) Host Pipe Clear Register 9 */ +#define REG_USBHS_HSTPIPIFR (0x40038590) /**< (USBHS) Host Pipe Set Register */ +#define REG_USBHS_HSTPIPIFR0 (0x40038590) /**< (USBHS) Host Pipe Set Register 0 */ +#define REG_USBHS_HSTPIPIFR1 (0x40038594) /**< (USBHS) Host Pipe Set Register 1 */ +#define REG_USBHS_HSTPIPIFR2 (0x40038598) /**< (USBHS) Host Pipe Set Register 2 */ +#define REG_USBHS_HSTPIPIFR3 (0x4003859C) /**< (USBHS) Host Pipe Set Register 3 */ +#define REG_USBHS_HSTPIPIFR4 (0x400385A0) /**< (USBHS) Host Pipe Set Register 4 */ +#define REG_USBHS_HSTPIPIFR5 (0x400385A4) /**< (USBHS) Host Pipe Set Register 5 */ +#define REG_USBHS_HSTPIPIFR6 (0x400385A8) /**< (USBHS) Host Pipe Set Register 6 */ +#define REG_USBHS_HSTPIPIFR7 (0x400385AC) /**< (USBHS) Host Pipe Set Register 7 */ +#define REG_USBHS_HSTPIPIFR8 (0x400385B0) /**< (USBHS) Host Pipe Set Register 8 */ +#define REG_USBHS_HSTPIPIFR9 (0x400385B4) /**< (USBHS) Host Pipe Set Register 9 */ +#define REG_USBHS_HSTPIPIMR (0x400385C0) /**< (USBHS) Host Pipe Mask Register */ +#define REG_USBHS_HSTPIPIMR0 (0x400385C0) /**< (USBHS) Host Pipe Mask Register 0 */ +#define REG_USBHS_HSTPIPIMR1 (0x400385C4) /**< (USBHS) Host Pipe Mask Register 1 */ +#define REG_USBHS_HSTPIPIMR2 (0x400385C8) /**< (USBHS) Host Pipe Mask Register 2 */ +#define REG_USBHS_HSTPIPIMR3 (0x400385CC) /**< (USBHS) Host Pipe Mask Register 3 */ +#define REG_USBHS_HSTPIPIMR4 (0x400385D0) /**< (USBHS) Host Pipe Mask Register 4 */ +#define REG_USBHS_HSTPIPIMR5 (0x400385D4) /**< (USBHS) Host Pipe Mask Register 5 */ +#define REG_USBHS_HSTPIPIMR6 (0x400385D8) /**< (USBHS) Host Pipe Mask Register 6 */ +#define REG_USBHS_HSTPIPIMR7 (0x400385DC) /**< (USBHS) Host Pipe Mask Register 7 */ +#define REG_USBHS_HSTPIPIMR8 (0x400385E0) /**< (USBHS) Host Pipe Mask Register 8 */ +#define REG_USBHS_HSTPIPIMR9 (0x400385E4) /**< (USBHS) Host Pipe Mask Register 9 */ +#define REG_USBHS_HSTPIPIER (0x400385F0) /**< (USBHS) Host Pipe Enable Register */ +#define REG_USBHS_HSTPIPIER0 (0x400385F0) /**< (USBHS) Host Pipe Enable Register 0 */ +#define REG_USBHS_HSTPIPIER1 (0x400385F4) /**< (USBHS) Host Pipe Enable Register 1 */ +#define REG_USBHS_HSTPIPIER2 (0x400385F8) /**< (USBHS) Host Pipe Enable Register 2 */ +#define REG_USBHS_HSTPIPIER3 (0x400385FC) /**< (USBHS) Host Pipe Enable Register 3 */ +#define REG_USBHS_HSTPIPIER4 (0x40038600) /**< (USBHS) Host Pipe Enable Register 4 */ +#define REG_USBHS_HSTPIPIER5 (0x40038604) /**< (USBHS) Host Pipe Enable Register 5 */ +#define REG_USBHS_HSTPIPIER6 (0x40038608) /**< (USBHS) Host Pipe Enable Register 6 */ +#define REG_USBHS_HSTPIPIER7 (0x4003860C) /**< (USBHS) Host Pipe Enable Register 7 */ +#define REG_USBHS_HSTPIPIER8 (0x40038610) /**< (USBHS) Host Pipe Enable Register 8 */ +#define REG_USBHS_HSTPIPIER9 (0x40038614) /**< (USBHS) Host Pipe Enable Register 9 */ +#define REG_USBHS_HSTPIPIDR (0x40038620) /**< (USBHS) Host Pipe Disable Register */ +#define REG_USBHS_HSTPIPIDR0 (0x40038620) /**< (USBHS) Host Pipe Disable Register 0 */ +#define REG_USBHS_HSTPIPIDR1 (0x40038624) /**< (USBHS) Host Pipe Disable Register 1 */ +#define REG_USBHS_HSTPIPIDR2 (0x40038628) /**< (USBHS) Host Pipe Disable Register 2 */ +#define REG_USBHS_HSTPIPIDR3 (0x4003862C) /**< (USBHS) Host Pipe Disable Register 3 */ +#define REG_USBHS_HSTPIPIDR4 (0x40038630) /**< (USBHS) Host Pipe Disable Register 4 */ +#define REG_USBHS_HSTPIPIDR5 (0x40038634) /**< (USBHS) Host Pipe Disable Register 5 */ +#define REG_USBHS_HSTPIPIDR6 (0x40038638) /**< (USBHS) Host Pipe Disable Register 6 */ +#define REG_USBHS_HSTPIPIDR7 (0x4003863C) /**< (USBHS) Host Pipe Disable Register 7 */ +#define REG_USBHS_HSTPIPIDR8 (0x40038640) /**< (USBHS) Host Pipe Disable Register 8 */ +#define REG_USBHS_HSTPIPIDR9 (0x40038644) /**< (USBHS) Host Pipe Disable Register 9 */ +#define REG_USBHS_HSTPIPINRQ (0x40038650) /**< (USBHS) Host Pipe IN Request Register */ +#define REG_USBHS_HSTPIPINRQ0 (0x40038650) /**< (USBHS) Host Pipe IN Request Register 0 */ +#define REG_USBHS_HSTPIPINRQ1 (0x40038654) /**< (USBHS) Host Pipe IN Request Register 1 */ +#define REG_USBHS_HSTPIPINRQ2 (0x40038658) /**< (USBHS) Host Pipe IN Request Register 2 */ +#define REG_USBHS_HSTPIPINRQ3 (0x4003865C) /**< (USBHS) Host Pipe IN Request Register 3 */ +#define REG_USBHS_HSTPIPINRQ4 (0x40038660) /**< (USBHS) Host Pipe IN Request Register 4 */ +#define REG_USBHS_HSTPIPINRQ5 (0x40038664) /**< (USBHS) Host Pipe IN Request Register 5 */ +#define REG_USBHS_HSTPIPINRQ6 (0x40038668) /**< (USBHS) Host Pipe IN Request Register 6 */ +#define REG_USBHS_HSTPIPINRQ7 (0x4003866C) /**< (USBHS) Host Pipe IN Request Register 7 */ +#define REG_USBHS_HSTPIPINRQ8 (0x40038670) /**< (USBHS) Host Pipe IN Request Register 8 */ +#define REG_USBHS_HSTPIPINRQ9 (0x40038674) /**< (USBHS) Host Pipe IN Request Register 9 */ +#define REG_USBHS_HSTPIPERR (0x40038680) /**< (USBHS) Host Pipe Error Register */ +#define REG_USBHS_HSTPIPERR0 (0x40038680) /**< (USBHS) Host Pipe Error Register 0 */ +#define REG_USBHS_HSTPIPERR1 (0x40038684) /**< (USBHS) Host Pipe Error Register 1 */ +#define REG_USBHS_HSTPIPERR2 (0x40038688) /**< (USBHS) Host Pipe Error Register 2 */ +#define REG_USBHS_HSTPIPERR3 (0x4003868C) /**< (USBHS) Host Pipe Error Register 3 */ +#define REG_USBHS_HSTPIPERR4 (0x40038690) /**< (USBHS) Host Pipe Error Register 4 */ +#define REG_USBHS_HSTPIPERR5 (0x40038694) /**< (USBHS) Host Pipe Error Register 5 */ +#define REG_USBHS_HSTPIPERR6 (0x40038698) /**< (USBHS) Host Pipe Error Register 6 */ +#define REG_USBHS_HSTPIPERR7 (0x4003869C) /**< (USBHS) Host Pipe Error Register 7 */ +#define REG_USBHS_HSTPIPERR8 (0x400386A0) /**< (USBHS) Host Pipe Error Register 8 */ +#define REG_USBHS_HSTPIPERR9 (0x400386A4) /**< (USBHS) Host Pipe Error Register 9 */ +#define REG_USBHS_CTRL (0x40038800) /**< (USBHS) General Control Register */ +#define REG_USBHS_SR (0x40038804) /**< (USBHS) General Status Register */ +#define REG_USBHS_SCR (0x40038808) /**< (USBHS) General Status Clear Register */ +#define REG_USBHS_SFR (0x4003880C) /**< (USBHS) General Status Set Register */ + +#else + +#define REG_USBHS_DEVDMANXTDSC0 (*(__IO uint32_t*)0x40038310U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 0 */ +#define REG_USBHS_DEVDMAADDRESS0 (*(__IO uint32_t*)0x40038314U) /**< (USBHS) Device DMA Channel Address Register 0 */ +#define REG_USBHS_DEVDMACONTROL0 (*(__IO uint32_t*)0x40038318U) /**< (USBHS) Device DMA Channel Control Register 0 */ +#define REG_USBHS_DEVDMASTATUS0 (*(__IO uint32_t*)0x4003831CU) /**< (USBHS) Device DMA Channel Status Register 0 */ +#define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038320U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 1 */ +#define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038324U) /**< (USBHS) Device DMA Channel Address Register 1 */ +#define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038328U) /**< (USBHS) Device DMA Channel Control Register 1 */ +#define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003832CU) /**< (USBHS) Device DMA Channel Status Register 1 */ +#define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038330U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 2 */ +#define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038334U) /**< (USBHS) Device DMA Channel Address Register 2 */ +#define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038338U) /**< (USBHS) Device DMA Channel Control Register 2 */ +#define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003833CU) /**< (USBHS) Device DMA Channel Status Register 2 */ +#define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038340U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 3 */ +#define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038344U) /**< (USBHS) Device DMA Channel Address Register 3 */ +#define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038348U) /**< (USBHS) Device DMA Channel Control Register 3 */ +#define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003834CU) /**< (USBHS) Device DMA Channel Status Register 3 */ +#define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038350U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 4 */ +#define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038354U) /**< (USBHS) Device DMA Channel Address Register 4 */ +#define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038358U) /**< (USBHS) Device DMA Channel Control Register 4 */ +#define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003835CU) /**< (USBHS) Device DMA Channel Status Register 4 */ +#define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038360U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 5 */ +#define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038364U) /**< (USBHS) Device DMA Channel Address Register 5 */ +#define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038368U) /**< (USBHS) Device DMA Channel Control Register 5 */ +#define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003836CU) /**< (USBHS) Device DMA Channel Status Register 5 */ +#define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038370U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 6 */ +#define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038374U) /**< (USBHS) Device DMA Channel Address Register 6 */ +#define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038378U) /**< (USBHS) Device DMA Channel Control Register 6 */ +#define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003837CU) /**< (USBHS) Device DMA Channel Status Register 6 */ +#define REG_USBHS_HSTDMANXTDSC0 (*(__IO uint32_t*)0x40038710U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 0 */ +#define REG_USBHS_HSTDMAADDRESS0 (*(__IO uint32_t*)0x40038714U) /**< (USBHS) Host DMA Channel Address Register 0 */ +#define REG_USBHS_HSTDMACONTROL0 (*(__IO uint32_t*)0x40038718U) /**< (USBHS) Host DMA Channel Control Register 0 */ +#define REG_USBHS_HSTDMASTATUS0 (*(__IO uint32_t*)0x4003871CU) /**< (USBHS) Host DMA Channel Status Register 0 */ +#define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038720U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 1 */ +#define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038724U) /**< (USBHS) Host DMA Channel Address Register 1 */ +#define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038728U) /**< (USBHS) Host DMA Channel Control Register 1 */ +#define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003872CU) /**< (USBHS) Host DMA Channel Status Register 1 */ +#define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038730U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 2 */ +#define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038734U) /**< (USBHS) Host DMA Channel Address Register 2 */ +#define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038738U) /**< (USBHS) Host DMA Channel Control Register 2 */ +#define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003873CU) /**< (USBHS) Host DMA Channel Status Register 2 */ +#define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038740U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 3 */ +#define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038744U) /**< (USBHS) Host DMA Channel Address Register 3 */ +#define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038748U) /**< (USBHS) Host DMA Channel Control Register 3 */ +#define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003874CU) /**< (USBHS) Host DMA Channel Status Register 3 */ +#define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038750U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 4 */ +#define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038754U) /**< (USBHS) Host DMA Channel Address Register 4 */ +#define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038758U) /**< (USBHS) Host DMA Channel Control Register 4 */ +#define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003875CU) /**< (USBHS) Host DMA Channel Status Register 4 */ +#define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038760U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 5 */ +#define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038764U) /**< (USBHS) Host DMA Channel Address Register 5 */ +#define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038768U) /**< (USBHS) Host DMA Channel Control Register 5 */ +#define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003876CU) /**< (USBHS) Host DMA Channel Status Register 5 */ +#define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038770U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 6 */ +#define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038774U) /**< (USBHS) Host DMA Channel Address Register 6 */ +#define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038778U) /**< (USBHS) Host DMA Channel Control Register 6 */ +#define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003877CU) /**< (USBHS) Host DMA Channel Status Register 6 */ +#define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< (USBHS) Device General Control Register */ +#define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< (USBHS) Device Global Interrupt Status Register */ +#define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< (USBHS) Device Global Interrupt Clear Register */ +#define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< (USBHS) Device Global Interrupt Set Register */ +#define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< (USBHS) Device Global Interrupt Mask Register */ +#define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< (USBHS) Device Global Interrupt Disable Register */ +#define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< (USBHS) Device Global Interrupt Enable Register */ +#define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< (USBHS) Device Endpoint Register */ +#define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< (USBHS) Device Frame Number Register */ +#define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register */ +#define REG_USBHS_DEVEPTCFG0 (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register 0 */ +#define REG_USBHS_DEVEPTCFG1 (*(__IO uint32_t*)0x40038104U) /**< (USBHS) Device Endpoint Configuration Register 1 */ +#define REG_USBHS_DEVEPTCFG2 (*(__IO uint32_t*)0x40038108U) /**< (USBHS) Device Endpoint Configuration Register 2 */ +#define REG_USBHS_DEVEPTCFG3 (*(__IO uint32_t*)0x4003810CU) /**< (USBHS) Device Endpoint Configuration Register 3 */ +#define REG_USBHS_DEVEPTCFG4 (*(__IO uint32_t*)0x40038110U) /**< (USBHS) Device Endpoint Configuration Register 4 */ +#define REG_USBHS_DEVEPTCFG5 (*(__IO uint32_t*)0x40038114U) /**< (USBHS) Device Endpoint Configuration Register 5 */ +#define REG_USBHS_DEVEPTCFG6 (*(__IO uint32_t*)0x40038118U) /**< (USBHS) Device Endpoint Configuration Register 6 */ +#define REG_USBHS_DEVEPTCFG7 (*(__IO uint32_t*)0x4003811CU) /**< (USBHS) Device Endpoint Configuration Register 7 */ +#define REG_USBHS_DEVEPTCFG8 (*(__IO uint32_t*)0x40038120U) /**< (USBHS) Device Endpoint Configuration Register 8 */ +#define REG_USBHS_DEVEPTCFG9 (*(__IO uint32_t*)0x40038124U) /**< (USBHS) Device Endpoint Configuration Register 9 */ +#define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Interrupt Status Register */ +#define REG_USBHS_DEVEPTISR0 (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Interrupt Status Register 0 */ +#define REG_USBHS_DEVEPTISR1 (*(__I uint32_t*)0x40038134U) /**< (USBHS) Device Endpoint Interrupt Status Register 1 */ +#define REG_USBHS_DEVEPTISR2 (*(__I uint32_t*)0x40038138U) /**< (USBHS) Device Endpoint Interrupt Status Register 2 */ +#define REG_USBHS_DEVEPTISR3 (*(__I uint32_t*)0x4003813CU) /**< (USBHS) Device Endpoint Interrupt Status Register 3 */ +#define REG_USBHS_DEVEPTISR4 (*(__I uint32_t*)0x40038140U) /**< (USBHS) Device Endpoint Interrupt Status Register 4 */ +#define REG_USBHS_DEVEPTISR5 (*(__I uint32_t*)0x40038144U) /**< (USBHS) Device Endpoint Interrupt Status Register 5 */ +#define REG_USBHS_DEVEPTISR6 (*(__I uint32_t*)0x40038148U) /**< (USBHS) Device Endpoint Interrupt Status Register 6 */ +#define REG_USBHS_DEVEPTISR7 (*(__I uint32_t*)0x4003814CU) /**< (USBHS) Device Endpoint Interrupt Status Register 7 */ +#define REG_USBHS_DEVEPTISR8 (*(__I uint32_t*)0x40038150U) /**< (USBHS) Device Endpoint Interrupt Status Register 8 */ +#define REG_USBHS_DEVEPTISR9 (*(__I uint32_t*)0x40038154U) /**< (USBHS) Device Endpoint Interrupt Status Register 9 */ +#define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Interrupt Clear Register */ +#define REG_USBHS_DEVEPTICR0 (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Interrupt Clear Register 0 */ +#define REG_USBHS_DEVEPTICR1 (*(__O uint32_t*)0x40038164U) /**< (USBHS) Device Endpoint Interrupt Clear Register 1 */ +#define REG_USBHS_DEVEPTICR2 (*(__O uint32_t*)0x40038168U) /**< (USBHS) Device Endpoint Interrupt Clear Register 2 */ +#define REG_USBHS_DEVEPTICR3 (*(__O uint32_t*)0x4003816CU) /**< (USBHS) Device Endpoint Interrupt Clear Register 3 */ +#define REG_USBHS_DEVEPTICR4 (*(__O uint32_t*)0x40038170U) /**< (USBHS) Device Endpoint Interrupt Clear Register 4 */ +#define REG_USBHS_DEVEPTICR5 (*(__O uint32_t*)0x40038174U) /**< (USBHS) Device Endpoint Interrupt Clear Register 5 */ +#define REG_USBHS_DEVEPTICR6 (*(__O uint32_t*)0x40038178U) /**< (USBHS) Device Endpoint Interrupt Clear Register 6 */ +#define REG_USBHS_DEVEPTICR7 (*(__O uint32_t*)0x4003817CU) /**< (USBHS) Device Endpoint Interrupt Clear Register 7 */ +#define REG_USBHS_DEVEPTICR8 (*(__O uint32_t*)0x40038180U) /**< (USBHS) Device Endpoint Interrupt Clear Register 8 */ +#define REG_USBHS_DEVEPTICR9 (*(__O uint32_t*)0x40038184U) /**< (USBHS) Device Endpoint Interrupt Clear Register 9 */ +#define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Interrupt Set Register */ +#define REG_USBHS_DEVEPTIFR0 (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Interrupt Set Register 0 */ +#define REG_USBHS_DEVEPTIFR1 (*(__O uint32_t*)0x40038194U) /**< (USBHS) Device Endpoint Interrupt Set Register 1 */ +#define REG_USBHS_DEVEPTIFR2 (*(__O uint32_t*)0x40038198U) /**< (USBHS) Device Endpoint Interrupt Set Register 2 */ +#define REG_USBHS_DEVEPTIFR3 (*(__O uint32_t*)0x4003819CU) /**< (USBHS) Device Endpoint Interrupt Set Register 3 */ +#define REG_USBHS_DEVEPTIFR4 (*(__O uint32_t*)0x400381A0U) /**< (USBHS) Device Endpoint Interrupt Set Register 4 */ +#define REG_USBHS_DEVEPTIFR5 (*(__O uint32_t*)0x400381A4U) /**< (USBHS) Device Endpoint Interrupt Set Register 5 */ +#define REG_USBHS_DEVEPTIFR6 (*(__O uint32_t*)0x400381A8U) /**< (USBHS) Device Endpoint Interrupt Set Register 6 */ +#define REG_USBHS_DEVEPTIFR7 (*(__O uint32_t*)0x400381ACU) /**< (USBHS) Device Endpoint Interrupt Set Register 7 */ +#define REG_USBHS_DEVEPTIFR8 (*(__O uint32_t*)0x400381B0U) /**< (USBHS) Device Endpoint Interrupt Set Register 8 */ +#define REG_USBHS_DEVEPTIFR9 (*(__O uint32_t*)0x400381B4U) /**< (USBHS) Device Endpoint Interrupt Set Register 9 */ +#define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Interrupt Mask Register */ +#define REG_USBHS_DEVEPTIMR0 (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 0 */ +#define REG_USBHS_DEVEPTIMR1 (*(__I uint32_t*)0x400381C4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 1 */ +#define REG_USBHS_DEVEPTIMR2 (*(__I uint32_t*)0x400381C8U) /**< (USBHS) Device Endpoint Interrupt Mask Register 2 */ +#define REG_USBHS_DEVEPTIMR3 (*(__I uint32_t*)0x400381CCU) /**< (USBHS) Device Endpoint Interrupt Mask Register 3 */ +#define REG_USBHS_DEVEPTIMR4 (*(__I uint32_t*)0x400381D0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 4 */ +#define REG_USBHS_DEVEPTIMR5 (*(__I uint32_t*)0x400381D4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 5 */ +#define REG_USBHS_DEVEPTIMR6 (*(__I uint32_t*)0x400381D8U) /**< (USBHS) Device Endpoint Interrupt Mask Register 6 */ +#define REG_USBHS_DEVEPTIMR7 (*(__I uint32_t*)0x400381DCU) /**< (USBHS) Device Endpoint Interrupt Mask Register 7 */ +#define REG_USBHS_DEVEPTIMR8 (*(__I uint32_t*)0x400381E0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 8 */ +#define REG_USBHS_DEVEPTIMR9 (*(__I uint32_t*)0x400381E4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 9 */ +#define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Interrupt Enable Register */ +#define REG_USBHS_DEVEPTIER0 (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Interrupt Enable Register 0 */ +#define REG_USBHS_DEVEPTIER1 (*(__O uint32_t*)0x400381F4U) /**< (USBHS) Device Endpoint Interrupt Enable Register 1 */ +#define REG_USBHS_DEVEPTIER2 (*(__O uint32_t*)0x400381F8U) /**< (USBHS) Device Endpoint Interrupt Enable Register 2 */ +#define REG_USBHS_DEVEPTIER3 (*(__O uint32_t*)0x400381FCU) /**< (USBHS) Device Endpoint Interrupt Enable Register 3 */ +#define REG_USBHS_DEVEPTIER4 (*(__O uint32_t*)0x40038200U) /**< (USBHS) Device Endpoint Interrupt Enable Register 4 */ +#define REG_USBHS_DEVEPTIER5 (*(__O uint32_t*)0x40038204U) /**< (USBHS) Device Endpoint Interrupt Enable Register 5 */ +#define REG_USBHS_DEVEPTIER6 (*(__O uint32_t*)0x40038208U) /**< (USBHS) Device Endpoint Interrupt Enable Register 6 */ +#define REG_USBHS_DEVEPTIER7 (*(__O uint32_t*)0x4003820CU) /**< (USBHS) Device Endpoint Interrupt Enable Register 7 */ +#define REG_USBHS_DEVEPTIER8 (*(__O uint32_t*)0x40038210U) /**< (USBHS) Device Endpoint Interrupt Enable Register 8 */ +#define REG_USBHS_DEVEPTIER9 (*(__O uint32_t*)0x40038214U) /**< (USBHS) Device Endpoint Interrupt Enable Register 9 */ +#define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Interrupt Disable Register */ +#define REG_USBHS_DEVEPTIDR0 (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Interrupt Disable Register 0 */ +#define REG_USBHS_DEVEPTIDR1 (*(__O uint32_t*)0x40038224U) /**< (USBHS) Device Endpoint Interrupt Disable Register 1 */ +#define REG_USBHS_DEVEPTIDR2 (*(__O uint32_t*)0x40038228U) /**< (USBHS) Device Endpoint Interrupt Disable Register 2 */ +#define REG_USBHS_DEVEPTIDR3 (*(__O uint32_t*)0x4003822CU) /**< (USBHS) Device Endpoint Interrupt Disable Register 3 */ +#define REG_USBHS_DEVEPTIDR4 (*(__O uint32_t*)0x40038230U) /**< (USBHS) Device Endpoint Interrupt Disable Register 4 */ +#define REG_USBHS_DEVEPTIDR5 (*(__O uint32_t*)0x40038234U) /**< (USBHS) Device Endpoint Interrupt Disable Register 5 */ +#define REG_USBHS_DEVEPTIDR6 (*(__O uint32_t*)0x40038238U) /**< (USBHS) Device Endpoint Interrupt Disable Register 6 */ +#define REG_USBHS_DEVEPTIDR7 (*(__O uint32_t*)0x4003823CU) /**< (USBHS) Device Endpoint Interrupt Disable Register 7 */ +#define REG_USBHS_DEVEPTIDR8 (*(__O uint32_t*)0x40038240U) /**< (USBHS) Device Endpoint Interrupt Disable Register 8 */ +#define REG_USBHS_DEVEPTIDR9 (*(__O uint32_t*)0x40038244U) /**< (USBHS) Device Endpoint Interrupt Disable Register 9 */ +#define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< (USBHS) Host General Control Register */ +#define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< (USBHS) Host Global Interrupt Status Register */ +#define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< (USBHS) Host Global Interrupt Clear Register */ +#define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< (USBHS) Host Global Interrupt Set Register */ +#define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< (USBHS) Host Global Interrupt Mask Register */ +#define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< (USBHS) Host Global Interrupt Disable Register */ +#define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< (USBHS) Host Global Interrupt Enable Register */ +#define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< (USBHS) Host Pipe Register */ +#define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< (USBHS) Host Frame Number Register */ +#define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< (USBHS) Host Address 1 Register */ +#define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< (USBHS) Host Address 2 Register */ +#define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< (USBHS) Host Address 3 Register */ +#define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register */ +#define REG_USBHS_HSTPIPCFG0 (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register 0 */ +#define REG_USBHS_HSTPIPCFG1 (*(__IO uint32_t*)0x40038504U) /**< (USBHS) Host Pipe Configuration Register 1 */ +#define REG_USBHS_HSTPIPCFG2 (*(__IO uint32_t*)0x40038508U) /**< (USBHS) Host Pipe Configuration Register 2 */ +#define REG_USBHS_HSTPIPCFG3 (*(__IO uint32_t*)0x4003850CU) /**< (USBHS) Host Pipe Configuration Register 3 */ +#define REG_USBHS_HSTPIPCFG4 (*(__IO uint32_t*)0x40038510U) /**< (USBHS) Host Pipe Configuration Register 4 */ +#define REG_USBHS_HSTPIPCFG5 (*(__IO uint32_t*)0x40038514U) /**< (USBHS) Host Pipe Configuration Register 5 */ +#define REG_USBHS_HSTPIPCFG6 (*(__IO uint32_t*)0x40038518U) /**< (USBHS) Host Pipe Configuration Register 6 */ +#define REG_USBHS_HSTPIPCFG7 (*(__IO uint32_t*)0x4003851CU) /**< (USBHS) Host Pipe Configuration Register 7 */ +#define REG_USBHS_HSTPIPCFG8 (*(__IO uint32_t*)0x40038520U) /**< (USBHS) Host Pipe Configuration Register 8 */ +#define REG_USBHS_HSTPIPCFG9 (*(__IO uint32_t*)0x40038524U) /**< (USBHS) Host Pipe Configuration Register 9 */ +#define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register */ +#define REG_USBHS_HSTPIPISR0 (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register 0 */ +#define REG_USBHS_HSTPIPISR1 (*(__I uint32_t*)0x40038534U) /**< (USBHS) Host Pipe Status Register 1 */ +#define REG_USBHS_HSTPIPISR2 (*(__I uint32_t*)0x40038538U) /**< (USBHS) Host Pipe Status Register 2 */ +#define REG_USBHS_HSTPIPISR3 (*(__I uint32_t*)0x4003853CU) /**< (USBHS) Host Pipe Status Register 3 */ +#define REG_USBHS_HSTPIPISR4 (*(__I uint32_t*)0x40038540U) /**< (USBHS) Host Pipe Status Register 4 */ +#define REG_USBHS_HSTPIPISR5 (*(__I uint32_t*)0x40038544U) /**< (USBHS) Host Pipe Status Register 5 */ +#define REG_USBHS_HSTPIPISR6 (*(__I uint32_t*)0x40038548U) /**< (USBHS) Host Pipe Status Register 6 */ +#define REG_USBHS_HSTPIPISR7 (*(__I uint32_t*)0x4003854CU) /**< (USBHS) Host Pipe Status Register 7 */ +#define REG_USBHS_HSTPIPISR8 (*(__I uint32_t*)0x40038550U) /**< (USBHS) Host Pipe Status Register 8 */ +#define REG_USBHS_HSTPIPISR9 (*(__I uint32_t*)0x40038554U) /**< (USBHS) Host Pipe Status Register 9 */ +#define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register */ +#define REG_USBHS_HSTPIPICR0 (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register 0 */ +#define REG_USBHS_HSTPIPICR1 (*(__O uint32_t*)0x40038564U) /**< (USBHS) Host Pipe Clear Register 1 */ +#define REG_USBHS_HSTPIPICR2 (*(__O uint32_t*)0x40038568U) /**< (USBHS) Host Pipe Clear Register 2 */ +#define REG_USBHS_HSTPIPICR3 (*(__O uint32_t*)0x4003856CU) /**< (USBHS) Host Pipe Clear Register 3 */ +#define REG_USBHS_HSTPIPICR4 (*(__O uint32_t*)0x40038570U) /**< (USBHS) Host Pipe Clear Register 4 */ +#define REG_USBHS_HSTPIPICR5 (*(__O uint32_t*)0x40038574U) /**< (USBHS) Host Pipe Clear Register 5 */ +#define REG_USBHS_HSTPIPICR6 (*(__O uint32_t*)0x40038578U) /**< (USBHS) Host Pipe Clear Register 6 */ +#define REG_USBHS_HSTPIPICR7 (*(__O uint32_t*)0x4003857CU) /**< (USBHS) Host Pipe Clear Register 7 */ +#define REG_USBHS_HSTPIPICR8 (*(__O uint32_t*)0x40038580U) /**< (USBHS) Host Pipe Clear Register 8 */ +#define REG_USBHS_HSTPIPICR9 (*(__O uint32_t*)0x40038584U) /**< (USBHS) Host Pipe Clear Register 9 */ +#define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register */ +#define REG_USBHS_HSTPIPIFR0 (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register 0 */ +#define REG_USBHS_HSTPIPIFR1 (*(__O uint32_t*)0x40038594U) /**< (USBHS) Host Pipe Set Register 1 */ +#define REG_USBHS_HSTPIPIFR2 (*(__O uint32_t*)0x40038598U) /**< (USBHS) Host Pipe Set Register 2 */ +#define REG_USBHS_HSTPIPIFR3 (*(__O uint32_t*)0x4003859CU) /**< (USBHS) Host Pipe Set Register 3 */ +#define REG_USBHS_HSTPIPIFR4 (*(__O uint32_t*)0x400385A0U) /**< (USBHS) Host Pipe Set Register 4 */ +#define REG_USBHS_HSTPIPIFR5 (*(__O uint32_t*)0x400385A4U) /**< (USBHS) Host Pipe Set Register 5 */ +#define REG_USBHS_HSTPIPIFR6 (*(__O uint32_t*)0x400385A8U) /**< (USBHS) Host Pipe Set Register 6 */ +#define REG_USBHS_HSTPIPIFR7 (*(__O uint32_t*)0x400385ACU) /**< (USBHS) Host Pipe Set Register 7 */ +#define REG_USBHS_HSTPIPIFR8 (*(__O uint32_t*)0x400385B0U) /**< (USBHS) Host Pipe Set Register 8 */ +#define REG_USBHS_HSTPIPIFR9 (*(__O uint32_t*)0x400385B4U) /**< (USBHS) Host Pipe Set Register 9 */ +#define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register */ +#define REG_USBHS_HSTPIPIMR0 (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register 0 */ +#define REG_USBHS_HSTPIPIMR1 (*(__I uint32_t*)0x400385C4U) /**< (USBHS) Host Pipe Mask Register 1 */ +#define REG_USBHS_HSTPIPIMR2 (*(__I uint32_t*)0x400385C8U) /**< (USBHS) Host Pipe Mask Register 2 */ +#define REG_USBHS_HSTPIPIMR3 (*(__I uint32_t*)0x400385CCU) /**< (USBHS) Host Pipe Mask Register 3 */ +#define REG_USBHS_HSTPIPIMR4 (*(__I uint32_t*)0x400385D0U) /**< (USBHS) Host Pipe Mask Register 4 */ +#define REG_USBHS_HSTPIPIMR5 (*(__I uint32_t*)0x400385D4U) /**< (USBHS) Host Pipe Mask Register 5 */ +#define REG_USBHS_HSTPIPIMR6 (*(__I uint32_t*)0x400385D8U) /**< (USBHS) Host Pipe Mask Register 6 */ +#define REG_USBHS_HSTPIPIMR7 (*(__I uint32_t*)0x400385DCU) /**< (USBHS) Host Pipe Mask Register 7 */ +#define REG_USBHS_HSTPIPIMR8 (*(__I uint32_t*)0x400385E0U) /**< (USBHS) Host Pipe Mask Register 8 */ +#define REG_USBHS_HSTPIPIMR9 (*(__I uint32_t*)0x400385E4U) /**< (USBHS) Host Pipe Mask Register 9 */ +#define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register */ +#define REG_USBHS_HSTPIPIER0 (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register 0 */ +#define REG_USBHS_HSTPIPIER1 (*(__O uint32_t*)0x400385F4U) /**< (USBHS) Host Pipe Enable Register 1 */ +#define REG_USBHS_HSTPIPIER2 (*(__O uint32_t*)0x400385F8U) /**< (USBHS) Host Pipe Enable Register 2 */ +#define REG_USBHS_HSTPIPIER3 (*(__O uint32_t*)0x400385FCU) /**< (USBHS) Host Pipe Enable Register 3 */ +#define REG_USBHS_HSTPIPIER4 (*(__O uint32_t*)0x40038600U) /**< (USBHS) Host Pipe Enable Register 4 */ +#define REG_USBHS_HSTPIPIER5 (*(__O uint32_t*)0x40038604U) /**< (USBHS) Host Pipe Enable Register 5 */ +#define REG_USBHS_HSTPIPIER6 (*(__O uint32_t*)0x40038608U) /**< (USBHS) Host Pipe Enable Register 6 */ +#define REG_USBHS_HSTPIPIER7 (*(__O uint32_t*)0x4003860CU) /**< (USBHS) Host Pipe Enable Register 7 */ +#define REG_USBHS_HSTPIPIER8 (*(__O uint32_t*)0x40038610U) /**< (USBHS) Host Pipe Enable Register 8 */ +#define REG_USBHS_HSTPIPIER9 (*(__O uint32_t*)0x40038614U) /**< (USBHS) Host Pipe Enable Register 9 */ +#define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register */ +#define REG_USBHS_HSTPIPIDR0 (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register 0 */ +#define REG_USBHS_HSTPIPIDR1 (*(__O uint32_t*)0x40038624U) /**< (USBHS) Host Pipe Disable Register 1 */ +#define REG_USBHS_HSTPIPIDR2 (*(__O uint32_t*)0x40038628U) /**< (USBHS) Host Pipe Disable Register 2 */ +#define REG_USBHS_HSTPIPIDR3 (*(__O uint32_t*)0x4003862CU) /**< (USBHS) Host Pipe Disable Register 3 */ +#define REG_USBHS_HSTPIPIDR4 (*(__O uint32_t*)0x40038630U) /**< (USBHS) Host Pipe Disable Register 4 */ +#define REG_USBHS_HSTPIPIDR5 (*(__O uint32_t*)0x40038634U) /**< (USBHS) Host Pipe Disable Register 5 */ +#define REG_USBHS_HSTPIPIDR6 (*(__O uint32_t*)0x40038638U) /**< (USBHS) Host Pipe Disable Register 6 */ +#define REG_USBHS_HSTPIPIDR7 (*(__O uint32_t*)0x4003863CU) /**< (USBHS) Host Pipe Disable Register 7 */ +#define REG_USBHS_HSTPIPIDR8 (*(__O uint32_t*)0x40038640U) /**< (USBHS) Host Pipe Disable Register 8 */ +#define REG_USBHS_HSTPIPIDR9 (*(__O uint32_t*)0x40038644U) /**< (USBHS) Host Pipe Disable Register 9 */ +#define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register */ +#define REG_USBHS_HSTPIPINRQ0 (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register 0 */ +#define REG_USBHS_HSTPIPINRQ1 (*(__IO uint32_t*)0x40038654U) /**< (USBHS) Host Pipe IN Request Register 1 */ +#define REG_USBHS_HSTPIPINRQ2 (*(__IO uint32_t*)0x40038658U) /**< (USBHS) Host Pipe IN Request Register 2 */ +#define REG_USBHS_HSTPIPINRQ3 (*(__IO uint32_t*)0x4003865CU) /**< (USBHS) Host Pipe IN Request Register 3 */ +#define REG_USBHS_HSTPIPINRQ4 (*(__IO uint32_t*)0x40038660U) /**< (USBHS) Host Pipe IN Request Register 4 */ +#define REG_USBHS_HSTPIPINRQ5 (*(__IO uint32_t*)0x40038664U) /**< (USBHS) Host Pipe IN Request Register 5 */ +#define REG_USBHS_HSTPIPINRQ6 (*(__IO uint32_t*)0x40038668U) /**< (USBHS) Host Pipe IN Request Register 6 */ +#define REG_USBHS_HSTPIPINRQ7 (*(__IO uint32_t*)0x4003866CU) /**< (USBHS) Host Pipe IN Request Register 7 */ +#define REG_USBHS_HSTPIPINRQ8 (*(__IO uint32_t*)0x40038670U) /**< (USBHS) Host Pipe IN Request Register 8 */ +#define REG_USBHS_HSTPIPINRQ9 (*(__IO uint32_t*)0x40038674U) /**< (USBHS) Host Pipe IN Request Register 9 */ +#define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register */ +#define REG_USBHS_HSTPIPERR0 (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register 0 */ +#define REG_USBHS_HSTPIPERR1 (*(__IO uint32_t*)0x40038684U) /**< (USBHS) Host Pipe Error Register 1 */ +#define REG_USBHS_HSTPIPERR2 (*(__IO uint32_t*)0x40038688U) /**< (USBHS) Host Pipe Error Register 2 */ +#define REG_USBHS_HSTPIPERR3 (*(__IO uint32_t*)0x4003868CU) /**< (USBHS) Host Pipe Error Register 3 */ +#define REG_USBHS_HSTPIPERR4 (*(__IO uint32_t*)0x40038690U) /**< (USBHS) Host Pipe Error Register 4 */ +#define REG_USBHS_HSTPIPERR5 (*(__IO uint32_t*)0x40038694U) /**< (USBHS) Host Pipe Error Register 5 */ +#define REG_USBHS_HSTPIPERR6 (*(__IO uint32_t*)0x40038698U) /**< (USBHS) Host Pipe Error Register 6 */ +#define REG_USBHS_HSTPIPERR7 (*(__IO uint32_t*)0x4003869CU) /**< (USBHS) Host Pipe Error Register 7 */ +#define REG_USBHS_HSTPIPERR8 (*(__IO uint32_t*)0x400386A0U) /**< (USBHS) Host Pipe Error Register 8 */ +#define REG_USBHS_HSTPIPERR9 (*(__IO uint32_t*)0x400386A4U) /**< (USBHS) Host Pipe Error Register 9 */ +#define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< (USBHS) General Control Register */ +#define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< (USBHS) General Status Register */ +#define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< (USBHS) General Status Clear Register */ +#define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< (USBHS) General Status Set Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for USBHS peripheral ========== */ +#define USBHS_INSTANCE_ID 34 +#define USBHS_CLOCK_ID 34 + +#endif /* _SAME70_USBHS_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/utmi.h b/bsp/microchip/same70/bsp/same70b/include/instance/utmi.h new file mode 100644 index 0000000000..be2320e8ed --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/utmi.h @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Instance description for UTMI + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_UTMI_INSTANCE_H_ +#define _SAME70_UTMI_INSTANCE_H_ + +/* ========== Register definition for UTMI peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_UTMI_OHCIICR (0x400E0410) /**< (UTMI) OHCI Interrupt Configuration Register */ +#define REG_UTMI_CKTRIM (0x400E0430) /**< (UTMI) UTMI Clock Trimming Register */ + +#else + +#define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< (UTMI) OHCI Interrupt Configuration Register */ +#define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< (UTMI) UTMI Clock Trimming Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_UTMI_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/wdt.h b/bsp/microchip/same70/bsp/same70b/include/instance/wdt.h new file mode 100644 index 0000000000..b56202a72c --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/wdt.h @@ -0,0 +1,52 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_WDT_INSTANCE_H_ +#define _SAME70_WDT_INSTANCE_H_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_WDT_CR (0x400E1850) /**< (WDT) Control Register */ +#define REG_WDT_MR (0x400E1854) /**< (WDT) Mode Register */ +#define REG_WDT_SR (0x400E1858) /**< (WDT) Status Register */ + +#else + +#define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< (WDT) Control Register */ +#define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< (WDT) Mode Register */ +#define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< (WDT) Status Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for WDT peripheral ========== */ +#define WDT_INSTANCE_ID 4 + +#endif /* _SAME70_WDT_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/instance/xdmac.h b/bsp/microchip/same70/bsp/same70b/include/instance/xdmac.h new file mode 100644 index 0000000000..fed2e5d154 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/instance/xdmac.h @@ -0,0 +1,753 @@ +/** + * \file + * + * \brief Instance description for XDMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70_XDMAC_INSTANCE_H_ +#define _SAME70_XDMAC_INSTANCE_H_ + +/* ========== Register definition for XDMAC peripheral ========== */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) + +#define REG_XDMAC_CIE0 (0x40078050) /**< (XDMAC) Channel Interrupt Enable Register 0 */ +#define REG_XDMAC_CID0 (0x40078054) /**< (XDMAC) Channel Interrupt Disable Register 0 */ +#define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register 0 */ +#define REG_XDMAC_CIS0 (0x4007805C) /**< (XDMAC) Channel Interrupt Status Register 0 */ +#define REG_XDMAC_CSA0 (0x40078060) /**< (XDMAC) Channel Source Address Register 0 */ +#define REG_XDMAC_CDA0 (0x40078064) /**< (XDMAC) Channel Destination Address Register 0 */ +#define REG_XDMAC_CNDA0 (0x40078068) /**< (XDMAC) Channel Next Descriptor Address Register 0 */ +#define REG_XDMAC_CNDC0 (0x4007806C) /**< (XDMAC) Channel Next Descriptor Control Register 0 */ +#define REG_XDMAC_CUBC0 (0x40078070) /**< (XDMAC) Channel Microblock Control Register 0 */ +#define REG_XDMAC_CBC0 (0x40078074) /**< (XDMAC) Channel Block Control Register 0 */ +#define REG_XDMAC_CC0 (0x40078078) /**< (XDMAC) Channel Configuration Register 0 */ +#define REG_XDMAC_CDS_MSP0 (0x4007807C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */ +#define REG_XDMAC_CSUS0 (0x40078080) /**< (XDMAC) Channel Source Microblock Stride 0 */ +#define REG_XDMAC_CDUS0 (0x40078084) /**< (XDMAC) Channel Destination Microblock Stride 0 */ +#define REG_XDMAC_CIE1 (0x40078090) /**< (XDMAC) Channel Interrupt Enable Register 1 */ +#define REG_XDMAC_CID1 (0x40078094) /**< (XDMAC) Channel Interrupt Disable Register 1 */ +#define REG_XDMAC_CIM1 (0x40078098) /**< (XDMAC) Channel Interrupt Mask Register 1 */ +#define REG_XDMAC_CIS1 (0x4007809C) /**< (XDMAC) Channel Interrupt Status Register 1 */ +#define REG_XDMAC_CSA1 (0x400780A0) /**< (XDMAC) Channel Source Address Register 1 */ +#define REG_XDMAC_CDA1 (0x400780A4) /**< (XDMAC) Channel Destination Address Register 1 */ +#define REG_XDMAC_CNDA1 (0x400780A8) /**< (XDMAC) Channel Next Descriptor Address Register 1 */ +#define REG_XDMAC_CNDC1 (0x400780AC) /**< (XDMAC) Channel Next Descriptor Control Register 1 */ +#define REG_XDMAC_CUBC1 (0x400780B0) /**< (XDMAC) Channel Microblock Control Register 1 */ +#define REG_XDMAC_CBC1 (0x400780B4) /**< (XDMAC) Channel Block Control Register 1 */ +#define REG_XDMAC_CC1 (0x400780B8) /**< (XDMAC) Channel Configuration Register 1 */ +#define REG_XDMAC_CDS_MSP1 (0x400780BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */ +#define REG_XDMAC_CSUS1 (0x400780C0) /**< (XDMAC) Channel Source Microblock Stride 1 */ +#define REG_XDMAC_CDUS1 (0x400780C4) /**< (XDMAC) Channel Destination Microblock Stride 1 */ +#define REG_XDMAC_CIE2 (0x400780D0) /**< (XDMAC) Channel Interrupt Enable Register 2 */ +#define REG_XDMAC_CID2 (0x400780D4) /**< (XDMAC) Channel Interrupt Disable Register 2 */ +#define REG_XDMAC_CIM2 (0x400780D8) /**< (XDMAC) Channel Interrupt Mask Register 2 */ +#define REG_XDMAC_CIS2 (0x400780DC) /**< (XDMAC) Channel Interrupt Status Register 2 */ +#define REG_XDMAC_CSA2 (0x400780E0) /**< (XDMAC) Channel Source Address Register 2 */ +#define REG_XDMAC_CDA2 (0x400780E4) /**< (XDMAC) Channel Destination Address Register 2 */ +#define REG_XDMAC_CNDA2 (0x400780E8) /**< (XDMAC) Channel Next Descriptor Address Register 2 */ +#define REG_XDMAC_CNDC2 (0x400780EC) /**< (XDMAC) Channel Next Descriptor Control Register 2 */ +#define REG_XDMAC_CUBC2 (0x400780F0) /**< (XDMAC) Channel Microblock Control Register 2 */ +#define REG_XDMAC_CBC2 (0x400780F4) /**< (XDMAC) Channel Block Control Register 2 */ +#define REG_XDMAC_CC2 (0x400780F8) /**< (XDMAC) Channel Configuration Register 2 */ +#define REG_XDMAC_CDS_MSP2 (0x400780FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */ +#define REG_XDMAC_CSUS2 (0x40078100) /**< (XDMAC) Channel Source Microblock Stride 2 */ +#define REG_XDMAC_CDUS2 (0x40078104) /**< (XDMAC) Channel Destination Microblock Stride 2 */ +#define REG_XDMAC_CIE3 (0x40078110) /**< (XDMAC) Channel Interrupt Enable Register 3 */ +#define REG_XDMAC_CID3 (0x40078114) /**< (XDMAC) Channel Interrupt Disable Register 3 */ +#define REG_XDMAC_CIM3 (0x40078118) /**< (XDMAC) Channel Interrupt Mask Register 3 */ +#define REG_XDMAC_CIS3 (0x4007811C) /**< (XDMAC) Channel Interrupt Status Register 3 */ +#define REG_XDMAC_CSA3 (0x40078120) /**< (XDMAC) Channel Source Address Register 3 */ +#define REG_XDMAC_CDA3 (0x40078124) /**< (XDMAC) Channel Destination Address Register 3 */ +#define REG_XDMAC_CNDA3 (0x40078128) /**< (XDMAC) Channel Next Descriptor Address Register 3 */ +#define REG_XDMAC_CNDC3 (0x4007812C) /**< (XDMAC) Channel Next Descriptor Control Register 3 */ +#define REG_XDMAC_CUBC3 (0x40078130) /**< (XDMAC) Channel Microblock Control Register 3 */ +#define REG_XDMAC_CBC3 (0x40078134) /**< (XDMAC) Channel Block Control Register 3 */ +#define REG_XDMAC_CC3 (0x40078138) /**< (XDMAC) Channel Configuration Register 3 */ +#define REG_XDMAC_CDS_MSP3 (0x4007813C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */ +#define REG_XDMAC_CSUS3 (0x40078140) /**< (XDMAC) Channel Source Microblock Stride 3 */ +#define REG_XDMAC_CDUS3 (0x40078144) /**< (XDMAC) Channel Destination Microblock Stride 3 */ +#define REG_XDMAC_CIE4 (0x40078150) /**< (XDMAC) Channel Interrupt Enable Register 4 */ +#define REG_XDMAC_CID4 (0x40078154) /**< (XDMAC) Channel Interrupt Disable Register 4 */ +#define REG_XDMAC_CIM4 (0x40078158) /**< (XDMAC) Channel Interrupt Mask Register 4 */ +#define REG_XDMAC_CIS4 (0x4007815C) /**< (XDMAC) Channel Interrupt Status Register 4 */ +#define REG_XDMAC_CSA4 (0x40078160) /**< (XDMAC) Channel Source Address Register 4 */ +#define REG_XDMAC_CDA4 (0x40078164) /**< (XDMAC) Channel Destination Address Register 4 */ +#define REG_XDMAC_CNDA4 (0x40078168) /**< (XDMAC) Channel Next Descriptor Address Register 4 */ +#define REG_XDMAC_CNDC4 (0x4007816C) /**< (XDMAC) Channel Next Descriptor Control Register 4 */ +#define REG_XDMAC_CUBC4 (0x40078170) /**< (XDMAC) Channel Microblock Control Register 4 */ +#define REG_XDMAC_CBC4 (0x40078174) /**< (XDMAC) Channel Block Control Register 4 */ +#define REG_XDMAC_CC4 (0x40078178) /**< (XDMAC) Channel Configuration Register 4 */ +#define REG_XDMAC_CDS_MSP4 (0x4007817C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */ +#define REG_XDMAC_CSUS4 (0x40078180) /**< (XDMAC) Channel Source Microblock Stride 4 */ +#define REG_XDMAC_CDUS4 (0x40078184) /**< (XDMAC) Channel Destination Microblock Stride 4 */ +#define REG_XDMAC_CIE5 (0x40078190) /**< (XDMAC) Channel Interrupt Enable Register 5 */ +#define REG_XDMAC_CID5 (0x40078194) /**< (XDMAC) Channel Interrupt Disable Register 5 */ +#define REG_XDMAC_CIM5 (0x40078198) /**< (XDMAC) Channel Interrupt Mask Register 5 */ +#define REG_XDMAC_CIS5 (0x4007819C) /**< (XDMAC) Channel Interrupt Status Register 5 */ +#define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register 5 */ +#define REG_XDMAC_CDA5 (0x400781A4) /**< (XDMAC) Channel Destination Address Register 5 */ +#define REG_XDMAC_CNDA5 (0x400781A8) /**< (XDMAC) Channel Next Descriptor Address Register 5 */ +#define REG_XDMAC_CNDC5 (0x400781AC) /**< (XDMAC) Channel Next Descriptor Control Register 5 */ +#define REG_XDMAC_CUBC5 (0x400781B0) /**< (XDMAC) Channel Microblock Control Register 5 */ +#define REG_XDMAC_CBC5 (0x400781B4) /**< (XDMAC) Channel Block Control Register 5 */ +#define REG_XDMAC_CC5 (0x400781B8) /**< (XDMAC) Channel Configuration Register 5 */ +#define REG_XDMAC_CDS_MSP5 (0x400781BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */ +#define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride 5 */ +#define REG_XDMAC_CDUS5 (0x400781C4) /**< (XDMAC) Channel Destination Microblock Stride 5 */ +#define REG_XDMAC_CIE6 (0x400781D0) /**< (XDMAC) Channel Interrupt Enable Register 6 */ +#define REG_XDMAC_CID6 (0x400781D4) /**< (XDMAC) Channel Interrupt Disable Register 6 */ +#define REG_XDMAC_CIM6 (0x400781D8) /**< (XDMAC) Channel Interrupt Mask Register 6 */ +#define REG_XDMAC_CIS6 (0x400781DC) /**< (XDMAC) Channel Interrupt Status Register 6 */ +#define REG_XDMAC_CSA6 (0x400781E0) /**< (XDMAC) Channel Source Address Register 6 */ +#define REG_XDMAC_CDA6 (0x400781E4) /**< (XDMAC) Channel Destination Address Register 6 */ +#define REG_XDMAC_CNDA6 (0x400781E8) /**< (XDMAC) Channel Next Descriptor Address Register 6 */ +#define REG_XDMAC_CNDC6 (0x400781EC) /**< (XDMAC) Channel Next Descriptor Control Register 6 */ +#define REG_XDMAC_CUBC6 (0x400781F0) /**< (XDMAC) Channel Microblock Control Register 6 */ +#define REG_XDMAC_CBC6 (0x400781F4) /**< (XDMAC) Channel Block Control Register 6 */ +#define REG_XDMAC_CC6 (0x400781F8) /**< (XDMAC) Channel Configuration Register 6 */ +#define REG_XDMAC_CDS_MSP6 (0x400781FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */ +#define REG_XDMAC_CSUS6 (0x40078200) /**< (XDMAC) Channel Source Microblock Stride 6 */ +#define REG_XDMAC_CDUS6 (0x40078204) /**< (XDMAC) Channel Destination Microblock Stride 6 */ +#define REG_XDMAC_CIE7 (0x40078210) /**< (XDMAC) Channel Interrupt Enable Register 7 */ +#define REG_XDMAC_CID7 (0x40078214) /**< (XDMAC) Channel Interrupt Disable Register 7 */ +#define REG_XDMAC_CIM7 (0x40078218) /**< (XDMAC) Channel Interrupt Mask Register 7 */ +#define REG_XDMAC_CIS7 (0x4007821C) /**< (XDMAC) Channel Interrupt Status Register 7 */ +#define REG_XDMAC_CSA7 (0x40078220) /**< (XDMAC) Channel Source Address Register 7 */ +#define REG_XDMAC_CDA7 (0x40078224) /**< (XDMAC) Channel Destination Address Register 7 */ +#define REG_XDMAC_CNDA7 (0x40078228) /**< (XDMAC) Channel Next Descriptor Address Register 7 */ +#define REG_XDMAC_CNDC7 (0x4007822C) /**< (XDMAC) Channel Next Descriptor Control Register 7 */ +#define REG_XDMAC_CUBC7 (0x40078230) /**< (XDMAC) Channel Microblock Control Register 7 */ +#define REG_XDMAC_CBC7 (0x40078234) /**< (XDMAC) Channel Block Control Register 7 */ +#define REG_XDMAC_CC7 (0x40078238) /**< (XDMAC) Channel Configuration Register 7 */ +#define REG_XDMAC_CDS_MSP7 (0x4007823C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */ +#define REG_XDMAC_CSUS7 (0x40078240) /**< (XDMAC) Channel Source Microblock Stride 7 */ +#define REG_XDMAC_CDUS7 (0x40078244) /**< (XDMAC) Channel Destination Microblock Stride 7 */ +#define REG_XDMAC_CIE8 (0x40078250) /**< (XDMAC) Channel Interrupt Enable Register 8 */ +#define REG_XDMAC_CID8 (0x40078254) /**< (XDMAC) Channel Interrupt Disable Register 8 */ +#define REG_XDMAC_CIM8 (0x40078258) /**< (XDMAC) Channel Interrupt Mask Register 8 */ +#define REG_XDMAC_CIS8 (0x4007825C) /**< (XDMAC) Channel Interrupt Status Register 8 */ +#define REG_XDMAC_CSA8 (0x40078260) /**< (XDMAC) Channel Source Address Register 8 */ +#define REG_XDMAC_CDA8 (0x40078264) /**< (XDMAC) Channel Destination Address Register 8 */ +#define REG_XDMAC_CNDA8 (0x40078268) /**< (XDMAC) Channel Next Descriptor Address Register 8 */ +#define REG_XDMAC_CNDC8 (0x4007826C) /**< (XDMAC) Channel Next Descriptor Control Register 8 */ +#define REG_XDMAC_CUBC8 (0x40078270) /**< (XDMAC) Channel Microblock Control Register 8 */ +#define REG_XDMAC_CBC8 (0x40078274) /**< (XDMAC) Channel Block Control Register 8 */ +#define REG_XDMAC_CC8 (0x40078278) /**< (XDMAC) Channel Configuration Register 8 */ +#define REG_XDMAC_CDS_MSP8 (0x4007827C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */ +#define REG_XDMAC_CSUS8 (0x40078280) /**< (XDMAC) Channel Source Microblock Stride 8 */ +#define REG_XDMAC_CDUS8 (0x40078284) /**< (XDMAC) Channel Destination Microblock Stride 8 */ +#define REG_XDMAC_CIE9 (0x40078290) /**< (XDMAC) Channel Interrupt Enable Register 9 */ +#define REG_XDMAC_CID9 (0x40078294) /**< (XDMAC) Channel Interrupt Disable Register 9 */ +#define REG_XDMAC_CIM9 (0x40078298) /**< (XDMAC) Channel Interrupt Mask Register 9 */ +#define REG_XDMAC_CIS9 (0x4007829C) /**< (XDMAC) Channel Interrupt Status Register 9 */ +#define REG_XDMAC_CSA9 (0x400782A0) /**< (XDMAC) Channel Source Address Register 9 */ +#define REG_XDMAC_CDA9 (0x400782A4) /**< (XDMAC) Channel Destination Address Register 9 */ +#define REG_XDMAC_CNDA9 (0x400782A8) /**< (XDMAC) Channel Next Descriptor Address Register 9 */ +#define REG_XDMAC_CNDC9 (0x400782AC) /**< (XDMAC) Channel Next Descriptor Control Register 9 */ +#define REG_XDMAC_CUBC9 (0x400782B0) /**< (XDMAC) Channel Microblock Control Register 9 */ +#define REG_XDMAC_CBC9 (0x400782B4) /**< (XDMAC) Channel Block Control Register 9 */ +#define REG_XDMAC_CC9 (0x400782B8) /**< (XDMAC) Channel Configuration Register 9 */ +#define REG_XDMAC_CDS_MSP9 (0x400782BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */ +#define REG_XDMAC_CSUS9 (0x400782C0) /**< (XDMAC) Channel Source Microblock Stride 9 */ +#define REG_XDMAC_CDUS9 (0x400782C4) /**< (XDMAC) Channel Destination Microblock Stride 9 */ +#define REG_XDMAC_CIE10 (0x400782D0) /**< (XDMAC) Channel Interrupt Enable Register 10 */ +#define REG_XDMAC_CID10 (0x400782D4) /**< (XDMAC) Channel Interrupt Disable Register 10 */ +#define REG_XDMAC_CIM10 (0x400782D8) /**< (XDMAC) Channel Interrupt Mask Register 10 */ +#define REG_XDMAC_CIS10 (0x400782DC) /**< (XDMAC) Channel Interrupt Status Register 10 */ +#define REG_XDMAC_CSA10 (0x400782E0) /**< (XDMAC) Channel Source Address Register 10 */ +#define REG_XDMAC_CDA10 (0x400782E4) /**< (XDMAC) Channel Destination Address Register 10 */ +#define REG_XDMAC_CNDA10 (0x400782E8) /**< (XDMAC) Channel Next Descriptor Address Register 10 */ +#define REG_XDMAC_CNDC10 (0x400782EC) /**< (XDMAC) Channel Next Descriptor Control Register 10 */ +#define REG_XDMAC_CUBC10 (0x400782F0) /**< (XDMAC) Channel Microblock Control Register 10 */ +#define REG_XDMAC_CBC10 (0x400782F4) /**< (XDMAC) Channel Block Control Register 10 */ +#define REG_XDMAC_CC10 (0x400782F8) /**< (XDMAC) Channel Configuration Register 10 */ +#define REG_XDMAC_CDS_MSP10 (0x400782FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */ +#define REG_XDMAC_CSUS10 (0x40078300) /**< (XDMAC) Channel Source Microblock Stride 10 */ +#define REG_XDMAC_CDUS10 (0x40078304) /**< (XDMAC) Channel Destination Microblock Stride 10 */ +#define REG_XDMAC_CIE11 (0x40078310) /**< (XDMAC) Channel Interrupt Enable Register 11 */ +#define REG_XDMAC_CID11 (0x40078314) /**< (XDMAC) Channel Interrupt Disable Register 11 */ +#define REG_XDMAC_CIM11 (0x40078318) /**< (XDMAC) Channel Interrupt Mask Register 11 */ +#define REG_XDMAC_CIS11 (0x4007831C) /**< (XDMAC) Channel Interrupt Status Register 11 */ +#define REG_XDMAC_CSA11 (0x40078320) /**< (XDMAC) Channel Source Address Register 11 */ +#define REG_XDMAC_CDA11 (0x40078324) /**< (XDMAC) Channel Destination Address Register 11 */ +#define REG_XDMAC_CNDA11 (0x40078328) /**< (XDMAC) Channel Next Descriptor Address Register 11 */ +#define REG_XDMAC_CNDC11 (0x4007832C) /**< (XDMAC) Channel Next Descriptor Control Register 11 */ +#define REG_XDMAC_CUBC11 (0x40078330) /**< (XDMAC) Channel Microblock Control Register 11 */ +#define REG_XDMAC_CBC11 (0x40078334) /**< (XDMAC) Channel Block Control Register 11 */ +#define REG_XDMAC_CC11 (0x40078338) /**< (XDMAC) Channel Configuration Register 11 */ +#define REG_XDMAC_CDS_MSP11 (0x4007833C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */ +#define REG_XDMAC_CSUS11 (0x40078340) /**< (XDMAC) Channel Source Microblock Stride 11 */ +#define REG_XDMAC_CDUS11 (0x40078344) /**< (XDMAC) Channel Destination Microblock Stride 11 */ +#define REG_XDMAC_CIE12 (0x40078350) /**< (XDMAC) Channel Interrupt Enable Register 12 */ +#define REG_XDMAC_CID12 (0x40078354) /**< (XDMAC) Channel Interrupt Disable Register 12 */ +#define REG_XDMAC_CIM12 (0x40078358) /**< (XDMAC) Channel Interrupt Mask Register 12 */ +#define REG_XDMAC_CIS12 (0x4007835C) /**< (XDMAC) Channel Interrupt Status Register 12 */ +#define REG_XDMAC_CSA12 (0x40078360) /**< (XDMAC) Channel Source Address Register 12 */ +#define REG_XDMAC_CDA12 (0x40078364) /**< (XDMAC) Channel Destination Address Register 12 */ +#define REG_XDMAC_CNDA12 (0x40078368) /**< (XDMAC) Channel Next Descriptor Address Register 12 */ +#define REG_XDMAC_CNDC12 (0x4007836C) /**< (XDMAC) Channel Next Descriptor Control Register 12 */ +#define REG_XDMAC_CUBC12 (0x40078370) /**< (XDMAC) Channel Microblock Control Register 12 */ +#define REG_XDMAC_CBC12 (0x40078374) /**< (XDMAC) Channel Block Control Register 12 */ +#define REG_XDMAC_CC12 (0x40078378) /**< (XDMAC) Channel Configuration Register 12 */ +#define REG_XDMAC_CDS_MSP12 (0x4007837C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */ +#define REG_XDMAC_CSUS12 (0x40078380) /**< (XDMAC) Channel Source Microblock Stride 12 */ +#define REG_XDMAC_CDUS12 (0x40078384) /**< (XDMAC) Channel Destination Microblock Stride 12 */ +#define REG_XDMAC_CIE13 (0x40078390) /**< (XDMAC) Channel Interrupt Enable Register 13 */ +#define REG_XDMAC_CID13 (0x40078394) /**< (XDMAC) Channel Interrupt Disable Register 13 */ +#define REG_XDMAC_CIM13 (0x40078398) /**< (XDMAC) Channel Interrupt Mask Register 13 */ +#define REG_XDMAC_CIS13 (0x4007839C) /**< (XDMAC) Channel Interrupt Status Register 13 */ +#define REG_XDMAC_CSA13 (0x400783A0) /**< (XDMAC) Channel Source Address Register 13 */ +#define REG_XDMAC_CDA13 (0x400783A4) /**< (XDMAC) Channel Destination Address Register 13 */ +#define REG_XDMAC_CNDA13 (0x400783A8) /**< (XDMAC) Channel Next Descriptor Address Register 13 */ +#define REG_XDMAC_CNDC13 (0x400783AC) /**< (XDMAC) Channel Next Descriptor Control Register 13 */ +#define REG_XDMAC_CUBC13 (0x400783B0) /**< (XDMAC) Channel Microblock Control Register 13 */ +#define REG_XDMAC_CBC13 (0x400783B4) /**< (XDMAC) Channel Block Control Register 13 */ +#define REG_XDMAC_CC13 (0x400783B8) /**< (XDMAC) Channel Configuration Register 13 */ +#define REG_XDMAC_CDS_MSP13 (0x400783BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */ +#define REG_XDMAC_CSUS13 (0x400783C0) /**< (XDMAC) Channel Source Microblock Stride 13 */ +#define REG_XDMAC_CDUS13 (0x400783C4) /**< (XDMAC) Channel Destination Microblock Stride 13 */ +#define REG_XDMAC_CIE14 (0x400783D0) /**< (XDMAC) Channel Interrupt Enable Register 14 */ +#define REG_XDMAC_CID14 (0x400783D4) /**< (XDMAC) Channel Interrupt Disable Register 14 */ +#define REG_XDMAC_CIM14 (0x400783D8) /**< (XDMAC) Channel Interrupt Mask Register 14 */ +#define REG_XDMAC_CIS14 (0x400783DC) /**< (XDMAC) Channel Interrupt Status Register 14 */ +#define REG_XDMAC_CSA14 (0x400783E0) /**< (XDMAC) Channel Source Address Register 14 */ +#define REG_XDMAC_CDA14 (0x400783E4) /**< (XDMAC) Channel Destination Address Register 14 */ +#define REG_XDMAC_CNDA14 (0x400783E8) /**< (XDMAC) Channel Next Descriptor Address Register 14 */ +#define REG_XDMAC_CNDC14 (0x400783EC) /**< (XDMAC) Channel Next Descriptor Control Register 14 */ +#define REG_XDMAC_CUBC14 (0x400783F0) /**< (XDMAC) Channel Microblock Control Register 14 */ +#define REG_XDMAC_CBC14 (0x400783F4) /**< (XDMAC) Channel Block Control Register 14 */ +#define REG_XDMAC_CC14 (0x400783F8) /**< (XDMAC) Channel Configuration Register 14 */ +#define REG_XDMAC_CDS_MSP14 (0x400783FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */ +#define REG_XDMAC_CSUS14 (0x40078400) /**< (XDMAC) Channel Source Microblock Stride 14 */ +#define REG_XDMAC_CDUS14 (0x40078404) /**< (XDMAC) Channel Destination Microblock Stride 14 */ +#define REG_XDMAC_CIE15 (0x40078410) /**< (XDMAC) Channel Interrupt Enable Register 15 */ +#define REG_XDMAC_CID15 (0x40078414) /**< (XDMAC) Channel Interrupt Disable Register 15 */ +#define REG_XDMAC_CIM15 (0x40078418) /**< (XDMAC) Channel Interrupt Mask Register 15 */ +#define REG_XDMAC_CIS15 (0x4007841C) /**< (XDMAC) Channel Interrupt Status Register 15 */ +#define REG_XDMAC_CSA15 (0x40078420) /**< (XDMAC) Channel Source Address Register 15 */ +#define REG_XDMAC_CDA15 (0x40078424) /**< (XDMAC) Channel Destination Address Register 15 */ +#define REG_XDMAC_CNDA15 (0x40078428) /**< (XDMAC) Channel Next Descriptor Address Register 15 */ +#define REG_XDMAC_CNDC15 (0x4007842C) /**< (XDMAC) Channel Next Descriptor Control Register 15 */ +#define REG_XDMAC_CUBC15 (0x40078430) /**< (XDMAC) Channel Microblock Control Register 15 */ +#define REG_XDMAC_CBC15 (0x40078434) /**< (XDMAC) Channel Block Control Register 15 */ +#define REG_XDMAC_CC15 (0x40078438) /**< (XDMAC) Channel Configuration Register 15 */ +#define REG_XDMAC_CDS_MSP15 (0x4007843C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */ +#define REG_XDMAC_CSUS15 (0x40078440) /**< (XDMAC) Channel Source Microblock Stride 15 */ +#define REG_XDMAC_CDUS15 (0x40078444) /**< (XDMAC) Channel Destination Microblock Stride 15 */ +#define REG_XDMAC_CIE16 (0x40078450) /**< (XDMAC) Channel Interrupt Enable Register 16 */ +#define REG_XDMAC_CID16 (0x40078454) /**< (XDMAC) Channel Interrupt Disable Register 16 */ +#define REG_XDMAC_CIM16 (0x40078458) /**< (XDMAC) Channel Interrupt Mask Register 16 */ +#define REG_XDMAC_CIS16 (0x4007845C) /**< (XDMAC) Channel Interrupt Status Register 16 */ +#define REG_XDMAC_CSA16 (0x40078460) /**< (XDMAC) Channel Source Address Register 16 */ +#define REG_XDMAC_CDA16 (0x40078464) /**< (XDMAC) Channel Destination Address Register 16 */ +#define REG_XDMAC_CNDA16 (0x40078468) /**< (XDMAC) Channel Next Descriptor Address Register 16 */ +#define REG_XDMAC_CNDC16 (0x4007846C) /**< (XDMAC) Channel Next Descriptor Control Register 16 */ +#define REG_XDMAC_CUBC16 (0x40078470) /**< (XDMAC) Channel Microblock Control Register 16 */ +#define REG_XDMAC_CBC16 (0x40078474) /**< (XDMAC) Channel Block Control Register 16 */ +#define REG_XDMAC_CC16 (0x40078478) /**< (XDMAC) Channel Configuration Register 16 */ +#define REG_XDMAC_CDS_MSP16 (0x4007847C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */ +#define REG_XDMAC_CSUS16 (0x40078480) /**< (XDMAC) Channel Source Microblock Stride 16 */ +#define REG_XDMAC_CDUS16 (0x40078484) /**< (XDMAC) Channel Destination Microblock Stride 16 */ +#define REG_XDMAC_CIE17 (0x40078490) /**< (XDMAC) Channel Interrupt Enable Register 17 */ +#define REG_XDMAC_CID17 (0x40078494) /**< (XDMAC) Channel Interrupt Disable Register 17 */ +#define REG_XDMAC_CIM17 (0x40078498) /**< (XDMAC) Channel Interrupt Mask Register 17 */ +#define REG_XDMAC_CIS17 (0x4007849C) /**< (XDMAC) Channel Interrupt Status Register 17 */ +#define REG_XDMAC_CSA17 (0x400784A0) /**< (XDMAC) Channel Source Address Register 17 */ +#define REG_XDMAC_CDA17 (0x400784A4) /**< (XDMAC) Channel Destination Address Register 17 */ +#define REG_XDMAC_CNDA17 (0x400784A8) /**< (XDMAC) Channel Next Descriptor Address Register 17 */ +#define REG_XDMAC_CNDC17 (0x400784AC) /**< (XDMAC) Channel Next Descriptor Control Register 17 */ +#define REG_XDMAC_CUBC17 (0x400784B0) /**< (XDMAC) Channel Microblock Control Register 17 */ +#define REG_XDMAC_CBC17 (0x400784B4) /**< (XDMAC) Channel Block Control Register 17 */ +#define REG_XDMAC_CC17 (0x400784B8) /**< (XDMAC) Channel Configuration Register 17 */ +#define REG_XDMAC_CDS_MSP17 (0x400784BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */ +#define REG_XDMAC_CSUS17 (0x400784C0) /**< (XDMAC) Channel Source Microblock Stride 17 */ +#define REG_XDMAC_CDUS17 (0x400784C4) /**< (XDMAC) Channel Destination Microblock Stride 17 */ +#define REG_XDMAC_CIE18 (0x400784D0) /**< (XDMAC) Channel Interrupt Enable Register 18 */ +#define REG_XDMAC_CID18 (0x400784D4) /**< (XDMAC) Channel Interrupt Disable Register 18 */ +#define REG_XDMAC_CIM18 (0x400784D8) /**< (XDMAC) Channel Interrupt Mask Register 18 */ +#define REG_XDMAC_CIS18 (0x400784DC) /**< (XDMAC) Channel Interrupt Status Register 18 */ +#define REG_XDMAC_CSA18 (0x400784E0) /**< (XDMAC) Channel Source Address Register 18 */ +#define REG_XDMAC_CDA18 (0x400784E4) /**< (XDMAC) Channel Destination Address Register 18 */ +#define REG_XDMAC_CNDA18 (0x400784E8) /**< (XDMAC) Channel Next Descriptor Address Register 18 */ +#define REG_XDMAC_CNDC18 (0x400784EC) /**< (XDMAC) Channel Next Descriptor Control Register 18 */ +#define REG_XDMAC_CUBC18 (0x400784F0) /**< (XDMAC) Channel Microblock Control Register 18 */ +#define REG_XDMAC_CBC18 (0x400784F4) /**< (XDMAC) Channel Block Control Register 18 */ +#define REG_XDMAC_CC18 (0x400784F8) /**< (XDMAC) Channel Configuration Register 18 */ +#define REG_XDMAC_CDS_MSP18 (0x400784FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */ +#define REG_XDMAC_CSUS18 (0x40078500) /**< (XDMAC) Channel Source Microblock Stride 18 */ +#define REG_XDMAC_CDUS18 (0x40078504) /**< (XDMAC) Channel Destination Microblock Stride 18 */ +#define REG_XDMAC_CIE19 (0x40078510) /**< (XDMAC) Channel Interrupt Enable Register 19 */ +#define REG_XDMAC_CID19 (0x40078514) /**< (XDMAC) Channel Interrupt Disable Register 19 */ +#define REG_XDMAC_CIM19 (0x40078518) /**< (XDMAC) Channel Interrupt Mask Register 19 */ +#define REG_XDMAC_CIS19 (0x4007851C) /**< (XDMAC) Channel Interrupt Status Register 19 */ +#define REG_XDMAC_CSA19 (0x40078520) /**< (XDMAC) Channel Source Address Register 19 */ +#define REG_XDMAC_CDA19 (0x40078524) /**< (XDMAC) Channel Destination Address Register 19 */ +#define REG_XDMAC_CNDA19 (0x40078528) /**< (XDMAC) Channel Next Descriptor Address Register 19 */ +#define REG_XDMAC_CNDC19 (0x4007852C) /**< (XDMAC) Channel Next Descriptor Control Register 19 */ +#define REG_XDMAC_CUBC19 (0x40078530) /**< (XDMAC) Channel Microblock Control Register 19 */ +#define REG_XDMAC_CBC19 (0x40078534) /**< (XDMAC) Channel Block Control Register 19 */ +#define REG_XDMAC_CC19 (0x40078538) /**< (XDMAC) Channel Configuration Register 19 */ +#define REG_XDMAC_CDS_MSP19 (0x4007853C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */ +#define REG_XDMAC_CSUS19 (0x40078540) /**< (XDMAC) Channel Source Microblock Stride 19 */ +#define REG_XDMAC_CDUS19 (0x40078544) /**< (XDMAC) Channel Destination Microblock Stride 19 */ +#define REG_XDMAC_CIE20 (0x40078550) /**< (XDMAC) Channel Interrupt Enable Register 20 */ +#define REG_XDMAC_CID20 (0x40078554) /**< (XDMAC) Channel Interrupt Disable Register 20 */ +#define REG_XDMAC_CIM20 (0x40078558) /**< (XDMAC) Channel Interrupt Mask Register 20 */ +#define REG_XDMAC_CIS20 (0x4007855C) /**< (XDMAC) Channel Interrupt Status Register 20 */ +#define REG_XDMAC_CSA20 (0x40078560) /**< (XDMAC) Channel Source Address Register 20 */ +#define REG_XDMAC_CDA20 (0x40078564) /**< (XDMAC) Channel Destination Address Register 20 */ +#define REG_XDMAC_CNDA20 (0x40078568) /**< (XDMAC) Channel Next Descriptor Address Register 20 */ +#define REG_XDMAC_CNDC20 (0x4007856C) /**< (XDMAC) Channel Next Descriptor Control Register 20 */ +#define REG_XDMAC_CUBC20 (0x40078570) /**< (XDMAC) Channel Microblock Control Register 20 */ +#define REG_XDMAC_CBC20 (0x40078574) /**< (XDMAC) Channel Block Control Register 20 */ +#define REG_XDMAC_CC20 (0x40078578) /**< (XDMAC) Channel Configuration Register 20 */ +#define REG_XDMAC_CDS_MSP20 (0x4007857C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */ +#define REG_XDMAC_CSUS20 (0x40078580) /**< (XDMAC) Channel Source Microblock Stride 20 */ +#define REG_XDMAC_CDUS20 (0x40078584) /**< (XDMAC) Channel Destination Microblock Stride 20 */ +#define REG_XDMAC_CIE21 (0x40078590) /**< (XDMAC) Channel Interrupt Enable Register 21 */ +#define REG_XDMAC_CID21 (0x40078594) /**< (XDMAC) Channel Interrupt Disable Register 21 */ +#define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register 21 */ +#define REG_XDMAC_CIS21 (0x4007859C) /**< (XDMAC) Channel Interrupt Status Register 21 */ +#define REG_XDMAC_CSA21 (0x400785A0) /**< (XDMAC) Channel Source Address Register 21 */ +#define REG_XDMAC_CDA21 (0x400785A4) /**< (XDMAC) Channel Destination Address Register 21 */ +#define REG_XDMAC_CNDA21 (0x400785A8) /**< (XDMAC) Channel Next Descriptor Address Register 21 */ +#define REG_XDMAC_CNDC21 (0x400785AC) /**< (XDMAC) Channel Next Descriptor Control Register 21 */ +#define REG_XDMAC_CUBC21 (0x400785B0) /**< (XDMAC) Channel Microblock Control Register 21 */ +#define REG_XDMAC_CBC21 (0x400785B4) /**< (XDMAC) Channel Block Control Register 21 */ +#define REG_XDMAC_CC21 (0x400785B8) /**< (XDMAC) Channel Configuration Register 21 */ +#define REG_XDMAC_CDS_MSP21 (0x400785BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */ +#define REG_XDMAC_CSUS21 (0x400785C0) /**< (XDMAC) Channel Source Microblock Stride 21 */ +#define REG_XDMAC_CDUS21 (0x400785C4) /**< (XDMAC) Channel Destination Microblock Stride 21 */ +#define REG_XDMAC_CIE22 (0x400785D0) /**< (XDMAC) Channel Interrupt Enable Register 22 */ +#define REG_XDMAC_CID22 (0x400785D4) /**< (XDMAC) Channel Interrupt Disable Register 22 */ +#define REG_XDMAC_CIM22 (0x400785D8) /**< (XDMAC) Channel Interrupt Mask Register 22 */ +#define REG_XDMAC_CIS22 (0x400785DC) /**< (XDMAC) Channel Interrupt Status Register 22 */ +#define REG_XDMAC_CSA22 (0x400785E0) /**< (XDMAC) Channel Source Address Register 22 */ +#define REG_XDMAC_CDA22 (0x400785E4) /**< (XDMAC) Channel Destination Address Register 22 */ +#define REG_XDMAC_CNDA22 (0x400785E8) /**< (XDMAC) Channel Next Descriptor Address Register 22 */ +#define REG_XDMAC_CNDC22 (0x400785EC) /**< (XDMAC) Channel Next Descriptor Control Register 22 */ +#define REG_XDMAC_CUBC22 (0x400785F0) /**< (XDMAC) Channel Microblock Control Register 22 */ +#define REG_XDMAC_CBC22 (0x400785F4) /**< (XDMAC) Channel Block Control Register 22 */ +#define REG_XDMAC_CC22 (0x400785F8) /**< (XDMAC) Channel Configuration Register 22 */ +#define REG_XDMAC_CDS_MSP22 (0x400785FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */ +#define REG_XDMAC_CSUS22 (0x40078600) /**< (XDMAC) Channel Source Microblock Stride 22 */ +#define REG_XDMAC_CDUS22 (0x40078604) /**< (XDMAC) Channel Destination Microblock Stride 22 */ +#define REG_XDMAC_CIE23 (0x40078610) /**< (XDMAC) Channel Interrupt Enable Register 23 */ +#define REG_XDMAC_CID23 (0x40078614) /**< (XDMAC) Channel Interrupt Disable Register 23 */ +#define REG_XDMAC_CIM23 (0x40078618) /**< (XDMAC) Channel Interrupt Mask Register 23 */ +#define REG_XDMAC_CIS23 (0x4007861C) /**< (XDMAC) Channel Interrupt Status Register 23 */ +#define REG_XDMAC_CSA23 (0x40078620) /**< (XDMAC) Channel Source Address Register 23 */ +#define REG_XDMAC_CDA23 (0x40078624) /**< (XDMAC) Channel Destination Address Register 23 */ +#define REG_XDMAC_CNDA23 (0x40078628) /**< (XDMAC) Channel Next Descriptor Address Register 23 */ +#define REG_XDMAC_CNDC23 (0x4007862C) /**< (XDMAC) Channel Next Descriptor Control Register 23 */ +#define REG_XDMAC_CUBC23 (0x40078630) /**< (XDMAC) Channel Microblock Control Register 23 */ +#define REG_XDMAC_CBC23 (0x40078634) /**< (XDMAC) Channel Block Control Register 23 */ +#define REG_XDMAC_CC23 (0x40078638) /**< (XDMAC) Channel Configuration Register 23 */ +#define REG_XDMAC_CDS_MSP23 (0x4007863C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */ +#define REG_XDMAC_CSUS23 (0x40078640) /**< (XDMAC) Channel Source Microblock Stride 23 */ +#define REG_XDMAC_CDUS23 (0x40078644) /**< (XDMAC) Channel Destination Microblock Stride 23 */ +#define REG_XDMAC_GTYPE (0x40078000) /**< (XDMAC) Global Type Register */ +#define REG_XDMAC_GCFG (0x40078004) /**< (XDMAC) Global Configuration Register */ +#define REG_XDMAC_GWAC (0x40078008) /**< (XDMAC) Global Weighted Arbiter Configuration Register */ +#define REG_XDMAC_GIE (0x4007800C) /**< (XDMAC) Global Interrupt Enable Register */ +#define REG_XDMAC_GID (0x40078010) /**< (XDMAC) Global Interrupt Disable Register */ +#define REG_XDMAC_GIM (0x40078014) /**< (XDMAC) Global Interrupt Mask Register */ +#define REG_XDMAC_GIS (0x40078018) /**< (XDMAC) Global Interrupt Status Register */ +#define REG_XDMAC_GE (0x4007801C) /**< (XDMAC) Global Channel Enable Register */ +#define REG_XDMAC_GD (0x40078020) /**< (XDMAC) Global Channel Disable Register */ +#define REG_XDMAC_GS (0x40078024) /**< (XDMAC) Global Channel Status Register */ +#define REG_XDMAC_GRS (0x40078028) /**< (XDMAC) Global Channel Read Suspend Register */ +#define REG_XDMAC_GWS (0x4007802C) /**< (XDMAC) Global Channel Write Suspend Register */ +#define REG_XDMAC_GRWS (0x40078030) /**< (XDMAC) Global Channel Read Write Suspend Register */ +#define REG_XDMAC_GRWR (0x40078034) /**< (XDMAC) Global Channel Read Write Resume Register */ +#define REG_XDMAC_GSWR (0x40078038) /**< (XDMAC) Global Channel Software Request Register */ +#define REG_XDMAC_GSWS (0x4007803C) /**< (XDMAC) Global Channel Software Request Status Register */ +#define REG_XDMAC_GSWF (0x40078040) /**< (XDMAC) Global Channel Software Flush Request Register */ + +#else + +#define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< (XDMAC) Channel Interrupt Enable Register 0 */ +#define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< (XDMAC) Channel Interrupt Disable Register 0 */ +#define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask Register 0 */ +#define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< (XDMAC) Channel Interrupt Status Register 0 */ +#define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< (XDMAC) Channel Source Address Register 0 */ +#define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< (XDMAC) Channel Destination Address Register 0 */ +#define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< (XDMAC) Channel Next Descriptor Address Register 0 */ +#define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< (XDMAC) Channel Next Descriptor Control Register 0 */ +#define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< (XDMAC) Channel Microblock Control Register 0 */ +#define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< (XDMAC) Channel Block Control Register 0 */ +#define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< (XDMAC) Channel Configuration Register 0 */ +#define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */ +#define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< (XDMAC) Channel Source Microblock Stride 0 */ +#define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< (XDMAC) Channel Destination Microblock Stride 0 */ +#define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< (XDMAC) Channel Interrupt Enable Register 1 */ +#define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< (XDMAC) Channel Interrupt Disable Register 1 */ +#define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< (XDMAC) Channel Interrupt Mask Register 1 */ +#define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< (XDMAC) Channel Interrupt Status Register 1 */ +#define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< (XDMAC) Channel Source Address Register 1 */ +#define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< (XDMAC) Channel Destination Address Register 1 */ +#define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< (XDMAC) Channel Next Descriptor Address Register 1 */ +#define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< (XDMAC) Channel Next Descriptor Control Register 1 */ +#define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< (XDMAC) Channel Microblock Control Register 1 */ +#define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< (XDMAC) Channel Block Control Register 1 */ +#define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< (XDMAC) Channel Configuration Register 1 */ +#define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */ +#define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< (XDMAC) Channel Source Microblock Stride 1 */ +#define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< (XDMAC) Channel Destination Microblock Stride 1 */ +#define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< (XDMAC) Channel Interrupt Enable Register 2 */ +#define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< (XDMAC) Channel Interrupt Disable Register 2 */ +#define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< (XDMAC) Channel Interrupt Mask Register 2 */ +#define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< (XDMAC) Channel Interrupt Status Register 2 */ +#define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< (XDMAC) Channel Source Address Register 2 */ +#define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< (XDMAC) Channel Destination Address Register 2 */ +#define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< (XDMAC) Channel Next Descriptor Address Register 2 */ +#define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< (XDMAC) Channel Next Descriptor Control Register 2 */ +#define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< (XDMAC) Channel Microblock Control Register 2 */ +#define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< (XDMAC) Channel Block Control Register 2 */ +#define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< (XDMAC) Channel Configuration Register 2 */ +#define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */ +#define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< (XDMAC) Channel Source Microblock Stride 2 */ +#define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< (XDMAC) Channel Destination Microblock Stride 2 */ +#define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< (XDMAC) Channel Interrupt Enable Register 3 */ +#define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< (XDMAC) Channel Interrupt Disable Register 3 */ +#define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< (XDMAC) Channel Interrupt Mask Register 3 */ +#define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< (XDMAC) Channel Interrupt Status Register 3 */ +#define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< (XDMAC) Channel Source Address Register 3 */ +#define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< (XDMAC) Channel Destination Address Register 3 */ +#define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< (XDMAC) Channel Next Descriptor Address Register 3 */ +#define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< (XDMAC) Channel Next Descriptor Control Register 3 */ +#define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< (XDMAC) Channel Microblock Control Register 3 */ +#define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< (XDMAC) Channel Block Control Register 3 */ +#define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< (XDMAC) Channel Configuration Register 3 */ +#define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */ +#define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< (XDMAC) Channel Source Microblock Stride 3 */ +#define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< (XDMAC) Channel Destination Microblock Stride 3 */ +#define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< (XDMAC) Channel Interrupt Enable Register 4 */ +#define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< (XDMAC) Channel Interrupt Disable Register 4 */ +#define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< (XDMAC) Channel Interrupt Mask Register 4 */ +#define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< (XDMAC) Channel Interrupt Status Register 4 */ +#define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< (XDMAC) Channel Source Address Register 4 */ +#define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< (XDMAC) Channel Destination Address Register 4 */ +#define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< (XDMAC) Channel Next Descriptor Address Register 4 */ +#define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< (XDMAC) Channel Next Descriptor Control Register 4 */ +#define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< (XDMAC) Channel Microblock Control Register 4 */ +#define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< (XDMAC) Channel Block Control Register 4 */ +#define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< (XDMAC) Channel Configuration Register 4 */ +#define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */ +#define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< (XDMAC) Channel Source Microblock Stride 4 */ +#define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< (XDMAC) Channel Destination Microblock Stride 4 */ +#define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< (XDMAC) Channel Interrupt Enable Register 5 */ +#define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< (XDMAC) Channel Interrupt Disable Register 5 */ +#define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< (XDMAC) Channel Interrupt Mask Register 5 */ +#define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< (XDMAC) Channel Interrupt Status Register 5 */ +#define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address Register 5 */ +#define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< (XDMAC) Channel Destination Address Register 5 */ +#define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< (XDMAC) Channel Next Descriptor Address Register 5 */ +#define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< (XDMAC) Channel Next Descriptor Control Register 5 */ +#define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< (XDMAC) Channel Microblock Control Register 5 */ +#define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< (XDMAC) Channel Block Control Register 5 */ +#define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< (XDMAC) Channel Configuration Register 5 */ +#define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */ +#define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblock Stride 5 */ +#define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< (XDMAC) Channel Destination Microblock Stride 5 */ +#define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< (XDMAC) Channel Interrupt Enable Register 6 */ +#define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< (XDMAC) Channel Interrupt Disable Register 6 */ +#define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< (XDMAC) Channel Interrupt Mask Register 6 */ +#define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< (XDMAC) Channel Interrupt Status Register 6 */ +#define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< (XDMAC) Channel Source Address Register 6 */ +#define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< (XDMAC) Channel Destination Address Register 6 */ +#define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< (XDMAC) Channel Next Descriptor Address Register 6 */ +#define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< (XDMAC) Channel Next Descriptor Control Register 6 */ +#define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< (XDMAC) Channel Microblock Control Register 6 */ +#define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< (XDMAC) Channel Block Control Register 6 */ +#define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< (XDMAC) Channel Configuration Register 6 */ +#define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */ +#define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< (XDMAC) Channel Source Microblock Stride 6 */ +#define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< (XDMAC) Channel Destination Microblock Stride 6 */ +#define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< (XDMAC) Channel Interrupt Enable Register 7 */ +#define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< (XDMAC) Channel Interrupt Disable Register 7 */ +#define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< (XDMAC) Channel Interrupt Mask Register 7 */ +#define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< (XDMAC) Channel Interrupt Status Register 7 */ +#define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< (XDMAC) Channel Source Address Register 7 */ +#define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< (XDMAC) Channel Destination Address Register 7 */ +#define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< (XDMAC) Channel Next Descriptor Address Register 7 */ +#define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< (XDMAC) Channel Next Descriptor Control Register 7 */ +#define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< (XDMAC) Channel Microblock Control Register 7 */ +#define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< (XDMAC) Channel Block Control Register 7 */ +#define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< (XDMAC) Channel Configuration Register 7 */ +#define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */ +#define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< (XDMAC) Channel Source Microblock Stride 7 */ +#define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< (XDMAC) Channel Destination Microblock Stride 7 */ +#define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< (XDMAC) Channel Interrupt Enable Register 8 */ +#define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< (XDMAC) Channel Interrupt Disable Register 8 */ +#define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< (XDMAC) Channel Interrupt Mask Register 8 */ +#define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< (XDMAC) Channel Interrupt Status Register 8 */ +#define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< (XDMAC) Channel Source Address Register 8 */ +#define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< (XDMAC) Channel Destination Address Register 8 */ +#define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< (XDMAC) Channel Next Descriptor Address Register 8 */ +#define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< (XDMAC) Channel Next Descriptor Control Register 8 */ +#define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< (XDMAC) Channel Microblock Control Register 8 */ +#define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< (XDMAC) Channel Block Control Register 8 */ +#define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< (XDMAC) Channel Configuration Register 8 */ +#define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */ +#define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< (XDMAC) Channel Source Microblock Stride 8 */ +#define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< (XDMAC) Channel Destination Microblock Stride 8 */ +#define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< (XDMAC) Channel Interrupt Enable Register 9 */ +#define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< (XDMAC) Channel Interrupt Disable Register 9 */ +#define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< (XDMAC) Channel Interrupt Mask Register 9 */ +#define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< (XDMAC) Channel Interrupt Status Register 9 */ +#define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< (XDMAC) Channel Source Address Register 9 */ +#define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< (XDMAC) Channel Destination Address Register 9 */ +#define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< (XDMAC) Channel Next Descriptor Address Register 9 */ +#define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< (XDMAC) Channel Next Descriptor Control Register 9 */ +#define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< (XDMAC) Channel Microblock Control Register 9 */ +#define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< (XDMAC) Channel Block Control Register 9 */ +#define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< (XDMAC) Channel Configuration Register 9 */ +#define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */ +#define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< (XDMAC) Channel Source Microblock Stride 9 */ +#define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< (XDMAC) Channel Destination Microblock Stride 9 */ +#define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< (XDMAC) Channel Interrupt Enable Register 10 */ +#define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< (XDMAC) Channel Interrupt Disable Register 10 */ +#define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< (XDMAC) Channel Interrupt Mask Register 10 */ +#define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< (XDMAC) Channel Interrupt Status Register 10 */ +#define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< (XDMAC) Channel Source Address Register 10 */ +#define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< (XDMAC) Channel Destination Address Register 10 */ +#define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< (XDMAC) Channel Next Descriptor Address Register 10 */ +#define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< (XDMAC) Channel Next Descriptor Control Register 10 */ +#define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< (XDMAC) Channel Microblock Control Register 10 */ +#define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< (XDMAC) Channel Block Control Register 10 */ +#define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< (XDMAC) Channel Configuration Register 10 */ +#define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */ +#define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< (XDMAC) Channel Source Microblock Stride 10 */ +#define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< (XDMAC) Channel Destination Microblock Stride 10 */ +#define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< (XDMAC) Channel Interrupt Enable Register 11 */ +#define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< (XDMAC) Channel Interrupt Disable Register 11 */ +#define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< (XDMAC) Channel Interrupt Mask Register 11 */ +#define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< (XDMAC) Channel Interrupt Status Register 11 */ +#define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< (XDMAC) Channel Source Address Register 11 */ +#define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< (XDMAC) Channel Destination Address Register 11 */ +#define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< (XDMAC) Channel Next Descriptor Address Register 11 */ +#define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< (XDMAC) Channel Next Descriptor Control Register 11 */ +#define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< (XDMAC) Channel Microblock Control Register 11 */ +#define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< (XDMAC) Channel Block Control Register 11 */ +#define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< (XDMAC) Channel Configuration Register 11 */ +#define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */ +#define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< (XDMAC) Channel Source Microblock Stride 11 */ +#define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< (XDMAC) Channel Destination Microblock Stride 11 */ +#define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< (XDMAC) Channel Interrupt Enable Register 12 */ +#define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< (XDMAC) Channel Interrupt Disable Register 12 */ +#define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< (XDMAC) Channel Interrupt Mask Register 12 */ +#define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< (XDMAC) Channel Interrupt Status Register 12 */ +#define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< (XDMAC) Channel Source Address Register 12 */ +#define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< (XDMAC) Channel Destination Address Register 12 */ +#define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< (XDMAC) Channel Next Descriptor Address Register 12 */ +#define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< (XDMAC) Channel Next Descriptor Control Register 12 */ +#define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< (XDMAC) Channel Microblock Control Register 12 */ +#define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< (XDMAC) Channel Block Control Register 12 */ +#define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< (XDMAC) Channel Configuration Register 12 */ +#define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */ +#define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< (XDMAC) Channel Source Microblock Stride 12 */ +#define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< (XDMAC) Channel Destination Microblock Stride 12 */ +#define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< (XDMAC) Channel Interrupt Enable Register 13 */ +#define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< (XDMAC) Channel Interrupt Disable Register 13 */ +#define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< (XDMAC) Channel Interrupt Mask Register 13 */ +#define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< (XDMAC) Channel Interrupt Status Register 13 */ +#define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< (XDMAC) Channel Source Address Register 13 */ +#define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< (XDMAC) Channel Destination Address Register 13 */ +#define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< (XDMAC) Channel Next Descriptor Address Register 13 */ +#define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< (XDMAC) Channel Next Descriptor Control Register 13 */ +#define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< (XDMAC) Channel Microblock Control Register 13 */ +#define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< (XDMAC) Channel Block Control Register 13 */ +#define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< (XDMAC) Channel Configuration Register 13 */ +#define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */ +#define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< (XDMAC) Channel Source Microblock Stride 13 */ +#define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< (XDMAC) Channel Destination Microblock Stride 13 */ +#define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< (XDMAC) Channel Interrupt Enable Register 14 */ +#define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< (XDMAC) Channel Interrupt Disable Register 14 */ +#define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< (XDMAC) Channel Interrupt Mask Register 14 */ +#define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< (XDMAC) Channel Interrupt Status Register 14 */ +#define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< (XDMAC) Channel Source Address Register 14 */ +#define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< (XDMAC) Channel Destination Address Register 14 */ +#define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< (XDMAC) Channel Next Descriptor Address Register 14 */ +#define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< (XDMAC) Channel Next Descriptor Control Register 14 */ +#define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< (XDMAC) Channel Microblock Control Register 14 */ +#define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< (XDMAC) Channel Block Control Register 14 */ +#define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< (XDMAC) Channel Configuration Register 14 */ +#define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */ +#define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< (XDMAC) Channel Source Microblock Stride 14 */ +#define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< (XDMAC) Channel Destination Microblock Stride 14 */ +#define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< (XDMAC) Channel Interrupt Enable Register 15 */ +#define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< (XDMAC) Channel Interrupt Disable Register 15 */ +#define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< (XDMAC) Channel Interrupt Mask Register 15 */ +#define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< (XDMAC) Channel Interrupt Status Register 15 */ +#define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< (XDMAC) Channel Source Address Register 15 */ +#define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< (XDMAC) Channel Destination Address Register 15 */ +#define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< (XDMAC) Channel Next Descriptor Address Register 15 */ +#define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< (XDMAC) Channel Next Descriptor Control Register 15 */ +#define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< (XDMAC) Channel Microblock Control Register 15 */ +#define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< (XDMAC) Channel Block Control Register 15 */ +#define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< (XDMAC) Channel Configuration Register 15 */ +#define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */ +#define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< (XDMAC) Channel Source Microblock Stride 15 */ +#define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< (XDMAC) Channel Destination Microblock Stride 15 */ +#define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< (XDMAC) Channel Interrupt Enable Register 16 */ +#define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< (XDMAC) Channel Interrupt Disable Register 16 */ +#define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< (XDMAC) Channel Interrupt Mask Register 16 */ +#define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< (XDMAC) Channel Interrupt Status Register 16 */ +#define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< (XDMAC) Channel Source Address Register 16 */ +#define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< (XDMAC) Channel Destination Address Register 16 */ +#define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< (XDMAC) Channel Next Descriptor Address Register 16 */ +#define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< (XDMAC) Channel Next Descriptor Control Register 16 */ +#define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< (XDMAC) Channel Microblock Control Register 16 */ +#define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< (XDMAC) Channel Block Control Register 16 */ +#define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< (XDMAC) Channel Configuration Register 16 */ +#define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */ +#define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< (XDMAC) Channel Source Microblock Stride 16 */ +#define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< (XDMAC) Channel Destination Microblock Stride 16 */ +#define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< (XDMAC) Channel Interrupt Enable Register 17 */ +#define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< (XDMAC) Channel Interrupt Disable Register 17 */ +#define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< (XDMAC) Channel Interrupt Mask Register 17 */ +#define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< (XDMAC) Channel Interrupt Status Register 17 */ +#define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< (XDMAC) Channel Source Address Register 17 */ +#define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< (XDMAC) Channel Destination Address Register 17 */ +#define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< (XDMAC) Channel Next Descriptor Address Register 17 */ +#define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< (XDMAC) Channel Next Descriptor Control Register 17 */ +#define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< (XDMAC) Channel Microblock Control Register 17 */ +#define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< (XDMAC) Channel Block Control Register 17 */ +#define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< (XDMAC) Channel Configuration Register 17 */ +#define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */ +#define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< (XDMAC) Channel Source Microblock Stride 17 */ +#define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< (XDMAC) Channel Destination Microblock Stride 17 */ +#define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< (XDMAC) Channel Interrupt Enable Register 18 */ +#define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< (XDMAC) Channel Interrupt Disable Register 18 */ +#define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< (XDMAC) Channel Interrupt Mask Register 18 */ +#define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< (XDMAC) Channel Interrupt Status Register 18 */ +#define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< (XDMAC) Channel Source Address Register 18 */ +#define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< (XDMAC) Channel Destination Address Register 18 */ +#define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< (XDMAC) Channel Next Descriptor Address Register 18 */ +#define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< (XDMAC) Channel Next Descriptor Control Register 18 */ +#define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< (XDMAC) Channel Microblock Control Register 18 */ +#define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< (XDMAC) Channel Block Control Register 18 */ +#define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< (XDMAC) Channel Configuration Register 18 */ +#define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */ +#define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< (XDMAC) Channel Source Microblock Stride 18 */ +#define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< (XDMAC) Channel Destination Microblock Stride 18 */ +#define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< (XDMAC) Channel Interrupt Enable Register 19 */ +#define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< (XDMAC) Channel Interrupt Disable Register 19 */ +#define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< (XDMAC) Channel Interrupt Mask Register 19 */ +#define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< (XDMAC) Channel Interrupt Status Register 19 */ +#define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< (XDMAC) Channel Source Address Register 19 */ +#define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< (XDMAC) Channel Destination Address Register 19 */ +#define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< (XDMAC) Channel Next Descriptor Address Register 19 */ +#define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< (XDMAC) Channel Next Descriptor Control Register 19 */ +#define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< (XDMAC) Channel Microblock Control Register 19 */ +#define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< (XDMAC) Channel Block Control Register 19 */ +#define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< (XDMAC) Channel Configuration Register 19 */ +#define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */ +#define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< (XDMAC) Channel Source Microblock Stride 19 */ +#define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< (XDMAC) Channel Destination Microblock Stride 19 */ +#define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< (XDMAC) Channel Interrupt Enable Register 20 */ +#define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< (XDMAC) Channel Interrupt Disable Register 20 */ +#define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< (XDMAC) Channel Interrupt Mask Register 20 */ +#define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< (XDMAC) Channel Interrupt Status Register 20 */ +#define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< (XDMAC) Channel Source Address Register 20 */ +#define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< (XDMAC) Channel Destination Address Register 20 */ +#define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< (XDMAC) Channel Next Descriptor Address Register 20 */ +#define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< (XDMAC) Channel Next Descriptor Control Register 20 */ +#define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< (XDMAC) Channel Microblock Control Register 20 */ +#define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< (XDMAC) Channel Block Control Register 20 */ +#define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< (XDMAC) Channel Configuration Register 20 */ +#define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */ +#define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< (XDMAC) Channel Source Microblock Stride 20 */ +#define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< (XDMAC) Channel Destination Microblock Stride 20 */ +#define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< (XDMAC) Channel Interrupt Enable Register 21 */ +#define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< (XDMAC) Channel Interrupt Disable Register 21 */ +#define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask Register 21 */ +#define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< (XDMAC) Channel Interrupt Status Register 21 */ +#define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< (XDMAC) Channel Source Address Register 21 */ +#define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< (XDMAC) Channel Destination Address Register 21 */ +#define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< (XDMAC) Channel Next Descriptor Address Register 21 */ +#define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< (XDMAC) Channel Next Descriptor Control Register 21 */ +#define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< (XDMAC) Channel Microblock Control Register 21 */ +#define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< (XDMAC) Channel Block Control Register 21 */ +#define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< (XDMAC) Channel Configuration Register 21 */ +#define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */ +#define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< (XDMAC) Channel Source Microblock Stride 21 */ +#define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< (XDMAC) Channel Destination Microblock Stride 21 */ +#define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< (XDMAC) Channel Interrupt Enable Register 22 */ +#define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< (XDMAC) Channel Interrupt Disable Register 22 */ +#define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< (XDMAC) Channel Interrupt Mask Register 22 */ +#define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< (XDMAC) Channel Interrupt Status Register 22 */ +#define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< (XDMAC) Channel Source Address Register 22 */ +#define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< (XDMAC) Channel Destination Address Register 22 */ +#define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< (XDMAC) Channel Next Descriptor Address Register 22 */ +#define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< (XDMAC) Channel Next Descriptor Control Register 22 */ +#define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< (XDMAC) Channel Microblock Control Register 22 */ +#define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< (XDMAC) Channel Block Control Register 22 */ +#define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< (XDMAC) Channel Configuration Register 22 */ +#define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */ +#define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< (XDMAC) Channel Source Microblock Stride 22 */ +#define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< (XDMAC) Channel Destination Microblock Stride 22 */ +#define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< (XDMAC) Channel Interrupt Enable Register 23 */ +#define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< (XDMAC) Channel Interrupt Disable Register 23 */ +#define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< (XDMAC) Channel Interrupt Mask Register 23 */ +#define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< (XDMAC) Channel Interrupt Status Register 23 */ +#define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< (XDMAC) Channel Source Address Register 23 */ +#define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< (XDMAC) Channel Destination Address Register 23 */ +#define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< (XDMAC) Channel Next Descriptor Address Register 23 */ +#define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< (XDMAC) Channel Next Descriptor Control Register 23 */ +#define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< (XDMAC) Channel Microblock Control Register 23 */ +#define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< (XDMAC) Channel Block Control Register 23 */ +#define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< (XDMAC) Channel Configuration Register 23 */ +#define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */ +#define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< (XDMAC) Channel Source Microblock Stride 23 */ +#define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< (XDMAC) Channel Destination Microblock Stride 23 */ +#define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< (XDMAC) Global Type Register */ +#define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< (XDMAC) Global Configuration Register */ +#define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< (XDMAC) Global Weighted Arbiter Configuration Register */ +#define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< (XDMAC) Global Interrupt Enable Register */ +#define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< (XDMAC) Global Interrupt Disable Register */ +#define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< (XDMAC) Global Interrupt Mask Register */ +#define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< (XDMAC) Global Interrupt Status Register */ +#define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< (XDMAC) Global Channel Enable Register */ +#define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< (XDMAC) Global Channel Disable Register */ +#define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< (XDMAC) Global Channel Status Register */ +#define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< (XDMAC) Global Channel Read Suspend Register */ +#define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< (XDMAC) Global Channel Write Suspend Register */ +#define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< (XDMAC) Global Channel Read Write Suspend Register */ +#define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< (XDMAC) Global Channel Read Write Resume Register */ +#define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< (XDMAC) Global Channel Software Request Register */ +#define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< (XDMAC) Global Channel Software Request Status Register */ +#define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< (XDMAC) Global Channel Software Flush Request Register */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance Parameter definitions for XDMAC peripheral ========== */ +#define XDMAC_INSTANCE_ID 58 +#define XDMAC_CLOCK_ID 58 + +#endif /* _SAME70_XDMAC_INSTANCE_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70j19b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70j19b.h new file mode 100644 index 0000000000..477bbb2c03 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70j19b.h @@ -0,0 +1,1108 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70J19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:37Z */ +#ifndef _SAME70J19B_PIO_H_ +#define _SAME70J19B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70J19B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70j20b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70j20b.h new file mode 100644 index 0000000000..d9b068e583 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70j20b.h @@ -0,0 +1,1108 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70J20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:41Z */ +#ifndef _SAME70J20B_PIO_H_ +#define _SAME70J20B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70J20B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70j21b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70j21b.h new file mode 100644 index 0000000000..40b0af23a4 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70j21b.h @@ -0,0 +1,1108 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70J21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:46Z */ +#ifndef _SAME70J21B_PIO_H_ +#define _SAME70J21B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70J21B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70n19b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70n19b.h new file mode 100644 index 0000000000..e41f3bf96c --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70n19b.h @@ -0,0 +1,1268 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70N19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:48Z */ +#ifndef _SAME70N19B_PIO_H_ +#define _SAME70N19B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: CANRX1 on PD28 mux B*/ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_UL_(1) << 28) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70N19B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70n20b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70n20b.h new file mode 100644 index 0000000000..a41ad407fe --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70n20b.h @@ -0,0 +1,1268 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70N20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:51Z */ +#ifndef _SAME70N20B_PIO_H_ +#define _SAME70N20B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: CANRX1 on PD28 mux B*/ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_UL_(1) << 28) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70N20B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70n21b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70n21b.h new file mode 100644 index 0000000000..5d26f3b3a4 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70n21b.h @@ -0,0 +1,1268 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70N21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:53Z */ +#ifndef _SAME70N21B_PIO_H_ +#define _SAME70N21B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: CANRX1 on PD28 mux B*/ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_UL_(1) << 28) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70N21B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70q19b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70q19b.h new file mode 100644 index 0000000000..a427065b21 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70q19b.h @@ -0,0 +1,1962 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70Q19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:55Z */ +#ifndef _SAME70Q19B_PIO_H_ +#define _SAME70Q19B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ +#define PIN_PE0 (128) /**< Pin Number for PE0 */ +#define PIN_PE1 (129) /**< Pin Number for PE1 */ +#define PIN_PE2 (130) /**< Pin Number for PE2 */ +#define PIN_PE3 (131) /**< Pin Number for PE3 */ +#define PIN_PE4 (132) /**< Pin Number for PE4 */ +#define PIN_PE5 (133) /**< Pin Number for PE5 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO Mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO Mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO Mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO Mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO Mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO Mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO Mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO Mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO Mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO Mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO Mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO Mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO Mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO Mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO Mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO Mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO Mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO Mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO Mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO Mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO Mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO Mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO Mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO Mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO Mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO Mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO Mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO Mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO Mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO Mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO Mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO Mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO Mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO Mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO Mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO Mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO Mask for PE5 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PC0_IDX ( 64) /**< PIO Index Number for PC0 */ +#define PIO_PC1_IDX ( 65) /**< PIO Index Number for PC1 */ +#define PIO_PC2_IDX ( 66) /**< PIO Index Number for PC2 */ +#define PIO_PC3_IDX ( 67) /**< PIO Index Number for PC3 */ +#define PIO_PC4_IDX ( 68) /**< PIO Index Number for PC4 */ +#define PIO_PC5_IDX ( 69) /**< PIO Index Number for PC5 */ +#define PIO_PC6_IDX ( 70) /**< PIO Index Number for PC6 */ +#define PIO_PC7_IDX ( 71) /**< PIO Index Number for PC7 */ +#define PIO_PC8_IDX ( 72) /**< PIO Index Number for PC8 */ +#define PIO_PC9_IDX ( 73) /**< PIO Index Number for PC9 */ +#define PIO_PC10_IDX ( 74) /**< PIO Index Number for PC10 */ +#define PIO_PC11_IDX ( 75) /**< PIO Index Number for PC11 */ +#define PIO_PC12_IDX ( 76) /**< PIO Index Number for PC12 */ +#define PIO_PC13_IDX ( 77) /**< PIO Index Number for PC13 */ +#define PIO_PC14_IDX ( 78) /**< PIO Index Number for PC14 */ +#define PIO_PC15_IDX ( 79) /**< PIO Index Number for PC15 */ +#define PIO_PC16_IDX ( 80) /**< PIO Index Number for PC16 */ +#define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */ +#define PIO_PC18_IDX ( 82) /**< PIO Index Number for PC18 */ +#define PIO_PC19_IDX ( 83) /**< PIO Index Number for PC19 */ +#define PIO_PC20_IDX ( 84) /**< PIO Index Number for PC20 */ +#define PIO_PC21_IDX ( 85) /**< PIO Index Number for PC21 */ +#define PIO_PC22_IDX ( 86) /**< PIO Index Number for PC22 */ +#define PIO_PC23_IDX ( 87) /**< PIO Index Number for PC23 */ +#define PIO_PC24_IDX ( 88) /**< PIO Index Number for PC24 */ +#define PIO_PC25_IDX ( 89) /**< PIO Index Number for PC25 */ +#define PIO_PC26_IDX ( 90) /**< PIO Index Number for PC26 */ +#define PIO_PC27_IDX ( 91) /**< PIO Index Number for PC27 */ +#define PIO_PC28_IDX ( 92) /**< PIO Index Number for PC28 */ +#define PIO_PC29_IDX ( 93) /**< PIO Index Number for PC29 */ +#define PIO_PC30_IDX ( 94) /**< PIO Index Number for PC30 */ +#define PIO_PC31_IDX ( 95) /**< PIO Index Number for PC31 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ +#define PIO_PE0_IDX (128) /**< PIO Index Number for PE0 */ +#define PIO_PE1_IDX (129) /**< PIO Index Number for PE1 */ +#define PIO_PE2_IDX (130) /**< PIO Index Number for PE2 */ +#define PIO_PE3_IDX (131) /**< PIO Index Number for PE3 */ +#define PIO_PE4_IDX (132) /**< PIO Index Number for PE4 */ +#define PIO_PE5_IDX (133) /**< PIO Index Number for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X1*/ +#define PIO_PE5X1_AFEC0_AD3 (_UL_(1) << 5) + +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X1*/ +#define PIO_PE4X1_AFEC0_AD4 (_UL_(1) << 4) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AD1 on PC13 mux X1*/ +#define PIO_PC13X1_AFEC1_AD1 (_UL_(1) << 13) + +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AD2 on PC15 mux X1*/ +#define PIO_PC15X1_AFEC1_AD2 (_UL_(1) << 15) + +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AD3 on PC12 mux X1*/ +#define PIO_PC12X1_AFEC1_AD3 (_UL_(1) << 12) + +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AD4 on PC29 mux X1*/ +#define PIO_PC29X1_AFEC1_AD4 (_UL_(1) << 29) + +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AD5 on PC30 mux X1*/ +#define PIO_PC30X1_AFEC1_AD5 (_UL_(1) << 30) + +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AD6 on PC31 mux X1*/ +#define PIO_PC31X1_AFEC1_AD6 (_UL_(1) << 31) + +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AD7 on PC26 mux X1*/ +#define PIO_PC26X1_AFEC1_AD7 (_UL_(1) << 26) + +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AD8 on PC27 mux X1*/ +#define PIO_PC27X1_AFEC1_AD8 (_UL_(1) << 27) + +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AD9 on PC0 mux X1*/ +#define PIO_PC0X1_AFEC1_AD9 (_UL_(1) << 0) + +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AD10 on PE3 mux X1*/ +#define PIO_PE3X1_AFEC1_AD10 (_UL_(1) << 3) + +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AD11 on PE0 mux X1*/ +#define PIO_PE0X1_AFEC1_AD11 (_UL_(1) << 0) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: A0 on PC18 mux A*/ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: A0 */ +#define PIO_PC18A_EBI_A0 (_UL_(1) << 18) + +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: A1 on PC19 mux A*/ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: A1 */ +#define PIO_PC19A_EBI_A1 (_UL_(1) << 19) + +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: A2 on PC20 mux A*/ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: A2 */ +#define PIO_PC20A_EBI_A2 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: A3 on PC21 mux A*/ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: A3 */ +#define PIO_PC21A_EBI_A3 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: A4 on PC22 mux A*/ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: A4 */ +#define PIO_PC22A_EBI_A4 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: A5 on PC23 mux A*/ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: A5 */ +#define PIO_PC23A_EBI_A5 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: A6 on PC24 mux A*/ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: A6 */ +#define PIO_PC24A_EBI_A6 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: A7 on PC25 mux A*/ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: A7 */ +#define PIO_PC25A_EBI_A7 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: A8 on PC26 mux A*/ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: A8 */ +#define PIO_PC26A_EBI_A8 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: A9 on PC27 mux A*/ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: A9 */ +#define PIO_PC27A_EBI_A9 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: A10 on PC28 mux A*/ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: A10 */ +#define PIO_PC28A_EBI_A10 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: A11 on PC29 mux A*/ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: A11 */ +#define PIO_PC29A_EBI_A11 (_UL_(1) << 29) + +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: A12 on PC30 mux A*/ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: A12 */ +#define PIO_PC30A_EBI_A12 (_UL_(1) << 30) + +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: A13 on PC31 mux A*/ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: A13 */ +#define PIO_PC31A_EBI_A13 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: A14 on PA18 mux C*/ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: A14 */ +#define PIO_PA18C_EBI_A14 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: A15 on PA19 mux C*/ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: A15 */ +#define PIO_PA19C_EBI_A15 (_UL_(1) << 19) + +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: A16 on PA20 mux C*/ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: A16 */ +#define PIO_PA20C_EBI_A16 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: A17 on PA0 mux C*/ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: A17 */ +#define PIO_PA0C_EBI_A17 (_UL_(1) << 0) + +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: A18 on PA1 mux C*/ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: A18 */ +#define PIO_PA1C_EBI_A18 (_UL_(1) << 1) + +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: A19 on PA23 mux C*/ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: A19 */ +#define PIO_PA23C_EBI_A19 (_UL_(1) << 23) + +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: A20 on PA24 mux C*/ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: A20 */ +#define PIO_PA24C_EBI_A20 (_UL_(1) << 24) + +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: A21 on PC16 mux A*/ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: A21 */ +#define PIO_PC16A_EBI_A21 (_UL_(1) << 16) + +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: A22 */ +#define PIO_PC17A_EBI_A22 (_UL_(1) << 17) + +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: A23 on PA25 mux C*/ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: A23 */ +#define PIO_PA25C_EBI_A23 (_UL_(1) << 25) + +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: D0 on PC0 mux A*/ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: D0 */ +#define PIO_PC0A_EBI_D0 (_UL_(1) << 0) + +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: D1 on PC1 mux A*/ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: D1 */ +#define PIO_PC1A_EBI_D1 (_UL_(1) << 1) + +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: D2 on PC2 mux A*/ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: D2 */ +#define PIO_PC2A_EBI_D2 (_UL_(1) << 2) + +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: D3 on PC3 mux A*/ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: D3 */ +#define PIO_PC3A_EBI_D3 (_UL_(1) << 3) + +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: D4 on PC4 mux A*/ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: D4 */ +#define PIO_PC4A_EBI_D4 (_UL_(1) << 4) + +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: D5 on PC5 mux A*/ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: D5 */ +#define PIO_PC5A_EBI_D5 (_UL_(1) << 5) + +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: D6 on PC6 mux A*/ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: D6 */ +#define PIO_PC6A_EBI_D6 (_UL_(1) << 6) + +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: D7 on PC7 mux A*/ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: D7 */ +#define PIO_PC7A_EBI_D7 (_UL_(1) << 7) + +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: D8 on PE0 mux A*/ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: D8 */ +#define PIO_PE0A_EBI_D8 (_UL_(1) << 0) + +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: D9 on PE1 mux A*/ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: D9 */ +#define PIO_PE1A_EBI_D9 (_UL_(1) << 1) + +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: D10 on PE2 mux A*/ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: D10 */ +#define PIO_PE2A_EBI_D10 (_UL_(1) << 2) + +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: D11 on PE3 mux A*/ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: D11 */ +#define PIO_PE3A_EBI_D11 (_UL_(1) << 3) + +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: D12 on PE4 mux A*/ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: D12 */ +#define PIO_PE4A_EBI_D12 (_UL_(1) << 4) + +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: D13 on PE5 mux A*/ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: D13 */ +#define PIO_PE5A_EBI_D13 (_UL_(1) << 5) + +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: D14 on PA15 mux A*/ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: D14 */ +#define PIO_PA15A_EBI_D14 (_UL_(1) << 15) + +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: D15 on PA16 mux A*/ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: D15 */ +#define PIO_PA16A_EBI_D15 (_UL_(1) << 16) + +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: NWAIT on PC13 mux A*/ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_UL_(1) << 13) + +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: NCS0 on PC14 mux A*/ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_UL_(1) << 14) + +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: NCS1 on PC15 mux A*/ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_UL_(1) << 15) + +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: NCS1 on PD18 mux A*/ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_UL_(1) << 18) + +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: NCS2 on PA22 mux C*/ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_UL_(1) << 22) + +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: NCS3 on PC12 mux A*/ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_UL_(1) << 12) + +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: NCS3 on PD19 mux A*/ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_UL_(1) << 19) + +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: NWR0 on PC8 mux A*/ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_UL_(1) << 8) + +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: NWR1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_UL_(1) << 15) + +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: NRD on PC11 mux A*/ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: NRD */ +#define PIO_PC11A_EBI_NRD (_UL_(1) << 11) + +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: NWE on PC8 mux A*/ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: NWE */ +#define PIO_PC8A_EBI_NWE (_UL_(1) << 8) + +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: NBS0 on PC18 mux A*/ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: NBS1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_UL_(1) << 15) + +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: NANDALE on PC16 mux A*/ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_UL_(1) << 16) + +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mux A*/ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_UL_(1) << 17) + +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: NANDOE on PC9 mux A*/ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_UL_(1) << 9) + +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: NANDWE on PC10 mux A*/ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_UL_(1) << 10) + +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: SDCK on PD23 mux C*/ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: SDCK */ +#define PIO_PD23C_EBI_SDCK (_UL_(1) << 23) + +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: SDCKE on PD14 mux C*/ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_UL_(1) << 14) + +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: SDCS on PC15 mux A*/ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PC15A_EBI_SDCS (_UL_(1) << 15) + +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: SDCS on PD18 mux A*/ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PD18A_EBI_SDCS (_UL_(1) << 18) + +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: BA0 on PA20 mux C*/ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: BA0 */ +#define PIO_PA20C_EBI_BA0 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: BA1 on PA0 mux C*/ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: BA1 */ +#define PIO_PA0C_EBI_BA1 (_UL_(1) << 0) + +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: SDWE on PD29 mux C*/ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: SDWE */ +#define PIO_PD29C_EBI_SDWE (_UL_(1) << 29) + +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: RAS on PD16 mux C*/ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: RAS */ +#define PIO_PD16C_EBI_RAS (_UL_(1) << 16) + +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: CAS on PD17 mux C*/ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: CAS */ +#define PIO_PD17C_EBI_CAS (_UL_(1) << 17) + +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: SDA10 on PC13 mux C*/ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: SDA10 on PD13 mux C*/ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: SDA0 on PC20 mux A*/ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: SDA1 on PC21 mux A*/ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: SDA2 on PC22 mux A*/ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: SDA3 on PC23 mux A*/ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: SDA4 on PC24 mux A*/ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: SDA5 on PC25 mux A*/ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: SDA6 on PC26 mux A*/ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: SDA7 on PC27 mux A*/ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: SDA8 on PC28 mux A*/ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: SDA9 on PC29 mux A*/ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_UL_(1) << 29) + +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: SDA11 on PC31 mux A*/ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: SDA12 on PA18 mux C*/ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_SDA13 _L_(19) /**< EBI signal: SDA13 on PA19 mux C*/ +#define MUX_PA19C_EBI_SDA13 _L_(2) /**< EBI signal line function value: SDA13 */ +#define PIO_PA19C_EBI_SDA13 (_UL_(1) << 19) + +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: DQM0 on PC18 mux A*/ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: DQM1 on PD15 mux C*/ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_UL_(1) << 15) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: CK on PA20 mux D*/ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: CK */ +#define PIO_PA20D_I2SC1_CK (_UL_(1) << 20) + +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: DI0 on PE2 mux C*/ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_UL_(1) << 2) + +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: DO0 on PE1 mux C*/ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_UL_(1) << 1) + +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: MCK on PA19 mux D*/ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: MCK */ +#define PIO_PA19D_I2SC1_MCK (_UL_(1) << 19) + +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: WS on PE0 mux C*/ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: WS */ +#define PIO_PE0C_I2SC1_WS (_UL_(1) << 0) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: CANRX1 on PC12 mux C*/ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_UL_(1) << 12) + +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: CANTX1 on PC14 mux C*/ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_UL_(1) << 14) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWMH2 on PC19 mux B*/ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_UL_(1) << 19) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWMH3 on PC13 mux B*/ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_UL_(1) << 13) + +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWMH3 on PC21 mux B*/ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_UL_(1) << 21) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWML0 on PC0 mux B*/ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_UL_(1) << 0) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWML1 on PC1 mux B*/ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_UL_(1) << 1) + +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWML1 on PC18 mux B*/ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_UL_(1) << 18) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWML2 on PC2 mux B*/ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_UL_(1) << 2) + +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWML2 on PC20 mux B*/ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_UL_(1) << 20) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWML3 on PC3 mux B*/ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_UL_(1) << 3) + +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWML3 on PC15 mux B*/ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWML3 on PC22 mux B*/ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_UL_(1) << 22) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: MISO on PC26 mux C*/ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: MISO */ +#define PIO_PC26C_SPI1_MISO (_UL_(1) << 26) + +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: MOSI on PC27 mux C*/ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: MOSI */ +#define PIO_PC27C_SPI1_MOSI (_UL_(1) << 27) + +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: NPCS0 on PC25 mux C*/ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_UL_(1) << 25) + +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: NPCS1 on PC28 mux C*/ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_UL_(1) << 28) + +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: NPCS1 on PD0 mux C*/ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_UL_(1) << 0) + +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: NPCS2 on PC29 mux C*/ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_UL_(1) << 29) + +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: NPCS2 on PD1 mux C*/ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_UL_(1) << 1) + +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: NPCS3 on PC30 mux C*/ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_UL_(1) << 30) + +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: NPCS3 on PD2 mux C*/ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_UL_(1) << 2) + +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPCK on PC24 mux C*/ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPCK */ +#define PIO_PC24C_SPI1_SPCK (_UL_(1) << 24) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TCLK3 on PC25 mux B*/ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_UL_(1) << 25) + +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TCLK4 on PC28 mux B*/ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_UL_(1) << 28) + +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TCLK5 on PC31 mux B*/ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_UL_(1) << 31) + +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TIOA3 on PC23 mux B*/ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_UL_(1) << 23) + +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TIOA4 on PC26 mux B*/ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_UL_(1) << 26) + +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TIOA5 on PC29 mux B*/ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_UL_(1) << 29) + +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TIOB3 on PC24 mux B*/ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_UL_(1) << 24) + +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TIOB4 on PC27 mux B*/ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_UL_(1) << 27) + +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TIOB5 on PC30 mux B*/ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_UL_(1) << 30) + +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TCLK6 on PC7 mux B*/ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_UL_(1) << 7) + +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TCLK7 on PC10 mux B*/ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_UL_(1) << 10) + +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TCLK8 on PC14 mux B*/ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_UL_(1) << 14) + +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TIOA6 on PC5 mux B*/ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_UL_(1) << 5) + +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TIOA7 on PC8 mux B*/ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_UL_(1) << 8) + +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TIOA8 on PC11 mux B*/ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_UL_(1) << 11) + +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TIOB6 on PC6 mux B*/ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_UL_(1) << 6) + +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TIOB7 on PC9 mux B*/ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_UL_(1) << 9) + +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TIOB8 on PC12 mux B*/ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_UL_(1) << 12) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TCLK9 on PE2 mux B*/ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_UL_(1) << 2) + +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TCLK10 on PE5 mux B*/ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_UL_(1) << 5) + +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TIOA9 on PE0 mux B*/ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_UL_(1) << 0) + +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TIOA10 on PE3 mux B*/ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_UL_(1) << 3) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TIOB9 on PE1 mux B*/ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_UL_(1) << 1) + +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TIOB10 on PE4 mux B*/ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_UL_(1) << 4) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70Q19B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70q20b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70q20b.h new file mode 100644 index 0000000000..df53114899 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70q20b.h @@ -0,0 +1,1962 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70Q20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:57Z */ +#ifndef _SAME70Q20B_PIO_H_ +#define _SAME70Q20B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ +#define PIN_PE0 (128) /**< Pin Number for PE0 */ +#define PIN_PE1 (129) /**< Pin Number for PE1 */ +#define PIN_PE2 (130) /**< Pin Number for PE2 */ +#define PIN_PE3 (131) /**< Pin Number for PE3 */ +#define PIN_PE4 (132) /**< Pin Number for PE4 */ +#define PIN_PE5 (133) /**< Pin Number for PE5 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO Mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO Mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO Mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO Mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO Mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO Mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO Mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO Mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO Mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO Mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO Mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO Mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO Mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO Mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO Mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO Mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO Mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO Mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO Mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO Mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO Mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO Mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO Mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO Mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO Mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO Mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO Mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO Mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO Mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO Mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO Mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO Mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO Mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO Mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO Mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO Mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO Mask for PE5 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PC0_IDX ( 64) /**< PIO Index Number for PC0 */ +#define PIO_PC1_IDX ( 65) /**< PIO Index Number for PC1 */ +#define PIO_PC2_IDX ( 66) /**< PIO Index Number for PC2 */ +#define PIO_PC3_IDX ( 67) /**< PIO Index Number for PC3 */ +#define PIO_PC4_IDX ( 68) /**< PIO Index Number for PC4 */ +#define PIO_PC5_IDX ( 69) /**< PIO Index Number for PC5 */ +#define PIO_PC6_IDX ( 70) /**< PIO Index Number for PC6 */ +#define PIO_PC7_IDX ( 71) /**< PIO Index Number for PC7 */ +#define PIO_PC8_IDX ( 72) /**< PIO Index Number for PC8 */ +#define PIO_PC9_IDX ( 73) /**< PIO Index Number for PC9 */ +#define PIO_PC10_IDX ( 74) /**< PIO Index Number for PC10 */ +#define PIO_PC11_IDX ( 75) /**< PIO Index Number for PC11 */ +#define PIO_PC12_IDX ( 76) /**< PIO Index Number for PC12 */ +#define PIO_PC13_IDX ( 77) /**< PIO Index Number for PC13 */ +#define PIO_PC14_IDX ( 78) /**< PIO Index Number for PC14 */ +#define PIO_PC15_IDX ( 79) /**< PIO Index Number for PC15 */ +#define PIO_PC16_IDX ( 80) /**< PIO Index Number for PC16 */ +#define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */ +#define PIO_PC18_IDX ( 82) /**< PIO Index Number for PC18 */ +#define PIO_PC19_IDX ( 83) /**< PIO Index Number for PC19 */ +#define PIO_PC20_IDX ( 84) /**< PIO Index Number for PC20 */ +#define PIO_PC21_IDX ( 85) /**< PIO Index Number for PC21 */ +#define PIO_PC22_IDX ( 86) /**< PIO Index Number for PC22 */ +#define PIO_PC23_IDX ( 87) /**< PIO Index Number for PC23 */ +#define PIO_PC24_IDX ( 88) /**< PIO Index Number for PC24 */ +#define PIO_PC25_IDX ( 89) /**< PIO Index Number for PC25 */ +#define PIO_PC26_IDX ( 90) /**< PIO Index Number for PC26 */ +#define PIO_PC27_IDX ( 91) /**< PIO Index Number for PC27 */ +#define PIO_PC28_IDX ( 92) /**< PIO Index Number for PC28 */ +#define PIO_PC29_IDX ( 93) /**< PIO Index Number for PC29 */ +#define PIO_PC30_IDX ( 94) /**< PIO Index Number for PC30 */ +#define PIO_PC31_IDX ( 95) /**< PIO Index Number for PC31 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ +#define PIO_PE0_IDX (128) /**< PIO Index Number for PE0 */ +#define PIO_PE1_IDX (129) /**< PIO Index Number for PE1 */ +#define PIO_PE2_IDX (130) /**< PIO Index Number for PE2 */ +#define PIO_PE3_IDX (131) /**< PIO Index Number for PE3 */ +#define PIO_PE4_IDX (132) /**< PIO Index Number for PE4 */ +#define PIO_PE5_IDX (133) /**< PIO Index Number for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X1*/ +#define PIO_PE5X1_AFEC0_AD3 (_UL_(1) << 5) + +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X1*/ +#define PIO_PE4X1_AFEC0_AD4 (_UL_(1) << 4) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AD1 on PC13 mux X1*/ +#define PIO_PC13X1_AFEC1_AD1 (_UL_(1) << 13) + +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AD2 on PC15 mux X1*/ +#define PIO_PC15X1_AFEC1_AD2 (_UL_(1) << 15) + +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AD3 on PC12 mux X1*/ +#define PIO_PC12X1_AFEC1_AD3 (_UL_(1) << 12) + +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AD4 on PC29 mux X1*/ +#define PIO_PC29X1_AFEC1_AD4 (_UL_(1) << 29) + +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AD5 on PC30 mux X1*/ +#define PIO_PC30X1_AFEC1_AD5 (_UL_(1) << 30) + +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AD6 on PC31 mux X1*/ +#define PIO_PC31X1_AFEC1_AD6 (_UL_(1) << 31) + +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AD7 on PC26 mux X1*/ +#define PIO_PC26X1_AFEC1_AD7 (_UL_(1) << 26) + +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AD8 on PC27 mux X1*/ +#define PIO_PC27X1_AFEC1_AD8 (_UL_(1) << 27) + +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AD9 on PC0 mux X1*/ +#define PIO_PC0X1_AFEC1_AD9 (_UL_(1) << 0) + +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AD10 on PE3 mux X1*/ +#define PIO_PE3X1_AFEC1_AD10 (_UL_(1) << 3) + +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AD11 on PE0 mux X1*/ +#define PIO_PE0X1_AFEC1_AD11 (_UL_(1) << 0) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: A0 on PC18 mux A*/ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: A0 */ +#define PIO_PC18A_EBI_A0 (_UL_(1) << 18) + +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: A1 on PC19 mux A*/ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: A1 */ +#define PIO_PC19A_EBI_A1 (_UL_(1) << 19) + +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: A2 on PC20 mux A*/ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: A2 */ +#define PIO_PC20A_EBI_A2 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: A3 on PC21 mux A*/ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: A3 */ +#define PIO_PC21A_EBI_A3 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: A4 on PC22 mux A*/ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: A4 */ +#define PIO_PC22A_EBI_A4 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: A5 on PC23 mux A*/ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: A5 */ +#define PIO_PC23A_EBI_A5 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: A6 on PC24 mux A*/ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: A6 */ +#define PIO_PC24A_EBI_A6 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: A7 on PC25 mux A*/ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: A7 */ +#define PIO_PC25A_EBI_A7 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: A8 on PC26 mux A*/ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: A8 */ +#define PIO_PC26A_EBI_A8 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: A9 on PC27 mux A*/ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: A9 */ +#define PIO_PC27A_EBI_A9 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: A10 on PC28 mux A*/ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: A10 */ +#define PIO_PC28A_EBI_A10 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: A11 on PC29 mux A*/ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: A11 */ +#define PIO_PC29A_EBI_A11 (_UL_(1) << 29) + +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: A12 on PC30 mux A*/ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: A12 */ +#define PIO_PC30A_EBI_A12 (_UL_(1) << 30) + +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: A13 on PC31 mux A*/ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: A13 */ +#define PIO_PC31A_EBI_A13 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: A14 on PA18 mux C*/ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: A14 */ +#define PIO_PA18C_EBI_A14 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: A15 on PA19 mux C*/ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: A15 */ +#define PIO_PA19C_EBI_A15 (_UL_(1) << 19) + +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: A16 on PA20 mux C*/ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: A16 */ +#define PIO_PA20C_EBI_A16 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: A17 on PA0 mux C*/ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: A17 */ +#define PIO_PA0C_EBI_A17 (_UL_(1) << 0) + +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: A18 on PA1 mux C*/ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: A18 */ +#define PIO_PA1C_EBI_A18 (_UL_(1) << 1) + +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: A19 on PA23 mux C*/ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: A19 */ +#define PIO_PA23C_EBI_A19 (_UL_(1) << 23) + +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: A20 on PA24 mux C*/ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: A20 */ +#define PIO_PA24C_EBI_A20 (_UL_(1) << 24) + +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: A21 on PC16 mux A*/ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: A21 */ +#define PIO_PC16A_EBI_A21 (_UL_(1) << 16) + +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: A22 */ +#define PIO_PC17A_EBI_A22 (_UL_(1) << 17) + +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: A23 on PA25 mux C*/ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: A23 */ +#define PIO_PA25C_EBI_A23 (_UL_(1) << 25) + +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: D0 on PC0 mux A*/ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: D0 */ +#define PIO_PC0A_EBI_D0 (_UL_(1) << 0) + +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: D1 on PC1 mux A*/ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: D1 */ +#define PIO_PC1A_EBI_D1 (_UL_(1) << 1) + +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: D2 on PC2 mux A*/ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: D2 */ +#define PIO_PC2A_EBI_D2 (_UL_(1) << 2) + +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: D3 on PC3 mux A*/ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: D3 */ +#define PIO_PC3A_EBI_D3 (_UL_(1) << 3) + +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: D4 on PC4 mux A*/ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: D4 */ +#define PIO_PC4A_EBI_D4 (_UL_(1) << 4) + +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: D5 on PC5 mux A*/ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: D5 */ +#define PIO_PC5A_EBI_D5 (_UL_(1) << 5) + +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: D6 on PC6 mux A*/ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: D6 */ +#define PIO_PC6A_EBI_D6 (_UL_(1) << 6) + +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: D7 on PC7 mux A*/ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: D7 */ +#define PIO_PC7A_EBI_D7 (_UL_(1) << 7) + +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: D8 on PE0 mux A*/ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: D8 */ +#define PIO_PE0A_EBI_D8 (_UL_(1) << 0) + +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: D9 on PE1 mux A*/ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: D9 */ +#define PIO_PE1A_EBI_D9 (_UL_(1) << 1) + +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: D10 on PE2 mux A*/ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: D10 */ +#define PIO_PE2A_EBI_D10 (_UL_(1) << 2) + +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: D11 on PE3 mux A*/ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: D11 */ +#define PIO_PE3A_EBI_D11 (_UL_(1) << 3) + +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: D12 on PE4 mux A*/ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: D12 */ +#define PIO_PE4A_EBI_D12 (_UL_(1) << 4) + +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: D13 on PE5 mux A*/ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: D13 */ +#define PIO_PE5A_EBI_D13 (_UL_(1) << 5) + +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: D14 on PA15 mux A*/ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: D14 */ +#define PIO_PA15A_EBI_D14 (_UL_(1) << 15) + +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: D15 on PA16 mux A*/ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: D15 */ +#define PIO_PA16A_EBI_D15 (_UL_(1) << 16) + +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: NWAIT on PC13 mux A*/ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_UL_(1) << 13) + +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: NCS0 on PC14 mux A*/ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_UL_(1) << 14) + +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: NCS1 on PC15 mux A*/ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_UL_(1) << 15) + +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: NCS1 on PD18 mux A*/ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_UL_(1) << 18) + +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: NCS2 on PA22 mux C*/ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_UL_(1) << 22) + +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: NCS3 on PC12 mux A*/ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_UL_(1) << 12) + +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: NCS3 on PD19 mux A*/ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_UL_(1) << 19) + +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: NWR0 on PC8 mux A*/ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_UL_(1) << 8) + +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: NWR1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_UL_(1) << 15) + +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: NRD on PC11 mux A*/ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: NRD */ +#define PIO_PC11A_EBI_NRD (_UL_(1) << 11) + +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: NWE on PC8 mux A*/ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: NWE */ +#define PIO_PC8A_EBI_NWE (_UL_(1) << 8) + +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: NBS0 on PC18 mux A*/ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: NBS1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_UL_(1) << 15) + +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: NANDALE on PC16 mux A*/ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_UL_(1) << 16) + +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mux A*/ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_UL_(1) << 17) + +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: NANDOE on PC9 mux A*/ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_UL_(1) << 9) + +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: NANDWE on PC10 mux A*/ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_UL_(1) << 10) + +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: SDCK on PD23 mux C*/ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: SDCK */ +#define PIO_PD23C_EBI_SDCK (_UL_(1) << 23) + +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: SDCKE on PD14 mux C*/ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_UL_(1) << 14) + +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: SDCS on PC15 mux A*/ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PC15A_EBI_SDCS (_UL_(1) << 15) + +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: SDCS on PD18 mux A*/ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PD18A_EBI_SDCS (_UL_(1) << 18) + +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: BA0 on PA20 mux C*/ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: BA0 */ +#define PIO_PA20C_EBI_BA0 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: BA1 on PA0 mux C*/ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: BA1 */ +#define PIO_PA0C_EBI_BA1 (_UL_(1) << 0) + +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: SDWE on PD29 mux C*/ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: SDWE */ +#define PIO_PD29C_EBI_SDWE (_UL_(1) << 29) + +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: RAS on PD16 mux C*/ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: RAS */ +#define PIO_PD16C_EBI_RAS (_UL_(1) << 16) + +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: CAS on PD17 mux C*/ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: CAS */ +#define PIO_PD17C_EBI_CAS (_UL_(1) << 17) + +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: SDA10 on PC13 mux C*/ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: SDA10 on PD13 mux C*/ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: SDA0 on PC20 mux A*/ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: SDA1 on PC21 mux A*/ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: SDA2 on PC22 mux A*/ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: SDA3 on PC23 mux A*/ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: SDA4 on PC24 mux A*/ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: SDA5 on PC25 mux A*/ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: SDA6 on PC26 mux A*/ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: SDA7 on PC27 mux A*/ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: SDA8 on PC28 mux A*/ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: SDA9 on PC29 mux A*/ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_UL_(1) << 29) + +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: SDA11 on PC31 mux A*/ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: SDA12 on PA18 mux C*/ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_SDA13 _L_(19) /**< EBI signal: SDA13 on PA19 mux C*/ +#define MUX_PA19C_EBI_SDA13 _L_(2) /**< EBI signal line function value: SDA13 */ +#define PIO_PA19C_EBI_SDA13 (_UL_(1) << 19) + +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: DQM0 on PC18 mux A*/ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: DQM1 on PD15 mux C*/ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_UL_(1) << 15) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: CK on PA20 mux D*/ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: CK */ +#define PIO_PA20D_I2SC1_CK (_UL_(1) << 20) + +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: DI0 on PE2 mux C*/ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_UL_(1) << 2) + +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: DO0 on PE1 mux C*/ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_UL_(1) << 1) + +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: MCK on PA19 mux D*/ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: MCK */ +#define PIO_PA19D_I2SC1_MCK (_UL_(1) << 19) + +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: WS on PE0 mux C*/ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: WS */ +#define PIO_PE0C_I2SC1_WS (_UL_(1) << 0) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: CANRX1 on PC12 mux C*/ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_UL_(1) << 12) + +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: CANTX1 on PC14 mux C*/ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_UL_(1) << 14) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWMH2 on PC19 mux B*/ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_UL_(1) << 19) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWMH3 on PC13 mux B*/ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_UL_(1) << 13) + +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWMH3 on PC21 mux B*/ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_UL_(1) << 21) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWML0 on PC0 mux B*/ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_UL_(1) << 0) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWML1 on PC1 mux B*/ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_UL_(1) << 1) + +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWML1 on PC18 mux B*/ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_UL_(1) << 18) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWML2 on PC2 mux B*/ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_UL_(1) << 2) + +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWML2 on PC20 mux B*/ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_UL_(1) << 20) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWML3 on PC3 mux B*/ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_UL_(1) << 3) + +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWML3 on PC15 mux B*/ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWML3 on PC22 mux B*/ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_UL_(1) << 22) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: MISO on PC26 mux C*/ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: MISO */ +#define PIO_PC26C_SPI1_MISO (_UL_(1) << 26) + +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: MOSI on PC27 mux C*/ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: MOSI */ +#define PIO_PC27C_SPI1_MOSI (_UL_(1) << 27) + +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: NPCS0 on PC25 mux C*/ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_UL_(1) << 25) + +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: NPCS1 on PC28 mux C*/ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_UL_(1) << 28) + +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: NPCS1 on PD0 mux C*/ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_UL_(1) << 0) + +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: NPCS2 on PC29 mux C*/ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_UL_(1) << 29) + +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: NPCS2 on PD1 mux C*/ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_UL_(1) << 1) + +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: NPCS3 on PC30 mux C*/ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_UL_(1) << 30) + +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: NPCS3 on PD2 mux C*/ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_UL_(1) << 2) + +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPCK on PC24 mux C*/ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPCK */ +#define PIO_PC24C_SPI1_SPCK (_UL_(1) << 24) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TCLK3 on PC25 mux B*/ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_UL_(1) << 25) + +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TCLK4 on PC28 mux B*/ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_UL_(1) << 28) + +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TCLK5 on PC31 mux B*/ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_UL_(1) << 31) + +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TIOA3 on PC23 mux B*/ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_UL_(1) << 23) + +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TIOA4 on PC26 mux B*/ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_UL_(1) << 26) + +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TIOA5 on PC29 mux B*/ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_UL_(1) << 29) + +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TIOB3 on PC24 mux B*/ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_UL_(1) << 24) + +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TIOB4 on PC27 mux B*/ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_UL_(1) << 27) + +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TIOB5 on PC30 mux B*/ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_UL_(1) << 30) + +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TCLK6 on PC7 mux B*/ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_UL_(1) << 7) + +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TCLK7 on PC10 mux B*/ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_UL_(1) << 10) + +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TCLK8 on PC14 mux B*/ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_UL_(1) << 14) + +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TIOA6 on PC5 mux B*/ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_UL_(1) << 5) + +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TIOA7 on PC8 mux B*/ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_UL_(1) << 8) + +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TIOA8 on PC11 mux B*/ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_UL_(1) << 11) + +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TIOB6 on PC6 mux B*/ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_UL_(1) << 6) + +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TIOB7 on PC9 mux B*/ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_UL_(1) << 9) + +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TIOB8 on PC12 mux B*/ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_UL_(1) << 12) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TCLK9 on PE2 mux B*/ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_UL_(1) << 2) + +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TCLK10 on PE5 mux B*/ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_UL_(1) << 5) + +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TIOA9 on PE0 mux B*/ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_UL_(1) << 0) + +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TIOA10 on PE3 mux B*/ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_UL_(1) << 3) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TIOB9 on PE1 mux B*/ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_UL_(1) << 1) + +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TIOB10 on PE4 mux B*/ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_UL_(1) << 4) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70Q20B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/pio/same70q21b.h b/bsp/microchip/same70/bsp/same70b/include/pio/same70q21b.h new file mode 100644 index 0000000000..89677fa261 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/pio/same70q21b.h @@ -0,0 +1,1962 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70Q21B_PIO_H_ +#define _SAME70Q21B_PIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99) /**< Pin Number for PD3 */ +#define PIN_PD4 (100) /**< Pin Number for PD4 */ +#define PIN_PD5 (101) /**< Pin Number for PD5 */ +#define PIN_PD6 (102) /**< Pin Number for PD6 */ +#define PIN_PD7 (103) /**< Pin Number for PD7 */ +#define PIN_PD8 (104) /**< Pin Number for PD8 */ +#define PIN_PD9 (105) /**< Pin Number for PD9 */ +#define PIN_PD10 (106) /**< Pin Number for PD10 */ +#define PIN_PD11 (107) /**< Pin Number for PD11 */ +#define PIN_PD12 (108) /**< Pin Number for PD12 */ +#define PIN_PD13 (109) /**< Pin Number for PD13 */ +#define PIN_PD14 (110) /**< Pin Number for PD14 */ +#define PIN_PD15 (111) /**< Pin Number for PD15 */ +#define PIN_PD16 (112) /**< Pin Number for PD16 */ +#define PIN_PD17 (113) /**< Pin Number for PD17 */ +#define PIN_PD18 (114) /**< Pin Number for PD18 */ +#define PIN_PD19 (115) /**< Pin Number for PD19 */ +#define PIN_PD20 (116) /**< Pin Number for PD20 */ +#define PIN_PD21 (117) /**< Pin Number for PD21 */ +#define PIN_PD22 (118) /**< Pin Number for PD22 */ +#define PIN_PD23 (119) /**< Pin Number for PD23 */ +#define PIN_PD24 (120) /**< Pin Number for PD24 */ +#define PIN_PD25 (121) /**< Pin Number for PD25 */ +#define PIN_PD26 (122) /**< Pin Number for PD26 */ +#define PIN_PD27 (123) /**< Pin Number for PD27 */ +#define PIN_PD28 (124) /**< Pin Number for PD28 */ +#define PIN_PD29 (125) /**< Pin Number for PD29 */ +#define PIN_PD30 (126) /**< Pin Number for PD30 */ +#define PIN_PD31 (127) /**< Pin Number for PD31 */ +#define PIN_PE0 (128) /**< Pin Number for PE0 */ +#define PIN_PE1 (129) /**< Pin Number for PE1 */ +#define PIN_PE2 (130) /**< Pin Number for PE2 */ +#define PIN_PE3 (131) /**< Pin Number for PE3 */ +#define PIN_PE4 (132) /**< Pin Number for PE4 */ +#define PIN_PE5 (133) /**< Pin Number for PE5 */ + + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO Mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO Mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO Mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO Mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO Mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO Mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO Mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO Mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO Mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO Mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO Mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO Mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO Mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO Mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO Mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO Mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO Mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO Mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO Mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO Mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO Mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO Mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO Mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO Mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO Mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO Mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO Mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO Mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO Mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO Mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO Mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO Mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO Mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO Mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO Mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO Mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO Mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO Mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO Mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO Mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO Mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO Mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO Mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO Mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO Mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO Mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO Mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO Mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO Mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO Mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO Mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO Mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO Mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO Mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO Mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO Mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO Mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO Mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO Mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO Mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO Mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO Mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO Mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO Mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO Mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO Mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO Mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO Mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO Mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO Mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO Mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO Mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO Mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO Mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO Mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO Mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO Mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO Mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO Mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO Mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO Mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO Mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO Mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO Mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO Mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO Mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO Mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO Mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO Mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO Mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO Mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO Mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO Mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO Mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO Mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO Mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO Mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO Mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO Mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO Mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO Mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO Mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO Mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO Mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO Mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO Mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO Mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO Mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO Mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO Mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO Mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO Mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO Mask for PE5 */ + + +/* ========== Peripheral I/O indexes ========== */ +#define PIO_PA0_IDX ( 0) /**< PIO Index Number for PA0 */ +#define PIO_PA1_IDX ( 1) /**< PIO Index Number for PA1 */ +#define PIO_PA2_IDX ( 2) /**< PIO Index Number for PA2 */ +#define PIO_PA3_IDX ( 3) /**< PIO Index Number for PA3 */ +#define PIO_PA4_IDX ( 4) /**< PIO Index Number for PA4 */ +#define PIO_PA5_IDX ( 5) /**< PIO Index Number for PA5 */ +#define PIO_PA6_IDX ( 6) /**< PIO Index Number for PA6 */ +#define PIO_PA7_IDX ( 7) /**< PIO Index Number for PA7 */ +#define PIO_PA8_IDX ( 8) /**< PIO Index Number for PA8 */ +#define PIO_PA9_IDX ( 9) /**< PIO Index Number for PA9 */ +#define PIO_PA10_IDX ( 10) /**< PIO Index Number for PA10 */ +#define PIO_PA11_IDX ( 11) /**< PIO Index Number for PA11 */ +#define PIO_PA12_IDX ( 12) /**< PIO Index Number for PA12 */ +#define PIO_PA13_IDX ( 13) /**< PIO Index Number for PA13 */ +#define PIO_PA14_IDX ( 14) /**< PIO Index Number for PA14 */ +#define PIO_PA15_IDX ( 15) /**< PIO Index Number for PA15 */ +#define PIO_PA16_IDX ( 16) /**< PIO Index Number for PA16 */ +#define PIO_PA17_IDX ( 17) /**< PIO Index Number for PA17 */ +#define PIO_PA18_IDX ( 18) /**< PIO Index Number for PA18 */ +#define PIO_PA19_IDX ( 19) /**< PIO Index Number for PA19 */ +#define PIO_PA20_IDX ( 20) /**< PIO Index Number for PA20 */ +#define PIO_PA21_IDX ( 21) /**< PIO Index Number for PA21 */ +#define PIO_PA22_IDX ( 22) /**< PIO Index Number for PA22 */ +#define PIO_PA23_IDX ( 23) /**< PIO Index Number for PA23 */ +#define PIO_PA24_IDX ( 24) /**< PIO Index Number for PA24 */ +#define PIO_PA25_IDX ( 25) /**< PIO Index Number for PA25 */ +#define PIO_PA26_IDX ( 26) /**< PIO Index Number for PA26 */ +#define PIO_PA27_IDX ( 27) /**< PIO Index Number for PA27 */ +#define PIO_PA28_IDX ( 28) /**< PIO Index Number for PA28 */ +#define PIO_PA29_IDX ( 29) /**< PIO Index Number for PA29 */ +#define PIO_PA30_IDX ( 30) /**< PIO Index Number for PA30 */ +#define PIO_PA31_IDX ( 31) /**< PIO Index Number for PA31 */ +#define PIO_PB0_IDX ( 32) /**< PIO Index Number for PB0 */ +#define PIO_PB1_IDX ( 33) /**< PIO Index Number for PB1 */ +#define PIO_PB2_IDX ( 34) /**< PIO Index Number for PB2 */ +#define PIO_PB3_IDX ( 35) /**< PIO Index Number for PB3 */ +#define PIO_PB4_IDX ( 36) /**< PIO Index Number for PB4 */ +#define PIO_PB5_IDX ( 37) /**< PIO Index Number for PB5 */ +#define PIO_PB6_IDX ( 38) /**< PIO Index Number for PB6 */ +#define PIO_PB7_IDX ( 39) /**< PIO Index Number for PB7 */ +#define PIO_PB8_IDX ( 40) /**< PIO Index Number for PB8 */ +#define PIO_PB9_IDX ( 41) /**< PIO Index Number for PB9 */ +#define PIO_PB12_IDX ( 44) /**< PIO Index Number for PB12 */ +#define PIO_PB13_IDX ( 45) /**< PIO Index Number for PB13 */ +#define PIO_PC0_IDX ( 64) /**< PIO Index Number for PC0 */ +#define PIO_PC1_IDX ( 65) /**< PIO Index Number for PC1 */ +#define PIO_PC2_IDX ( 66) /**< PIO Index Number for PC2 */ +#define PIO_PC3_IDX ( 67) /**< PIO Index Number for PC3 */ +#define PIO_PC4_IDX ( 68) /**< PIO Index Number for PC4 */ +#define PIO_PC5_IDX ( 69) /**< PIO Index Number for PC5 */ +#define PIO_PC6_IDX ( 70) /**< PIO Index Number for PC6 */ +#define PIO_PC7_IDX ( 71) /**< PIO Index Number for PC7 */ +#define PIO_PC8_IDX ( 72) /**< PIO Index Number for PC8 */ +#define PIO_PC9_IDX ( 73) /**< PIO Index Number for PC9 */ +#define PIO_PC10_IDX ( 74) /**< PIO Index Number for PC10 */ +#define PIO_PC11_IDX ( 75) /**< PIO Index Number for PC11 */ +#define PIO_PC12_IDX ( 76) /**< PIO Index Number for PC12 */ +#define PIO_PC13_IDX ( 77) /**< PIO Index Number for PC13 */ +#define PIO_PC14_IDX ( 78) /**< PIO Index Number for PC14 */ +#define PIO_PC15_IDX ( 79) /**< PIO Index Number for PC15 */ +#define PIO_PC16_IDX ( 80) /**< PIO Index Number for PC16 */ +#define PIO_PC17_IDX ( 81) /**< PIO Index Number for PC17 */ +#define PIO_PC18_IDX ( 82) /**< PIO Index Number for PC18 */ +#define PIO_PC19_IDX ( 83) /**< PIO Index Number for PC19 */ +#define PIO_PC20_IDX ( 84) /**< PIO Index Number for PC20 */ +#define PIO_PC21_IDX ( 85) /**< PIO Index Number for PC21 */ +#define PIO_PC22_IDX ( 86) /**< PIO Index Number for PC22 */ +#define PIO_PC23_IDX ( 87) /**< PIO Index Number for PC23 */ +#define PIO_PC24_IDX ( 88) /**< PIO Index Number for PC24 */ +#define PIO_PC25_IDX ( 89) /**< PIO Index Number for PC25 */ +#define PIO_PC26_IDX ( 90) /**< PIO Index Number for PC26 */ +#define PIO_PC27_IDX ( 91) /**< PIO Index Number for PC27 */ +#define PIO_PC28_IDX ( 92) /**< PIO Index Number for PC28 */ +#define PIO_PC29_IDX ( 93) /**< PIO Index Number for PC29 */ +#define PIO_PC30_IDX ( 94) /**< PIO Index Number for PC30 */ +#define PIO_PC31_IDX ( 95) /**< PIO Index Number for PC31 */ +#define PIO_PD0_IDX ( 96) /**< PIO Index Number for PD0 */ +#define PIO_PD1_IDX ( 97) /**< PIO Index Number for PD1 */ +#define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */ +#define PIO_PD3_IDX ( 99) /**< PIO Index Number for PD3 */ +#define PIO_PD4_IDX (100) /**< PIO Index Number for PD4 */ +#define PIO_PD5_IDX (101) /**< PIO Index Number for PD5 */ +#define PIO_PD6_IDX (102) /**< PIO Index Number for PD6 */ +#define PIO_PD7_IDX (103) /**< PIO Index Number for PD7 */ +#define PIO_PD8_IDX (104) /**< PIO Index Number for PD8 */ +#define PIO_PD9_IDX (105) /**< PIO Index Number for PD9 */ +#define PIO_PD10_IDX (106) /**< PIO Index Number for PD10 */ +#define PIO_PD11_IDX (107) /**< PIO Index Number for PD11 */ +#define PIO_PD12_IDX (108) /**< PIO Index Number for PD12 */ +#define PIO_PD13_IDX (109) /**< PIO Index Number for PD13 */ +#define PIO_PD14_IDX (110) /**< PIO Index Number for PD14 */ +#define PIO_PD15_IDX (111) /**< PIO Index Number for PD15 */ +#define PIO_PD16_IDX (112) /**< PIO Index Number for PD16 */ +#define PIO_PD17_IDX (113) /**< PIO Index Number for PD17 */ +#define PIO_PD18_IDX (114) /**< PIO Index Number for PD18 */ +#define PIO_PD19_IDX (115) /**< PIO Index Number for PD19 */ +#define PIO_PD20_IDX (116) /**< PIO Index Number for PD20 */ +#define PIO_PD21_IDX (117) /**< PIO Index Number for PD21 */ +#define PIO_PD22_IDX (118) /**< PIO Index Number for PD22 */ +#define PIO_PD23_IDX (119) /**< PIO Index Number for PD23 */ +#define PIO_PD24_IDX (120) /**< PIO Index Number for PD24 */ +#define PIO_PD25_IDX (121) /**< PIO Index Number for PD25 */ +#define PIO_PD26_IDX (122) /**< PIO Index Number for PD26 */ +#define PIO_PD27_IDX (123) /**< PIO Index Number for PD27 */ +#define PIO_PD28_IDX (124) /**< PIO Index Number for PD28 */ +#define PIO_PD29_IDX (125) /**< PIO Index Number for PD29 */ +#define PIO_PD30_IDX (126) /**< PIO Index Number for PD30 */ +#define PIO_PD31_IDX (127) /**< PIO Index Number for PD31 */ +#define PIO_PE0_IDX (128) /**< PIO Index Number for PE0 */ +#define PIO_PE1_IDX (129) /**< PIO Index Number for PE1 */ +#define PIO_PE2_IDX (130) /**< PIO Index Number for PE2 */ +#define PIO_PE3_IDX (131) /**< PIO Index Number for PE3 */ +#define PIO_PE4_IDX (132) /**< PIO Index Number for PE4 */ +#define PIO_PE5_IDX (133) /**< PIO Index Number for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: ADTRG on PA8 mux B*/ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_UL_(1) << 8) + +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AD0 on PD30 mux X1*/ +#define PIO_PD30X1_AFEC0_AD0 (_UL_(1) << 30) + +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AD1 on PA21 mux X1*/ +#define PIO_PA21X1_AFEC0_AD1 (_UL_(1) << 21) + +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AD2 on PB3 mux X1*/ +#define PIO_PB3X1_AFEC0_AD2 (_UL_(1) << 3) + +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AD3 on PE5 mux X1*/ +#define PIO_PE5X1_AFEC0_AD3 (_UL_(1) << 5) + +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AD4 on PE4 mux X1*/ +#define PIO_PE4X1_AFEC0_AD4 (_UL_(1) << 4) + +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AD5 on PB2 mux X1*/ +#define PIO_PB2X1_AFEC0_AD5 (_UL_(1) << 2) + +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AD6 on PA17 mux X1*/ +#define PIO_PA17X1_AFEC0_AD6 (_UL_(1) << 17) + +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AD7 on PA18 mux X1*/ +#define PIO_PA18X1_AFEC0_AD7 (_UL_(1) << 18) + +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AD8 on PA19 mux X1*/ +#define PIO_PA19X1_AFEC0_AD8 (_UL_(1) << 19) + +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AD9 on PA20 mux X1*/ +#define PIO_PA20X1_AFEC0_AD9 (_UL_(1) << 20) + +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AD10 on PB0 mux X1*/ +#define PIO_PB0X1_AFEC0_AD10 (_UL_(1) << 0) + +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: ADTRG on PD9 mux C*/ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_UL_(1) << 9) + +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AD0 on PB1 mux X1*/ +#define PIO_PB1X1_AFEC1_AD0 (_UL_(1) << 1) + +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AD1 on PC13 mux X1*/ +#define PIO_PC13X1_AFEC1_AD1 (_UL_(1) << 13) + +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AD2 on PC15 mux X1*/ +#define PIO_PC15X1_AFEC1_AD2 (_UL_(1) << 15) + +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AD3 on PC12 mux X1*/ +#define PIO_PC12X1_AFEC1_AD3 (_UL_(1) << 12) + +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AD4 on PC29 mux X1*/ +#define PIO_PC29X1_AFEC1_AD4 (_UL_(1) << 29) + +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AD5 on PC30 mux X1*/ +#define PIO_PC30X1_AFEC1_AD5 (_UL_(1) << 30) + +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AD6 on PC31 mux X1*/ +#define PIO_PC31X1_AFEC1_AD6 (_UL_(1) << 31) + +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AD7 on PC26 mux X1*/ +#define PIO_PC26X1_AFEC1_AD7 (_UL_(1) << 26) + +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AD8 on PC27 mux X1*/ +#define PIO_PC27X1_AFEC1_AD8 (_UL_(1) << 27) + +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AD9 on PC0 mux X1*/ +#define PIO_PC0X1_AFEC1_AD9 (_UL_(1) << 0) + +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AD10 on PE3 mux X1*/ +#define PIO_PE3X1_AFEC1_AD10 (_UL_(1) << 3) + +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AD11 on PE0 mux X1*/ +#define PIO_PE0X1_AFEC1_AD11 (_UL_(1) << 0) + +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DAC0 on PB13 mux X1*/ +#define PIO_PB13X1_DACC_DAC0 (_UL_(1) << 13) + +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DAC1 on PD0 mux X1*/ +#define PIO_PD0X1_DACC_DAC1 (_UL_(1) << 0) + +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DATRG on PA2 mux C*/ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DATRG */ +#define PIO_PA2C_DACC_DATRG (_UL_(1) << 2) + +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: A0 on PC18 mux A*/ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: A0 */ +#define PIO_PC18A_EBI_A0 (_UL_(1) << 18) + +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: A1 on PC19 mux A*/ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: A1 */ +#define PIO_PC19A_EBI_A1 (_UL_(1) << 19) + +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: A2 on PC20 mux A*/ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: A2 */ +#define PIO_PC20A_EBI_A2 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: A3 on PC21 mux A*/ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: A3 */ +#define PIO_PC21A_EBI_A3 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: A4 on PC22 mux A*/ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: A4 */ +#define PIO_PC22A_EBI_A4 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: A5 on PC23 mux A*/ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: A5 */ +#define PIO_PC23A_EBI_A5 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: A6 on PC24 mux A*/ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: A6 */ +#define PIO_PC24A_EBI_A6 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: A7 on PC25 mux A*/ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: A7 */ +#define PIO_PC25A_EBI_A7 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: A8 on PC26 mux A*/ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: A8 */ +#define PIO_PC26A_EBI_A8 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: A9 on PC27 mux A*/ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: A9 */ +#define PIO_PC27A_EBI_A9 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: A10 on PC28 mux A*/ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: A10 */ +#define PIO_PC28A_EBI_A10 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: A11 on PC29 mux A*/ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: A11 */ +#define PIO_PC29A_EBI_A11 (_UL_(1) << 29) + +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: A12 on PC30 mux A*/ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: A12 */ +#define PIO_PC30A_EBI_A12 (_UL_(1) << 30) + +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: A13 on PC31 mux A*/ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: A13 */ +#define PIO_PC31A_EBI_A13 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: A14 on PA18 mux C*/ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: A14 */ +#define PIO_PA18C_EBI_A14 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: A15 on PA19 mux C*/ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: A15 */ +#define PIO_PA19C_EBI_A15 (_UL_(1) << 19) + +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: A16 on PA20 mux C*/ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: A16 */ +#define PIO_PA20C_EBI_A16 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: A17 on PA0 mux C*/ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: A17 */ +#define PIO_PA0C_EBI_A17 (_UL_(1) << 0) + +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: A18 on PA1 mux C*/ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: A18 */ +#define PIO_PA1C_EBI_A18 (_UL_(1) << 1) + +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: A19 on PA23 mux C*/ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: A19 */ +#define PIO_PA23C_EBI_A19 (_UL_(1) << 23) + +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: A20 on PA24 mux C*/ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: A20 */ +#define PIO_PA24C_EBI_A20 (_UL_(1) << 24) + +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: A21 on PC16 mux A*/ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: A21 */ +#define PIO_PC16A_EBI_A21 (_UL_(1) << 16) + +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: A22 on PC17 mux A*/ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: A22 */ +#define PIO_PC17A_EBI_A22 (_UL_(1) << 17) + +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: A23 on PA25 mux C*/ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: A23 */ +#define PIO_PA25C_EBI_A23 (_UL_(1) << 25) + +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: D0 on PC0 mux A*/ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: D0 */ +#define PIO_PC0A_EBI_D0 (_UL_(1) << 0) + +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: D1 on PC1 mux A*/ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: D1 */ +#define PIO_PC1A_EBI_D1 (_UL_(1) << 1) + +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: D2 on PC2 mux A*/ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: D2 */ +#define PIO_PC2A_EBI_D2 (_UL_(1) << 2) + +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: D3 on PC3 mux A*/ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: D3 */ +#define PIO_PC3A_EBI_D3 (_UL_(1) << 3) + +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: D4 on PC4 mux A*/ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: D4 */ +#define PIO_PC4A_EBI_D4 (_UL_(1) << 4) + +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: D5 on PC5 mux A*/ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: D5 */ +#define PIO_PC5A_EBI_D5 (_UL_(1) << 5) + +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: D6 on PC6 mux A*/ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: D6 */ +#define PIO_PC6A_EBI_D6 (_UL_(1) << 6) + +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: D7 on PC7 mux A*/ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: D7 */ +#define PIO_PC7A_EBI_D7 (_UL_(1) << 7) + +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: D8 on PE0 mux A*/ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: D8 */ +#define PIO_PE0A_EBI_D8 (_UL_(1) << 0) + +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: D9 on PE1 mux A*/ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: D9 */ +#define PIO_PE1A_EBI_D9 (_UL_(1) << 1) + +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: D10 on PE2 mux A*/ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: D10 */ +#define PIO_PE2A_EBI_D10 (_UL_(1) << 2) + +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: D11 on PE3 mux A*/ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: D11 */ +#define PIO_PE3A_EBI_D11 (_UL_(1) << 3) + +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: D12 on PE4 mux A*/ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: D12 */ +#define PIO_PE4A_EBI_D12 (_UL_(1) << 4) + +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: D13 on PE5 mux A*/ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: D13 */ +#define PIO_PE5A_EBI_D13 (_UL_(1) << 5) + +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: D14 on PA15 mux A*/ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: D14 */ +#define PIO_PA15A_EBI_D14 (_UL_(1) << 15) + +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: D15 on PA16 mux A*/ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: D15 */ +#define PIO_PA16A_EBI_D15 (_UL_(1) << 16) + +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: NWAIT on PC13 mux A*/ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_UL_(1) << 13) + +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: NCS0 on PC14 mux A*/ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_UL_(1) << 14) + +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: NCS1 on PC15 mux A*/ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_UL_(1) << 15) + +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: NCS1 on PD18 mux A*/ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_UL_(1) << 18) + +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: NCS2 on PA22 mux C*/ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_UL_(1) << 22) + +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: NCS3 on PC12 mux A*/ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_UL_(1) << 12) + +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: NCS3 on PD19 mux A*/ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_UL_(1) << 19) + +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: NWR0 on PC8 mux A*/ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_UL_(1) << 8) + +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: NWR1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_UL_(1) << 15) + +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: NRD on PC11 mux A*/ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: NRD */ +#define PIO_PC11A_EBI_NRD (_UL_(1) << 11) + +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: NWE on PC8 mux A*/ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: NWE */ +#define PIO_PC8A_EBI_NWE (_UL_(1) << 8) + +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: NBS0 on PC18 mux A*/ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: NBS1 on PD15 mux C*/ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_UL_(1) << 15) + +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: NANDALE on PC16 mux A*/ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_UL_(1) << 16) + +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: NANDCLE on PC17 mux A*/ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_UL_(1) << 17) + +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: NANDOE on PC9 mux A*/ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_UL_(1) << 9) + +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: NANDWE on PC10 mux A*/ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_UL_(1) << 10) + +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: SDCK on PD23 mux C*/ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: SDCK */ +#define PIO_PD23C_EBI_SDCK (_UL_(1) << 23) + +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: SDCKE on PD14 mux C*/ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_UL_(1) << 14) + +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: SDCS on PC15 mux A*/ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PC15A_EBI_SDCS (_UL_(1) << 15) + +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: SDCS on PD18 mux A*/ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: SDCS */ +#define PIO_PD18A_EBI_SDCS (_UL_(1) << 18) + +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: BA0 on PA20 mux C*/ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: BA0 */ +#define PIO_PA20C_EBI_BA0 (_UL_(1) << 20) + +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: BA1 on PA0 mux C*/ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: BA1 */ +#define PIO_PA0C_EBI_BA1 (_UL_(1) << 0) + +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: SDWE on PD29 mux C*/ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: SDWE */ +#define PIO_PD29C_EBI_SDWE (_UL_(1) << 29) + +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: RAS on PD16 mux C*/ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: RAS */ +#define PIO_PD16C_EBI_RAS (_UL_(1) << 16) + +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: CAS on PD17 mux C*/ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: CAS */ +#define PIO_PD17C_EBI_CAS (_UL_(1) << 17) + +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: SDA10 on PC13 mux C*/ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: SDA10 on PD13 mux C*/ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_UL_(1) << 13) + +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: SDA0 on PC20 mux A*/ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_UL_(1) << 20) + +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: SDA1 on PC21 mux A*/ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_UL_(1) << 21) + +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: SDA2 on PC22 mux A*/ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_UL_(1) << 22) + +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: SDA3 on PC23 mux A*/ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_UL_(1) << 23) + +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: SDA4 on PC24 mux A*/ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_UL_(1) << 24) + +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: SDA5 on PC25 mux A*/ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_UL_(1) << 25) + +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: SDA6 on PC26 mux A*/ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_UL_(1) << 26) + +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: SDA7 on PC27 mux A*/ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_UL_(1) << 27) + +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: SDA8 on PC28 mux A*/ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_UL_(1) << 28) + +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: SDA9 on PC29 mux A*/ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_UL_(1) << 29) + +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: SDA11 on PC31 mux A*/ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_UL_(1) << 31) + +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: SDA12 on PA18 mux C*/ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_UL_(1) << 18) + +#define PIN_PA19C_EBI_SDA13 _L_(19) /**< EBI signal: SDA13 on PA19 mux C*/ +#define MUX_PA19C_EBI_SDA13 _L_(2) /**< EBI signal line function value: SDA13 */ +#define PIO_PA19C_EBI_SDA13 (_UL_(1) << 19) + +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: DQM0 on PC18 mux A*/ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_UL_(1) << 18) + +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: DQM1 on PD15 mux C*/ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_UL_(1) << 15) + +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: ERASE on PB12 mux X1*/ +#define PIO_PB12X1_EFC_ERASE (_UL_(1) << 12) + +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GCOL on PD13 mux A*/ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GCOL */ +#define PIO_PD13A_GMAC_GCOL (_UL_(1) << 13) + +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GCRS on PD10 mux A*/ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GCRS */ +#define PIO_PD10A_GMAC_GCRS (_UL_(1) << 10) + +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMDC on PD8 mux A*/ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMDC */ +#define PIO_PD8A_GMAC_GMDC (_UL_(1) << 8) + +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMDIO on PD9 mux A*/ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_UL_(1) << 9) + +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GRXCK on PD14 mux A*/ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_UL_(1) << 14) + +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GRXDV on PD4 mux A*/ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_UL_(1) << 4) + +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GRXER on PD7 mux A*/ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GRXER */ +#define PIO_PD7A_GMAC_GRXER (_UL_(1) << 7) + +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GRX0 on PD5 mux A*/ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_UL_(1) << 5) + +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GRX1 on PD6 mux A*/ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_UL_(1) << 6) + +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GRX2 on PD11 mux A*/ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_UL_(1) << 11) + +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GRX3 on PD12 mux A*/ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_UL_(1) << 12) + +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GTSUCOMP on PB1 mux B*/ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_UL_(1) << 1) + +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GTSUCOMP on PB12 mux B*/ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_UL_(1) << 12) + +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GTSUCOMP on PD11 mux C*/ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_UL_(1) << 11) + +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GTSUCOMP on PD20 mux C*/ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_UL_(1) << 20) + +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GTXCK on PD0 mux A*/ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_UL_(1) << 0) + +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GTXEN on PD1 mux A*/ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_UL_(1) << 1) + +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GTXER on PD17 mux A*/ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GTXER */ +#define PIO_PD17A_GMAC_GTXER (_UL_(1) << 17) + +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A*/ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_UL_(1) << 2) + +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GTX1 on PD3 mux A*/ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_UL_(1) << 3) + +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GTX2 on PD15 mux A*/ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_UL_(1) << 15) + +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GTX3 on PD16 mux A*/ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_UL_(1) << 16) + +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: MCCDA on PA28 mux C*/ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_UL_(1) << 28) + +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: MCCK on PA25 mux D*/ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_UL_(1) << 25) + +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: MCDA0 on PA30 mux C*/ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_UL_(1) << 30) + +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: MCDA1 on PA31 mux C*/ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_UL_(1) << 31) + +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: MCDA2 on PA26 mux C*/ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_UL_(1) << 26) + +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: MCDA3 on PA27 mux C*/ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_UL_(1) << 27) + +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: CK on PA1 mux D*/ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: CK */ +#define PIO_PA1D_I2SC0_CK (_UL_(1) << 1) + +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: DI0 on PA16 mux D*/ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_UL_(1) << 16) + +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: DO0 on PA30 mux D*/ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_UL_(1) << 30) + +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: MCK on PA0 mux D*/ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: MCK */ +#define PIO_PA0D_I2SC0_MCK (_UL_(1) << 0) + +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: WS on PA15 mux D*/ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: WS */ +#define PIO_PA15D_I2SC0_WS (_UL_(1) << 15) + +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: CK on PA20 mux D*/ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: CK */ +#define PIO_PA20D_I2SC1_CK (_UL_(1) << 20) + +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: DI0 on PE2 mux C*/ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_UL_(1) << 2) + +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: DO0 on PE1 mux C*/ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_UL_(1) << 1) + +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: MCK on PA19 mux D*/ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: MCK */ +#define PIO_PA19D_I2SC1_MCK (_UL_(1) << 19) + +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: WS on PE0 mux C*/ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: WS */ +#define PIO_PE0C_I2SC1_WS (_UL_(1) << 0) + +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: D0 on PD22 mux D*/ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: D0 */ +#define PIO_PD22D_ISI_D0 (_UL_(1) << 22) + +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: D1 on PD21 mux D*/ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: D1 */ +#define PIO_PD21D_ISI_D1 (_UL_(1) << 21) + +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: D2 on PB3 mux D*/ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: D2 */ +#define PIO_PB3D_ISI_D2 (_UL_(1) << 3) + +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: D3 on PA9 mux B*/ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: D3 */ +#define PIO_PA9B_ISI_D3 (_UL_(1) << 9) + +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: D4 on PA5 mux B*/ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: D4 */ +#define PIO_PA5B_ISI_D4 (_UL_(1) << 5) + +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: D5 on PD11 mux D*/ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: D5 */ +#define PIO_PD11D_ISI_D5 (_UL_(1) << 11) + +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: D6 on PD12 mux D*/ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: D6 */ +#define PIO_PD12D_ISI_D6 (_UL_(1) << 12) + +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: D7 on PA27 mux D*/ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: D7 */ +#define PIO_PA27D_ISI_D7 (_UL_(1) << 27) + +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: D8 on PD27 mux D*/ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: D8 */ +#define PIO_PD27D_ISI_D8 (_UL_(1) << 27) + +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: D9 on PD28 mux D*/ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: D9 */ +#define PIO_PD28D_ISI_D9 (_UL_(1) << 28) + +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: D10 on PD30 mux D*/ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: D10 */ +#define PIO_PD30D_ISI_D10 (_UL_(1) << 30) + +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: D11 on PD31 mux D*/ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: D11 */ +#define PIO_PD31D_ISI_D11 (_UL_(1) << 31) + +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: HSYNC on PD24 mux D*/ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_UL_(1) << 24) + +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: PCK on PA24 mux D*/ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: PCK */ +#define PIO_PA24D_ISI_PCK (_UL_(1) << 24) + +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: VSYNC on PD25 mux D*/ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_UL_(1) << 25) + +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: CANRX0 on PB3 mux A*/ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_UL_(1) << 3) + +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: CANTX0 on PB2 mux A*/ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_UL_(1) << 2) + +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: CANRX1 on PC12 mux C*/ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_UL_(1) << 12) + +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: CANTX1 on PC14 mux C*/ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_UL_(1) << 14) + +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: CANTX1 on PD12 mux B*/ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_UL_(1) << 12) + +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PCK0 on PA6 mux B*/ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_UL_(1) << 6) + +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PCK0 on PB12 mux D*/ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_UL_(1) << 12) + +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PCK0 on PB13 mux B*/ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_UL_(1) << 13) + +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PCK1 on PA17 mux B*/ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_UL_(1) << 17) + +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PCK1 on PA21 mux B*/ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_UL_(1) << 21) + +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PCK2 on PA3 mux C*/ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PCK2 on PA18 mux B*/ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_UL_(1) << 18) + +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PCK2 on PA31 mux B*/ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PCK2 on PB3 mux B*/ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_UL_(1) << 3) + +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PCK2 on PD31 mux C*/ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_UL_(1) << 31) + +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: XIN on PB9 mux X1*/ +#define PIO_PB9X1_PMC_XIN (_UL_(1) << 9) + +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: XOUT on PB8 mux X1*/ +#define PIO_PB8X1_PMC_XOUT (_UL_(1) << 8) + +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: XIN32 on PA7 mux X1*/ +#define PIO_PA7X1_PMC_XIN32 (_UL_(1) << 7) + +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: XOUT32 on PA8 mux X1*/ +#define PIO_PA8X1_PMC_XOUT32 (_UL_(1) << 8) + +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWMEXTRG0 on PA10 mux B*/ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_UL_(1) << 10) + +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWMEXTRG1 on PA22 mux B*/ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_UL_(1) << 22) + +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWMFI0 on PA9 mux C*/ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_UL_(1) << 9) + +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWMFI1 on PD8 mux B*/ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_UL_(1) << 8) + +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWMFI2 on PD9 mux B*/ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_UL_(1) << 9) + +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWMH0 on PA0 mux A*/ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWMH0 on PA11 mux B*/ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWMH0 on PA23 mux B*/ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_UL_(1) << 23) + +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWMH0 on PB0 mux A*/ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_UL_(1) << 0) + +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWMH0 on PD11 mux B*/ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_UL_(1) << 11) + +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWMH0 on PD20 mux A*/ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_UL_(1) << 20) + +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWMH1 on PA2 mux A*/ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_UL_(1) << 2) + +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWMH1 on PA12 mux B*/ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_UL_(1) << 12) + +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWMH1 on PA24 mux B*/ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_UL_(1) << 24) + +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWMH1 on PB1 mux A*/ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_UL_(1) << 1) + +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWMH1 on PD21 mux A*/ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_UL_(1) << 21) + +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWMH2 on PA13 mux B*/ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_UL_(1) << 13) + +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWMH2 on PA25 mux B*/ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_UL_(1) << 25) + +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWMH2 on PB4 mux B*/ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_UL_(1) << 4) + +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWMH2 on PC19 mux B*/ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_UL_(1) << 19) + +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWMH2 on PD22 mux A*/ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_UL_(1) << 22) + +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWMH3 on PA7 mux B*/ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_UL_(1) << 7) + +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWMH3 on PA14 mux B*/ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_UL_(1) << 14) + +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWMH3 on PA17 mux C*/ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_UL_(1) << 17) + +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWMH3 on PC13 mux B*/ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_UL_(1) << 13) + +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWMH3 on PC21 mux B*/ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_UL_(1) << 21) + +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWMH3 on PD23 mux A*/ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_UL_(1) << 23) + +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWML0 on PA1 mux A*/ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_UL_(1) << 1) + +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWML0 on PA19 mux B*/ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_UL_(1) << 19) + +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWML0 on PB5 mux B*/ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_UL_(1) << 5) + +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWML0 on PC0 mux B*/ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_UL_(1) << 0) + +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWML0 on PD10 mux B*/ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_UL_(1) << 10) + +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWML0 on PD24 mux A*/ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_UL_(1) << 24) + +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWML1 on PA20 mux B*/ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_UL_(1) << 20) + +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWML1 on PB12 mux A*/ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_UL_(1) << 12) + +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWML1 on PC1 mux B*/ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_UL_(1) << 1) + +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWML1 on PC18 mux B*/ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_UL_(1) << 18) + +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWML1 on PD25 mux A*/ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_UL_(1) << 25) + +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWML2 on PA16 mux C*/ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_UL_(1) << 16) + +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWML2 on PA30 mux A*/ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_UL_(1) << 30) + +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWML2 on PB13 mux A*/ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_UL_(1) << 13) + +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWML2 on PC2 mux B*/ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_UL_(1) << 2) + +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWML2 on PC20 mux B*/ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_UL_(1) << 20) + +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWML2 on PD26 mux A*/ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_UL_(1) << 26) + +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWML3 on PA15 mux C*/ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWML3 on PC3 mux B*/ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_UL_(1) << 3) + +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWML3 on PC15 mux B*/ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_UL_(1) << 15) + +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWML3 on PC22 mux B*/ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_UL_(1) << 22) + +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWML3 on PD27 mux A*/ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_UL_(1) << 27) + +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWMEXTRG0 on PA30 mux B*/ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_UL_(1) << 30) + +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWMEXTRG1 on PA18 mux A*/ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_UL_(1) << 18) + +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWMFI0 on PA21 mux C*/ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_UL_(1) << 21) + +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWMFI1 on PA26 mux D*/ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_UL_(1) << 26) + +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWMFI2 on PA28 mux D*/ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_UL_(1) << 28) + +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWMH0 on PA12 mux C*/ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_UL_(1) << 12) + +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWMH0 on PD1 mux B*/ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_UL_(1) << 1) + +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWMH1 on PA14 mux C*/ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_UL_(1) << 14) + +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWMH1 on PD3 mux B*/ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_UL_(1) << 3) + +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWMH2 on PA31 mux D*/ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_UL_(1) << 31) + +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWMH2 on PD5 mux B*/ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_UL_(1) << 5) + +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWMH3 on PA8 mux A*/ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_UL_(1) << 8) + +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWMH3 on PD7 mux B*/ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_UL_(1) << 7) + +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWML0 on PA11 mux C*/ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_UL_(1) << 11) + +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWML0 on PD0 mux B*/ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_UL_(1) << 0) + +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWML1 on PA13 mux C*/ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_UL_(1) << 13) + +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux B*/ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_UL_(1) << 2) + +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWML2 on PA23 mux D*/ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_UL_(1) << 23) + +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWML2 on PD4 mux B*/ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_UL_(1) << 4) + +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWML3 on PA5 mux A*/ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_UL_(1) << 5) + +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWML3 on PD6 mux B*/ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_UL_(1) << 6) + +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QCS on PA11 mux A*/ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QCS */ +#define PIO_PA11A_QSPI_QCS (_UL_(1) << 11) + +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QIO0 on PA13 mux A*/ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_UL_(1) << 13) + +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QIO1 on PA12 mux A*/ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_UL_(1) << 12) + +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QIO2 on PA17 mux A*/ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_UL_(1) << 17) + +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QIO3 on PD31 mux A*/ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_UL_(1) << 31) + +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSCK on PA14 mux A*/ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSCK */ +#define PIO_PA14A_QSPI_QSCK (_UL_(1) << 14) + +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTCOUT0 on PB0 mux X1*/ +#define PIO_PB0X1_RTC_RTCOUT0 (_UL_(1) << 0) + +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTCOUT1 on PB1 mux X1*/ +#define PIO_PB1X1_RTC_RTCOUT1 (_UL_(1) << 1) + +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: MISO on PD20 mux B*/ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: MISO */ +#define PIO_PD20B_SPI0_MISO (_UL_(1) << 20) + +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: MOSI on PD21 mux B*/ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: MOSI */ +#define PIO_PD21B_SPI0_MOSI (_UL_(1) << 21) + +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: NPCS0 on PB2 mux D*/ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_UL_(1) << 2) + +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: NPCS1 on PA31 mux A*/ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_UL_(1) << 31) + +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: NPCS1 on PD25 mux B*/ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_UL_(1) << 25) + +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: NPCS2 on PD12 mux C*/ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_UL_(1) << 12) + +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: NPCS3 on PD27 mux B*/ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_UL_(1) << 27) + +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPCK on PD22 mux B*/ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPCK */ +#define PIO_PD22B_SPI0_SPCK (_UL_(1) << 22) + +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: MISO on PC26 mux C*/ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: MISO */ +#define PIO_PC26C_SPI1_MISO (_UL_(1) << 26) + +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: MOSI on PC27 mux C*/ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: MOSI */ +#define PIO_PC27C_SPI1_MOSI (_UL_(1) << 27) + +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: NPCS0 on PC25 mux C*/ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_UL_(1) << 25) + +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: NPCS1 on PC28 mux C*/ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_UL_(1) << 28) + +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: NPCS1 on PD0 mux C*/ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_UL_(1) << 0) + +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: NPCS2 on PC29 mux C*/ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_UL_(1) << 29) + +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: NPCS2 on PD1 mux C*/ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_UL_(1) << 1) + +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: NPCS3 on PC30 mux C*/ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_UL_(1) << 30) + +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: NPCS3 on PD2 mux C*/ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_UL_(1) << 2) + +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPCK on PC24 mux C*/ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPCK */ +#define PIO_PC24C_SPI1_SPCK (_UL_(1) << 24) + +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: RD on PA10 mux C*/ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: RD */ +#define PIO_PA10C_SSC_RD (_UL_(1) << 10) + +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: RF on PD24 mux B*/ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: RF */ +#define PIO_PD24B_SSC_RF (_UL_(1) << 24) + +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: RK on PA22 mux A*/ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: RK */ +#define PIO_PA22A_SSC_RK (_UL_(1) << 22) + +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: TD on PB5 mux D*/ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: TD */ +#define PIO_PB5D_SSC_TD (_UL_(1) << 5) + +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: TD on PD10 mux C*/ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: TD */ +#define PIO_PD10C_SSC_TD (_UL_(1) << 10) + +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: TD on PD26 mux B*/ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: TD */ +#define PIO_PD26B_SSC_TD (_UL_(1) << 26) + +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: TF on PB0 mux D*/ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: TF */ +#define PIO_PB0D_SSC_TF (_UL_(1) << 0) + +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: TK on PB1 mux D*/ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: TK */ +#define PIO_PB1D_SSC_TK (_UL_(1) << 1) + +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: WKUP0 on PA0 mux X1*/ +#define PIO_PA0X1_SUPC_WKUP0 (_UL_(1) << 0) + +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: WKUP1 on PA1 mux X1*/ +#define PIO_PA1X1_SUPC_WKUP1 (_UL_(1) << 1) + +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: WKUP2 on PA2 mux X1*/ +#define PIO_PA2X1_SUPC_WKUP2 (_UL_(1) << 2) + +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: WKUP3 on PA4 mux X1*/ +#define PIO_PA4X1_SUPC_WKUP3 (_UL_(1) << 4) + +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: WKUP4 on PA5 mux X1*/ +#define PIO_PA5X1_SUPC_WKUP4 (_UL_(1) << 5) + +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: WKUP6 on PA9 mux X1*/ +#define PIO_PA9X1_SUPC_WKUP6 (_UL_(1) << 9) + +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: WKUP7 on PA11 mux X1*/ +#define PIO_PA11X1_SUPC_WKUP7 (_UL_(1) << 11) + +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: WKUP8 on PA14 mux X1*/ +#define PIO_PA14X1_SUPC_WKUP8 (_UL_(1) << 14) + +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: WKUP9 on PA19 mux X1*/ +#define PIO_PA19X1_SUPC_WKUP9 (_UL_(1) << 19) + +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: WKUP10 on PA20 mux X1*/ +#define PIO_PA20X1_SUPC_WKUP10 (_UL_(1) << 20) + +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: WKUP11 on PA30 mux X1*/ +#define PIO_PA30X1_SUPC_WKUP11 (_UL_(1) << 30) + +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: WKUP12 on PB3 mux X1*/ +#define PIO_PB3X1_SUPC_WKUP12 (_UL_(1) << 3) + +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: WKUP13 on PB5 mux X1*/ +#define PIO_PB5X1_SUPC_WKUP13 (_UL_(1) << 5) + +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: WKUP5 on PD28 mux X1*/ +#define PIO_PD28X1_SUPC_WKUP5 (_UL_(1) << 28) + +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TCLK0 on PA4 mux B*/ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_UL_(1) << 4) + +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TCLK1 on PA28 mux B*/ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_UL_(1) << 28) + +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TCLK2 on PA29 mux B*/ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_UL_(1) << 29) + +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TIOA0 on PA0 mux B*/ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_UL_(1) << 0) + +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TIOA1 on PA15 mux B*/ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_UL_(1) << 15) + +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TIOA2 on PA26 mux B*/ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_UL_(1) << 26) + +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TIOB0 on PA1 mux B*/ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_UL_(1) << 1) + +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TIOB1 on PA16 mux B*/ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_UL_(1) << 16) + +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TIOB2 on PA27 mux B*/ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_UL_(1) << 27) + +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TCLK3 on PC25 mux B*/ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_UL_(1) << 25) + +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TCLK4 on PC28 mux B*/ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_UL_(1) << 28) + +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TCLK5 on PC31 mux B*/ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_UL_(1) << 31) + +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TIOA3 on PC23 mux B*/ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_UL_(1) << 23) + +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TIOA4 on PC26 mux B*/ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_UL_(1) << 26) + +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TIOA5 on PC29 mux B*/ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_UL_(1) << 29) + +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TIOB3 on PC24 mux B*/ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_UL_(1) << 24) + +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TIOB4 on PC27 mux B*/ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_UL_(1) << 27) + +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TIOB5 on PC30 mux B*/ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_UL_(1) << 30) + +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TCLK6 on PC7 mux B*/ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_UL_(1) << 7) + +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TCLK7 on PC10 mux B*/ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_UL_(1) << 10) + +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TCLK8 on PC14 mux B*/ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_UL_(1) << 14) + +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TIOA6 on PC5 mux B*/ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_UL_(1) << 5) + +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TIOA7 on PC8 mux B*/ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_UL_(1) << 8) + +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TIOA8 on PC11 mux B*/ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_UL_(1) << 11) + +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TIOB6 on PC6 mux B*/ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_UL_(1) << 6) + +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TIOB7 on PC9 mux B*/ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_UL_(1) << 9) + +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TIOB8 on PC12 mux B*/ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_UL_(1) << 12) + +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TCLK9 on PE2 mux B*/ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_UL_(1) << 2) + +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TCLK10 on PE5 mux B*/ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_UL_(1) << 5) + +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TCLK11 on PD24 mux C*/ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_UL_(1) << 24) + +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TIOA9 on PE0 mux B*/ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_UL_(1) << 0) + +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TIOA10 on PE3 mux B*/ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_UL_(1) << 3) + +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TIOA11 on PD21 mux C*/ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_UL_(1) << 21) + +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TIOB9 on PE1 mux B*/ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_UL_(1) << 1) + +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TIOB10 on PE4 mux B*/ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_UL_(1) << 4) + +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TIOB11 on PD22 mux C*/ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_UL_(1) << 22) + +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWCK0 on PA4 mux A*/ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_UL_(1) << 4) + +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWD0 on PA3 mux A*/ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_UL_(1) << 3) + +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWCK1 on PB5 mux A*/ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_UL_(1) << 5) + +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWD1 on PB4 mux A*/ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_UL_(1) << 4) + +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWCK2 on PD28 mux C*/ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_UL_(1) << 28) + +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWD2 on PD27 mux C*/ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_UL_(1) << 27) + +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: URXD0 on PA9 mux A*/ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_UL_(1) << 9) + +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UTXD0 on PA10 mux A*/ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_UL_(1) << 10) + +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: URXD1 on PA5 mux C*/ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_UL_(1) << 5) + +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UTXD1 on PA4 mux C*/ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_UL_(1) << 4) + +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UTXD1 on PA6 mux C*/ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_UL_(1) << 6) + +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UTXD1 on PD26 mux D*/ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_UL_(1) << 26) + +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: URXD2 on PD25 mux C*/ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_UL_(1) << 25) + +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UTXD2 on PD26 mux C*/ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_UL_(1) << 26) + +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: URXD3 on PD28 mux A*/ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_UL_(1) << 28) + +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UTXD3 on PD30 mux A*/ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_UL_(1) << 30) + +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UTXD3 on PD31 mux B*/ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_UL_(1) << 31) + +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: URXD4 on PD18 mux C*/ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_UL_(1) << 18) + +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UTXD4 on PD3 mux C*/ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_UL_(1) << 3) + +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UTXD4 on PD19 mux C*/ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_UL_(1) << 19) + +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: CTS0 on PB2 mux C*/ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_UL_(1) << 2) + +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: DCD0 on PD0 mux D*/ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_UL_(1) << 0) + +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux D*/ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_UL_(1) << 2) + +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: DTR0 on PD1 mux D*/ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_UL_(1) << 1) + +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: RI0 on PD3 mux D*/ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: RI0 */ +#define PIO_PD3D_USART0_RI0 (_UL_(1) << 3) + +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: RTS0 on PB3 mux C*/ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_UL_(1) << 3) + +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: RXD0 on PB0 mux C*/ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_UL_(1) << 0) + +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: SCK0 on PB13 mux C*/ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_UL_(1) << 13) + +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: TXD0 on PB1 mux C*/ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_UL_(1) << 1) + +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: CTS1 on PA25 mux A*/ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_UL_(1) << 25) + +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: DCD1 on PA26 mux A*/ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_UL_(1) << 26) + +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: DSR1 on PA28 mux A*/ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_UL_(1) << 28) + +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: DTR1 on PA27 mux A*/ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_UL_(1) << 27) + +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: LONCOL1 on PA3 mux B*/ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_UL_(1) << 3) + +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: RI1 on PA29 mux A*/ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: RI1 */ +#define PIO_PA29A_USART1_RI1 (_UL_(1) << 29) + +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: RTS1 on PA24 mux A*/ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_UL_(1) << 24) + +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: RXD1 on PA21 mux A*/ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_UL_(1) << 21) + +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: SCK1 on PA23 mux A*/ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_UL_(1) << 23) + +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: TXD1 on PB4 mux D*/ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_UL_(1) << 4) + +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: CTS2 on PD19 mux B*/ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_UL_(1) << 19) + +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: DCD2 on PD4 mux D*/ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_UL_(1) << 4) + +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: DSR2 on PD6 mux D*/ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_UL_(1) << 6) + +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: DTR2 on PD5 mux D*/ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_UL_(1) << 5) + +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: RI2 on PD7 mux D*/ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: RI2 */ +#define PIO_PD7D_USART2_RI2 (_UL_(1) << 7) + +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: RTS2 on PD18 mux B*/ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_UL_(1) << 18) + +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: RXD2 on PD15 mux B*/ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_UL_(1) << 15) + +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: SCK2 on PD17 mux B*/ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_UL_(1) << 17) + +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: TXD2 on PD16 mux B*/ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_UL_(1) << 16) + +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: TDI on PB4 mux X1*/ +#define PIO_PB4X1_ICE_TDI (_UL_(1) << 4) + +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: TDO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TDO (_UL_(1) << 5) + +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: TRACESWO on PB5 mux X1*/ +#define PIO_PB5X1_ICE_TRACESWO (_UL_(1) << 5) + +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: TMS on PB6 mux X1*/ +#define PIO_PB6X1_ICE_TMS (_UL_(1) << 6) + +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: SWDIO on PB6 mux X1*/ +#define PIO_PB6X1_ICE_SWDIO (_UL_(1) << 6) + +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: TCK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_TCK (_UL_(1) << 7) + +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: SWDCLK on PB7 mux X1*/ +#define PIO_PB7X1_ICE_SWDCLK (_UL_(1) << 7) + +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TRACECLK on PD8 mux D*/ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_UL_(1) << 8) + +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TRACED0 on PD4 mux C*/ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_UL_(1) << 4) + +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TRACED1 on PD5 mux C*/ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_UL_(1) << 5) + +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TRACED2 on PD6 mux C*/ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_UL_(1) << 6) + +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TRACED3 on PD7 mux C*/ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_UL_(1) << 7) + + +#endif /* _SAME70Q21B_PIO_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/sam.h b/bsp/microchip/same70/bsp/same70b/include/sam.h new file mode 100644 index 0000000000..a5bb2a4c45 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/sam.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME70J19B__) || defined(__ATSAME70J19B__) +#include "same70j19b.h" +#elif defined(__SAME70J20B__) || defined(__ATSAME70J20B__) +#include "same70j20b.h" +#elif defined(__SAME70J21B__) || defined(__ATSAME70J21B__) +#include "same70j21b.h" +#elif defined(__SAME70N19B__) || defined(__ATSAME70N19B__) +#include "same70n19b.h" +#elif defined(__SAME70N20B__) || defined(__ATSAME70N20B__) +#include "same70n20b.h" +#elif defined(__SAME70N21B__) || defined(__ATSAME70N21B__) +#include "same70n21b.h" +#elif defined(__SAME70Q19B__) || defined(__ATSAME70Q19B__) +#include "same70q19b.h" +#elif defined(__SAME70Q20B__) || defined(__ATSAME70Q20B__) +#include "same70q20b.h" +#elif defined(__SAME70Q21B__) || defined(__ATSAME70Q21B__) +#include "same70q21b.h" +#else +#error Library does not support the specified device +#endif + +#endif /* _SAM_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70j19b.h b/bsp/microchip/same70/bsp/same70b/include/same70j19b.h new file mode 100644 index 0000000000..5f6d950bc0 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70j19b.h @@ -0,0 +1,853 @@ +/** + * \file + * + * \brief Header file for ATSAME70J19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:37Z */ +#ifndef _SAME70J19B_H_ +#define _SAME70J19B_H_ + +/** \addtogroup SAME70J19B_definitions SAME70J19B definitions + This file defines all structures and symbols for SAME70J19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70J19B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70J19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70J19B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70J19B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70J19B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70J19B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70J19B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70J19B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70J19B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70J19B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70J19B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70J19B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70J19B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16 , /**< 16 SAME70J19B Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70J19B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70J19B Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22 , /**< 22 SAME70J19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70J19B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70J19B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70J19B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70J19B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70J19B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70J19B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70J19B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70J19B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70J19B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70J19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70J19B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70J19B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70J19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70J19B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39 , /**< 39 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70J19B Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43 , /**< 43 SAME70J19B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70J19B Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47 , /**< 47 SAME70J19B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70J19B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70J19B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70J19B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70J19B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70J19B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70J19B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70J19B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70J19B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70J19B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70J19B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70J19B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70J19B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70J19B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70J19B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70J19B Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70J19B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70J19B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70J19B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70J19B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70J19B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70J19B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70J19B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70J19B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70J19B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70J19B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70J19B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 SAME70J19B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 SAME70J19B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70J19B Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 SAME70J19B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70J19B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70J19B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70J19B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70J19B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70J19B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70J19B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70J19B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70J19B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70J19B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70J19B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70J19B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70J19B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70J19B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70J19B Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70J19B Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70J19B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70J19B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 SAME70J19B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70J19B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70J19B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70J19B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70J19B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70J19B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70J19B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70J19B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70J19B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70J19B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70J19B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70J19B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70J19B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70J19B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70J19B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70J19B Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70J19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70J19B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70J19B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70J19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70J19B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70J19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70J19B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN_INST_NUM 1 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS_INST_NUM 2 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART_INST_NUM 3 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART_INST_NUM 2 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19B*/ +/* ************************************************************************** */ +#include "pio/same70j19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 1024) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00040000) /* 256kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J19B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J19B definitions */ + + +#endif /* _SAME70J19B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70j20b.h b/bsp/microchip/same70/bsp/same70b/include/same70j20b.h new file mode 100644 index 0000000000..aa70967c56 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70j20b.h @@ -0,0 +1,853 @@ +/** + * \file + * + * \brief Header file for ATSAME70J20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:41Z */ +#ifndef _SAME70J20B_H_ +#define _SAME70J20B_H_ + +/** \addtogroup SAME70J20B_definitions SAME70J20B definitions + This file defines all structures and symbols for SAME70J20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70J20B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70J20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70J20B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70J20B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70J20B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70J20B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70J20B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70J20B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70J20B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70J20B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70J20B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70J20B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70J20B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70J20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70J20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16 , /**< 16 SAME70J20B Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70J20B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70J20B Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22 , /**< 22 SAME70J20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70J20B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70J20B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70J20B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70J20B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70J20B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70J20B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70J20B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70J20B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70J20B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70J20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70J20B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70J20B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70J20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70J20B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39 , /**< 39 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70J20B Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43 , /**< 43 SAME70J20B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70J20B Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47 , /**< 47 SAME70J20B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70J20B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70J20B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70J20B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70J20B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70J20B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70J20B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70J20B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70J20B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70J20B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70J20B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70J20B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70J20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70J20B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70J20B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70J20B Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70J20B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70J20B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70J20B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70J20B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70J20B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70J20B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70J20B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70J20B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70J20B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70J20B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70J20B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70J20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70J20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 SAME70J20B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 SAME70J20B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70J20B Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 SAME70J20B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70J20B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70J20B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70J20B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70J20B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70J20B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70J20B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70J20B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70J20B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70J20B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70J20B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70J20B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70J20B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70J20B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70J20B Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70J20B Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70J20B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70J20B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 SAME70J20B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70J20B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70J20B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70J20B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70J20B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70J20B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70J20B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70J20B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70J20B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70J20B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70J20B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70J20B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70J20B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70J20B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70J20B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70J20B Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70J20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70J20B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70J20B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70J20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70J20B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70J20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70J20B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70J20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN_INST_NUM 1 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS_INST_NUM 2 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART_INST_NUM 3 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART_INST_NUM 2 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20B*/ +/* ************************************************************************** */ +#include "pio/same70j20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 2048) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J20B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J20B definitions */ + + +#endif /* _SAME70J20B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70j21b.h b/bsp/microchip/same70/bsp/same70b/include/same70j21b.h new file mode 100644 index 0000000000..e0f7a0ded4 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70j21b.h @@ -0,0 +1,853 @@ +/** + * \file + * + * \brief Header file for ATSAME70J21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:46Z */ +#ifndef _SAME70J21B_H_ +#define _SAME70J21B_H_ + +/** \addtogroup SAME70J21B_definitions SAME70J21B definitions + This file defines all structures and symbols for SAME70J21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70J21B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70J21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70J21B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70J21B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70J21B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70J21B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70J21B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70J21B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70J21B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70J21B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70J21B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70J21B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70J21B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70J21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70J21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16 , /**< 16 SAME70J21B Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70J21B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70J21B Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22 , /**< 22 SAME70J21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70J21B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70J21B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70J21B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70J21B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70J21B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70J21B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70J21B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70J21B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70J21B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70J21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70J21B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70J21B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70J21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70J21B Controller Area Network (MCAN0) */ + GMAC_IRQn = 39 , /**< 39 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70J21B Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43 , /**< 43 SAME70J21B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70J21B Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47 , /**< 47 SAME70J21B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70J21B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70J21B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70J21B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70J21B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70J21B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70J21B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70J21B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70J21B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70J21B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70J21B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70J21B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70J21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70J21B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70J21B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70J21B Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70J21B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70J21B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70J21B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70J21B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70J21B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70J21B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70J21B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70J21B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70J21B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70J21B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70J21B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70J21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70J21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 SAME70J21B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 SAME70J21B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70J21B Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 SAME70J21B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70J21B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70J21B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70J21B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70J21B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70J21B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70J21B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70J21B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70J21B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70J21B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70J21B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70J21B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70J21B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70J21B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70J21B Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70J21B Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70J21B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70J21B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 SAME70J21B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70J21B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70J21B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70J21B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70J21B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70J21B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70J21B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70J21B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70J21B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70J21B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70J21B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70J21B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70J21B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70J21B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70J21B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70J21B Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70J21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70J21B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70J21B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70J21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70J21B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70J21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70J21B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70J21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN_INST_NUM 1 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS_INST_NUM 2 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART_INST_NUM 3 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART_INST_NUM 2 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21B*/ +/* ************************************************************************** */ +#include "pio/same70j21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 4096) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J21B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J21B definitions */ + + +#endif /* _SAME70J21B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70n19b.h b/bsp/microchip/same70/bsp/same70b/include/same70n19b.h new file mode 100644 index 0000000000..e8bbafe4e0 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70n19b.h @@ -0,0 +1,915 @@ +/** + * \file + * + * \brief Header file for ATSAME70N19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:48Z */ +#ifndef _SAME70N19B_H_ +#define _SAME70N19B_H_ + +/** \addtogroup SAME70N19B_definitions SAME70N19B definitions + This file defines all structures and symbols for SAME70N19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70N19B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70N19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70N19B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70N19B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70N19B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70N19B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70N19B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70N19B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70N19B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70N19B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70N19B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70N19B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70N19B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70N19B Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18 , /**< 18 SAME70N19B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70N19B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70N19B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70N19B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70N19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70N19B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70N19B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70N19B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70N19B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70N19B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70N19B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70N19B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70N19B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70N19B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70N19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70N19B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70N19B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70N19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70N19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70N19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70N19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70N19B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70N19B Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43 , /**< 43 SAME70N19B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70N19B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70N19B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70N19B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70N19B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70N19B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70N19B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70N19B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70N19B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70N19B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70N19B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70N19B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70N19B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70N19B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70N19B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70N19B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70N19B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70N19B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70N19B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70N19B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70N19B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70N19B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70N19B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70N19B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70N19B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70N19B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70N19B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70N19B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70N19B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70N19B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70N19B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70N19B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70N19B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70N19B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 SAME70N19B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70N19B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70N19B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70N19B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70N19B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70N19B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70N19B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70N19B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70N19B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70N19B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70N19B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70N19B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70N19B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70N19B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70N19B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70N19B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70N19B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70N19B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70N19B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70N19B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70N19B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70N19B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70N19B Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70N19B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70N19B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70N19B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70N19B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70N19B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70N19B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70N19B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70N19B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70N19B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70N19B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70N19B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70N19B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70N19B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70N19B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70N19B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70N19B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70N19B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70N19B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70N19B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70N19B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70N19B Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70N19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70N19B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70N19B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70N19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70N19B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/spi0.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70N19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_COUNT ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70N19B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70N19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC_INST_NUM 1 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI_INST_NUM 1 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19B*/ +/* ************************************************************************** */ +#include "pio/same70n19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 1024) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00040000) /* 256kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N19B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N19B definitions */ + + +#endif /* _SAME70N19B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70n20b.h b/bsp/microchip/same70/bsp/same70b/include/same70n20b.h new file mode 100644 index 0000000000..e6f7e73239 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70n20b.h @@ -0,0 +1,915 @@ +/** + * \file + * + * \brief Header file for ATSAME70N20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:51Z */ +#ifndef _SAME70N20B_H_ +#define _SAME70N20B_H_ + +/** \addtogroup SAME70N20B_definitions SAME70N20B definitions + This file defines all structures and symbols for SAME70N20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70N20B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70N20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70N20B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70N20B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70N20B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70N20B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70N20B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70N20B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70N20B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70N20B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70N20B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70N20B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70N20B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70N20B Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18 , /**< 18 SAME70N20B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70N20B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70N20B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70N20B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70N20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70N20B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70N20B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70N20B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70N20B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70N20B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70N20B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70N20B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70N20B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70N20B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70N20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70N20B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70N20B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70N20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70N20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70N20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70N20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70N20B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70N20B Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43 , /**< 43 SAME70N20B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70N20B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70N20B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70N20B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70N20B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70N20B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70N20B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70N20B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70N20B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70N20B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70N20B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70N20B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70N20B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70N20B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70N20B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70N20B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70N20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70N20B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70N20B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70N20B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70N20B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70N20B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70N20B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70N20B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70N20B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70N20B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70N20B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70N20B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70N20B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70N20B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70N20B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70N20B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70N20B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70N20B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 SAME70N20B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70N20B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70N20B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70N20B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70N20B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70N20B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70N20B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70N20B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70N20B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70N20B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70N20B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70N20B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70N20B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70N20B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70N20B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70N20B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70N20B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70N20B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70N20B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70N20B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70N20B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70N20B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70N20B Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70N20B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70N20B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70N20B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70N20B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70N20B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70N20B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70N20B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70N20B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70N20B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70N20B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70N20B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70N20B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70N20B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70N20B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70N20B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70N20B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70N20B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70N20B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70N20B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70N20B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70N20B Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70N20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70N20B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70N20B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70N20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70N20B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/spi0.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70N20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_COUNT ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70N20B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70N20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC_INST_NUM 1 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI_INST_NUM 1 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20B*/ +/* ************************************************************************** */ +#include "pio/same70n20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 2048) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N20B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N20B definitions */ + + +#endif /* _SAME70N20B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70n21b.h b/bsp/microchip/same70/bsp/same70b/include/same70n21b.h new file mode 100644 index 0000000000..dc26af90bd --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70n21b.h @@ -0,0 +1,915 @@ +/** + * \file + * + * \brief Header file for ATSAME70N21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:53Z */ +#ifndef _SAME70N21B_H_ +#define _SAME70N21B_H_ + +/** \addtogroup SAME70N21B_definitions SAME70N21B definitions + This file defines all structures and symbols for SAME70N21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70N21B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70N21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70N21B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70N21B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70N21B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70N21B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70N21B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70N21B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70N21B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70N21B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70N21B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70N21B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70N21B Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13 , /**< 13 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70N21B Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18 , /**< 18 SAME70N21B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70N21B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70N21B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70N21B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70N21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70N21B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70N21B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70N21B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70N21B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70N21B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70N21B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70N21B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70N21B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70N21B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70N21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70N21B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70N21B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70N21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70N21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70N21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70N21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70N21B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70N21B Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43 , /**< 43 SAME70N21B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70N21B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70N21B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70N21B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70N21B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70N21B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70N21B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70N21B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70N21B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70N21B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70N21B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70N21B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70N21B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70N21B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70N21B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70N21B Floating Point Unit (FPU) */ + RSWDT_IRQn = 63 , /**< 63 SAME70N21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70N21B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70N21B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70N21B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70N21B Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70N21B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70N21B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70N21B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70N21B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70N21B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70N21B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70N21B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70N21B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70N21B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70N21B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70N21B Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70N21B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70N21B Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 SAME70N21B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70N21B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70N21B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70N21B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70N21B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70N21B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70N21B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70N21B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70N21B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70N21B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70N21B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70N21B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70N21B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70N21B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70N21B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70N21B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70N21B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70N21B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70N21B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70N21B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70N21B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70N21B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70N21B Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 SAME70N21B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70N21B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70N21B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70N21B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70N21B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70N21B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70N21B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70N21B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70N21B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70N21B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70N21B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70N21B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70N21B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70N21B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70N21B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70N21B Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 SAME70N21B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70N21B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70N21B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70N21B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70N21B Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70N21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70N21B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70N21B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70N21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70N21B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/piod.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/spi0.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70N21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_COUNT ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70N21B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70N21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC_INST_NUM 1 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI_INST_NUM 1 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21B*/ +/* ************************************************************************** */ +#include "pio/same70n21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 4096) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N21B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N21B definitions */ + + +#endif /* _SAME70N21B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70q19b.h b/bsp/microchip/same70/bsp/same70b/include/same70q19b.h new file mode 100644 index 0000000000..4c3aa05433 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70q19b.h @@ -0,0 +1,967 @@ +/** + * \file + * + * \brief Header file for ATSAME70Q19B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:55Z */ +#ifndef _SAME70Q19B_H_ +#define _SAME70Q19B_H_ + +/** \addtogroup SAME70Q19B_definitions SAME70Q19B definitions + This file defines all structures and symbols for SAME70Q19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70Q19B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70Q19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70Q19B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70Q19B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70Q19B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70Q19B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70Q19B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70Q19B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70Q19B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70Q19B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70Q19B Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12 , /**< 12 SAME70Q19B Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13 , /**< 13 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70Q19B Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17 , /**< 17 SAME70Q19B Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18 , /**< 18 SAME70Q19B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70Q19B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70Q19B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70Q19B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70Q19B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70Q19B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70Q19B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70Q19B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70Q19B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70Q19B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70Q19B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70Q19B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70Q19B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70Q19B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70Q19B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70Q19B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70Q19B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70Q19B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70Q19B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70Q19B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70Q19B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70Q19B Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42 , /**< 42 SAME70Q19B Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43 , /**< 43 SAME70Q19B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70Q19B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70Q19B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70Q19B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70Q19B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70Q19B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70Q19B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70Q19B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70Q19B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70Q19B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70Q19B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70Q19B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70Q19B Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62 , /**< 62 SAME70Q19B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63 , /**< 63 SAME70Q19B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70Q19B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70Q19B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70Q19B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70Q19B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70 , /**< 70 SAME70Q19B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70Q19B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70Q19B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70Q19B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70Q19B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70Q19B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70Q19B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70Q19B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70Q19B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70Q19B Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 SAME70Q19B Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70Q19B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70Q19B Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 SAME70Q19B Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 SAME70Q19B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70Q19B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70Q19B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70Q19B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70Q19B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70Q19B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70Q19B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70Q19B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70Q19B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70Q19B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70Q19B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70Q19B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70Q19B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70Q19B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70Q19B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70Q19B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70Q19B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70Q19B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70Q19B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70Q19B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70Q19B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70Q19B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70Q19B Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 SAME70Q19B Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 SAME70Q19B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70Q19B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70Q19B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70Q19B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70Q19B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70Q19B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70Q19B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70Q19B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70Q19B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70Q19B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70Q19B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70Q19B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70Q19B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70Q19B Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SAME70Q19B SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 SAME70Q19B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70Q19B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70Q19B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70Q19B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70Q19B Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 SAME70Q19B Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70Q19B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70Q19B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70Q19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70Q19B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/sdramc.h" +#include "instance/smc.h" +#include "instance/spi0.h" +#include "instance/spi1.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70Q19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_COUNT ( 71) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70Q19B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000) /**< \brief (I2SC1 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600) /**< \brief (PIOE ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SDRAMC (0x40084000) /**< \brief (SDRAMC ) Base Address */ +#define SMC (0x40080000) /**< \brief (SMC ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SPI1 (0x40058000) /**< \brief (SPI1 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define I2SC_INST_NUM 2 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0, I2SC1 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define PIO_INST_NUM 5 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOC, PIOD, PIOE } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC ) Base Address */ +#define SDRAMC_INST_NUM 1 /**< \brief (SDRAMC ) Number of instances */ +#define SDRAMC_INSTS { SDRAMC } /**< \brief (SDRAMC ) Instances List */ + +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SMC_INST_NUM 1 /**< \brief (SMC ) Number of instances */ +#define SMC_INSTS { SMC } /**< \brief (SMC ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define SPI_INST_NUM 2 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0, SPI1 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19B*/ +/* ************************************************************************** */ +#include "pio/same70q19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 1024) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00040000) /* 256kB Memory segment type: ram */ +#define EBI_CS0_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _U_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _U_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _U_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _U_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _U_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _U_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q19B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q19B definitions */ + + +#endif /* _SAME70Q19B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70q20b.h b/bsp/microchip/same70/bsp/same70b/include/same70q20b.h new file mode 100644 index 0000000000..fa743602c3 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70q20b.h @@ -0,0 +1,967 @@ +/** + * \file + * + * \brief Header file for ATSAME70Q20B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:57Z */ +#ifndef _SAME70Q20B_H_ +#define _SAME70Q20B_H_ + +/** \addtogroup SAME70Q20B_definitions SAME70Q20B definitions + This file defines all structures and symbols for SAME70Q20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70Q20B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70Q20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70Q20B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70Q20B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70Q20B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70Q20B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70Q20B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70Q20B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70Q20B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70Q20B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70Q20B Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12 , /**< 12 SAME70Q20B Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13 , /**< 13 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70Q20B Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17 , /**< 17 SAME70Q20B Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18 , /**< 18 SAME70Q20B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70Q20B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70Q20B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70Q20B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70Q20B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70Q20B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70Q20B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70Q20B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70Q20B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70Q20B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70Q20B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70Q20B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70Q20B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70Q20B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70Q20B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70Q20B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70Q20B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70Q20B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70Q20B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70Q20B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70Q20B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70Q20B Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42 , /**< 42 SAME70Q20B Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43 , /**< 43 SAME70Q20B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70Q20B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70Q20B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70Q20B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70Q20B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70Q20B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70Q20B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70Q20B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70Q20B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70Q20B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70Q20B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70Q20B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70Q20B Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62 , /**< 62 SAME70Q20B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63 , /**< 63 SAME70Q20B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70Q20B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70Q20B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70Q20B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70Q20B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70 , /**< 70 SAME70Q20B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70Q20B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70Q20B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70Q20B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70Q20B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70Q20B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70Q20B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70Q20B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70Q20B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70Q20B Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 SAME70Q20B Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70Q20B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70Q20B Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 SAME70Q20B Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 SAME70Q20B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70Q20B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70Q20B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70Q20B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70Q20B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70Q20B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70Q20B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70Q20B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70Q20B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70Q20B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70Q20B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70Q20B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70Q20B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70Q20B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70Q20B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70Q20B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70Q20B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70Q20B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70Q20B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70Q20B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70Q20B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70Q20B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70Q20B Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 SAME70Q20B Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 SAME70Q20B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70Q20B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70Q20B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70Q20B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70Q20B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70Q20B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70Q20B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70Q20B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70Q20B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70Q20B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70Q20B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70Q20B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70Q20B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70Q20B Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SAME70Q20B SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 SAME70Q20B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70Q20B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70Q20B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70Q20B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70Q20B Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 SAME70Q20B Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70Q20B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70Q20B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70Q20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70Q20B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/sdramc.h" +#include "instance/smc.h" +#include "instance/spi0.h" +#include "instance/spi1.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70Q20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_COUNT ( 71) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70Q20B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000) /**< \brief (I2SC1 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600) /**< \brief (PIOE ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SDRAMC (0x40084000) /**< \brief (SDRAMC ) Base Address */ +#define SMC (0x40080000) /**< \brief (SMC ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SPI1 (0x40058000) /**< \brief (SPI1 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define I2SC_INST_NUM 2 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0, I2SC1 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define PIO_INST_NUM 5 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOC, PIOD, PIOE } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC ) Base Address */ +#define SDRAMC_INST_NUM 1 /**< \brief (SDRAMC ) Number of instances */ +#define SDRAMC_INSTS { SDRAMC } /**< \brief (SDRAMC ) Instances List */ + +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SMC_INST_NUM 1 /**< \brief (SMC ) Number of instances */ +#define SMC_INSTS { SMC } /**< \brief (SMC ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define SPI_INST_NUM 2 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0, SPI1 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20B*/ +/* ************************************************************************** */ +#include "pio/same70q20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 2048) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _U_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _U_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _U_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _U_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _U_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _U_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q20B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q20B definitions */ + + +#endif /* _SAME70Q20B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/same70q21b.h b/bsp/microchip/same70/bsp/same70b/include/same70q21b.h new file mode 100644 index 0000000000..cd35069379 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/same70q21b.h @@ -0,0 +1,967 @@ +/** + * \file + * + * \brief Header file for ATSAME70Q21B + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/* file generated from device description version 2019-01-18T21:19:59Z */ +#ifndef _SAME70Q21B_H_ +#define _SAME70Q21B_H_ + +/** \addtogroup SAME70Q21B_definitions SAME70Q21B definitions + This file defines all structures and symbols for SAME70Q21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/** \defgroup Atmel_glob_defs Atmel Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + + \remark + CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint_t' respective types. + Default the header files will follow the CMSIS core syntax. + * @{ + */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#include + +/* IO definitions (access restrictions to peripheral registers) */ +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ + +#define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else /* Assembler */ +#define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) + +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/** \addtogroup SAME70Q21B_cmsis CMSIS Definitions + * @{ + */ +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ + PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ + SysTick_IRQn = -1 , /**< 15 System Tick Timer */ +/****** SAME70Q21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0 , /**< 0 SAME70Q21B Supply Controller (SUPC) */ + RSTC_IRQn = 1 , /**< 1 SAME70Q21B Reset Controller (RSTC) */ + RTC_IRQn = 2 , /**< 2 SAME70Q21B Real-time Clock (RTC) */ + RTT_IRQn = 3 , /**< 3 SAME70Q21B Real-time Timer (RTT) */ + WDT_IRQn = 4 , /**< 4 SAME70Q21B Watchdog Timer (WDT) */ + PMC_IRQn = 5 , /**< 5 SAME70Q21B Power Management Controller (PMC) */ + EFC_IRQn = 6 , /**< 6 SAME70Q21B Embedded Flash Controller (EFC) */ + UART0_IRQn = 7 , /**< 7 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8 , /**< 8 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10 , /**< 10 SAME70Q21B Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11 , /**< 11 SAME70Q21B Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12 , /**< 12 SAME70Q21B Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13 , /**< 13 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14 , /**< 14 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15 , /**< 15 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16 , /**< 16 SAME70Q21B Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17 , /**< 17 SAME70Q21B Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18 , /**< 18 SAME70Q21B High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19 , /**< 19 SAME70Q21B Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20 , /**< 20 SAME70Q21B Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21 , /**< 21 SAME70Q21B Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22 , /**< 22 SAME70Q21B Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23 , /**< 23 SAME70Q21B Timer Counter (TC0) */ + TC1_IRQn = 24 , /**< 24 SAME70Q21B Timer Counter (TC0) */ + TC2_IRQn = 25 , /**< 25 SAME70Q21B Timer Counter (TC0) */ + TC3_IRQn = 26 , /**< 26 SAME70Q21B Timer Counter (TC1) */ + TC4_IRQn = 27 , /**< 27 SAME70Q21B Timer Counter (TC1) */ + TC5_IRQn = 28 , /**< 28 SAME70Q21B Timer Counter (TC1) */ + AFEC0_IRQn = 29 , /**< 29 SAME70Q21B Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30 , /**< 30 SAME70Q21B Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31 , /**< 31 SAME70Q21B Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32 , /**< 32 SAME70Q21B Integrity Check Monitor (ICM) */ + ACC_IRQn = 33 , /**< 33 SAME70Q21B Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34 , /**< 34 SAME70Q21B USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35 , /**< 35 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36 , /**< 36 SAME70Q21B Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37 , /**< 37 SAME70Q21B Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38 , /**< 38 SAME70Q21B Controller Area Network (MCAN1) */ + GMAC_IRQn = 39 , /**< 39 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40 , /**< 40 SAME70Q21B Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41 , /**< 41 SAME70Q21B Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42 , /**< 42 SAME70Q21B Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43 , /**< 43 SAME70Q21B Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44 , /**< 44 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45 , /**< 45 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46 , /**< 46 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47 , /**< 47 SAME70Q21B Timer Counter (TC2) */ + TC7_IRQn = 48 , /**< 48 SAME70Q21B Timer Counter (TC2) */ + TC8_IRQn = 49 , /**< 49 SAME70Q21B Timer Counter (TC2) */ + TC9_IRQn = 50 , /**< 50 SAME70Q21B Timer Counter (TC3) */ + TC10_IRQn = 51 , /**< 51 SAME70Q21B Timer Counter (TC3) */ + TC11_IRQn = 52 , /**< 52 SAME70Q21B Timer Counter (TC3) */ + AES_IRQn = 56 , /**< 56 SAME70Q21B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57 , /**< 57 SAME70Q21B True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58 , /**< 58 SAME70Q21B Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59 , /**< 59 SAME70Q21B Image Sensor Interface (ISI) */ + PWM1_IRQn = 60 , /**< 60 SAME70Q21B Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61 , /**< 61 SAME70Q21B Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62 , /**< 62 SAME70Q21B SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63 , /**< 63 SAME70Q21B Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64 , /**< 64 SAME70Q21B System Control Block (SCB) */ + CCF_IRQn = 65 , /**< 65 SAME70Q21B System Control Block (SCB) */ + GMAC_Q1_IRQn = 66 , /**< 66 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67 , /**< 67 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68 , /**< 68 SAME70Q21B Floating Point Unit (FPU) */ + I2SC0_IRQn = 69 , /**< 69 SAME70Q21B Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70 , /**< 70 SAME70Q21B Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71 , /**< 71 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72 , /**< 72 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73 , /**< 73 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + + PERIPH_COUNT_IRQn = 74 /**< Number of peripheral IDs */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* Cortex-M handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 SAME70Q21B Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 SAME70Q21B Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 SAME70Q21B Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 SAME70Q21B Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 SAME70Q21B Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 SAME70Q21B Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 SAME70Q21B Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 SAME70Q21B Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 SAME70Q21B Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 SAME70Q21B Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 SAME70Q21B Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 SAME70Q21B Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 SAME70Q21B Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 SAME70Q21B High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 SAME70Q21B Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 SAME70Q21B Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 SAME70Q21B Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 SAME70Q21B Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 SAME70Q21B Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 SAME70Q21B Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 SAME70Q21B Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 SAME70Q21B Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 SAME70Q21B Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 SAME70Q21B Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 SAME70Q21B Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 SAME70Q21B Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 SAME70Q21B Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 SAME70Q21B Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 SAME70Q21B Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 SAME70Q21B USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 SAME70Q21B Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 SAME70Q21B Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 SAME70Q21B Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 SAME70Q21B Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 SAME70Q21B Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 SAME70Q21B Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 SAME70Q21B Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 SAME70Q21B Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 SAME70Q21B Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 SAME70Q21B Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 SAME70Q21B Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 SAME70Q21B Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 SAME70Q21B Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 SAME70Q21B Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 SAME70Q21B Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 SAME70Q21B Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 SAME70Q21B True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 SAME70Q21B Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 SAME70Q21B Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 SAME70Q21B Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 SAME70Q21B Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SAME70Q21B SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 SAME70Q21B Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 SAME70Q21B System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 SAME70Q21B System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 SAME70Q21B Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 SAME70Q21B Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 SAME70Q21B Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 SAME70Q21B Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS + +/* CORTEX-M7 core handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void CCF_Handler ( void ); +void CCW_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void FPU_Handler ( void ); +void GMAC_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +void HSMCI_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void IXC_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ + + +/* Defines for Deprecated Interrupt and Exceptions handler names */ +#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ +#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ +#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ +#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +/* + * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __LITTLE_ENDIAN 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 +#define __DEVICE_IS_SAM 1 + +/* + * \brief CMSIS includes + */ +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same70.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/** @} end of SAME70Q21B_cmsis CMSIS Definitions */ + +/** \defgroup SAME70Q21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \defgroup SAME70Q21B_reg Registers Access Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#include "instance/acc.h" +#include "instance/aes.h" +#include "instance/afec0.h" +#include "instance/afec1.h" +#include "instance/chipid.h" +#include "instance/dacc.h" +#include "instance/efc.h" +#include "instance/gmac.h" +#include "instance/gpbr.h" +#include "instance/hsmci.h" +#include "instance/i2sc0.h" +#include "instance/i2sc1.h" +#include "instance/icm.h" +#include "instance/isi.h" +#include "instance/matrix.h" +#include "instance/mcan0.h" +#include "instance/mcan1.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/piod.h" +#include "instance/pioe.h" +#include "instance/pmc.h" +#include "instance/pwm0.h" +#include "instance/pwm1.h" +#include "instance/qspi.h" +#include "instance/rstc.h" +#include "instance/rswdt.h" +#include "instance/rtc.h" +#include "instance/rtt.h" +#include "instance/sdramc.h" +#include "instance/smc.h" +#include "instance/spi0.h" +#include "instance/spi1.h" +#include "instance/ssc.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/trng.h" +#include "instance/twihs0.h" +#include "instance/twihs1.h" +#include "instance/twihs2.h" +#include "instance/uart0.h" +#include "instance/uart1.h" +#include "instance/uart2.h" +#include "instance/uart3.h" +#include "instance/uart4.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/usbhs.h" +#include "instance/utmi.h" +#include "instance/wdt.h" +#include "instance/xdmac.h" +/** @} end of Registers Access Definitions */ + +/** \addtogroup SAME70Q21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_COUNT ( 71) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup legacy_SAME70Q21B_id Legacy Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 +#define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 +#define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 +#define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 +#define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 +#define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 +#define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 +#define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 +#define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 +#define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 +#define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 +#define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 +/** @} end of Legacy Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC (0x40044000) /**< \brief (ACC ) Base Address */ +#define AES (0x4006C000) /**< \brief (AES ) Base Address */ +#define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ +#define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ +#define DACC (0x40040000) /**< \brief (DACC ) Base Address */ +#define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ +#define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ +#define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ +#define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ +#define I2SC0 (0x4008C000) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 (0x40090000) /**< \brief (I2SC1 ) Base Address */ +#define ICM (0x40048000) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ +#define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ +#define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ +#define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600) /**< \brief (PIOE ) Base Address */ +#define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ +#define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ +#define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ +#define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ +#define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ +#define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ +#define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ +#define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ +#define SDRAMC (0x40084000) /**< \brief (SDRAMC ) Base Address */ +#define SMC (0x40080000) /**< \brief (SMC ) Base Address */ +#define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ +#define SPI1 (0x40058000) /**< \brief (SPI1 ) Base Address */ +#define SSC (0x40004000) /**< \brief (SSC ) Base Address */ +#define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ +#define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ +#define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ +#define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ +#define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ +#define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ +#define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ +#define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ +#define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ +#define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ +#define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ +#define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ +#define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ +#define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ +#define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ + +#else /* For C/C++ compiler */ + +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ +#define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ + +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES ) Instances List */ + +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ +#define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ + +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ +#define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ + +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ +#define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ + +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ +#define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ + +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ + +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ +#define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ + +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ +#define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ + +#define I2SC0 ((I2sc *)0x4008C000U) /**< \brief (I2SC0 ) Base Address */ +#define I2SC1 ((I2sc *)0x40090000U) /**< \brief (I2SC1 ) Base Address */ +#define I2SC_INST_NUM 2 /**< \brief (I2SC ) Number of instances */ +#define I2SC_INSTS { I2SC0, I2SC1 } /**< \brief (I2SC ) Instances List */ + +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ + +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ +#define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ + +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ +#define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ +#define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ + +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ +#define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ + +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define PIO_INST_NUM 5 /**< \brief (PIO ) Number of instances */ +#define PIO_INSTS { PIOA, PIOB, PIOC, PIOD, PIOE } /**< \brief (PIO ) Instances List */ + +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ +#define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ + +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ +#define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ + +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ + +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ + +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ +#define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ + +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ + +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ +#define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ + +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC ) Base Address */ +#define SDRAMC_INST_NUM 1 /**< \brief (SDRAMC ) Number of instances */ +#define SDRAMC_INSTS { SDRAMC } /**< \brief (SDRAMC ) Instances List */ + +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SMC_INST_NUM 1 /**< \brief (SMC ) Number of instances */ +#define SMC_INSTS { SMC } /**< \brief (SMC ) Instances List */ + +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define SPI_INST_NUM 2 /**< \brief (SPI ) Number of instances */ +#define SPI_INSTS { SPI0, SPI1 } /**< \brief (SPI ) Instances List */ + +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ +#define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ + +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ + +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ + +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ + +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ +#define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ +#define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ + +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ +#define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ + +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ +#define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ + +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ +#define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ + +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ +#define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ + +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ + +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ +#define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ + +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21B*/ +/* ************************************************************************** */ +#include "pio/same70q21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21B*/ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _U_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _U_( 512) +#define IFLASH_NB_OF_PAGES _U_( 4096) + +#define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _U_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _U_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _U_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _U_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _U_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _U_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _U_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q21B */ +/* ************************************************************************** */ +#define JTAGID _UL_(0X05B3D03F) +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q21B definitions */ + + +#endif /* _SAME70Q21B_H_ */ diff --git a/bsp/microchip/same70/bsp/same70b/include/system_same70.h b/bsp/microchip/same70/bsp/same70b/include/system_same70.h new file mode 100644 index 0000000000..55aba26021 --- /dev/null +++ b/bsp/microchip/same70/bsp/same70b/include/system_same70.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon device startup + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SYSTEM_SAME70_H_INCLUDED_ +#define _SYSTEM_SAME70_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAME70_H_INCLUDED */ diff --git a/bsp/microchip/same70/rtconfig.h b/bsp/microchip/same70/rtconfig.h new file mode 100644 index 0000000000..f16d65036b --- /dev/null +++ b/bsp/microchip/same70/rtconfig.h @@ -0,0 +1,176 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40100 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* POSIX extension functions */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +#define SOC_SAME70Q21 + +/* Onboard Peripheral Drivers */ + +#define SAME70_CAN0 +#define SAME70_ADC0 + +#endif diff --git a/bsp/microchip/same70/rtconfig.py b/bsp/microchip/same70/rtconfig.py new file mode 100644 index 0000000000..8fbfc8dfb4 --- /dev/null +++ b/bsp/microchip/same70/rtconfig.py @@ -0,0 +1,69 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +DEVICE_SERIES = 'SAME70' +#DEVICE_SERIES = 'SAMS70' +#DEVICE_SERIES = 'SAMV70' +#DEVICE_SERIES = 'SAMV71' +DEVICE_TYPE = '__SAME70Q21B__' +#DEVICE_TYPE = '__SAMS70Q21B__' +DEVICE_PART = 'same70' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:/workspace/tools/embedcpp/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -mlong-calls' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T bsp/same70b/gcc/gcc/same70q21b_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +